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DW−20
TLV5639C
TLV5639I
PW−20
SLAS189C – MARCH 1999 – REVISED JANUARY 2004
2.7-V TO 5.5-V LOW-POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS
WITH INTERNAL REFERENCE AND POWER DOWN
FEATURES
•
•
•
•
•
•
•
DW OR PW PACKAGE
(TOP VIEW)
12-Bit Voltage Output DAC
Programmable Internal Reference
Programmable Settling Time vs Power
Consumption
– 1 µs in Fast Mode
– 3.5 µs in Slow Mode
Compatible With TMS320
Differential Nonlinearity . . . <0.5 LSB Typ
Voltage Output Range . . . 2x the Reference
Voltage
Monotonic Over Temperature
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
D1
D0
CS
WE
LDAC
REG
AGND
OUT
REF
VDD
APPLICATIONS
•
•
•
•
•
Digital Servo Control Loops
Digital Offset and Gain Adjustment
Industrial Process Control
Machine and Motion Control Devices
Mass Storage Devices
DESCRIPTION
The TLV5639 is a 12-bit voltage output digital-to-analog converter (DAC) with a microprocessor compatible
parallel interface. It is programmed with a 16-bit data word containing 4 control and 12 data bits. Developed for a
wide range of supply voltages, the TLV5639 can be operated from 2.7 V to 5.5 V.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the
designer to optimize speed versus power dissipation. Because of its ability to source up to 1 mA, the internal
reference can also be used as a system reference. With its on-chip programmable precision voltage reference,
the TLV5639 simplifies overall system design. The settling time and the reference voltage can be chosen by the
control bits within the 16-bit data word.
Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is
available in 20-pin SOIC and TSSOP packages in standard commercial and industrial temperature ranges.
AVAILABLE OPTIONS
TA
PACKAGE
SOIC (DW)
TSSOP (PW)
0°C to 70°C
TLV5639CDW
TLV5639CPW
-40°C to 85°C
TLV5639IDW
TLV5639IPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2004, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
REF
AGND
VDD
PGA With
Output Enable
Voltage
Bandgap
D(0–11)
Powerdown
and Speed
Control
Power-On
Reset
4
REG
Interface
Control
CS
12
WE
x2
2
4-Bit
Control
Latch
12
12-Bit
DAC
Holding
Latch
12-Bit
DAC
Register
12
LDAC
Terminal Functions
TERMINAL
I/O/P
DESCRIPTION
NAME
NO.
AGND
14
P
Ground
CS
18
I
Chip select. Digital input active low, used to enable/disable inputs
1-10, 19,
20
I
Data input
D0-D11
LDAC
16
I
Load DAC. Digital input active low, used to load DAC output
OUT
13
O
DAC analog voltage output
REG
15
I
Register select. Digital input, used to access control register
REF
12
I/O
VDD
11
P
Positive power supply
WE
17
I
Write enable. Digital input active low, used to latch data
2
Analog reference voltage input/output
OUT
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TLV5639I
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SLAS189C – MARCH 1999 – REVISED JANUARY 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage (VDD to AGND)
7V
Reference input voltage range
- 0.3 V to VDD + 0.3 V
Digital input voltage range
Operating free-air temperature range, TA
- 0.3 V to VDD + 0.3 V
TLV5639C
0°C to 70°C
TLV5639I
-40°C to 85°C
Storage temperature range, Tstg
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VDD
MIN
NOM
MAX
VDD = 5 V
4.5
5
5.5
V
VDD = 3 V
2.7
3
3.3
V
2
V
Power on threshold voltage, POR
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
Reference voltage, Vref to REF terminal
Reference voltage, Vref to REF terminal
0.55
VDD = 2.7 V
2
VDD = 5.5 V
2.4
0.6
VDD = 5.5 V
1
VDD = 5 V
(1)
AGND
2.048
VDD-1.5
VDD = 3 V
(1)
AGND
1.024
VDD-1.5
2
Load capacitance, CL
Operating free-air temperature, TA
(1)
V
VDD = 2.7 V
Load resistance, RL
UNIT
V
V
V
kΩ
100
TLV5639C
0
70
TLV5639I
40
85
pF
°C
Due to the x2 output buffer, a reference input voltage ≥ VDD/2 causes clipping of the transfer function. The output buffer of the internal
reference must be disabled, if an external reference is used.
3
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SLAS189C – MARCH 1999 – REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
POWER SUPPLY
PARAMETER
TEST CONDITIONS
VDD= 5 V
IDD
Power supply current
No load,
All inputs = AGND or VDD,
DAC latch = 0x800
VDD = 3 V
MIN
(1)
(2)
Power supply rejection ratio
UNIT
REF
on
Fast
2.3
2.8
mA
Slow
1.3
1.6
mA
REF
off
Fast
1.9
2.4
mA
Slow
0.9
1.2
mA
REF
on
Fast
2.1
2.6
mA
Slow
1.2
1.5
mA
REF
off
Fast
1.8
2.3
mA
0.9
1.1
mA
0.01
1
µA
Slow
Power down supply current
PSRR
TYP MAX
Zero scale, External reference (1)
60
Full scale, External reference (2)
60
dB
Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) - EZS(VDDmin))/VDDmax]
Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) - EG(VDDmin))/VDDmax]
STATIC DAC SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
12
bits
INL
Integral nonlinearity, end point adjusted
RL = 10 kΩ, CL = 100 pF, See note
(1)
±1.2
±3
LSB
DNL
Differential nonlinearity
RL = 10 kΩ, CL = 100 pF, See note
(2)
±0.3
±0.5
LSB
See note
(3)
EZSTC Zero-scale-error temperature coefficient
See note
(4)
EG
Gain error
See note
(5)
EGTC
Gain error temperature coefficient
See note
(6)
EZS
(1)
(2)
(3)
(4)
(5)
(6)
Zero-scale error (offset error at zero scale)
±12
20
LSB
ppm/°C
±0.3
20
% full
scale V
ppm/°C
The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from
the line between zero and full scale excluding the effects of zero code and full-scale errors (see text).
The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB
amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)
as a change in the digital input code.
Zero-scale error is the deviation from zero voltage output when the digital input code is zero (see text).
Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/2Vref× 106/(Tmax - Tmin).
Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 k excluding the effects of the zero-error.
Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/2Vref× 106/(Tmax - Tmin).
OUTPUT SPECIFICATIONS
PARAMETER
VO
Output voltage
Output load regulation accuracy
4
TEST CONDITIONS
RL = 10 kΩ
VO= 4.096 V, 2.048 V,
MIN
TYP
MAX
VDD-0.4
RL = 2 kΩ
±0.29
UNIT
V
% full
scale V
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SLAS189C – MARCH 1999 – REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
REFERENCE PIN CONFIGURED AS OUTPUT (REF)
PARAMETER
TEST CONDITIONS
Vref(OUTL)
Low reference voltage
Vref(OUTH)
High reference voltage
Iref(source)
Output source current
Iref(sink)
Output sink current
PSRR
Power supply rejection ratio
VDD > 4.75 V
MIN
TYP
MAX
UNIT
1.003
1.024
1.045
V
2.027
2.048
2.069
1
1
V
mA
mA
48
dB
REFERENCE PIN CONFIGURED AS INPUT (REF)
PARAMETER
VI
Input voltage
RI
Input resistance
CI
Input capacitance
TEST CONDITIONS
MIN
Reference input bandwidth
REF = 0.2 Vpp + 1.024 V dc
10 kHz
Harmonic distortion, reference
input
REF = 1 Vpp + 2.048 V dc,
VDD = 5 V
50 kHz
100 kHz
Reference feedthrough
(1)
TYP
MAX
0
REF = 1 Vpp at 1 kHz + 1.024 V dc, See
VDD- 1.5
UNIT
V
10
MΩ
5
pF
Fast
900
Slow
500
Fast
87
Slow
77
Fast
74
Slow
61
Fast
66
dB
80
dB
(1)
kHz
dB
dB
Reference feedthrough is measured at the DAC output with an input code = 0x000.
DIGITAL INPUTS
PARAMETER
TEST CONDITIONS
IIH
High-level digital input current
VI = VDD
IIL
Low-level digital input current
VI = 0 V
Ci
Input capacitance
MIN
TYP
MAX
1
1
UNIT
µA
µA
8
pF
5
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SLAS189C – MARCH 1999 – REVISED JANUARY 2004
OPERATING CHARACTERISTICS
over recommended operating free-air temperature range, Vref = 2.048 V, and Vref = 1.024 V, (unless otherwise noted)
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
ts(FS)
Output settling time, full
scale
RL = 10 kΩ, CL = 100 pF,
see note (1)
Fast
1
3
Slow
3.5
7
ts(CC)
Output settling time, code
to code
RL = 10 kΩ, CL = 100 pF,
see note (2)
Fast
0.5
1.5
Slow
1
2
SR
Slew rate
RL = 10 kΩ, CL = 100 pF,
see note (3)
Fast
6
10
Slow
1.2
1.7
Glitch energy
DIN = 0 to 1, fCLK = 100 kHz, CS = VDD
SNR
Signal-to-noise ratio
SINAD
Signal-to-noise + distortion
THD
Total harmonic distortion
SFDR
Spurious free dynamic
range
(1)
(2)
(3)
fs = 480 kSPS,
fB = 20 kHz,
CL = 100 pF
fout = 1 kHz,
RL = 10 kΩ,
78
61
67
µs
nV-S
69
63
µs
V/µs
5
73
UNIT
62
dB
74
Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of
0x020 to 0xFDF or 0xFDF to 0x020.
Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of
one count.
Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
DIGITAL INPUT TIMING REQUIREMENTS
MIN
NOM
MAX
UNIT
tsu(CS-WE)
Setup time, CS low before negative WE edge
15
ns
tsu(D)
Setup time, data ready before positive WE edge
10
ns
tsu(R)
Setup time, REG ready before positive WE edge
20
ns
th(DR)
Hold time, data and REG held valid after positive WE edge
5
ns
tsu(WE-LD)
Setup time, positive WE edge before LDAC low
5
ns
twH(WE)
Pulse duration, WE high
20
ns
tw(LD)
Pulse duration, LDAC low
23
ns
6
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SLAS189C – MARCH 1999 – REVISED JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
D(0–7)
X
REG
X
Data
X
Reg
X
tsu(D)
tsu(R)
CS
th(DR)
twH(WE)
tsu(CS-WE)
WE
tsu(WE-LD)
tw(LD)
LDAC
Figure 1. Timing Diagram
7
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SLAS189C – MARCH 1999 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
DNL − Differential Nonlinearity − LSB
DIFFERENTIAL NONLINEARITY ERROR
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
512
1024
1536
2048
2560
3072
3584
4096
3072
3584
4096
Digital Code
Figure 2.
INL − Intergral Nonlinearity − LSB
INTEGRAL NONLINEARITY ERROR
3
2
1
0
−1
−2
−3
0
512
1024
1536
2048
Digital Code
Figure 3.
8
2560
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SLAS189C – MARCH 1999 – REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (continued)
MAXIMUM OUTPUT VOLTAGE
vs
LOAD CURRENT
MAXIMUM OUTPUT VOLTAGE
vs
LOAD CURRENT
2.04
4.08
VDD = 3 V,
Vref = Int. 1 V,
Input Code = 0xFFF
2.0395
2.039
4.079
VO − Output Voltage − V
VO − Output Voltage − V
VDD = 5 V,
Vref = Int. 2 V,
Input Code = 0xFFF
4.0795
Fast Mode, Source
2.0385
Fast Mode, Source
4.0785
2.038
2.0375
4.078
4.0775
2.037
Slow Mode, Source
4.077
Slow Mode, Source
2.0365
4.0765
2.036
4.076
2.0355
4.0755
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
1.5
2
2.5
3
Load Current − mA
Figure 4.
Figure 5.
MINIMUM OUTPUT VOLTAGE
vs
LOAD CURRENT
MINIMUM OUTPUT VOLTAGE
vs
LOAD CURRENT
0.25
0.5
1
4.5
Fast Mode, Sink
0.2
VO − Output Voltage − V
0.2
VO − Output Voltage − V
4
0.25
Fast Mode, Sink
0.15
0.1
Slow Mode, Sink
0.05
0
3.5
Load Current − mA
0.5
1
1.5
2
2.5
3
Load Current − mA
Figure 6.
3.5
4
0.1
Slow Mode, Sink
0.05
VDD = 5 V,
Vref = Int. 2 V,
Input Code = 0x000
0
0.15
4.5
0
VDD = 3 V,
Vref = Int. 1 V,
Input Code = 0x000
0
0.5
1
1.5
2
2.5
3
Load Current − mA
3.5
4
4.5
Figure 7.
9
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TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
THD − Total Harmonic Distortion − dB
−10
THD+N − Total Harmonic Distortion and Noise − dB
0
VDD = 5 V,
REF = 1 V dc + 1 V pp Sinewave,
Output Full Scale
−20
−30
−40
−50
−60
Slow Mode
−70
−80
Fast Mode
−90
−100
100
10000
1000
100000
0
VDD = 5 V,
REF = 1 V dc + 1 V pp Sinewave,
Output Full Scale
−10
−20
−30
−40
−50
−60
Slow Mode
−70
−80
Fast Mode
−90
−100
100
1000
f − Frequency − Hz
Figure 8.
Figure 9.
POWER DOWN SUPPLY CURRENT
vs
TIME
1
0.9
I DD − Supply Current − mA
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
10
20
30
40
50
t − Time − µs
Figure 10.
10
10000
f − Frequency − Hz
60
70
80
90
100000
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APPLICATION INFORMATION
GENERAL FUNCTION
The TLV5639 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel
interface, a speed and power down control logic, a programmable internal reference, a resistor string, and a
rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by:
2 REF CODE [V]
0x1000
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A poweron reset initially puts the internal latches to a defined state (all bits zero).
PARALLEL INTERFACE
The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written
to the DAC holding latch or the control register depends on REG. REG = 0 selects the DAC holding latch,REG =
1 selects the control register. LDAC low updates the DAC with the value in the holding latch. LDAC is an
asynchronous input and can be held low, if a separate update is not necessary. However, to control the DAC
using the load feature, there should be approximately a 5 ns delay after the positive WE edge before driving
LDAC low.
TMS320C2XX, 5X
TMS320C3X
A(0–15)
A(0–15)
TLV5639
TLV5639
REG
REG
IS
Address
Decoder
Address
Decoder
CS
R/W
WE
LDAC
TCLK0
LDAC
WE
CS
>=1
WE
IOSTROBE
D(0–11)
D(0–11)
D(0–15)
D(0–15)
Figure 11.
DATA FORMAT
The TLV5639 writes data either to the DAC holding latch or to the control register, depending on the level of the
REG input.
Data destination:
REG = 0 → DAC holding latch
REG = 1 → control register
11
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APPLICATION INFORMATION (continued)
The following table lists the meaning of the bits within the control register:
(1)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
REF1
REF0
X
PWR
SPD
X (1)
X (1)
X (1)
X (1)
X (1)
X (1)
X (1)
0 (1)
0 (1)
X (1)
0 (1)
0 (1)
Default values
SPD
: Speed control bit
1 = fast mode
0 = slow mode
PWR
: Power control bit
1 = power down
0 = normal operation
REF1 and REF0 determine the reference source and the reference voltage.
REFERENCE BITS
REF1
REF0
REFERENCE
0
0
External
0
1
1.024 V
1
0
2.048 V
1
1
External
If an external reference voltage is applied to the REF pin, external reference must be selected.
LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE END SUPPLIES
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage remains at zero until the input code value produces a sufficient positive output voltage to
overcome the negative offset voltage, resulting in the transfer function shown in Figure 12.
Output
Voltage
0V
Negative
Offset
DAC Code
Figure 12. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is
measured between full scale code and the lowest code that produces a positive output voltage.
12
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TLV5639 INTERFACED to TMS320C203 DSP
HARDWARE INTERFACE
Figure 13 shows an example of the connection between the TLV5639 and the TMS320C203 DSP. The only
other device that is needed in addition to the DSP and the DAC is the 74AC138 address decoding circuit . Using
this configuration, the DAC data is at address 0x0084 and the DAC control word is at address 0x0085 within the
I/O memory space of the TMS320C203.
LDAC is tied low so that the output voltage is updated on the rising WE edge.
TMS320C203
74AC138
A2
A
A3
A4
B
C
Y1
5V
A6
IS
G1
G2A
G2B
TLV5639
CS
A0
D(0–11)
REG
12
WE
D(0–11)
OUT
WE
To Other Devices Requiring
Voltage Reference
RLOAD
LDAC
REF
Figure 13. TLV5639 to TMS320C203 DSP Interface Connection
SOFTWARE
Writing data or control information to the TLV5639 is done using a single command. For example, the line of
code which reads:
out
62h,
dac_ctrl
writes the contents of address 0x0062 to the I/O address equated to dac_ctrl (0x0085, the address where the
DAC control register has been mapped).
The following code shows how to set the DAC up to use the internal reference and operate in FAST mode by a
write to the control register. Timer interrupts are then enabled and repeatedly generated every 205 µs to provide
a timebase for synchronizing the waveform generation. In this example, the waveform is generated by simply
incrementing a counter and outputting the counter value to the DAC data word once every timer interrupt. This
results in a saw waveform.
13
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;
;
;
;
File:
Function:
Processors:
{ 1999 Texas
RAMP.ASM
ramp generation with TLV5639
TMS320C203
Instruments
;---------- I/O and memory mapped regs --------------.include regs.asm
dac_data
.equ
0084h
dac_ctrl
.equ
0085h
;------------- vectors ------------------------------.ps
0h
b
start
b
INT1
b
INT23
b
TIM_ISR
----------Main Program---------.ps
1000h
.entry
start:
ldp
#0
; set data page to 0
; disable interrupts
setc
INTM
; disable maskable interrupts
splk
#0ffffh, IFR
splk
#0004h, IMR
; set up the timer
splk
#0000h, 60h
splk
#0042h, 61h
out
61h, PRD
out
60h, TIM
splk
#0c2fh,
62h
out
62h,
TCR
splk
#0011h, 62h
; set up the DAC
; SPD=1 (FAST mode) and ; REF1=1
out
14
(2.048 V internal ref enable)
TLV5639C
TLV5639I
www.ti.com
SLAS189C – MARCH 1999 – REVISED JANUARY 2004
62h, dac_ctrl
clrc
INTM
; enable interrupts
; loop forever!
next
idle
b
next
---------- Interrupt Service Routines---------INT1:
ret
; do nothing and return
INT23:
ret
; do nothing and return
TIM_ISR:
; timer interrupt handler
add
#1h
; increment accumulator
sacl
60h
out
60h, dac_data ; write to DAC
clrc
intm
; re-enable interrupts
ret
; return from interrupt
.END
15
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TLV5639CDW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
TLV5639CDWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
TLV5639CPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
TLV5639CPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
TLV5639IDW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
TLV5639IDWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
TLV5639IPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
TLV5639IPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
TLV5639IPWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
TLV5639IPWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV5639IPWR
Package Package Pins
Type Drawing
TSSOP
PW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV5639IPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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