TI TMS27C256-15

 SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
D Organization . . . 32 768 by 8 Bits
D Single 5-V Power Supply
D Pin Compatible With Existing 256K MOS
D
D
D
D
D
D
D
D
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
ROMs, PROMs, and EPROMs
All Inputs / Outputs Fully TTL Compatible
Max Access / Min Cycle Time
VCC ± 10%
’27C/ PC256-10
100 ns
’27C/ PC256-12
120 ns
’27C/ PC256-15
150 ns
’27C/ PC256-17
170 ns
’27C/ PC256-20
200 ns
’27C/ PC256-25
250 ns
Power Saving CMOS Technology
Very High-Speed SNAP! Pulse
Programming
3-State Output Buffers
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
Latchup Immunity of 250 mA on All Input
and Output Lines
Low Power Dissipation ( VCC = 5.5 V )
− Active . . . 165 mW Worst Case
− Standby . . . 1.4 mW Worst Case
(CMOS Input Levels)
Temperature Range Options
256K EPROM Available With MIL-STD-883C
Class B High Reliability Processing
(SMJ27C256)
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
FM PACKAGE
( TOP VIEW )
A7
A12
VPP
NU
VCC
A14
A13
D
D
J PACKAGE
( TOP VIEW )
4
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
description
3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
A8
A9
A11
NC
G
A10
E
DQ7
DQ6
14 15 16 17 18 19 20
The TMS27PC256 series are 32 768 by 8-bit
(262 144-bit), one-time programmmable (OTP)
electrically programmable read-only memories
(PROMs).
DQ1
DQ2
GND
NU
DQ3
DQ4
DQ5
The TMS27C256 series are 32 768 by 8-bit
(262 144-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).
PIN NOMENCLATURE
A0 −A14
DQ0 −DQ7
E
G
GND
NC
NU
VCC
VPP
Address Inputs
Inputs (programming) / Outputs
Chip Enable / Powerdown
Output Enable
Ground
No Internal Connection
Make No External Connection
5-V Power Supply
13-V Power Supply †
† Only in program mode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0 !)) '!!&"&#+
POST OFFICE BOX 1443
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1
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The data outputs are 3-state for connecting multiple devices to a common bus. The TMS27C256 and the
TMS27PC256 are pin compatible with 28-pin 256K MOS ROMs, PROMs, and EPROMs.
The TMS27C256 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting-hole rows on 15,2-mm (600-mil) centers. The TMS27PC256 OTP PROM is supplied in a 32-lead
plastic leaded chip-carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).
The TMS27C256 and TMS27PC256 are offered with two choices of temperature ranges of 0°C to 70°C (JL and
FML suffixes) and − 40°C to 85°C (JE and FME suffixes). See Table 1.
All package styles conform to JEDEC standards.
Table 1. Temperature Range Suffixes
EPROM
AND
OTP PROM
SUFFIX FOR OPERATING
FREE-AIR TEMPERATURE RANGES
0°C TO 70°C
− 40°C TO 85°C
JL
JE
FML
FME
TMS27C512-xxx
TMS27PC512-xxx
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming . All programming signals
are TTL level. These devices are programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse
programming algorithm uses a VPP of 13 V and a VCC of 6.5 V for a nominal programming time of four seconds.
For programming outside the system, existing EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.
2
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SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
operation
The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are
TTL level except for VPP during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature mode.
Table 2. Operation Modes
MODE†
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
G
VIL
VIL
VIL
VIH
VIH
X
VIL
VIH
VIH
VIL
VIH
X
VIL
VIL
VPP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VPP
VCC
VPP
VCC
VPP
VCC
VCC
VCC
A9
X
X
X
X
X
X
A0
X
X
X
X
X
X
VH‡
VIL
DQ0 −DQ7
Data Out
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
MFG
DEVICE
97
04
E
VH‡
VIH
CODE
† X can be VIL or VIH.
‡ VH = 12 V ± 0.5 V.
read/ output disable
When the outputs of two or more TMS27C256s or TMS27PC256s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
latchup immunity
Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active ICC supply current can be reduced from 30 mA to 500 µA ( TTL-level inputs) or 250 µA (CMOS-level
inputs) by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance
state.
erasure ( TMS27C256)
Before programming, the TMS27C256 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to
assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV
intensity × exposure time) is 15-W•s / cm2. A typical 12-mW / cm2, filterless UV lamp erases the device in 21
minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal
ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C256, the window
should be covered with an opaque label.
POST OFFICE BOX 1443
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3
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
initializing ( TMS27PC256)
The one-time programmable TMS27PC256 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The 256K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of four seconds. Actual programming
time varies as a function of the programmer used.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when VPP = 13 V, VCC = 6.5 V, G = VIH, and E = VIL. More than one device
can be programmed when the devices are connected in parallel. Locations can be programmed in any order.
When the SNAP! Pulse programming routine is complete, all bits are verified with VCC = VPP = 5 V.
program inhibit
Programming can be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits can be verified with VPP = 13 V when G = VIL and E = VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other addresses must
be held low. The signature code for these devices is 9704. A0 selects the manufacturer’s code 97 (Hex), and
A0 high selects the device code 04, as shown in Table 3.
Table 3. Signature Mode
IDENTIFIER†
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
VIL
VIH
1
0
0
1
0
1
1
1
97
DEVICE CODE
0
0
0
0
0
1
† E = G = VIL, A9 = VH, A1 −A8 = VIL, A10 −A15 = VIL, VPP = VCC, PGM = VIH or VIL.
0
0
04
MANUFACTURER CODE
4
PINS
A0
POST OFFICE BOX 1443
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SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
Start
Address = First Location
Program
Mode
VCC = 6.5 V, VPP = 13 V
Program One Pulse = tw = 100 µs
Increment Address
No
Last
Address?
Yes
Address = First Location
X=0
Program One Pulse = tw = 100 µs
No
Increment
Address
Verify
One Byte
Fail
X=X+1
X = 10?
Interactive
Mode
Pass
No
Last
Address?
Yes
Yes
VCC = VPP = 5 V ±10%
Compare
All Bytes
To Original
Data
Device Failed
Fail
Final
Verification
Pass
Device Passed
Figure 1. SNAP! Pulse Programming Flowchart
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5
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
logic symbol†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
E
G
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
EPROM
32 768 × 8
0
A
0
32 767
A
A
A
A
A
A
A
A
11
12
13
15
16
17
18
19
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
14
20
22
[PWR DWN]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
E
&
EN
G
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
OTP PROM
32 768 × 8
0
A
0
32 767
A
A
A
A
A
A
A
A
11
12
13
15
16
17
18
19
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
14
20
22
[PWR DWN]
&
EN
† These symbols are in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC (see Note 1) : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 7 V
Supply voltage range, VPP : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to VCC + 1 V
A9 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 13.5 V
Output voltage range (see Note 1) : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to VCC + 1 V
Operating free-air temperature range (’27C256-_ _JL, ’27PC256-_ _FML) TA : . . . . . . . . . . . . . . 0°C to 70°C
Operating free-air temperature range (’27C5256-_ _JE, ’27PC256-_ _FME) TA : . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
6
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SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
recommended operating conditions
MIN
Read mode (see Note 2)
VCC
Supply voltage
VPP
Supply voltage
VIH
High-level dc input voltage
VIL
Low-level dc input voltage
TA
Operating free-air temperature
TA
Operating free-air temperature
SNAP! Pulse programming algorithm
Read mode
SNAP! Pulse programming algorithm
TTL
NOM
MAX
4.5
5
5.5
6.25
6.5
6.75
13
VCC+0.6
13.25
V
VCC+1
VCC+1
V
VCC −0.6
12.75
2
CMOS
VCC − 0.2
− 0.5
TTL
CMOS
UNIT
V
0.8
V
− 0.5
0.2
’27C256-_ _JL
’27PC256-_ _FML
0
70
°C
’27C256-_ _JE
’27PC256-_ _FME
− 40
85
°C
NOTE 2: VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted
into or removed from the board when VPP or VCC is applied.
electrical characteristics over recommended ranges of operating conditions
PARAMETER
TEST CONDITIONS
IOH = − 2.5 mA
IOH = − 20 µA
VOH
High-level dc output voltage
VOL
Low-level dc output voltage
II
IO
Input current (leakage)
IPP1
IPP2
VPP supply current
VPP supply current (during program pulse)
Output current (leakage)
VCC supply current
ICC1
(standby)
TTL-input level
CMOS-input level
ICC2 VCC supply current (active)
MIN
TYP†
MAX
UNIT
3.5
V
VCC − 0.1
IOL = 2.1 mA
IOL = 20 µA
VI = 0 V to 5.5 V
0.4
±1
µA
VO = 0 V to VCC
VPP = VCC = 5.5 V
±1
µA
VPP = 13 V
VCC = 5.5 V,
0.1
E = VIH
VCC = 5.5 V,
E = VCC
VCC = 5.5 V,
E = VIL,
tcycle = minimum cycle time,
outputs open
V
1
10
µA
35
50
mA
250
500
100
250
15
30
A
µA
mA
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz†
PARAMETER
Ci
TEST CONDITIONS
Input capacitance
Co
Output capacitance
† Capacitance measurements are made on a sample basis only.
‡ Typical values are at TA = 25°C and nominal voltages.
POST OFFICE BOX 1443
VI = 0,
VO = 0,
TYP‡
MAX
UNIT
f = 1 MHz
6
10
pF
f = 1 MHz
10
14
pF
• HOUSTON, TEXAS 77251−1443
MIN
7
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
switching characteristics over recommended range of operating conditions
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
’27C256-10
’27PC256-10
MIN
MAX
’27C256-12
’27PC256-12
MIN
MAX
’27C256-15
’27PC256-15
MIN
UNIT
MAX
ta(A)
ta(E)
Access time from address
100
120
150
ns
Access time from chip enable
100
120
150
ns
ten(G)
Output enable time from G
55
55
75
ns
tdis
Output disable time from G or E, whichever
occurs first†
60
ns
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs first†
0
45
0
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
ta(A)
ta(E)
CL = 100 pF,
1 Series 74 TTL Load,
Input tr ≤ 20 ns,
Input tf ≤ 20 ns
45
0
’27C256-17
’27PC256-17
MIN
0
MAX
0
’27C256-20
’27PC256-20
MIN
0
MAX
ns
’27C256-25
’27PC256-25
MIN
UNIT
MAX
Access time from address
170
200
250
ns
Access time from chip enable
170
200
250
ns
75
75
100
ns
60
ns
ten(G)
Output enable time from G
tdis
Output disable time from G or E, whichever
occurs first†
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs first†
CL = 100 pF,
1 Series 74 TTL Load,
Input tr ≤ 20 ns,
Input tf ≤ 20 ns
0
0
60
0
60
0
0
0
ns
† Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low) (see Figure 2).
4. Common test conditions apply for the tdis except during programming.
switching characteristics for programming: VCC = 6.50 V and VPP = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)
PARAMETER
tdis(G)
ten(G)
Output disable time from G
MIN
MAX
UNIT
0
130
ns
150
ns
Output enable time from G
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low).
timing requirements for programming
MIN
NOM
MAX
UNIT
µs
th(A)
th(D)
Hold time, address
tw(IPGM)
tsu(A)
Pulse duration, initial program
Setup time, address
2
µs
tsu(G)
tsu(E)
Setup time, G
2
µs
Setup time, E
2
µs
tsu(D)
tsu(VPP)
Setup time, data
2
µs
Setup time, VPP
2
µs
tsu(VCC)
Setup time, VCC
2
µs
8
0
Hold time, data
µs
2
95
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
100
105
µs
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
2.08 V
RL = 800 Ω
Output
Under Test
CL = 100 pF
(see Note A)
NOTE A: CL includes probe and fixture capacitance.
ac testing input/output wave forms
2.4 V
2V
0.8 V
0.4 V
2V
0.8 V
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
Figure 2. AC Testing Output Load Circuit
VIH
A0 −A14
Addresses Valid
VIL
VIH
E
VIL
ta(E)
VIH
G
ta(A)
VIL
tdis
ten(G)
tv(A)
VOH
DQ0 −DQ7
Output Valid
Hi-Z
Hi-Z
VOL
Figure 3. Read-Cycle Timing
POST OFFICE BOX 1443
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9
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
Program
Verify
Address
N+1
Address Stable
A0 −A14
VIH
VIL
th(A)
tsu(A)
VIH / VOH
DQ0 −DQ7
Hi-Z
Data-In Stable
Data-Out Valid
VIL / VOH
tdis(G)†
tsu(D)
VPP‡
VPP
VCC
tsu(VPP)
VCC‡
VCC
tsu(VCC)
tsu(E)
VCC
th(D)
VIH
E
ten(G)†
tw(IPGM)
VIL
tsu(G)
VIH
G
VIL
† tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer
‡ 13-V VPP and 6.5-V VCC for SNAP! Pulse programming
Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)
10
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SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
FM (R-PQCC-J32)
PLASTIC J-LEADED CHIP CARRIER
Seating Plane
0.004 (0,10)
0.140 (3,56)
0.132 (3,35)
0.495 (12,57)
4
0.485 (12,32)
0.129 (3,28)
0.123 (3,12)
0.453 (11,51)
0.447 (11,35)
0.049 (1,24)
0.043 (1,09)
1
0.008 (0,20) NOM
30
29
5
0.020 (0,51)
0.015 (0,38)
0.595 (15,11)
0.585 (14,86)
0.553 (14,05)
0.547 (13,89)
0.030 (0,76)
TYP
21
13
14
20
0.050 (1,27)
4040201-4 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-016
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
11
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
J (R-CDIP-T**)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PIN SHOWN
B
13
24
C
12
1
Lens Protrusion
0.010 (0,25) MAX
0.065 (1,65)
0.045 (1,14)
0.090 (2,29)
0.060 (1,53)
0.018 (0,46) MIN
0.175 (4,45)
0.140 (3,56)
A
Seating Plane
0°−ā 10°
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
PINS**
A
B
C
24
NARR
DIM
0.012 (0,30)
0.008 (0,20)
32
28
WIDE
NARR
WIDE
NARR
40
WIDE
NARR
WIDE
MAX
0.624(15,85) 0.624(15,85)
0.624(15,85) 0.624(15,85)
0.624(15,85) 0.624(15,85)
0.624(15,85) 0.624(15,85)
MIN
0.590(14,99) 0.590(14,99)
0.590(14,99) 0.590(14,99)
0.590(14,99) 0.590(14,99)
0.590(14,99) 0.590(14,99)
MAX
1.265(32,13) 1.265(32,13)
1.465(37,21) 1.465(37,21)
1.668(42,37) 1.668(42,37)
2.068(52,53) 2.068(52,53)
MIN
1.235(31,37) 1.235(31,37)
1.435(36,45) 1.435(36,45)
1.632(41,45) 1.632(41,45)
2.032(51,61) 2.032(51,61)
MAX
0.541(13,74) 0.598(15,19)
0.541(13,74) 0.598(15,19)
0.541(13,74) 0.598(15,19)
0.541(13,74) 0.598(15,19)
MIN
0.514(13,06) 0.571(14,50)
0.514(13,06) 0.571(14,50)
0.514(13,06) 0.571(14,50)
0.514(13,06) 0.571(14,50)
4040084 / B 04/95
NOTES: A.
B.
C.
D.
12
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
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