ETC TMS28F1600B90CDCDE

TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
D
D
D
D
D
D
D
D
Auto-Select VCC and VPP Voltages
– 2.7 V, 3.3 V, or 5 V Read Operation (VCC)
– 2.7 V, 3.3 V, 5 V, or 12 V Program Erase
(VPP)
Fast Read Access Time
– 5 V:
80/90 ns MAX
– 2.7 V, 3.3 V: 90/100 ns MAX
Low Power Consumption (VCC = 5.5V)
– Active Write
220 mW (Byte Mode)†
– Active Read
248 mW (Byte Mode)†
– Active Write
220 mW (Word Mode)†
– Active Read
248 mW (Word Mode)†
– Block-Erase 220 mW†
– Standby
0.55 mW
– Deep Power-Down Mode 0.044 mW
Automatic Power-Saving Mode
Sector Architecture
– One 16K-Byte Protected Boot Block
– Two 8K-Byte Parameter Blocks
– One 96K-Byte Main Block
– Fifteen 128K-Byte Main Blocks
– Top or Bottom Boot Locations
User-Selectable x8 or x16 Operation
Fully Automated On-Chip Erase and
Byte/Word Program Operations
All Inputs/Outputs TTL-Compatible
Supports Concurrent Operations
– Read During Program
– Read During Erase
– Program During Erase
– Two-Byte / -Word Programming
– Two Sector Combinations Erasure
D
D
D
D
D
D
D
Enhanced Suspend Options
– Sector-Erase-Suspend to Read
– Sector-Erase-Suspend to Program
– Program-Suspend to Read
Command Set Compatible With Previous
Generation of Flash
Transition Between Single-Operation and
Concurrent-Operations Mode by way of
Software Command
100 000 Program / Erase Cycles Per Sector
Hardware Write-Protection for Boot Block
Two Temperature Ranges
– Commercial
0°C to 70° C
– Extended
– 40°C to 85° C
Industry Standard Packaging (JEDEC)
– 48-Pin TSOP (DCD Suffix)
PIN NOMENCLATURE
A0 – A19
BYTE
DQ0 – DQ14
DQ15/A–1
CE
OE
NC
RP
VCC
VPP
VSS
WE
WP
PRODUCT PREVIEW
D
Address Inputs
Byte Enable
Data In / Data out
Data In/Out (word-wide mode)
Low Order Address (byte-wide mode)
Chip Enable
Output Enable
No Internal Connection
Reset / Deep Power Down
Power Supply
Power Supply for Program / Erase
Ground
Write Enable
Write Protect
description
The TMS28F1600T / B is a 16777216-bit, boot-block flash memory that can be electrically block-erased and
reprogrammed. The TMS28F1600T/B is organized in a sectored architecture consisting of one 16K-byte
protected boot sector, two 8K-byte parameter sectors, one 96K-byte main sector, and fifteen 128K-byte main
sectors. Operation as a 2M-byte (8-bit) or a 1M-word (16-bit) organization is user-selectable.
Embedded program and block-erase functions are fully automated by two on-chip write state machines
(WSMs), simplifying these operations and relieving the system microcontroller of these secondary tasks. WSM
statuses can be monitored by two on-chip status registers, one for each WSM, to determine progress of
program/erase tasks.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† In single-operation mode
Copyright  1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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1
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
PRODUCT PREVIEW
TMS28F1600T/B
48-PIN TSOP (DCD)
(TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RP
VPP
WP
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2
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A16
BYTE
VSS
DQ15 / A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
description (continued)
The ’28F1600 has the auto-select feature that allows the user alternative read and program/erase voltages for
maximum flexibility. Memory reads can be performed using VCC = 2.7 or 3.3 V for optimum power consumption
or at VCC = 5 V for device performance. Erasing or programming the device can be accomplished with
VPP = 2.7 V, 3.3 V, or 5 V which eliminates having to use a 12-V source and/or in-system voltage converters.
Alternatively, 12-V VPP operation exists for systems that already have a 12-V power supply.
device symbol nomenclature
TMS28F1600
T
80
C
DCD
L
Temperature Range Designator
L =
0°C to 70°C
E = – 40°C to 85°C
Package Designator
DCD = Plastic Dual Small-Outline Package (48-Pin)
PRODUCT PREVIEW
Program/Erase Endurance
C = 100 000 Cycles
B = 10 000 Cycles
Speed Designator
80 = 80 ns
90 = 90 ns
Boot-Block Location Indicator
T = Top Location
B = Bottom Location
Table 1. VCC / VPP Voltage Configurations†
DEVICE CONFIGURATION
TMS28F1600T
TMS28F1600B
† 3-V range indicates 2.7 V to 3.6 V maximum.
READ VOLTAGE (VCC)
2.7 V to 3.6 V, 5 V ± 10 %
2.7 V to 3.6 V, 5 V ± 10 %
PROGRAM/ERASE VOLTAGE (VPP)
" 5%
3 V/5 V ± 10% or 12 V " 5%
3 V/5 V ± 10% or 12 V
architecture
The TMS28F1600T / B uses a sectored architecture to allow independent erasure of selected memory blocks.
The sector to be erased is selected by using any valid address within that sector.
The TMS28F1600T/B has two (2) memory banks. Bank A consists of:
D
D
D
D
One 16K-byte protected boot sector
Two 8K-byte parameter sectors
One 96K-byte main sector and
Seven 128K-byte main sectors
and bank B consists of:
D
Eight 128K-byte main sectors
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
architecture (continued)
Embedded program and block-erase functions for each memory bank are fully automated by a separate and
independent WSM. With two WSMs, each controlling one memory bank (8M bits of memory space), the overall
system performance is greatly improved by allowing the device to be programmed/erased in one bank while
simultaneously reading data from another sector of the other memory bank. The device also can be
erased / programmed in one sector of one memory bank while simultaneously erased / programmed in another
sector of the other memory bank.
Within each bank, the suspend command can be used to suspend the erase operation to read from or program
data to another sector not being erased. The suspend command can be used also to suspend the program
operation so that data from any address location other than the one being programmed can be read.
PRODUCT PREVIEW
The TMS28F1600 is available with the sector architecture mapped with the boot block located at the top
(TMS28F1600T) or at the bottom (TMS28F1600B) of the memory array, as required by different
microprocessors. The bottom boot block is mapped with the 16K-byte boot block located at the low-order
address range (00000h to 01FFFh, word mode). The top boot block is mapped with the 16K-byte boot block
located at the high-order address range (FFFFFh to FE000h, word mode). Figure 1 and Figure 2 show the
memory maps for the top and bottom boot block configuration, respectively.
boot-sector data protection
The 16K-byte boot block can be used to store key system data that is seldom changed in normal operation. Data
in this block can be protected by using different combinations of the reset/power-down pin (RP), the write protect
pin (WP) and VPP supply levels. See Table 2 for a listing of these combinations.
Table 2. Data Protection Combinations
DATA PROTECTION PROVIDED
VPP
All sectors locked
VPPLK
All sectors locked (reset)
X
All sectors unlocked
Only boot block locked
4
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VPPLK
VPPLK
VPPLK
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RP
WP
X
X
VIL
VHH
X
VIH
VIH
VIH
VIL
X
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INPUT
BUFFER
ADDRESS
COUNTER
B
A0 – A19
ADDRESS
COUNTER
A
ADDRESS
DECODER
X DECODER
Y DECODER
ADDRESS
LATCH
DQ0 – DQ7
DQ8 – DQ15/A – 1
Y DECODER
X DECODER
functional block diagram
128KByte
Main
16KByte
Boot
Block
OUTPUT
BUFFER
8KByte
Para
96KByte
Main
128KByte
Main
128KByte
Main
128KByte
Main
128KByte
Main
128KByte
Main
STATUS REGISTER B
Y Gating/Sensing
128KByte
Main
128KByte
Main
STATUS REGISTER A
ID REGISTER
DATA
COMPARATOR
128KByte
Main
128KByte
Main
128KByte
Main
PRODUCT PREVIEW
128KByte
Main
DATA
COMPARATOR
128KByte
Main
Y Gating/Senting
128KByte
Main
OUTPUT
BUFFER
OUTPUT MULTIPLEXER
8KByte
Para
INPUT
BUFFER
128KByte
Main
Data
Register B
Data
Register A
Program/
Erase
Voltage
Switch
VPP
VPP
I/O
LOGIC
INPUT
BUFFER
Program/
Erase
Voltge
Switch
BYTE
WRITE
STATE
MACHINE B
COMMAND
STATE
MACHINE
B
COMMAND
STATE
MACHINE
A
WRITE
STATE
MACHINE
A
CE
WE
OE
RP
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
5
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
parameter sector
Two parameter sectors of 8K bytes each can be used like a scratch pad to store frequently updated data.
Alternatively, the parameter sectors can be used for additional boot or main-sector data. If a parameter sector
is used to store additional boot-block data, caution should be exercised because the parameter sector does not
have the boot-block data protection safety feature.
main sector
PRODUCT PREVIEW
Primary memory on the TMS28F1600T/B is located in sixteen main sectors. Fifteen of the sectors have storage
capacity for 128K-bytes and the remaining sector has storage capacity of 96K bytes.
6
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
main sector (continued)
1E0000h
1DFFFFh
1C0000h
1BFFFFh
1A0000h
19FFFFh
180000h
17FFFFh
160000h
15FFFFh
140000h
13FFFFh
120000h
11FFFFh
100000h
FFFFFh
E0000h
DFFFFh
C0000h
BFFFFh
A0000h
9FFFFh
80000h
7FFFFh
60000h
5FFFFh
40000h
3FFFFh
20000h
1FFFFh
00000h
Parameter Sector
8K Address
Parameter Sector
4K Address
Parameter Sector
8K Address
Parameter Sector
4K Address
Main Sector
96K Address
Main Sector
48K Address
Main Sector
128K Address
Main Sector
128K Address
Main Sector
128K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
64K Address
Main Sector
64K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
128K Address
Main Sector
128K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
64K Address
Main Sector
64K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Address
Range
FFFFFh
FE000h
FDFFFh
FD000h
FCFFFh
FC000h
FBFFFh
F0000h
EFFFFh
E0000h
DFFFFh
D0000h
CFFFFh
C0000h
BFFFFh
PRODUCT PREVIEW
1F8000h
1F7FFFh
Boot Sector
8K Address
Bank A
(Write State Machine A)
1FA000h
1F9FFFh
Boot Sector
16K Address
Bank B
(Write State Machine B)
1FC000h
1FBFFFh
x16 Configuration
Bank A
(Write State Machine A)
1FFFFFh
x8 Configuration
Bank B
(Write State Machine B)
Address
Range
B0000h
AFFFFh
A0000h
9FFFFh
90000h
8FFFFh
80000h
7FFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
FFFFh
0000h
Figure 1. TMS28F1600T (Top Boot Sector) Memory Map
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
main sector (continued)
1A0000h
19FFFFh
180000h
17FFFFh
160000h
15FFFFh
140000h
13FFFFh
PRODUCT PREVIEW
120000h
11FFFFh
100000h
FFFFFh
E0000h
DFFFFh
C0000h
BFFFFh
A0000h
9FFFFh
80000h
7FFFFh
60000h
5FFFFh
40000h
3FFFFh
20000h
1FFFFh
8000h
7FFFh
6000h
5FFFh
4000h
3FFFh
00000h
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
128K Address
Main Sector
128K Address
Bank B
(Write State Machine B)
1C0000h
1BFFFFh
Main Sector
128K Address
Main Sector
64K Address
Main Sector
64K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
64K Address
Main Sector
128K Address
Main Sector
128K Address
Main Sector
128K Address
Main Sector
96K Address
Bank A
(Write State Machine A)
1E0000h
1DFFFFh
x16 Configuration
Bank B
(Write State Machine B)
1FFFFFh
x8 Configuration
Bank A
(Write State Machine A)
Address
Range
Main Sector
64K Address
Main Sector
64K Address
Main Sector
64K Address
Main Sector
48K Address
Parameter Sector
8K Address
Parameter Sector
4K Address
Parameter Sector
8K Address
Parameter Sector
4K Address
Boot Sector
16K Address
Boot Sector
8K Address
Figure 2. TMS28F1600B (Bottom Boot Sector) Memory Map
8
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Address
Range
FFFFFh
FC000h
EFFFFh
E0000h
DFFFFh
D0000h
CFFFFh
C0000h
BFFFFh
B0000h
AFFFFh
A0000h
9FFFFh
90000h
8FFFFh
80000h
7FFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
FFFFh
4000h
3FFFh
3000h
2FFFh
2000h
1FFFh
00000h
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
data protection
Data is secured or unsecured by using different combinations of the reset/power-down pin (RP), the write
protect pin (WP) and VPP supply levels. Table 2 lists these combinations.
There are two ways to secure the entire memory against inadvertent alteration of data. The VPP supply pin can
be held below the VPP lock-out voltage level (VPPLK) or the reset / deep power-down pin (RP) can be pulled to
a logic-low level. Note that if RP is held low, the device resets, which means it powers down and, therefore,
cannot be read. Typically, this pin is tied to the system reset for additional protection during system power up.
The boot sector has an additional security feature through the WP pin. When the RP pin is at logic-high level,
the WP pin controls whether the boot sector is protected. When WP is held at logic-low level, the boot sector
is protected. When WP is held at logic-high level, the boot sector is unprotected along with the rest of the other
sectors. Alternatively, the entire memory can be unprotected by pulling the RP pin to VHH (12 V).
There are two CSMs and each is corresponded to one WSM. The CSMs act as an interface between the external
microprocessor and the two internal WSMs. Commands are issued to the CSMs using standard microprocessor
write timings. Since both CSMs share the same data path, commands issued to the device are processed by
both CSMs simultaneously. If CSM A determines that the command is not applicable to the memory bank/WSM
that it is interfacing with (memory bank A), then that command is ignored and CSM B sends the command to
bank B/WSM B for execution. The CSM main task is to determine if the inputted command is valid and to send
the valid command to the corresponding WSM. In single-operation mode, the contents of both status registers
and the state of both CSMs are synchronized. Therefore, from the user’s point of view, the device behaves as
if there is only one CSM, one status register and one WSM that control both memory banks. In
concurrent-operations mode, the contents of both status registers and the state of both CSMs are independent.
When a program or erase command is issued to the CSM for one memory bank, the WSM for that memory bank
controls the internal program/erase sequences and the CSM responds to status-read and suspend/resume
only. After the WSM completes its task, the WSM status bit (SB7) is set to a logic-high level (1), allowing the
CSM to respond to the full command set again (see Table 5 for the status register bit definition). The complete
command sets are listed in Table 3 and the description of these commands are shown in Table 4.
Table 3. Command State Machine Codes for Device-Mode Selection
COMMAND CODE
ON DQ0 – DQ7†
DEVICE MODE
Standard Command Set
00h
Invalid / Reserved
10h
Alternate Program Setup
20h
Block-Erase Setup
40h
Program Setup
50h
Clear Status Register
70h
Read Status Register
90h
Algorithm Selection
B0h
Erase-Program Suspend
D0h
Erase-Program Resume / Block-Erase Confirm
FFh
Read Array
Extended Command Set
CBh
Enable Concurrent Mode
CEh
Disable Concurrent Mode
† DQ0 is the least significant bit. DQ8–DQ15 can be any valid 2-state level.
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PRODUCT PREVIEW
command state machine (CSM)
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
command state machine (CSM) (continued)
Table 4. Command Definitions for Single and Concurrent Operations
COMMAND
BUS CYCLE
REQUIRED
FIRST BUS CYCLE
OPERATION
ADDRESS
SECOND BUS CYCLE
DATA
INPUT
OPERATION
ADDRESS
DATA
IN/OUT
RA
Data Out
Read Operations
Read Array
1
Write
See Notes
1 and 2
FFh
Read
Read Algorithm-Selection Code
3
Write
X
90h
Read
A0
M/D
Read
See
Note 1
SRB
Read Status Register
2
Write
X
70h
Clear Status Register
1
Write
See
Notes 1
and 2
50h
PRODUCT PREVIEW
Program Operations
Program-Setup / Program
(byte/word)
2
Write
PA
40h or 10h
Write
PA
PD
Program-Suspend/
Program-Resume
2
Write
See
Notes 1
and 2
B0h
Write
See
Note 1
D0h
Erase Operations
Block-Erase Setup/
Block-Erase Confirm
2
Write
BEA
20h
Write
BEA
D0h
Erase-Suspend/
Erase-Resume
2
Write
See
Notes 1
and 2
B0h
Write
See
Notes 1
and 2
D0h
Concurrent Operations
Enable Concurrent Mode
(see Note 2)
1
Write
X
CBh
Disable Concurrent Mode
(see Note 2)
1
Write
X
CEh
Legend:
BEA
M/D
PA
PD
RA
SRB
X
NOTES:
Block-erase address. Any address selected within a block selects that block for erase.
Manufacturer-equivalent / device-equivalent code
Address to be programmed
Data to be programmed at PA
Address to be read from
Status-register data byte that can be found on DQ0–DQ7
Don’t care
1. For single operation: address = don’t care
For concurrent operation:
address = 0xxxxxh for low-order address memory bank/WSM
address = 1xxxxxh for high-order address memory bank/WSM
2. To operate the device concurrently, the user must first issue the enable concurrent mode command. This command is valid only when
the device is not busy performing any operation (that is, WSM is not active). To exit the concurrent-operation mode, the user must
issue the disable concurrent mode command. This command is valid only when the device is in concurrent-operations mode and
none of the memory banks/WSMs are active.
10
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
operation
The TMS28F1600T/B is capable of performing either single or concurrent operations. Single operation means
that the device is performing one operation on one memory bank at a time, or in other words, only one WSM
is active. A WSM is considered active even when it is in a suspended state. Therefore, from the user’s point
of view, the device behaves as if there is only one WSM that controls both memory banks. Concurrent operations
mean that the device is performing two operations on two memory banks simultaneously, or in other words, both
WSMs are active.
To enable the concurrent-operations mode, the user must issue the enable concurrent mode command to the
CSM. This command is valid only when the device is not busy performing any operation (that is, WSM is not
active). Once the concurrent-operations mode is enabled, both status registers are cleared, both CSMs are
reset to the read-array mode, and any commands issued to the CSMs from that point forward must be in
accordance with the concurrent-operations command definitions. Command definitions for both single and
concurrent-operations modes are listed in Table 4. Note that both command definitions are the same except
for four commands: read array, read status register, clear status register, and suspend/resume. In
single-operation mode, the addresses are don’t care for those commands. However, in concurrent-operations
mode, the user must indicate to the CSMs to which write-state machine/memory bank the command is
applicable by supplying the memory bank address. This is the only difference between single and concurrent
operations as far as command definitions are concerned.
To initiate concurrent operations once the concurrent mode is enabled, the user sequentially issues two
commands to the CSMs, one for each memory bank; the issued commands must be in accordance with the
concurrent-operations command definitions. Note that while the concurrent mode is enabled, the user does not
have to operate the device concurrently; the user can operate the device as in single-operation mode but with
the command definitions slightly modified. In addition, the user can access and clear each status register
individually in concurrent mode.
To exit the concurrent-operations mode and return to the standard flash single-operation mode, the user must
issue a disable concurrent mode command to the CSMs. This command is valid only when the device is in
concurrent-operations mode and none of the memory banks/WSMs are active. Once concurrent-operations
mode is disabled, both status registers are cleared and both CSMs reset to the read-array mode. Alternatively,
the user can use the reset/power-down mode to reset the device to single-operation, read-array mode.
Since both registers are cleared when concurrent-operations mode is enabled/disabled, it is recommended that
the status register be read, if required, before the concurrent mode is enabled/disabled.
concurrent operations
Since the TMS28F1600T / B has two independent WSMs, two operations can be performed on two memory
banks concurrently. However, there are some rules and restrictions that must be adhered to when operating
the device concurrently.
First, read is an operation that cannot be performed concurrently with another read. Second, if read is to be a
part of a concurrent operation, then read must be the last command issued to the CSM. Third, once a read
command is issued, the CSM does not accept any other command until the read operation is complete. Read
array, read algorithm-selection, read status register and clear status register commands are considered to be
the same (that is, a read operation) as far as concurrent operations are concerned.
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11
PRODUCT PREVIEW
Device operations are selected by entering 8-bit command codes with conventional microprocessor timing into
two on-chip CSMs through I/O pins DQ0 – DQ7. When the device is powered up, internal reset circuitry initializes
the CSMs to single-operation, read-array mode. In single-operation mode, the device is functionally compatible
with the existing 8-Mbit boot-block devices (TMS28F800T/B). Changing the mode of operation requires a
command code to be entered into the CSM. Table 3 lists the CSM codes for all modes of operation.
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
concurrent operations (continued)
For example, a concurrent read-erase operation is not possible because as soon as the CSM receives the read
command, no other command is processed until the read operation is complete. Whereas, a concurrent
erase-read operation is possible because the erase command is given first (for example, to erase a sector in
memory bank A) and the read command is given last (for example, to access bank B). Only when the read
operation is complete, is the CSM ready to accept any other valid command. At this point, the user has two
options from which to choose. If operation on memory bank B is desired, then the user can send a read, program,
or erase command. If operation on memory bank A is desired, then the user can either do an erase-suspend
to read or an erase-suspend to program; both of which must be done in a sector that is not being erased.
Two rules / restrictions govern the suspend operation:
D
PRODUCT PREVIEW
D
Read array, read status register, and program-resume are the only valid commands for the applicable
WSM/ memory bank after a program operation is suspended; all other commands are invalid and are
ignored by the CSM. If concurrent-operations mode is enabled, then the other CSM will accept any other
valid command for the other WSM / memory bank.
Read array, read status register, program, and erase-resume are the only valid commands for the applicable
WSM/ memory bank after a sector-erase operation is suspended; all other commands are invalid and are
ignored by the CSM. If concurrent-operations mode is enabled, then the other CSM will accept any other
valid command for the other WSM / memory bank.
In general, any operation or combination of operations is possible as long as it does not violate the
rules / restrictions mentioned above. Note that multiple suspension within the same memory bank is allowed.
For example, if an erase operation is suspended for a program operation, then that program operation can also
be suspended to read data. Table 5 shows all the legal operations that can be performed concurrently.
12
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concurrent operations (continued)
Table 5. Concurrent Operations State Matrix†
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MEMORY BANK A
B
A
N
K
B
ProgramSuspendRead‡¶
SectorErase
EraseSuspend
EraseSuspendRead‡¶
EraseSuspendProgram
EraseSuspend
ProgramSuspend
EraseSuspend
ProgramSuspendRead‡¶
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Not
Allowed
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Not
Allowed
Not
Allowed
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Not
Allowed
Not
Allowed
Not
Allowed
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Program
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Program-Suspend
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Program-SuspendRead‡¶
Not
Allowed
Not
Allowed
Not
Allowed
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Sector-Erase
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Erase-Suspend
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Erase-SuspendRead‡¶
Not
Allowed
Not
Allowed
Not
Allowed
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Erase-SuspendProgram
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Erase-Suspend
Program-Suspend
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Erase-Suspend
Program-SuspendRead‡¶
Not
Allowed
Not
Allowed
Not
Allowed
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Yes
Yes
Not
Allowed
Algorithm
Selection‡§
Read
Status
Register‡
Clear
Status
Register‡
Read Array‡
Not
Allowed
Not
Allowed
Not
Allowed
Algorithm Selection‡§
Not
Allowed
Not
Allowed
Read Status Register‡
Not
Allowed
Clear Status Register‡
13
PRODUCT PREVIEW
SMJS836 – JANUARY 1997
† Reset/deep power-down places both write-state machines/memory banks in the reset/deep power-down mode.
‡ Read array, algorithm-selection, read status register, and clear status register are considered “read” operations. Therefore, if a read operation is to be a part of concurrent operations,
it must be the last command issued. If the read operation is issued first, then the CSM will not process any other command until the read operation is complete.
§ Either WSM can access the manufacturer and device ID information
¶ The clear-status-register and read-algorithm-selection commands are not functional during erase-suspend and program-suspend modes.
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
M
E
M
O
R
Y
Program
ProgramSuspend
Read
Array‡
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
command definition
Command definitions for both single and concurrent operations are listed in Table 4. Note that both command
definitions are the same except for four commands: read array, read status register, clear status register, and
suspend/ resume. In single-operation mode, the address is a don’t care for these commands. However, in
concurrent-operations mode, the user must indicate to the CSM which write-state machine / memory bank the
command is applicable to by supplying the memory bank address.
In single-operation mode, the user can use either single or concurrent operations command definitions to send
the desired command to the CSM. However, once the concurrent-operations mode is enabled, all subsequent
commands issued must be in accordance with the concurrent-operations mode command definitions.
Once a specific command code has been entered, the WSM executes an internal algorithm generating the
necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and
data for each of the bus cycles.
PRODUCT PREVIEW
Following the read-algorithm-selection-code command, two read cycles are required to access the
manufacturer-equivalent code and the device-equivalent code. Table 7 and Table 8 show the code for
word-wide mode and byte-wide mode, respectively.
status register
There are two 8-bit on-chip status registers. Status register A corresponds to WSM A and status register B
corresponds to WSM B. The status register can be monitored to see whether the state of a program/erase
operation is pending or complete by writing a read-status command to the CSM and reading the resulting status
code on I/O pins DQ0–DQ7. This is valid for operation in either the byte or word-wide mode. When writing to
the CSM in word-wide mode, the high-order I / O pins (DQ8 – DQ15) can be set to any valid 2-state level. When
reading the status bit during a word-wide read operation, the high-order I / Os (DQ8 – DQ15) are set to 00h
internally, so the user needs to interpret only the low-order I/O pins (DQ0 – DQ7).
After a read-status command has been given, the data appearing on DQ0 – DQ7 remains as status register data
until a new command is issued to the CSM. To return the device to other modes of operation, a new command
must be issued to the CSM.
Register data is updated on the falling edge of OE or CE. The latest falling edge of either of these two signals
updates the latches within a given read cycle. Latching the data prevents errors from occurring should the
register input change during a status register read. To assure that the status register output contains updated
status data, CE or OE must be toggled for each subsequent status read.
The status registers provide the internal state of the WSMs to the external microprocessor. During periods when
the WSMs are active, the status registers can be polled to determine the status of the WSMs. Table 6 defines
the status register bits and their functions.
In single-operation mode, the contents of both status registers and the state of both CSMs are synchronized.
Therefore, from the user’s point of view, the device behaves as if only one CSM, one status register, and one
WSM are controlling both memory banks. In concurrent-operations mode, the contents of both status registers
and the state of both CSMs are independent. Therefore, in concurrent-operations mode, the user can access
and clear each status register individually.
14
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
status register (continued)
Table 6. Status-Register Bit Definitions and Functions (see Note 3)
SB7
SB6
FUNCTION
DATA
COMMENTS
Write state machine
status
1 = Ready
0 = Busy
If SB7 = 0 (busy), the WSM has not completed an erase or
programming operation. If SB7 = 1 (ready), other polling operations can
be performed. Until this occurs, the other status bits are not valid. If the
WSM status bit shows busy (0), the user must periodically toggle CE
or OE to determine when the WSM has completed an operation
(SB7 = 1) since SB7 is not updated automatically at the completion of
a WSM task.
Erase-suspend status
(ESS)
1 = Erase suspended
0 = Erase in progress or
completed
When an erase-suspend command is issued, the WSM halts execution
and sets the ESS bit high (SB6 = 1), indicating that the erase operation
has been suspended. The WSM status bit also is set high (SB 7 =1)
indicating that the erase-suspend operation has been completed
successfully. The ESS bit remains at a logic-high level until an
erase-resume command is input to the CSM (code D0h).
SB5
Erase status
(ES)
1 = Sector-erase error
0 = Sector-erase good
SB5 = 0 indicates that a successful sector erasure has occurred.
SB5 = 1 indicates that an erasure error has occurred. In this case, the
WSM has completed the maximum allowed erase pulses determined
by the internal algorithm, but this was insufficient to erase the device
completely.
SB4
Program status
(PS)
1 = Byte/word program error
0 = Byte/word program good
SB4 = 0 indicates successful programming has occurred at the
addressed sector location.
SB4 = 1 indicates that the WSM was unable to program the addressed
sector location correctly.
SB3
Vpp status
(Vpps)
1 = Program abort :
Vpp range error
0 = Vpp good
SB2
Program-suspend
status (PSS)
1 = Program suspended
0 = Program in progress or
completed
SB0 – SB1
Reserved
SB3 provides information on the status of Vpp during programming. If
Vpp is lower than VPPL after a program or erase command has been
issued, SB3 is set to a 1, indicating that the programming operation is
aborted. If Vpp is between VPPH and VPPL, SB3 is not set.
When a program-suspend command is issued, the WSM halts
execution and sets the PSS bit high (SB2 = 1), indicating that the
program operation has been suspended. The WSM status bit also is set
high (SB 7 =1) indicating that the program-suspend operation has been
completed successfully. The PSS bit remains at a logic-high level until
a program-resume command is input to the CSM (code D0h).
These bits must be masked out when reading the status register.
NOTE 3: VPPL and VPPH correspond to the minimum and maximum operating voltage range of VPP, respectively.
byte- or word-wide mode selection
Device operation is either byte-wide or word-wide mode user-selectable and is determined by the logic state
of BYTE. When BYTE is at logic-high level, the device is in the word-wide mode and data is written to, or read
from, I/O pins DQ0–DQ15. When BYTE is at logic-low level, the device is in the byte-wide mode and data is
written to, or read from, I/O pins DQ0–DQ7. In the byte-wide mode, I/O pins DQ8–DQ14 are placed in the
high-impedance state and DQ15/A-1 becomes the low-order address pin. Table 7 and Table 8 summarize
operations for word-wide mode and byte-wide mode, respectively.
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15
PRODUCT PREVIEW
STATUS
BIT
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
byte- or word-wide mode selection (continued)
Table 7. Operation Modes for Word-Wide Mode (BYTE = VIH) (see Note 4)
MODE
Read
WP
CE
OE
RP
WE
A9
A0
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
A9
A0
VPP
X
VID
VIL
X
X
PRODUCT PREVIEW
Algorithm-selection mode
DQ15–DQ0
Data out
Manufacturer-equivalent code 0089h
Device-equivalent code 00xxh
(top boot block)
X
VIL
VIL
VIH
VIH
VID
VIH
X
Output disable
X
VIH
VIH
VIH
X
X
X
Hi-Z
X
VIH
X
X
Standby
VIL
VIH
X
X
X
Hi-Z
Reset/deep power down
X
X
X
X
X
X
X
Hi-Z
Write (see Notes 3 and 5)
VIL
or
VIH
VIL
VIH
or
VHH
A0
VPPL
or
VPPH
VIL
VIH
VIL
A9
Device-equivalent code 00xxh
(bottom boot block)
Data in
Table 8. Operation Modes for Byte-Wide Mode (BYTE = VIL) (see Note 4)
MODE
WP
CE
OE
RP
WE
A9
A0
VPP
Read lower byte
X
VIL
VIL
VIH
VIH
VIH
VIH
A0
X
X
VIL
VIL
A9
Read upper byte
A9
A0
X
X
VIL
VIL
VIH
VIH
VID
VIL
X
DQ15/
A–1
VIL
VIH
X
DQ14–DQ8
DQ7–DQ0
Hi-Z
Data out
Hi-Z
Data out
Hi-Z
Manufacturer-equivalent
code 89h
Algorithm-selection mode
Device-equivalent code
??h (top boot block)
X
VIL
VIL
VIH
VIH
VID
VIH
X
X
Hi Z
Hi-Z
Output disable
X
VIH
X
VIH
VIH
VIH
X
X
X
X
Hi-Z
Hi-Z
X
X
X
X
X
Hi-Z
Hi-Z
Reset/deep power down
X
VIL
VIH
X
X
Standby
X
X
X
X
X
X
Hi-Z
Hi-Z
Write (see Notes 3 and 5)
VIL
or
VIH
VIL
VIH
VIL
VIH
or
VHH
VIL
A9
A0
VPPL
or
VPPH
X
Hi-Z
Data in
Device-equivalent code
??h (bottom boot block)
NOTES: 3. VPPL and VPPH correspond to the minimum and maximum operating voltage range of VPP, respectively.
4. X = don’t care
5. When writing commands to the ’28F1600T/B, VPP must be in the appropriate VPP voltage range for sector-erase or program
commands to be executed. Also, depending on the combination of RP and WP, the boot block can be secured and, therefore, is not
programmable (see Table 2 for the combinations).
command state machine (CSM) operations
The CSM decodes instructions for read, read algorithm-selection code, read status register, clear status
register, program, erase, erase/program suspend, and erase/program resume. The 8-bit command code is
input to the device on DQ0–DQ7 (see Table 3 for CSM codes). The CSMs act as an interface between the
external microprocessor and the two internal WSMs. During a program/erase cycle, the CSM informs the
applicable WSM (based on the input address) that a program or erase has been requested. The selected WSM
controls the program/erase sequences during a program/erase cycle and the CSM responds only to status read
and program/erase suspend commands. If concurrent-operations mode is enabled, then the other CSM will
respond to the full command set (if idle) or any valid command (if busy) for the other bank.
16
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CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
command state machine (CSM) operations (continued)
When the WSM has completed its task, the WSM status bit (SB7) of the status register is set to a logic-high level
and the CSM responds to the full command set again. In single-operation mode, the states of both CSMs are
synchronized and remain in the last issued command state until the microprocessor issues another command.
In concurrent-operations mode, the state of each CSM is independent and they also remain in the last issued
command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when VPP is within its correct voltage range.
To prevent inadvertent program/erase to the device, it is recommended that RP be tied to the system reset
signal.
The internal circuitry can set only the VPP status (SB3), the program status (SB4), and the erase-status bit (SB5)
of the status register. The clear-status register command (50h) allows the external microprocessor to clear these
status bits and synchronize to internal operations. When the status bits are cleared, the CSM returns to the
read-array mode. This is true for both single and concurrent operations mode. In single-operation mode, the
clear-status-register command clears both status registers. In concurrent operations mode, the memory bank
address determines which register to clear (see Table 4 for concurrent operations command definitions). Note
that clear status register command is not functional during program-suspend and erase-suspend modes.
read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
D
D
D
Read array. The array is read by entering the command code FFh on DQ0 – DQ7. Control pins CE and OE
must be at a logic-low level (VIL) and WE and RP must be at a logic-high level (VIH) to read data from the
memory bank. Data is available on DQ0 – DQ15 (word-wide mode) or DQ0 – DQ7 (byte-wide mode). Any
valid address within any of the sectors selects that sector and allows data to be read from the sector.
Read algorithm-selection code. Algorithm-selection codes are read by entering command code 90h on
DQ0– DQ7. Two bus cycles are required for this operation: the first to enter the command code and the next
two to read the manufacturer equivalent and the device-equivalent codes. Control pins CE and OE must
be at the logic-low level (VIL) and WE and RP must be at the logic-high level (VIH). Two identifier bytes are
accessed by toggling A0. The manufacturer-equivalent code is obtained on DQ0 – DQ7 with A0 at the
logic-low level (VIL). The device-equivalent code is obtained when A0 is set to a logic-high level (VIH).
Alternately, the manufacturer- and device-equivalent codes can be read by applying VID (nominally 12 V)
to A9 and selecting the desired code by toggling A0 high or low. All other addresses are “don’t care” (see
Table 4, Table 7 and Table 8). Note that algorithm-selection operation can be done concurrently with the
program / erase operation since the information can be accessed by either WSM (see Table 5).
Read status register. The status register is read by entering the command code 70h on DQ0 – DQ7. Control
pins CE and OE must be at a logic-low level (VIL) and WE and RP must be at a logic-high level (VIH). Two
bus cycles are required for this operation: one to enter the command code and a second to read the status
register. In a given read cycle, status-register contents are updated on the falling edge of CE or OE,
whichever occurs last within the cycle. For concurrent operations, the user must specify which register to
read status from by supplying the memory bank address. For single operations, the address is a don’t care
(see Table 4).
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PRODUCT PREVIEW
clear status register
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
programming operations
There are three CSM commands for programming: program setup, alternate program setup, and program
suspend/resume (see Table 4).
Program setup and alternate program setup are the same as far as the programming operation is concerned
except that they have different command codes.
D
Program setup. After the program setup command code is entered, the selected WSM takes over and
correctly sequences the device to complete the program operation. During this time, the CSM responds only
to status-read and -suspend commands (see Figure 3 and Figure 4). If the concurrent-operations mode is
enabled, then the other CSM will respond to the full command set or any valid command for the other bank.
PRODUCT PREVIEW
Taking RP to VIL during programming aborts the program operation. During programming, VPP must remain
in the appropriate VPP voltage range as shown in the recommended operating conditions table. Different
combinations of RP, WP, and VPP pin voltage levels ensure that data in certain sectors are protected, and,
therefore, cannot be programmed (see Table 2 for a list of combinations). Only 0s are written and compared
during a program operation. If 1s are programmed, the memory-cell contents do not change and no error
occurs.
A program-setup command can be aborted by writting FFh (in byte-wide mode) or FFFFh (in word-wide
mode) during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status
reads. When the WSM status bit (SB7) is set to a logic-high level, signifying that the nonprogram operation is
terminated, all commands for the applicable bank to the CSM become valid again.
D
Program suspend/program resume. During the execution of a programming operation, the
program-suspend command (B0h) can be entered to direct the WSM to suspend the programming
operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the
read-array, read-status register, and program-resume commands. While the selected WSM is in the
program-suspend state, data from any address location except for the location that was being programmed
can be read. To resume the programming operation, a program-resume command (D0h) must be issued
to make the CSM clear the suspend state that was set previously.
If concurrent-operations mode is enabled, then the user must specify which memory bank/WSM to
suspend/resume by supplying the memory bank address. Programming on the low-order address memory
bank is suspended/resumed if the address input is within its valid address range (that is, A19 = 0).
Programming on the high-order address memory bank is suspended/resumed if the address input is within
its valid address range (that is, A19 = 1). While the selected memory bank/WSM is in the program-suspend
state, data from any address location within the same memory bank (except for the location that was being
programmed) can be read. Figure 5 shows the program suspend/resume flowchart.
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CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
Start
COMMAND
Issue Program-Setup
Command and Byte Address
Write
Write
program
setup
Data = 40h or 10h
Addr = Address of byte to
be programmed
Issue Byte
Address/Data
Write
Write data
Data = Byte to be
programmed
Addr = Address of byte to
be programmed
Read Status-Register
Bits
No
No
SB7 = 1
?
Program
Suspend
?
Program
Suspend
Loop
Read
Status-register data.
Single-operation mode:
Addr = don’t care
Concurrent-operations mode:
Addr = 0xxxxxh for
low-order address
memory bank
= 1xxxxxh for
high-order address
memory bank
Toggle OE or CE to update
status register
Standby
Check SB7
1 = Ready, 0 = Busy
Yes
Yes
Full Status-Register
Check (optional)
See Note A
Byte-Program Completed
Repeat for subsequent bytes.
Write FFh after the last byte-programming operation to reset
the device to read-array mode
FULL STATUS-REGISTER-CHECK FLOW
Read
Status-Register Bits
No
SB3 = 0
?
VPP Range Error
BUS
OPERATION
COMMAND
No
Check SB3
1 = Detect VPP low
(see Note B)
Standby
Check SB4
1 = Byte-program error
(see Note C)
Byte-Program
Failed
Yes
COMMENTS
Standby
Yes
SB4 = 0
?
COMMENTS
Byte-Program Passed
NOTES: A. Full status-register check can be done after each byte or after a sequence of bytes.
B. SB3 must be cleared before attempting additional program / erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 3. Automated Byte-Programming Flowchart
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PRODUCT PREVIEW
BUS
OPERATION
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
Start
BUS
OPERATION
COMMAND
Write
Write
program
setup
Data = 40h or 10h
Addr = Address of
word to be
programmed
Write
Write data
Data = Word to be
programmed
Addr = Address of
word to be
programmed
Issue Program-Setup
Command and Word
Address
Issue Word
Address/Data
Read Status-Register
Bits
Program
Suspend
Loop
No
No
PRODUCT PREVIEW
SB7 = 1
?
Read
Status-register data.
Single-operation mode:
Addr = don’t care
Concurrent-operations
mode:
Addr = 0xxxxxh for
low-order address
memory bank
= 1xxxxxh for
high-order
address memory
bank
Toggle OE or CE to update
status register.
Standby
Check SB7
1 = Ready, 0 = Busy
Yes
Program
Suspend
?
Yes
Full Status-Register
Check (optional)
See Note A
Word-Program
Completed
FULL STATUS-REGISTER-CHECK FLOW
Repeat for subsequent words.
Write FFh after the last word-programming operation to
reset the device to read-array mode.
Read Status-Register
Bits
SB3 = 0
?
No
VPP Range Error
BUS
OPERATION
Yes
SB4 = 0
?
No
COMMENTS
COMMAND
Standby
Check SB3
1 = Detect VPP low
(see Note B)
Standby
Check SB4
1 = Word-program
error
(see Note C)
Word-Program
Failed
Yes
COMMENTS
Word-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program / erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 4. Automated Word-Programming Flowchart
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CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
BUS
OPERATION
COMMAND
Write
Program
suspend
Issue Program-Suspend
Command
Read Status-Register
Bits
SB7 = 1
?
No
Status-register data.
Single-operation mode:
Addr = don’t care
Concurrent-operations mode:
Addr = 0xxxxxh for
low-order address
memory bank
= 1xxxxxh for
high-order address
memory bank
Toggle OE or CE to
update status register
Standby
Check SB7
1 = Ready
Standby
Check SB2
1 = Program suspended
No
Program
Completed
Yes
Issue Memory-Read
Command
Finished
Reading
?
Yes
No
Write
Read
memory
Issue Program-Resume
Command
Program Continued
Data = B0h
Single-operation mode:
Addr = don’t care
Concurrent-operations mode:
Addr = 0xxxxxh for
low-order address
memory bank
= 1xxxxxh for
high-order address
memory bank
Read
Yes
SB2 = 1
?
COMMENTS
See Note A
Read
Write
Data = FFh
Single-operation mode:
Addr = don’t care
Concurrent-operations mode:
Addr = 0xxxxxh for
low-order address
memory bank
= 1xxxxxh for
high-order address
memory bank
Read data from locations other
than that being programmed.
Program
resume
Data = D0h
Single-operation mode:
Addr = don’t care
Concurrent-operations mode:
Addr = 0xxxxxh for
low-order address
memory bank
= 1xxxxxh for
high-order address
memory bank
NOTE A: Refer to programming flowchart for complete programming procedure
Figure 5. Program-Suspend /Resume Flowchart
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PRODUCT PREVIEW
Start
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
erase operations
There are two erase operations that can be performed by the TMS28F1600T / B: sector erase and erase
suspend/erase-resume. An erase operation must be used to initialize all bits in a sector to 1s. After sector-erase
confirm is issued, the CSM responds only status reads or erase-suspend commands for the applicable bank
until the applicable WSM completes its task. If concurrent mode is enabled, then the other CSM responds to
the full command set or any valid command for the other bank.
PRODUCT PREVIEW
D
Sector erasure. Sector erasure inside the memory array sets all bits within the addressed sector to
logic 1s. Erasure is accomplished only by sectors; data at single address locations within the sector cannot
be individually erased. The sector to be erased is selected by using any valid address within that sector.
Note that different combinations of RP, WP and VPP pin voltage levels ensure that data in certain sectors
are protected and, therefore, cannot be erased (see Table 2 for a list of combinations). Sector erasure is
initiated by a command sequence to the CSM: sector-erase setup (20h) followed by sector-erase confirm
(D0h) (see Figure 6). A two-command erase sequence protects against accidental erasure of memory
contents.
Erase setup and confirm commands are latched on the rising edge of WE or CE, whichever occurs first.
Sector addresses are latched during the sector-erase-confirm command on the rising edge of WE or CE
(See Figure 13 and Figure 14). When the sector-erase-confirm command is complete, the selected WSM
automatically executes a sequence of events to complete the sector erasure (see Figure 6). During this
sequence, the sector is programmed with logic 0s, data is verified, all bits in the sector are erased to logic 1s,
and finally, verification is performed to assure that all bits are erased correctly. Monitoring of the erase
operation is possible through the use of the status register. If the concurrent-operations mode is enabled,
then status registers A and B can be used to monitor the erase operation of the corresponding memory
bank.
D
Erase suspend/erase resume. During the execution of an erase operation, the erase-suspend command
(B0h) can be entered to direct the WSM to suspend the erase operation. Once the WSM has reached the
suspend state, it allows the CSM to respond only to the read-array, read-status register, program, and
erase-resume commands. While the selected WSM is in the erase-suspend state, data can be read from
any sector except for the sector that is being erase-suspended. Similarly, data can be programmed to any
address location except for the sector that is being erase-suspended. To resume the erase operation, an
erase-resume command (D0h) must be issued to cause the CSM to clear the suspend state previously set.
It is important to note that erase cannot be resumed until the program operation initiated during
erase-suspend has been completed. The following steps must be completed in sequence to continue the
erase operation.
1. Sector-erase operation is suspended to program
2. Program operation is suspended to read
3. Program operation is resumed by the user
4. Program operation is completed
5. Another resume command is issued
If the concurrent-operations mode is enabled, then the user must specify which memory bank/WSM to
suspend/resume by supplying the memory bank address. An erase operation on a low-order address
memory bank is suspended/resumed if the address input is within its valid address range (that is, A19 = 0).
An erase operation on a high-order address memory bank is suspended/resumed if the address input is
within its valid address range (that is, A19 = 1). While the selected memory bank/WSM is in the
erase-suspend state, data from any sector within the same memory bank (except for the sector that was
being erased) can be read. Similarly, data can be programmed to any address location of the memory bank
except for the sector that is being erase-suspended. Figure 7 shows the erase-suspend/erase-resume
flowchart.
22
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CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
automatic power-saving mode
PRODUCT PREVIEW
Substantial power savings are realized during periods when the array is not being read. During this time, the
device switches to the automatic power-saving (APS) mode. When the device switches to this mode, ICC is
typically reduced from 40 mA to 1 mA (Iout = 0 mA). The low level of power is maintained until another read
operation is initiated. In this mode, the I/O pins retain the data from the last memory address read until a new
address is read. There is no wake-up time associated with the APS mode; the device can be read with standard
access time from the APS mode. This mode is entered automatically if no control pins toggle within a 200-ns
time-out period. At least one transition on CE must occur after power up to activate this mode.
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
BUS
OPERATION
Start
Read Status-Register Bits
No
SB7 = 1
?
No
Erase
Suspend
?
EraseSuspend
Loop
Write erase
setup
Data = 20h
Sector Addr = Address
within
sector to
be erased
Write
Erase
Data = D0h
Sector Addr = Address
within
sector to
be erased
Read
Status-register data.
Single-operation mode:
Addr = don’t care
Concurrent-operations mode:
Addr = 0xxxxxh for
low-order address
memory bank
= 1xxxxxh for
high-order address
memory bank
Toggle OE or CE to
update status register
Standby
Check SB7
1 = Ready, 0 = Busy
Yes
PRODUCT PREVIEW
Yes
Full Status-Register
Check (optional)
See Note A
Block-Erase Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
SB3 = 0
?
COMMENTS
Write
Issue Erase-Setup Command
and Block Address
Issue Block-Erase-Confirm
Command and
Block Address
COMMAND
Repeat for subsequent blocks.
Write FFh after the last block-erase operation to reset the
device to read-array mode
No
VPP Range Error
Yes
SB4 = 1,
SB5 = 1
?
No
Yes
SB5 = 0
?
No
Command Sequence
Error
BUS
OPERATION
COMMAND
COMMENTS
Standby
Check SB3
1 = Detect VPP low
(see Note B)
Standby
Check SB4 and SB5
1 = Sector-erase
error
Standby
Check SB5
1 = Sector-erase error
(see Note C)
Block-Erase Failed
Yes
Block-Erase Passed
NOTES: A. Full status-register check can be done after each block or after a sequence of blocks.
B. SB3 must be cleared before attempting additional program / erase operations.
C. SB5 is cleared only by the clear-status-register command in cases where multiple blocks are erased before full status is checked.
Figure 6. Automated Block-Erase Flowchart
24
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CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
Write
Issue Erase-Suspend
Command
COMMAND
Erase
suspend
Read Status-Register
Bits
SB7 = 1
?
No
Status-register data.
Single-operation mode:
Addr = don’t care
Concurrent-operations mode:
Addr = 0xxxxxh for
low-order address
memory bank
= 1xxxxxh for
high-order address
memory bank
Toggle OE or CE to
update status register
Standby
Check SB7
1 = Ready
Standby
Check SB6
1 = Suspended
No
Erase
Completed
Yes
Read or
Program?
Program
Data = B0h
Single-operation mode:
Addr = don’t care
Concurrent-operations mode:
Addr = 0xxxxxh for
low-order address
memory bank
= 1xxxxxh for
high-order address
memory bank
Read
Yes
SB6 = 1
?
COMMENTS
Read
Issue
Memory-Read
Command
Program Loop
See Note A
Write
No
Finished
Read or
Program
?
Erase
resume
Yes
Issue Erase-Resume
Command
Erase Continued
Data = D0h
Single-operation mode:
Addr = don’t care
Concurrent-operations mode:
Addr = 0xxxxxh for
low-order address
memory bank
= 1xxxxxh for
high-order address
memory bank
See Note B
NOTES: A. Refer to the programming flowchart for complete programming procedures.
B. Refer to block-erase flowchart for complete erasure procedure
Figure 7. Erase-Suspend /Resume Flowchart
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PRODUCT PREVIEW
BUS
OPERATION
Start
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
reset/deep power-down mode
Very low levels of power consumption can be attained by using a special pin, RP, to disable the internal device
circuitry. When RP is at a CMOS logic-low level of 0.0 V ± 0.2 V, a much lower ICC value or power is achievable.
This is important in portable applications where extended battery life is of major concern.
A recovery time is required when exiting from deep power-down mode. For a read-array operation, a minimum
of td(RP) is required before data is valid, and a minimum of trec(RPHZ) and trec(RPHW) in deep power-down mode
is required before data input to the CSM can be recognized. With RP at ground, both WSMs are reset and both
status registers are cleared, effectively eliminating accidental programming to memory banks during system
reset. After restoration of power, the device does not recognize any operation command until RP is returned
to a VIH or VHH level.
Should RP go low during a program or erase operation, the device powers down and, therefore, becomes
nonfunctional. Data being written or erased at that time becomes invalid or indeterminate, requiring that the
operation be performed again after power restoration.
PRODUCT PREVIEW
power supply detection
RP must be connected to the system reset / power good signal to ensure that proper synchronization is
maintained between the CPU and the flash memory operating modes. The default state after power up and exit
from deep power-down mode is the single-operation, read-array mode. RP also is used to indicate that the
power supply is stable so that the operating supply voltage can be established (2.7 V, 3.3 V, or 5 V). Figure 9
shows the proper power-up sequence. To reset the operating supply voltage, the device must be completely
powered off (VCC = 0 V) before the new supply voltage is detected.
26
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Supply voltage range, VPP (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V
Input voltage range: All inputs except A9, RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
RP, A9 (see Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V
Output voltage range (see Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
Operating free-air temperature range, TA , during read/erase/program: L suffix . . . . . . . . . . . . . . 0°C to 70°C
E suffix . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 6. All voltage values are with respect to VSS.
7. The voltage on any input can undershoot to – 2 V for periods less than 20 ns.
8. The voltage on any output can overshoot to 7 V for periods less than 20 ns.
PRODUCT PREVIEW
The TMS28F1600 allows memory reads to be performed using VCC = 2.7 V to 3.6 V for optimum power
consumption or VCC = 5 ± 10% for device performance. Erasing or programming the device can be
accomplished with VPP = 2.7 V – 12 V for maximum flexibility.
recommended operating conditions
VCC
Supply voltage
During program/read/erase suspend
VPP
Supply voltage
VIH
High level dc input voltage
High-level
VIL
Low level dc input voltage
Low-level
VLKO
VHH
VCC lock-out voltage from program/erase
RP unlock voltage
VPPLK
VPP lock-out voltage from program/erase
TA
Operating
O
erating free-air tem
temperature
erature during read/erase/
read/erase/program
rogram
MIN
NOM
MAX
3-V VCC range
2.7
3
3.6
5-V VCC range
4.5
5
5.5
During read only ( VPPL )
During program/erase suspend, VPP can have VCC as MIN
or NOM
TTL
0
6.5
2.7
12.6
2
CMOS
VCC + 0.5
VCC + 0.2
VCC – 0.2
– 0.5
TTL
CMOS
UNIT
0.8
VSS – 0.2
2
VSS + 0.2
V
V
V
V
V
11.4
12
13
V
1.5
V
L Suffix
0
70
°C
E Suffix
–40
85
°C
word/byte typical write and sector-erase duration for TMS28F1600T/B (see Notes 9 and 10)
3-V VCC
RANGE
PARAMETER
5-V VCC
RANGE
UNIT
128K sector-erase time
2
1
s
16K sector-erase time
0.5
0.3
s
128K sector byte-program time
1.3
1
s
128K sector word-program time
0.8
0.6
s
NOTES: 9. Excludes system-level overhead
10. Typical values shown are at TA = 25°C
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
electrical characteristics for TMS28F1600T/B over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
High level output voltage
High-level
VOL
VID
Low-level output voltage
VCC = VCCMIN, IOH = – 2.5 mA
VCC = VCCMIN, IOH = – 100 µA
VCC = VCCMIN, IOL = 5.8 mA
A9 selection code voltage
During read algorithm-selection mode
Input current (leakage), except for A9 when
A9 = VID (see Note 11)
VCC = VCCMAX,VI = 0 V to VCCMAX, RP = VHH
IID
IRP
A9 selection code current
A9 = VID
IO
Output current (leakage)
IPPS
VPP standby current (standby)
IPPL
VPP supply
y current ((reset / deep
power-down mode)
IPP1
VPP supply current (active read)
II
PRODUCT PREVIEW
TEST CONDITIONS
IPP2
IPP3
TTL
CMOS
VPP supplyy current (active
(
word-write))
(see Notes 12 and 13)
Programming in progress
0.45
V
12.6
V
±1
µA
500
µA
500
µA
±10
µA
10
10
5
5
50
50
5-V VPP range,
3-V VCC range
17
5-V VPP range,
5-V VCC range
15
12-V VPP range,
3-V VCC range
12
12-V VPP range,
5-V VCC range
10
5-V VPP range,
3-V VCC range
17
5-V VPP range,
5-V VCC range
15
12-V VPP range,
3-V VCC range
12-V VPP range,
5-V VCC range
NOTES: 11. DQ15/A–1 is tested for output leakage only.
12. Not 100% tested; characterization data available
13. All ac current values are RMS unless otherwise noted.
28
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11.4
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UNIT
V
VCC – 0.4
VCC = VCCMAX,VO = 0 V to VCCMAX
3-V VCC range
VPP ≤ VCC
5-V VCC range
3-V VCC range
RP = VSS ± 0.2
0 2 V,
V VPP ≤ VCC
5-V VCC range
3-V VCC range
VPP ≥ VCC
5-V VCC range
Programming in progress
MAX
2.4
RP boot-block unlock current
VPP supply
y current ((active byte-write)
y
)
(see Notes 12 and 13)
MIN
µA
µA
µA
mA
mA
12
10
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
electrical characteristics for TMS28F1600T/B over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
IPP4
IPP5
TEST CONDITIONS
VPP supply
y current ((sector-erase))
(see Notes 12 and 13)
VPP supply current
(erase / program-suspend)
program suspend)
(see Notes 12 and 13)
Sector erase in progress
Sector-erase
Erase / program suspended
TTL input level
TTL-input
ICCS
VCC supply
y current
(standby)
CMOS input level
CMOS-input
ICCL
VCC supply current (reset / deep power-down
mode)
TTL input level
TTL-input
ICC1
VCC supply
y current
(active read)
CMOS input level
CMOS-input
ICC2
VCC supplyy current (active
(
byte-write)
y
)
(see Notes 12, 13, and 14)
VCC = VCCMAX,,
CE = RP = VIH
MAX
15
5-V VPP range,
5-V VCC range
15
12-V VPP range,
3-V VCC range
10
12-V VPP range,
5-V VCC range
10
5-V VPP range,
3-V VCC range
50
5-V VPP range,
5-V VCC range
50
12-V VPP range,
3-V VCC range
50
12-V VPP range,
5-V VCC range
50
µA
1
5-V VCC range
1
3-V VCC range
80
5-V VCC range
100
8
3-V VCC range
25
CE = VIL, IOUT = 0 mA,
f = 10 MHz
5-V VCC range
35
CE = VIL, IOUT = 0 mA,
f = 5 MHz
3-V VCC range
25
CE = VIL, IOUT = 0 mA,
f = 10 MHz
5-V VCC range
35
5-V VPP range,
3-V VCC range
30
5-V VPP range,
5-V VCC range
35
VCC = VCCMAX,,
Programming in progress
UNIT
mA
3-V VCC range
RP = VSS ± 0.2 V; VCC = VCCMAX
CE = VIL, IOUT = 0 mA,
f = 5 MHz
MIN
5-V VPP range,
3-V VCC range
PRODUCT PREVIEW
PARAMETER
mA
µA
µA
mA
mA
12-V VPP range,
3-V VCC range
12-V VPP range,
5-V VCC range
mA
30
35
NOTES: 12. Not 100% tested; characterization data available
13. All ac current values are RMS unless otherwise noted.
14. These values are the current for one memory bank. If both memory banks are active, then the current for each bank should be added
together in order to calculate the total current for the chip. For example, if bank A is in the erase mode and bank B is in the read mode,
then ICC total = ICC4 + ICC1.
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
electrical characteristics for TMS28F1600T/B over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted) (continued)
PARAMETER
ICC3
PRODUCT PREVIEW
ICC4
ICC5
VCC supplyy current (active
word-write))
(
(see Notes 12, 13, and 14)
(
)
VCC supplyy current (sector-erase)
(see Notes 12, 13, and 14)
VCC supply
y current ((erase / program-suspend)
g
)
(see Notes 12, 13, and 14)
TEST CONDITIONS
VCC = VCCMAX,,
Programming in progress
VCC = VCCMAX,,
Sector-erase in progress
VCC = VCCMAX,CE = VIH,
Sector erase / program
Sector-erase
suspended
MIN
MAX
5-V VPP range,
3-V VCC range
30
5-V VPP range,
5-V VCC range
35
12-V VPP range,
3-V VCC range
30
12-V VPP range,
5-V VCC range
35
5-V VPP range,
3-V VCC range
30
5-V VPP range,
5-V VCC range
35
12-V VPP range,
3-V VCC range
30
12-V VPP range,
5-V VCC range
35
UNIT
mA
mA
3-V VCC range
4
5-V VCC range
4
mA
NOTES: 12. Not 100% tested; characterization data available
13. All ac current values are RMS unless otherwise noted.
14. These values are the current for one memory bank. If both memory banks are active, then the current for each bank should be added
together in order to calculate the total current for the chip. For example, if bank A is in the erase mode and bank B is in the read mode,
then ICC total = ICC4 + ICC1 .
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz, VI = 0 V
PARAMETER
Ci
Input capacitance
Co
Output capacitance
30
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TEST CONDITIONS
VO = 0 V
• HOUSTON, TEXAS 77251–1443
MIN
MAX
UNIT
8
pF
12
pF
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
power-up and reset switching characteristics for TMS28F1600T/B over recommended ranges of
supply voltage (commercial and extended temperature ranges)(see Notes 12 and 15)
’28F1600y-80
ALT.
SYMBOL
PARAMETER
3-V VCC
RANGE
MIN
’28F1600y-90
5-V VCC
RANGE
MAX
MIN
3-V VCC
RANGE
MAX
MIN
5-V VCC
RANGE
MAX
MIN
UNIT
MAX
tsu(VCC)
Setup time, RP low to VCC at
4.5 V MIN. (to VCC at 2.7 V MIN or
3.6 V MAX) (see Note 16)
tPL5V
tPL3V
ta(DV)
Access time, address valid to data
valid
tAVQV
90
80
100
90
ns
tsu(DV)
Setup time, RP high to data valid
tPHQV
800
450
800
450
ns
th(RP5)
Hold time, VCC at 4.5 V (MIN) to RP
high
t5VPH
2
2
2
2
µs
th(RP3)
Hold time, VCC at 2.7 V (MIN) to RP
high
t3VPH
2
2
2
2
µs
0
0
0
0
ns
PRODUCT PREVIEW
NOTES: 12. Not 100% tested; characterization data available
15. CE and OE are switched low after power up.
16. The power supply can switch low concurrently with RP going low.
PARAMETER MEASUREMENT INFORMATION
IOL
VIH
Output
Under
Test
VZ
VOH
VOL
VIL
VOLTAGE WAVEFORMS
CL
(see Note A)
IOH
NOTES: A. CL includes probe and fixture capacitance.
B. AC test conditions are driven at VIH and VIL. Timing measurements are made at VOH and VOL levels on both inputs and outputs.
Refer to Table 9 for values based on VCC operating range.
C. Each device should have a 0.1-mF ceramic capacitor connected to VCC and VSS as close as possible to the device pins.
Figure 8. Load Circuit and Voltage Waveforms
Table 9. AC Test Conditions
VCC RANGE
5 V ± 10%
IOL
2.1
IOH
–0.4
VZ†
1.5
VOL
0.8
VOH
2.0
VIL
0.45
VIH
2.4
CL
100
tf
tr
< 10
< 10
3.3 ± 0.3 V
0.5
–0.5
1.5
1.5
1.5
0.0
3.0
50
< 10
< 10
1.35
1.35
1.35
0.0
2.7
50
< 10
< 10
2.7 to 3.6 V
0.1
–0.1
† VZ is the measured value used to detect high impedance.
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
switching characteristics for TMS28F1600T/B over recommended ranges of supply voltage
(commercial and extended temperature ranges)
read operations
’28F1600y-80
PARAMETER
ALT.
SYMBOL
3-V VCC
RANGE
MIN
PRODUCT PREVIEW
ta(A)
Access time from A0 – A19
(see Note 17)
’28F1600y-90
5-V VCC
RANGE
MAX
MIN
3-V VCC
RANGE
MAX
MIN
5-V VCC
RANGE
MAX
MIN
UNIT
MAX
tAVQV
90
80
100
90
ns
90
80
100
90
ns
60
40
65
45
ns
90
80
100
90
ns
ta(E)
ta(G)
Access time from CE
tc(R)
Cycle time, read
tELQV
tGLQV
tAVAV
td(E)
Delay time, CE low to
low-impedance output
tELQX
0
0
0
0
ns
td(G)
Delay time, OE low to
low-impedance output
tGLQX
0
0
0
0
ns
tdis(E)
Disable time, CE to the
high-impedance output
tEHQZ
55
30
55
35
ns
tdis(G)
Disable time, OE to the
high-impedance output
tGHQZ
45
30
45
35
ns
th(D)
Hold time, DQ valid from A0 – A19,
CE, or OE, whichever occurs first
(see Note 17)
tAXQX
tsu(EB)
Setup time, BYTE from CE low
tELFL
tELFH
7
5
7
5
ns
td(RP)
Delay time, output time from RP high
tPHQV
800
450
800
450
ns
tdis(BL)
Disable time, BYTE low to
DQ8 – DQ15 in the high-impedance
state
tFLQZ
90
80
100
90
ns
tFHQV
90
80
100
90
ns
Access time from OE
ta(BH)
Access time from BYTE going high
NOTE 17: A–1 – A19 for byte-wide
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0
0
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0
0
ns
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
timing requirements for TMS28F1600T/B over recommended ranges of supply voltage
(commercial and extended temperature ranges)
write/erase operations — WE-controlled writes
ALT.
SYMBOL
3-V VCC
RANGE
MIN
tc( W )
Cycle time, write
MAX
’28F1600y-90
5-V VCC
RANGE
MIN
MAX
3-V VCC
RANGE
MIN
MAX
5-V VCC
RANGE
MIN
UNIT
MAX
tAVAV
90
80
100
90
ns
tc( W )OP
Cycle time, duration of
programming operation
tWHQV1
6
6
6
6
µs
tc( W )ERB
Cycle time, erase operation
(boot block)
tWHQV2
0.3
0.3
0.3
0.3
s
tc( W )ERP
Cycle time, erase operation
(parameter block)
tWHQV3
0.3
0.3
0.3
0.3
s
tc( W )ERM
Cycle time, erase operation
(main block)
tWHQV4
0.6
0.6
0.6
0.6
s
td(RPR)
th(A)
Delay time, boot-block relock
0
0
0
10
ns
Hold time, DQ valid
tPHBR
tWHAX
tWHDX
th(D)
th(E)
0
0
0
0
ns
Hold time, CE
tWHEH
0
0
0
0
ns
th( VPP)
Hold time, VPP from valid status
register bit
tQVVL
0
0
0
0
ns
th(RP)
Hold time, RP at VHH from valid
status register bit
tQVPH
0
0
0
0
ns
th(WP)
Hold time, WP from valid status
register bit
tWHPL
0
0
0
0
ns
tsu(WP)
Setup time, WP before write
operation
tELPH
90
50
90
50
ns
tsu(A)
Setup time, A0 – A19
(see Note 17)
tAVWH
90
50
90
50
ns
tsu(D)
Setup time, DQ
tDVWH
90
50
90
50
ns
tsu(E)
Setup time, CE before write
operation
tELWL
0
0
0
0
ns
tsu(RP)
Setup time, RP at VHH to WE
going high
tPHHWH
200
100
200
100
ns
tsu( VPP)1
Setup time, VPP to WE going
high
tVPWH
200
100
200
100
ns
tWLWH
tWLWL
90
50
90
50
ns
Pulse duration, WE high
20
30
20
30
ns
Recovery time, RP high to WE
going low
tPHWL
800
450
800
450
ns
tw( W )
tw( WH)
trec(RPHW)
Hold time, A0 – A19 (see Note 17)
Pulse duration, WE low
200
100
200
100
ns
PRODUCT PREVIEW
’28F1600y-80
NOTE 17: A–1 – A19 for byte-wide
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33
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
timing requirements for TMS28F1600T/B over recommended ranges of supply voltage
(commercial and extended temperature ranges) (continued)
write/erase operations — CE-controlled writes
’28F1600y-80
ALT.
SYMBOL
3-V VCC
RANGE
PRODUCT PREVIEW
MIN
tc( E )
Cycle time, write
MAX
’28F1600y-90
5-V VCC
RANGE
MIN
MAX
3-V VCC
RANGE
MIN
MAX
5-V VCC
RANGE
MIN
UNIT
MAX
tAVAV
90
80
100
90
ns
tc(E)OP
Cycle time, duration of
programming operation
tEHQV1
6
6
6
6
µs
tc(E)ERB
Cycle time, erase operation
(boot block)
tEHQV2
0.3
0.3
0.3
0.3
s
tc(E)ERP
Cycle time, erase operation
(parameter block)
tEHQV3
0.3
0.3
0.3
0.3
s
tc(E)ERM
Cycle time, erase operation
(main block)
tEHQV4
0.6
0.6
0.6
0.6
s
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th( W )
Hold time, DQ valid
tPHBR
tEHAX
200
100
200
100
ns
0
0
0
0
ns
0
0
0
0
ns
Hold time, WE
tEHDX
tEHWH
0
0
0
0
ns
th (VPP)
Hold time, VPP from valid
status-register bit
tQVVL
0
0
0
0
ns
th(RP)
Hold time, RP at VHH from valid
status-register bit
tQVPH
0
0
0
0
ns
th(WP)
Hold time, WP from valid status
register bit
tWHPL
0
0
0
0
ns
tsu(WP)
Setup time, WP before write
operation
tELPH
90
50
90
50
ns
90
50
90
50
ns
Setup time, DQ
tAVEH
tDVEH
90
50
90
50
ns
tsu( W )
Setup time, WE before write
operation
tWLEL
0
0
0
0
ns
tsu(RP)
Setup time, RP at VHH to CE going
high
tPHHEH
200
100
200
100
ns
tsu(A)
tsu(D)
Hold time, A0 – A19 (see Note 17)
Setup time, A0 – A19 (see Note 17)
tsu( VPP)2
tw(E)
Setup time, VPP to CE going high
tVPEH
tELEH
200
100
200
100
ns
Pulse duration, CE low
90
50
90
50
ns
tw( EH)
Pulse duration, CE high
tEHEL
20
30
20
30
ns
trec(RPHE)
Recovery time, RP high to CE
going low
tPHEL
800
450
800
450
ns
NOTE 17: A–1 – A19 for byte-wide
34
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PARAMETER MEASUREMENT INFORMATION
RP (P)
2.7 V
VCC (3 V, 5 V)†
2.4 V
0V
4.5 V
th(RP3)
tsu(VCC)
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
th(RP5)
Address (A)
Valid
Valid
ta(DV)
ta(DV)
Data (D)
Valid 2.7 – 3.6 V Outputs
tsu(DV)
† 3-V range indicates 2.7 V to 3.6 V maximum
Figure 9. Power-Up Timing and Reset Switching
Valid 5.0 Outputs
tsu(DV)
35
SMJS836 – JANUARY 1997
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
5.0 V
PRODUCT PREVIEW
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
tc(R)
A –1 – A19 (byte-wide)
A0 – A19 (word-wide)
Address Valid
ta(A)
CE
tdis(E)
ta(E)
OE
tdis(G)
ta(G)
WE
td(G)
th(D)
PRODUCT PREVIEW
td(E)
DQ0 – DQ7 (byte-wide)
DQ0 – DQ15 (word-wide)
VCC
Hi-Z
Hi-Z
td(RP)
RP
Figure 10. Read-Cycle Timing
36
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
Power Up
and
A –1 – A19 Standby
(byte-wide)
A0 – A19
(word-wide)
Write
Program-Setup
Command
Write Valid
Address or
Data
Automated
Byte / WordProgramming
Read StatusRegister Bits
Write
Read-Array
Command
(see Note A)
(see Note A)
tc(W)
tsu(A)
th(A)
CE
tsu(E)
th(E)
OE
tc( W )OP
PRODUCT PREVIEW
tw( WH )
WE
DQ0 – DQ7
(byte-wide)
DQ0 – DQ15
(word-wide)
tw( W )
tsu(D)
th(D)
Data
Valid SR
Hi-Z
Hi-Z
FFh
Hi-Z
40h or 10h
trec(RPHW)
tsu(RP)
th(RP)
RP
tsu(WP)
th(WP)
WP
th( VPP)
tsu( VPP)1
VPP
NOTE A: Single-operation mode:
Address = Don’t Care
Concurrent-operations mode: Address = 0xxxxxh for low-order address memory bank
= 1xxxxxh for high-order address memory bank
Figure 11. Write-Cycle Timing ( WE-Controlled Write)
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
Power Up
and
– A19 Standby
A –1
(byte-wide)
A0 – A19
(word-wide)
Write
Program-Setup
Command
Automated
Byte / WordProgramming
Write Valid
Address
And Data
tc( W )
Read Status
Register Bits
Write
Read-Array
Command
(see Note A)
(see Note A)
tsu(A)
th(A)
WE
tsu( W )
th( W )
OE
tc(E)OP
PRODUCT PREVIEW
tw(EH)
CE
DQ0 –
DQ7
(bytewide)
DQ0 –
DQ15
(wordwide)
tw(E)
tsu(D)
th(D)
Data
Valid SR
Hi-Z
Hi-Z
Hi-Z
40h or 10h
tsu(RP)
trec(RPHE)
th(RP)
RP
tsu(WP)
th(WP)
WP
tsu( VPP)2
VPP
NOTE A: Single-operation mode:
Address = Don’t Care
Concurrent-operations mode: Address = 0xxxxxh for low-order address memory bank
= 1xxxxxh for high-order address memory bank
Figure 12. Write-Cycle Timing (CE-Controlled Write)
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FFh
th( VPP)
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
Power
Up and
A –1 – A19 Standby
(byte-wide)
A0 – A19
(word-wide)
Write
Erase-Setup
Command
Write EraseConfirm
Command
Automated
Erase
tc( W )
Read StatusRegister Bits
Write
Read-Array
Command
(see Note A)
(see Note A)
tsu(A)
th(A)
CE
tsu(E)
th(E)
OE
tc( W )ERB
tc( W )ERP
tc( W )ERM
tw( WH)
DQ0 –
DQ7
(bytewide)
DQ0 –
DQ15
(wordwide)
tw( W )
tsu(D)
th(D)
Hi-Z
D0h
Valid SR
Hi-Z
20h
trec(RPHW)
PRODUCT PREVIEW
WE
FFh
Hi-Z
tsu(RP)
th(RP)
VHH
VIH
RP
tsu(WP)
th(WP)
WP
tsu( VPP)1
th( VPP)
VPPH
VPPL
VPP
NOTE A: Single-operation mode:
Address = Don’t Care
Concurrent-operations mode: Address = 0xxxxxh for low-order address memory bank
= 1xxxxxh for high-order address memory bank
Figure 13. Erase-Cycle Timing (WE-Controlled Write)
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
Power Up
and
A –1 – A19 Standby
(byte-wide)
A0 – A19
(word-wide)
Write
Erase-Setup
Command
Write EraseConfirm
Command
tc( W )
Automated
Erase
Read StatusRegister Bits
Write
Read-Array
Command
(see Note A)
(see Note A)
tsu(A)
th(A)
WE
tsu( W )
th( W )
OE
tc(E)ERB
tc(E)ERP
tc(E)ERM
PRODUCT PREVIEW
tw(EH)
CE
DQ0 – DQ7
(byte-wide)
DQ0 – DQ15
(word-wide)
tw(E)
tsu(D)
th(D)
Hi-Z
D0h
Valid SR
Hi-Z
20h
trec(RPHE)
Hi-Z
tsu(RP)
th(RP)
RP
tsu(WP)
th(WP)
WP
tsu( VPP)2
VPP
NOTE A: Single-operation mode:
Address = Don’t Care
Concurrent-operations mode: Address = 0xxxxxh for low-order address memory bank
= 1xxxxxh for high-order address memory bank
Figure 14. Erase-Cycle Timing (CE-Controlled Write)
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FFh
th( VPP)
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
A–1 – A19
(byte-wide)
A0 – A19
(word-wide)
Address Valid
tc( R )
ta(A)
CE
ta(E)
tdis(E)
PRODUCT PREVIEW
OE
tdis(G)
ta(G)
BYTE
th(D)
tsu(EB)
DQ0 – DQ7
Hi-Z
Hi-Z
Byte DQ0 – DQ7
td(G)
Word DQ0 – DQ7
td(E)
DQ8 – DQ14
Hi-Z
Hi-Z
ta(A)
tdis(BL)
Word DQ8 – DQ14
DQ15/A –1
Hi-Z
A –1 Input
Hi-Z
Word DQ15
Figure 15. BYTE Timing, Changing From Word-Wide to Byte-Wide Mode
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TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
A –1 – A19
(byte-wide)
A0 – A19
(word-wide)
Address Valid
tc( R )
ta(A)
CE
ta(E)
tdis(E)
PRODUCT PREVIEW
OE
tdis(G)
ta(G)
BYTE
th(D)
tsu(EB)
Byte DQ0 – DQ7
ta(BH)
DQ0 – DQ7
Hi-Z
Hi-Z
td(G)
Word DQ0 – DQ7
td(E)
DQ8 – DQ14
Hi-Z
Hi-Z
Word DQ8 – DQ14
Word DQ15
DQ15/A –1
A –1 Input
Hi-Z
Figure 16. BYTE Timing, Changing From Byte-Wide to Word-Wide Mode
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Hi-Z
TMS28F1600T, TMS28F1600B
16M-BIT (1M BY 16, 2M BY 8)
CONCURRENT OPERATIONS AUTO-SELECT BOOT-BLOCK FLASH MEMORY
SMJS836 – JANUARY 1997
MECHANICAL DATA
DCD (R-PDSO-G48)
PLASTIC DUAL SMALL-OUTLINE PACKAGE
1
48
0.020 (0,5)
0.476 (12,10)
0.469 (11,90)
0.012 (0,30)
0.004 (0,10)
0.008 (0,21) M
25
24
0.795 (20,20)
0.780 (19,80)
0.041 (1,05)
0.037 (0,95)
0.006 (0,15)
NOM
PRODUCT PREVIEW
0.728 (18,50)
0.720 (18,30)
0.047 (1,20) MAX
Seating Plane
0.028 (0,70)
0.020 (0,50)
0.004 (0,10)
0.010 (0,25) NOM
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
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Copyright  1998, Texas Instruments Incorporated
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