TI TMS28F800AXY

TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
D
D
D
D
D
D
D
D
D
D
Organization . . .
1 048 576 By 8 Bits
524 288 By 16 Bits
Array-Blocking Architecture
– Two 8K-Byte/4K-Word Parameter Blocks
– One 96K-Byte/48K-Word Main Block
– Seven 128K-Byte/64K-Word Main Blocks
– One 16K-Byte/8K-Word Protected Boot
Block
– Top or Bottom Boot Locations
All Inputs / Outputs TTL-Compatible
Maximum Access / Minimum Cycle Time
5-V VCC 3-V VCC
’28F008Axy70 70 ns
100 ns
’28F008Axy80 80 ns
120 ns
’28F800Axy70 70 ns
100 ns
’28F800Axy80 80 ns
120 ns
(See Table 1 for VCC/VPP Voltage
Configuration)
100 000- and 10 000-Program/ Erase Cycle
Versions
Three Temperature Ranges
– Commercial . . . 0°C to 70°C
– Extended . . . – 40°C to 85°C
– Automotive . . . – 40°C to 125°C
Embedded Program/Erase Algorithms
– Automated Byte Programming
– Automated Word Programming
– Automated Block Erase
– Erase Suspend/Erase Resume
Automatic Power-Saving Mode
JEDEC Standards Compatible
– Compatible With JEDEC Byte/Word
Pinouts
– Compatible With JEDEC EEPROM
Command Set
Fully Automated On-Chip Erase and
Byte / Word Program Operations
D
D
D
D
D
Package Options
– 44-Pin Plastic Small-Outline Package
(PSOP) (DBJ Suffix)
– 40-Pin Thin Small-Outline Package
(TSOP) (DCD Suffix)
– 48-Pin TSOP (DCD Suffix)
– 48-Ball Micro Ball Grid Array
(µBGAt) available
Low Power Dissipation ( VCC = 5.5 V )
– Active Write . . . 330 mW ( Byte Write)
– Active Read . . . 220 mW ( Byte Read)
– Active Write . . . 330 mW ( Word Write)
– Active Read . . . 275 mW ( Word Read)
– Block Erase . . . 330 mW
– Standby . . . 0.55 mW (CMOS-Input
Levels)
– Deep Power-Down Mode . . . 0.044 mW
Write-Protection for Boot Block
Industry Standard Command-State Machine
(CSM)
– Erase Suspend/Resume
– Algorithm-Selection Identifier
Flexible VPP/Supply Voltage Combination
PIN NOMENCLATURE
A0 – A18
A0 – A19
BYTE
DQ0 – DQ14
DQ15/A –1
CE
OE
NC
RP
VCC
VPP
VSS
WE
WP
Address Inputs
Address Inputs (for 40-pin TSOP only)
Byte Enable
Data In / Out
Data In / Out (word-wide mode),
Low-Order Address (byte-wide mode)
Chip Enable
Output Enable
No Internal Connection
Reset / Deep Power Down
Power Supply
Power Supply for Program / Erase
Ground
Write Enable
Write Protect (for 40-pin and 48-pin
TSOP only)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
µBGA is a trademark of Tessera, Inc.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
programming operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device symbol nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
logic symbol for TMS28F008Axy 40-pin package . . . . . . . . . . . 6
automatic power-saving mode . . . . . . . . . . . . . . . . . . . . . . .
logic symbol for TMS28F800Axy 44-pin package . . . . . . . . . . . 7
reset / deep power-down mode . . . . . . . . . . . . . . . . . . . . . .
logic symbol for TMS28F800Axy 48-pin package . . . . . . . . . . . 8
absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
recommended operating conditions . . . . . . . . . . . . . . . . . . . . .
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
word/byte typical write and block-erase performance . . . . . .
block memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
boot-block data protection . . . . . . . . . . . . . . . . . . . . . . . . . . 12
power-up and reset switching characteristics for
parameter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TMS28F008ASy or ’AEy and
main block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TMS28F800ASy or ’AEy . . . . . . . . . . . . . . . . . . . . . . . . . .
data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
power-up and reset switching characteristics for
command-state machine (CSM) . . . . . . . . . . . . . . . . . . . . . 13
TMS28F008AVy or ’ALy and
TMS28F800AVy or ’ALy . . . . . . . . . . . . . . . . . . . . . . . . . . .
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
power-up and reset switching characteristics for
command definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TMS28F008AZy and TMS28F800AZy . . . . . . . . . . . . . .
status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . .
byte-wide or word-wide mode selection . . . . . . . . . . . . . . . 16
mechanical data DBJ (R-PDSO-G44) . . . . . . . . . . . . .
command-state machine (CSM) operations . . . . . . . . . . . 18
mechanical data DCD (R-PDSO-G**) . . . . . . . . . . . . . .
clear status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
18
19
19
20
20
25
27
27
28
30
34
37
40
48
49
description
The TMS28F800Axy is a 8 388 608-bit, boot-block flash memory that can be electrically block-erased and
reprogrammed. The TMS28F800Axy is organized in a blocked architecture consisting of:
D
D
D
D
One 16K-byte/8K-word protected boot block
Two 8K-byte/4K-word parameter blocks
One 96K-byte/48K-word main block
Seven 128K-byte/64K-word main blocks
The device can be ordered in four different voltage configurations (see Table 1). Operation as a 1024K-byte
(8-bit) or a 512K-word (16-bit) organization is user-definable.
Embedded program and block-erase functions are fully automated by the on-chip write-state machine (WSM),
simplifying these operations and relieving the system microcontroller of these secondary tasks. WSM status
can be monitored by an on-chip status register to determine progress of program/erase tasks. The device
features user-selectable block erasure.
The TMS28F800AEy configuration allows the user to perform memory reads using 2.7–3.6-V VCC and 5-V VCC
for optimum power consumption. Erasing or programming the device can be accomplished with VPP = 3 V,
5 V, or 12-V. This configuration is offered in the commercial temperature range (0°C to 70°C) and the extended
temperature range (–40°C to 85°C). Also, TMS28F800ASy offers VCC = 3 – 3.6 V and VCC = 5 V for optimum
power consumption. The TMS28F800ALy configuration allows performance of memory reads using
VCC = 3.0 – 3.6 V for optimum power consumption. The TMS28F800AVy configuration allows performance of
memory reads using VCC = 2.7–3.6 V for optimum power consumption.
The TMS28F800AZy configuration offers a 5-V memory read with a 3-V/5-V/12-V program and erase. This
configuration is offered in three temperature ranges: 0°C to 70°C, – 40°C to 85°C, – 40°C to 125°C.
The TMS28F800Axy is offered in a 44-pin plastic small-outline package (PSOP) and a 48-pin thin small-outline
package (TSOP) organized as 16-bit or 8-bit.
The TMS28F008 is functionally equivalent to the ’F800 except that it is organized only as a 8-bit configuration,
and it is offered only in a 40-pin TSOP.
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
TMS28F800Axy
44-PIN PSOP (DBJ)
(TOP VIEW)
VPP
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RP
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15/A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
TMS28F800Axy
48-PIN TSOP (DCD)
(TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RP
VPP
WP
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
A16
BYTE
VSS
DQ15 / A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
3
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
TMS28F008Axy
40-PIN TSOP (DCD)
( TOP VIEW )
A16
A15
A14
A13
A12
A11
A9
A8
WE
RP
VPP
WP
A18
A7
A6
A5
A4
A3
A2
A1
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
TMS28F800Axy
48-BALL µBGA
(TOP VIEW)
1
2
3
4
5
6
7
8
NC
A7
A4
A
A13 A11
A8
VPP WP
B
A14 A10 WE
RP
A18 A17
A5
A2
A15 A12
A9
NC
NC
A6
A3
A1
A16 D14
D5
D11
D2
D8
CE
A0
BYTE D15 D6
D12
D3
D9
D0
VSS
VCC D10
D1
OE
C
D
E
F
VSS D7
4
D13
POST OFFICE BOX 1443
D4
• HOUSTON, TEXAS 77251–1443
A17
VSS
NC
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE
GND
CE
A0
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
device symbol nomenclature
TMS28FXXXA
X
T
70
C
DBJ
L
Temperature Range Designator
L = Commercial (0°C to 70°C)
E = Extended (– 40°C to 85°C)
Q = Automotive (– 40°C to 125°C)
Package Designator
DBJ = Plastic Small-Outline Package (44-Pin)
DCD = Plastic Dual Small-Outline Package (48-Pin)
DCD = Plastic Dual Small-Outline Package (40-Pin)
Program/Erase Endurance
C = 100 000 Cycles
B = 10 000 Cycles
Speed Designator
70 = 70 ns
80 = 80 ns
10 = 100 ns
12 = 120 ns
Boot-Block Location Indicator
T = Top Location
B = Bottom Location
E = 2.7 – 3.6-V/5-V VCC and 3-V/5-V/12-V VPP
L = 3.0 – 3.6-V VCC and 3-V/5-V/12-V VPP
S = 3.0 – 3.6-V/5-V VCC and 3-V/5-V/12-V VPP
V = 2.7–3.6 VCC and 3-V/5-V/12-V VPP
Z = 4.5-V–5.5-V VCC and 3-V/5-V/12-V VPP
(See Note A)
008
800
NOTE A: VCC and VPP are nominal unless otherwise stated.
Table 1. VCC / VPP Voltage Configurations
DEVICE CONFIGURATION
TMS28F800AEy
READ VOLTAGE (VCC)
2.7 V to 3.6 V/5 V ± 10 %
PROGRAM/ERASE VOLTAGE (VPP)
3 V/5 V ± 10% or 12 V
TMS28F800AZy
5 V ± 10 %
TMS28F008AEy
2.7 V to 3.6 V/5 V ± 10 %
3 V/5 V ± 10% or 12 V
TMS28F008AZy
5 V ± 10 %
3 V/5 V ± 10% or 12 V
TMS28F800ASy
3.3 V/5 V ± 10 %
TMS28F008ASy
3.3 V/5 V ± 10 %
TMS28F800AVy
2.7 V to 3.6 V
TMS28F008AVy
2.7 V to 3.6 V
TMS28F800ALy
3.3 V ± 10 %
TMS28F008ALy
3.3 V± 10 %
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
" 5%
3 V/5 V ± 10% or 12 V ± 5 %
" 5%
" 5%
3 V/5 V ± 10% or 12 V " 5%
3 V/5 V ± 10% or 12 V " 5%
3 V/5 V ± 10% or 12 V " 5%
3 V/5 V ± 10% or 12 V " 5%
3 V/5 V ± 10% or 12 V " 5%
3 V/5 V ± 10% or 12 V " 5%
5
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
logic symbol for the TMS28F008Axy 40-pin package†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
RP
WP
CE
OE
WE
21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
10
12
22
24
9
0
A
0
1048575
19
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
FLASH
MEMORY
1048576 × 8
A, Z4
25
26
27
28
32
33
34
35
† This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DCD package.
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
logic symbol for TMS28F800Axy 44-pin package†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
RP
BYTE
CE
OE
WE
11
10
9
8
7
6
5
4
42
41
40
39
38
37
36
35
34
3
2
44
33
12
14
43
0
A
0
524 287
18
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1
FLASH
MEMORY
524288 × 16
A, Z4
15
17
19
21
24
26
28
30
16
18
20
22
25
27
29
31
† This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DBJ package.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
logic symbol for TMS28F800Axy 48-pin package†
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
RP
BYTE
WP
CE
OE
WE
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
0
A
0
524 287
18
12
47
14
26
28
11
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15 / A-1
FLASH
MEMORY
524288 × 16
A, Z4
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
† This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DCD package.
8
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
functional block diagram
DQ8 – DQ15/A –1
DQ0 – DQ7
8
8
8
DQ15/A –1
Input Buffer
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
Data
Register
BYTE
I/O Logic
Identification
Register
Output
Multiplexer
Command
State
Machine
Status
Register
A0 – 19
A18
Input
Buffer
PowerReduction
Control
CE
WE
OE
Data
Comparator
Write
State
Machine
RP
WP
Program/
Erase
Voltage
Switch
VPP
Address
Latch
Y Decoder
Address
Counter
X Decoder
Y Gating / Sensing
16K8KByte
Byte
Boot Para.
Block Block
8KByte
Para.
Block
POST OFFICE BOX 1443
96KByte
Main
Block
128KByte
Main
Block
128KByte
Main
Block
• HOUSTON, TEXAS 77251–1443
128KByte
Main
Block
128KByte
Main
Block
128KByte
Main
Block
128KByte
Main
Block
128KByte
Main
Block
9
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
architecture
The TMS28F008Axy and TMS28F800Axy use a blocked architecture to allow independent erasure of selected
memory blocks. The block to be erased is selected by using any valid address within that block.
block memory maps (’28F800Axy 16-bit configuration)
The TMS28F800Axy is available with the block architecture mapped in either of two configurations: the boot
block located at the top or at the bottom of the memory array, as required by different microprocessors. The
TMS28F800AxB (bottom boot block) is mapped with the 8K-word boot block located at the low-order address
range (00000h to 01FFFh). The TMS28F800AxT (top boot block) is inverted with respect to the TMS28F800AxB
with the boot block located at the high-order address range (7E000h to 7FFFFh). Both of these address ranges
are for word-wide mode. Figure 1 and Figure 2 show the memory maps for these configurations.
block memory maps (’28F008Axy and ’28F800Axy 8-bit configuration)
The TMS28F008Axy and TMS28F800Axy are available with the block architecture mapped in either of two
configurations: the boot block located at the top (e.g., TMS28F008AxT) or at the bottom (e.g., TMS28F008AxB)
of the memory array, as required by different microprocessors. The ’28F008AxB and ’28F800AxB (8-bit) are
mapped with 16K-byte boot block located at the low-order address range (00000h to 03FFFh). The
TMS28F008AxT and TMS28F800AxT (8-bit) are inverted with respect to the TMS28F008AxB models with the
boot block located at the higher-order address range (FC000h to FFFFFh).
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
block memory maps (continued)
Address
Range 8-bit Configuration
FFFFFh
FC000h
FBFFFh
FA000h
F9FFFh
F8000h
F7FFFh
E0000h
DFFFFh
C0000h
BFFFFh
A0000h
9FFFFh
80000h
7FFFFh
60000h
5FFFFh
40000h
3FFFFh
20000h
1FFFFh
16-bit Configuration Address
Range
Boot Block
16K Addresses
Boot Block
8K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Main Block
96K Addresses
Main Block
48K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
00000h
7FFFFh
7E000h
7DFFFh
7D000h
7CFFFh
7C000h
7BFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
00000h
DQ15/A –1 Is LSB Address
A0 Is LSB Address
NOTE A: ’28F008Axy is offered in a 40-pin TSOP package, 8-bit configuration only, and A0 is the LSB address.
Figure 1. TMS28F008AxT and TMS28F800AxT ( Top Boot Block ) Memory Map
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AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
block memory maps (continued)
Address
Range
FFFFFh
E0000h
DFFFFh
C0000h
BFFFFh
A0000h
9FFFFh
80000h
7FFFFh
60000h
5FFFFh
40000h
3FFFFh
20000h
1FFFFh
08000h
7FFFh
06000h
5FFFh
04000h
3FFFh
00000h
8-bit Configuration
16-bit Configuration
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
128K Addresses
Main Block
64K Addresses
Main Block
96K Addresses
Main Block
48K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Parameter Block
8K Addresses
Parameter Block
4K Addresses
Boot Block
16K Addresses
Boot Block
8K Addresses
DQ15/A –1 Is LSB Address
Address
Range
7FFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
00000h
A0 Is LSB Address
NOTE A: ’28F008Axy is offered in a 40-pin TSOP package, 8-bit configuration only, and A0 is LSB adddress.
Figure 2. TMS28F008AxB and TMS28F800AxB (Bottom Boot Block ) Memory Map
boot-block data protection
The 16K-byte boot block can be used to store key system data that is seldom changed in normal operation. Data
in this block can be secured by using different combinations of the reset/deep power-down pin (RP), the write
protect pin (WP) and VPP supply levels. Table 2 provides a list of these combinations.
parameter block
Two parameter blocks of 8K bytes each can be used like a scratch pad to store frequently updated data.
Alternatively, the parameter blocks can be used for additional boot- or main-block data. If a parameter block is
used to store additional boot-block data, caution must be exercised because the parameter block does not have
the boot-block data-protection safety feature.
main block
Primary memory on the TMS28F800Axy is located in eight main blocks. Seven of the blocks have storage
capacity for 128K bytes and the eighth block has storage capacity for 96K bytes.
12
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data protection
Data is secured or unsecured by using different combinations of the reset/deep power-down pin (RP), the write
protect pin (WP) and VPP supply levels. See to Table 2 for a listing of these combinations.
There are two configurations to secure the entire memory against inadvertant alteration of data. The VPP supply
pin can be held below the VPP lock-out voltage level (VPPLK) or the RP can be pulled to a logic-low level. If RP
is held low, the device resets, which means it powers down and, therefore, cannot be read. Typically, this pin
is tied to the system reset for additional protection during system power up.
The boot-block sector has an additional security feature through the WP pin. When the RP pin is at a logic-high
level, the WP pin controls whether the boot-block sector is protected. When WP is held at the logic-low level,
the boot block is protected. When WP is held at the logic-high level, the boot block is unprotected along with
the rest of the other sectors. Alternatively, the entire memory can be unprotected by pulling the RP pin to
VHH (12 V).
Table 2. Data-Protection Combinations (see Note 1)
VPP
≤ VPPLK
RP
WP
All blocks locked
DATA PROTECTION PROVIDED
X
X
All blocks locked (reset)
≥ VPPLK
X
All blocks unlocked
≥ VPPLK
VIL
VHH
Only boot block locked
≥ VPPLK
All blocks unlocked
≥ VPPLK
VIH
VIH
VIL
VIH
X
NOTE 1: For TMS28F008AZy and TMS28F800AZy (12-V VPP) products, the WP pin is
disabled and can be left floating. To unlock blocks, RP must be at VHH.
command-state machine (CSM)
Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface
between the external microprocessor and the internal WSM. Table 1 lists the CSM codes and device modes,
and Table 4 lists the data for the bus cycle. When a program or erase command is issued to the CSM, the WSM
controls the internal sequences and the CSM responds only to status reads. After the WSM completes its task,
the WSM status bit (SB7) is set to a 1, allowing the CSM to respond to the full command set again.
operation
Device operations are selected by entering standard JEDEC 8-bit command codes with conventional
microprocessor timing into an on-chip CSM through I/O pins DQ0–DQ7. When the device is powered up,
internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation
requires that a command code be entered into the CSM. Table 1 lists the CSM codes for all modes of operation.
The on-chip status register allows the progress of various operations to be monitored. The status register is
interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data
on I/O pins DQ0–DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7.
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operation (continued)
Table 3. CSM Codes for Device-Mode Selection
COMMAND
CODE ON
DQ0–DQ7†
00h
10h
20h
40h
50h
70h
90h
B0h
D0h
FFh
DEVICE MODE
Invalid/Reserved
Alternate Program Setup
Block-Erase Setup
Program Setup
Clear Status Register
Read Status Register
Algorithm Selection
Erase-Suspend
Erase-Resume/Block-Erase Confirm
Read Array
† DQ0 is the least significant bit. DQ8–DQ15 can be any valid 2-state
level.
command definition
Once a specific command code has been entered, the WSM executes an internal algorithm generating the
necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and
data for each of the bus cycles.
Table 4. Command Definitions
FIRST BUS CYCLE
BUS
CYCLES
REQUIRED
OPERATION
Read Array
1
Write
Read Algorithm-Selection Code
3
Read Status Register
2
Clear Status Register
1
COMMAND
SECOND BUS CYCLE
DATA
INPUT
OPERATION
ADDRESS
DATA
IN/OUT
X
FFh
Read
X
Data Out
Write
X
90h
Read
A0
M/D
Write
X
70h
Read
X
SRB
Write
X
50h
40h or 10h
Write
PA
PD
ADDRESS
Read Operations
Program Mode
Program Setup / Program
(byte / word)
2
Write
PA
Erase Operations
Block-Erase Setup/
Block-Erase Confirm
2
Write
BEA
20h
Write
BEA
D0h
Erase Suspend/
Erase Resume
2
Write
X
B0h
Write
X
D0h
Legend:
BEA
M/D
PA
PD
SRB
X
14
Block-erase address. Any address selected within a block selects that block for erase.
Manufacturer-equivalent/ device-equivalent code
Address to be programmed
Data to be programmed at PA
Status-register data byte that can be found on DQ0 – DQ7
Don’t care
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status register
The status register can be used to determine whether the state of a program/erase operation is pending or
complete. The status register is monitored by writing a read-status command to the CSM and reading the
resulting status code on I/O pins DQ0–DQ7. This is valid for operations in either the byte-wide or word-wide
mode. When writing to the CSM in word-wide mode, the high-order I/O pins (DQ8–DQ15) can be set to any valid
2-state level. When reading the status bits during a word-wide read operation, the high-order I/O pins
(DQ8–DQ15) are set to 00h internally, so the user needs to interpret only the low-order I/O pins (D0–DQ7).
After a read-status command has been given, the data appearing on DQ0–DQ7 remains as status register data
until a new command is issued to the CSM. To return the device to other modes of operation, a new command
must be issued to the CSM.
Register data is updated on the falling edge of OE or CE. The latest falling edge of either of these two signals
updates the latch within a given read cycle. Latching the data prevents errors from occurring should the register
input change during a status-register read. To ensure that the status-register output contains updated status
data, CE or OE must be toggled for each subsequent status read.
The status register provides the internal state of the WSM to the external microprocessor. During periods when
the WSM is active, the status register can be polled to determine the WSM status. Table 5 defines the
status-register bits and their functions.
Table 5. Status-Register Bit Definitions and Functions
STATUS
BIT
FUNCTION
DATA
COMMENTS
1 = Readyy
0 = Busy
If SB7 = 0 (busy), the WSM has not completed an erase or
programming operation. If SB7 = 1 (ready), other polling operations
can be performed. Until this occurs, the other status bits are not
valid If the WSM status bit shows busy (0)
valid.
(0), the user must toggle
CE or OE periodically to determine when the WSM has completed
an operation (SB7 = 1) since SB7 is not updated automatically at
the completion of a WSM task.
Erase-suspend status
(ESS)
1 = Erase suspended
0 = Erase in progress or
completed
When an erase-suspend command is issued, the WSM halts
execution and sets the ESS bit high (SB6 = 1), indicating that the
erase operation has been suspended. The WSMS bit also is set
high (SB7 = 1), indicating that the erase-suspend operation has
been completed successfully. The ESS bit remains at a logic-high
level until an erase-resume command is input to the CSM
(code D0h ).
SB5
Erase status (ES)
1 = Block-erase error
0 = Block-erase good
SB5 = 0 indicates that a successful block erasure has occurred.
SB5 = 1 indicates that an erase error has occurred. In this case,
the WSM has completed the maximum allowed erase pulses
determined by the internal algorithm, but this was insufficient to
erase the device completely.
SB4
Program status (PS)
1 = Byte/word-program error
0 = Byte/word-program good
SB4 = 0 indicates successful programming has occurred at the
addressed block location. SB4 = 1 indicates that the WSM was
unable to program the addressed block location correctly.
SB3
VPP status (VPPS)
1 = Program abort:
VPP range error
0 = VPP good
SB3 provides information on the status of VPP during
programming. If VPP is lower than VPPL after a program or erase
command has been issued, SB3 is set to a 1, indicating that the
programming operation is aborted. If VPP is between VPPH and
VPPL, SB3 is not set.
SB2–
SB0
Reserved
SB7
SB6
Write-state-machine status
(WSMS)
These bits must be masked out when reading the status register.
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byte-wide or word-wide mode selection
The memory array is divided into two parts: an upper-half that outputs data through I/O pins DQ8–DQ15, and
a lower-half that outputs data through DQ0–DQ7. Device operation in either byte-wide or word-wide mode is
user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic-high level, the device
is in the word-wide mode and data is written to, or read from, I/O pins DQ0–DQ15. When BYTE is at a logic-low
level, the device is in the byte-wide mode and data is written to or read from I/O pins DQ0–DQ7. In the byte-wide
mode, I/O pins DQ8–DQ14 are placed in the high-impedance state and DQ15/A–1 becomes the low-order
address pin and selects either the upper- or lower-half of the array. Array data from the upper half (DQ8–DQ15)
and the lower half (DQ0–DQ7) are multiplexed to appear on DQ0–DQ7. Table 6 and Table 7 summarize
operations for word-wide mode and byte-wide mode, respectively. Table 8 summarizes the operation for
’28F008Axy.
Table 6. Operation Modes for Word-Wide Mode (BYTE = VIH) (’28F800Axy) (see Note 2)
MODE
WP
CE
OE
RP
WE
A9
A0
X
VIL
VIL
VIH
VIH
X
X
VPP
X
X
VIL
VIL
VIH
VIH
VID
VIL
X
Read
Algorithm-selection mode
DQ0–DQ15
Data out
Manufacturer-equivalent code
0089h
Device-equivalent code 889Ch
(top boot block)
X
VIL
VIL
VIH
VIH
VID
VIH
X
Output disable
X
VIH
VIH
VIH
X
X
X
Hi-Z
X
VIH
X
X
Standby
VIL
VIH
X
X
X
Hi-Z
Reset/deep power down
X
X
X
VIL
VIH or
VHH
X
X
X
X
Hi-Z
VIL or
VIH
Write (see Note 3)
VIL
VIH
VIL
X
X
Device-equivalent code 889Dh
(bottom boot block)
VPPLor
Data in
VPPH
Table 7. Operation Modes for Byte-Wide Mode (BYTE = VIL) (’28F800Axy) (see Note 2)
MODE
WP
CE
OE
RP
WE
A9
A0
Read lower byte
X
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
X
Read upper byte
X
X
VIL
VIL
VIH
VIH
VID
Algorithm-selection
g
mode
DQ15/A–1
VIL
DQ8–DQ14
X
VPP
X
DQ0–DQ7
Hi-Z
Data out
X
X
VIH
Hi-Z
Data out
VIL
X
X
Hi-Z
Manufacturer-equivalent
code 89h
Device-equivalent
q
code
9Ch (top boot block)
X
VIL
VIL
VIH
VIH
VID
VIH
X
X
Hi Z
Hi-Z
Output disable
X
VIH
X
VIH
VIH
VIH
X
X
X
X
Hi-Z
Hi-Z
X
VIL
VIH
X
Standby
X
X
X
X
Hi-Z
Hi-Z
Reset/deep power
down
X
X
X
VIL
X
X
X
X
X
Hi-Z
Hi-Z
Write (see Note 3)
VIL
or
VIH
VIL
VIH
VIH
or
VHH
VIL
X
X
VPPL
or
VPPH
X
Hi-Z
Data in
Device-equivalent code
9Dh (bottom boot block)
NOTES: 2. X = don’t care
3. When writing commands to the ’28F008Axy and the ’28F800Axy, VPP must be in the appropriate VPP voltage range (as shown in
the recommended operating conditions table for a specific product) for block-erase or program commands to be executed. Also,
depending on the combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for
a list of the combinations).
16
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SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
byte-wide or word-wide mode selection (continued)
Table 8. Operation Modes for Byte-Wide Mode (’28F008Axy) (see Note 2)
MODE
Read
WP
CE
OE
RP
WE
A9
A0
X
VIL
VIL
VIH
VIH
X
X
VPP
X
X
VIL
VIL
VIH
VIH
VID
VIL
X
Algorithm-selection mode
DQ0 – DQ7
Data out
Manufacturer-equivalent code
89h
Device-equivalent code 98
(top boot block)
X
VIL
VIL
VIH
VIH
VID
VIH
X
Output disable
X
VIH
X
VIH
VIH
VIH
X
X
X
Hi-Z
X
VIL
VIH
X
X
Standby
X
X
X
Hi-Z
X
VIL
VIH or
VHH
X
X
X
X
Hi-Z
Reset / deep power down
Write (see Note 3)
X
VIL or
VIH
VIL
VIH
VIL
X
X
Device-equivalent code 99
(bottom boot block)
VPPLor
Data in
VPPH
NOTES: 2. X = don’t care
3. When writing commands to the ’28F008Axy and the ’28F800Axy, VPP must be in the appropriate VPP voltage range (as shown in
the recommended operating conditions table for a specific product) for block-erase or program commands to be executed. Also,
depending on the combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for
a list of the combinations).
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SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
command-state machine (CSM) operations
The CSM decodes instructions for read, read algorithm-selection code, read-status register, clear-status
register, program, erase, erase-suspend, and erase-resume. The 8-bit command code is input to the device on
DQ0–DQ7 (see Table 1 for CSM codes). During a program or erase cycle, the CSM informs the WSM that a
program or erase cycle has been requested. During a program cycle, the WSM controls the program sequences
and the CSM responds only to status reads.
During an erase cycle, the CSM responds to status-read and erase-suspend commands. When the WSM has
completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full
command set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when VPP is within its correct voltage range.
For data protection, it is recommended that RP be held at a logic-low level during a CPU reset.
clear status register
The internal circuitry can set only the VPP status bit (SB3), the program status bit (SB4), and the erase status
bit (SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor
to clear these status bits and synchronize to internal operations. When the status bits are cleared, the device
returns to the read-array mode.
read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
D
read array
The array level is read by entering the command code FFh on DQ0–DQ7. Control pins CE and OE must be
at a logic-low level (VIL) and WE and RP must be at a logic-high level (VIH) to read data from the array. Data is
available on DQ0–DQ15 (word-wide mode) or DQ0–DQ7 (byte-wide mode). Any valid address within any of
the blocks selects that block and allows data to be read from the block.
D
read algorithm-selection code
Algorithm-selection codes are read by entering command code 90h on DQ0–DQ7. Two bus cycles are
required for this operation: the first to enter the command code and a second to read the device-equivalent
code. Control pins CE and OE must be at a logic-low level (VIL) and WE and RP must be at a logic-high level
(VIH). Two identifier bytes are accessed by toggling A0. The manufacturer-equivalent code is obtained on
DQ0–DQ7 with A0 at a logic-low level (VIL). The device-equivalent code is obtained when A0 is set to a
logic-high level (VIH). Alternatively, the manufacturer- and device-equivalent codes can be read by applying
VID (nominally 12 V) to A9 and selecting the desired code by toggling A0 high or low. All other addresses are
“don’t cares” (see Table 4, Table 6, and Table 7).
D
read status register
The status register is read by entering the command code 70h on DQ0–DQ7. Control pins CE and OE must
be at a logic-low level (VIL) and WE and RP must be at a logic-high level (VIH). Two bus cycles are required
for this operation: one to enter the command code and a second to read the status register. In a given read
cycle, status register contents are updated on the falling edge of CE or OE, whichever occurs last within the
cycle.
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programming operations
There are two CSM commands for programming: program setup and alternate program setup
(see Table 1). After the desired command code is entered, the WSM takes over and correctly sequences the
device to complete the program operation. During this time, the CSM responds only to status reads until the
program operation has been completed, after which all commands to the CSM become valid again. Once a
program command has been issued, the WSM normally cannot be interrupted until the program algorithm is
completed (see Figure 3 and Figure 4).
Taking RP to VIL during programming aborts the program operation. During programming, VPP must remain in
the appropriate VPP voltage range as shown in the recommended operating conditions table. Different
combinations of RP, WP, and VPP pin voltage levels ensure that data in certain blocks are secured, and,
therefore, cannot be programmed (see Table 2 for a list of combinations). Only 0s are written and compared
during a program operation. If 1s are programmed, the memory cell contents do not change and no error occurs.
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads.
When the WSM status bit (SB7) is set to a logic-high level, signifying the nonprogram operation is terminated,
all commands to the CSM become valid again.
erase operations
There are two erase operations that can be performed by the TMS28F008Axy and TMS28F800Axy devices:
block erase and erase suspend/erase resume. An erase operation must be used to initialize all bits in an array
block to 1s. After block-erase confirm is issued, the CSM responds only to status reads or erase-suspend
commands until the WSM completes its task.
D
block erasure
Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is
accomplished only by blocks; data at single address locations within the array cannot be erased individually.
The block to be erased is selected by using any valid address within that block. Note that different
combinations of RP, WP and VPP pin voltage levels ensure that data in certain blocks are secure and,
therefore, cannot be erased (see Table 2 for a list of combinations). Block erasure is initiated by a command
sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (D0h) (see Figure 5). A
two-command erase sequence protects against accidental erasure of memory contents.
Erase-setup and erase-confirm commands are latched on the rising edge of CE or WE, whichever occurs
first. Block addresses are latched during the block-erase-confirm command on the rising edge of CE or WE
(see Figure 15 and Figure 16). When the block-erase-confirm command is complete, the WSM
automatically executes a sequence of events to complete the block erasure. During this sequence, the block
is programmed with logic 0s, data is verified, all bits in the block are erased, and finally, verification is
performed to ensure that all bits are erased correctly. Monitoring of the erase operation is possible through
the status register (see “read status register” in the subsection “read operations”).
D
erase suspend/erase resume
During the execution of an erase operation, the erase-suspend command (B0h) can be entered to direct the
WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to
respond only to the read-array, read-status-register, and erase-resume commands. During the
erase-suspend operation, array data should be read from a block other than the one being erased. To
resume the erase operation, an erase-resume command (D0h) must be issued to cause the CSM to clear
the suspend state previously set (see Figure 5 and Figure 6).
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automatic power-saving mode
Substantial power savings are realized during periods when the array is not being read. During this time, the
device switches to the automatic power-saving (APS) mode. When the device switches to this mode, ICC
reduces by an order of magnitude. For example, for a 5 V port, ICC typically reduces from 40 mA to 1 mA. The
low level of power is maintained until another read operation is initiated. In this mode, the I/O pins retain the data
from the last memory address read until a new address is read. This mode is entered automatically if no new
address is accessed within a 200-ns time-out period.
reset/deep power-down mode
Very low levels of power consumption can be attained by using a special pin, RP, to disable internal device
circuitry. When RP is at a CMOS logic-low level of 0.0 V ± 0.2 V, a much lower ICC value or power is achievable.
This is important in portable applications where extended battery life is of major concern.
A recovery time is required when exiting from deep power-down mode. For a read-array operation, a
minimum of td(RP) is required before data is valid, and a minimum of trec(RPHE) and trec(RPHW) in deep
power-down mode is required before data input to the CSM can be recognized. With RP at ground, the WSM
is reset and the status register is cleared, effectively eliminating accidental programming to the array during
system reset. After restoration of power, the device does not recognize any operation command until RP is
returned to a VIH or VHH level.
Should RP go low during a program or erase operation, the device powers down and, therefore, becomes
nonfunctional. Data being written or erased at that time becomes invalid or indeterminate, requiring that the
operation be performed again after power restoration.
20
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
Start
BUS
OPERATION
Issue Program-Setup
Command and Byte Address
Issue Byte
Address/Data
COMMAND
Write
Write
program
setup
Data = 40h or 10h
Addr = Address of
byte to be
programmed
Write
Write data
Data = Byte to be
programmed
Addr = Address of
byte to be
programmed
Read Status-Register
Bits
SB7 = 1
?
Read
Status-register data.
Toggle OE or CE to update status register
Standby
Check SB7
1 = Ready, 0 = Busy
No
Yes
Full Status-Register
Check (optional)
COMMENTS
Repeat for subsequent bytes.
Write FFh after the last byte-programming operation to
reset the device to read-array mode
See Note A
Byte-Program Completed
FULL STATUS-REGISTER-CHECK FLOW
Read
Status-Register Bits
SB3 = 0
?
No
BUS
OPERATION
VPP Range Error
Standby
Byte-Program
Failed
Standby
COMMAND
Yes
SB4 = 0
?
No
COMMENTS
Check SB3
1 = Detect VPP low
(see Note B)
Check SB4
1 = Byte-program error
(see Note C)
Yes
Byte-Program Passed
NOTES: A. Full status-register check can be done after each byte or after a sequence of bytes.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 3. Automated Byte-Programming Flow Chart
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
21
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
BUS
OPERATION
Start
Read Status-Register
Bits
No
SB7 = 1
?
COMMENTS
Write
Write
program
setup
Data = 40h or 10h
Addr = Address of
word to be
programmed
Write
Write data
Data = Word to be
programmed
Addr = Address of
word to be
programmed
Issue Program-Setup
Command and Word
Address
Issue Word
Address/Data
COMMAND
Read
Status-register data.
Toggle OE or CE to
update status register.
Standby
Check SB7
1 = Ready, 0 = Busy
Repeat for subsequent words.
Write FFh after the last word-programming operation to
reset the device to read-array mode.
Yes
Full Status-Register
Check (optional)
See Note A
Word-Program
Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
BUS
OPERATION
SB3 = 0
?
No
VPP Range Error
Yes
SB4 = 0
?
No
COMMAND
COMMENTS
Standby
Check SB3
1 = Detect VPP low
(see Note B)
Standby
Check SB4
1 = Word-program
error
(see Note C)
Word-Program
Failed
Yes
Word-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 4. Automated Word-Programming Flow Chart
22
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
BUS
OPERATION
Start
COMMAND
COMMENTS
Write
Write erase
setup
Data = 20h
Block Addr = Address
within
block to
be
erased
Write
Erase
Data = D0h
Block Addr = Address
within
block to
be
erased
Issue Erase-Setup Command
and Block Address
Issue Block-Erase-Confirm
Command and
Block Address
Read Status-Register Bits
No
SB7 = 1
?
No
Erase
Suspend
?
EraseSuspend
Loop
Yes
Read
Status-register data.
Toggle OE or CE to
update status register
Standby
Check SB7
1 = Ready, 0 = Busy
Yes
Full Status-Register
Check (optional)
See Note A
Repeat for subsequent blocks.
Write FFh after the last block-erase operation to reset the
device to read-array mode
Block-Erase Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
SB3 = 0
?
BUS
OPERATION
No
COMMAND
COMMENTS
Standby
Check SB3
1 = Detect VPP low
(see Note B)
Command Sequence
Error
Standby
Check SB4 and SB5
1 = Block-erase
error
Block-Erase Failed
Standby
Check SB5
1 = Block-erase error
(see Note C)
VPP Range Error
Yes
SB4 = 1,
SB5 = 1
?
No
Yes
SB5 = 0
?
No
Yes
Block-Erase Passed
NOTES: A. Full status-register check can be done after each block or after a sequence of blocks.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB5 is cleared only by the clear-status-register command in cases where multiple blocks are erased before full status is checked.
Figure 5. Automated Block-Erase Flow Chart
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
23
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
BUS
OPERATION
Start
Write
Issue Erase-Suspend
Command
Read Status-Register
Bits
No
SB7 = 1
?
Yes
COMMAND
Erase
suspend
Erase
Completed
Yes
Status-register data.
Toggle OE or CE to
update status register
Standby
Check SB7
1 = Ready
Standby
Check SB6
1 = Suspended
Write
Issue Memory-Read
Command
Issue Erase-Resume
Command
Erase Continued
Read
memory
Read
No
Finished
Reading
?
Yes
Write
Erase
resume
See Note A
Figure 6. Erase-Suspend/Erase-Resume Flow Chart
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Data = FFh
Read data from block
other than that being
erased.
NOTE A: See block-erase flow chart for complete erasure procedure
24
Data = B0h
Read
No
SB6 = 1
?
COMMENTS
Data = D0h
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Supply voltage range, VPP (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V
Input voltage range: All inputs except A9, RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
RP, A9 (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V
Output voltage range (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 1 V
Ambient temperature range, TA, during read/erase/program:
L suffix . . . . . . . . . . . . . . 0°C to 70°C
E suffix . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 4. All voltage values are with respect to VSS.
5. The voltage on any input or output can undershoot to – 2 V for periods of less than 20 ns. See Figure 7.
6. The voltage on any input or output can overshoot to 2 V for periods of less than 20 ns. See Figure 8.
5 ns
5 ns
+0.8 V
–0.5 V
VCC–2.0 V
20 ns
Figure 7. Maximum Negative Overshoot Waveform
20 ns
VCC + 2.0 V
VCC + 0.5 V
2.0 V
5 ns
5 ns
Figure 8. Maximum Positive Overshoot Waveform
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
25
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
PARAMETER MEASUREMENT INFORMATION
IOL
0.1 mA
Output
Under
Test
1.35 V
CL
(see Note A)
IOH
–0.1 mA
2.7 V
1.35 V
1.35 V
0.0 V
VOLTAGE WAVEFORMS FOR -100, -120
Conditions: VIH = 2.7 V
VIL = 0 V
CL = 30 pF
Measurements taken at: 1.35 V for logic high
1.35 V for logic low
Input rise and fall = <5 ns
NOTES: A. CL includes probe and fixture capacitance.
B. Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS, as closely as possible to the device pins.
Figure 9. 3-V Testing Load Circuit and Voltage Waveform
IOL
0.5 mA
Output
Under
Test
1.40 V
CL
(see Note A)
IOH
–0.5 mA
2.4 V
0.45 V
2V
0.8 V
VOLTAGE WAVEFORMS FOR -70, -80
Conditions: VIH = 2.45 V
VIL = 0.45 V
CL = 100 pF
Measurements taken at: 2.0 V for logic high
0.8 V for logic low
Input rise and fall = <20 ns
NOTES: A. CL includes probe and fixture capacitance.
B. Each device should have a 0.1-µF ceramic capacitor connected between VCC and VSS, as closely as possible to the device pins.
Figure 10. 5-V Testing Load Circuit and Voltage Waveform
26
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED MARCH 1998
recommended operating conditions
3 VCC
VCC
Supply voltage
During write/read/erase/erase suspend
3.3 VCC
5 VCC
During read only (VPPL)
VPP
Supply voltage
VIL
Low level dc input voltage
Low-level
VLKO
VHH
VCC lock-out voltage from write/erase (see Note 7)
RP unlock voltage
VPPLK
VPP lock-out voltage from write/erase (see Note 7)
TA
Ambient tem
temperature
erature during read/erase/
read/erase/program:
rogram:
MAX
3
3.6
3
3.3
3.6
4.5
5
5.5
6.5
3 VPP
3.0
3.3
3.6
5 VPP
4.5
5
5.5
12 VPP
11.4
12
TTL
High level dc input voltage
High-level
NOM
2.7
0
During
D
i write/erase/erase
it /
/
suspend,
d VPP can have
h
VCC
as MIN or NOM
VIH
MIN
CMOS
TTL
CMOS
2
0.8
VSS – 0.2
1.2
V
V
V
12.6
VCC + 0.5
VCC + 0.2
VCC – 0.2
– 0.5
UNIT
VSS + 0.2
V
V
V
11.4
13
V
0
12
1.5
V
L Suffix
0
70
°C
E Suffix
–40
85
°C
NOTE 7: Typical values shown are at TA = 25°C.
word/byte typical write and block-erase performance (see Notes 7 and 8)
MIN
TYP
MAX
UNIT
Main-block erase time
2.4
s
Main-block byte-program time
1.7
s
Main-block word-program time
1.1
s
0.84
s
Parameter/ boot-block erase time
NOTES: 7. Typical values shown are at TA = 25°C.
8. Excludes system-level overhead (all times in seconds)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
27
TEST CONDITIONS
TMS28F800AVy
y
TMS28F008AVy
TMS28F800AZy
y
TMS28F008AZy
3 V/3.3 V
5V
MIN
VOH
g
g
High-level
output voltage
TTL
VCC = VCC MIN, IOH = – 2.5 mA (5 V)
VCC = VCC MIN, IOH = –2 mA (3 V)
Low-level output voltage
VCC = VCC MIN, IOH = – 100 µA
VCC = VCC MIN, IOL = 5.8 mA
A9 selection-code voltage
During read algorithm-selection mode
Input current (leakage), except for A9 when
A9 = VID (see Note 9)
VCC = VCC MAX, VI = 0 V to VCC MAX,
IID
IRP
A9 selection-code current
IO
IPPR
CMOS
VOL
VID
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
II
IPPS
IPPL
MAX
2.4
VCC – 0.4
MIN
MAX
2.4
0.55 VCC
VCC – 0.4
V
0.55 VCC
0.45
V
12.6
V
±1
±1
µA
A9 = VID
500
500
µA
RP boot-block unlock current
RP = VHH
500
500
µA
Output current (leakage)
VCC = VCC MAX, VO = 0 V to VCC MAX
VPP ≥ VPPH2 (at 12 V)
±10
±10
µA
200
200
µA
10
10
µA
5
5
µA
200
200
µA
VPP read current
VPP standby current (standby)
VPP ≤ VCC
RP = VSS ± 0.2 V, VPP ≤ VCC
0.45
UNIT
11.4
12.6
11.4
IPP1
VPP supply current (reset / deep power-down mode)
VPP supply current (active read)
IPP2
VPP supply current (active byte-write)
(see Notes 10 and 11)
Programming in progress
30
30
mA
IPP3
VPP supply current (active word-write)
(see Notes 10 and 11)
Programming in progress
30
30
mA
IPP4
VPP supply current (block-erase)
(see Notes 10 and 11)
Block-erase in progress
30
30
mA
IPP5
VPP supply current (erase-suspend)
(see Notes 10 and 11)
Block-erase suspended
200
200
µA
TTL-input level
VCC = VCC MAX
1.5
2
mA
ICCS
VCC supply current (standby)
CMOS-input
level
VCC = VCC MAX, CE = RP = VCC ± 0.2 V
110
130
µA
ICCL
VCC supply current (reset / deep power
power-down
down mode)
0°C to 70°C
8
8
– 40°C to 85°C
8
8
VPP ≥ VCC
RP = VSS ± 0.2
02V
NOTES: 9. DQ15/A–1 is tested for output leakage only.
10. Characterization data available
11. All ac current values are RMS unless otherwise noted.
CE = RP = VIH
µA
Template Release Date: 7–11–94
PARAMETER
TMS28F008Axy, TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
TMS28F800AEy
y AND TMS28008AEy
y
TMS28F800ASyAND TMS28F008ASy
SMJS851A – NOVEMBER 1997 – REVVISED FEBRUARY 1998
28
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted)
(continued)
TMS28F800AEy
y AND TMS28008AEy
y
TMS28F800ASy AND TMS28F008ASy
PARAMETER
TEST CONDITIONS
TMS28F800AVy
y
TMS28F008AVy
TMS28F800AZy
y
TMS28F008AZy
3 V/3.3 V
5V
MIN
ICC1
MAX
MIN
UNIT
MAX
TTL-input level
VCC MAX, CE = VIL,
IOUT = 0 mA,
OE = VIH = 5 MHz (3 V) 10 MHz (5 V)
30
30
mA
CMOS-input level
VCC MAX, CE = GND,
f = 5 MHz (3 V)
IOUT = 0 mA, OE =VCC
10 MHz (5 V)
30
30
mA
VCC supply current (active read)
VCC supply current (active byte-write)
(see Notes 9, 10, and 11)
VCC = VCC MAX,
Programming in progress
60
60
mA
ICC3
VCC supply current (active word-write)
(see Notes 9, 10, and 11)
VCC = VCC MAX,
Programming in progress
60
60
mA
ICC4
VCC supply current (block-erase)
(see Notes 9, 10, and 11)
VCC = VCC MAX,
Block-erase in progress
60
60
mA
ICC5
VCC supply current (erase-suspend)
(see Notes 9 and 10)
VCC = VCC MAX,
Block-erase suspended
8
8
mA
NOTES: 9. DQ15/A–1 is tested for output leakage only.
10. Characterization data available
11. All ac current values are RMS unless otherwise noted.
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
29
TMS28F008Axy, TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ICC2
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
power-up and reset switching characteristics for TMS28F008ASy or ’AEy and TMS28F800ASy or
’AEy over recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 10, 11, and 12)
PARAMETER
ALT.
SYMBOL
’28F008AEy 70
’28F800AEy 70
’28F008ASy 70
’28F800ASy 70
3 V/3.3-V VCC
RANGE
MIN
MAX
’28F008AEy 80
’28F800AEy 80
’28F008ASy 80
’28F800ASy 80
5-V VCC
RANGE
MIN
3 V/3.3-V VCC
RANGE
MAX
MIN
MAX
UNIT
5-V VCC
RANGE
MIN
MAX
tsu(VCC)
Setup time, RP low to VCC at
3 V MIN or 3.6 V MAX)
(see Note 13)
tPL5V
tPL3V
ta(DV)
Address valid to data valid
tAVQV
100
70
120
80
ns
tsu(DV)
Setup time, RP high to data
valid
tPHQV
800
450
800
450
ns
th(RP5)
Hold time, VCC at 4.5 V (MIN)
to RP high
t5VPH
2
2
2
2
µs
th(RP3)
Hold time, VCC at 3 V (MIN) to
RP high
t3VPH
2
2
2
2
µs
NOTES: 10.
11.
12.
13.
30
0
0
0
Characterization data available
All ac current values are RMS unless otherwise noted.
E and G are switched low after power up.
The power supply can switch low concurrently with RP going low.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
0
ns
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
switching characteristics for TMS28F008ASy or ’AEy and TMS28F800ASy or ’AEy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
read operations
PARAMETER
ALT.
SYMBOL
’28F008ASy 70
’28F800ASy 70
’28F008AEy 70
’28F800AEy 70
’28F008ASy 80
’28F800ASy 80
’28F008AEy 80
’28F800AEy 80
3V
5V
3V
5V
MIN
ta(A)
Access time, from A0 – A18
(see Note 14)
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
tAVQV
100
70
120
80
ns
100
70
120
80
ns
65
35
65
40
ns
100
70
120
80
ns
ta(E)
ta(G)
Access time, from CE
tc(R)
Cycle time, read
tELQV
tGLQV
tAVAV
td(E)
Delay time, CE low to
low-impedance output
tELQX
0
0
0
0
ns
td(G)
Delay time, OE low to
low-impedance output
tGLQX
0
0
0
0
ns
tdis(E)
Disable time, CE to
high-impedance output
tEHQZ
55
25
55
30
ns
tdis(G)
Disable time, OE to
high-impedance output
tGHQZ
45
25
45
30
ns
th(D)
Hold time, DQ valid from
A0 – A17, CE, or OE,
whichever occurs first
(see Note 14)
tAXQX
tsu(EB)
Setup time, BYTE from CE
low
tELFL
tELFH
7
5
5
5
ns
td(RP)
Delay time, output from RP
high
tPHQV
800
450
800
450
ns
tdis(BL)
Disable time, BYTE low to
DQ8 – DQ15 in the
high-impedance state
tFLQZ
100
70
120
80
ns
ta(BH)
Access time, from BYTE
going high
tFHQV
100
70
120
80
ns
Access time, from OE
0
0
0
0
ns
NOTE 14: For 28F800 (8-bit configuration) A–1, A–1 – A18 with A–1 as LSB address. For 28F008 (16-bit configuration): A0–A19 with A0 as LSB
address.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
31
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
timing requirements for TMS28F008ASy or ’AEy and TMS28F800ASy or ’AEy (commercial and
extended temperature ranges)
write/erase operations — WE-controlled writes
ALT.
SYMBOL
’28F008ASy 70
’28F800ASy 70
’28F008AEy 70
’28F800AEy 70
’28F008ASy80
’28F800ASy80
’28F008AEy80
’28F800AEy80
3V
5V
3V
5V
MIN
tc( W )
Cycle time, write
tc( W )OP
Cycle time, duration of
programming operation
tc( W )ERB
MAX
MIN
MAX
MIN
MAX
MIN
MAX
100
70
120
80
ns
tWHQV1
6
6
6
6
µs
Cycle time, erase
operation (boot block)
tWHQV2
0.3
0.3
0.3
0.3
s
tc( W )ERP
Cycle time, erase
operation (parameter
block)
tWHQV3
0.3
0.3
0.3
0.3
s
tc( W )ERM
Cycle time, erase
operation (main block)
tWHQV4
0.6
0.6
0.6
0.6
s
td(RPR)
Delay time, boot-block
relock
tPHBR
th(A)
Hold time, A0 – A18
(see Note 14)
tWHAX
0
0
0
0
ns
0
0
0
0
ns
Hold time, CE
tWHDX
tWHEH
0
0
0
0
ns
th( VPP)
Hold time, VPP from
valid status-register bit
tQVVL
0
0
0
0
ns
th(RP)
Hold time, RP at VHH
from valid status-register
bit
tQVPH
0
0
0
0
ns
th(WP)
Hold time, WP from valid
status-register bit
tWHPL
0
0
0
0
ns
tsu(WP)
Setup time, WP before
write operation
tELPH
90
50
100
50
ns
tsu(A)
Setup time, A0 – A17
(see Note 14)
tAVWH
90
50
100
50
ns
tsu(D)
Setup time, DQ
tDVWH
90
50
100
50
ns
tsu(E)
Setup time, CE before
write operation
tELWL
0
0
0
0
ns
tsu(RP)
Setup time, RP at VHH to
WE going high
tPHHWH
200
100
100
100
ns
tsu( VPP)1
Setup time, VPP to WE
going high
tVPWH
200
100
100
100
ns
tWLWH
tWLWL
90
50
100
50
ns
Pulse duration, WE high
20
10
30
30
ns
Recovery time, RP high
to WE going low
tPHWL
1.5
450
1.5
450
µs
th(D)
th(E)
tw( W )
tw( WH)
trec(RPHW)
Hold time, DQ valid
Pulse duration, WE low
tAVAV
UNIT
200
100
200
100
ns
NOTE 14: For 28F800 (8-bit configuration) A–1, A–1 – A18 with A–1 as LSB address. For 28F008 (16-bit configuration): A0–A19 with A0 as LSB
address.
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
timing requirements for TMS28F008ASy or ’AEy and TMS28F800ASy or ’AEy (commercial and
extended temperature ranges)
write/erase operations — CE-controlled writes
ALT.
SYMBOL
tc( E )
Cycle time, write
tc(E)OP
Cycle time, duration of
programming operation
tc(E)ERB
MIN
MAX
’28F008AEy 70
’28F800AEy 70
MIN
MAX
’28F008ASy80
’28F800ASy80
MIN
MAX
’28F008AEy80
’28F800AEy80
MIN
UNIT
MAX
100
70
120
80
ns
tEHQV1
6
6
6
6
µs
Cycle time, erase
operation (boot block)
tEHQV2
0.3
0.3
0.3
0.3
s
tc(E)ERP
Cycle time, erase
operation (parameter
block)
tEHQV3
0.3
0.3
0.3
0.3
s
tc(E)ERM
Cycle time, erase
operation (main block)
tEHQV4
0.6
0.6
0.6
0.6
s
td(RPR)
Delay time, boot-block
relock
tPHBR
th(A)
Hold time, A0 – A18
(see Note 14)
tEHAX
0
0
0
0
ns
tEHDX
tEHWH
0
0
0
0
ns
Hold time, WE
0
0
0
0
ns
th (VPP)
Hold time, VPP from valid
status-register bit
tQVVL
0
0
0
0
ns
th(RP)
Hold time, RP at VHH from
valid status-register bit
tQVPH
0
0
0
0
ns
th(WP)
Hold time, WP from valid
status-register bit
tWHPL
0
0
0
0
ns
tsu(WP)
Setup time, WP before
write operation
tELPH
90
50
100
50
ns
tsu(A)
Setup time, A0 – A18
(see Note 14)
tAVEH
90
50
100
50
ns
tsu(D)
Setup time, DQ
tDVEH
90
50
100
50
ns
tsu( W )
Setup time, WE before
write operation
tWLEL
0
0
0
0
ns
tsu(RP)
Setup time, RP at VHH to
CE going high
tPHHEH
200
100
100
100
ns
tsu( VPP)2
Setup time, VPP to CE
going high
tVPEH
200
100
100
100
ns
tELEH
tEHEL
90
50
100
50
ns
Pulse duration, CE high
20
10
30
30
ns
Recovery time, RP high to
CE going low
tPHEL
1.5
450
1.5
450
µs
th(D)
th( W )
tw(E)
tw( EH)
trec(RPHE)
Hold time, DQ valid
Pulse duration, CE low
tAVAV
’28F008ASy 70
’28F800ASy 70
200
100
200
100
ns
NOTE 14: For 28F800 (8-bit configuration) A–1, A–1 – A18 with A–1 as LSB address. For 28F008 (16-bit configuration): A0–A19 with A0 as LSB
address.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
33
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
power-up and reset switching characteristics for TMS28F008AVy or ’ALy and TMS28F800AVy or
’ALy over recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 10, 11, and 12)
ALT.
SYMBOL
PARAMETER
tsu(VCC)
ta(DV)
tsu(DV)
Setup time, RP low to VCC at 3 V MIN or 3.6 V MAX
(see Note 13)
tPL5V
tPL3V
Access time, address valid to data valid
tAVQV
tPHQV
t3VPH
Setup time, RP high before data valid
th(RP3)
Hold time, VCC at 3 V (MIN) to RP high
NOTES: 10. Characterization data available
11. All ac current values are RMS unless otherwise noted.
12. E and G are switched low after power up.
13. The power supply can switch low concurrently with RP going low.
’28F008AVy100
’28F800AVy 100
’28F008ALy100
’28F800ALy100
’28F008AVy120
’28F800AVy 120
’28F008ALy120
’28F800ALy120
3.3-V VCC
RANGE
3.3-V VCC
RANGE
MIN
MIN
MAX
0
UNIT
MAX
0
ns
100
120
ns
800
800
ns
2
µs
2
switching characteristics for TMS28F008AVy or ’ALy and TMS28F800AV or ’ALy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
read operations
ALT.
SYMBOL
PARAMETER
’28F008AVy 100
’28F800AVy 100
’28F008ALy100
’28F800ALy100
3V
MIN
ta(A)
ta(E)
Access time, from A0 – A18 (see Note 14)
ta(G)
tc(R)
Access time, from OE
td(E)
td(G)
Delay time, CE low to low-impedance output
tdis(E)
tdis(G)
Disable time, CE to high-impedance output
Access time, from CE
Cycle time, read
UNIT
3V
MAX
MIN
MAX
tAVQV
tELQV
100
120
ns
100
120
ns
tGLQV
tAVAV
65
65
ns
tELQX
tGLQX
Delay time, OE low to low-impedance output
’28F008AVy 120
’28F800AVy 120
’28F008ALy120
’28F800ALy120
100
120
ns
0
0
ns
0
0
ns
Disable time, OE to high-impedance output
tEHQZ
tGHQZ
55
55
ns
45
45
ns
th(D)
Hold time, DQ valid from A0 – A17, CE, or OE, whichever occurs
first (see Note 14)
tAXQX
tsu(EB)
Setup time, BYTE from CE low
tELFL
tELFH
7
5
ns
td(RP)
Delay time, output from RP high
tPHQV
800
800
ns
tdis(BL)
Disable time, BYTE low to DQ8 – DQ15 in the high-impedance
state
tFLQZ
100
120
ns
0
0
ns
ta(BH)
Access time, from BYTE going high
tFHQV
100
120
ns
NOTE 14: For 28F800 (8-bit configuration) A–1, A–1 – A18 with A–1 as LSB address. For 28F008 (16-bit configuration): A0–A19 with A0 as LSB
address.
34
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
timing requirements for TMS28F008AVy or ’ALy and TMS28F800AVy or ’ALy (commercial and
extended temperature ranges)
write/erase operations — WE-controlled writes
ALT.
SYMBOL
’28F008AVy 100
’28F800AVy 100
’28F008ALy100
’28F800ALy100
3V
MIN
tc( W )
tc( W )OP
Cycle time, write
tc( W )ERB
tc( W )ERP
Cycle time, erase operation (boot block)
tc( W )ERM
Cycle time, erase operation (main block)
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th(E)
Hold time, DQ valid
th( VPP)
th(RP)
Hold time, VPP from valid status-register bit
th(WP)
tsu(WP)
Hold time, WP from valid status-register bit
tsu(A)
tsu(D)
Setup time, A0 – A17 (see Note 14)
tsu(E)
tsu(RP)
tsu( VPP)1
tw( W )
Setup time, VPP to WE going high
tw( WH)
trec(RPHW)
Pulse duration, WE high
Cycle time, duration of programming operation
Cycle time, erase operation (parameter block)
Hold time, A0 – A18 (see Note 14)
’28F008AVy120
’28F800AVy120
’28F008ALy120
’28F800ALy120
UNIT
3V
MAX
MIN
MAX
tAVAV
tWHQV1
tWHQV2
100
120
ns
6
6
µs
0.3
0.3
s
tWHQV3
tWHQV4
0.3
0.3
s
0.6
0.6
s
tPHBR
tWHAX
tWHDX
200
200
ns
0
0
ns
0
0
ns
tWHEH
tQVVL
0
0
ns
0
0
ns
tQVPH
tWHPL
0
0
ns
0
0
ns
90
100
ns
90
100
ns
Setup time, DQ
tELPH
tAVWH
tDVWH
90
100
ns
Setup time, CE before write operation
tELWL
0
0
ns
tPHHWH
tVPWH
200
100
ns
200
100
ns
tWLWH
tWLWL
90
100
ns
20
30
ns
Hold time, CE
Hold time, RP at VHH from valid status-register bit
Setup time, WP before write operation
Setup time, RP at VHH to WE going high
Pulse duration, WE low
tPHWL
1.5
1.5
µs
NOTE 14: For 28F800 (8-bit configuration) A–1, A–1 – A18 with A–1 as LSB address. For 28F008 (16-bit configuration): A0–A19 with A0 as LSB
address.
Recovery time, RP high to WE going low
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
35
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
timing requirements for TMS28F008AVy or ’ALy and TMS28F800AVy or ’ALy (commercial and
extended temperature ranges) (continued)
write/erase operations — CE-controlled writes
ALT.
SYMBOL
’28F008AVy 100
’28F800AVy 100
’28F008ALy100
’28F800ALy100
MIN
tc( E )
tc(E)OP
Cycle time, write
tc(E)ERB
tc(E)ERP
Cycle time, erase operation (boot block)
tc(E)ERM
td(RPR)
Cycle time, erase operation (main block)
th(A)
th(D)
Hold time, A0 – A18 (see Note 14)
th( W )
th (VPP)
Hold time, WE
th(RP)
th(WP)
Hold time, RP at VHH from valid status-register bit
tsu(WP)
tsu(A)
Setup time, WP before write operation
tsu(D)
tsu( W )
Setup time, DQ
tsu(RP)
tsu( VPP)2
Setup time, RP at VHH to CE going high
tw(E)
tw( EH)
Pulse duration, CE low
Cycle time, duration of programming operation
Cycle time, erase operation (parameter block)
Delay time, boot-block relock
Hold time, DQ valid
Hold time, VPP from valid status-register bit
Hold time, WP from valid status-register bit
Setup time, A0 – A18 (see Note 14)
Setup time, WE before write operation
Setup time, VPP to CE going high
Pulse duration, CE high
tAVAV
100
tEHQV1
tEHQV2
tEHQV3
tEHQV4
tPHBR
tEHAX
MAX
’28F008AVy80
’28F800AVy80
’28F008ALy80
’28F800ALy80
MIN
UNIT
MAX
120
ns
6
6
µs
0.3
0.3
s
0.3
0.3
s
0.6
0.6
200
s
200
ns
0
0
ns
tEHDX
tEHWH
0
0
ns
0
0
ns
tQVVL
tQVPH
0
0
ns
0
0
ns
tWHPL
tELPH
0
0
ns
90
100
ns
tAVEH
tDVEH
tWLEL
90
100
ns
90
100
ns
0
0
ns
tPHHEH
tVPEH
200
100
ns
200
100
ns
tELEH
tEHEL
90
100
ns
20
30
ns
trec(RPHE) Recovery time, RP high to CE going low
tPHEL
1.5
1.5
µs
NOTE 14: For 28F800 (8-bit configuration) A–1, A–1 – A18 with A–1 as LSB address. For 28F008 (16-bit configuration): A0–A19 with A0 as LSB
address.
36
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
power-up and reset switching characteristics for TMS28F008AZy and TMS28F800AZy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 10, 11, and 12)
ALT.
SYMBOL
PARAMETER
tsu(VCC)
ta(DV)
tsu(DV)
Setup time, RP low to VCC at 4.5 V MIN or 5.5 V MAX)
(see Note 13)
Address valid to data valid
Setup time, RP high to data valid
th(RP5)
Hold time, VCC at 4.5 V (MIN) to RP high
NOTES: 10. Characterization data available
11. All ac current values are RMS unless otherwise noted.
12. E and G are switched low after power up.
13. The power supply can switch low concurrently with RP going low.
tPL5V
tAVQV
tPHQV
t5VPH
’28F008AZy 70
’28F800AZy 70
MIN
MAX
0
’28F008AZy 80
’28F800AZy 80
MIN
UNIT
MAX
0
ns
70
80
ns
450
450
ns
2
µs
2
switching characteristics for TMS28F008AZy and TMS28F800AZy over recommended ranges of
supply voltage (commercial and extended temperature ranges)
read operations
ALT.
SYMBOL
PARAMETER
ta(A)
ta(E)
Access time, from A0 – A18 (see Note 14)
ta(G)
tc(R)
Access time, from OE
td(E)
td(G)
Delay time, CE low to low-impedance output
tdis(E)
tdis(G)
Disable time, CE to high-impedance output
Access time, from CE
Cycle time, read
MIN
MAX
’28F008AZy 80
’28F800AZy 80
MIN
UNIT
MAX
tAVQV
tELQV
70
80
ns
70
80
ns
tGLQV
tAVAV
35
40
ns
tELQX
tGLQX
Delay time, OE low to low-impedance output
’28F008AZy 70
’28F800AZy 70
70
80
ns
0
0
ns
0
0
ns
Disable time, OE to high-impedance output
tEHQZ
tGHQZ
25
30
ns
25
30
ns
th(D)
Hold time, DQ valid from A0 – A17, CE, or OE, whichever occurs
first (see Note 14)
tAXQX
tsu(EB)
Setup time, BYTE from CE low
tELFL
tELFH
5
5
ns
td(RP)
Delay time, output from RP high
tPHQV
450
450
ns
tdis(BL)
Disable time, BYTE low to DQ8 – DQ15 in the high-impedance
state
tFLQZ
70
80
ns
0
0
ns
ta(BH)
Access time, from BYTE going high
tFHQV
70
80
ns
NOTE 14: For 28F800 (8-bit configuration) A–1, A–1 – A18 with A–1 as LSB address. For 28F008 (16-bit configuration): A0–A19 with A0 as LSB
address.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
37
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
timing requirements for TMS28F008AZy and TMS28F800AZy (commercial and extended
temperature ranges)
write/erase operations — WE-controlled writes
ALT.
SYMBOL
’28F008AZy 70
’28F800AZy 70
’28F008AZy80
’28F800AZy80
5V
5V
MIN
tc( W )
tc( W )OP
Cycle time, write
tc( W )ERB
tc( W )ERP
Cycle time, erase operation (boot block)
tc( W )ERM
Cycle time, erase operation (main block)
td(RPR)
th(A)
Delay time, boot-block relock
th(D)
th(E)
Hold time, DQ valid
th( VPP)
th(RP)
Hold time, VPP from valid status-register bit
th(WP)
tsu(WP)
Hold time, WP from valid status-register bit
tsu(A)
tsu(D)
Setup time, A0 – A17 (see Note 14)
tsu(E)
tsu(RP)
Setup time, CE before write operation
tsu( VPP)1
tw( W )
Setup time, VPP to WE going high
tw( WH)
trec(RPHW)
Pulse duration, WE high
Cycle time, duration of programming operation
Cycle time, erase operation (parameter block)
Hold time, RP at VHH from valid status-register bit
Setup time, WP before write operation
Setup time, DQ
Setup time, RP at VHH to WE going high
Pulse duration, WE low
MAX
70
80
ns
tWHQV1
tWHQV2
6
6
µs
0.3
0.3
s
0.3
0.3
s
tPHBR
tWHAX
Hold time, CE
MIN
tAVAV
tWHQV3
tWHQV4
Hold time, A0 – A18 (see Note 14)
MAX
UNIT
0.6
0.6
100
s
100
ns
0
0
ns
tWHDX
tWHEH
0
0
ns
0
0
ns
tQVVL
tQVPH
tWHPL
0
0
ns
0
0
ns
0
0
ns
tELPH
tAVWH
50
50
ns
50
50
ns
tDVWH
tELWL
50
50
ns
0
0
ns
tPHHWH
tVPWH
100
100
ns
100
100
ns
tWLWH
tWLWL
50
50
ns
10
30
ns
tPHWL
450
450
µs
NOTE 14: For 28F800 (8-bit configuration) A–1, A–1 – A18 with A–1 as LSB address. For 28F008 (16-bit configuration): A0–A19 with A0 as LSB
address.
38
Recovery time, RP high to WE going low
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
timing requirements for TMS28F008AZy and TMS28F800AZy (commercial and extended
temperature ranges)
write/erase operations — CE-controlled writes
ALT.
SYMBOL
tc( E )
tc(E)OP
Cycle time, write
tc(E)ERB
tc(E)ERP
Cycle time, erase operation (boot block)
tc(E)ERM
td(RPR)
Cycle time, erase operation (main block)
th(A)
th(D)
Hold time, A0 – A18 (see Note 14)
th( W )
th (VPP)
Hold time, WE
th(RP)
th(WP)
Hold time, RP at VHH from valid status-register bit
tsu(WP)
tsu(A)
Setup time, WP before write operation
tsu(D)
tsu( W )
Setup time, DQ
tsu(RP)
tsu( VPP)2
Setup time, RP at VHH to CE going high
tw(E)
tw( EH)
Pulse duration, CE low
Cycle time, duration of programming operation
Cycle time, erase operation (parameter block)
Delay time, boot-block relock
Hold time, DQ valid
Hold time, VPP from valid status-register bit
Hold time, WP from valid status-register bit
Setup time, A0 – A18 (see Note 14)
Setup time, WE before write operation
Setup time, VPP to CE going high
Pulse duration, CE high
tAVAV
tEHQV1
tEHQV2
tEHQV3
tEHQV4
tPHBR
tEHAX
’28F008AZy 70
’28F800AZy 70
MIN
MAX
’28F008AZy80
’28F800AZy80
MIN
UNIT
MAX
70
80
ns
6
6
µs
0.3
0.3
s
0.3
0.3
s
0.6
0.6
s
100
100
ns
0
0
ns
tEHDX
tEHWH
0
0
ns
0
0
ns
tQVVL
tQVPH
0
0
ns
0
0
ns
tWHPL
tELPH
0
0
ns
50
50
ns
tAVEH
tDVEH
tWLEL
50
50
ns
50
50
ns
0
0
ns
tPHHEH
tVPEH
100
100
ns
100
100
ns
tELEH
tEHEL
50
50
ns
10
30
ns
trec(RPHE) Recovery time, RP high to CE going low
tPHEL
450
450
µs
NOTE 14: For 28F800 (8-bit configuration) A–1, A–1 – A18 with A–1 as LSB address. For 28F008 (16-bit configuration): A0–A19 with A0 as LSB
address.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
39
3V
VCC (3 V, 5 V)
2.7 V
0V
4.5 V
th(RP3)
tsu(VCC)
th(RP5)
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Address (A)
Valid
Valid
ta(DV)
ta(DV)
Data (D)
Valid 3.0 Outputs
tsu(DV)
Figure 11. Power-Up Timing and Reset Switching
Valid 5.0 Outputs
tsu(DV)
Template Release Date: 7–11–94
5.0 V
TMS28F008Axy, TMS28F800Axy
1 048 576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
RP (P)
SMJS851A – NOVEMBER 1997 – REVVISED FEBRUARY 1998
40
PARAMETER MEASUREMENT INFORMATION
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
tc(R)
A –1 – A18
(Byte-Wide)
A0 – A18
(Word-Wide)
Address Valid
ta(A)
CE
tdis(E)
ta(E)
OE
tdis(G)
ta(G)
WE
DQ0 – DQ7
(Byte-Wide)
DQ0 – DQ15
(Word-Wide)
VCC
td(G)
th(D)
td(E)
Hi-Z
Hi-Z
td(RP)
RP
Figure 12. Read-Cycle Timing
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
41
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
A –1 – A18 Standby
(Byte-Wide)
A0 – A18
(Word-Wide)
tc(W)
Write
Program-Setup
Command
Write Valid
Address or
Data
Automated
Byte / WordProgramming
Write
Read-Array
Command
Read StatusRegister Bits
tsu(A)
th(A)
CE
tsu(E)
th(E)
OE
tc( W )OP
tw( WH )
WE
DQ0 – DQ7
(Byte-Wide)
DQ0 – DQ15
(Word-Wide)
tw( W )
tsu(D)
th(D)
Data
Valid SR
Hi-Z
Hi-Z
Hi-Z
40h or 10h
trec(RPHW)
tsu(RP)
th(RP)
RP
tsu(WP)
th(WP)
WP
th( VPP)
tsu( VPP)1
VPP
Figure 13. Write-Cycle Timing ( WE-Controlled Write)
42
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
FFh
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
– A18 Standby
A –1
(Byte-Wide)
A0 – A18
(Word-Wide)
Write
Program-Setup
Command
Automated
Byte / WordProgramming
Write Valid
Address
And Data
tc( W )
Read Status
Register Bits
Write
Read-Array
Command
tsu(A)
th(A)
WE
tsu( W )
th( W )
OE
tc(E)OP
tw(EH)
CE
DQ0 – DQ7
(Byte-Wide)
DQ0 –DQ15
(Word-Wide)
tw(E)
tsu(D)
th(D)
Data
Valid SR
Hi-Z
Hi-Z
FFh
Hi-Z
40h or 10h
tsu(RP)
trec(RPHE)
th(RP)
RP
tsu(WP)
th(WP)
WP
tsu( VPP)2
th( VPP)
VPP
Figure 14. Write-Cycle Timing (CE-Controlled Write)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
43
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power
Up and
A –1 – A18 Standby
(Byte-Wide)
A0 – A18
(Word-Wide)
Write
Erase-Setup
Command
Write EraseConfirm
Command
Automated
Erase
tc( W )
Read StatusRegister Bits
Write
Read-Array
Command
tsu(A)
th(A)
CE
tsu(E)
th(E)
OE
tc( W )ERB
tc( W )ERP
tc( W )ERM
tw( WH)
WE
DQ0 –DQ7
(Byte-Wide)
DQ0 –DQ15
(Word-Wide)
tw( W )
tsu(D)
th(D)
Hi-Z
D0h
Valid SR
Hi-Z
20h
trec(RPHW)
FFh
Hi-Z
tsu(RP)
th(RP)
VHH
VIH
RP
tsu(WP)
th(WP)
WP
tsu( VPP)1
th( VPP)
VPPH
VPPL
VPP
Figure 15. Erase-Cycle Timing (WE-Controlled Write)
44
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
A –1 – A18 Standby
(Byte-Wide)
A0 – A18
(Word-Wide)
Write
Erase-Setup
Command
Write EraseConfirm
Command
Automated
Erase
tc( W )
Read StatusRegister Bits
Write
Read-Array
Command
tsu(A)
th(A)
WE
tsu( W )
th( W )
OE
tc(E)ERB
tc(E)ERP
tc(E)ERM
tw(EH)
CE
DQ0 – DQ7
(Byte-Wide)
DQ0 – DQ15
(Word-Wide)
tw(E)
tsu(D)
th(D)
Hi-Z
D0h
Valid SR
Hi-Z
20h
trec(RPHE)
FFh
Hi-Z
tsu(RP)
th(RP)
RP
tsu(WP)
th(WP)
WP
tsu( VPP)2
th( VPP)
VPP
Figure 16. Erase-Cycle Timing (CE-Controlled Write)
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
45
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
A–1 – A18
(Byte-Wide)
A0 – A18
(Word-Wide)
Address Valid
tc( R )
ta(A)
CE
ta(E)
tdis(E)
OE
tdis(G)
ta(G)
BYTE
th(D)
tsu(EB)
DQ0 – DQ7
Hi-Z
Hi-Z
Byte DQ0 – DQ7
td(G)
Word DQ0 – DQ7
td(E)
DQ8 – DQ14
Hi-Z
Hi-Z
ta(A)
tdis(BL)
Word DQ8 – DQ14
DQ15/A –1
Hi-Z
A –1 Input
Word DQ15
Figure 17. BYTE Timing, Changing From Word-Wide to Byte-Wide Mode
46
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Hi-Z
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
A –1 – A18
(Byte-Wide)
A0 – A18
(Word-Wide)
Address Valid
tc( R )
ta(A)
CE
ta(E)
tdis(E)
OE
tdis(G)
ta(G)
BYTE
th(D)
tsu(EB)
Byte DQ0 – DQ7
ta(BH)
DQ0 – DQ7
Hi-Z
Hi-Z
td(G)
Word DQ0 – DQ7
td(E)
DQ8 – DQ14
Hi-Z
Hi-Z
Word DQ8 – DQ14
Word DQ15
DQ15/A –1
A –1 Input
Hi-Z
Hi-Z
Figure 18. BYTE Timing, Changing From Byte-Wide to Word-Wide Mode
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
47
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
MECHANICAL DATA
DBJ (R-PDSO-G44)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
0,35
1,27
0,16 M
44
23
13,40
13,20
16,10
15,90
0,15 NOM
1
22
28,30
28,10
Gage Plane
0,25
0°– 8°
0,80
Seating Plane
2,625 MAX
0,50 MIN
0,10
4073325 / A 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
48
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
MECHANICAL DATA
DCD (R-PDSO-G**)
PLASTIC DUAL SMALL-OUTLINE PACKAGE
40 PIN SHOWN
NO. OF
PINS **
MAX
MIN
40
0.402
(10,20)
0.385
(9,80)
48
0.476
(12,10)
0.469
(11,90)
1
40
0.020 (0,5)
A
A
0.012 (0,30)
0.004 (0,10)
0.008 (0,21) M
21
20
0.728 (18,50)
0.720 (18,30)
0.795 (20,20)
0.780 (19,80)
0.041 (1,05)
0.037 (0,95)
0.006 (0,15)
NOM
0.047 (1,20) MAX
Seating Plane
0.028 (0,70)
0.020 (0,50)
0.004 (0,10)
0.010 (0,25) NOM
4073307/B 07/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
POST OFFICE BOX 1443
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49
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
A
absolute maximum ratings 26
access times 1
algorithms 1
architecture 1, 4, 11
Automated Block-Erase Flow Chart
24
Automated Byte-Programming Flow
Chart 22
Automated Word-Programming
Flow Chart 23
automatic power-saving mode 21
B
block-erase functions 4
block erasure 20
block memory maps 11
boot-block data protection 13
BYTE Timing, Changing From
Byte-Wide to Word-Wide Mode
48
BYTE Timing, Changing From
Word-Wide to
Byte-Wide Mode 47
byte-wide or word-wide mode
selection 16
C
clear status register 19
command definition 15
command-state machine (CSM)
14
command-state machine (CSM) operations 19
CSM codes for device-mode selection 15
cycle times 1
D
data protection 14
Data-Protection Combinations 14
description 4
device symbol nomenclature 5
50
E
electrical characteristics 29
Erase-Cycle Timing (CE-Controlled
Write) 46
Erase-Cycle Timing (WE-Controlled
Write) 45
erase operations 20
Erase-Suspend-/Erase-Resume
Flow Chart 25
erase suspend/erase resume 20
F
flow chart
automated block-erase 24
automated byte-programming
22
automated word-programming
23
erase-suspend/erase-resume 25
functional block diagram 10
L
logic symbol for the
TMS28F008Axy,
40-pin package 6
logic symbol for TMS28F800Axy,
44-pin package 7
logic symbol for TMS28LF800Axy,
48-pin package 8
M
Maximum Positive Overshoot Waveform 26
memory map
bottom boot block 13
top boot block 12
O
operation 14
Operation Modes for Byte-Wide
Mode 17, 18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
Operation Modes for Word-Wide
Mode 17
organization 1
P
packaging 1
44-pin TSOP 2
48-pin TSOP 2
parameter block 13
pinout
40-pin TSOP 3
44-pin TSOP 2
48-ball micro ball grid array 3
48-pin TSOP 2
powe-up and reset switching
characteristics, ’AZy 38
power-up and reset switching,
’AEy and ’ASy 31
power-up and reset switching
characteristics, ’AVy 35
programming operations 20
R
read algorithm-selection code 19
read array 19
Read-Cycle Timing 42
read operations 19
’ASy and ’AEy 32
read status register 19
recommended operating conditions
28
reset/deep power-down mode 21
S
status register 16
Status-Register Bit Definitions and
Functions 16
switching characteristics for ’ASy,
’AEy,
read operations 32
switching characteristics for ’AVy,
read operations 35
TMS28F008Axy,TMS28F800Axy
1048576 BY 8-BIT/524 288 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS851A – NOVEMBER 1997 – REVISED FEBRUARY 1998
switching characteristics for ’AZy,
read operations 38
T
table, data-protection combinations
14
table
absolute maximum ratings 26
command definitions 15
CSM codes for device-mode
selection 15
operation modes for byte-wide
mode 18
operation modes for word-wide
mode 17
recommended operating conditions 28
status-register bit definitions 16
VCC/VPP voltage configurations 5
word/byte typical write and blockerase 28
temperature ranges 1
timing requirements for ’ASy, ’AEy,
write/erase
operations 33, 34
timing requirements for ’AVy, write/
erase
operations 36, 37
timing requirements for ’AZy, write/
erase
operations 39, 40
TMS28F008AEy 1
TMS28F008ASy 1
TMS28F008AVy 1
TMS28F008AxB and
TMS28F800AxB
Memory Map 13
TMS28F008AxT and
TMS28F800AxT
Memory Map 12
TMS28F008AZy 1
TMS28F800AEy 1, 4
TMS28F800ASy 1, 4
TMS28F800AVy 1, 4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS28F800AZy 1
V
VCC/VPP Voltage Configurations
5
voltage configurations 4
W
word/byte typical write and blockerase performance (see Notes
7 and 8) 28
Write-Cycle Timing (WE-Controlled
Write) 43
Write-Cycle Timing (CE-Controlled
Write) 44
write-state machine (WSM) 4
write/erase operations – CE-controlled writes 34
write/erase operations –WE-controlled writes 33
51
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