TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 1 TMS320C6742 Fixed/Floating-Point DSP 1.1 Features • • • 300-MHz C674x VLIW DSP C674x Instruction Set Features – Superset of the C67x+™ and C64x+™ ISAs – 2400/1800 C674x MIPS/MFLOPS – Byte-Addressable (8-/16-/32-/64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions C674x Two Level Cache Memory Architecture – 32K-Byte L1P Program RAM/Cache – 32K-Byte L1D Data RAM/Cache – 64K-Byte L2 Unified Mapped RAM/Cache – Flexible RAM/Cache Partition (L1 and L2) – 1024K-Byte Boot ROM Enhanced Direct-Memory-Access Controller 3 (EDMA3): – 2 Channel Controllers – 3 Transfer Controllers – 64 Independent DMA Channels – 16 Quick DMA Channels – Programmable Transfer Burst Size TMS320C674x Floating-Point VLIW DSP Core – Load-Store Architecture With Non-Aligned Support – 64 General-Purpose Registers (32 Bit) – Six ALU (32-/40-Bit) Functional Units • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks • Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle – Two Multiply Functional Units • Mixed-Precision IEEE Floating Point Multiply Supported up to: – 2 SP x SP -> SP Per Clock – 2 SP x SP -> DP Every Two Clocks – 2 SP x DP -> DP Every Three Clocks – 2 DP x DP -> DP Every Four Clocks • • • • • • • • • Fixed Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples – Instruction Packing Reduces Code Size – All Instructions Conditional – Hardware Support for Modulo Loop Operation – Protected Mode Operation – Exceptions Support for Error Detection and Program Redirection Software Support – TI DSP/BIOS™ – Chip Support Library and DSP Library 1.8V or 3.3V LVCMOS IOs (except DDR2 interfaces) Two External Memory Interfaces: – EMIFA • NOR (8-/16-Bit-Wide Data) • NAND (8-/16-Bit-Wide Data) • 16-Bit SDRAM With 128 MB Address Space – DDR2/Mobile DDR Memory Controller • 16-Bit DDR2 SDRAM With 512 MB Address Space or • 16-Bit mDDR SDRAM With 256 MB Address Space One Configurable 16550 type UART Modules: – With Modem Control Signals – 16-byte FIFO – 16x or 13x Oversampling Option One Serial Peripheral Interface (SPI) With Multiple Chip-Selects One Master/Slave Inter-Integrated Circuit (I2C Bus™) One Multichannel Audio Serial Port: – Transmit/Receive Clocks up to 50 MHz – Two Clock Zones and 16 Serial Data Pins – Supports TDM, I2S, and Similar Formats – DIT-Capable – FIFO buffers for Transmit and Receive One Multichannel Buffered Serial Ports: – Transmit/Receive Clocks up to 50 MHz – Two Clock Zones and 16 Serial Data Pins – Supports TDM, I2S, and Similar Formats Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. TMS320C6000, C6000 are trademarks of Texas Instruments. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2009, Texas Instruments Incorporated PRODUCT PREVIEW • • TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 • • • • PRODUCT PREVIEW 2 – AC97 Audio Codec Interface – Telecom Interfaces (ST-Bus, H100) – 128-channel TDM – FIFO buffers for Transmit and Receive Real-Time Clock With 32 KHz Oscillator and Separate Power Rail One 64-Bit General-Purpose Timers (Configurable as Two 32-Bit Timers) One 64-Bit General-Purpose Timer (Watch Dog) Two Enhanced Pulse Width Modulators (eHRPWM): – Dedicated 16-Bit Time-Base Counter With Period And Frequency Control – 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs TMS320C6742 Fixed/Floating-Point DSP www.ti.com • • • • – Dead-Band Generation – PWM Chopping by High-Frequency Carrier – Trip Zone Input Three 32-Bit Enhanced Capture Modules (eCAP): – Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs – Single Shot Capture of up to Four Event Time-Stamps 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZWT Suffix], 0.80-mm Ball Pitch Commercial or Extended Temperature Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 1.2 Trademarks DSP/BIOS, TMS320C6000, C6000, TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas Instruments. PRODUCT PREVIEW All trademarks are the property of their respective owners. Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP 3 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 1.3 Description The device is a Low-power applications processor based on a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 64KB memory space that is shared between program and data space. L2 also has a 1024KB Boot ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system. PRODUCT PREVIEW The peripheral set includes: one inter-integrated circuit (I2C) Bus interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; one multichannel buffered serial port (McBSP) with FIFO buffers; one SPI interface with multiple chip selects; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART interface ( with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The device has a complete set of development tools for the DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. 4 TMS320C6742 Fixed/Floating-Point DSP Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 1.4 Functional Block Diagram DSP Subsystem JTAG Interface System Control C674x™ DSP CPU PLL/Clock Generator w/OSC Input Clock(s) GeneralPurpose Timer (x1) RTC/ 32-kHz OSC AET 32KB L1 Pgm Power/Sleep Controller 32KB L1 RAM 64KB L2 RAM Pin Multiplexing 1024KB L2 ROM PRODUCT PREVIEW Switched Central Resource (SCR) Peripherals DMA Audio Ports EDMA3 (x2) McASP w/FIFO Connectivity HPI Serial Interfaces Control Timers ePWM (x2) eCAP (x3) McBSP (x1) I2C (x1) SPI (x1) UART (x1) External Memory Interfaces EMIFA(8b/16B) NAND/Flash 16b SDRAM DDR2/MDDR Controller Figure 1-1. Functional Block Diagram Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP 5 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Contents 1 2 3 TMS320C6742 Fixed/Floating-Point DSP PRODUCT PREVIEW 5 Behavior ............................................. 49 1 Features .............................................. 1 6.3 Power Supplies ...................................... 49 1.2 Trademarks ........................................... 3 6.4 Reset ................................................ 50 1.3 Description ............................................ 4 6.5 Crystal Oscillator or External Clock Input ........... 53 1.4 Functional Block Diagram ............................ 5 6.6 Clock PLLs .......................................... 54 Revision History ......................................... 7 Device Overview ......................................... 8 6.7 Interrupts ............................................ 58 6.8 Power and Sleep Controller (PSC) .................. 64 .............................. Documentation Support 6.9 EDMA 3.2 Device Characteristics ................................ 8 6.10 External Memory Interface A (EMIFA) .............. 75 3.3 Device Compatibility .................................. 9 6.11 DDR2/mDDR Controller ............................. 84 3.4 DSP Subsystem ..................................... 10 6.12 Multichannel Audio Serial Port (McASP) ............ 97 16 6.13 Multichannel Buffered Serial Port (McBSP)........ 106 19 6.14 Serial Peripheral Interface Ports (SPI1) 22 6.15 6.16 Inter-Integrated Circuit Serial Ports (I2C) .......... 128 Universal Asynchronous Receiver/Transmitter (UART) ............................................. 132 42 6.17 Host-Port Interface (UHPI) ......................... 134 42 6.18 6.19 Enhanced Capture (eCAP) Peripheral ............. 142 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) ......................................... 145 6.20 Timers .............................................. 150 6.21 Real Time Clock (RTC) ............................ 152 6.22 General-Purpose Input/Output (GPIO)............. 155 6.23 Emulation Logic .................................... 159 ............................. 3.6 Pin Assignments .................................... 3.7 Pin Multiplexing Control ............................. 3.8 Terminal Functions .................................. Device Configuration .................................. 4.1 Boot Modes ......................................... 4.2 SYSCFG Module .................................... Device Operating Conditions ........................ Memory Map Summary 8 23 42 45 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted) ................................. 45 5.2 5.3 6 Recommended Operating Conditions ............... 46 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted) ............ 47 Peripheral Information and Electrical Specifications ........................................... 48 6.1 6.2 6 ............................................... 3.1 3.5 4 ........... 1.1 Parameter Information .............................. 48 Recommended Clock and Control Signal Transition Contents 7 ........... 69 112 Mechanical Packaging and Orderable Information ............................................. 161 7.1 Device Support..................................... 161 7.2 Thermal Data for ZCE Package 7.3 Thermal Data for ZWT Package ................... 164 ................... 163 Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 2 Revision History PRODUCT PREVIEW NOTE: This is a placeholder for the Revision History Table for future revisions of the document. Submit Documentation Feedback Revision History 7 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 3 Device Overview 3.1 Documentation Support 3.1.1 Related Documentation From Texas Instruments The following documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com. PRODUCT PREVIEW DSP Reference Guides SPRUG82 TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches and describes how the two-level cache-based internal memory architecture in the TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency. The internal memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory. SPRUFE8 TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added functionality and an expanded instruction set. SPRUFK5 TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. SPRUFK9 TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the device. 3.2 Device Characteristics Table 3-1 provides an overview of the device. The table shows significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count. 8 Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 3-1. Characteristics of C6742 HARDWARE FEATURES DDR2 or Mobile DDR, 16-bit bus width, up to 150 MHz EMIFA Asynchronous (8/16-bit bus width) RAM, Flash, 16-bit SDRAM, NOR, NAND EDMA3 64 independent channels, 16 QDMA channels, 2 channel controllers, 3 transfer controllers Timers 2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as Watch Dog) UART Not all peripherals pins SPI are available at the same time (for more I2C detail, see the Device Configurations section). Multichannel Audio Serial Port [McASP] Multichannel Buffered Serial Port [McBSP] 1 (with RTS and CTS flow control) 1 (with one hardware chip select) 1 ( Master/Slave) 1 (each with transmit/receive, FIFO buffer, 16 serializers) 1 (with transmit/receive, FIFO buffer, 16) eHRPWM 4 Single Edge, 4 Dual Edge Symmetric, or 2 Dual Edge Asymmetric Outputs eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs UHPI 1 (16-bit multiplexed address/data) General-Purpose Input/Output Port 9 banks of 16-bit Size (Bytes) 488KB RAM, 1088KB Boot ROM Organization DSP 32KB L1 Program (L1P)/Cache (up to 32KB) 32KB L1 Data (L1D)/Cache (up to 32KB) 64KB Unified Mapped RAM/Cache (L2) 1024KB ROM (L2) DSP Memories can be made accessible to EDMA3 and other peripherals. C674x CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1400 C674x Megamodule Revision Revision ID Register (MM_REVID[15:0]) 0x0000 JTAG BSDL_ID DEVIDR0 Register CPU Frequency MHz Cycle Time ns CPU Frequency MHz Cycle Time ns Voltage Core (V) I/O (V) (1) 0x0B7D_102F 674x DSP 300 MHz 674x DSP 3.33 ns 674x DSP 300 MHz 674x DSP 3.33 ns 1.2 V 1.8V or 3.3 V 13 mm x 13 mm, 361-Ball 0.65 mm pitch, PBGA (ZCE) Packages Product Status (1) PRODUCT PREVIEW Peripherals On-Chip Memory C6742 DDR2/mDDR Controller 16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT) Product Preview (PP), Advance Information (AI), or Production Data (PD) PP PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. 3.3 Device Compatibility The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both the C64x+ and C67x+ DSP families. Submit Documentation Feedback Device Overview 9 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 3.4 DSP Subsystem The DSP Subsystem includes the following features: • C674x DSP CPU • 32KB L1 Program (L1P)/Cache (up to 32KB) • 32KB L1 Data (L1D)/Cache (up to 32KB) • 64KB Unified Mapped RAM/Cache (L2) • 1MB Mask-programmable ROM • Little endian PRODUCT PREVIEW 32K Bytes L1P RAM/ Cache 64K Bytes L2 RAM 256 256 256 Cache Control Memory Protect 1M Byte L2 ROM 256 Cache Control Memory Protect L1P Bandwidth Mgmt L2 Bandwidth Mgmt 256 256 256 Instruction Fetch 256 Power Down Interrupt Controller C674x Fixed/Floating Point CPU IDMA Register File A Register File B 64 64 256 CFG Bandwidth Mgmt Memory Protect Cache Control 8 x 32 EMC L1D MDMA 64 32K Bytes L1D RAM/ Cache 32 Configuration Peripherals Bus SDMA 64 64 64 High Performance Switch Fabric Figure 3-1. C674xMegamodule Block Diagram 10 Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com 3.4.1 SPRS587 – JUNE 2009 C674x DSP CPU Description The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the C67x+ core. Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types. The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions. The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C674x core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support. Other new features include: • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible. • Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools. • Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication. • Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration). • Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions. Submit Documentation Feedback Device Overview 11 PRODUCT PREVIEW The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 • www.ti.com Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls. For more details on the C674x CPU and its enhancements over the C64x architecture, see the following documents: • TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRUFE8) • TMS320C64x Technical Overview (literature number SPRU395) PRODUCT PREVIEW 12 Device Overview Submit Documentation Feedback www.ti.com ÁÁTMS320C6742 Fixed/Floating-Point DSP ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á SPRS587 – JUNE 2009 src1 Odd register file A (A1, A3, A5...A31) src2 .L1 odd dst Even register file A (A0, A2, A4...A30) (D) even dst long src ST1b ST1a 32 MSB 32 LSB long src Data path A .S1 8 8 even dst odd dst src1 (D) LD1b LD1a 32 LSB DA2 32 32 src2 32 MSB DA1 LD2a LD2b Á Á Á Á Á Á .M1 dst2 dst1 src1 (A) (B) (C) dst .D1 src1 src2 2x 1x Odd register file B (B1, B3, B5...B31) src2 .D2 32 LSB 32 MSB src1 dst src2 .M2 Even register file B (B0, B2, B4...B30) (C) src1 dst2 32 (B) dst1 32 (A) src2 src1 .S2 odd dst even dst long src Data path B ST2a ST2b 32 MSB 32 LSB long src even dst .L2 (D) 8 8 (D) odd dst src2 src1 Control Register A. B. C. D. On .M unit, dst2 is 32 MSB. On .M unit, dst1 is 32 LSB. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. Figure 3-2. TMS320C674x CPU (DSP Core) Data Paths Submit Documentation Feedback Device Overview 13 PRODUCT PREVIEW src2 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 3.4.2 www.ti.com DSP Memory Mapping The DSP memory map is shown in . By default the DSP also has access to most on and off chip memory areas. Additionally, the DSP megamodule includes the capability to limit access to its internal memories through its SDMA port; without needing an external MPU unit. 3.4.2.1 External Memories The DSP has access to the following External memories: • Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA) • SDRAM (DDR2) 3.4.2.2 DSP Internal Memories PRODUCT PREVIEW The DSP has access to the following DSP memories: • L2 RAM • L1P RAM • L1D RAM 3.4.2.3 C674x CPU The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 64 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. Table 3-2 shows a memory map of the C674x CPU cache registers for the device. Table 3-2. C674x Cache Registers Byte Address Register Name 0x0184 0000 L2CFG 0x0184 0020 L1PCFG 0x0184 0024 L1PCC 0x0184 0040 L1DCFG 0x0184 0044 L1DCC 0x0184 0048 - 0x0184 0FFC - 0x0184 1000 EDMAWEIGHT Register Description L2 Cache configuration register L1P Size Cache configuration register L1P Freeze Mode Cache configuration register L1D Size Cache configuration register L1D Freeze Mode Cache configuration register Reserved L2 EDMA access control register 0x0184 1004 - 0x0184 1FFC - 0x0184 2000 L2ALLOC0 Reserved L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3 0x0184 2010 - 0x0184 3FFF - 0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register 14 Reserved 0x0184 4018 L2IBAR L2 invalidate base address register 0x0184 401C L2IWC L2 invalidate word count register 0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register 0x0184 4034 L1DWIWC L1D writeback invalidate word count register Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 3-2. C674x Cache Registers (continued) Byte Address Register Name 0x0184 4038 - 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 L1DIBAR L1D invalidate base address register 0x0184 404C L1DIWC L1D invalidate word count register - 0x0184 5000 L2WB 0x0184 5004 L2WBINV 0x0184 5008 L2INV 0x0184 500C - 0x0184 5027 - 0x0184 5028 L1PINV 0x0184 502C - 0x0184 5039 - Reserved L2 writeback all register L2 writeback invalidate all register L2 Global Invalidate without writeback Reserved PRODUCT PREVIEW 0x0184 4050 - 0x0184 4FFF Register Description Reserved L1P Global Invalidate Reserved 0x0184 5040 L1DWB 0x0184 5044 L1DWBINV L1D Global Writeback 0x0184 5048 L1DINV L1D Global Invalidate without writeback 0x0184 8000 – 0x0184 80FF MAR0 - MAR63 Reserved 0x0000 0000 – 0x3FFF FFFF 0x0184 8100 – 0x0184 817F MAR64 – MAR95 Memory Attribute Registers for EMIFA SDRAM Data (CS0) 0x4000 0000 – 0x5FFF FFFF 0x0184 8180 – 0x0184 8187 MAR96 - MAR97 Memory Attribute Registers for EMIFA Async Data (CS2) 0x6000 0000 – 0x61FF FFFF 0x0184 8188 – 0x0184 818F MAR98 – MAR99 Memory Attribute Registers for EMIFA Async Data (CS3) 0x6200 0000 – 0x63FF FFFF 0x0184 8190 – 0x0184 8197 MAR100 – MAR101 Memory Attribute Registers for EMIFA Async Data (CS4) 0x6400 0000 – 0x65FF FFFF 0x0184 8198 – 0x0184 819F MAR102 – MAR103 Memory Attribute Registers for EMIFA Async Data (CS5) 0x6600 0000 – 0x67FF FFFF 0x0184 81A0 – 0x0184 81FF MAR104 – MAR127 Reserved 0x6800 0000 – 0x7FFF FFFF 0x0184 8200 MAR128 Reserved 0x8000 0000 - 0x81FF FFFF 0x0184 8204 – 0x0184 82FF MAR129 – MAR191 Reserved 0x8200 0000 – 0xBFFF FFFF 0x0184 8300 – 0x0184 837F MAR192 – MAR223 Memory Attribute Registers for DDR2 Data (CS2) 0xC000 0000 – 0xDFFF FFFF 0x0184 8380 – 0x0184 83FF MAR224 – MAR255 Reserved 0xE000 0000 – 0xFFFF FFFF L1D Global Writeback with Invalidate See the following table for a detailed top level device memory map that includes the DSP memory space. Submit Documentation Feedback Device Overview 15 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 3.5 Memory Map Summary Table 3-3. C6746 Top Level Memory Map Start Address End Address Size DSP Mem Map 0x0000 0000 0x006F FFFF 0x0070 0000 0x0080 0000 0x007F FFFF 1024K DSP L2 ROM 0x0080 FFFF 64K 0x0081 0000 0x00DF FFFF DSP L2 RAM 32K DSP L1P RAM 32K DSP L1D RAM 0x00E0 0000 0x00E0 7FFF 0x00E0 8000 0x00EF FFFF PRODUCT PREVIEW 0x00F0 0000 0x00F0 7FFF 0x00F0 8000 0x017F FFFF 0x0180 0000 0x0180 FFFF 64K DSP Interrupt Controller 0x0181 0000 0x0181 0FFF 4K DSP Powerdown Controller 0x0181 1000 0x0181 1FFF 4K DSP Security ID DSP Revision ID EDMA Mem Map 0x0181 2000 0x0181 2FFF 4K 0x0181 3000 0x0181 FFFF 52K 0x0182 0000 0x0182 FFFF 64K DSP EMC 0x0183 0000 0x0183 FFFF 64K DSP Internal Reserved 0x0184 0000 0x0184 FFFF 64K DSP Memory System 0x0185 0000 0x01BB FFFF 0x01BC 0000 0x01BC 0FFF 0x01BC 1000 0x01BC 17FF 0x01BC 1800 0x01BC 18FF 0x01BC 1900 0x01BF FFFF 0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC 0x01C0 8000 0x01C0 83FF 1K EDMA3 TC0 0x01C0 8400 0x01C0 87FF 1K EDMA3 TC1 0x01C0 8800 0x01C0 FFFF 0x01C1 0000 0x01C1 0FFF 4K PSC 0 0x01C1 1000 0x01C1 1FFF 4K PLL Controller 0 0x01C1 2000 0x01C1 3FFF 4K SYSCFG0 0x01C1 4000 0x01C1 4FFF 0x01C1 5000 0x01C1 FFFF 0x01C2 0000 0x01C2 0FFF 4K Timer0 0x01C2 1000 0x01C2 1FFF 4K Timer1 0x01C2 2000 0x01C2 2FFF 4K I2C 0 0x01C2 3000 0x01C2 3FFF 4K RTC 0x01C2 4000 0x01C3 FFFF 0x01C4 0000 0x01C4 0FFF 4K 0x01C4 1000 0x01C4 1FFF 4K 0x01C4 2000 0x01C4 2FFF 4K 0x01C4 3000 0x01CF FFFF 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Ctrl 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data 0x01D0 3000 0x01D0 BFFF 0x01D0 C000 0x01D0 CFFF 16 Device Overview Master Peripheral Mem Map UART 0 Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 3-3. C6746 Top Level Memory Map (continued) End Address 0x01D0 D000 0x01D0 DFFF 0x01D0 E000 0x01D0 FFFF 0x01D1 0000 0x01D1 07FF 0x01D1 0800 0x01D1 0FFF Size DSP Mem Map EDMA Mem Map 0x01D1 1000 0x01D1 17FF 2K McBSP1 0x01D1 1800 0x01D1 1FFF 2K McBSP1 FIFO Ctrl 0x01D1 2000 0x01DF FFFF 0x01E0 0000 0x01E0 FFFF 0x01E1 0000 0x01E1 0FFF 4K UHPI 0x01E1 1000 0x01E1 2FFF 0x01E1 3000 0x01E1 3FFF 0x01E1 4000 0x01E1 5FFF 0x01E1 6000 0x01E1 6FFF 0x01E1 7000 0x01E1 7FFF PLL Controller 1 0x01E1 8000 0x01E1 9FFF 0x01E1 A000 0x01E1 AFFF 4K 0x01E1 B000 0x01E1 BFFF 4K 0x01E1 C000 0x01E1 FFFF 0x01E2 0000 0x01E2 1FFF 0x01E2 2000 0x01E2 2FFF 0x01E2 3000 0x01E2 3FFF 0x01E2 4000 0x01E2 4FFF 0x01E2 5000 0x01E2 5FFF 0x01E2 6000 0x01E2 6FFF 4K GPIO 0x01E2 7000 0x01E2 7FFF 4K PSC 1 0x01E2 8000 0x01E2 8FFF 4K SYSCFG1 0x01E2 9000 0x01E2 BFFF 0x01E2 C000 0x01E2 CFFF 0x01E2 D000 0x01E2 FFFF 0x01E3 0000 0x01E3 7FFF 32K EDMA3 CC1 0x01E3 8000 0x01E3 83FF 1K EDMA3 TC2 0x01E3 8400 0x01EF FFFF 0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 0x01F0 4000 0x01F0 5FFF 0x01F0 6000 0x01F0 6FFF 4K ECAP 0 0x01F0 7000 0x01F0 7FFF 4K ECAP 1 0x01F0 8000 0x01F0 8FFF 4K ECAP 2 0x01F0 9000 0x01F0 BFFF 0x01F0 C000 0x01F0 CFFF 0x01F0 D000 0x01F0 DFFF 0x01F0 E000 0x01F0 EFFF 4K SPI1 0x01F0 F000 0x01F0 FFFF 0x01F1 0000 0x01F1 0FFF Submit Documentation Feedback Master Peripheral Mem Map PRODUCT PREVIEW Start Address 4K Device Overview 17 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 3-3. C6746 Top Level Memory Map (continued) Start Address End Address Size 0x01F1 1000 0x01F1 1FFF 4K McBSP1 FIFO Data 0x01F1 2000 0x116F FFFF 0x1170 0000 0x117F FFFF 1024K DSP L2 ROM 0x1180 0000 0x1180 FFFF 64K DSP L2 RAM 0x1181 0000 0x11DF FFFF 32K DSP L1P RAM 32K DSP L1D RAM EDMA Mem Map PRODUCT PREVIEW 0x11E0 0000 0x11E0 7FFF 0x11E0 8000 0x11EF FFFF 0x11F0 0000 0x11F0 7FFF 0x11F0 8000 0x3FFF FFFF 0x4000 0000 0x5FFF FFFF 512M EMIFA SDRAM data (CS0) 0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) 0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) 0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) 0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) 0x6800 0000 0x6800 7FFF 32K EMIFA Control Regs 0x6800 8000 0x7FFF FFFF 32K DDR2 Control Regs 512M DDR2 Data 0x8000 0000 0x8001 FFFF 0x8002 0000 0xAFFF FFFF 0xB000 0000 0xB000 7FFF 0xB000 8000 0xBFFF FFFF 0xC000 0000 0xDFFF FFFF 0xE000 0000 0xFFFC FFFF 0xFFFD 0000 0xFFFD FFFF 0xFFFE 0000 0xFFFE DFFF 0xFFFE E000 0xFFFE FFFF 0xFFFF 0000 0xFFFF 1FFF 0xFFFF 2000 0xFFFF FFFF 18 DSP Mem Map Device Overview Master Peripheral Mem Map Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 3.6 Pin Assignments Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. 3.6.1 Pin Map (Bottom View) W V 1 2 3 4 5 6 7 8 9 10 GP7[8] GP7[9] GP7[10] DDR_A[10] DDR_A[6] DDR_A[2] DDR_CLKN DDR_CLKP DDR_RAS DDR_D[15] W GP7[11] GP7[12] GP7[13] DDR_A[12] DDR_A[5] DDR_A[3] DDR_CKE DDR_BA[0] DDR_CS DDR_D[13] V GP7[14] GP7[15] GP7[0]/ BOOT[0] DDR_A[8] DDR_A[4] DDR_A[7] DDR_A[0] DDR_BA[2] DDR_CAS DDR_D[12] U U T GP7[1]/ BOOT[1] GP7[2]/ BOOT[2] GP7[3]/ BOOT[3] DDR_A[11] DDR_A[13] DDR_A[9] DDR_A[1] DDR_WE DDR_BA[1] DDR_D[10] T R GP7[4]/ BOOT[4] GP7[5]/ BOOT[5] GP7[6]/ BOOT[6] DVDD3313_C GP6[0] DDR_VREF DDR_DVDD18 DDR_DVDD18 DDR_DVDD18 DDR_DQM[1] R P NC NC NC GP7[7]/ BOOT[7] DVDD3318_C DVDD3318_C DDR_DVDD18 DDR_DVDD18 DDR_DVDD18 DDR_DVDD18 P N NC NC NC NC VSS DDR_DVDD18 RVDD CVDD DDR_DVDD18 DDR_DVDD18 N VSS VSS VSS VSS CVDD CVDD VSS M DVDD3318_C VSS DVDD18 VSS VSS VSS VSS L DVDD18 CVDD VSS VSS VSS VSS K 5 6 7 8 9 10 M VSS NC L NC NC K VSS 1 NC VSS GP6[3] GP6[1] VSS 2 3 4 PRODUCT PREVIEW The following graphics show the bottom view of the ZCE and ZWT packages pin assignments in four quadrants (A, B, C, and D). The pin assignments for both packages are identical. Figure 3-3. Pin Map (Quad A) Submit Documentation Feedback Device Overview 19 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com PRODUCT PREVIEW 11 12 13 14 W DDR_D[7] DDR_D[6] DDR_DQM[0] UHPI_HCS/ GP6[7]/ V DDR_DQS[1] DDR_D[5] DDR_D[4] DDR_D[2] UHPI_HDS1/ GP6[6] U DDR_D[14] DDR_ZP DDR_D[3] DDR_D[1] DDR_D[0] T DDR_D[9] DDR_D[11] DDR_D[8] DDR_DQS[0] UHPI_HRW/ GP6[8] R DDR_DQGATE0 DDR_DQGATE1 DVDD18 P VSS DVSS3318_C DVDD18 NC NC NC N VSS VSS DVDD3318_C NC PLL1_VDDA12 NC M VSS NC DVDD3318_C NC PLL1_VSSA12 L VSS CVDD DVDD3318_C K VSS CVDD DVDD3318_C 11 12 13 UHPI_HD[13]/ 15 16 17 UHPI_HCNTL1/ GP6[10] UHPI_HD[12]/ UHPI_HD[10]/ UHPI_HD[14]/ UHPI_HD[11]/ UHPI_HD[1]/ 18 19 UHPI_HD[9]/ UHPI_HD[8]/ W UHPI_HD[7]/ UHPI_HD[6]/ V UHPI_HHWIL/ GP6[9] UHPI_HCNTL0/ GP6[11] UHPI_HD[4]/ RESETOUT/ UHPI_HAS/ GP6[15] UHPI_HINT/ GP6[12] UHPI_HRDY/ GP6[13] UHPI_HD[0]/ GP6[5] UHPI_HD[15]/ UHPI_HD[5]/ U CLKOUT/ UHPI_HDS2/ GP6[14] RSV2 UHPI_HD[3] UHPI_HD[2] T R NC NC P NC NC NC N TDI PLL0_VSSA12 NC NC M PLL0_VDDA12 TMS TRST OSCVSS OSCIN L RESET DVDD3318_B EMU1 NC OSCOUT K 14 15 16 18 19 RTC_CVDD GP8[0] 17 Figure 3-4. Pin Map (Quad B) 20 Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 11 12 13 14 15 16 17 18 19 J VSS CVDD DVDD18 DVDD3318_B TCK EMU0 NMI TDO RTC_XI J H CVDD CVDD CVDD RVDD VSS SPI1_ENA/ GP2[12] SPI1_SOMI/ GP2[11] RTC_VSS RTC_XO H G DVDD18 DVDD18 CVDD DVDD3318_A DVDD3318_A SPI1_SCS[7]/ I2C0_SCL/ GP1[15] SPI1_SIMO/ GP2[10] SPI1_SCS[6]/ I2C0_SDA/ GP1[4] SPI1_CLK/ GP2[13] G F DVDD3318_B DVDD3318_B DVDD3318_B DVDD18 DVDD3318_A SPI1_SCS[4]/ GP1[2] E EMA_A[18]/ GP4[2] EMA_A[16]/ GP4[0] EMA_A[6]/ GP5[6] DVDD3318_B CVDD TM64P0_OUT12/ GP1[7]/ D EMA_A[13]/ GP5[13] EMA_A[9]/ GP5[9] EMA_A[12]/ GP5[12] EMA_A[3]/ GP5[3] EMA_A[1]/ GP5[1] UART0_RTS/ GP8[1]/ C EMA_A[15]/ GP5[15] EMA_A[10]/ GP5[10] EMA_A[5]/ GP5[5] EMA_A[0]/ GP5[0] EMA_BA[0]/ GP2[8] B EMA_A[17]/ GP4[1] EMA_A[11]/ GP5[11] EMA_A7/ GP5[7] EMA_A[2]/ GP5[2] A EMA_A[20]/ GP4[4] EMA_A[14]/ GP5[14] EMA_A[8]/ GP5[8] 11 12 13 SPI1_SCS[1]/ EPWM1A/ GP2[15]/ SPI1_SCS[2]/ GP1[0] SPI1_SCS[3]/ GP1[1] SPI1_SCS[0]/ EPWM1B/ GP2[14]/ TM64P1_OUT12/ GP1[6]/ TM64P1_IN12 UART0_TXD/ GP8[3]/ EPWM0A/ GP1[8]/ EPWMSYNCI/ GP8[6]/ EPWM0B/ EPWMSYNCO/ GP8[5]/ UART0_RXD/ GP8[4]/ EMA_OE/ GP3[10] EMA_CS[5]/ GP3[12] EMA_CS[2]/ GP3[15] EMA_WAIT[0]/ GP3[8] EMA_WAIT[1]/ GP2[1] B EMA_A[4]/ GP5[4] EMA_BA[1]/ GP2[9] EMA_RAS/ GP2[5] EMA_CS[3]/ GP3[14] EMA_CS[0]/ GP2[0] VSS A 14 15 16 17 18 19 SPI1_SCS[5]/ GP1[3] UART0_CTS/ GP8[2]/ PRODUCT PREVIEW www.ti.com F E D C Figure 3-5. Pin Map (Quad C) Submit Documentation Feedback Device Overview 21 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 J www.ti.com 1 2 3 4 5 6 7 8 9 10 NC NC GP6[2] GP8[13] DVDD3318_C CVDD VSS VSS VSS VSS J VSS GP6[4] GP8[9] DVDD3318_A CVDD CVDD VSS VSS CVDD H PRODUCT PREVIEW H VSS G GP8[15] GP8[14] GP8[12]/ GP8[8] DVDD3318_A DVDD18 CVDD CVDD DVDD3318_B DVDD18 G GP8[11] GP8[10] AXR0/ ECAP0_APWM0/ GP8[7]/ RSVD/ RTC_ALARM/ GP0[8]/ DEEPSLEEP DVDD3318_A DVDD3318_B DVDD3318_B DVDD3318_B EMA_CS[4]/ GP3[13] DVDD3318_B F AXR3/ GP1[11]/ AXR8/ CLKS1/ ECAP1_APWM1/ GP0[0] RVDD EMA_D[15]/ GP3[7] EMA_D[5]/ GP4[13] EMA_D[3]/ GP4[11] EMA_A[23]/ MMCSD0_CLK/ GP4[7] EMA_D[8]/ GP3[0] E EMA_D[11]/ GP3[3] EMA_D[7]/ GP4[15] EMA_SDCKE/ GP2[6] EMA_D[9]/ GP3[1] F E D C AXR1/ GP1[19]/ AXR2/ GP2[10]/ AXR4/ GP1[12]/ AXR7/ EPWM1TZ[0]/ GP1[15] AXR6/ GP1[14]/ B ACLKX/ GP0[14] A ACLKR/ GP0[15] 1 AXR5/ GP1[13]/ AXR10/ DR1/ GP0[2] AMUTE/ GP0[9] AFSR/ GP0[13] AXR9/ DX1/ GP0[1] AXR12/ FSR1/ GP0[4] AXR11/ FSX1/ GP0[3] EMA_D[6]/ GP4[14] EMA_D[14]/ GP3[6] EMA_WEN_DQM[0]/ GP2[3] EMA_D[0]/ GP4[8] AFX/ GP0[12] AXR13/ CLKX1/ GP0[5] AXR14/ CLKR1/ GP0[6] EMA_D[4]/ GP4[12] EMA_D[13]/ GP3[5] EMA_CLK/ GP2[7] EMA_D[2]/ GP4[10] EMA_WE/ GP3[11] AHCLKR/ GP0[11] AHCLKX/ GP0[10] AXR15/ EPWM0TZ[0]/ ECAP2_APWM2/ GP0[7] EMA_WEB_DQM[1]/ GP2[2] EMA_D[12]/ GP3[4] EMA_D[10]/ GP3[2] EMA_D[1]/ GP4[9] EMA_CAS/ GP2[4] 2 3 4 5 6 7 8 9 EMA_A_RW/ GP3[9] D EMA_A[19]/ GP4[3] C EMA_A[21]/ GP4[5] B EMA_A[22]/ GP4[6] A 10 Figure 3-6. Pin Map (Quad D) 3.7 Pin Multiplexing Control Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module. For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed with several different functions has a corresponding 4-bit field in one of the PINMUX registers. Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data and output enable values only. The default pin multiplexing control for almost every pin is to select 'none' of the peripheral functions in which case the pin's IO buffer is held tri-stated. Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers have no effect on input from a pin. 22 Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 3.8 Terminal Functions Table 3-4 to Table 3-21 identify the external signal names, the associated pin/ball numbers along with the mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description. 3.8.1 Device Reset, NMI and JTAG Table 3-4. Reset, NMI and JTAG Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) DESCRIPTION K14 I IPU B Device reset input NMI J17 I IPU B Non-Maskable Interrupt T17 (4) IPD C Reset output RESETOUT / UHPI_HAS/ GP6[15] O JTAG TMS L16 I IPU B JTAG test mode select TDI TDO M16 I IPU B JTAG test data input J18 O IPU B JTAG test data output TCK J15 I IPU B JTAG test clock TRST L17 I IPD B JTAG test reset EMU[0] J16 I/O IPU B Emulation pin EMU[1] K16 I/O IPU B Emulation pin GP8[0] K17 I/O IPD B General-purpose input/output (1) (2) (3) (4) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Open drain mode for RESETOUT function. Submit Documentation Feedback Device Overview 23 PRODUCT PREVIEW RESET RESET TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 3.8.2 www.ti.com High-Frequency Oscillator and PLL Table 3-5. High-Frequency Oscillator and PLL Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) IPU C DESCRIPTION CLKOUT / UHPI_HDS2 / GP6[14] T18 O PLL Observation Clock OSCIN L19 I — — Oscillator input OSCOUT K19 O — — Oscillator output OSCVSS L18 GND — — Oscillator ground (for filter only) PLL0_VDDA L15 PWR — — PLL analog VDD (1.2-V filtered supply) PLL0_VSSA M17 GND — — PLL analog VSS (for filter) PLL1_VDDA N15 PWR — — PLL analog VDD (1.2-V filtered supply) PLL1_VSSA M15 GND — — PLL analog VSS (for filter) 1.2-V OSCILLATOR 1.2-V PLL0 PRODUCT PREVIEW 1.2-V PLL1 (1) (2) (3) 24 I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com 3.8.3 SPRS587 – JUNE 2009 Real-Time Clock and 32-kHz Oscillator Table 3-6. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions NAME NO. TYPE (1) PULL (2) POWER GROUP (3) — — RTC 32-kHz oscillator input RTC_XI J19 I RTC_XO DESCRIPTION H19 O — — RTC 32-kHz oscillator output RTC_ALARM / GP0[8] /DEEPSLEEP F4 O CP[0] A RTC Alarm RTC_CVDD L14 PWR — — RTC module core power (isolated from chip CVDD) RTC_Vss H18 GND — — Oscillator ground (for filter) (1) (2) (3) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. 3.8.4 DEEPSLEEP Power Control Table 3-7. DEEPSLEEP Power Control Terminal Functions SIGNAL NAME RTC_ALARM / GP0[8] /DEEPSLEEP (1) (2) (3) NO. F4 TYPE (1) PULL (2) POWER GROUP (3) I CP[0] A DESCRIPTION DEEPSLEEP power control output I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. 3.8.5 External Memory Interface A (EMIFA) Submit Documentation Feedback Device Overview 25 PRODUCT PREVIEW SIGNAL TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 3-8. External Memory Interface A (EMIFA) Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) PRODUCT PREVIEW EMA_D[15] / GP3[7] E6 I/O CP[17] B EMA_D[14] / GP3[6] C7 I/O CP[17] B EMA_D[13] / GP3[5] B6 I/O CP[17] B EMA_D[12] / GP3[4] A6 I/O CP[17] B EMA_D[11] / GP3[3] D6 I/O CP[17] B EMA_D[10] / GP3[2] A7 I/O CP[17] B EMA_D[9] / GP3[1] D9 I/O CP[17] B EMA_D[8] / GP3[0] E10 I/O CP[17] B EMA_D[7] / GP4[15] D7 I/O CP[17] B EMA_D[6] / GP4[14] C6 I/O CP[17] B EMA_D[5] / GP4[13] E7 I/O CP[17] B EMA_D[4] / GP4[12] B5 I/O CP[17] B EMA_D[3] / GP4[11] E8 I/O CP[17] B EMA_D[2] / GP4[10] B8 I/O CP[17] B EMA_D[1] / GP4[9] A8 I/O CP[17] B EMA_D[0] / GP4[8] C9 I/O CP[17] B (1) (2) (3) 26 DESCRIPTION EMIFA data bus I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 3-8. External Memory Interface A (EMIFA) Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) DESCRIPTION E9 O CP[18] B EMA_A[22]/GP4[6] A10 O CP[18] B EMA_A[21] /GP4[5] B10 O CP[18] B EMA_A[20] /GP4[4] A11 O CP[18] B EMA_A[19] /GP4[3] C10 O CP[18] B EMA_A[18] /GP4[2] E11 O CP[18] B EMA_A[17] /GP4[1] B11 O CP[18] B EMA_A[16]/GP4[0] E12 O CP[18] B EMA_A[15]/GP5[15] C11 O CP[19] B EMA_A[14] /GP5[14] A12 O CP[19] B EMA_A[13] / GP5[13] D11 O CP[19] B EMA_A[12] / GP5[12] D13 O CP[19] B EMA_A[11] / GP5[11] B12 O CP[19] B EMA_A[10] / GP5[10] C12 O CP[19] B EMA_A[9] / GP5[9] D12 O CP[19] B EMA_A[8] / GP5[8] A13 O CP[19] B EMA_A[7] / GP5[7] B13 O CP[20] B EMA_A[6] / GP5[6] E13 O CP[20] B EMA_A[5] / GP5[5] C13 O CP[20] B EMA_A[4] / GP5[4] A14 O CP[20] B EMA_A[3] / GP5[3] D14 O CP[20] B EMA_A[2] / GP5[2] B14 O CP[20] B EMA_A[1] / GP5[1] D15 O CP[20] B EMA_A[0] / GP5[0] C14 O CP[20] B EMA_BA[0] / GP2[8] C15 O CP[16] B EMA_BA[1] / GP2[9] A15 O CP[16] B EMA_CLK / GP2[7] B7 O CP[16] B EMIFA clock EMA_SDCKE / GP2[6] D8 O CP[16] B EMIFA SDRAM clock enable EMA_RAS / GP2[5] A16 O CP[16] B EMIFA SDRAM row address strobe EMA_CAS / GP2[4] A9 O CP[16] B EMIFA SDRAM column address strobe EMA_CS[0] / GP2[0] A18 O CP[16] B EMA_CS[2] / GP3[15] B17 O CP[16] B EMA_CS[3] / GP3[14] A17 O CP[16] B EMA_CS[4] / GP3[13] F9 O CP[16] B EMA_CS[5] / GP3[12] B16 O CP[16] B EMA_A_RW / GP3[9] D10 O CP[16] B EMIFA Async Read/Write control EMA_WE / GP3[11] B9 O CP[16] B EMIFA SDRAM write enable EMA_WEN_DQM[1] / GP2[2] A5 O CP[16] B EMIFA write enable/data mask for EMA_D[15:8] EMA_WEN_DQM[0] / GP2[3] C8 O CP[16] B EMIFA write enable/data mask for EMA_D[7:0] EMA_OE / GP3[10] B15 O CP[16] B EMIFA output enable EMA_WAIT[0] / GP3[8] B18 I CP[16] B EMA_WAIT[1] / GP2[1] B19 I CP[16] B Submit Documentation Feedback PRODUCT PREVIEW EMA_A[23]/GP4[7] EMIFA address bus EMIFA bank address EMIFA Async Chip Select EMIFA wait input/interrupt Device Overview 27 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 3.8.6 www.ti.com DDR2 Controller (DDR2) Table 3-9. DDR2 Controller (DDR2) Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) DESCRIPTION PRODUCT PREVIEW DDR_D[15] W10 I/O IPD DDR_D[14] U11 I/O IPD DDR_D[13] V10 I/O IPD DDR_D[12] U10 I/O IPD DDR_D[11] T12 I/O IPD DDR_D[10] T10 I/O IPD DDR_D[9] T11 I/O IPD DDR_D[8] T13 I/O IPD DDR_D[7] W11 I/O IPD DDR_D[6] W12 I/O IPD DDR_D[5] V12 I/O IPD DDR_D[4] V13 I/O IPD DDR_D[3] U13 I/O IPD DDR_D[2] V14 I/O IPD DDR_D[1] U14 I/O IPD DDR_D[0] U15 I/O IPD DDR_A[13] T5 O IPD DDR_A[12] V4 O IPD DDR_A[11] T4 O IPD DDR_A[10] W4 O IPD DDR_A[9] T6 O IPD DDR_A[8] U4 O IPD DDR_A[7] U6 O IPD DDR_A[6] W5 O IPD DDR_A[5] V5 O IPD DDR_A[4] U5 O IPD DDR_A[3] V6 O IPD DDR_A[2] W6 O IPD DDR_A[1] T7 O IPD DDR_A[0] U7 O IPD DDR_CLKP W8 O IPD DDR2 clock (positive) DDR_CLKN W7 O IPD DDR2 clock (negative) DDR_CKE V7 O IPD DDR2 clock enable DDR_WE T8 O IPD DDR2 write enable DDR_RAS W9 O IPD DDR2 row address strobe DDR_CAS U9 O IPD DDR2 column address strobe DDR_CS V9 O IPD DDR2 chip select DDR_DQM[0] W13 O IPD DDR_DQM[1] R10 O IPD (1) (2) 28 DDR2 SDRAM data bus DDR2 row/column address DDR2 data mask outputs I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 3-9. DDR2 Controller (DDR2) Terminal Functions (continued) NAME NO. TYPE (1) PULL (2) DESCRIPTION DDR_DQS[0] T14 I/O IPD DDR_DQS[1] V11 I/O IPD DDR_BA[2] U8 O IPD DDR_BA[1] T9 O IPD DDR_BA[0] V8 O IPD DDR_DQGATE0 R11 O IPD DDR2 loopback signal for external DQS gating. Route to DDR and back to DDR_DQGATE1 with same constraints as used for DDR clock and data. DDR_DQGATE1 R12 I IPD DDR2 loopback signal for external DQS gating. Route to DDR and back to DDR_DQGATE0 with same constraints as used for DDR clock and data. DDR_ZP U12 O — DDR2 reference output for drive strength calibration of N and P channel outputs. Tie to ground via 50 ohm resistor @ 0.5% tolerance. DDR_VREF R6 I — DDR voltage input for the DDR2/mDDR I/O buffers. Note even in the case of mDDR an external resistor divider connected to this pin is necessary. N6, N9, N10, P7, P8, P9, P10, R7, R8, R9 PWR — DDR PHY 1.8V power supply pins DDR_DVDD18 Submit Documentation Feedback DDR2 data strobe inputs/outputs DDR2 SDRAM bank address Device Overview 29 PRODUCT PREVIEW SIGNAL TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 3.8.7 www.ti.com Serial Peripheral Interface Modules (SPI) Table 3-10. Serial Peripheral Interface (SPI) Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) DESCRIPTION SPI1 PRODUCT PREVIEW SPI1_CLK / GP2[13] G19 O CP[15] A SPI1 clock SPI1_ENA / GP2[12] H16 O CP[15] A SPI1 enable SPI1_SCS[0] / EPWM1B / GP2[14] E19 O CP[14] A SPI1_SCS[1] / EPWM1A / GP2[15] F18 O CP[14] A SPI1_SCS[2] / GP1[0] F19 O CP[13] A SPI1_SCS[3] / GP1[1] E18 O CP[13] A SPI1_SCS[4] / GP1[2] F16 O CP[12] A SPI1_SCS[5] / GP1[3] F17 O CP[12] A SPI1_SCS[6] / I2C0_SDA / GP1[4] G18 O CP[11] A SPI1_SCS[7] / I2C0_SCL / GP1[5] G16 O CP[11] A SPI1_SIMO / GP2[10] G17 I/O/Z CP[15] A SPI1 data slave-in-master-out SPI1_SOMI / GP2[11] H17 I/O/Z CP[15] A SPI1 data slave-out-master-in (1) (2) (3) 30 SPI1 chip selects I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com 3.8.8 SPRS587 – JUNE 2009 Enhanced Capture/Auxiliary PWM Modules (eCAP0) The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon how the eCAP module is programmed. Table 3-11. Enhanced Capture Module (eCAP) Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) CP[6] A enhanced capture 0 input or auxiliary PWM 0 output CP[3] A enhanced capture 1 input or auxiliary PWM 1 output CP[1] A enhanced capture 2 input or auxiliary PWM 2 output DESCRIPTION eCAP0 AXR0 / ECAP0_APWM0 / GP8[7] F3 I/O AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] E4 I/O eCAP2 AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7] (1) (2) (3) A4 I/O I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview 31 PRODUCT PREVIEW eCAP1 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 3.8.9 www.ti.com Enhanced Pulse Width Modulators (eHRPWM) Table 3-12. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) DESCRIPTION eHRPWM0 EPWM0A / GP1[8] D19 I/O CP[7] A eHRPWM0 A output (with high-resolution) EPWM0B C17 I/O CP[7] A eHRPWM0 B output A4 I/O CP[1] A eHRPWM0 trip zone input EPWMSYNCI / GP8[6] C16 I/O CP[7] A eHRPWM0 sync input EPWMSYNCO / GP8[5] C18 I/O CP[7] A eHRPWM0 sync output AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7] PRODUCT PREVIEW eHRPWM1 SPI1_SCS[1] / EPWM1A / GP2[15] F18 I/O CP[14] A eHRPWM1 A output (with high-resolution) SPI1_SCS[0] / EPWM1B / GP2[14] E19 I/O CP[14] A eHRPWM1 B output AXR7 / EPWM1TZ[0] / GP1[15] D2 I/O CP[4] A eHRPWM1 trip zone input (1) (2) (3) 32 I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com 3.8.10 SPRS587 – JUNE 2009 Boot Table 3-13. Boot Mode Selection Terminal Functions (1) NAME NO. TYPE (2) PULL (3) POWER GROUP (4) GP7[7] / BOOT[7] P4 I CP[29] C GP7[6] / BOOT[6] R3 I CP[29] C GP7[5] / BOOT[5] R2 I CP[29] C GP7[4] / BOOT[4] R1 I CP[29] C GP7[3] / BOOT[3] T3 I CP[29] C GP7[2] / BOOT[2] T2 I CP[29] C GP7[1] / BOOT[1] T1 I CP[29] C GP7[0] / BOOT[0] U3 I CP[29] C (1) (2) (3) (4) DESCRIPTION Boot Mode Selection Pins Boot decoding is defined in the bootloader application report. I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview 33 PRODUCT PREVIEW SIGNAL TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 3.8.11 Universal Asynchronous Receiver/Transmitters (UART0) Table 3-14. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) DESCRIPTION UART0 UART0_RXD / GP8[4] C19 I CP[8] A UART0 receive data UART0_TXD / GP8[3] D18 O CP[8] A UART0 transmit data UART0_RTS / GP8[1] D16 O CP[9] A UART0 ready-to-send output UART0_CTS / GP8[2] E17 I CP[9] A UART0 clear-to-send input (1) PRODUCT PREVIEW (2) (3) 34 I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module.The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 3.8.12 Inter-Integrated Circuit Modules(I2C0) Table 3-15. Inter-Integrated Circuit (I2C) Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) DESCRIPTION SPI1_SCS[6] / I2C0_SDA / GP1[4] G18 I/O CP[11] A I2C0 serial data SPI1_SCS[7] / I2C0_SCL / GP1[5] G16 I/O CP[11] A I2C0 serial clock (1) (2) (3) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module.The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview 35 PRODUCT PREVIEW I2C0 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 3.8.13 Timers Table 3-16. Timers Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) DESCRIPTION TIMER0 TM64P0_OUT12 / GP1[7] /TM64P0_IN12 E16 I CP[10] A Timer0 lower input. TM64P0_OUT12 / GP1[7] / TM64P0_IN12 E16 O CP[10] A Timer0 lower output TIMER1 (Watchdog) PRODUCT PREVIEW TM64P1_OUT12 / GP1[6] / TM64P1_IN12 D17 I CP[10] A Timer1 lower input. TM64P1_OUT12 / GP1[6] / TM64P1_IN12 D17 O CP[10] A Timer1 lower output (1) (2) (3) 36 I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 3.8.14 Multichannel Audio Serial Ports (McASP) Table 3-17. Multichannel Audio Serial Ports Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) DESCRIPTION AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7] A4 I/O CP[1] A AXR14 / CLKR1 / GP0[6] B4 I/O CP[2] A AXR13 / CLKX1 / GP0[5] B3 I/O CP[2] A AXR12 / FSR1 / GP0[4] C4 I/O CP[2] A AXR11 / FSX1 / GP0[3] C5 I/O CP[2] A AXR10 / DR1 / GP0[2] D4 I/O CP[2] A AXR9 / DX1 / GP0[1] C3 I/O CP[2] A AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] E4 I/O CP[3] A AXR7 / EPWM1TZ[0] / GP1[15] D2 I/O CP[4] A AXR6 / GP1[14] C1 I/O CP[5] A AXR5 / GP1[13] D3 I/O CP[5] A AXR4 / GP1[12] D1 I/O CP[5] A AXR3 / GP1[11] E3 I/O CP[5] A AXR2 / GP1[10] E2 I/O CP[5] A AXR1 / GP1[9] E1 I/O CP[5] A AXR0 / ECAP0_APWM0 / GP8[7] F3 I/O CP[6] A AHCLKX / GP0[10] A3 I/O CP[0] A McASP0 transmit master clock ACLKX / GP0[14] B1 I/O CP[0] A McASP0 transmit bit clock AFSX / GP0[12] B2 I/O CP[0] A McASP0 transmit frame sync AHCLKR / GP0[11] A2 I/O CP[0] A McASP0 receive master clock ACLKR / GP0[15] A1 I/O CP[0] A McASP0 receive bit clock AFSR / GP0[13] C2 I/O CP[0] A McASP0 receive frame sync AMUTE / GP0[9] D5 I/O CP[0] A McASP0 mute output (1) (2) (3) PRODUCT PREVIEW McASP0 McASP0 serial data I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Submit Documentation Feedback Device Overview 37 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 3.8.15 Multichannel Buffered Serial Ports (McBSP) Table 3-18. Multichannel Buffered Serial Ports (McBSPs) Terminal Functions SIGNAL NAME NO. TYPE (1) PULL (2) POWER GROUP (3) DESCRIPTION McBSP1 PRODUCT PREVIEW AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] E4 I CP[3] A McBSP1 sample rate generator clock input AXR14 / CLKR1 / GP0[6] B4 I/O CP[2] A McBSP1 receive clock AXR12 / FSR1 / GP0[4] C4 I/O CP[2] A McBSP1 receive frame sync AXR10 / DR1 / GP0[2] D4 I CP[2] A McBSP1 receive data AXR13 / CLKX1 / GP0[5] B3 I/O CP[2] A McBSP1 transmit clock AXR11 / FSX1 / GP0[3] C5 I/O CP[2] A McBSP1 transmit frame sync AXR9 / DX1 / GP0[1] C3 O CP[2] A McBSP1 transmit data (1) (2) (3) 38 I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com 3.8.16 SPRS587 – JUNE 2009 Universal Host-Port Interface (UHPI) Table 3-19. Universal Host-Port Interface (UHPI) Terminal Functions TYPE (1) PULL (2) POWER GROUP (3) U18 I/O CP[26] C UHPI_HD[14] V16 I/O CP[26] C UHPI_HD[13] R14 I/O CP[26] C UHPI_HD[12] W16 I/O CP[26] C UHPI_HD[11] V17 I/O CP[26] C UHPI_HD[10] W17 I/O CP[26] C UHPI_HD[9] W18 I/O CP[26] C UHPI_HD[8] W19 I/O CP[26] C UHPI_HD[7] V18 I/O CP[27] C UHPI_HD[6] V19 I/O CP[27] C UHPI_HD[5] U19 I/O CP[27] C UHPI_HD[4] T16 I/O CP[27] C UHPI_HD[3] R18 I/O CP[27] C UHPI_HD[2] R19 I/O CP[27] C UHPI_HD[1] R15 I/O CP[27] C UHPI_HD[0] P17 I/O CP[27] C UHPI_HCNTL0 /GP6[11] U17 I CP[24] C UHPI_HCNTL1 /GP6[10] W15 I CP[24] C UHPI_HHWIL /GP6[9] U16 I CP[24] C UHPI half-word identification control UHPI_HRW /GP6[8] T15 I CP[24] C UHPI read/write UHPI_HCS / GP6[7] W14 I CP[25] C UHPI chip select UHPI_HDS1 / GP6[6] V15 I CP[25] C CLKOUT / UHPI_HDS2 T18 I CP[22] C UHPI_HINT / GP6[12] R16 I CP[23] C UHPI host interrupt UHPI_HRDY / GP6[13] R17 O CP[23] C UHPI ready RESETOUT / UHPI_HAS / GP6[15] T17 I CP[21] C UHPI address strobe NAME NO. UHPI_HD[15] (1) (2) (3) DESCRIPTION PRODUCT PREVIEW SIGNAL UHPI data bus UHPI access control UHPI data strobe I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal. Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral. IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the device is out of reset. During reset, all of the pins associated with these registers are weakly pulled down. If the application requires a pull-up, an external pull-up can be used. This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power supply DVDD3318_C. 3.8.17 Reserved and No Connect Table 3-20. Reserved and No Connect Terminal Functions SIGNAL NAME RSV2 (1) NO. T19 TYPE (1) PWR DESCRIPTION Reserved. For proper device operation, this pin must be tied directly to CVDD. PWR = Supply voltage. Submit Documentation Feedback Device Overview 39 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 3-20. Reserved and No Connect Terminal Functions (continued) SIGNAL NAME NC NO. M3, M14, N16 TYPE (1) — DESCRIPTION No connect (Leave unconnected, do not connect to power or ground.) PRODUCT PREVIEW 40 Device Overview Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 3.8.18 Supply and Ground Table 3-21. Supply and Ground Terminal Functions NAME NO. TYPE (1) DESCRIPTION CVDD (Core supply) E15, G7, G8, G13, H6, H7, H10, H11, H12, H13, J6, J12, K6, K12, L12, M8, M9, N8 PWR 1.2-V core supply voltage pins RVDD (Internal RAM supply) E5, H14, N7 PWR 1.2V internal ram supply voltage pins DVDD18 (I/O supply) F14, G6, G10, G11, G12, J13, K5, L6, N6, N9, N10, P7, P8, P9, P10, P13, R7, R8, R9, R13 PWR 1.8V I/O supply voltage pins DVDD3318_A (I/O supply) F5, F15, G5, G14, G15, H5 PWR 1.8V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group A DVDD3318_B (I/O supply) E14, F6, F7, F8, F10, F11, F12, F13, G9, J14, K15 PWR 1.8V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group B DVDD3318_C (I/O supply) J5, K13, L4, L13, M13, N13, P5, P6, P12, R4 PWR 1.8V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group C VSS (Ground) A19, H8, H9, H15, J7, J8, J9, J10, J11, K7, K8, K9, K10, K11, L5, L7, L8, L9, L10, L11, M4, M5, M6, M7, M10, M11, N5, N11, N12, P11 GND Ground pins. (1) PWR = Supply voltage, GND - Ground. Submit Documentation Feedback Device Overview 41 PRODUCT PREVIEW SIGNAL TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 4 Device Configuration 4.1 Boot Modes This device supports a variety of boot modes through an internal DSP ROM bootloader. This device does not support dedicated hardware boot modes; therefore, all boot modes utilize the internal DSP ROM. The input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by the values of the BOOT pins. See Using the D800K001 Bootloader Application Report (SPRAB04) for more details on the ROM Boot Loader. PRODUCT PREVIEW The following boot modes are supported: • NAND Flash boot – 8-bit NAND • NOR Flash boot – NOR Direct boot (8-bit or 16-bit) – NOR Legacy boot (8-bit or 16-bit) – NOR AIS boot (8-bit or 16-bit) • HPI Boot • I2C0 Boot – EEPROM (Master Mode) – External Host (Slave Mode) • SPI1 Boot – Serial Flash (Master Mode) – SERIAL EEPROM (Master Mode) – External Host (Slave Mode) • UART0 Boot – External Host 4.2 SYSCFG Module The following system level features of the chip are controlled by the SYSCFG peripheral: • Readable Device, Die, and Chip Revision ID • Control of Pin Multiplexing • Priority of bus accesses different bus masters in the system • Capture at power on reset the chip BOOT pin values and make them available to software • Control of the DeepSleep power management function • Enable and selection of the programmable pin pullups and pulldowns • Special case settings for peripherals: – Locking of PLL controller settings – Default burst sizes for EDMA3 transfer controllers – Selection of the source for the eCAP module input capture (including on chip sources) – McASP AMUTEIN selection and clearing of AMUTE status for the McASP – Clock source selection for EMIFA – DDR2 Controller PHY settings • Selects the source of emulation suspend signal (from DSP) of peripherals supporting this function. Since the SYSCFG peripheral controls global operation of the device, its registers are protected against erroneous accesses by several mechanisms: 42 Device Configuration Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com • • SPRS587 – JUNE 2009 A special key sequence must be written to KICK0, KICK1 registers before any other registers are writeable. Additionally, many registers are accessible only by a host (DSP) when it is operating in its privileged mode. (ex. from the kernel, but not from user space code). Table 4-1. System Configuration (SYSCFG) Module Register Access Register Name Register Description Register Access REVID Revision Identification Register — 0x01C14008 DIEIDR0 Device Identification Register 0 — 0x01C1400C DIEIDR1 Device Identification Register 1 — 0x01C14010 DIEIDR2 Device Identification Register 2 — 0x01C14014 DIEIDR3 Device Identification Register 3 0x01C1 4020 BOOTCFG Boot Configuration Register Privileged mode 0x01C1 4038 KICK0R Kick 0 Register Privileged mode 0x01C1 403C KICK1R Kick 1 Register Privileged mode 0x01C1 4044 HOST1CFG Host 1 Configuration Register 0x01C1 40E0 IRAWSTAT Interrupt Raw Status/Set Register Privileged mode 0x01C1 40E4 IENSTAT Interrupt Enable Status/Clear Register Privileged mode 0x01C1 40E8 IENSET Interrupt Enable Register Privileged mode 0x01C1 40EC IENCLR Interrupt Enable Clear Register Privileged mode 0x01C1 40F0 EOI End of Interrupt Register Privileged mode 0x01C1 40F4 FLTADDRR Fault Address Register Privileged mode 0x01C1 40F8 FLTSTAT Fault Status Register 0x01C1 4110 MSTPRI0 Master Priority 0 Registers Privileged mode 0x01C1 4114 MSTPRI1 Master Priority 1 Registers Privileged mode 0x01C1 4118 MSTPRI2 Master Priority 2 Registers Privileged mode 0x01C1 4120 PINMUX0 Pin Multiplexing Control 0 Register Privileged mode 0x01C1 4124 PINMUX1 Pin Multiplexing Control 1 Register Privileged mode 0x01C1 4128 PINMUX2 Pin Multiplexing Control 2 Register Privileged mode 0x01C1 412C PINMUX3 Pin Multiplexing Control 3 Register Privileged mode 0x01C1 4130 PINMUX4 Pin Multiplexing Control 4 Register Privileged mode 0x01C1 4134 PINMUX5 Pin Multiplexing Control 5 Register Privileged mode 0x01C1 4138 PINMUX6 Pin Multiplexing Control 6 Register Privileged mode 0x01C1 413C PINMUX7 Pin Multiplexing Control 7 Register Privileged mode 0x01C1 4140 PINMUX8 Pin Multiplexing Control 8 Register Privileged mode 0x01C1 4144 PINMUX9 Pin Multiplexing Control 9 Register Privileged mode 0x01C1 4148 PINMUX10 Pin Multiplexing Control 10 Register Privileged mode 0x01C1 414C PINMUX11 Pin Multiplexing Control 11 Register Privileged mode 0x01C1 4150 PINMUX12 Pin Multiplexing Control 12 Register Privileged mode 0x01C1 4154 PINMUX13 Pin Multiplexing Control 13 Register Privileged mode 0x01C1 4158 PINMUX14 Pin Multiplexing Control 14 Register Privileged mode 0x01C1 415C PINMUX15 Pin Multiplexing Control 15 Register Privileged mode 0x01C1 4160 PINMUX16 Pin Multiplexing Control 16 Register Privileged mode 0x01C1 4164 PINMUX17 Pin Multiplexing Control 17 Register Privileged mode 0x01C1 4168 PINMUX18 Pin Multiplexing Control 18 Register Privileged mode 0x01C1 416C PINMUX19 Pin Multiplexing Control 19 Register Privileged mode 0x01C1 4170 SUSPSRC Suspend Source Register Privileged mode 0x01C1 4174 CHIPSIG Chip Signal Register — 0x01C1 4178 CHIPSIG_CLR Chip Signal Clear Register — Submit Documentation Feedback — PRODUCT PREVIEW Register Address 0x01C1 4000 — — Device Configuration 43 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 4-1. System Configuration (SYSCFG) Module Register Access (continued) Register Address Register Name Register Description Register Access 0x01C1 417C CFGCHIP0 Chip Configuration 0 Register Privileged mode 0x01C1 4180 CFGCHIP1 Chip Configuration 1 Register Privileged mode 0x01C1 4188 CFGCHIP3 Chip Configuration 3 Register Privileged mode 0x01C1 418C CFGCHIP4 Chip Configuration 4 Register Privileged mode 0x01E2 C000 VTPIO_CTL VTPIO COntrol Register Privileged mode 0x01E2 C004 DDR_SLEW DDR Slew Register Privileged mode 0x01E2 C008 DeepSleep DeepSleep Register Privileged mode 0x01E2 C00C PUPD_ENA Pullup / Pulldown Enable Register Privileged mode 0x01E2 C010 PUPD_SEL Pullup / Pulldown Selection Register Privileged mode 0x01E2 C014 RXACTIVE RXACTIVE Control Register Privileged mode PRODUCT PREVIEW 44 Device Configuration Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 5 Device Operating Conditions 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted) (1) Core Logic, Variable and Fixed (CVDD, RVDD, RTC_CVDD, PLL0_VDDA , PLL1_VDDA I/O, 1.8V (DDR_DVDD18) Output voltage (VO) ranges Clamp Current (3) -0.5 V to 1.4 V -0.5 V to 2 V (3) I/O, 3.3V (DVDD3318_A, DVDD3318_B, DVDD3318_C) Input voltage (VI) ranges ,) -0.5 V to 3.8V (3) Oscillator inputs (OSCIN, RTC_XI), 1.2V -0.3 V to CVDD + 0.3V Dual-voltage LVCMOS inputs, 3.3V or 1.8V (Steady State) -0.3V to DVDD + 0.3V Dual-voltage LVCMOS inputs, 3.3V or 1.8V (Transient) DVDD + 20% up to 20% of Signal Period Dual-voltage LVCMOS outputs, 3.3V or 1.8V (Steady State) -0.5 V to DVDD + 0.3V Dual-voltage LVCMOS outputs, 3.3V or 1.8V (Transient) DVDD + 20% up to 20% of Signal Period ±20mA Input or Output Voltages 0.3V above or below their respective power rails. Limit clamp current that flows through the I/O's internal diode protection cells. Operating Junction Temperature ranges, TJ Commercial (default) 0°C to 90°C Extended (A version) -40°C to 105°C Storage temperature range, Tstg (default) -55°C to 150°C (1) (2) (3) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This pin is an internal LDO output and connected via 0.22 F capacitor to VSS All voltage values are with respect to VSS, PLL0_VSSA, OSCVSS, RTC_VSS Submit Documentation Feedback Device Operating Conditions 45 PRODUCT PREVIEW Supply voltage ranges (2) TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 5.2 Recommended Operating Conditions NAME CVDD Supply Voltage MIN NOM MAX UNIT 1.14 1.2 or 1.26 1.32 V 1.1V operating point 1.05 1.1 1.16 V 1.0V operating point 0.95 1.0 1.05 V Internal RAM Supply Voltage 1.14 1.2 or 1.26 1.32 V RTC_CVDD RTC Core Logic Supply Voltage 1.14 1.2 or 1.26 1.32 V PLL0_VDDA PLL0 Supply Voltage 1.14 1.2 or 1.26 1.32 V PLL1_VDDA PLL1 Supply Voltage 1.14 1.2 or 1.26 1.32 V DDR_DVDD18 DDR2 PHY Supply Voltage 1.71 1.8 1.89 V 0.49* DDR_DVDD18 0.5* DDR_DVDD1 8 0.51* DDR_DVDD18 V PRODUCT PREVIEW DDR_VREF DDR2/mDDR reference voltage DDR_ZP DDR2/mDDR impedance control, connected via 200Ω resistor to Vss DVDD3318_A Power Group A Dual-voltage IO Supply Voltage 1.8V operating point 1.71 1.8 1.89 V 3.3V operating point 3.15 3.3 3.45 V Power Group B Dual-voltage IO Supply Voltage 1.8V operating point 1.71 1.8 1.89 V 3.3V operating point 3.15 3.3 3.45 V DVDD3318_C Power Group C Dual-voltage IO Supply Voltage 1.8V operating point 1.71 1.8 1.89 V 3.3V operating point 3.15 3.3 3.45 V VSS Core Logic Digital Ground V PLL0_VSSA PLL0 Ground V PLL1_VSSA PLL1 Ground V Oscillator Ground V OSCVSS (1) RTC Oscillator Ground VIH High-level input voltage, Dual-voltage I/O, 3.3V (2) V 0.65*DVDD V High-level input voltage, RTC_XI 0.8*RTC_CVDD V High-level input voltage, OSCIN 0.8*CVDD tt 46 V 0.8 V 0.35*DVDD V Low-level input voltage, RTC_XI 0.2*RTC_CVDD V Low-level input voltage, OSCIN 0.2*CVDD V 5 ns (2) 10%-90%, All Inputs (except USB0 and DDR2) FSYSCLK1,6 Extended temperature grade (A suffix) (2) (2) Low-level input voltage, Dual-voltage I/O, 3.3V (2) Commercial temperature grade (default) (1) V High-level input voltage, Dual-voltage I/O, 1.8V Voltage Input Low V 2 High-level input voltage, Dual-voltage I/O, 1.8V VIL Operating Frequency Vss RTC_VSS (1) Voltage Input High Transition Time CONDITION 1.2V operating point RVDD DVDD3318_B Supply Ground DESCRIPTION Core Logic Supply Voltage (variable) CVDD = 1.2V operating point 0 300 CVDD = 1.1V operating point 0 200 CVDD = 1.0V operating point 0 100 CVDD = 1.2V operating point 0 300 CVDD = 1.1V operating point 0 200 CVDD = 1.0V operating point 0 100 MHz MHz When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground. These IO specifications apply to the dual-voltage IOs only and do not apply to DDR2/mDDR . DDR2/mDDR IOs are 1.8V IOs and adhere to the JESD79-2A standard. Device Operating Conditions Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted) VOH TEST CONDITIONS High-level output voltage (dual-voltage LVCMOS IOs at 3.3V) (1) High-level output voltage (dual-voltage LVCMOS IOs at 1.8V) (1) VOL Low-level output voltage (dual-voltage LVCMOS I/Os at 3.3V) Low-level output voltage (dual-voltage LVCMOS I/Os at 1.8V) MIN TYP II (2) Input current (dual-voltage LVCMOS I/Os) UNIT 2.4 V DVDD = 3.15V, IOH = -100 µA 2.95 V DVDD-0.45 V DVDD = 1.65V, IOH = -2 mA DVDD = 3.15V, IOL = 4mA 0.4 V DVDD = 3.15V, IOL = -100 µA 0.2 V DVDD = 1.65V, IOL = 2mA 0.45 V ±9 µA VI = VSS to DVDD without opposing internal resistor (1) MAX DVDD = 3.15V, IOH = -4 mA VI = VSS to DVDD with opposing internal pullup resistor (3) 70 310 µA VI = VSS to DVDD with opposing internal pulldown resistor (3) -75 -270 µA All peripherals -6 mA All peripherals 6 mA (1) IOH High-level output current (dual-voltage LVCMOS I/Os) (1) IOL Low-level output current (dual-voltage LVCMOS I/Os) Input capacitance (dual-voltage LVCMOS) Capacit Output capacitance (dual-voltage ance LVCMOS) (1) (2) (3) 3 pF 3 pF These IO specifications apply to the dual-voltage IOs only and do not apply to DDR2/mDDR . DDR2/mDDR IOs are 1.8V IOs and adhere to the JESD79-2A standard. II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current. Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. Submit Documentation Feedback Device Operating Conditions 47 PRODUCT PREVIEW PARAMETER TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6 Peripheral Information and Electrical Specifications 6.1 Parameter Information 6.1.1 Parameter Information Device-Specific Information Tester Pin Electronics 42 Ω 3.5 nH Transmission Line PRODUCT PREVIEW Z0 = 50 Ω (see note) 4.0 pF A. 1.85 pF Data Sheet Timing Reference Point Output Under Test Device Pin (see note) The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 6-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 6.1.1.1 Signal Transition Levels All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O, Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V. Vref Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels 48 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 6.3 Power Supplies Power-on Sequence The device should be powered-on in the following order: • 1) RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other supplies being applied. If the RTC is not used, RTC_CVDD should be connected to CVDD. • 2a) All variable 1.2V - 1.0V core logic supplies (CVDD) • 2b) All static 1.2V logic supplies (RVDD, VDDA_12_PLL0, VDDA_12_PLL1). If voltage scaling is not used on the device, groups 2a) and 2b) can be controlled from the same power supply and powered up together. • 3) All static 1.8V IO supplies (DVDD18, DDR_DVDD18) and any of the LVCMOS IO supply groups used at 1.8V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C). • 4)LVCMOS IO supply groups used at 3.3V nominal (DVDD3318_A, DVDD3318_B, or DVDD3318_C). There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V supplies by more than 2 volts. 6.3.2 Power-off Sequence The power supplies can be powered-off in any order as long as LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed static 1.8V supplies by more than 2 volts. There is no specific required voltage ramp down rate for any of the supplies (except as required to meet the above mentioned voltage condition). Submit Documentation Feedback Peripheral Information and Electrical Specifications 49 PRODUCT PREVIEW 6.3.1 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.4 Reset 6.4.1 Power-On Reset (POR) A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal logic to its default state. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence. RESETOUT is an output for use by other controllers in the system that indicates the device is currently in reset. PRODUCT PREVIEW A summary of the effects of Power-On Reset is given below: • All internal logic (including emulation logic and the PLL logic) is reset to its default state • Internal memory is not maintained through a POR • RESETOUT goes active • All device pins go to a high-impedance state • The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC A watchdog reset triggers a POR. 6.4.2 Warm Reset A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low (TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT which remains active through the reset sequence. RESETOUT is an output for use by other controllers in the system that indicates the device is currently in reset. A summary of the effects of Warm Reset is given below: • All internal logic (except for the emulation logic and the PLL logic) is reset to its default state • Internal memory is maintained through a warm reset • RESETOUT goes active • All device pins go to a high-impedance state • The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the RTC 50 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com 6.4.3 SPRS587 – JUNE 2009 Reset Electrical Data Timings Table 6-1 assumes testing over the recommended operating conditions. NO. (2) ) 1.2V PARAMETER MIN 1.1V MAX MIN 1.0V MAX MIN UNIT MAX 1 tw(RSTL) Pulse width, RESET/TRST low 100 100 100 ns 2 tsu(BPV-RSTH) Setup time, boot pins valid before RESET/TRST high 20 20 20 ns 3 th(RSTH-BPV) Hold time, boot pins valid after RESET/TRST high 20 20 20 ns 4 5 (1) (2) (3) td(RSTH-RESETOUTH) RESET high to RESETOUT high; Warm reset td(RSTL-RESETOUTL) 14 16 20 RESET high to RESETOUT high; Power-on Reset 14 16 20 Delay time, RESET/TRST low to RESETOUT low 14 16 20 cycles (3) ns PRODUCT PREVIEW Table 6-1. Reset Timing Requirements ( (1), RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-4 for details. For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this table refer to RESET only (TRST is held high). OSCIN cycles. Power Supplies Ramping Power Supplies Stable Clock Source Stable OSCIN 1 RESET TRST 4 RESETOUT 3 2 Boot Pins Config Figure 6-4. Power-On Reset (RESET and TRST active) Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 51 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Power Supplies Stable OSCIN TRST 1 RESET 5 4 RESETOUT PRODUCT PREVIEW 3 2 Boot Pins Driven or Hi-Z Config Figure 6-5. Warm Reset (RESET active, TRST high) Timing 52 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.5 Crystal Oscillator or External Clock Input The device includes two choices to provide an external clock input, which is fed to the on-chip PLLs to generate high-frequency system clocks. These options are illustrated in Figure 6-6 and Figure 6-7. For input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended. Typical C1, C2 values are 10-20 pF. Figure 6-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit. Figure 6-7 illustrates the option that uses an external 1.2V clock input. C2 Clock Input to PLL OSCIN PRODUCT PREVIEW X1 OSCOUT C1 OSCVSS Figure 6-6. On-Chip Oscillator Table 6-2. Oscillator Timing Requirements PARAMETER fosc Oscillator frequency range (OSCIN/OSCOUT) Submit Documentation Feedback MIN MAX UNIT 12 30 MHz Peripheral Information and Electrical Specifications 53 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com OSCIN NC Clock Input to PLL OSCOUT OSCVSS PRODUCT PREVIEW Figure 6-7. External 1.2V Clock Source Table 6-3. OSCIN Timing Requirements for an Externally Driven Clock PARAMETER fCLKIN OSCIN frequency range tc(CLKIN) Cycle time, external clock driven on OSCIN MIN MAX UNIT 12 50 MHz 20 ns tw(CLKINH) Pulse width high, external clock on OSCIN 0.4 tc(CLKIN) ns tw(CLKINL) Pulse width low, external clock on OSCIN 0.4 tc(CLKIN) ns tt(CLKIN) Transition time, OSCIN 5 ns 6.6 Clock PLLs The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the mDDR/DDR2 Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0. The PLL controller provides the following: • Glitch-Free Transitions (on changing clock settings) • Domain Clocks Alignment • Clock Gating • PLL power down The various clock outputs given by the controller are as follows: • Domain Clocks: SYSCLK [1:n] • Auxiliary Clock from reference clock source: AUXCLK Various dividers that can be used are as follows: • Post-PLL Divider: POSTDIV • SYSCLK Divider: D1, , Dn Various other controls supported are as follows: • PLL Multiplier Control: PLLM • Software programmable PLL Bypass: PLLEN 6.6.1 PLL Device-Specific Information The device DSP generates the high-frequency internal clocks it requires through an on-chip PLL. 54 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-8. 1.14V - 1.32V 50R PLLn_VDDA 0.1 µF VSS 50R 0.01 µF PLLn_VSSA Ferrite Bead: Murata BLM31PG500SN1L or Equivalent The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. PLL0 outputs seven clocks that have programmable divider options. PLL1 outputs three clocks that have programmable divider options. Figure 6-9 illustrates the high-level view of the PLL Topology. The PLLs are disabled by default after a device reset. They must be configured by software according to the allowable operating conditions listed in Table 6-4 before enabling the device to run from the PLL by setting PLLEN = 1. Submit Documentation Feedback Peripheral Information and Electrical Specifications 55 PRODUCT PREVIEW Figure 6-8. PLL External Filtering Components TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com PLL Controller 0 PLLCTL[EXTCLKSRC] PLL1_SYSCLK3 1 PLLCTL[PLLEN] PLLCTL[CLKMODE] CLKIN 1 OSCIN 0 0 PREDIV POSTDIV PLL 0 PLLDIV1 (/1) SYSCLK1 1 PLLDIV2 (/2) SYSCLK2 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/3) SYSCLK5 PLLDIV6 (/1) SYSCLK6 PLLDIV7 (/6) SYSCLK7 PLLDIV3 (/3) SYSCLK3 PLLM PRODUCT PREVIEW EMIFA Internal Clock Source 0 DIV4.5 1 CFGCHIP3[EMA_CLKSRC] AUXCLK OBSCLK (OBSCLK Pin) DIV4.5 OSCDIV PLL Controller 1 PLLCTL[PLLEN] PLL POSTDIV PLLM 0 PLLDIV2 (/2) SYSCLK2 1 PLLDIV3 (/3) SYSCLK3 PLLDIV1 (/1) SYSCLK1 DDR2/mDDR Internal Clock Source Figure 6-9. PLL Topology 56 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 NO. 1 PARAMETER PLLRST: Assertion time during initialization 2 Lock time: The time that the application has to wait for the PLL to acquire lock before setting PLLEN, after changing PREDIV, PLLM, or OSCIN 3 PREDIV: Pre-divider value 4 PLLREF: PLL input frequency 5 PLLM: PLL multiplier values 6 PLLOUT: PLL output frequency 7 (1) POSTDIV: Post-divider value Default Value MIN MAX UNIT N/A 125 N/A ns N/A 2000 N Max PLL Lock Time = m where N = Pre-Divider Ratio M = PLL Multiplier OSCIN cycles N/A /1 /1 /32 ns 12 50 MHz x20 x4 x32 N/A 400 600 (1) MHz /32 ns /1 /2 (1) PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL output clock. 6.6.2 Device Clock Generation PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1 manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test points. PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the mDDR/DDR2 Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on the application requirements. In addition, some peripherals have specific clock options independent of the ASYNC clock domain. Submit Documentation Feedback Peripheral Information and Electrical Specifications 57 PRODUCT PREVIEW Table 6-4. Allowed PLL Operating Conditions (PLL0 and PLL1) TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.7 Interrupts The device has a large number of interrupts to service the needs of its many peripherals and subsystems. PRODUCT PREVIEW 58 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com 6.7.1 SPRS587 – JUNE 2009 DSP Interrupts PRODUCT PREVIEW The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable and is listed in Table 6-5. Also, the interrupt controller controls the generation of the CPU exceptions, NMI, and emulation interrupts. Table 6-6 summarizes the C674x interrupt controller registers and memory locations. Submit Documentation Feedback Peripheral Information and Electrical Specifications 59 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-5. C6742 DSP Interrupts PRODUCT PREVIEW 60 EVT# Interrupt Name 0 EVT0 Source C674x Int Ctl 0 1 EVT1 C674x Int Ctl 1 2 EVT2 C674x Int Ctl 2 3 EVT3 C674x Int Ctl 3 4 T64P0_TINT12 5 SYSCFG_CHIPINT2 Timer64P0 - TINT12 6 - 7 EHRPWM0 8 EDMA3_0_CC0_INT1 9 EMU_DTDMA C674x-ECM 10 EHRPWM0TZ HiResTimer/PWM0 Trip Zone Interrupt 11 EMU_RTDXRX C674x-RTDX 12 EMU_RTDXTX C674x-RTDX 13 IDMAINT0 C674x-EMC 14 IDMAINT1 C674x-EMC 15 - Reserved 16 - Reserved 17 - Reserved 18 EHRPWM1 19 - Reserved 20 - Reserved 21 - Reserved 22 - Reserved 23 EHRPWM1TZ 24 - Reserved 25 - Reserved 26 - Reserved 27 - Reserved 28 - Reserved 29 - Reserved 30 - Reserved 31 - Reserved 32 - Reserved 33 - Reserved 34 UHPI_DSPINT 35 - 36 IIC0_INT SYSCFG CHIPSIG Register Reserved HiResTimer/PWM0 Interrupt EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt HiResTimer/PWM1 Interrupt HiResTimer/PWM1 Trip Zone Interrupt UHPI DSP Interrupt Reserved I2C0 37 - 38 UART0_INT 39 - 40 T64P1_TINT12 Timer64P1 Interrupt 12 41 GPIO_B1INT GPIO Bank 1 Interrupt 42 - 43 SPI1_INT 44 - 45 ECAP0 Peripheral Information and Electrical Specifications Reserved UART0 Reserved Reserved SPI1 Reserved ECAP0 Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-5. C6742 DSP Interrupts (continued) EVT# Interrupt Name 46 - 47 ECAP1 48 T64P1_TINT34 Timer64P1 Interrupt 34 49 GPIO_B2INT GPIO Bank 2 Interrupt 50 ECAP2 52 GPIO_B3INT 53 - 54 GPIO_B4INT Reserved ECAP1 Reserved ECAP2 GPIO Bank 3 Interrupt Reserved GPIO Bank 4 Interrupt 55 EMIFA_INT 56 EDMA3_0_CC0_ERRINT EDMA3_0 Channel Controller 0 Error Interrupt 57 EDMA3_0_TC0_ERRINT EDMA3_0 Transfer Controller 0 Error Interrupt 58 EDMA3_0_TC1_ERRINT EDMA3_0 Transfer Controller 1 Error Interrupt 59 GPIO_B5INT 60 DDR2_MEMERR 61 MCASP0_INT McASP0 Combined RX/TX Interrupts 62 GPIO_B6INT GPIO Bank 6 Interrupt 63 RTC_IRQS 64 T64P0_TINT34 Timer64P0 Interrupt 34 65 GPIO_B0INT GPIO Bank 0 Interrupt 66 - 67 SYSCFG_CHIPINT3 68 - Reserved 69 - Reserved 70 PSC0_ALLINT PSC0 71 PSC1_ALLINT PSC1 72 GPIO_B7INT 74 PROTERR 75 GPIO_B8INT 76 - Reserved 77 - Reserved 78 - Reserved 79 - Reserved 80 - Reserved 81 - Reserved 82 - Reserved 83 - Reserved 84 - Reserved 85 - Reserved 86 - Reserved 87 - Reserved 88 - Reserved 89 MCBSP1_RINT McBSP1 Receive Interrupt 90 MCBSP1_XINT McBSP1 Transmit Interrupt 91 EDMA3_1_CC0_INT1 92 EDMA3_1_CC0_ERRINT Submit Documentation Feedback EMIFA PRODUCT PREVIEW 51 Source GPIO Bank 5 Interrupt DDR2 Memory Error Interrupt RTC Combined Reserved SYSCFG_CHIPSIG Register GPIO Bank 7 Interrupt SYSCFG Protection Shared Interrupt GPIO Bank 8 Interrupt EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer Completion Interrupt EDMA3_1 Channel Controller 0 Error Interrupt Peripheral Information and Electrical Specifications 61 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-5. C6742 DSP Interrupts (continued) PRODUCT PREVIEW 62 EVT# Interrupt Name 93 EDMA3_1_TC0_ERRINT 94 - Reserved 95 - Reserved 96 INTERR C674x-Int Ctl 97 EMC_IDMAERR C674x-EMC 98 - Reserved 99 - Reserved 100 - Reserved 101 - Reserved 102 - Reserved 103 - Reserved 104 - Reserved 105 - Reserved 106 - Reserved 107 - Reserved 108 - Reserved 109 - Reserved 110 - Reserved 111 - Reserved 112 - Reserved 113 PMC_ED 114 - Reserved 115 - Reserved 116 UMC_ED1 C674x-UMC 117 UMC_ED2 C674x-UMC 118 PDC_INT C674x-PDC 119 SYS_CMPA C674x-SYS 120 PMC_CMPA C674x-PMC 121 PMC_CMPA C674x-PMC 122 DMC_CMPA C674x-DMC 123 DMC_CMPA C674x-DMC 124 UMC_CMPA C674x-UMC 125 UMC_CMPA C674x-UMC 126 EMC_CMPA C674x-EMC 127 EMC_BUSERR C674x-EMC Peripheral Information and Electrical Specifications Source EDMA3_1 Transfer Controller 0 Error Interrupt C674x-PMC Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 BYTE ADDRESS REGISTER NAME DESCRIPTION 0x0180 0000 EVTFLAG0 Event flag register 0 0x0180 0004 EVTFLAG1 Event flag register 1 0x0180 0008 EVTFLAG2 Event flag register 2 0x0180 000C EVTFLAG3 Event flag register 3 0x0180 0020 EVTSET0 Event set register 0 0x0180 0024 EVTSET1 Event set register 1 0x0180 0028 EVTSET2 Event set register 2 0x0180 002C EVTSET3 Event set register 3 0x0180 0040 EVTCLR0 Event clear register 0 0x0180 0044 EVTCLR1 Event clear register 1 0x0180 0048 EVTCLR2 Event clear register 2 0x0180 004C EVTCLR3 Event clear register 3 0x0180 0080 EVTMASK0 Event mask register 0 0x0180 0084 EVTMASK1 Event mask register 1 0x0180 0088 EVTMASK2 Event mask register 2 0x0180 008C EVTMASK3 Event mask register 3 0x0180 00A0 MEVTFLAG0 Masked event flag register 0 0x0180 00A4 MEVTFLAG1 Masked event flag register 1 0x0180 00A8 MEVTFLAG2 Masked event flag register 2 0x0180 00AC MEVTFLAG3 Masked event flag register 3 0x0180 00C0 EXPMASK0 Exception mask register 0 0x0180 00C4 EXPMASK1 Exception mask register 1 0x0180 00C8 EXPMASK2 Exception mask register 2 0x0180 00CC EXPMASK3 Exception mask register 3 0x0180 00E0 MEXPFLAG0 Masked exception flag register 0 0x0180 00E4 MEXPFLAG1 Masked exception flag register 1 0x0180 00E8 MEXPFLAG2 Masked exception flag register 2 0x0180 00EC MEXPFLAG3 Masked exception flag register 3 0x0180 0104 INTMUX1 Interrupt mux register 1 0x0180 0108 INTMUX2 Interrupt mux register 2 0x0180 010C INTMUX3 Interrupt mux register 3 0x0180 0140 - 0x0180 0144 - Reserved 0x0180 0180 INTXSTAT Interrupt exception status 0x0180 0184 INTXCLR Interrupt exception clear 0x0180 0188 INTDMASK Dropped interrupt mask register 0x0180 01C0 EVTASRT Event assert register Submit Documentation Feedback Peripheral Information and Electrical Specifications PRODUCT PREVIEW Table 6-6. C674x DSP Interrupt Controller Registers 63 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.8 Power and Sleep Controller (PSC) The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off, clock on/off, resets (device level and module level). It is used primarily to provide granular power control for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC and provides clock and reset control. PRODUCT PREVIEW The PSC includes the following features: • Provides a software interface to: – Control module clock enable/disable – Control module reset – Control CPU local reset • Supports IcePick emulation features: power, clock and reset PSC0 controls 16 local PSCs. PSC1 controls 32 local PSCs. Table 6-7. Power and Sleep Controller (PSC) Registers PSC0 BYTE ADDRESS PSC1 BYTE ADDRESS 0x01C1 0000 0x01E2 7000 REVID Peripheral Revision and Class Information Register 0x01C1 0018 0x01E2 7018 INTEVAL Interrupt Evaluation Register 0x01C1 0040 0x01E2 7040 MERRPR0 Module Error Pending Register 0 (module 0-15) (PSC0) 0x01C1 0050 0x01E2 7050 MERRCR0 0x01C1 0060 0x01E2 7060 PERRPR Power Error Pending Register 0x01C1 0068 0x01E2 7068 PERRCR Power Error Clear Register 0x01C1 0120 0x01E2 7120 PTCMD Power Domain Transition Command Register 0x01C1 0128 0x01E2 7128 PTSTAT Power Domain Transition Status Register 0x01C1 0200 0x01E2 7200 PDSTAT0 Power Domain 0 Status Register 0x01C1 0204 0x01E2 7204 PDSTAT1 Power Domain 1 Status Register 0x01C1 0300 0x01E2 7300 PDCTL0 Power Domain 0 Control Register 0x01C1 0304 0x01E2 7304 PDCTL1 Power Domain 1 Control Register 0x01C1 0400 0x01E2 7400 PDCFG0 Power Domain 0 Configuration Register 0x01C1 0404 0x01E2 7404 PDCFG1 Power Domain 1 Configuration Register 0x01C1 0800 0x01E2 7800 MDSTAT0 Module 0 Status Register 0x01C1 0804 0x01E2 7804 MDSTAT1 Module 1 Status Register 0x01C1 0808 0x01E2 7808 MDSTAT2 Module 2 Status Register 0x01C1 080C 0x01E2 780C MDSTAT3 Module 3 Status Register 0x01C1 0810 0x01E2 7810 MDSTAT4 Module 4 Status Register 0x01C1 0814 0x01E2 7814 MDSTAT5 Module 5 Status Register ACRONYM REGISTER DESCRIPTION Module Error Pending Register 0 (module 0-31) (PSC1) Module Error Clear Register 0 (module 0-15) (PSC0) Module Error Clear Register 0 (module 0-31) (PSC1) 64 0x01C1 0818 0x01E2 7818 MDSTAT6 Module 6 Status Register 0x01C1 081C 0x01E2 781C MDSTAT7 Module 7 Status Register 0x01C1 0820 0x01E2 7820 MDSTAT8 Module 8 Status Register 0x01C1 0824 0x01E2 7824 MDSTAT9 Module 9 Status Register 0x01C1 0828 0x01E2 7828 MDSTAT10 Module 10 Status Register 0x01C1 082C 0x01E2 782C MDSTAT11 Module 11 Status Register 0x01C1 0830 0x01E2 7830 MDSTAT12 Module 12 Status Register 0x01C1 0834 0x01E2 7834 MDSTAT13 Module 13 Status Register Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-7. Power and Sleep Controller (PSC) Registers (continued) PSC0 BYTE ADDRESS PSC1 BYTE ADDRESS 0x01C1 0838 0x01E2 7838 MDSTAT14 Module 14 Status Register 0x01C1 083C 0x01E2 783C MDSTAT15 Module 15 Status Register - 0x01E2 7840 MDSTAT16 Module 16 Status Register - 0x01E2 7844 MDSTAT17 Module 17 Status Register - 0x01E2 7848 MDSTAT18 Module 18 Status Register - 0x01E2 784C MDSTAT19 Module 19 Status Register - 0x01E2 7850 MDSTAT20 Module 20 Status Register - 0x01E2 7854 MDSTAT21 Module 21 Status Register - 0x01E2 7858 MDSTAT22 Module 22 Status Register - 0x01E2 785C MDSTAT23 Module 23 Status Register - 0x01E2 7860 MDSTAT24 Module 24 Status Register - 0x01E2 7864 MDSTAT25 Module 25 Status Register - 0x01E2 7868 MDSTAT26 Module 26 Status Register - 0x01E2 786C MDSTAT27 Module 27 Status Register - 0x01E2 7870 MDSTAT28 Module 28 Status Register - 0x01E2 7874 MDSTAT29 Module 29 Status Register - 0x01E2 7878 MDSTAT30 Module 30 Status Register - 0x01E2 787C MDSTAT31 Module 31 Status Register 0x01C1 0A00 0x01E2 7A00 MDCTL0 Module 0 Control Register 0x01C1 0A04 0x01E2 7A04 MDCTL1 Module 1 Control Register 0x01C1 0A08 0x01E2 7A08 MDCTL2 Module 2 Control Register 0x01C1 0A0C 0x01E2 7A0C MDCTL3 Module 3 Control Register 0x01C1 0A10 0x01E2 7A10 MDCTL4 Module 4 Control Register 0x01C1 0A14 0x01E2 7A14 MDCTL5 Module 5 Control Register REGISTER DESCRIPTION 0x01C1 0A18 0x01E2 7A18 MDCTL6 Module 6 Control Register 0x01C1 0A1C 0x01E2 7A1C MDCTL7 Module 7 Control Register 0x01C1 0A20 0x01E2 7A20 MDCTL8 Module 8 Control Register 0x01C1 0A24 0x01E2 7A24 MDCTL9 Module 9 Control Register 0x01C1 0A28 0x01E2 7A28 MDCTL10 Module 10 Control Register 0x01C1 0A2C 0x01E2 7A2C MDCTL11 Module 11 Control Register 0x01C1 0A30 0x01E2 7A30 MDCTL12 Module 12 Control Register 0x01C1 0A34 0x01E2 7A34 MDCTL13 Module 13 Control Register 0x01C1 0A38 0x01E2 7A38 MDCTL14 Module 14 Control Register 0x01C1 0A3C 0x01E2 7A3C MDCTL15 Module 15 Control Register - 0x01E2 7A40 MDCTL16 Module 16 Control Register - 0x01E2 7A44 MDCTL17 Module 17 Control Register - 0x01E2 7A48 MDCTL18 Module 18 Control Register - 0x01E2 7A4C MDCTL19 Module 19 Control Register - 0x01E2 7A50 MDCTL20 Module 20 Control Register - 0x01E2 7A54 MDCTL21 Module 21 Control Register - 0x01E2 7A58 MDCTL22 Module 22 Control Register - 0x01E2 7A5C MDCTL23 Module 23 Control Register - 0x01E2 7A60 MDCTL24 Module 24 Control Register - 0x01E2 7A64 MDCTL25 Module 25 Control Register - 0x01E2 7A68 MDCTL26 Module 26 Control Register - 0x01E2 7A6C MDCTL27 Module 27 Control Register Submit Documentation Feedback Peripheral Information and Electrical Specifications PRODUCT PREVIEW ACRONYM 65 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-7. Power and Sleep Controller (PSC) Registers (continued) PSC0 BYTE ADDRESS PSC1 BYTE ADDRESS - 0x01E2 7A70 MDCTL28 Module 28 Control Register - 0x01E2 7A74 MDCTL29 Module 29 Control Register - 0x01E2 7A78 MDCTL30 Module 30 Control Register - 0x01E2 7A7C MDCTL31 Module 31 Control Register 6.8.1 ACRONYM REGISTER DESCRIPTION Power Domain and Module Topology The device includes two PSC modules. PRODUCT PREVIEW Each PSC module controls clock states for several of the on chip modules, controllers and interconnect components. Table 6-8 and Table 6-9 lists the set of peripherals/modules that are controlled by the PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset) module states. See the device-specific data manual for the peripherals available on a given device. The module states and terminology are defined in Section 6.8.1.2. Table 6-8. PSC0 Default Module Configuration LPSC Number Module Name Power Domain Default Module State Auto Sleep/Wake Only 0 EDMA3 Channel Controller 0 AlwaysON (PD0) SwRstDisable — 1 EDMA3 Transfer Controller 0 AlwaysON (PD0) SwRstDisable — 2 EDMA3 Transfer Controller 1 AlwaysON (PD0) SwRstDisable — 3 EMIFA (Br7) AlwaysON (PD0) SwRstDisable — 4 — — — — 5 — — — — 6 — — — — 7 — — — — 8 — — — — 9 UART 0 AlwaysON (PD0) SwRstDisable — 10 SCR0 (Br 0, Br 1, Br 2, Br 8) AlwaysON (PD0) Enable Yes 11 SCR1 (Br 4) AlwaysON (PD0) Enable Yes 12 SCR2 (Br 3, Br 5, Br 6) AlwaysON (PD0) Enable Yes 13 — — — — 14 — — — — 15 DSP PD_DSP (PD1) Enable — 66 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 LPSC Number Module Name Power Domain Default Module State Auto Sleep/Wake Only 0 EDMA3 Channel Controller 1 AlwaysON (PD0) SwRstDisable — 1 — — — — 2 — — — — 3 GPIO AlwaysON (PD0) SwRstDisable — 4 UHPI AlwaysON (PD0) SwRstDisable — 5 — — — — 6 DDR2 (and SCR_F3) AlwaysON (PD0) SwRstDisable — 7 McASP0 ( + McASP0 FIFO) AlwaysON (PD0) SwRstDisable — 8 — — — — 9 — — — — 10 SPI 1 AlwaysON (PD0) SwRstDisable — 11 — — — — 12 — — — — 13 — — — — 14 — — — — 15 McBSP1 ( + McBSP1 FIFO) AlwaysON (PD0) SwRstDisable — 17 eHRPWM0/1 AlwaysON (PD0) SwRstDisable — 18 — — — — 19 — — — — 20 ECAP0/1/2 AlwaysON (PD0) SwRstDisable — 21 EDMA3 Transfer Controller 2 AlwaysON (PD0) SwRstDisable — 22 — — — — 23 — — — — 24 SCR_F0 (and bridge F0) AlwaysON (PD0) Enable Yes 25 SCR_F1 (and bridge F1) AlwaysON (PD0) Enable Yes 26 SCR_F2 (and bridge F2) AlwaysON (PD0) Enable Yes 27 SCR_F6 (and bridge F3) AlwaysON (PD0) Enable Yes 28 SCR_F7 (and bridge F4) AlwaysON (PD0) Enable Yes 29 SCR_F8 (and bridge F5) AlwaysON (PD0) Enable Yes 30 Bridge F7 (DDR Controller path) AlwaysON (PD0) Enable Yes 31 — — — — Submit Documentation Feedback Peripheral Information and Electrical Specifications PRODUCT PREVIEW Table 6-9. PSC1 Default Module Configuration 67 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.8.1.1 Power Domain States A power domain can only be in one of the two states: ON or OFF, defined as follows: • ON: power to the domain is on • OFF: power to the domain is off For both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the ON state when the chip is powered-on. This domain is not programmable to OFF state. • On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories 6.8.1.2 Module States The PSC defines several possible states for a module. This states are essentially a combination of the module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are defined in Table 6-10. PRODUCT PREVIEW Table 6-10. Module States Module State Module Reset Module Clock Module State Definition Enable De-asserted On A module in the enable state has its module reset de-asserted and it has its clock on. This is the normal operational state for a given module Disable De-asserted Off A module in the disabled state has its module reset de-asserted and it has its module clock off. This state is typically used for disabling a module clock to save power. The device is designed in full static CMOS, so when you stop a module clock, it retains the module’s state. When the clock is restarted, the module resumes operating from the stopping point. SyncReset Asserted On A module state in the SyncReset state has its module reset asserted and it has its clock on. Generally, software is not expected to initiate this state SwRstDisable Asserted Off A module in the SwResetDisable state has its module reset asserted and it has its clock disabled. After initial power-on, several modules come up in the SwRstDisable state. Generally, software is not expected to initiate this state Auto Sleep De-asserted Off A module in the Auto Sleep state also has its module reset de-asserted and its module clock disabled, similar to the Disable state. However this is a special state, once a module is configured in this state by software, it can “automatically” transition to “Enable” state whenever there is an internal read/write request made to it, and after servicing the request it will “automatically” transition into the sleep state (with module reset re de-asserted and module clock disabled), without any software intervention. The transition from sleep to enabled and back to sleep state has some cycle latency associated with it. It is not envisioned to use this mode when peripherals are fully operational and moving data. Auto Wake De-asserted Off A module in the Auto Wake state also has its module reset de-asserted and its module clock disabled, similar to the Disable state. However this is a special state, once a module is configured in this state by software, it will “automatically” transition to “Enable” state whenever there is an internal read/write request made to it, and will remain in the “Enabled” state from then on (with module reset re de-asserted and module clock on), without any software intervention. The transition from sleep to enabled state has some cycle latency associated with it. It is not envisioned to use this mode when peripherals are fully operational and moving data. 68 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.9 EDMA The EDMA controller handles all data transfers between memories and the device slave peripherals on the device. These data transfers include cache servicing, non-cacheable memory accesses, user-programmed data transfers, and host accesses. 6.9.1 EDMA3 Channel Synchronization Events Each EDMA channel controller supports up to 32 channels which service peripherals and memory. Table 6-11lists the source of the EDMA synchronization events associated with each of the programmable EDMA channels. Table 6-11. EDMA Synchronization Events Event Name / Source Event Event Name / Source 0 McASP0 Receive 16 Reserved 1 McASP0 Transmit 17 Reserved 2 Reserved 18 SPI1 Receive 3 Reserved 19 SPI1 Transmit 4 McBSP1 Receive 20 Reserved 5 McBSP1 Transmit 21 Reserved 6 GPIO Bank 0 Interrupt 22 GPIO Bank 2 Interrupt 7 GPIO Bank 1 Interrupt 23 GPIO Bank 3 Interrupt 8 UART0 Receive 24 I2C0 Receive 9 UART0 Transmit 25 I2C0 Transmit 10 Timer64P0 Event Out 12 26 Reserved 11 Timer64P0 Event Out 34 27 Reserved 12 Reserved 28 GPIO Bank 4 Interrupt 13 Reserved 29 GPIO Bank 5 Interrupt 14 Reserved 30 Reserved 15 Reserved 31 Reserved PRODUCT PREVIEW EDMA0 Channel Controller 0 Event EDMA1 Channel Controller 1 Event Event Name / Source Event Event Name / Source 0 Reserved 16 GPIO Bank 6 Interrupt 1 Reserved 17 GPIO Bank 7 Interrupt 2 Reserved 18 GPIO Bank 8 Interrupt 3 Reserved 19 Reserved 4 Reserved 20 Reserved 5 Reserved 21 Reserved 6 Reserved 22 Reserved 7 Reserved 23 Reserved 8 Reserved 24 Reserved 9 Reserved 25 Reserved 10 Reserved 26 Reserved 11 Reserved 27 Reserved 12 Reserved 28 Reserved 13 Reserved 29 Reserved 14 Reserved 30 Reserved 15 Reserved 31 Reserved Submit Documentation Feedback Peripheral Information and Electrical Specifications 69 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 6.9.2 www.ti.com EDMA Peripheral Register Descriptions Table 6-12 is the list of EDMA3 Channel Controller Registers and Table 6-13 is the list of EDMA3 Transfer Controller registers. Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers EDMA0 Channel Controller 0 BYTE ADDRESS EDMA1 Channel Controller 0 BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C0 0000 0x01E3 0000 PID 0x01C0 0004 0x01E3 0004 CCCFG 0x01C0 0200 0x01E3 0200 QCHMAP0 QDMA Channel 0 Mapping Register 0x01C0 0204 0x01E3 0204 QCHMAP1 QDMA Channel 1 Mapping Register Peripheral Identification Register EDMA3CC Configuration Register Global Registers PRODUCT PREVIEW 0x01C0 0208 0x01E3 0208 QCHMAP2 QDMA Channel 2 Mapping Register 0x01C0 020C 0x01E3 020C QCHMAP3 QDMA Channel 3 Mapping Register 0x01C0 0210 0x01E3 0210 QCHMAP4 QDMA Channel 4 Mapping Register 0x01C0 0214 0x01E3 0214 QCHMAP5 QDMA Channel 5 Mapping Register 0x01C0 0218 0x01E3 0218 QCHMAP6 QDMA Channel 6 Mapping Register 0x01C0 021C 0x01E3 021C QCHMAP7 QDMA Channel 7 Mapping Register 0x01C0 0240 0x01E3 0240 DMAQNUM0 DMA Channel Queue Number Register 0 0x01C0 0244 0x01E3 0244 DMAQNUM1 DMA Channel Queue Number Register 1 0x01C0 0248 0x01E3 0248 DMAQNUM2 DMA Channel Queue Number Register 2 0x01C0 024C 0x01E3 024C DMAQNUM3 DMA Channel Queue Number Register 3 0x01C0 0260 0x01E3 0260 QDMAQNUM QDMA Channel Queue Number Register 0x01C0 0284 0x01E3 0284 0x01C0 0300 0x01E3 0300 EMR 0x01C0 0308 0x01E3 0308 EMCR Event Missed Clear Register 0x01C0 0310 0x01E3 0310 QEMR QDMA Event Missed Register 0x01C0 0314 0x01E3 0314 QEMCR QDMA Event Missed Clear Register 0x01C0 0318 0x01E3 0318 CCERR EDMA3CC Error Register 0x01C0 031C 0x01E3 031C CCERRCLR 0x01C0 0320 0x01E3 0320 EEVAL Error Evaluate Register 0x01C0 0340 0x01E3 0340 DRAE0 DMA Region Access Enable Register for Region 0 0x01C0 0348 0x01E3 0348 DRAE1 DMA Region Access Enable Register for Region 1 0x01C0 0350 0x01E3 0350 DRAE2 DMA Region Access Enable Register for Region 2 0x01C0 0358 0x01E3 0358 DRAE3 DMA Region Access Enable Register for Region 3 0x01C0 0380 0x01E3 0380 QRAE0 QDMA Region Access Enable Register for Region 0 0x01C0 0384 0x01E3 0384 QRAE1 QDMA Region Access Enable Register for Region 1 0x01C0 0388 0x01E3 0388 QRAE2 QDMA Region Access Enable Register for Region 2 0x01C0 038C 0x01E3 038C QRAE3 QDMA Region Access Enable Register for Region 3 0x01C0 0400 - 0x01C0 043C 0x01E3 0400 - 0x01E3 043C Q0E0-Q0E15 Event Queue Entry Registers Q0E0-Q0E15 0x01C0 0440 - 0x01C0 047C 0x01E3 0440 - 0x01E3 047C Q1E0-Q1E15 Event Queue Entry Registers Q1E0-Q1E15 0x01C0 0600 0x01E3 0600 0x01C0 0604 0x01C0 0620 0x01C0 0640 QUEPRI Queue Priority Register (1) Event Missed Register EDMA3CC Error Clear Register QSTAT0 Queue 0 Status Register 0x01E3 0604 QSTAT1 Queue 1 Status Register 0x01E3 0620 QWMTHRA 0x01E3 0640 CCSTAT Queue Watermark Threshold A Register EDMA3CC Status Register Global Channel Registers (1) 70 On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority. Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers (continued) EDMA0 Channel Controller 0 BYTE ADDRESS EDMA1 Channel Controller 0 BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C0 1000 0x01E3 1000 ER 0x01C0 1008 0x01E3 1008 ECR Event Clear Register 0x01C0 1010 0x01E3 1010 ESR Event Set Register 0x01C0 1018 0x01E3 1018 CER Chained Event Register 0x01C0 1020 0x01E3 1020 EER Event Enable Register 0x01C0 1028 0x01E3 1028 EECR Event Enable Clear Register 0x01C0 1030 0x01E3 1030 EESR Event Enable Set Register 0x01C0 1038 0x01E3 1038 SER Secondary Event Register 0x01C0 1040 0x01E3 1040 SECR 0x01C0 1050 0x01E3 1050 IER 0x01C0 1058 0x01E3 1058 IECR Interrupt Enable Clear Register 0x01C0 1060 0x01E3 1060 IESR Interrupt Enable Set Register 0x01C0 1068 0x01E3 1068 IPR Interrupt Pending Register 0x01C0 1070 0x01E3 1070 ICR Interrupt Clear Register 0x01C0 1078 0x01E3 1078 IEVAL 0x01C0 1080 0x01E3 1080 QER 0x01C0 1084 0x01E3 1084 QEER Event Register PRODUCT PREVIEW Secondary Event Clear Register Interrupt Enable Register Interrupt Evaluate Register QDMA Event Register QDMA Event Enable Register 0x01C0 1088 0x01E3 1088 QEECR QDMA Event Enable Clear Register 0x01C0 108C 0x01E3 108C QEESR QDMA Event Enable Set Register 0x01C0 1090 0x01E3 1090 QSER QDMA Secondary Event Register 0x01C0 1094 0x01E3 1094 QSECR QDMA Secondary Event Clear Register Shadow Region 0 Channel Registers 0x01C0 2000 0x01E3 2000 ER 0x01C0 2008 0x01E3 2008 ECR Event Register Event Clear Register 0x01C0 2010 0x01E3 2010 ESR Event Set Register 0x01C0 2018 0x01E3 2018 CER Chained Event Register 0x01C0 2020 0x01E3 2020 EER Event Enable Register 0x01C0 2028 0x01E3 2028 EECR Event Enable Clear Register 0x01C0 2030 0x01E3 2030 EESR Event Enable Set Register 0x01C0 2038 0x01E3 2038 SER Secondary Event Register 0x01C0 2040 0x01E3 2040 SECR 0x01C0 2050 0x01E3 2050 IER 0x01C0 2058 0x01E3 2058 IECR Interrupt Enable Clear Register 0x01C0 2060 0x01E3 2060 IESR Interrupt Enable Set Register 0x01C0 2068 0x01E3 2068 IPR Interrupt Pending Register 0x01C0 2070 0x01E3 2070 ICR Interrupt Clear Register 0x01C0 2078 0x01E3 2078 IEVAL 0x01C0 2080 0x01E3 2080 QER 0x01C0 2084 0x01E3 2084 QEER 0x01C0 2088 0x01E3 2088 QEECR QDMA Event Enable Clear Register 0x01C0 208C 0x01E3 208C QEESR QDMA Event Enable Set Register 0x01C0 2090 0x01E3 2090 QSER QDMA Secondary Event Register 0x01C0 2094 0x01E3 2094 QSECR Secondary Event Clear Register Interrupt Enable Register Interrupt Evaluate Register QDMA Event Register QDMA Event Enable Register QDMA Secondary Event Clear Register Shadow Region 1 Channel Registers 0x01C0 2200 0x01E3 2200 ER 0x01C0 2208 0x01E3 2208 ECR Submit Documentation Feedback Event Register Event Clear Register Peripheral Information and Electrical Specifications 71 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers (continued) PRODUCT PREVIEW EDMA0 Channel Controller 0 BYTE ADDRESS EDMA1 Channel Controller 0 BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C0 2210 0x01E3 2210 ESR Event Set Register 0x01C0 2218 0x01E3 2218 CER Chained Event Register 0x01C0 2220 0x01E3 2220 EER Event Enable Register 0x01C0 2228 0x01E3 2228 EECR Event Enable Clear Register 0x01C0 2230 0x01E3 2230 EESR Event Enable Set Register 0x01C0 2238 0x01E3 2238 SER Secondary Event Register 0x01C0 2240 0x01E3 2240 SECR 0x01C0 2250 0x01E3 2250 IER 0x01C0 2258 0x01E3 2258 IECR Interrupt Enable Clear Register 0x01C0 2260 0x01E3 2260 IESR Interrupt Enable Set Register 0x01C0 2268 0x01E3 2268 IPR Interrupt Pending Register 0x01C0 2270 0x01E3 2270 ICR Interrupt Clear Register 0x01C0 2278 0x01E3 2278 IEVAL 0x01C0 2280 0x01E3 2280 QER 0x01C0 2284 0x01E3 2284 QEER 0x01C0 2288 0x01E3 2288 QEECR QDMA Event Enable Clear Register 0x01C0 228C 0x01E3 228C QEESR QDMA Event Enable Set Register 0x01C0 2290 0x01E3 2290 QSER QDMA Secondary Event Register 0x01C0 2294 0x01E3 2294 QSECR 0x01C0 4000 - 0x01C0 4FFF 0x01E3 4000 - 0x01E3 4FFF — Secondary Event Clear Register Interrupt Enable Register Interrupt Evaluate Register QDMA Event Register QDMA Event Enable Register QDMA Secondary Event Clear Register Parameter RAM (PaRAM) Table 6-13. EDMA3 Transfer Controller (EDMA3TC) Registers EDMA0 Transfer Controller 0 BYTE ADDRESS EDMA0 Transfer Controller 1 BYTE ADDRESS EDMA1 Transfer Controller 0 BYTE ADDRESS 0x01C0 8000 0x01C0 8400 0x01E3 8000 PID Peripheral Identification Register 0x01C0 8004 0x01C0 8404 0x01E3 8004 TCCFG EDMA3TC Configuration Register 0x01C0 8100 0x01C0 8500 0x01E3 8100 TCSTAT EDMA3TC Channel Status Register 0x01C0 8120 0x01C0 8520 0x01E3 8120 ERRSTAT Error Status Register 0x01C0 8124 0x01C0 8524 0x01E3 8124 ERREN Error Enable Register 72 ACRONYM REGISTER DESCRIPTION 0x01C0 8128 0x01C0 8528 0x01E3 8128 ERRCLR Error Clear Register 0x01C0 812C 0x01C0 852C 0x01E3 812C ERRDET Error Details Register 0x01C0 8130 0x01C0 8530 0x01E3 8130 ERRCMD Error Interrupt Command Register 0x01C0 8140 0x01C0 8540 0x01E3 8140 RDRATE Read Command Rate Register 0x01C0 8240 0x01C0 8640 0x01E3 8240 SAOPT Source Active Options Register 0x01C0 8244 0x01C0 8644 0x01E3 8244 SASRC Source Active Source Address Register 0x01C0 8248 0x01C0 8648 0x01E3 8248 SACNT Source Active Count Register 0x01C0 824C 0x01C0 864C 0x01E3 824C SADST Source Active Destination Address Register 0x01C0 8250 0x01C0 8650 0x01E3 8250 SABIDX Source Active B-Index Register 0x01C0 8254 0x01C0 8654 0x01E3 8254 SAMPPRXY Source Active Memory Protection Proxy Register Source Active Count Reload Register 0x01C0 8258 0x01C0 8658 0x01E3 8258 SACNTRLD 0x01C0 825C 0x01C0 865C 0x01E3 825C SASRCBREF Source Active Source Address B-Reference Register 0x01C0 8260 0x01C0 8660 0x01E3 8260 SADSTBREF Source Active Destination Address B-Reference Register 0x01C0 8280 0x01C0 8680 0x01E3 8280 DFCNTRLD 0x01C0 8284 0x01C0 8684 0x01E3 8284 DFSRCBREF Peripheral Information and Electrical Specifications Destination FIFO Set Count Reload Register Destination FIFO Set Source Address B-Reference Register Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-13. EDMA3 Transfer Controller (EDMA3TC) Registers (continued) EDMA0 Transfer Controller 0 BYTE ADDRESS EDMA0 Transfer Controller 1 BYTE ADDRESS EDMA1 Transfer Controller 0 BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C0 8288 0x01C0 8688 0x01E3 8288 DFDSTBREF 0x01C0 8300 0x01C0 8700 0x01E3 8300 DFOPT0 Destination FIFO Options Register 0 0x01C0 8304 0x01C0 8704 0x01E3 8304 DFSRC0 Destination FIFO Source Address Register 0 0x01C0 8308 0x01C0 8708 0x01E3 8308 DFCNT0 Destination FIFO Count Register 0 0x01C0 830C 0x01C0 870C 0x01E3 830C DFDST0 Destination FIFO Destination Address Register 0 0x01C0 8310 0x01C0 8710 0x01E3 8310 DFBIDX0 Destination FIFO B-Index Register 0 0x01C0 8314 0x01C0 8714 0x01E3 8314 DFMPPRXY0 0x01C0 8340 0x01C0 8740 0x01E3 8340 DFOPT1 Destination FIFO Options Register 1 0x01C0 8344 0x01C0 8744 0x01E3 8344 DFSRC1 Destination FIFO Source Address Register 1 Destination FIFO Set Destination Address B-Reference Register 0x01C0 8348 0x01C0 8748 0x01E3 8348 DFCNT1 Destination FIFO Count Register 1 0x01C0 834C 0x01C0 874C 0x01E3 834C DFDST1 Destination FIFO Destination Address Register 1 0x01C0 8350 0x01C0 8750 0x01E3 8350 DFBIDX1 Destination FIFO B-Index Register 1 0x01C0 8354 0x01C0 8754 0x01E3 8354 DFMPPRXY1 0x01C0 8380 0x01C0 8780 0x01E3 8380 DFOPT2 Destination FIFO Options Register 2 0x01C0 8384 0x01C0 8784 0x01E3 8384 DFSRC2 Destination FIFO Source Address Register 2 PRODUCT PREVIEW Destination FIFO Memory Protection Proxy Register 0 Destination FIFO Memory Protection Proxy Register 1 0x01C0 8388 0x01C0 8788 0x01E3 8388 DFCNT2 Destination FIFO Count Register 2 0x01C0 838C 0x01C0 878C 0x01E3 838C DFDST2 Destination FIFO Destination Address Register 2 0x01C0 8390 0x01C0 8790 0x01E3 8390 DFBIDX2 Destination FIFO B-Index Register 2 0x01C0 8394 0x01C0 8794 0x01E3 8394 DFMPPRXY2 0x01C0 83C0 0x01C0 87C0 0x01E3 83C0 DFOPT3 Destination FIFO Options Register 3 0x01C0 83C4 0x01C0 87C4 0x01E3 83C4 DFSRC3 Destination FIFO Source Address Register 3 0x01C0 83C8 0x01C0 87C8 0x01E3 83C8 DFCNT3 Destination FIFO Count Register 3 0x01C0 83CC 0x01C0 87CC 0x01E3 83CC DFDST3 Destination FIFO Destination Address Register 3 0x01C0 83D0 0x01C0 87D0 0x01E3 83D0 DFBIDX3 Destination FIFO B-Index Register 3 0x01C0 83D4 0x01C0 87D4 0x01E3 83D4 DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 2 Destination FIFO Memory Protection Proxy Register 3 Table 6-14 shows an abbreviation of the set of registers which make up the parameter set for each of 128 EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-15 shows the parameter set entry registers with relative memory address locations within each of the parameter sets. Table 6-14. EDMA Parameter Set RAM EDMA0 Channel Controller 0 BYTE ADDRESS RANGE EDMA1 Channel Controller 0 BYTE ADDRESS RANGE 0x01C0 4000 - 0x01C0 401F 0x01E3 4000 - 0x01E3 401F Parameters Set 0 (8 32-bit words) DESCRIPTION 0x01C0 4020 - 0x01C0 403F 0x01E3 4020 - 0x01E3 403F Parameters Set 1 (8 32-bit words) 0x01C0 4040 - 0x01CC0 405F 0x01E3 4040 - 0x01CE3 405F Parameters Set 2 (8 32-bit words) 0x01C0 4060 - 0x01C0 407F 0x01E3 4060 - 0x01E3 407F Parameters Set 3 (8 32-bit words) 0x01C0 4080 - 0x01C0 409F 0x01E3 4080 - 0x01E3 409F Parameters Set 4 (8 32-bit words) 0x01C0 40A0 - 0x01C0 40BF 0x01E3 40A0 - 0x01E3 40BF Parameters Set 5 (8 32-bit words) ... ... 0x01C0 4FC0 - 0x01C0 4FDF 0x01E3 4FC0 - 0x01E3 4FDF Parameters Set 126 (8 32-bit words) 0x01C0 4FE0 - 0x01C0 4FFF 0x01E3 4FE0 - 0x01E3 4FFF Parameters Set 127 (8 32-bit words) Submit Documentation Feedback ... Peripheral Information and Electrical Specifications 73 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-15. Parameter Set Entries OFFSET BYTE ADDRESS WITHIN THE PARAMETER SET ACRONYM PARAMETER ENTRY 0x0000 OPT Option 0x0004 SRC Source Address 0x0008 A_B_CNT 0x000C DST 0x0010 SRC_DST_BIDX Source B Index, Destination B Index 0x0014 LINK_BCNTRLD Link Address, B Count Reload 0x0018 SRC_DST_CIDX Source C Index, Destination C Index 0x001C CCNT A Count, B Count Destination Address C Count PRODUCT PREVIEW 74 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.10 External Memory Interface A (EMIFA) EMIFA is one of two external memory interfaces supported on the device. It is primarily intended to support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However on this device, EMIFA also provides a secondary interface to SDRAM. 6.10.1 EMIFA Asynchronous Memory Support The EMIFA data bus width is up to 16-bits.The device supports up to 24 address lines and two external wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIFA (EMA_CS[5:2]). Each chip select has the following individually programmable attributes: • Data Bus Width • Read cycle timings: setup, hold, strobe • Write cycle timings: setup, hold, strobe • Bus turn around time • Extended Wait Option With Programmable Timeout • Select Strobe Option • NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes. 6.10.2 EMIFA Synchronous DRAM Memory Support The device supports 16-bit SDRAM in addition to the asynchronous memories listed in Section 6.10.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are supported are: • One, Two, and Four Bank SDRAM devices • Devices with Eight, Nine, Ten, and Eleven Column Address • CAS Latency of two or three clock cycles • Sixteen Bit Data Bus Width Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory contents; since the SDRAM will continue to refresh itself even without clocks from the device. Powerdown mode achieves even lower power, except the device must periodically wake the SDRAM up and issue refreshes if data retention is required. Finally, note that the EMIFA does not support Mobile SDRAM devices. Table 6-16 shows the supported SDRAM configurations for EMIFA. Submit Documentation Feedback Peripheral Information and Electrical Specifications 75 PRODUCT PREVIEW EMIFA supports asynchronous: • SRAM memories • NAND Flash memories • NOR Flash memories TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-16. EMIFA Supported SDRAM Configurations (1) SDRAM Memory Data Bus Width (bits) 16 PRODUCT PREVIEW 8 (1) Number of Memories EMIFA Data Bus Size (bits) Rows Columns Banks Total Memory (Mbits) Total Memory (Mbytes) Memory Density (Mbits) 1 16 16 8 1 256 32 256 1 16 16 8 2 512 64 512 1 16 16 8 4 1024 128 1024 1 16 16 9 1 512 64 512 1 16 16 9 2 1024 128 1024 1 16 16 9 4 2048 256 2048 1 16 16 10 1 1024 128 1024 1 16 16 10 2 2048 256 2048 1 16 16 10 4 4096 512 4096 1 16 16 11 1 2048 256 2048 1 16 16 11 2 4096 512 4096 1 16 15 11 4 4096 512 4096 2 16 16 8 1 256 32 128 2 16 16 8 2 512 64 256 2 16 16 8 4 1024 128 512 2 16 16 9 1 512 64 256 2 16 16 9 2 1024 128 512 2 16 16 9 4 2048 256 1024 2 16 16 10 1 1024 128 512 2 16 16 10 2 2048 256 1024 2 16 16 10 4 4096 512 2048 2 16 16 11 1 2048 256 1024 2 16 16 11 2 4096 512 2048 2 16 15 11 4 4096 512 2048 The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of supporting these densities are not available in the market. 6.10.3 EMIFA SDRAM Loading Limitations EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads. Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by board simulation using IBIS models. 76 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.10.5 External Memory Interface Register Descriptions Table 6-17 is a list of the EMIF registers. For more information about these registers, see the C674x DSP External Memory Interface (EMIF) User's Guide (literature number SPRUFL6). Table 6-17. External Memory Interface (EMIFA) Registers ACRONYM REGISTER DESCRIPTION 0x6800 0000 MIDR Module ID Register 0x6800 0004 AWCC Asynchronous Wait Cycle Configuration Register 0x6800 0008 SDCR SDRAM Configuration Register 0x6800 000C SDRCR SDRAM Refresh Control Register 0x6800 0010 CE2CFG Asynchronous 1 Configuration Register 0x6800 0014 CE3CFG Asynchronous 2 Configuration Register 0x6800 0018 CE4CFG Asynchronous 3 Configuration Register 0x6800 001C CE5CFG Asynchronous 4 Configuration Register 0x6800 0020 SDTIMR SDRAM Timing Register 0x6800 003C SDSRETR 0x6800 0040 INTRAW EMIFA Interrupt Raw Register 0x6800 0044 INTMSK EMIFA Interrupt Mask Register 0x6800 0048 INTMSKSET EMIFA Interrupt Mask Set Register 0x6800 004C INTMSKCLR EMIFA Interrupt Mask Clear Register 0x6800 0060 NANDFCR NAND Flash Control Register 0x6800 0064 NANDFSR NAND Flash Status Register 0x6800 0070 NANDF1ECC NAND Flash 1 ECC Register (CS2 Space) 0x6800 0074 NANDF2ECC NAND Flash 2 ECC Register (CS3 Space) 0x6800 0078 NANDF3ECC NAND Flash 3 ECC Register (CS4 Space) 0x6800 007C NANDF4ECC NAND Flash 4 ECC Register (CS5 Space) 0x6800 00BC NAND4BITECCLOAD 0x6800 00C0 NAND4BITECC1 NAND Flash 4-Bit ECC Register 1 0x6800 00C4 NAND4BITECC2 NAND Flash 4-Bit ECC Register 2 0x6800 00C8 NAND4BITECC3 NAND Flash 4-Bit ECC Register 3 0x6800 00CC NAND4BITECC4 NAND Flash 4-Bit ECC Register 4 0x6800 00D0 NANDERRADD1 NAND Flash 4-Bit ECC Error Address Register 1 0x6800 00D4 NANDERRADD2 NAND Flash 4-Bit ECC Error Address Register 2 0x6800 00D8 NANDERRVAL1 NAND Flash 4-Bit ECC Error Value Register 1 0x6800 00DC NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register 2 Submit Documentation Feedback PRODUCT PREVIEW BYTE ADDRESS SDRAM Self Refresh Exit Timing Register NAND Flash 4-Bit ECC Load Register Peripheral Information and Electrical Specifications 77 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.10.6 EMIFA Electrical Data/Timing Table 6-18 through Table 6-21 assume testing over recommended operating conditions. Table 6-18. Timing Requirements for EMIFA SDRAM Interface NO. PARAMETER 19 tsu(EMA_DV-EM_CLKH) Input setup time, read data valid on EMA_D[31:0] before EMA_CLK rising 20 th(CLKH-DIV) Input hold time, read data valid on EMA_D[31:0] after EMA_CLK rising 1.2V MIN 1.1V MAX MIN MAX 1.0V MIN MAX UNIT 2 3 3 ns 1.6 1.6 1.6 ns Table 6-19. Switching Characteristics for EMIFA SDRAM Interface PRODUCT PREVIEW NO. PARAMETER 1.2V MIN 1.1V MAX MIN MAX 1.0V MIN MAX UNIT 1 tc(CLK) Cycle time, EMIF clock EMA_CLK 10 15 20 ns 2 tw(CLK) Pulse width, EMIF clock EMA_CLK high or low 3 5 8 ns 3 td(CLKH-CSV) Delay time, EMA_CLK rising to EMA_CS[0] valid 4 toh(CLKH-CSIV) Output hold time, EMA_CLK rising to EMA_CS[0] invalid 5 td(CLKH-DQMV) Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid 6 toh(CLKH-DQMIV) Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid 7 td(CLKH-AV) Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0] valid 8 toh(CLKH-AIV) Output hold time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0] invalid 9 td(CLKH-DV) Delay time, EMA_CLK rising to EMA_D[15:0] valid 10 toh(CLKH-DIV) Output hold time, EMA_CLK rising to EMA_D[15:0] invalid 11 td(CLKH-RASV) Delay time, EMA_CLK rising to EMA_RAS valid 12 toh(CLKH-RASIV) Output hold time, EMA_CLK rising to EMA_RAS invalid 13 td(CLKH-CASV) Delay time, EMA_CLK rising to EMA_CAS valid 14 toh(CLKH-CASIV) Output hold time, EMA_CLK rising to EMA_CAS invalid 15 td(CLKH-WEV) Delay time, EMA_CLK rising to EMA_WE valid 16 toh(CLKH-WEIV) Output hold time, EMA_CLK rising to EMA_WE invalid 17 tdis(CLKH-DHZ) Delay time, EMA_CLK rising to EMA_D[15:0] tri-stated 18 tena(CLKH-DLZ) Output hold time, EMA_CLK rising to EMA_D[15:0] driving 78 Peripheral Information and Electrical Specifications 7 1 9.5 1 7 1 9.5 1 7 1 9.5 7 1 1 1 1 1 1 7 1 1 1 7 1 ns ns 13 1 ns ns 13 9.5 1 ns ns 13 9.5 ns ns 13 9.5 ns ns 13 9.5 7 1 1 1 7 ns ns 13 9.5 ns ns 13 1 1 1 13 1 ns ns Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 1 BASIC SDRAM WRITE OPERATION 2 2 EMA_CLK 3 4 EMA_CS[0] 5 6 EMA_WE_DQM[1:0] 7 8 7 8 EMA_BA[1:0] EMA_A[12:0] PRODUCT PREVIEW 9 10 EMA_D[15:0] 11 12 EMA_RAS 13 EMA_CAS 15 16 EMA_WE Figure 6-12. EMIFA Basic SDRAM Write Operation BASIC SDRAM READ OPERATION 1 2 2 EMA_CLK 3 4 EMA_CS[0] 5 6 EMA_WE_DQM[1:0] 7 8 7 8 EMA_BA[1:0] EMA_A[12:0] 19 17 20 2 EM_CLK Delay 18 EMA_D[15:0] 11 12 EMA_RAS 13 14 EMA_CAS EMA_WE Figure 6-13. EMIFA Basic SDRAM Read Operation Submit Documentation Feedback Peripheral Information and Electrical Specifications 79 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com (1) Table 6-20. Timing Requirements for EMIFA Asynchronous Memory Interface NO. 1.2V PARAMETER MIN 1.1V MAX MIN 1.0V MAX MIN MAX UNIT READS and WRITES 2 tw(EM_WAIT) Pulse duration, EM_WAIT assertion and deassertion 2E 2E 2E ns READS 12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high 13 th(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high tsu(EMOEL-EMWAIT) Setup Time, EM_WAIT asserted before end of Strobe Phase (2) tsu(EMWEL-EMWAIT) Setup Time, EM_WAIT asserted before end of Strobe Phase (2) 14 3 TBD TBD ns 0.5 TBD TBD ns 4E+3 4E+3 4E+3 ns 4E+3 4E+3 4E+3 ns WRITES 28 PRODUCT PREVIEW (1) (2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns. Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. Table 6-21. Switching Characteristics for EMIFA Asynchronous Memory Interface NO . (1) (2) (3) 1.2V, 1.1V, 1.0V PARAMETER MIN Nom UNIT MAX READS and WRITES 1 td(TURNAROUND) Turn around time (TA)*E - 3 (TA)*E (TA)*E + 3 ns EMIF read cycle time (EW = 0) (RS+RST+RH)*E -3 (RS+RST+RH)*E (RS+RST+RH)*E +3 ns EMIF read cycle time (EW = 1) (RS+RST+RH+(E WC*16))*E - 3 (RS+RST+RH+(EW (RS+RST+RH+(E C*16))*E WC*16))*E + 3 ns READS 3 4 5 tc(EMRCYCLE) tsu(EMCEL-EMOEL) th(EMOEH-EMCEH) Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 0) (RS)*E-3 (RS)*E (RS)*E+3 ns Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 1) -3 0 +3 ns Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 0) (RH)*E - 3 (RH)*E (RH)*E + 3 ns Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 1) -3 0 +3 ns 6 tsu(EMBAV-EMOEL) Output setup time, EMA_BA[1:0] valid to EMA_OE low (RS)*E-3 (RS)*E (RS)*E+3 ns 7 th(EMOEH-EMBAIV) Output hold time, EMA_OE high to EMA_BA[1:0] invalid (RH)*E-3 (RH)*E (RH)*E+3 ns 8 tsu(EMBAV-EMOEL) Output setup time, EMA_A[13:0] valid to EMA_OE low (RS)*E-3 (RS)*E (RS)*E+3 ns 9 th(EMOEH-EMAIV) Output hold time, EMA_OE high to EMA_A[13:0] invalid (RH)*E-3 (RH)*E (RH)*E+3 ns EMA_OE active low width (EW = 0) (RST)*E-3 (RST)*E (RST)*E+3 ns 10 tw(EMOEL) EMA_OE active low width (EW = 1) (RST+(EWC*16)) *E-3 (RST+(EWC*16))*E (RST+(EWC*16)) *E+3 ns (1) (2) (3) 80 TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256]. E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns. EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-21. Switching Characteristics for EMIFA Asynchronous Memory Interface (continued) NO . 11 1.2V, 1.1V, 1.0V PARAMETER td(EMWAITHEMOEH) MIN Delay time from EMA_WAIT deasserted to EMA_OE high Nom UNIT MAX 3E-3 4E 4E+3 ns EMIF write cycle time (EW = 0) (WS+WST+WH)* E-3 (WS+WST+WH)*E (WS+WST+WH)* E+3 ns EMIF write cycle time (EW = 1) (WS+WST+WH+( EWC*16))*E - 3 (WS+WST+WH+(E (WS+WST+WH+( WC*16))*E EWC*16))*E + 3 ns 15 16 17 18 tc(EMWCYCLE) tsu(EMCEL-EMWEL) th(EMWEH-EMCEH) tsu(EMDQMVEMWEL) 19 th(EMWEHEMDQMIV) Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 0) (WS)*E - 3 (WS)*E (WS)*E + 3 ns Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 1) -3 0 +3 ns Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 0) (WH)*E-3 (WH)*E (WH)*E+3 ns Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 1) -3 0 +3 ns Output setup time, EMA_BA[1:0] valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns Output hold time, EMA_WE high to EMA_BA[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns 20 tsu(EMBAV-EMWEL) Output setup time, EMA_BA[1:0] valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns 21 th(EMWEH-EMBAIV) Output hold time, EMA_WE high to EMA_BA[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns 22 tsu(EMAV-EMWEL) Output setup time, EMA_A[13:0] valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns 23 th(EMWEH-EMAIV) Output hold time, EMA_WE high to EMA_A[13:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns EMA_WE active low width (EW = 0) (WST)*E-3 (WST)*E (WST)*E+3 ns 24 tw(EMWEL) EMA_WE active low width (EW = 1) (WST+(EWC*16)) *E-3 (WST+(EWC*16)) (WST+(EWC*16))*E *E+3 ns 25 td(EMWAITHEMWEH) Delay time from EMA_WAIT deasserted to EMA_WE high 3E-3 4E 4E+3 ns 26 tsu(EMDV-EMWEL) Output setup time, EMA_D[15:0] valid to EMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns 27 th(EMWEH-EMDIV) Output hold time, EMA_WE high to EMA_D[15:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns Submit Documentation Feedback Peripheral Information and Electrical Specifications PRODUCT PREVIEW WRITES 81 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 3 1 EMA_CE[5:2] EMA_BA[1:0] EMA_A[12:0] EMA_WE_DQM[1:0] PRODUCT PREVIEW 4 8 5 9 6 29 7 30 10 EMA_OE 13 12 EMA_D[15:0] EMA_WE Figure 6-14. Asynchronous Memory Read Timing for EMIFA 15 1 EMA_CE[5:2] EMA_BA[1:0] EMA_A[12:0] EMA_WE_DQM[1:0] 16 17 18 19 20 22 24 21 23 EMA_WE 27 26 EMA_D[15:0] EMA_OE Figure 6-15. Asynchronous Memory Write Timing for EMIFA 82 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 EMA_CE[5:2] SETUP STROBE Extended Due to EMA_WAIT STROBE HOLD EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] 14 11 EMA_OE EMA_WAIT Asserted 2 Deasserted PRODUCT PREVIEW 2 Figure 6-16. EMA_WAIT Read Timing Requirements EMA_CE[5:2] SETUP STROBE Extended Due to EMA_WAIT STROBE HOLD EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] 28 25 EMA_WE 2 EMA_WAIT Asserted 2 Deasserted Figure 6-17. EMA_WAIT Write Timing Requirements Submit Documentation Feedback Peripheral Information and Electrical Specifications 83 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.11 DDR2/mDDR Controller The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices. The DDR2/mDDR Memory Controller support the following features: • • • • • PRODUCT PREVIEW • • • • • • • • • • • • • JESD79D-2A standard compliant DDR2 SDRAM Mobile DDR SDRAM 512 MByte memory space for DDR2 256 MByte memory space for mDDR CAS latencies: – DDR2: 2, 3, 4 and 5 – mDDR: 2 and 3 Internal banks: – DDR2: 1, 2, 4 and 8 – mDDR:1, 2 and 4 Burst length: 8 Burst type: sequential 1 chip select (CS) signal Page sizes: 256, 512, 1024 and 2048 SDRAM autoinitialization Self-refresh mode Partial array self-refresh (for mDDR) Power down mode Prioritized refresh Programmable refresh rate and backlog counter Programmable timing parameters Little endian 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing Table 6-22. Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR Memory Controller No. 1 PARAMETER tc(DDR_CLK) Cycle time, DDR_CLKP / DDR_CLKN (1) DDR2 is not supported at this voltage operating point. 84 Peripheral Information and Electrical Specifications 1.2V 1.1V 1.0V MIN MAX MIN MAX MIN MAX DDR2 125 150 125 150 — (1) — (1) mDDR 100 133 100 133 100 133 UNIT MHz Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.11.2 DDR2/mDDR Controller Register Description(s) Table 6-23. DDR2/mDDR Controller Registers ACRONYM REGISTER DESCRIPTION 0xB000 0000 REVID Revision ID Register 0xB000 0004 SDRSTAT SDRAM Status Register 0xB000 0008 SDCR SDRAM Configuration Register 0xB000 000C SDRCR SDRAM Refresh Control Register 0xB000 0010 SDTIMR1 SDRAM Timing Register 1 0xB000 0014 SDTIMR2 SDRAM Timing Register 2 0xB000 001C SDCR2 SDRAM Configuration Register 2 0xB000 0020 PBBPR Peripheral Bus Burst Priority Register 0xB000 0040 PC1 Performance Counter 1 Registers 0xB000 0044 PC2 Performance Counter 2 Register 0xB000 0048 PCC Performance Counter Configuration Register 0xB000 004C PCMRS Performance Counter Master Region Select Register 0xB000 0050 PCT Performance Counter Time Register 0xB000 00C0 IRR Interrupt Raw Register 0xB000 00C4 IMR Interrupt Mask Register 0xB000 00C8 IMSR Interrupt Mask Set Register 0xB000 00CC IMCR Interrupt Mask Clear Register 0xB000 00E4 DRPYC1R DDR PHY Control Register 1 0x01E2 C000 VTPIO_CTL VTP IO Control Register 6.11.3 DDR2/mDDR Interface This section provides the timing specification for the DDR2/mDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0). 6.11.3.1 DDR2/mDDR Interface Schematic Figure 6-18 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The dual-memory system shown in Figure 6-19. Pin numbers for the device can be obtained from the pin description section. Submit Documentation Feedback Peripheral Information and Electrical Specifications 85 PRODUCT PREVIEW BYTE ADDRESS TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com DDR2/mDDR Memory Controller DDR2/mDDR ODT DDR_D[0] T DQ0 DDR_D[7] T DQ7 DDR_DQM[0] DDR_DQS[0] T T LDM LDQS DDR_D[8] T LDQS DQ8 DDR_D[15] T DQ15 DDR_DQM[1] DDR_DQS[1] T UDM UDQS NC PRODUCT PREVIEW T UDQS 50 Ω .5% NC DDR_BA[0] T BA0 DDR_BA[2] T BA2 DDR_A[0] T A0 DDR_A[13] DDR_CS DDR_CAS DDR_RAS DDR_WE DDR_CKE DDR_CLKP DDR_CLKN T A13 T CS CAS RAS WE CKE CK CK T T T T T T DDR_ZP DDR_DQGATE0 DDR_DQGATE1 T (1) DDR_DVDD18 T 0.1 μF 1 K Ω 1% DDR_VREF VREF 0.1 μF T (1) 0.1 μF 0.1 μF VREF 0.1 μF 1 K Ω 1% Terminator, if desired. See terminator comments. See Figure 6-25 for DQGATE routing specifications. Figure 6-18. DDR2/mDDR Single-Memory High Level Schematic 86 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 DDR2/mDDR Memory Controller ODT T DQ0 - DQ7 BA0-BA2 A0-A13 DDR_DQM[0] DDR_DQS[0] T DM DQS DQS CK CK CS CAS RAS WE CKE VREF DDR_BA[0:2] DDR_A[0:13] T T DDR_CLKP DDR_CLKN DDR_CS DDR_CAS DDR_RAS DDR_WE DDR_CKE T DDR_DQM1 DDR_DQS1 T T T T T T T T NC 50 Ω .5% DDR_D[8:15] T DDR_ZP BA0-BA2 A0-A13 CK CK CS CAS RAS WE CKE DM DQS DQS DQ0 - DQ7 DDR_DVDD18 ODT (1) DDR_DQGATE0 DDR_DQGATE1 PRODUCT PREVIEW NC Upper Byte DDR2/mDDR T Lower Byte DDR2/mDDR DDR_D[0:7] T VREF T 0.1 μF 1 K Ω 1% DDR_VREF VREF 0.1 μF T (1) 0.1 μF 0.1 μF 0.1 μF 1 K Ω 1% Terminator, if desired. See terminator comments. See Figure 6-25 for DQGATE routing specifications. Figure 6-19. DDR2/mDDR Dual-Memory High Level Schematic Submit Documentation Feedback Peripheral Information and Electrical Specifications 87 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.11.3.2 Compatible JEDEC DDR2/mDDR Devices Table 6-24 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2/mDDR-400 speed grade DDR2/mDDR devices. The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control signals are shared just like regular dual chip memory configurations. Table 6-24. Compatible JEDEC DDR2/mDDR Devices No. Parameter Min Max Unit Notes PRODUCT PREVIEW 1 JEDEC DDR2/mDDR Device Speed Grade 2 JEDEC DDR2/mDDR Device Bit Width x8 x16 Bits 3 JEDEC DDR2/mDDR Device Count 1 2 Devices (1) DDR2/mDDR-400 See Note (1) Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility. 6.11.3.3 PCB Stackup The minimum stackup required for routing the device is a six layer stack as shown in Table 6-25. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint.Complete stack up specifications are provided in Table 6-26. Table 6-25. C6742 Minimum PCB Stack Up Layer Type Description 1 Signal Top Routing Mostly Horizontal 2 Plane Ground 3 Plane Power 4 Signal Internal Routing 5 Plane Ground 6 Signal Bottom Routing Mostly Vertical Table 6-26. PCB Stack Up Specifications No. Parameter Min Typ Max Unit Notes 1 PCB Routing/Plane Layers 6 2 Signal Routing Layers 3 3 Full ground layers under DDR2/mDDR routing region 2 4 Number of ground plane cuts allowed within DDR routing region 5 Number of ground reference planes required for each DDR2/mDDR routing layer 6 Number of layers between DDR2/mDDR routing layer and reference ground plane 7 PCB Routing Feature Size 4 Mils 8 PCB Trace Width w 4 Mils 8 PCB BGA escape via pad size 18 Mils 9 PCB BGA escape via hole size 8 Mils 10 DSP Device BGA pad size See Note (1) 11 DDR2/mDDR Device BGA pad size See Note (2) 12 Single Ended Impedance, Zo 50 13 Impedance Control Z-5 See Note (3) (1) (2) (3) 88 0 1 0 Z 75 Ω Z+5 Ω Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size. Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size. Z is the nominal singled ended impedance selected for the PCB specified by item 12. Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.11.3.4 Placement Figure 6-19 shows the required placement for the C6742 device as well as the DDR2/mDDR devices. The dimensions for Figure 6-20 are defined in Table 6-27. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2/mDDR systems, the second DDR2/mDDR device is omitted from the placement. X Y DDR2/mDDR Device Y OFFSET PRODUCT PREVIEW Y OFFSET DDR2/mDDR Controller A1 A1 Recommended DDR2/mDDR Device Orientation Figure 6-20. C6742 and DDR2/mDDR Device Placement Table 6-27. Placement Specifications No. 1 Parameter Min X Max Unit 1750 Mils See Notes Notes (1) (2) , 2 Y 1280 Mils See Notes (1) (2) 3 Y Offset 650 Mils See Notes (1) (2) (3) 4 (1) (2) (3) (4) Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout Region 4 w See Note , . , (4) See Figure 6-20 for dimension definitions. Measurements from center of device to center of DDR2/mDDR device. For single memory systems it is recommended that Y Offset be as small as possible. Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing layers by a ground plane. Submit Documentation Feedback Peripheral Information and Electrical Specifications 89 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.11.3.5 DDR2/mDDR Keep Out Region The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 6-21. The size of this region varies with the placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6-27. DDR2/mDDR Device PRODUCT PREVIEW DDR2/mDDR Controller A1 A1 Region should encompass all DDR2/mDDR circuitry and varies depending on placement. Non-DDR2/mDDR signals should not be routed on the DDR signal layers within the DDR2/mDDR keep out region. Non-DDR2/mDDR signals may be routed in the region provided they are routed on layers separated from DDR2/mDDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region. In addition, the 1.8 V power plane should cover the entire keep out region. Figure 6-21. DDR2/mDDR Keepout Region 90 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.11.3.6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other circuitry. Table 6-28 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the DSP and DDR2/mDDR interfaces. Additional bulk bypass capacitance may be needed for other circuitry. Table 6-28. Bulk Bypass Capacitors Parameter Min Max Unit 1 DDR_DVDD18 Supply Bulk Bypass Capacitor Count 3 2 DDR_DVDD18 Supply Bulk Bypass Total Capacitance 30 µF 3 DDR#1 Bulk Bypass Capacitor Count 1 Devices 4 DDR#1 Bulk Bypass Total Capacitance 22 µF 5 DDR#2 Bulk Bypass Capacitor Count 1 Devices 22 µF 6 (1) (2) DDR#2 Bulk Bypass Total Capacitance Devices Notes See Note (1) See Note (1) See Notes See Note (1) (2) , (2) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass caps. Only used on dual-memory systems 6.11.3.7 High-Speed Bypass Capacitors High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR2/mDDR power, and DSP/DDR2/mDDR ground connections. Table 6-29 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Table 6-29. High-Speed Bypass Capacitors No. Parameter Min Max Unit 0402 10 Mils 1 HS Bypass Capacitor Package Size 2 Distance from HS bypass capacitor to device being bypassed 3 Number of connection vias for each HS bypass capacitor 2 4 Trace length from bypass capacitor contact to connection via 1 5 Number of connection vias for each DDR2/mDDR device power or ground balls 6 Trace length from DDR2/mDDR device power ball to connection via 7 DDR_DVDD18 Supply HS Bypass Capacitor Count 10 8 DDR_DVDD18 Supply HS Bypass Capacitor Total Capacitance 0.6 µF 9 DDR#1 HS Bypass Capacitor Count 8 Devices 10 DDR#1 HS Bypass Capacitor Total Capacitance 11 DDR#2 HS Bypass Capacitor Count 12 (1) (2) (3) (4) DDR#2 HS Bypass Capacitor Total Capacitance 250 See Note (1) See Note (2) See Note (3) See Note (3) Mils Vias 30 Notes Mils Vias 1 35 Mils Devices 0.4 µF 8 Devices 0.4 µF See Notes See Note (3) (4) , (4) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. These devices should be placed as close as possible to the device being bypassed. Only used on dual-memory systems Submit Documentation Feedback Peripheral Information and Electrical Specifications 91 PRODUCT PREVIEW No. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.11.3.8 Net Classes Table 6-30 lists the clock net classes for the DDR2/mDDR interface. Table 6-31 lists the signal net classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for the termination and routing rules that follow. Table 6-30. Clock Net Class Definitions Clock Net Class DSP Pin Names CK DDR_CLKP / DDR_CLKN DQS0 DDR_DQS[0] DQS1 DDR_DQS[1] Table 6-31. Signal Net Class Definitions PRODUCT PREVIEW Clock Net Class ADDR_CTRL Associated Clock Net Class DSP Pin Names CK DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE D0 DQS0 DDR_D[7:0], DDR_DQM0 D1 DQS1 DDR_D[15:8], DDR_DQM1 CK, DQS0, DQS1 DDR_DQGATE0, DDR_DQGATE1 DQGATE 6.11.3.9 DDR2/mDDR Signal Termination No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. Table 6-32 shows the specifications for the series terminators. Table 6-32. DDR2/mDDR Signal Terminations No. Min CK Net Class 0 2 ADDR_CTRL Net Class 0 Typ 22 Max Unit 10 Ω See Note Notes Zo Ω See Notes (1) (2) (3) (1) , , 3 Data Byte Net Classes (DQS[0], DQS[1], D0, D1) 0 22 Zo Ω See Notes (1) (2) (3) (4) 4 DQGATE Net Class (DQGATE) 0 10 Zo Ω See Notes (1) (2) (3) (1) (2) (3) (4) 92 Parameter 1 , , , , , Only series termination is permitted, parallel or SST specifically disallowed. Terminator values larger than typical only recommended to address EMI issues. Termination value should be uniform across net class. When no termination is used on data lines (0 Ω), the DDR2/mDDR devices must be programmed to operate in 60% strength mode. Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.11.3.10 VREF Routing VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the C6742 . VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a resistive divider as shown in Figure 6-18. Other methods of creating VREF are not recommended. Figure 6-22 shows the layout guidelines for VREF. VREF Bypass Capacitor DDR2/mDDR Device A1 VREF Nominal Minimum Trace Width is 20 Mils PRODUCT PREVIEW DDR2/mDDR A1 Neck down to minimum in BGA escape regions is acceptable. Narrowing to accomodate via congestion for short distances is also acceptable. Best performance is obtained if the width of VREF is maximized. Figure 6-22. VREF Routing and Topology Submit Documentation Feedback Peripheral Information and Electrical Specifications 93 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing Figure 6-23 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized. B DDR2/mDDR Controller A1 T C A PRODUCT PREVIEW A1 Figure 6-23. CK and ADDR_CTRL Routing and Topology Table 6-33. CK and ADDR_CTRL Routing Specification No. Parameter Min Typ Max Unit 25 Mils 25 Mils (1) See Note (2) See Note (3) 4w See Note (2) 3w See Note (2) See Note (1) CK A to B/A to C Skew Length Mismatch 2 CK B to C Skew Length Mismatch 3 Center to center CK to other DDR2/mDDR trace spacing 4 CK/ADDR_CTRL nominal trace length 5 6 7 Center to center ADDR_CTRL to other DDR2/mDDR trace spacing 8 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing 9 ADDR_CTRL A to B/A to C Skew Length Mismatch 100 Mils 10 ADDR_CTRL B to C Skew Length Mismatch 100 Mils (1) (2) (3) 94 Notes See Note 1 4w CACLM-50 CACLM CACLM+50 Mils ADDR_CTRL to CK Skew Length Mismatch 100 Mils ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils Series terminator, if used, should be located closest to DSP. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes. Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Figure 6-24 shows the topology and routing for the DQS and DQ net class; the routes are point to point. Skew matching across bytes is not needed nor recommended. E0 A1 T A1 DDR2/mDDR Controller T E1 Table 6-34. DQS and DQ Routing Specification No. (1) (2) (3) (4) (5) Parameter 1 DQS E Skew Length Mismatch 2 Center to center DQS to other DDR2/mDDR trace spacing 3 DQS/D nominal trace length Min Typ Max Unit 25 Mils 4w DQLM-50 Notes See Note DQLM DQLM+50 Mils (1) See Notes (2) (3) , 4 D to DQS Skew Length Mismatch 100 Mils See Note (3) 5 D to D Skew Length Mismatch 100 Mils See Note (3) 6 Center to center D to other DDR2/mDDR trace spacing 4w See Notes (1) (4) 7 Center to Center D to other D trace spacing 3w See Notes (5) (1) 8 DQ/DQS E Skew Length Mismatch 100 Mils See Note , , (3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. Series terminator, if used, should be located closest to DDR. There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1. D's from other DQS domains are considered other DDR2/mDDR trace. DQLM is the longest Manhattan distance of each of the DQS and D net class. Submit Documentation Feedback Peripheral Information and Electrical Specifications 95 PRODUCT PREVIEW Figure 6-24. DQS and DQ Routing and Topology TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Figure 6-25 shows the routing for the DQGATE net class. Table 6-35 contains the routing specification. A1 T DDR2/mDDR Controller F T A1 PRODUCT PREVIEW Figure 6-25. DQGATE Routing Table 6-35. DQGATE Routing Specification No. DQGATE Length F 2 Center to center DQGATE to any other trace spacing 3 DQS/D nominal trace length 4 DQGATE Skew (1) (2) 96 Parameter 1 Min Typ Max Unit CKB0B1 Notes See Note (1) See Note (2) 4w DQLM-50 DQLM DQLM+50 Mils 100 Mils CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets. Skew from CKB0B1 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 The McASP serial port is specifically designed for multichannel audio applications. Its key features are: • Flexible clock and frame sync generation logic and on-chip dividers • Up to sixteen transmit or receive data pins and serializers • Large number of serial data format options, including: – TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst) – Time slots of 8,12,16, 20, 24, 28, and 32 bits – First bit delay 0, 1, or 2 clocks – MSB or LSB first bit order – Left- or right-aligned data words within time slots • DIT Mode with 384-bit Channel Status and 384-bit User Data registers • Extensive error checking and mute generation logic • All unused pins GPIO-capable • • Transmit & Receive FIFO Buffers allow the McASP to operate at a higher sample rate by making it more tolerant to DMA latency. Dynamic Adjustment of Clock Dividers – Clock Divider Value may be changed without resetting the McASP Pins Peripheral Configuration Bus GIO Control DIT RAM 384 C 384 U Optional Tra n s m it F o rm a tte r McASP DMA Bus (Dedicated) Receive F o rm a tte r Receive Logic C lo ck /F ra m e G e n e ra to r State Machine Clock Check and Error Detection Function AHCLKRx Receive Master Clock ACLKRx Receive Bit Clock AFSRx R e c e iv e L e ft/R ig h t C lo ck o r F ra m e S y n c AMUTEINx The McASP DOES NOT have a AMUTEx dedicated AMUTEIN pin. AFSXx AHCLKXx Tra n s m it L e ft/R ig h t C lo ck o r F ra m e S y n c Tra n s m it B it C lo ck Tra n s m it M a s te r C lo ck Serializer 0 AXRx[0] Tra n s m it/R e c e iv e S e ria l D a ta P in Serializer 1 AXRx[1] Tra n s m it/R e c e iv e S e ria l D a ta P in Serializer y AXRx[y] Tra n s m it/R e c e iv e S e ria l D a ta P in Tra n s m it L o g ic C lo ck /F ra m e G e n e ra to r State Machine ACLKXx McASP Figure 6-26. McASP Block Diagram Submit Documentation Feedback Peripheral Information and Electrical Specifications 97 PRODUCT PREVIEW 6.12 Multichannel Audio Serial Port (McASP) TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.12.1 McASP Peripheral Registers Description(s) Registers for the McASP are summarized in Table 6-36. The registers are accessed through the peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be accessed through the DMA port, as listed in Table 6-37 Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-38. Note that the AFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control registers are accessed through the peripheral configuration port. Table 6-36. McASP Registers Accessed Through Peripheral Configuration Port PRODUCT PREVIEW BYTE ADDRESS ACRONYM 0x01D0 0000 REV 0x01D0 0010 PFUNC Pin function register 0x01D0 0014 PDIR Pin direction register 0x01D0 0018 PDOUT 0x01D0 001C PDIN Pin data output register Read returns: Pin data input register 0x01D0 001C PDSET Writes affect: Pin data set register (alternate write address: PDOUT) 0x01D0 0020 PDCLR Pin data clear register (alternate write address: PDOUT) 0x01D0 0044 GBLCTL Global control register 0x01D0 0048 AMUTE Audio mute control register 0x01D0 004C DLBCTL Digital loopback control register 0x01D0 0050 DITCTL DIT mode control register 0x01D0 0060 RGBLCTL 0x01D0 0064 RMASK 0x01D0 0068 RFMT Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows receiver to be reset independently from transmitter Receive format unit bit mask register Receive bit stream format register 0x01D0 006C AFSRCTL 0x01D0 0070 ACLKRCTL 0x01D0 0074 AHCLKRCTL 0x01D0 0078 RTDM 0x01D0 007C RINTCTL 0x01D0 0080 RSTAT Receiver status register 0x01D0 0084 RSLOT Current receive TDM time slot register 0x01D0 0088 RCLKCHK Receive clock check control register 0x01D0 008C REVTCTL Receiver DMA event control register XGBLCTL Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows transmitter to be reset independently from receiver 0x01D0 00A0 98 REGISTER DESCRIPTION Revision identification register 0x01D0 00A4 XMASK 0x01D0 00A8 XFMT 0x01D0 00AC AFSXCTL Receive frame sync control register Receive clock control register Receive high-frequency clock control register Receive TDM time slot 0-31 register Receiver interrupt control register Transmit format unit bit mask register Transmit bit stream format register Transmit frame sync control register 0x01D0 00B0 ACLKXCTL 0x01D0 00B4 AHCLKXCTL 0x01D0 00B8 XTDM Transmit TDM time slot 0-31 register 0x01D0 00BC XINTCTL Transmitter interrupt control register 0x01D0 00C0 XSTAT Transmitter status register 0x01D0 00C4 XSLOT Current transmit TDM time slot register 0x01D0 00C8 XCLKCHK Transmit clock check control register 0x01D0 00CC XEVTCTL Transmitter DMA event control register 0x01D0 0100 DITCSRA0 Left (even TDM time slot) channel status register (DIT mode) 0 0x01D0 0104 DITCSRA1 Left (even TDM time slot) channel status register (DIT mode) 1 Peripheral Information and Electrical Specifications Transmit clock control register Transmit high-frequency clock control register Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-36. McASP Registers Accessed Through Peripheral Configuration Port (continued) (1) ACRONYM 0x01D0 0108 DITCSRA2 Left (even TDM time slot) channel status register (DIT mode) 2 REGISTER DESCRIPTION 0x01D0 010C DITCSRA3 Left (even TDM time slot) channel status register (DIT mode) 3 0x01D0 0110 DITCSRA4 Left (even TDM time slot) channel status register (DIT mode) 4 0x01D0 0114 DITCSRA5 Left (even TDM time slot) channel status register (DIT mode) 5 0x01D0 0118 DITCSRB0 Right (odd TDM time slot) channel status register (DIT mode) 0 0x01D0 011C DITCSRB1 Right (odd TDM time slot) channel status register (DIT mode) 1 0x01D0 0120 DITCSRB2 Right (odd TDM time slot) channel status register (DIT mode) 2 0x01D0 0124 DITCSRB3 Right (odd TDM time slot) channel status register (DIT mode) 3 0x01D0 0128 DITCSRB4 Right (odd TDM time slot) channel status register (DIT mode) 4 0x01D0 012C DITCSRB5 Right (odd TDM time slot) channel status register (DIT mode) 5 0x01D0 0130 DITUDRA0 Left (even TDM time slot) channel user data register (DIT mode) 0 0x01D0 0134 DITUDRA1 Left (even TDM time slot) channel user data register (DIT mode) 1 0x01D0 0138 DITUDRA2 Left (even TDM time slot) channel user data register (DIT mode) 2 0x01D0 013C DITUDRA3 Left (even TDM time slot) channel user data register (DIT mode) 3 0x01D0 0140 DITUDRA4 Left (even TDM time slot) channel user data register (DIT mode) 4 0x01D0 0144 DITUDRA5 Left (even TDM time slot) channel user data register (DIT mode) 5 0x01D0 0148 DITUDRB0 Right (odd TDM time slot) channel user data register (DIT mode) 0 0x01D0 014C DITUDRB1 Right (odd TDM time slot) channel user data register (DIT mode) 1 0x01D0 0150 DITUDRB2 Right (odd TDM time slot) channel user data register (DIT mode) 2 0x01D0 0154 DITUDRB3 Right (odd TDM time slot) channel user data register (DIT mode) 3 0x01D0 0158 DITUDRB4 Right (odd TDM time slot) channel user data register (DIT mode) 4 0x01D0 015C DITUDRB5 Right (odd TDM time slot) channel user data register (DIT mode) 5 0x01D0 0180 SRCTL0 Serializer control register 0 0x01D0 0184 SRCTL1 Serializer control register 1 0x01D0 0188 SRCTL2 Serializer control register 2 0x01D0 018C SRCTL3 Serializer control register 3 0x01D0 0190 SRCTL4 Serializer control register 4 0x01D0 0194 SRCTL5 Serializer control register 5 0x01D0 0198 SRCTL6 Serializer control register 6 0x01D0 019C SRCTL7 Serializer control register 7 0x01D0 01A0 SRCTL8 Serializer control register 8 0x01D0 01A4 SRCTL9 Serializer control register 9 0x01D0 01A8 SRCTL10 Serializer control register 10 0x01D0 01AC SRCTL11 Serializer control register 11 0x01D0 01B0 SRCTL12 Serializer control register 12 0x01D0 01B4 SRCTL13 Serializer control register 13 0x01D0 01B8 SRCTL14 Serializer control register 14 0x01D0 01BC SRCTL15 Serializer control register 15 0x01D0 0200 XBUF0 (1) Transmit buffer register for serializer 0 0x01D0 0204 XBUF1 (1) Transmit buffer register for serializer 1 0x01D0 0208 XBUF2 (1) Transmit buffer register for serializer 2 0x01D0 020C XBUF3 (1) Transmit buffer register for serializer 3 0x01D0 0210 XBUF4 (1) Transmit buffer register for serializer 4 0x01D0 0214 XBUF5 (1) Transmit buffer register for serializer 5 0x01D0 0218 XBUF6 (1) Transmit buffer register for serializer 6 0x01D0 021C (1) Transmit buffer register for serializer 7 XBUF7 PRODUCT PREVIEW BYTE ADDRESS Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT. Submit Documentation Feedback Peripheral Information and Electrical Specifications 99 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-36. McASP Registers Accessed Through Peripheral Configuration Port (continued) PRODUCT PREVIEW (2) BYTE ADDRESS ACRONYM 0x01D0 0220 XBUF8 (1) Transmit buffer register for serializer 8 REGISTER DESCRIPTION 0x01D0 0224 XBUF9 (1) Transmit buffer register for serializer 9 0x01D0 0228 XBUF10 (1) Transmit buffer register for serializer 10 0x01D0 022C XBUF11 (1) Transmit buffer register for serializer 11 0x01D0 0230 XBUF12 (1) Transmit buffer register for serializer 12 0x01D0 0234 XBUF13 (1) Transmit buffer register for serializer 13 0x01D0 0238 XBUF14 (1) Transmit buffer register for serializer 14 0x01D0 023C XBUF15 (1) Transmit buffer register for serializer 15 0x01D0 0280 RBUF0 (2) Receive buffer register for serializer 0 0x01D0 0284 RBUF1 (2) Receive buffer register for serializer 1 0x01D0 0288 RBUF2 (2) Receive buffer register for serializer 2 0x01D0 028C RBUF3 (2) Receive buffer register for serializer 3 0x01D0 0290 RBUF4 (2) Receive buffer register for serializer 4 0x01D0 0294 RBUF5 (2) Receive buffer register for serializer 5 0x01D0 0298 RBUF6 (2) Receive buffer register for serializer 6 0x01D0 029C RBUF7 (2) Receive buffer register for serializer 7 0x01D0 02A0 RBUF8 (2) Receive buffer register for serializer 8 0x01D0 02A4 RBUF9 (2) Receive buffer register for serializer 9 0x01D0 02A8 RBUF10 (2) Receive buffer register for serializer 10 0x01D0 02AC RBUF11 (2) Receive buffer register for serializer 11 0x01D0 02B0 RBUF12 (2) Receive buffer register for serializer 12 0x01D0 02B4 RBUF13 (2) Receive buffer register for serializer 13 0x01D0 02B8 RBUF14 (2) Receive buffer register for serializer 14 0x01D0 02BC RBUF15 (2) Receive buffer register for serializer 15 Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT. Table 6-37. McASP Registers Accessed Through DMA Port ACCESS TYPE BYTE ADDRESS ACRONYM Read Accesses 0x01D0 2000 RBUF REGISTER DESCRIPTION Receive buffer DMA port address. Cycles through receive serializers, skipping over transmit serializers and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Reads from DMA port only if XBUSEL = 0 in XFMT. Write Accesses 0x01D0 2000 XBUF Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA port only if RBUSEL = 0 in RFMT. Table 6-38. McASP AFIFO Registers Accessed Through Peripheral Configuration Port 100 BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01D0 1000 AFIFOREV AFIFO revision identification register 0x01D0 1010 WFIFOCTL Write FIFO control register 0x01D0 1014 WFIFOSTS Write FIFO status register 0x01D0 1018 RFIFOCTL Read FIFO control register 0x01D0 101C RFIFOSTS Read FIFO status register Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.12.2 McASP Electrical Data/Timing 6.12.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing Table 6-39 and Table 6-41 assume testing over recommended operating conditions (see Figure 6-27 and Figure 6-28). Table 6-39. Timing Requirements for McASP0 (1.2V, 1.1V) (1) (2) 1.2V PARAMETER MIN 1.1V MAX MIN MAX UNIT 1 tc(AHCLKRX) Cycle time, AHCLKR/X 20 22 ns 2 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 10 11 ns 3 tc(ACLKRX) Cycle time, ACLKR/X AHCLKR/X ext 20 (3) 22 (3) ns 4 tw(ACLKRX) Pulse duration, ACLKR/W high or low AHCLKR/X ext 10 11 ns AHCLKR/X int 11.5 12 ns 4 5 ns 5 6 7 8 (1) (2) (3) (4) (5) tsu(AFSRX-ACLKRX) Setup time, AFSR/X input to ACLKR/X (4) th(ACLKRX-AFSRX) Hold time, AFSR/X input after ACLKR/X (4) tsu(AXR-ACLKRX) Setup time, AXR0[n] input to ACLKR/X (4) (5) th(ACLKRX-AXR) Hold time, AXR0[n] input after ACLKR/X (4) (5) AHCLKR/X ext input AHCLKR/X ext output 4 5 ns AHCLKR/X int -1 -2 ns AHCLKR/X ext input 0.4 1 ns AHCLKR/X ext output 0.4 1 ns AHCLKR/X int 11.5 12 ns AHCLKR/X ext 4 5 ns AHCLKR/X int -1 -2 ns AHCLKR/X ext input 0.4 1 ns AHCLKR/X ext output 0.4 1 ns ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1 ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0 ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1 ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1 ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0 ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1 P = SYSCLK2 period This timing is limited by the timing shown or 2P, whichever is greater. McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0 McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0 Submit Documentation Feedback Peripheral Information and Electrical Specifications 101 PRODUCT PREVIEW NO. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-40. Timing Requirements for McASP0 (1.0V) (1) (2) NO. 1.0V PARAMETER MIN MAX UNIT 1 tc(AHCLKRX) Cycle time, AHCLKR/X 26.6 ns 2 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 13.3 ns 3 tc(ACLKRX) Cycle time, ACLKR/X AHCLKR/X ext 26.6 (3) ns 4 tw(ACLKRX) Pulse duration, ACLKR/W high or low AHCLKR/X ext 13.3 ns AHCLKR/X int 16 ns AHCLKR/X ext input 5.5 ns AHCLKR/X ext output 5.5 ns 5 6 PRODUCT PREVIEW 7 8 (1) (2) (3) (4) (5) 102 tsu(AFSRX-ACLKRX) th(ACLKRX-AFSRX) tsu(AXR-ACLKRX) th(ACLKRX-AXR) Setup time, AFSR/X input to ACLKR/X (4) Hold time, AFSR/X input after ACLKR/X (4) Setup time, AXR0[n] input to ACLKR/X (4) (5) Hold time, AXR0[n] input after ACLKR/X (4) (5) AHCLKR/X int -2 ns AHCLKR/X ext input 1 ns AHCLKR/X ext output 1 ns AHCLKR/X int 16 ns AHCLKR/X ext 5.5 ns AHCLKR/X int -2 ns AHCLKR/X ext input 1 ns AHCLKR/X ext output 1 ns ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1 ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0 ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1 ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1 ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0 ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1 P = SYSCLK2 period This timing is limited by the timing shown or 2P, whichever is greater. McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0 McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-41. Switching Characteristics for McASP0 (1.2V, 1.1V) (1) 9 tc(AHCLKRX) Cycle time, AHCLKR/X 10 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 11 tc(ACLKRX) Cycle time, ACLKR/X 12 tw(ACLKRX) 13 td(ACLKRX-AFSRX) 14 td(ACLKX-AXRV) 15 (1) (2) (3) (4) (5) (6) 1.2V PARAMETER tdis(ACLKX-AXRHZ) MIN ACLKR/X int Pulse duration, ACLKR/X high or low Delay time, ACLKR/X transmit edge to AFSX/R output valid (6) Delay time, ACLKX transmit edge to AXR output valid ACLKR/X int 1.1V MAX MIN MAX UNIT 20 22 ns AH – 2.5 (2) AH – 2.5 (2) ns 20 (3) (4) 22 (3) (4) ns A – 2.5 (5) A – 2.5 (5) ns ACLKR/X int 0 6 0 8 ns ACLKR/X ext input 2 13.5 2 14.5 ns ACLKR/X ext output 2 13.5 2 14.5 ns ACLKR/X int 0 6 0 8 ns ACLKR/X ext input 2 13.5 2 14.5 ns ACLKR/X ext output 2 13.5 2 14.5 ns 0 6 0 8 ns 2 13.5 2 14.5 ns Disable time, ACLKR/X transmit edge to ACLKR/X int AXR high impedance following last data ACLKR/X ext bit McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1 ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0 ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1 ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1 ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0 ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1 AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns. P = SYSCLK2 period This timing is limited by the timing shown or 2P, whichever is greater. A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns. McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0 Table 6-42. Switching Characteristics for McASP0 (1.0V) (1) NO. 9 tc(AHCLKRX) Cycle time, AHCLKR/X 10 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low 11 tc(ACLKRX) Cycle time, ACLKR/X 12 1.0V PARAMETER tw(ACLKRX) Pulse duration, ACLKR/X high or low MIN 14 15 (1) (2) (3) (4) (5) (6) td(ACLKRX-AFSRX) td(ACLKX-AXRV) 26.6 ns ns ACLKR/X int 26.6 (3) (4) ns ACLKR/X int (5) tdis(ACLKX-AXRHZ) Disable time, ACLKR/X transmit edge to AXR high impedance following last data bit A – 2.5 ns 0 10 ns 2 19 ns ACLKR/X ext output 2 19 ns ACLKR/X int 0 10 ns ACLKR/X ext input 2 19 ns ACLKR/X ext output 2 19 ns ACLKR/X int 0 10 ns ACLKR/X ext 2 19 ns Delay time, ACLKR/X transmit edge to AFSX/R output valid (6) ACLKR/X ext input Delay time, ACLKX transmit edge to AXR output valid UNIT AH – 2.5 (2) ACLKR/X int 13 MAX McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1 ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0 ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1 ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1 ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0 ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1 AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns. P = SYSCLK2 period This timing is limited by the timing shown or 2P, whichever is greater. A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns. McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0 Submit Documentation Feedback Peripheral Information and Electrical Specifications 103 PRODUCT PREVIEW NO. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 2 1 2 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 4 3 4 ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) PRODUCT PREVIEW 6 5 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). Figure 6-27. McASP Input Timings 104 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 10 10 9 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 12 11 12 ACLKR/X (CLKRP = CLKXP = 1)(A) ACLKR/X (CLKRP = CLKXP = 0)(B) PRODUCT PREVIEW 13 13 13 13 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) 13 13 13 AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 14 15 AXR[n] (Data Out/Transmit) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). C31 Figure 6-28. McASP Output Timings Submit Documentation Feedback Peripheral Information and Electrical Specifications 105 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.13 Multichannel Buffered Serial Port (McBSP) The McBSP provides these functions: • Full-duplex communication • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit • Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices • External shift clock or an internal, programmable frequency shift clock for data transfer • Transmit & Receive FIFO Buffers allow the McBSP to operate at a higher sample rate by making it more tolerant to DMA latency PRODUCT PREVIEW If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater. 6.13.1 McBSP Peripheral Register Description(s) Table 6-43. McBSP/FIFO Registers McBSP1 BYTE ADDRESS ACRONYM 0x01D1 1000 DRR McBSP Data Receive Register (read-only) 0x01D1 1004 DXR McBSP Data Transmit Register 0x01D1 1008 SPCR 0x01D1 100C RCR McBSP Receive Control Register 0x01D1 1010 XCR McBSP Transmit Control Register 0x01D1 1014 SRGR REGISTER DESCRIPTION McBSP Registers McBSP Serial Port Control Register McBSP Sample Rate Generator register 0x01D1 1018 MCR 0x01D1 101C RCERE0 McBSP Multichannel Control Register McBSP Enhanced Receive Channel Enable Register 0 Partition A/B 0x01D1 1020 XCERE0 McBSP Enhanced Transmit Channel Enable Register 0 Partition A/B 0x01D1 1024 PCR 0x01D1 1028 RCERE1 McBSP Pin Control Register McBSP Enhanced Receive Channel Enable Register 1 Partition C/D 0x01D1 102C XCERE1 McBSP Enhanced Transmit Channel Enable Register 1 Partition C/D 0x01D1 1030 RCERE2 McBSP Enhanced Receive Channel Enable Register 2 Partition E/F 0x01D1 1034 XCERE2 McBSP Enhanced Transmit Channel Enable Register 2 Partition E/F 0x01D1 1038 RCERE3 McBSP Enhanced Receive Channel Enable Register 3 Partition G/H 0x01D1 103C XCERE3 McBSP Enhanced Transmit Channel Enable Register 3 Partition G/H 0x01D1 1800 BFIFOREV BFIFO Revision Identification Register 0x01D1 1810 WFIFOCTL Write FIFO Control Register 0x01D1 1814 WFIFOSTS Write FIFO Status Register 0x01D1 1818 RFIFOCTL Read FIFO Control Register 0x01D1 181C RFIFOSTS Read FIFO Status Register McBSP FIFO Control and Status Registers McBSP FIFO Data Registers 0x01F1 1000 RBUF McBSP FIFO Receive Buffer 0x01F1 1000 XBUF McBSP FIFO Transmit Buffer 106 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.13.2 McBSP Electrical Data/Timing The following assume testing over recommended operating conditions. 6.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing Table 6-44. Timing Requirements for McBSP1 [1.2V, 1.1V] (1) (see Figure 6-29) 1.2V PARAMETER MIN 1.1V MAX MIN 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P or 20 (2) (3) 2P or 25 (2) 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P-1 P - 1 (4) 4 tt Transition time, rising edge or falling edge 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low 8 th(CKRL-DRV) 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low 11 th(CKXL-FXH) (1) (2) (3) (4) Hold time, DR valid after CLKR low Hold time, external FSX high after CLKX low 5 MAX UNIT ns ns 5 CLKR int 15 18 CLKR ext 5 5 CLKR int 6 6 CLKR ext 3 3 CLKR int 15 18 CLKR ext 5 5 CLKR int 3 3 CLKR ext 3 3 CLKX int 15 18 CLKX ext 5 5 CLKX int 6 6 CLKX ext 3 3 ns ns ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns. Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle. Submit Documentation Feedback Peripheral Information and Electrical Specifications 107 PRODUCT PREVIEW NO. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-45. Timing Requirements for McBSP1 [1.0V] (1) (see Figure 6-29) NO. 2 tc(CKRX) Cycle time, CLKR/X PRODUCT PREVIEW 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low 4 tt Transition time, rising edge or falling edge 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low 6 th(CKRL-FRH) 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low 8 th(CKRL-DRV) 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low 11 th(CKXL-FXH) (1) (2) (3) (4) 108 1.0V PARAMETER Hold time, external FSR high after CLKR low Hold time, DR valid after CLKR low Hold time, external FSX high after CLKX low MIN CLKR/X ext CLKR/X ext MAX 2P or 26.6 (2) (3) P-1 UNIT ns (4) ns 5 CLKR int 21 CLKR ext 10 CLKR int 6 CLKR ext 3 CLKR int 21 CLKR ext 10 CLKR int 3 CLKR ext 3 CLKX int 21 CLKX ext 10 CLKX int 6 CLKX ext 3 ns ns ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns. Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle. Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-46. Switching Characteristics for McBSP1 [1.2V, 1.1V] (1) (2) (see Figure 6-29) 1.2V PARAMETER 1.1V MIN MAX MIN MAX 2.5 16.5 3 18 UNIT 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P or 20 (3) (4) 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 2 (5) C + 2 (5) C - 2 (5) C + 2 (5) ns 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -4 6.5 -4 13 ns CLKR ext 2.5 16.5 2.5 18 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX int -4 6.5 -4 13 CLKX ext 2.5 16.5 2.5 18 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high CLKX int -4 6.5 -4 13 CLKX ext -2 16.5 -2 18 13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX int -4 + D1 (6) 6.5 + D2 (6) -4 + D1 (6) 13 + D2 (6) CLKX ext 2.5 + D1 (6) 16.5 + D2 (6) 2.5 + D1 (6) 18 + D2 (6) 14 td(FXH-DXV) (1) (2) (3) (4) (5) (6) (7) 2P or 25 (3) (4) ns ns Delay time, FSX high to DX valid FSX int -4 (7) 6.5 (7) -4 (7) 13 (7) ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext -2 (7) 16.5 (7) -2 (7) 18 ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns. Use whichever value is greater. C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period) S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above). Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 6P, D2 = 12P Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 6P, D2 = 12P Submit Documentation Feedback Peripheral Information and Electrical Specifications 109 PRODUCT PREVIEW NO. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-47. Switching Characteristics for McBSP1 [1.0V] (1) (2) (see Figure 6-29) NO. 1.0V PARAMETER MIN MAX 3 23 UNIT PRODUCT PREVIEW 1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input 2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P or 26.6 (3) (4) (5) 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 2 (6) C + 2 (6) ns CLKR int -4 13 ns CLKR ext 2.5 23 CLKX int -4 13 CLKX ext 2.5 23 CLKX int -4 13 CLKX ext -2 23 CLKX int -4 + D1 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 13 td(CKXH-DXV) Delay time, CLKX high to DX valid 14 td(FXH-DXV) (1) (2) (3) (4) (5) (6) (7) (8) 110 CLKX ext 2.5 + D1 (7) ns ns 13 + D2 (7) 23 + D2 (7) Delay time, FSX high to DX valid FSX int -4 (8) 13 (8) ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext -2 (8) 23 (8) ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns. Use whichever value is greater. C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period) S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above). Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 6P, D2 = 12P Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 6P, D2 = 12P Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 8 DR Bit(n1) (n2) (n3) 2 3 PRODUCT PREVIEW 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 14 13 (A) Bit(n1) 12 DX Bit 0 13 (A) (n2) (n3) Figure 6-29. McBSP Timing(B) Table 6-48. Timing Requirements for McBSP1 FSR When GSYNC = 1 (see Figure 6-30) NO. 1.2V PARAMETER MIN MAX 1.1V MIN MAX 1.0V MIN MAX UNIT 1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 5 5 10 ns 2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 4 4 ns CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) Figure 6-30. FSR Timing When GSYNC = 1 Submit Documentation Feedback Peripheral Information and Electrical Specifications 111 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.14 Serial Peripheral Interface Ports (SPI1) Figure 6-31 is a block diagram of the SPI module, which is a simple shift register and buffer plus control logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many data formatting options. SPIx_SIMO SPIx_SOMI Peripheral Configuration Bus PRODUCT PREVIEW Interrupt and DMA Requests 16-Bit Shift Register 16-Bit Buffer SPIx_ENA State GPIO Machine SPIx_SCS Control (all pins) Clock SPIx_CLK Control Figure 6-31. Block Diagram of SPI Module The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA). The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are other slave devices on the same SPI port. The device will only shift data and drive the SPIx_SOMI pin when SPIx_SCS is held low. In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the same SPI bus. In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI communications and, on average, increases SPI bus throughput since the master does not need to delay each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer can begin as soon as both the master and slave have actually serviced the previous SPI transfer. 112 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Optional − Slave Chip Select SPIx_SCS SPIx_SCS SPIx_ENA SPIx_ENA SPIx_CLK SPIx_CLK SPIx_SOMI SPIx_SOMI SPIx_SIMO SPIx_SIMO MASTER SPI SLAVE SPI PRODUCT PREVIEW Optional Enable (Ready) Figure 6-32. Illustration of SPI Master-to-SPI Slave Connection Submit Documentation Feedback Peripheral Information and Electrical Specifications 113 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.14.1 SPI Peripheral Registers Description(s) Table 6-49is a list of the SPI registers. Table 6-49. SPIx Configuration Registers SPI1 BYTE ADDRESS PRODUCT PREVIEW 114 REGISTER NAME DESCRIPTION 0x01F0 E000 SPIGCR0 Global Control Register 0 0x01F0 E004 SPIGCR1 Global Control Register 1 0x01F0 E008 SPIINT0 Interrupt Register 0x01F0 E00C SPILVL Interrupt Level Register 0x01F0 E010 SPIFLG Flag Register 0x01F0 E014 SPIPC0 Pin Control Register 0 (Pin Function) 0x01F0 E018 SPIPC1 Pin Control Register 1 (Pin Direction) 0x01F0 E01C SPIPC2 Pin Control Register 2 (Pin Data In) 0x01F0 E020 SPIPC3 Pin Control Register 3 (Pin Data Out) 0x01F0 E024 SPIPC4 Pin Control Register 4 (Pin Data Set) 0x01F0 E028 SPIPC5 Pin Control Register 5 (Pin Data Clear) 0x01F0 E02C Reserved Reserved - Do not write to this register 0x01F0 E030 Reserved Reserved - Do not write to this register 0x01F0 E034 Reserved Reserved - Do not write to this register 0x01F0 E038 SPIDAT0 Shift Register 0 (without format select) 0x01F0 E03C SPIDAT1 Shift Register 1 (with format select) 0x01F0 E040 SPIBUF Buffer Register 0x01F0 E044 SPIEMU Emulation Register 0x01F0 E048 SPIDELAY Delay Register 0x01F0 E04C SPIDEF Default Chip Select Register 0x01F0 E050 SPIFMT0 Format Register 0 0x01F0 E054 SPIFMT1 Format Register 1 0x01F0 E058 SPIFMT2 Format Register 2 0x01F0 E05C SPIFMT3 Format Register 3 0x01F0 E060 INTVEC0 Interrupt Vector for SPI INT0 0x01F0 E064 INTVEC1 Interrupt Vector for SPI INT1 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.14.2 SPI Electrical Data/Timing 6.14.2.1 Serial Peripheral Interface (SPI) Timing The following tables and timing diagrams assume testing over recommended operating conditions ( Table 6-50. General Timing Requirements for SPI1 Master Modes (1) 1 1.2V PARAMETER 1.1V 1.0V MIN MAX MIN MAX MIN MAX 20 (2) 256P 30 (2) 256P 40 (2) 256P UNIT tc(SPC)M Cycle Time, SPI1_CLK, All Master Modes 2 tw(SPCH)M Pulse Width High, SPI1_CLK, All Master Modes 0.5M-1 0.5M-1 0.5M-1 ns 3 tw(SPCL)M Pulse Width Low, SPI1_CLK, All Master Modes 0.5M-1 0.5M-1 0.5M-1 ns 4,5 5 td(SIMO_SPC)M td(SPC_SIMO)M Delay, initial data bit valid on SPI1_SIMO to initial edge on SPI1_CLK (3) Polarity = 0, Phase = 0, to SPI1_CLK rising 5 5 6 Polarity = 0, Phase = 1, to SPI1_CLK rising -0.5M+5 -0.5M+5 -0.5M+6 Polarity = 1, Phase = 0, to SPI1_CLK falling 5 5 6 Polarity = 1, Phase = 1, to SPI1_CLK falling -0.5M+5 -0.5M+5 -0.5M+6 Polarity = 0, Phase = 0, from SPI1_CLK rising 5 5 6 5 5 6 ns Polarity = 0, Phase = 1, Delay, subsequent from SPI1_CLK bits valid on falling SPI1_SIMO after Polarity = 1, Phase = transmit edge of 0, SPI1_CLK from SPI1_CLK falling ns Polarity = 1, Phase = 1, from SPI1_CLK rising 6 (1) (2) (3) toh(SPC_SIMO)M Output hold time, SPI1_SIMO valid after receive edge of SPI1_CLK ns 5 5 6 5 5 6 Polarity = 0, Phase = 0, from SPI1_CLK falling 0.5M-3 0.5M-3 0.5M-3 Polarity = 0, Phase = 1, from SPI1_CLK rising 0.5M-3 0.5M-3 0.5M-3 Polarity = 1, Phase = 0, from SPI1_CLK rising 0.5M-3 0.5M-3 0.5M-3 Polarity = 1, Phase = 1, from SPI1_CLK falling 0.5M-3 0.5M-3 0.5M-3 ns P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period) This timing is limited by the timing shown or 2P, whichever is greater. First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI. Submit Documentation Feedback Peripheral Information and Electrical Specifications 115 PRODUCT PREVIEW NO. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-50. General Timing Requirements for SPI1 Master Modes (continued) NO. 7 PRODUCT PREVIEW 8 116 1.2V PARAMETER tsu(SOMI_SPC)M tih(SPC_SOMI)M Input Setup Time, SPI1_SOMI valid before receive edge of SPI1_CLK Input Hold Time, SPI1_SOMI valid after receive edge of SPI1_CLK MIN 1.1V MAX MIN 1.0V MAX MIN Polarity = 0, Phase = 0, to SPI1_CLK falling 1.5 1.5 1.5 Polarity = 0, Phase = 1, to SPI1_CLK rising 1.5 1.5 1.5 Polarity = 1, Phase = 0, to SPI1_CLK rising 1.5 1.5 1.5 Polarity = 1, Phase = 1, to SPI1_CLK falling 1.5 1.5 1.5 Polarity = 0, Phase = 0, from SPI1_CLK falling 4 5 6 Polarity = 0, Phase = 1, from SPI1_CLK rising 4 5 6 Polarity = 1, Phase = 0, from SPI1_CLK rising 4 5 6 Polarity = 1, Phase = 1, from SPI1_CLK falling 4 5 6 Peripheral Information and Electrical Specifications MAX UNIT ns ns Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-51. General Timing Requirements for SPI1 Slave Modes (1) 1.2V PARAMETER 1.1V 1.0V MIN MAX MIN MAX MIN MAX 40 (2) 256P 50 (2) 256P 60 (2) 256P UNIT 9 tc(SPC)S Cycle Time, SPI1_CLK, All Slave Modes 10 tw(SPCH)S Pulse Width High, SPI1_CLK, All Slave Modes 18 22 27 ns 11 tw(SPCL)S Pulse Width Low, SPI1_CLK, All Slave Modes 18 22 27 ns Polarity = 0, Phase = 0, to SPI1_CLK rising 2P 2P 2P Polarity = 0, Phase = 1, to SPI1_CLK rising 2P 2P 2P Polarity = 1, Phase = 0, to SPI1_CLK falling 2P 2P 2P Polarity = 1, Phase = 1, to SPI1_CLK falling 2P 2P 2P 12 tsu(SOMI_SPC)S Setup time, transmit data written to SPI before initial clock edge from master. (3) (4) ns Polarity = 0, Phase = 0, from SPI1_CLK rising 13 td(SPC_SOMI)S Polarity = 0, Phase = 1, Delay, subsequent bits valid from SPI1_CLK falling on SPI1_SOMI after transmit edge of SPI1_CLK Polarity = 1, Phase = 0, from SPI1_CLK falling 14 15 16 (1) (2) (3) (4) toh(SPC_SOMI)S tsu(SIMO_SPC)S tih(SPC_SIMO)S Input Setup Time, SPI1_SIMO valid before receive edge of SPI1_CLK Input Hold Time, SPI1_SIMO valid after receive edge of SPI1_CLK 15 17 19 15 17 19 15 17 19 15 17 19 ns Polarity = 1, Phase = 1, from SPI1_CLK rising Output hold time, SPI1_SOMI valid after receive edge of SPI1_CLK ns Polarity = 0, Phase = 0, from SPI1_CLK falling 0.5S-4 0.5S-10 0.5S-12 Polarity = 0, Phase = 1, from SPI1_CLK rising 0.5S-4 0.5S-10 0.5S-12 Polarity = 1, Phase = 0, from SPI1_CLK rising 0.5S-4 0.5S-10 0.5S-12 Polarity = 1, Phase = 1, from SPI1_CLK falling 0.5S-4 0.5S-10 0.5S-12 Polarity = 0, Phase = 0, to SPI1_CLK falling 1.5 1.5 1.5 Polarity = 0, Phase = 1, to SPI1_CLK rising 1.5 1.5 1.5 Polarity = 1, Phase = 0, to SPI1_CLK rising 1.5 1.5 1.5 Polarity = 1, Phase = 1, to SPI1_CLK falling 1.5 1.5 1.5 Polarity = 0, Phase = 0, from SPI1_CLK falling 4 5 6 Polarity = 0, Phase = 1, from SPI1_CLK rising 4 5 6 Polarity = 1, Phase = 0, from SPI1_CLK rising 4 5 6 Polarity = 1, Phase = 1, from SPI1_CLK falling 4 5 6 ns ns ns P = SYSCLK2 period; S = tc(SPC)S (SPI slave bit clock period) This timing is limited by the timing shown or 2P, whichever is greater. First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO. Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU. Submit Documentation Feedback Peripheral Information and Electrical Specifications 117 PRODUCT PREVIEW NO. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-52. Additional (1) SPI1 Master Timings, 4-Pin Enable Option (2) (3) NO. 17 td(EN PRODUCT PREVIEW 18 (1) (2) (3) (4) (5) 1.2V PARAMETER A_SPC)M td(SPC_ENA)M Delay from slave assertion of SPI1_ENA active to first SPI1_CLK from master. (4) Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer. (5) MIN 1.1V MAX MIN 1.0V MAX MIN MAX Polarity = 0, Phase = 0, to SPI1_CLK rising 3P+5 3P+5 3P+6 Polarity = 0, Phase = 1, to SPI1_CLK rising 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 Polarity = 1, Phase = 0, to SPI1_CLK falling 3P+5 3P+5 3P+6 Polarity = 1, Phase = 1, to SPI1_CLK falling 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 Polarity = 0, Phase = 0, from SPI1_CLK falling 0.5M+P+5 0.5M+P+5 0.5M+P+6 Polarity = 0, Phase = 1, from SPI1_CLK falling P+5 P+5 P+6 Polarity = 1, Phase = 0, from SPI1_CLK rising 0.5M+P+5 0.5M+P+5 0.5M+P+6 Polarity = 1, Phase = 1, from SPI1_CLK rising P+5 P+5 P+6 UNIT ns ns These parameters are in addition to the general timings for SPI master modes (Table 6-50). P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes. In the case where the master SPI is ready with new data before SPI1_ENA assertion. In the case where the master SPI is ready with new data before SPI1_ENA deassertion. Table 6-53. Additional (1) SPI1 Master Timings, 4-Pin Chip Select Option (2) (3) NO. 19 20 (1) (2) (3) (4) (5) (6) (7) 118 PARAMETER td(SCS_SPC)M td(SPC_SCS)M Delay from SPI1_SCS active to first SPI1_CLK (4) (5) Delay from final SPI1_CLK edge to master deasserting SPI1_SCS (6) (7) 1.2V MIN 1.1V MAX MIN 1.0V MAX MIN Polarity = 0, Phase = 0, to SPI1_CLK rising 2P-1 2P-5 2P-6 Polarity = 0, Phase = 1, to SPI1_CLK rising 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6 Polarity = 1, Phase = 0, to SPI1_CLK falling 2P-1 2P-5 2P-6 Polarity = 1, Phase = 1, to SPI1_CLK falling 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6 Polarity = 0, Phase = 0, from SPI1_CLK falling 0.5M+P-1 0.5M+P-5 0.5M+P-6 Polarity = 0, Phase = 1, from SPI1_CLK falling P-1 P-5 P-6 Polarity = 1, Phase = 0, from SPI1_CLK rising 0.5M+P-1 0.5M+P-5 0.5M+P-6 Polarity = 1, Phase = 1, from SPI1_CLK rising P-1 P-5 P-6 MAX UNIT ns ns These parameters are in addition to the general timings for SPI master modes (Table 6-50). P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes. In the case where the master SPI is ready with new data before SPI1_SCS assertion. This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0]. Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted. This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0]. Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-54. Additional (1) SPI1 Master Timings, 5-Pin Option (2) (3) NO. 18 20 21 22 (1) (2) (3) (4) (5) (6) (7) (8) (9) 1.2V PARAMETER td(SPC_ENA)M td(SPC_SCS)M MIN Max delay for slave to deassert SPI1_ENA after final SPI1_CLK edge to ensure master does not begin the next transfer. (4) Delay from final SPI1_CLK edge to master deasserting SPI1_SCS (5) (6) td(SCS_SPC)M Delay from SPI1_SCS active to first SPI1_CLK MAX MIN 1.0V MAX MIN MAX Polarity = 0, Phase = 0, from SPI1_CLK falling 0.5M+P+5 0.5M+P+5 0.5M+P+6 Polarity = 0, Phase = 1, from SPI1_CLK falling P+5 P+5 P+6 Polarity = 1, Phase = 0, from SPI1_CLK rising 0.5M+P+5 0.5M+P+5 0.5M+P+6 Polarity = 1, Phase = 1, from SPI1_CLK rising P+5 P+5 P+6 UNIT ns Polarity = 0, Phase = 0, from SPI1_CLK falling 0.5M+P-1 0.5M+P-5 0.5M+P-6 Polarity = 0, Phase = 1, from SPI1_CLK falling P-1 P-5 P-6 Polarity = 1, Phase = 0, from SPI1_CLK rising 0.5M+P-1 0.5M+P-5 0.5M+P-6 Polarity = 1, Phase = 1, from SPI1_CLK rising P-1 P-5 P-6 ns Max delay for slave SPI to drive SPI1_ENA valid after master asserts SPI1_SCS to td(SCSL_ENAL)M delay the master from beginning the next transfer, (7) (8) (9) 1.1V C2TDELAY+P C2TDELAY+P C2TDELAY+P Polarity = 0, Phase = 0, to SPI1_CLK rising 2P-1 2P-5 2P-6 Polarity = 0, Phase = 1, to SPI1_CLK rising 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6 Polarity = 1, Phase = 0, to SPI1_CLK falling 2P-1 2P-5 2P-6 Polarity = 1, Phase = 1, to SPI1_CLK falling 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6 ns ns These parameters are in addition to the general timings for SPI master modes (Table 6-51). P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes. In the case where the master SPI is ready with new data before SPI1_ENA deassertion. Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted. This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0]. If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA. In the case where the master SPI is ready with new data before SPI1_SCS assertion. This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0]. Submit Documentation Feedback Peripheral Information and Electrical Specifications 119 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-54. Additional SPI1 Master Timings, 5-Pin Option (continued) NO. 23 1.2V PARAMETER td(ENA_SPC)M Delay from assertion of SPI1_ENA low to first SPI1_CLK edge. (10) MIN 1.1V MAX MIN 1.0V MAX MIN MAX Polarity = 0, Phase = 0, to SPI1_CLK rising 3P+5 3P+5 3P+6 Polarity = 0, Phase = 1, to SPI1_CLK rising 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 Polarity = 1, Phase = 0, to SPI1_CLK falling 3P+5 3P+5 3P+6 Polarity = 1, Phase = 1, to SPI1_CLK falling 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6 UNIT ns (10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed. 120 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-55. Additional (1) SPI1 Slave Timings, 4-Pin Enable Option (2) (3) NO. 24 (1) (2) (3) 1.2V PARAMETER Delay from final td(SPC_ENAH)S SPI1_CLK edge to slave deasserting SPI1_ENA. 1.1V 1.0V MIN MAX MIN MAX MIN MAX Polarity = 0, Phase = 0, from SPI1_CLK falling 1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19 Polarity = 0, Phase = 1, from SPI1_CLK falling –0.5M+1.5P-3 –0.5M+2.5P+15 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19 Polarity = 1, Phase = 0, from SPI1_CLK rising 1.5P-3 2.5P+15 1.5P-10 2.5P+17 1.5P-12 2.5P+19 Polarity = 1, Phase = 1, from SPI1_CLK rising –0.5M+1.5P-3 –0.5M+2.5P+15 –0.5M+1.5P-10 –0.5M+2.5P+17 –0.5M+1.5P-12 –0.5M+2.5P+19 UNIT ns These parameters are in addition to the general timings for SPI slave modes (Table 6-51). P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes. Submit Documentation Feedback Peripheral Information and Electrical Specifications 121 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-56. Additional (1) SPI1 Slave Timings, 4-Pin Chip Select Option (2) (3) NO. 25 26 1.2V PARAMETER td(SCSL_SPC)S td(SPC_SCSH)S MIN Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave. Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted. 1.1V MAX MIN 1.0V MAX MIN P+1.5 P+1.5 P+1.5 Polarity = 0, Phase = 0, from SPI1_CLK falling 0.5M+P+4 0.5M+P+5 0.5M+P+6 Polarity = 0, Phase = 1, from SPI1_CLK falling P+4 P+5 P+6 Polarity = 1, Phase = 0, from SPI1_CLK rising 0.5M+P+4 0.5M+P+5 0.5M+P+6 Polarity = 1, Phase = 1, from SPI1_CLK rising P+4 P+5 P+6 MAX UNIT ns ns 27 tena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid P+15 P+17 P+19 ns 28 tdis(SCSH_SOMI)S Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI P+15 P+17 P+19 ns (1) (2) (3) 122 These parameters are in addition to the general timings for SPI slave modes (Table 6-51). P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes. Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-57. Additional (1) SPI1 Slave Timings, 5-Pin Option (2) (3) NO. 25 26 1.2V PARAMETER td(SCSL_SPC)S td(SPC_SCSH)S MIN Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave. Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted. 1.1V MAX MIN 1.0V MAX MIN P+1.5 P+1.5 P+1.5 Polarity = 0, Phase = 0, from SPI1_CLK falling 0.5M+P+4 0.5M+P+5 0.5M+P+6 Polarity = 0, Phase = 1, from SPI1_CLK falling P+4 P+5 P+6 Polarity = 1, Phase = 0, from SPI1_CLK rising 0.5M+P+4 0.5M+P+5 0.5M+P+6 Polarity = 1, Phase = 1, from SPI1_CLK rising P+4 P+5 P+6 MAX UNIT ns ns 27 tena(SCSL_SOMI)S Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid P+15 P+17 P+19 ns 28 tdis(SCSH_SOMI)S Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI P+15 P+17 P+19 ns 29 tena(SCSL_ENA)S Delay from master deasserting SPI1_SCS to slave driving SPI1_ENA valid 15 17 19 ns Polarity = 0, Phase = 0, from SPI1_CLK falling 2.5P+15 2.5P+17 2.5P+19 Polarity = 0, Phase = 1, from SPI1_CLK rising 2.5P+15 2.5P+17 2.5P+19 Polarity = 1, Phase = 0, from SPI1_CLK rising 2.5P+15 2.5P+17 2.5P+19 Polarity = 1, Phase = 1, from SPI1_CLK falling 2.5P+15 2.5P+17 2.5P+19 30 (1) (2) (3) (4) tdis(SPC_ENA)S Delay from final clock receive edge on SPI1_CLK to slave 3-stating or driving high SPI1_ENA. (4) ns These parameters are in addition to the general timings for SPI slave modes (Table 6-51). P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes. SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master. Submit Documentation Feedback Peripheral Information and Electrical Specifications 123 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 1 2 MASTER MODE POLARITY = 0 PHASE = 0 3 SPIx_CLK 5 4 SPIx_SIMO MO(0) 7 SPIx_SOMI 6 MO(1) MO(n−1) MO(n) 8 MI(0) MI(1) MI(n−1) MI(n) PRODUCT PREVIEW MASTER MODE POLARITY = 0 PHASE = 1 4 SPIx_CLK 6 5 SPIx_SIMO MO(0) 7 SPIx_SOMI MO(1) MO(n−1) MI(1) MI(n−1) MO(n) 8 MI(0) MI(n) 4 MASTER MODE POLARITY = 1 PHASE = 0 SPIx_CLK 5 SPIx_SIMO 6 MO(0) 7 SPIx_SOMI MO(1) MO(n−1) MO(n) 8 MI(0) MI(1) MI(n−1) MI(n) MASTER MODE POLARITY = 1 PHASE = 1 SPIx_CLK 5 4 SPIx_SIMO MO(0) 7 SPIx_SOMI MI(0) 6 MO(1) MO(n−1) MI(1) MI(n−1) MO(n) 8 MI(n) Figure 6-33. SPI Timings—Master Mode 124 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 9 12 10 SLAVE MODE POLARITY = 0 PHASE = 0 11 SPIx_CLK 15 SPIx_SIMO 16 SI(0) SI(1) SI(n−1) 13 SPIx_SOMI SO(0) SI(n) 14 SO(1) SO(n−1) 12 SO(n) PRODUCT PREVIEW SLAVE MODE POLARITY = 0 PHASE = 1 SPIx_CLK 15 SPIx_SIMO 16 SI(0) SI(1) 13 SPIx_SOMI SO(0) SI(n−1) SI(n) SO(n−1) SO(n) 14 SO(1) SLAVE MODE POLARITY = 1 PHASE = 0 12 SPIx_CLK 15 SPIx_SIMO 16 SI(0) SI(1) SI(n−1) 13 SPIx_SOMI SO(0) SI(n) 14 SO(1) SO(n−1) SO(n) SLAVE MODE POLARITY = 1 PHASE = 1 12 SPIx_CLK 15 16 SPIx_SIMO SI(0) SPIx_SOMI SO(0) SI(1) 13 SO(1) SI(n−1) SI(n) 14 SO(n−1) SO(n) Figure 6-34. SPI Timings—Slave Mode Submit Documentation Feedback Peripheral Information and Electrical Specifications 125 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com MASTER MODE 4 PIN WITH ENABLE 17 18 SPIx_CLK SPIx_SIMO MO(0) SPIx_SOMI MI(0) MO(1) MO(n−1) MI(1) MI(n−1) MO(n) MI(n) SPIx_ENA MASTER MODE 4 PIN WITH CHIP SELECT 19 20 SPIx_CLK SPIx_SIMO MO(0) SPIx_SOMI PRODUCT PREVIEW MI(0) MO(1) MO(n−1) MO(n) MI(1) MI(n−1) MI(n) SPIx_SCS MASTER MODE 5 PIN 22 20 MO(1) 23 18 SPIx_CLK SPIx_SIMO MO(0) MO(n−1) MO(n) SPIx_SOMI 21 SPIx_ENA MI(0) MI(1) MI(n−1) MI(n) DESEL(A) DESEL(A) SPIx_SCS A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) Figure 6-35. SPI Timings—Master Mode (4-Pin and 5-Pin) 126 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 SLAVE MODE 4 PIN WITH ENABLE 24 SPIx_CLK SPIx_SOMI SO(0) SO(1) SO(n−1) SO(n) SPIx_SIMO SI(0) SPIx_ENA SI(1) SI(n−1) SI(n) SLAVE MODE 4 PIN WITH CHIP SELECT 26 25 SPIx_CLK SPIx_SOMI 28 SO(n−1) SO(0) SO(1) SO(n) PRODUCT PREVIEW 27 SPIx_SIMO SI(0) SPIx_SCS SI(1) SI(n−1) SI(n) SLAVE MODE 5 PIN 26 30 25 SPIx_CLK 27 SPIx_SOMI 28 SO(1) SO(0) SO(n−1) SO(n) SPIx_SIMO 29 SPIx_ENA DESEL(A) SI(0) SI(1) SI(n−1) SI(n) DESEL(A) SPIx_SCS A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) Figure 6-36. SPI Timings—Slave Mode (4-Pin and 5-Pin) Submit Documentation Feedback Peripheral Information and Electrical Specifications 127 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.15 Inter-Integrated Circuit Serial Ports (I2C) 6.15.1 I2C Device-Specific Information I2C port supports: • Compatible with Philips® I2C Specification Revision 2.1 (January 2000) • Fast Mode up to 400 Kbps (no fail-safe I/O buffers) • Noise Filter to Remove Noise 50 ns or less • Seven- and Ten-Bit Device Addressing Modes • Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality • Events: DMA, Interrupt, or Polling • General-Purpose I/O Capability if not used as I2C PRODUCT PREVIEW Figure 6-37 is block diagram of the device I2C Module. Clock Prescaler I2CPSCx Control Prescaler Register I2CCOARx Own Address Register I2CSARx Slave Address Register Bit Clock Generator I2Cx_SCL Noise Filter I2CCLKHx Clock Divide High Register I2CCMDRx Mode Register I2CCLKLx Clock Divide Low Register I2CEMDRx Extended Mode Register I2CCNTx Data Count Register I2CPID1 Peripheral ID Register 1 I2CPID2 Peripheral ID Register 2 Transmit I2Cx_SDA Noise Filter I2CXSRx Transmit Shift Register I2CDXRx Transmit Buffer Interrupt/DMA Receive I2CIERx I2CDRRx Receive Buffer I2CSTRx I2CRSRx Receive Shift Register I2CSRCx I2CPFUNC Pin Function Register I2CPDOUT Interrupt Enable Register Interrupt Status Register Interrupt Source Register Peripheral Configuration Bus Interrupt DMA Requests Control I2CPDIR I2CPDIN Pin Direction Register Pin Data In Register I2CPDSET I2CPDCLR Pin Data Out Register Pin Data Set Register Pin Data Clear Register Figure 6-37. I2C Module Block Diagram 128 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.15.2 I2C Peripheral Registers Description(s) Table 6-58 is the list of the I2C registers. Table 6-58. Inter-Integrated Circuit (I2C) Registers I2C0 BYTE ADDRESS ACRONYM 0x01C2 2000 ICOAR I2C Own Address Register 0x01C2 2004 ICIMR I2C Interrupt Mask Register 0x01C2 2008 ICSTR I2C Interrupt Status Register 0x01C2 200C ICCLKL I2C Clock Low-Time Divider Register 0x01C2 2010 ICCLKH I2C Clock High-Time Divider Register 0x01C2 2014 ICCNT I2C Data Count Register 0x01C2 2018 ICDRR I2C Data Receive Register 0x01C2 201C ICSAR I2C Slave Address Register 0x01C2 2020 ICDXR I2C Data Transmit Register 0x01C2 2024 ICMDR I2C Mode Register 0x01C2 2028 ICIVR I2C Interrupt Vector Register 0x01C2 202C ICEMDR I2C Extended Mode Register 0x01C2 2030 ICPSC I2C Prescaler Register 0x01C2 2034 REVID1 I2C Revision Identification Register 1 0x01C2 2038 REVID2 I2C Revision Identification Register 2 0x01C2 2048 ICPFUNC I2C Pin Function Register 0x01C2 204C ICPDIR I2C Pin Direction Register 0x01C2 2050 ICPDIN I2C Pin Data In Register 0x01C2 2054 ICPDOUT I2C Pin Data Out Register 0x01C2 2058 ICPDSET I2C Pin Data Set Register 0x01C2 205C ICPDCLR I2C Pin Data Clear Register Submit Documentation Feedback Peripheral Information and Electrical Specifications PRODUCT PREVIEW REGISTER DESCRIPTION 129 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.15.3 I2C Electrical Data/Timing 6.15.3.1 Inter-Integrated Circuit (I2C) Timing Table 6-59 and Table 6-60 assume testing over recommended operating conditions (see Figure 6-38 and Figure 6-39). Table 6-59. Timing Requirements for I2C Input 1.2V, 1.1V, 1.0V NO. PARAMETER Standard Mode MIN MAX Fast Mode MIN UNIT MAX PRODUCT PREVIEW 1 tc(SCL) Cycle time, I2Cx_SCL 10 2.5 µs 2 tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low 4.7 0.6 µs 3 th(SCLL-SDAL) Hold time, I2Cx_SCL low after I2Cx_SDA low 4 0.6 µs 4 tw(SCLL) Pulse duration, I2Cx_SCL low 4.7 1.3 µs 5 tw(SCLH) Pulse duration, I2Cx_SCL high 4 0.6 µs 6 tsu(SDA-SCLH) Setup time, I2Cx_SDA before I2Cx_SCL high 250 100 7 th(SDA-SCLL) Hold time, I2Cx_SDA after I2Cx_SCL low 0 0 8 tw(SDAH) Pulse duration, I2Cx_SDA high 4.7 1.3 ns 0.9 µs µs 9 tr(SDA) Rise time, I2Cx_SDA 1000 20 + 0.1Cb 300 ns 10 tr(SCL) Rise time, I2Cx_SCL 1000 20 + 0.1Cb 300 ns 11 tf(SDA) Fall time, I2Cx_SDA 300 20 + 0.1Cb 300 ns 12 tf(SCL) Fall time, I2Cx_SCL 300 20 + 0.1Cb 300 ns 13 tsu(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high 14 tw(SP) Pulse duration, spike (must be suppressed) 15 Cb Capacitive load for each bus line 4 0.6 N/A 0 µs 400 Table 6-60. Switching Characteristics for I2C 50 ns 400 pF (1) 1.2V, 1.1V, 1.0V NO. PARAMETER Standard Mode MIN MAX Fast Mode MIN UNIT MAX 16 tc(SCL) Cycle time, I2Cx_SCL 10 2.5 µs 17 tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low 4.7 0.6 µs 18 th(SDAL-SCLL) Hold time, I2Cx_SCL low after I2Cx_SDA low 4 0.6 µs 19 tw(SCLL) Pulse duration, I2Cx_SCL low 4.7 1.3 µs 20 tw(SCLH) Pulse duration, I2Cx_SCL high 4 0.6 µs 21 tsu(SDAV-SCLH) Setup time, I2Cx_SDA valid before I2Cx_SCL high 250 100 22 th(SCLL-SDAV) Hold time, I2Cx_SDA valid after I2Cx_SCL low 0 0 23 tw(SDAH) Pulse duration, I2Cx_SDA high 4.7 1.3 µs 28 tsu(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high 4 0.6 µs (1) 130 ns 0.9 µs I2C must be configured correctly to meet the timings in Table 6-60. Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 11 9 I2Cx_SDA 6 8 14 4 13 5 10 I2Cx_SCL 12 3 2 7 3 Stop Start Repeated Start Stop PRODUCT PREVIEW 1 Figure 6-38. I2C Receive Timings 26 24 I2Cx_SDA 21 23 19 28 20 25 I2Cx_SCL 16 27 18 17 22 18 Stop Start Repeated Start Stop Figure 6-39. I2C Transmit Timings Submit Documentation Feedback Peripheral Information and Electrical Specifications 131 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 6.16 www.ti.com Universal Asynchronous Receiver/Transmitter (UART) PRODUCT PREVIEW The UART has the following features: • 16-byte storage space for both the transmitter and receiver FIFOs • 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA • DMA signaling capability for both received and transmitted data • Programmable auto-rts and auto-cts for autoflow control • Programmable Baud Rate up to 3MBaud • Programmable Oversampling Options of x13 and x16 • Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates • Prioritized interrupts • Programmable serial data formats – 5, 6, 7, or 8-bit characters – Even, odd, or no parity bit generation and detection – 1, 1.5, or 2 stop bit generation • False start bit detection • Line break generation and detection • Internal diagnostic capabilities – Loopback controls for communications link fault isolation – Break, parity, overrun, and framing error simulation • Modem control functions (CTS, RTS) The UART registers are listed in Section 6.16.1 6.16.1 UART Peripheral Registers Description(s) Table 6-61 is the list of UART registers. Table 6-61. UART Registers 132 UART0 BYTE ADDRESS ACRONYM 0x01C4 2000 RBR Receiver Buffer Register (read only) 0x01C4 2000 THR Transmitter Holding Register (write only) 0x01C4 2004 IER Interrupt Enable Register 0x01C4 2008 IIR Interrupt Identification Register (read only) 0x01C4 2008 FCR FIFO Control Register (write only) 0x01C4 200C LCR Line Control Register 0x01C4 2010 MCR Modem Control Register 0x01C4 2014 LSR Line Status Register 0x01C4 2018 MSR Modem Status Register 0x01C4 201C SCR Scratchpad Register 0x01C4 2020 DLL Divisor LSB Latch 0x01C4 2024 DLH Divisor MSB Latch 0x01C4 2028 REVID1 0x01C4 2030 PWREMU_MGMT 0x01C4 2034 MDR Peripheral Information and Electrical Specifications REGISTER DESCRIPTION Revision Identification Register 1 Power and Emulation Management Register Mode Definition Register Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.16.2 UART Electrical Data/Timing Table 6-62. Timing Requirements for UART Receive (1) (see Figure 6-40) NO. 1.2V, 1.1V, 1.0V PARAMETER MIN MAX UNIT 4 tw(URXDB) Pulse duration, receive data bit (RXDn) 0.96U 1.05U ns 5 tw(URXSB) Pulse duration, receive start bit 0.96U 1.05U ns (1) U = UART baud time = 1/programmed baud rate. NO. (1) 1.2V, 1.1V, 1.0V PARAMETER 1 f(baud) Maximum programmable baud rate 2 tw(UTXDB) Pulse duration, transmit data bit (TXDn) 3 tw(UTXSB) Pulse duration, transmit start bit MIN MAX UNIT 3 MBaud U-2 U+2 ns U-2 U+2 ns U = UART baud time = 1/programmed baud rate. 3 2 UART_TXDn Start Bit Data Bits 5 4 UART_RXDn Start Bit Data Bits Figure 6-40. UART Transmit/Receive Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 133 PRODUCT PREVIEW Table 6-63. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (1) (see Figure 6-40) TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.17 Host-Port Interface (UHPI) 6.17.1 HPI Device-Specific Information The device includes a user-configurable 16-bit Host-port interface (HPI16). 6.17.2 HPI Peripheral Register Description(s) Table 6-64. HPI Control Registers BYTE ADDRESS ACRONYM 0x01E1 0000 PID 0x01E1 0004 PWREMU_MGMT REGISTER DESCRIPTION HPI power and emulation management register GPIO_EN 0x01E1 0010 GPIO_DIR1 General Purpose IO Direction Register 1 0x01E1 0014 GPIO_DAT1 General Purpose IO Data Register 1 0x01E1 0018 GPIO_DIR2 General Purpose IO Direction Register 2 0x01E1 001C GPIO_DAT2 General Purpose IO Data Register 2 0x01E1 0020 GPIO_DIR3 General Purpose IO Direction Register 3 0x01E1 0024 GPIO_DAT3 General Purpose IO Data Register 3 01E1 0028 - Reserved 01E1 002C - Reserved 01E1 0030 HPIC HPI control register 01E1 0034 HPIA (HPIAW) (1) HPI address register (Write) 01E1 0038 HPIA (HPIAR) (1) HPI address register (Read) 01E1 000C - 01E1 07FF - PRODUCT PREVIEW 0x01E1 0008 0x01E1 000C (1) 134 COMMENTS Peripheral Identification Register The CPU has read/write access to the PWREMU_MGMT register. Reserved General Purpose IO Enable Register The Host and the CPU both have read/write access to the HPIC register. The Host has read/write access to the HPIA registers. The CPU has only read access to the HPIA registers. Reserved There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the Host. The CPU can access HPIAW and HPIAR independently. Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.17.3 HPI Electrical Data/Timing Table 6-65. Timing Requirements for Host-Port Interface [1.2V, 1.1V] (1) (2) MIN MAX UNIT 1 tsu(SELV-HSTBL) Setup time, select signals (3) valid before UHPI_HSTROBE low 5 ns 2 th(HSTBL-SELV) Hold time, select signals (3) valid after UHPI_HSTROBE low 2 ns 3 tw(HSTBL) Pulse duration, UHPI_HSTROBE active low 15 ns 4 tw(HSTBH) Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses 2M ns 9 tsu(SELV-HASL) Setup time, selects signals valid before UHPI_HAS low 5 10 th(HASL-SELV) Hold time, select signals valid after UHPI_HAS low 2 11 tsu(HDV-HSTBH) Setup time, host data valid before UHPI_HSTROBE high 5 ns 12 th(HSTBH-HDV) Hold time, host data valid after UHPI_HSTROBE high 2 ns 13 th(HRDYL-HSTBH) Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE should not be inactivated until UHPI_HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns 16 tsu(HASL-HSTBL) Setup time, UHPI_HAS low before UHPI_HSTROBE low 5 17 th(HSTBL-HASH) Hold time, UHPI_HAS low after UHPI_HSTROBE low 2 (1) (2) (3) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS. M=SYSCLK2 period (CPU clock frequency)/2 in ns. For example, when running parts at 300 MHz, use M=6.67 ns. Select signals include: HCNTL[1:0], HR/W and HHWIL. Submit Documentation Feedback Peripheral Information and Electrical Specifications 135 PRODUCT PREVIEW 1.2V, 1.1V, 1.0V NO. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-66. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.2V, 1.1V] (1) (2) (3) NO. PARAMETER 1.2V MIN 1.1V MAX MIN MAX UNIT PRODUCT PREVIEW For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: Back-to-back HPIA writes (can be either first or second half-word) Case 2: HPIA write following a PREFETCH command (can be either first or second half-word) Case 3: HPID write when FIFO is full or flushing (can be either first or second half-word) Case 4: HPIA write and Write FIFO not empty For HPI Read, HRDY can go high (not ready) for these HPI Read conditions: Case 1: HPID read (with auto-increment) and data not in Read FIFO (can only happen to first half-word of HPID access) Case 2: First half-word access of HPID Read without auto-increment For HPI Read, HRDY stays low (ready) for these HPI Read conditions: Case 1: HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access) Case 2: HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access) Case 3: HPIC or HPIA read (applies to either half-word access) 5 td(HSTBL-HRDYV) Delay time, HSTROBE low to HRDY valid 5a td(HASL-HRDYV) Delay time, HAS low to HRDY valid 6 ten(HSTBL-HDLZ) Enable time, HD driven from HSTROBE low 7 td(HRDYL-HDV) Delay time, HRDY low to HD valid 8 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 14 tdis(HSTBH-HDHZ) Disable time, HD high-impedance from HSTROBE high 15 18 (1) (2) (3) 136 td(HSTBL-HDV) td(HSTBH-HRDYV) 15 17 15 17 1.5 1.5 0 1.5 ns ns 0 1.5 ns ns 15 17 ns Delay time, HSTROBE low to HD valid For HPI Read. Applies to conditions where data is already residing in HPID/FIFO: Case 1: HPIC or HPIA read Case 2: First half-word of HPID read with auto-increment and data is already in Read FIFO Case 3: Second half-word of HPID read with or without auto-increment 15 17 ns Delay time, HSTROBE high to HRDY valid For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: HPID write when Write FIFO is full (can happen to either half-word) Case 2: HPIA write (can happen to either half-word) Case 3: HPID write without auto-increment (only happens to second half-word) 15 17 ns M=SYSCLK2 period (CPU clock frequency)/2 in ns. For example, when running parts at 300 MHz, use M=6.67 ns. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low). Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-67. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V] (1) (2) (3) NO. 1.0V PARAMETER MIN MAX UNIT For HPI Read, HRDY can go high (not ready) for these HPI Read conditions: Case 1: HPID read (with auto-increment) and data not in Read FIFO (can only happen to first half-word of HPID access) Case 2: First half-word access of HPID Read without auto-increment For HPI Read, HRDY stays low (ready) for these HPI Read conditions: Case 1: HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access) Case 2: HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access) Case 3: HPIC or HPIA read (applies to either half-word access) 5 td(HSTBL-HRDYV) Delay time, HSTROBE low to HRDY valid 5a td(HASL-HRDYV) Delay time, HAS low to HRDY valid 6 ten(HSTBL-HDLZ) Enable time, HD driven from HSTROBE low 7 td(HRDYL-HDV) Delay time, HRDY low to HD valid 8 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 14 tdis(HSTBH-HDHZ) Disable time, HD high-impedance from HSTROBE high 15 18 (1) (2) (3) td(HSTBL-HDV) td(HSTBH-HRDYV) 22 ns 22 1.5 ns 0 1.5 ns ns 22 ns Delay time, HSTROBE low to HD valid For HPI Read. Applies to conditions where data is already residing in HPID/FIFO: Case 1: HPIC or HPIA read Case 2: First half-word of HPID read with auto-increment and data is already in Read FIFO Case 3: Second half-word of HPID read with or without auto-increment 22 ns Delay time, HSTROBE high to HRDY valid For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: HPID write when Write FIFO is full (can happen to either half-word) Case 2: HPIA write (can happen to either half-word) Case 3: HPID write without auto-increment (only happens to second half-word) 22 ns M=SYSCLK2 period (CPU clock frequency)/2 in ns. For example, when running parts at 300 MHz, use M=6.67 ns. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low). Submit Documentation Feedback Peripheral Information and Electrical Specifications 137 PRODUCT PREVIEW For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: Back-to-back HPIA writes (can be either first or second half-word) Case 2: HPIA write following a PREFETCH command (can be either first or second half-word) Case 3: HPID write when FIFO is full or flushing (can be either first or second half-word) Case 4: HPIA write and Write FIFO not empty TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com UHPI_HCS UHPI_HAS(D) 2 2 1 1 UHPI_HCNTL[1:0] 2 1 2 1 UHPI_HR/W 2 2 1 1 UHPI_HHWIL PRODUCT PREVIEW 4 3 3 UHPI_HSTROBE(A)(C) 15 15 14 14 6 8 8 6 UHPI_HD[15:0] (output) 5 13 7 1st Half-Word 2nd Half-Word UHPI_HRDY(B) A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR UHPI_HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE. D The diagram above assumes UHPI_HAS has been pulled high. Figure 6-41. UHPI Read Timing (HAS Not Used, Tied High) 138 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 UHPI_HAS(A) 17 10 17 9 10 9 UHPI_HCNTL[1:0] 10 10 9 9 UHPI_HR/W 10 10 9 9 UHPI_HHWIL 4 3 UHPI_HSTROBE(B) 14 UHPI_HD[15:0] 6 (output) 5a 8 1st half-word 14 15 7 PRODUCT PREVIEW 16 16 UHPI_HCS 8 2nd half-word UHPI_HRDY A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle. B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS. Figure 6-42. UHPI Read Timing (HAS Used) Submit Documentation Feedback Peripheral Information and Electrical Specifications 139 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com UHPI_HCS UHPI_HAS(D) 1 1 2 2 UHPI_HCNTL[1:0] 1 1 2 2 UHPI_HR/W 1 1 2 2 PRODUCT PREVIEW UHPI_HHWIL 3 3 4 UHPI_HSTROBE(A)(C) 11 UHPI_HD[15:0] (input) 11 12 12 1st Half-Word 5 13 2nd Half-Word 18 13 18 5 UHPI_HRDY(B) A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR UHPI_HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE. D The diagram above assumes UHPI_HAS has been pulled high. Figure 6-43. UHPI Write Timing (HAS Not Used, Tied High) 140 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 17 UHPI_HAS† 17 10 10 9 9 UHPI_HCNTL[1:0] 10 10 9 9 UHPI_HR/W 10 10 9 9 UHPI_HHWIL 3 4 16 16 UHPI_HCS 11 12 UHPI_HD[15:0] (input) 1st half-word 5a PRODUCT PREVIEW UHPI_HSTROBE‡ 11 12 2nd half-word 13 UHPI_HRDY A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle. B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS. Figure 6-44. UHPI Write Timing (HAS Used) Submit Documentation Feedback Peripheral Information and Electrical Specifications 141 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.18 Enhanced Capture (eCAP) Peripheral The device contains up to three enhanced capture (eCAP) modules. Figure 6-45 shows a functional block diagram of a module. Uses for ECAP include: • Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors) • Elapsed time measurements between position sensor triggers • Period and duty cycle measurements of pulse train signals • Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors PRODUCT PREVIEW The ECAP module described in this specification includes the following features: • 32 bit time base • 4 event time-stamp registers (each 32 bits) • Edge polarity selection for up to 4 sequenced time-stamp capture events • Interrupt on either of the 4 events • Single shot capture of up to 4 event time-stamps • Continuous mode capture of time-stamps in a 4 deep circular buffer • Absolute time-stamp capture • Difference mode time-stamp capture • All the above resources are dedicated to a single input pin The eCAP modules are clocked at the ASYNC3 clock domain rate. The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, and ECAP4EN CLK are set to low, indicating that the peripheral clock is off. 142 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 SYNC www.ti.com SYNCIn SYNCOut CTRPHS (phase register−32 bit) TSCTR (counter−32 bit) APWM mode OVF RST CTR_OVF Delta−mode CTR [0−31] PRD [0−31] PWM compare logic CMP [0−31] 32 CTR=PRD CTR [0−31] CTR=CMP 32 LD1 CAP1 (APRD active) APRD shadow 32 32 Polarity select LD 32 CMP [0−31] CAP2 (ACMP active) 32 LD LD2 Polarity select Event qualifier ACMP shadow 32 CAP3 (APRD shadow) LD 32 CAP4 (ACMP shadow) LD eCAPx PRODUCT PREVIEW 32 MODE SELECT PRD [0−31] Event Pre-scale Polarity select LD3 LD4 Polarity select 4 Capture events 4 CEVT[1:4] to Interrupt Controller Interrupt Trigger and Flag control CTR_OVF Continuous / Oneshot Capture Control CTR=PRD CTR=CMP Figure 6-45. eCAP Functional Block Diagram Submit Documentation Feedback Peripheral Information and Electrical Specifications 143 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-68 is the list of the ECAP registers. Table 6-68. ECAPx Configuration Registers ECAP0 BYTE ADDRESS ECAP1 BYTE ADDRESS ECAP2 BYTE ADDRESS 0x01F0 6000 0x01F0 7000 0x01F0 8000 TSCTR 0x01F0 6004 0x01F0 7004 0x01F0 8004 CTRPHS 0x01F0 6008 0x01F0 7008 0x01F0 8008 CAP1 Capture 1 Register 0x01F0 600C 0x01F0 700C 0x01F0 800C CAP2 Capture 2 Register 0x01F0 6010 0x01F0 7010 0x01F0 8010 CAP3 Capture 3 Register 0x01F0 6014 0x01F0 7014 0x01F0 8014 CAP4 Capture 4 Register 0x01F0 6028 0x01F0 7028 0x01F0 8028 ECCTL1 Capture Control Register 1 REGISTER NAME DESCRIPTION Time-Stamp Counter Counter Phase Offset Value Register PRODUCT PREVIEW 0x01F0 602A 0x01F0 702A 0x01F0 802A ECCTL2 Capture Control Register 2 0x01F0 602C 0x01F0 702C 0x01F0 802C ECEINT Capture Interrupt Enable Register 0x01F0 602E 0x01F0 702E 0x01F0 802E ECFLG Capture Interrupt Flag Register 0x01F0 6030 0x01F0 7030 0x01F0 8030 ECCLR Capture Interrupt Clear Register 0x01F0 6032 0x01F0 7032 0x01F0 8032 ECFRC Capture Interrupt Force Register 0x01F0 605C 0x01F0 705C 0x01F0 805C REVID Revision ID Table 6-69 shows the eCAP timing requirement and Table 6-70 shows the eCAP switching characteristics. Table 6-69. Timing Requirements for Enhanced Capture (eCAP) PARAMETER TEST CONDITIONS 1.2V, 1.1V, 1.0V MIN tw(CAP) Capture input pulse width MAX UNIT Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles Table 6-70. Switching Characteristics Over Recommended Operating Conditions for eCAP PARAMETER 1.2V MIN tw(APWM) 144 Pulse duration, APWMx output high/low Peripheral Information and Electrical Specifications 20 1.1V MAX MIN 20 1.0V MAX MIN 20 UNIT MAX ns Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.19 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) The device contains two enhanced PWM Modules (eHRPWM). Figure 6-46 shows a block diagram of multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the eHRPWM. EPWMSYNCI EPWM0INT EPWM0SYNCI EPWM0A ePWM0 module EPWM0B PRODUCT PREVIEW TZ Interrupt Controllers EPWM0SYNCO GPIO MUX EPWM1SYNCI EPWM1INT EPWM1A ePWM1 module EPWM1SYNCO To eCAP0 module (sync in) EPWM1B TZ EPWMSYNCO Peripheral Bus Figure 6-46. Multiple PWM Modules in a C6742 System Submit Documentation Feedback Peripheral Information and Electrical Specifications 145 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Time−base (TB) Sync in/out select Mux CTR=ZERO CTR=CMPB Disabled TBPRD shadow (16) TBPRD active (16) CTR=PRD EPWMSYNCO TBCTL[SYNCOSEL] TBCTL[CNTLDE] EPWMSYNCI Counter up/down (16 bit) CTR=ZERO CTR_Dir TBCNT active (16) TBPHSHR (8) PRODUCT PREVIEW 16 8 TBPHS active (24) Phase control Counter compare (CC) CTR=CMPA CMPAHR (8) 16 TBCTL[SWFSYNC] (software forced sync) Action qualifier (AQ) CTR = PRD CTR = ZERO CTR = CMPA CTR = CMPB CTR_Dir 8 Event trigger and interrupt (ET) EPWMxINT HiRes PWM (HRPWM) CMPA active (24) EPWMA EPWMxA CMPA shadow (24) CTR=CMPB Dead band (DB) 16 PWM chopper (PC) EPWMB EPWMxB CMPB active (16) CMPB shadow (16) Trip zone (TZ) EPWMxTZINT CTR = ZERO TZ Figure 6-47. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections 146 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-71. eHRPWM Module Control and Status Registers Grouped by Submodule eHRPWM0 BYTE ADDRESS eHRPWM1 BYTE ADDRESS 0x01F0 0000 0x01F0 2000 TBCTL No Time-Base Control Register 0x01F0 0002 0x01F0 2002 TBSTS No Time-Base Status Register 0x01F0 0004 0x01F0 2004 TBPHSHR No Extension for HRPWM Phase Register 0x01F0 0006 0x01F0 2006 TBPHS No Time-Base Phase Register 0x01F0 0008 0x01F0 2008 TBCNT No Time-Base Counter Register 0x01F0 000A 0x01F0 200A TBPRD Yes Time-Base Period Register 0x01F0 000E 0x01F0 200E CMPCTL No Counter-Compare Control Register 0x01F0 0010 0x01F0 2010 CMPAHR No Extension for HRPWM Counter-Compare A Register 0x01F0 0012 0x01F0 2012 CMPA Yes Counter-Compare A Register 0x01F0 0014 0x01F0 2014 CMPB Yes Counter-Compare B Register Acronym Shadow Register Description Time-Base Submodule Registers (1) (1) Action-Qualifier Submodule Registers 0x01F0 0016 0x01F0 2016 AQCTLA No Action-Qualifier Control Register for Output A (eHRPWMxA) 0x01F0 0018 0x01F0 2018 AQCTLB No Action-Qualifier Control Register for Output B (eHRPWMxB) 0x01F0 001A 0x01F0 201A AQSFRC No Action-Qualifier Software Force Register 0x01F0 001C 0x01F0 201C AQCSFRC Yes Action-Qualifier Continuous S/W Force Register Set 0x01F0 001E 0x01F0 201E DBCTL No Dead-Band Generator Control Register 0x01F0 0020 0x01F0 2020 DBRED No Dead-Band Generator Rising Edge Delay Count Register 0x01F0 0022 0x01F0 2022 DBFED No Dead-Band Generator Falling Edge Delay Count Register Dead-Band Generator Submodule Registers PWM-Chopper Submodule Registers 0x01F0 003C 0x01F0 203C PCCTL No PWM-Chopper Control Register Trip-Zone Submodule Registers 0x01F0 0024 0x01F0 2024 TZSEL No Trip-Zone Select Register 0x01F0 0028 0x01F0 2028 TZCTL No Trip-Zone Control Register 0x01F0 002A 0x01F0 202A TZEINT No Trip-Zone Enable Interrupt Register 0x01F0 002C 0x01F0 202C TZFLG No Trip-Zone Flag Register 0x01F0 002E 0x01F0 202E TZCLR No Trip-Zone Clear Register 0x01F0 0030 0x01F0 2030 TZFRC No Trip-Zone Force Register 0x01F0 0032 0x01F0 2032 ETSEL No Event-Trigger Selection Register 0x01F0 0034 0x01F0 2034 ETPS No Event-Trigger Pre-Scale Register 0x01F0 0036 0x01F0 2036 ETFLG No Event-Trigger Flag Register 0x01F0 0038 0x01F0 2038 ETCLR No Event-Trigger Clear Register 0x01F0 003A 0x01F0 203A ETFRC No Event-Trigger Force Register Event-Trigger Submodule Registers High-Resolution PWM (HRPWM) Submodule Registers 0x01F0 1020 (1) 0x01F0 3020 HRCNFG No HRPWM Configuration Register (1) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these locations are reserved. Submit Documentation Feedback Peripheral Information and Electrical Specifications 147 PRODUCT PREVIEW Counter-Compare Submodule Registers TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.19.1 Enhanced Pulse Width Modulator (eHRPWM) Timing PWM refers to PWM outputs on eHRPWM1-6. Table 6-72 shows the PWM timing requirements and Table 6-73, switching characteristics. Table 6-72. Timing Requirements for eHRPWM PARAMETER TEST CONDITIONS 1.2V, 1.1V, 1.0V MIN tw(SYNCIN) Sync input pulse width UNIT MAX Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles Table 6-73. Switching Characteristics Over Recommended Operating Conditions for eHRPWM PRODUCT PREVIEW PARAMETER tw(PWM) Pulse duration, PWMx output high/low tw(SYNCOUT) Sync output pulse width td(PWM)TZA Delay time, trip input active to PWM forced high Delay time, trip input active to PWM forced low td(TZ-PWM)HZ 148 TEST CONDITIONS 1.2V MIN 1.1V MAX MIN 1.0V MAX MIN 20 TBD TBD 8tc(SCO) 8tc(SCO) 8tc(SCO) UNIT MAX ns cycles no pin load Delay time, trip input active to PWM Hi-Z Peripheral Information and Electrical Specifications ns 25 TBD TBD 20 TBD TBD ns Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.19.2 Trip-Zone Input Timing tw(TZ) TZ td(TZ-PWM)HZ PWM(A) A. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Table 6-74. Trip-Zone input Timing Requirements PARAMETER TEST CONDITIONS 1.2V, 1.1V, 1.0V MIN tw(TZ) Pulse duration, TZx input low MAX UNIT Asynchronous 1tc(SCO) cycles Synchronous 2tc(SCO) cycles Table 6-75 shows the high-resolution PWM switching characteristics. Table 6-75. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz) PARAMETER 1.2V MIN Micro Edge Positioning (MEP) step size (1) (1) TYP 200 1.1V MAX MIN TYP TBD 1.0V MAX MIN TYP MAX UNIT TBD ps Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase with low voltage and high temperature and decrease with voltage and cold temperature. Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per SYSCLKOUT period dynamically while the HRPWM is in operation. Submit Documentation Feedback Peripheral Information and Electrical Specifications 149 PRODUCT PREVIEW Figure 6-48. PWM Hi-Z Characteristics TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.20 Timers The timers support the following features: • Configurable as single 64-bit timer or two 32-bit timers • Period timeouts generate interrupts, DMA events or external pin events • 8 32-bit compare registers • Compare matches generate interrupt events • Capture capability • 64-bit Watchdog capability (Timer64P1 only) Table 6-76 lists the timer registers. Table 6-76. Timer Registers PRODUCT PREVIEW TIMER64P 0 BYTE ADDRESS TIMER64P 1 BYTE ADDRESS ACRONYM 0x01C2 0000 0x01C2 1000 REV 0x01C2 0004 0x01C2 1004 EMUMGT 0x01C2 0008 0x01C2 1008 GPINTGPEN 0x01C2 000C 0x01C2 100C GPDATGPDIR 0x01C2 0010 0x01C2 1010 TIM12 Timer Counter Register 12 0x01C2 0014 0x01C2 1014 TIM34 Timer Counter Register 34 0x01C2 0018 0x01C2 1018 PRD12 Timer Period Register 12 0x01C2 001C 0x01C2 101C PRD34 Timer Period Register 34 0x01C2 0020 0x01C2 1020 TCR 0x01C2 0024 0x01C2 1024 TGCR 0x01C2 0028 0x01C2 1028 WDTCR 0x01C2 0034 0x01C2 1034 REL12 Timer Reload Register 12 0x01C2 0038 0x01C2 1038 REL34 Timer Reload Register 34 0x01C2 003C 0x01C2 103C CAP12 Timer Capture Register 12 0x01C2 0040 0x01C2 1040 CAP34 Timer Capture Register 34 0x01C2 0044 0x01C2 1044 INTCTLSTAT 0x01C2 0060 0x01C2 1060 CMP0 Compare Register 0 0x01C2 0064 0x01C2 1064 CMP1 Compare Register 1 0x01C2 0068 0x01C2 1068 CMP2 Compare Register 2 0x01C2 006C 0x01C2 106C CMP3 Compare Register 3 0x01C2 0070 0x01C2 1070 CMP4 Compare Register 4 0x01C2 0074 0x01C2 1074 CMP5 Compare Register 5 0x01C2 0078 0x01C2 1078 CMP6 Compare Register 6 0x01C2 007C 0x01C2 107C CMP7 Compare Register 7 150 Peripheral Information and Electrical Specifications REGISTER DESCRIPTION Revision Register Emulation Management Register GPIO Interrupt and GPIO Enable Register GPIO Data and GPIO Direction Register Timer Control Register Timer Global Control Register Watchdog Timer Control Register Timer Interrupt Control and Status Register Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com 6.20.1 SPRS587 – JUNE 2009 Timer Electrical Data/Timing Table 6-77. Timing Requirements for Timer Input (1) (2) (see Figure 6-49) NO. 1.2V, 1.1V, 1.0V PARAMETER MIN MAX 1 tc(TM64Px_IN12) Cycle time, TM64Px_IN12 2 tw(TINPH) Pulse duration, TM64Px_IN12 high 0.45C 0.55C ns 3 tw(TINPL) Pulse duration, TM64Px_IN12 low 0.45C 0.55C ns 4 tt(TM64Px_IN12) Transition time, TM64Px_IN12 0.05C ns ns P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns. C = TM64P0_IN12 cycle time in ns. For example, when TM64Px_IN12 frequency is 27 MHz, use C = 37.037 ns 1 2 3 4 4 TM64P0_IN12 Figure 6-49. Timer Timing Table 6-78. Switching Characteristics Over Recommended Operating Conditions for Timer Output NO. 5 6 (1) 1.2V, 1.1V, 1.0V PARAMETER MIN MAX (1) UNIT tw(TOUTH) Pulse duration, TM64P0_OUT12 high 4P ns tw(TOUTL) Pulse duration, TM64P0_OUT12 low 4P ns P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns. 5 6 TM64P0_OUT12 Figure 6-50. Timer Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 151 PRODUCT PREVIEW (1) (2) 4P UNIT TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.21 Real Time Clock (RTC) The RTC provides a time reference to an application running on the device. The current date and time is tracked in a set of counter registers that update once per second. The time can be represented in 12-hour or 24-hour mode. The calendar and time registers are buffered during reads and writes so that updates do not interfere with the accuracy of the time and date. Alarms are available to interrupt the CPU at a particular time, or at periodic time intervals, such as once per minute or once per day. In addition, the RTC can interrupt the CPU every time the calendar and time registers are updated, or at programmable periodic intervals. PRODUCT PREVIEW The real-time clock (RTC) provides the following features: • 100-year calendar (xx00 to xx99) • Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation • Binary-coded-decimal (BCD) representation of time, calendar, and alarm • 12-hour clock mode (with AM and PM) or 24-hour clock mode • Alarm interrupt • Periodic interrupt • Single interrupt to the CPU • Supports external 32.768-kHz crystal or external clock source of the same frequency • Separate isolated power supply Figure 6-51 shows a block diagram of the RTC. RTC_XI Counter 32 kHz Oscillator Compensation Seconds Minutes Week Days XTAL RTC_XO Hours Days Months Years Oscillator Alarm Alarm Interrupts Timer Periodic Interrupts Figure 6-51. Real-Time Clock Block Diagram 152 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.21.1 Clock Source The clock reference for the RTC is an external 32.768-kHz crystal or an external clock source of the same frequency. The RTC also has a separate power supply that is isolated from the rest of the system. When the CPU and other peripherals are without power, the RTC can remain powered to preserve the current time and calendar information. Even if the RTC is not used, it must remain powered when the rest of the device is powered. The source for the RTC reference clock may be provided by a crystal or by an external clock source. The RTC has an internal oscillator buffer to support direct operation with a crystal. The crystal is connected between pins RTC_XI and RTC_XO. RTC_XI is the input to the on-chip oscillator and RTC_XO is the output from the oscillator back to the crystal. If the RTC is not used, the RTC_XI pin should be held either low or high, RTC_XO should be left unconnected, RTC_CVDD should be connected to the device CVDD and RTC_VSS should remain grounded. Switch for Device Core Power +1.2V CVDD Real Time Clock C2 XTAL 32.768 kHz RTC_CVDD RTC_X1 RTC_X0 32K OSC C1 Real Time Clock (RTC) Module RTC_VSS Isolated RTC Power Domain Figure 6-52. Clock Source Submit Documentation Feedback Peripheral Information and Electrical Specifications 153 PRODUCT PREVIEW An external 32.768-kHz clock source may be used instead of a crystal. In such a case, the clock source is connected to RTC_XI, and RTC_XO is left unconnected. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.21.2 Registers Table 6-79 lists the memory-mapped registers for the RTC. See the device-specific data manual for the memory address of these registers. Table 6-79. Real-Time Clock (RTC) Registers BYTE ADDRESS ACRONYM 0x01C2 3000 SECOND Seconds Register 0x01C2 3004 MINUTE Minutes Register PRODUCT PREVIEW 154 0x01C2 3008 HOUR 0x01C2 300C DAY 0x01C2 3010 MONTH REGISTER DESCRIPTION Hours Register Day of the Month Register Month Register 0x01C2 3014 YEAR Year Register 0x01C2 3018 DOTW Day of the Week Register 0x01C2 3020 ALARMSECOND Alarm Seconds Register 0x01C2 3024 ALARMMINUTE Alarm Minutes Register 0x01C2 3028 ALARMHOUR Alarm Hours Register 0x01C2 302C ALARMDAY Alarm Days Register 0x01C2 3030 ALARMMONTH 0x01C2 3034 ALARMYEAR 0x01C2 3040 CTRL Control Register 0x01C2 3044 STATUS Status Register Alarm Months Register Alarm Years Register 0x01C2 3048 INTERRUPT 0x01C2 304C COMPLSB Interrupt Enable Register Compensation (LSB) Register 0x01C2 3050 COMPMSB Compensation (MSB) Register 0x01C2 3054 OSC 0x01C2 3060 SCRATCH0 Scratch 0 (General-Purpose) Register 0x01C2 3064 SCRATCH1 Scratch 1 (General-Purpose) Register 0x01C2 3068 SCRATCH2 Scratch 2 (General-Purpose) Register 0x01C2 306C KICK0 Kick 0 (Write Protect) Register 0x01C2 3070 KICK1 Kick 1 (Write Protect) Register Oscillator Register Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.22 General-Purpose Input/Output (GPIO) The device GPIO peripheral supports the following: • Up to 144 Pins configurable as GPIO • External Interrupt and DMA request Capability – Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or falling edges on the pin. – The interrupt requests within each bank are combined (logical or) to create eight unique bank level interrupt requests. – The bank level interrupt service routine may poll the INTSTATx register for its bank to determine which pin(s) have triggered the interrupt. – GPIO Banks 0, 1, 2, 3, 4, 5, 6, 7 and 8 Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59, 62, 72 and 75 respectively – GPIO Banks 0, 1, 2, 3, 4, and 5 are assigned to EDMA events 6, 7, 22, 23, 28, 29, and 29 respectively on Channel Controller 0 and GPIO Banks 6, 7, and 8 are assigned to EDMA events 16, 17, and 18 respectively on Channel Controller 1. • Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to anther process during GPIO programming). • Separate Input/Output registers • Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can be toggled by direct write to the output register(s). • Output register, when read, reflects output drive status. This, in addition to the input register reflecting pin status and open-drain I/O cell, allows wired logic be implemented. The memory map for the GPIO registers is shown in Table 6-80. Submit Documentation Feedback Peripheral Information and Electrical Specifications 155 PRODUCT PREVIEW The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices. The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]). TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 6.22.1 GPIO Register Description(s) Table 6-80. GPIO Registers BYTE ADDRESS ACRONYM 0x01E2 6000 REV 0x01E2 6004 RESERVED 0x01E2 6008 BINTEN REGISTER DESCRIPTION Peripheral Revision Register Reserved GPIO Interrupt Per-Bank Enable Register GPIO Banks 0 and 1 0x01E2 6010 DIR01 0x01E2 6014 OUT_DATA01 GPIO Banks 0 and 1 Direction Register GPIO Banks 0 and 1 Output Data Register PRODUCT PREVIEW 0x01E2 6018 SET_DATA01 GPIO Banks 0 and 1 Set Data Register 0x01E2 601C CLR_DATA01 GPIO Banks 0 and 1 Clear Data Register 0x01E2 6020 IN_DATA01 GPIO Banks 0 and 1 Input Data Register 0x01E2 6024 SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register 0x01E2 6028 CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register 0x01E2 602C SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register 0x01E2 6030 CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register 0x01E2 6034 INTSTAT01 GPIO Banks 0 and 1 Interrupt Status Register GPIO Banks 2 and 3 0x01E2 6038 DIR23 GPIO Banks 2 and 3 Direction Register 0x01E2 603C OUT_DATA23 GPIO Banks 2 and 3 Output Data Register 0x01E2 6040 SET_DATA23 GPIO Banks 2 and 3 Set Data Register 0x01E2 6044 CLR_DATA23 GPIO Banks 2 and 3 Clear Data Register GPIO Banks 2 and 3 Input Data Register 0x01E2 6048 IN_DATA23 0x01E2 604C SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register 0x01E2 6050 CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register 0x01E2 6054 SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register 0x01E2 6058 CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register 0x01E2 605C INTSTAT23 GPIO Banks 2 and 3 Interrupt Status Register GPIO Banks 4 and 5 0x01E2 6060 DIR45 0x01E2 6064 OUT_DATA45 GPIO Banks 4 and 5 Direction Register GPIO Banks 4 and 5 Output Data Register 0x01E2 6068 SET_DATA45 GPIO Banks 4 and 5 Set Data Register 0x01E2 606C CLR_DATA45 GPIO Banks 4 and 5 Clear Data Register 0x01E2 6070 IN_DATA45 GPIO Banks 4 and 5 Input Data Register 0x01E2 6074 SET_RIS_TRIG45 GPIO Banks 4 and 5 Set Rising Edge Interrupt Register 0x01E2 6078 CLR_RIS_TRIG45 GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register 0x01E2 607C SET_FAL_TRIG45 GPIO Banks 4 and 5 Set Falling Edge Interrupt Register 0x01E2 6080 CLR_FAL_TRIG45 GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register 0x01E2 6084 INTSTAT45 0x01E2 6088 DIR67 0x01E2 608C OUT_DATA67 GPIO Banks 6 and 7 Output Data Register 0x01E2 6090 SET_DATA67 GPIO Banks 6 and 7 Set Data Register 0x01E2 6094 CLR_DATA67 GPIO Banks 6 and 7 Clear Data Register 0x01E2 6098 IN_DATA67 GPIO Banks 6 and 7 Input Data Register GPIO Banks 4 and 5 Interrupt Status Register GPIO Banks 6 and 7 156 GPIO Banks 6 and 7 Direction Register 0x01E2 609C SET_RIS_TRIG67 GPIO Banks 6 and 7 Set Rising Edge Interrupt Register 0x01E2 60A0 CLR_RIS_TRIG67 GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register 0x01E2 60A4 SET_FAL_TRIG67 GPIO Banks 6 and 7 Set Falling Edge Interrupt Register Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 Table 6-80. GPIO Registers (continued) BYTE ADDRESS ACRONYM 0x01E2 60A8 CLR_FAL_TRIG67 REGISTER DESCRIPTION 0x01E2 60AC INTSTAT67 0x01E2 60B0 DIR8 0x01E2 60B4 OUT_DATA8 GPIO Bank 8 Output Data Register GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register GPIO Banks 6 and 7 Interrupt Status Register GPIO Bank 8 0x01E2 60B8 SET_DATA8 GPIO Bank 8 Set Data Register 0x01E2 60BC CLR_DATA8 GPIO Bank 8 Clear Data Register 0x01E2 60C0 IN_DATA8 GPIO Bank 8 Input Data Register 0x01E2 60C4 SET_RIS_TRIG8 GPIO Bank 8 Set Rising Edge Interrupt Register 0x01E2 60C8 CLR_RIS_TRIG8 GPIO Bank 8 Clear Rising Edge Interrupt Register 0x01E2 60CC SET_FAL_TRIG8 GPIO Bank 8 Set Falling Edge Interrupt Register 0x01E2 60D0 CLR_FAL_TRIG8 GPIO Bank 8 Clear Falling Edge Interrupt Register 0x01E2 60D4 INTSTAT8 Submit Documentation Feedback PRODUCT PREVIEW GPIO Bank 8 Direction Register GPIO Bank 8 Interrupt Status Register Peripheral Information and Electrical Specifications 157 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 6.22.2 www.ti.com GPIO Peripheral Input/Output Electrical Data/Timing Table 6-81. Timing Requirements for GPIO Inputs (1) (see Figure 6-53) 1.2V, 1.1V, 1.0V NO. 1 tw(GPIH) 2 (1) MIN tw(GPIL) Pulse duration, GPn[m] as input high Pulse duration, GPn[m] as input low MAX UNIT 2C (1) (2) ns (1) (2) ns 2C The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device enough time to access the GPIO register through the internal bus. C=SYSCLK4 period in ns. For example, when running parts at 300 MHz, C=13.33 ns (2) PRODUCT PREVIEW Table 6-82. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 6-53) NO. 3 tw(GPOH) 4 (1) 1.2V, 1.1V, 1.0V PARAMETER tw(GPOL) MIN 2C (1) Pulse duration, GPn[m] as output high Pulse duration, GPn[m] as output low 2C MAX UNIT (2) ns (1) (2) ns This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity. C=SYSCLK4 period in ns. For example, when running parts at 300 MHz, C=13.33 ns (2) 2 1 GPn[m] as input 4 3 GPn[m] as output Figure 6-53. GPIO Port Timing 6.22.3 GPIO Peripheral External Interrupts Electrical Data/Timing Table 6-83. Timing Requirements for External Interrupts (1) (see Figure 6-54) 1.2V, 1.1V, 1.0V NO. MIN MAX UNIT 1 tw(ILOW) Width of the external interrupt pulse low 2C (1) (2) ns 2 tw(IHIGH) Width of the external interrupt pulse high 2C (1) (2) ns (1) (2) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have the device recognize the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to access the GPIO register through the internal bus. C=SYSCLK4 period in ns. For example, when running parts at 300 MHz, C=13.33 ns 2 GPn[m] as input 1 Figure 6-54. GPIO External Interrupt Timing 158 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 6.23 Emulation Logic The debug capabilities and features for DSP are as shown below. PRODUCT PREVIEW DSP: • Basic Debug – Execution Control – System Visibility • Real-Time Debug – Interrupts serviced while halted – Low/non-intrusive system visibility while running • Advanced Debug – Global Start – Global Stop – Specify targeted memory level(s) during memory accesses – HSRTDX (High Speed Real Time Data eXchange) • Advanced System Control – Subsystem reset via debug – Peripheral notification of debug events – Cache-coherent debug accesses • Analysis Actions – Stop program execution – Generate debug interrupt – Benchmarking with counters – External trigger generation – Debug state machine state transition – Combinational and Sequential event generation • Analysis Events – Program event detection – Data event detection – External trigger Detection – System event detection (i.e. cache miss) – Debug state machine state detection • Analysis Configuration – Application access – Debugger access Table 6-84. DSP Debug Features Category Hardware Feature Availability Software breakpoint Unlimited Up to 10 HWBPs, including: Basic Debug Hardware breakpoint 4 precise (1) HWBPs inside DSP core and one of them is associated with a counter. 2 imprecise (1) HWBPs from AET. 4 imprecise (1) (1) HWBPs from AET which are shared for watch point. Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints will halt the processor some number of cycles after the selected instruction depending on device conditions. Submit Documentation Feedback Peripheral Information and Electrical Specifications 159 TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com Table 6-84. DSP Debug Features (continued) Category Analysis Hardware Feature Availability Watch point Up to 4 watch points, which are shared with HWBPs, and can also be used as 2 watch points with data (32 bits) Watch point with Data Up to 2, Which can also be used as 4 watch points. Counters/timers 1x64-bits (cycle only) + 2x32-bits (water mark counters) External Event Trigger In 1 External Event Trigger Out 1 6.23.1 JTAG Port Description The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS, TDI, and TDO). PRODUCT PREVIEW TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed while the TRST pin is pulled low. Table 6-85. JTAG Port Description PIN TYPE NAME DESCRIPTION TRST I Test Logic Reset When asserted (active low) causes all test and debug logic in the device to be reset along with the IEEE 1149.1 interface TCK I Test Clock This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic. TMS I Test Mode Select Directs the next state of the IEEE 1149.1 test access port state machine TDI I Test Data Input Scan data input to the device TDO O Test Data Output Scan data output of the device EMU0 I/O Emulation 0 Channel 0 trigger + HSRTDX EMU1 I/O Emulation 1 Channel 1 trigger + HSRTDX 6.23.2 Scan Chain Configuration Parameters Table 6-86 shows the TAP configuration details required to configure the router/emulator for this device. Table 6-86. JTAG Port Description Router Port ID Default TAP TAP Name Tap IR Length 17 No C674x 38 19 No ETB 4 The router is revision C and has a 6-bit IR length. 6.23.3 Initial Scan Chain Configuration The first level of debug interface that sees the scan controller is the TAP router module. The debugger can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of the TAP controllers without disrupting the IR state of the other TAPs. 160 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 7 Mechanical Packaging and Orderable Information This section describes the device orderable part numbers, packaging options, materials, thermal and mechanical parameters. 7.1 Device Support 7.1.1 Development Support TI offers an extensive line of development tools for the device platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE). Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software needed to support any application. Hardware Development Tools: Extended Development System (XDS™) Emulator For a complete listing of development-support tools for the device, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. 7.1.2 Device and Development-Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320C6745). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. Submit Documentation Feedback Mechanical Packaging and Orderable Information 161 PRODUCT PREVIEW The following products support development of the device applications: TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, "Blank" is the default). Figure 7-1 provides a legend for reading the complete device. TMS 320 C6742 PREFIX TMX = Experimental Device TMS = Qualified Device ( ) ZWT ( ) ( ) DEVICE SPEED RANGE 3 = 300 Mhz DEVICE FAMILY 320 = TMS320™ DSP Family PRODUCT PREVIEW TEMPERATURE RANGE (JUNCTION) Blank = 0°C to 90°C, Commercial Grade A = –40°C to 105°C, Industrial Grade DEVICE C6742 PACKAGE TYPE(A) ZCE = 361-Pin Plastic BGA, with Pb-free Soldered Balls [Green], 0.65 mm Ball Pitch ZWT = 361-Pin Plastic BGA, with PB-free Soldered Balls [Green], 0.8 mm Ball Pitch SILICON REVISION Blank = Revision 1.0 Figure 7-1. Device Nomenclature 162 Mechanical Packaging and Orderable Information Submit Documentation Feedback TMS320C6742 Fixed/Floating-Point DSP www.ti.com SPRS587 – JUNE 2009 7.2 Thermal Data for ZCE Package The following table(s) show the thermal resistance characteristics for the PBGA–ZCE mechanical package. Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZCE] 1 RΘJC Junction-to-case 7.6 N/A 2 RΘJB Junction-to-board 11.3 N /A 3 RΘJA Junction-to-free air 23.9 0.00 21.2 0.50 20.3 1.00 19.5 2.00 7 18.6 4.00 8 0.2 0.00 9 0.3 0.50 0.3 1.00 11 0.4 2.00 12 0.5 4.00 13 11.2 0.00 14 11.1 0.50 4 5 6 10 15 (1) (2) AIR FLOW (m/s) (2) RΘJMA PsiJT PsiJB Junction-to-moving air Junction-to-package top 11.1 1.00 16 Junction-to-board 11.0 2.00 17 10.9 4.00 These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. Power dissipation of 500 mW and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and 1.5oz (50um) inner copper thickness m/s = meters per second Submit Documentation Feedback Mechanical Packaging and Orderable Information 163 PRODUCT PREVIEW °C/W (1) NO. TMS320C6742 Fixed/Floating-Point DSP SPRS587 – JUNE 2009 www.ti.com 7.3 Thermal Data for ZWT Package The following table(s) show the thermal resistance characteristics for the PBGA–ZWT mechanical package. Table 7-2. Thermal Resistance Characteristics (PBGA Package) [ZWT] °C/W (1) NO. AIR FLOW (m/s) (2) 1 RΘJC Junction-to-case 7.3 N/A 2 RΘJB Junction-to-board 12.4 N /A 3 RΘJA Junction-to-free air 23.7 0.00 21.0 0.50 20.1 1.00 19.3 2.00 7 18.4 4.00 8 0.2 0.00 9 0.3 0.50 0.3 1.00 11 0.4 2.00 12 0.5 4.00 13 12.3 0.00 14 12.2 0.50 4 5 6 PRODUCT PREVIEW 10 15 RΘJMA PsiJT Junction-to-package top 12.1 1.00 16 12.0 2.00 17 11.9 4.00 (1) (2) 164 PsiJB Junction-to-moving air Junction-to-board These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. Power dissipation of 1W and ambient temp of 70C assumed. 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