TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Piccolo Microcontrollers Check for Samples: TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 1 TMS320F2806x ( Piccolo™) MCUs 1.1 Features • High-Efficiency 32-Bit CPU (TMS320C28x™) – 80 MHz (12.5-ns Cycle Time) – 16 x 16 and 32 x 32 MAC Operations – 16 x 16 Dual MAC – Harvard Bus Architecture – Atomic Operations – Fast Interrupt Response and Processing – Unified Memory Programming Model – Code-Efficient (in C/C++ and Assembly) • Floating-Point Unit – Native Single-Precision Floating-Point Operations • Programmable Control Law Accelerator (CLA) – 32-Bit Floating-Point Math Accelerator – Executes Code Independently of the Main CPU • Viterbi, Complex Math, CRC Unit (VCU) – Extends C28x™ Instruction Set to Support Complex Multiply, Viterbi Operations, and Cyclic Redundency Check (CRC) • Embedded Memory – Up to 256KB Flash – Up to 100KB RAM – 2KB OTP ROM • 6-Channel DMA • Low Device and System Cost – Single 3.3-V Supply – No Power Sequencing Requirement – Integrated Power-on Reset and Brown-out Reset – Low-Power Operating Modes – No Analog Support Pin • Clocking – Two Internal Zero-pin Oscillators – On-Chip Crystal Oscillator/External Clock Input – Dynamic PLL Ratio Changes Supported – Watchdog Timer Module – Missing Clock Detection Circuitry • Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts • Three 32-Bit CPU Timers • Advanced Control Peripherals • Up to 8 Enhanced Pulse Width Modulator (ePWM) Modules – 16 PWM Channels Total (8 HRPWM-Capable) – Independent 16-Bit Timer in Each Module • 3 Input Capture (eCAP) Modules • 4 High-Resolution Input Capture (HRCAP) Modules • 2 Quadrature Encoder (eQEP) Modules • 12-Bit ADC, Dual Sample-and-Hold – Up to 3 MSPS – Up to 16 Channels • On-Chip Temperature Sensor • 128-Bit Security Key/Lock – Protects Secure Memory Blocks – Prevents Firmware Reverse Engineering • Serial Port Peripherals – Up to Two Serial Communications Interface (SCI) [UART] Modules – Two Serial Peripheral Interface (SPI) Modules – One Inter-Integrated-Circuit (I2C) Bus – One Multi-Channel Buffered Serial Port (McBSP) Bus – One Enhanced Controller Area Network (eCAN) • Up to 54 Individually Programmable, Multiplexed GPIO Pins With Input Filtering • Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware • 2806x Packages – 80-Pin PFP and 100-Pin PZP PowerPAD™ Low-Profile Quad Flatpacks (LQFPs) – 80-Pin PN and 100-Pin PZ LQFPs 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Piccolo, PowerPAD, C28x, TMS320C2000, C2000, Code Composer Studio, XDS510, XDS560, TMS320C28x, TMS320C54x, TMS320C55x are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 2 3 ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Copyright © 2010–2011, Texas Instruments Incorporated ADVANCE INFORMATION 123 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 1.2 www.ti.com Description The F2806x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, as well as providing a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead/latency. ADVANCE INFORMATION 2 TMS320F2806x ( Piccolo™) MCUs Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 1.3 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Functional Block Diagram M0 SARAM (1Kx16) (0-wait, Non-Secure) L0 DPSARAM (2Kx16) (0-wait, Secure) CLA Data RAM2 M1 SARAM (1Kx16) (0-wait, Non-Secure) L1 DPSARAM (1Kx16) (0-wait, Secure) CLA Data RAM0 L5 DPSARAM (8Kx16) (0-wait, Non-Secure) DMA RAM0 L3 DPSARAM (4Kx16) (0-wait, Secure) CLA Program RAM L7 DPSARAM (8Kx16) (0-wait, Non-Secure) DMA RAM2 PUMP L4 SARAM (8Kx16) (0-wait, Secure) L8 DPSARAM (8Kx16) (0-wait, Non-Secure) DMA RAM3 FLASH 64K/128Kx16 8 equal sectors Secure Code Security Module (CSM) L2 DPSARAM (1Kx16) (0-wait, Secure) CLA Data RAM1 L6 DPSARAM (8Kx16) (0-wait, Non-Secure) DMA RAM1 DMA Bus OTP 1Kx16 Secure PSWD OTP/Flash Wrapper TRST C28x 32-bit CPU FPU VCU GPIO Mux COMP + DAC TCK, TDI, TMS TDO CLA + Message OSC1, OSC2, Ext, PLLs, RAMs LPM, WD, CPU Timers 0/1/2. PIE DMA 6-ch ADC 0-wait Result Regs ADVANCE INFORMATION COMP1A COMP1B COMP2A COMP2B COMP3A COMP3B Boot-ROM (32Kx16) (0-wait, Non-Secure) XCLKIN GPIO Mux COMP3OUT CLA Bus COMP2OUT 32-bit Peripheral Bus GPIO Mux AIO Mux COMP1OUT DMA Bus Memory Bus Memory Bus DMA Bus LPM Wakeup 3 Ext. Interrupts X1 X2 XRS CLA Bus DMA Bus A7:0 Memory Bus ADC B7:0 CANTXx HRCAP- eCAN-A 1/2/3/4 (32-mbox) CANRXx MFSRA MDRA MCLKRA MFSXA MDXA MCLKXA ESYNCI ESYNCO EPWMxB TZx eCAP- eQEP1/2/3 1/2 32-bit Peripheral Bus HRCAPx McBSP-A HRPWM (8ch) (CLA accessible) EQEPxA EQEPxB EQEPxI EQEPxS ePWM1 to ePWM8 EPWMxA SCLx SDAx SPISIMOx SPISOMIx SPICLKx SPISTEx SCITXDx SCIRXDx SCI-A/B SPI-A/B I2C-A (4L FIFO) (4L FIFO) (4L FIFO) 32-bit Peripheral Bus ECAPx 32-bit Peripheral Bus (CLA accessible) 16-bit Peripheral Bus 32-bit Peripheral Bus GPIO Mux A. Not all peripheral pins are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram TMS320F2806x ( Piccolo™) MCUs Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 3 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 1.4 www.ti.com System Device Diagram C28x Core (80-MHz) PWM1 (DMA-accessible) PWM-1A PWM-1B FPU PWM2 (DMA-accessible) PWM-2A PWM-2B Flash Memory PWM3 (DMA-accessible) PWM-3A PWM-3B RAM PWM4 (DMA-accessible) PWM-4A PWM-4B PWM5 (DMA-accessible) PWM-5A PWM-5B PWM6 (DMA-accessible) PWM-6A PWM-6B PWM7 (DMA-accessible) PWM-7A PWM-7B PWM8 (DMA-accessible) PWM-8A PWM-8B ADC (DMAaccessible) VREFLO VREFHI VCU VREF ADVANCE INFORMATION A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 RAM (Dual-Access) 12-bit 3-MSPS Dual-S/H SOCbased CLA Core 80-MHz Floating-Point (Accelerator) (DMA-accessible) Temp Sensor 6 TZ1 TZ2 TZ3 CMP1-out CMP2-out CMP3-out Trip Zone CMP1-Out 10-bit DAC CMP2-Out eCAP x 3 10-bit DAC CMP3-Out 10-bit DAC Analog Comparators HRCAP x 4 Timers 32-bit Vreg Int-Osc-2 X1 X2 On-chip Osc POR/BOR WD Timer-1 UART x 2 Timer-2 SPI x 2 PLL System GPIO Control eCAP 8 eQEP 4 HRCAP COMMS Timer-0 CLKSEL Int-Osc-1 eQEP x 2 3 I2C CAN McBSP (DMA-accessible) 4 8 2 2 6 Figure 1-2. Peripheral Blocks 4 TMS320F2806x ( Piccolo™) MCUs Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 1 2 3 4 .................. 1 1.1 Features .............................................. 1 1.2 Description ........................................... 2 1.3 Functional Block Diagram ............................ 3 1.4 System Device Diagram ............................. 4 Revision History ......................................... 6 Device Overview ........................................ 7 3.1 Device Characteristics ............................... 7 3.2 Memory Maps ...................................... 10 3.3 Pin Assignments .................................... 20 3.4 Signal Descriptions ................................. 22 3.5 Brief Descriptions ................................... 31 3.6 Register Map ....................................... 40 3.7 Device Emulation Registers ........................ 42 3.8 VREG/BOR/POR ................................... 43 3.9 System Control ..................................... 45 3.10 Low-power Modes Block ........................... 53 Device and Documentation Support ............... 54 4.1 Getting Started ..................................... 54 4.2 Development Support .............................. 54 TMS320F2806x ( Piccolo™) MCUs 4.3 6 Documentation Support Test Load Circuit 60 6.3 Device Clock Table 61 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 .......... ........................................ Detailed Descriptions ............................... Serial Peripheral Interface (SPI) Module ........... Control Law Accelerator (CLA) Overview 75 Analog Block 78 Serial Communications Interface (SCI) Module 6.15 Enhanced Controller Area Network (eCAN) Module 6.16 6.17 Inter-Integrated Circuit (I2C) ...................... 119 Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1/2/3/4/5/6/7/8) ............................ 122 6.18 High-Resolution PWM (HRPWM) 129 6.19 Enhanced Capture Module (eCAP1) 130 6.20 6.21 Enhanced Quadrature Encoder Modules (eQEP1/2) ..................................................... 6.23 6.24 ................. .............. High-Resolution Capture (HRCAP) Module ....... ..................................................... JTAG Port ......................................... General-Purpose Input/Output (GPIO) MUX ...... Flash Timing ....................................... 105 115 132 133 136 137 149 59 Mechanical Packaging and Orderable Information ............................................ 151 60 7.1 60 7.2 ...................................... Packaging Information ............................ Thermal Data Contents Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 102 Multichannel Buffered Serial Port (McBSP) Module 6.22 7 92 93 6.14 57 58 64 Interrupts ............................................ 70 ..................................................... 58 63 67 Emulator Connection Without Signal Buffering for the MCU ............................................ 69 ..................................................... 56 58 ................................... ................................. Clock Requirements and Characteristics ........... Power Sequencing ................................. Current Consumption ............................... 6.2 6.4 Device and Development Support Tool Nomenclature ....................................... 54 ............................ 4.5 Community Resources ............................. Device Operating Conditions ....................... 5.1 Absolute Maximum Ratings ........................ 5.2 Recommended Operating Conditions .............. 5.3 Electrical Characteristics ........................... Peripheral and Electrical Specifications .......... 6.1 Parameter Information .............................. 4.4 5 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 151 152 5 ADVANCE INFORMATION www.ti.com TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 2 Revision History This data sheet revision history highlights the technical changes made to the SPRS698 device-specific data sheet to make it an SPRS698A revision. Scope: Added 80-pin PN package and 100-pin PZ package. Added "T" temperature range (–40°C to 105°C). Added new sections. Information/data on the TMS320F2806x devices is now Advance Information. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS ADVANCE INFORMATION Global • • • Added 80-pin PN package Added 100-pin PZ package Added "T" temperature range (–40°C to 105°C) Section 1 TMS320F2806x (Piccolo™) MCUs • • Added Section 1.2, Description Figure 1-1, Functional Block Diagram: – Removed "32-bit Peripheral Bus" Section 3 Device Overview • Table 3-1, Hardware Features: – 6-Channel DMA: Added "0" to TYPE column – High-resolution capture modules (HRCAP): Added "0" to TYPE column – Multi-Channel Buffered Serial Port (McBSP): Added "1" to TYPE column – Updated "Temperature options" Added Section 3.2, Memory Maps Figure 3-8, 80-Pin PN/PFP LQFP (Top View): – Removed SCI-B signals and eQEP2 signals Table 3-6, Terminal Functions: – Added "SCI-B is only available in the PZ and PZP packages" note to DESCRIPTION of PN/PFP pins# 39, 59, 76, 70, 41, 52, 78, 1 – Added "eQEP2 is only available in the PZ and PZP packages" note to DESCRIPTION of PN/PFP pins# 77, 31, 62, 61, 33, 32 Added Section 3.5, Brief Descriptions Added Section 3.6, Register Map Added Section 3.7, Device Emulation Registers Added Section 3.8, VREG/BOR/POR Added Section 3.9, System Control Added Section 3.10, Low-power Modes Block • • • • • • • • • Section 4 • Device and • Documentation Support • Added Section 4.1, Getting Started Section 4.3, Device and Development Support Tool Nomenclature: – Updated PACKAGE TYPE in Figure 4-1, Device Nomenclature Added Section 4.4, Documentation Support Added Section 6, Peripheral and Electrical Specifications Section 7 Mechanical Packaging and Orderable Information 6 Revision History • Added Section 7.1, Thermal Data Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3 Device Overview 3.1 Device Characteristics ADVANCE INFORMATION Table 3-1 lists the features of the TMS320F2806x devices. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 7 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 3-1. Hardware Features FEATURE 28069 (80 MHz) TYPE (1) 100-Pin PZ/PZP LQFP Package Type Instruction cycle – 28068 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28067 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28066 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28065 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28064 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28063 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28062 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 80-Pin PN/PFP LQFP 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns 12.5 ns Floating-Point Unit (FPU) Yes Yes Yes Yes Yes Yes Yes Yes Viterbi, Complex Math, CRC Unit (VCU) Yes Yes No No Yes Yes No No ADVANCE INFORMATION Control Law Accelerator (CLA) 0 Yes No No No Yes No No No 6-Channel DMA 0 Yes Yes Yes Yes Yes Yes Yes Yes On-chip Flash (16-bit word) – 128K 128K 128K 128K 64K 64K 64K 64K On-chip SARAM (16-bit word) – 50K 50K 50K 34K 50K 50K 34K 26K Code security for on-chip flash/SARAM/OTP blocks – Yes Yes Yes Yes Yes Yes Yes Yes Boot ROM (32K x 16) – Yes Yes Yes Yes Yes Yes Yes Yes One-time programmable (OTP) ROM (16-bit word) – ePWM outputs 1 19 15 19 15 19 15 19 15 19 15 19 15 19 15 19 High-resolution ePWM Channels 1 8 6 8 6 8 6 8 6 8 6 8 6 8 6 8 eCAP inputs 0 High-resolution capture modules (HRCAP) 0 eQEP modules 0 Watchdog timer – 1K 3 Channels 3 2 Dual Sample-and-Hold 3 4 1 2 Yes 1K 3 4 1 2 Yes 1K 3 4 1 2 Yes 1K 3 4 1 2 Yes 1K 2 Yes 6 3 4 1 15 4 1 2 Yes 1 Yes 3 3 3 3 3 3 3 3 325 ns 325 ns 325 ns 325 ns 325 ns 325 ns 325 ns 325 ns 16 Temperature Sensor 1K 3 4 1 Yes Conversion Time 1K 3 4 2 MSPS 12-Bit ADC 1K 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 32-Bit CPU timers – 3 3 3 3 3 3 3 3 Comparators with Integrated DACs 0 3 3 3 3 3 3 3 3 Inter-integrated circuit (I2C) 0 1 1 1 1 1 1 1 1 Multi-Channel Buffered Serial Port (McBSP) 1 1 1 1 1 1 1 1 1 Enhanced Controller Area Network (eCAN) 0 1 1 1 1 1 1 1 1 Serial Peripheral Interface (SPI) 1 2 2 2 2 2 2 2 Serial Communications Interface (SCI) 0 (1) 8 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides. Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 3-1. Hardware Features (continued) TYPE 100-Pin PZ/PZP LQFP Package Type 28068 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28067 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28066 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28065 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28064 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 28063 (80 MHz) 80-Pin PN/PFP LQFP 100-Pin PZ/PZP LQFP 80-Pin PN/PFP LQFP 2-pin Oscillator 1 1 1 1 1 1 1 0-pin Oscillator 2 2 2 2 2 2 2 I/O pins (shared) GPIO – AIO – 54 40 54 6 40 54 6 40 54 6 40 54 6 40 54 6 40 54 6 28062 (80 MHz) 100-Pin PZ/PZP LQFP 80-Pin PN/PFP LQFP 1 2 40 54 6 40 6 External interrupts – 3 3 3 3 3 3 3 3 Supply voltage (nominal) – 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Temperature options Product status (2) (1) (2) T: –40°C to 105°C – PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN S: –40°C to 125°C – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP Q: –40°C to 125°C (1) – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP – TMX TMX TMX TMX TMX TMX TMX PFP TMX "Q" refers to Q100 qualification for automotive applications. See Section 4.3, Device and Development Support Tool Nomenclature, for descriptions of device stages. The "TMX" product status denotes an experimental device that is not necessarily representative of the final device's electrical specifications. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Device Overview 9 ADVANCE INFORMATION FEATURE 28069 (80 MHz) (1) TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.2 www.ti.com Memory Maps In Figure 3-1 through Figure 3-7, the following apply: • Memory blocks are not to scale. • Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space. • Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order. • Certain memory ranges are EALLOW protected against spurious writes after configuration. • Locations 0x3D 7C80–0x3D 7CC0 contain the internal oscillator and ADC calibration routines. These locations are not programmable by the user. ADVANCE INFORMATION 10 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Data Space Prog Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Reserved Peripheral Frame 0 0x00 1400 CLA Registers 0x00 1480 CLA-to-CPU Message RAM 0x00 1500 CPU-to-CLA Message RAM 0x00 1580 Reserved 0x00 2000 0x00 5000 Reserved Peripheral Frame 3 (4K x 16, Protected) DMA-Accessible Peripheral Frame 1 (4K x 16, Protected) ADVANCE INFORMATION 0x00 6000 Reserved 0x00 7000 Peripheral Frame 2 (4K x 16, Protected) 0x00 8000 0x00 8800 0x00 8C00 0x00 9000 0x00 A000 0x00 C000 0x00 E000 0x01 0000 0x01 2000 L0 DPSARAM (2K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM2) L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 0) L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 1) L3 DPSARAM (4K x 16) (0-Wait, Secure Zone + ECSL, CLA Program RAM) L4 SARAM (8K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) L5 DPSARAM (8K x 16) (0-Wait, DMA RAM 0) L6 DPSARAM (8K x 16) (0-Wait, DMA RAM 1) L7 DPSARAM (8K x 16) (0-Wait, DMA RAM 2) L8 DPSARAM (8K x 16) (0-Wait, DMA RAM 3) 0x01 4000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7BFA 0x3D 7C80 0x3D 7CC0 0x3D 7CD0 0x3D 7E80 Reserved Calibration Data Get_mode function Reserved PARTID Calibration Data 0x3D 7EB0 0x3D 8000 Reserved FLASH (128K x 16, 8 Sectors, Secure Zone + ECSL) 0x3F 7FF8 128-Bit Password 0x3F 8000 Boot ROM (32K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 3-1. 28069 Memory Map Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 11 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Data Space Prog Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Peripheral Frame 0 0x00 1400 0x00 5000 Reserved Reserved Peripheral Frame 3 (4K x 16, Protected) DMA-Accessible 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) Reserved 0x00 7000 Peripheral Frame 2 (4K x 16, Protected) ADVANCE INFORMATION 0x00 8000 0x00 8800 0x00 8C00 0x00 9000 0x00 A000 0x00 C000 0x00 E000 0x01 0000 0x01 2000 L0 DPSARAM (2K x 16) (0-Wait, Secure Zone + ECSL) L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL) L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL) L3 DPSARAM (4K x 16) (0-Wait, Secure Zone + ECSL) L4 SARAM (8K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) L5 DPSARAM (8K x 16) (0-Wait, DMA RAM 0) L6 DPSARAM (8K x 16) (0-Wait, DMA RAM 1) L7 DPSARAM (8K x 16) (0-Wait, DMA RAM 2) L8 DPSARAM (8K x 16) (0-Wait, DMA RAM 3) 0x01 4000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7BFA 0x3D 7C80 0x3D 7CC0 0x3D 7CD0 0x3D 7E80 Reserved Calibration Data Get_mode function Reserved PARTID Calibration Data 0x3D 7EB0 0x3D 8000 Reserved FLASH (128K x 16, 8 Sectors, Secure Zone + ECSL) 0x3F 7FF8 128-Bit Password 0x3F 8000 Boot ROM (32K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 3-2. 28068/28067 Memory Map 12 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Data Space Prog Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Peripheral Frame 0 0x00 1400 0x00 5000 Reserved Reserved Peripheral Frame 3 (4K x 16, Protected) DMA-Accessible 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) Reserved 0x00 7000 0x00 8000 0x00 8800 0x00 8C00 0x00 9000 0x00 A000 0x00 C000 0x00 E000 L0 DPSARAM (2K x 16) (0-Wait, Secure Zone + ECSL) L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL) L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL) L3 DPSARAM (4K x 16) (0-Wait, Secure Zone + ECSL) L4 SARAM (8K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) L5 DPSARAM (8K x 16) (0-Wait, DMA RAM 0) L6 DPSARAM (8K x 16) (0-Wait, DMA RAM 1) 0x01 0000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7BFA 0x3D 7C80 0x3D 7CC0 0x3D 7CD0 0x3D 7E80 ADVANCE INFORMATION Peripheral Frame 2 (4K x 16, Protected) Reserved Calibration Data Get_mode function Reserved PARTID Calibration Data 0x3D 7EB0 0x3D 8000 Reserved FLASH (128K x 16, 8 Sectors, Secure Zone + ECSL) 0x3F 7FF8 128-Bit Password 0x3F 8000 Boot ROM (32K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 3-3. 28066 Memory Map Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 13 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Data Space Prog Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Reserved Peripheral Frame 0 0x00 1400 CLA Registers 0x00 1480 CLA-to-CPU Message RAM 0x00 1500 CPU-to-CLA Message RAM 0x00 1580 Reserved 0x00 2000 0x00 5000 Reserved Peripheral Frame 3 (4K x 16, Protected) DMA-Accessible 0x00 6000 ADVANCE INFORMATION Peripheral Frame 1 (4K x 16, Protected) Reserved 0x00 7000 Peripheral Frame 2 (4K x 16, Protected) 0x00 8000 0x00 8800 0x00 8C00 0x00 9000 0x00 A000 0x00 C000 0x00 E000 0x01 0000 0x01 2000 L0 DPSARAM (2K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM2) L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 0) L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 1) L3 DPSARAM (4K x 16) (0-Wait, Secure Zone + ECSL, CLA Program RAM) L4 SARAM (8K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) L5 DPSARAM (8K x 16) (0-Wait, DMA RAM 0) L6 DPSARAM (8K x 16) (0-Wait, DMA RAM 1) L7 DPSARAM (8K x 16) (0-Wait, DMA RAM 2) L8 DPSARAM (8K x 16) (0-Wait, DMA RAM 3) 0x01 4000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7BFA 0x3D 7C80 0x3D 7CC0 0x3D 7CD0 0x3D 7E80 Reserved Calibration Data Get_mode function Reserved PARTID Calibration Data 0x3D 7EB0 0x3E 8000 Reserved FLASH (64K x 16, 8 Sectors, Secure Zone + ECSL) 0x3F 7FF8 128-Bit Password 0x3F 8000 Boot ROM (32K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 3-4. 28065 Memory Map 14 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Data Space Prog Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Peripheral Frame 0 0x00 1400 0x00 5000 Reserved Reserved Peripheral Frame 3 (4K x 16, Protected) DMA-Accessible 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) Reserved 0x00 7000 0x00 8000 0x00 8800 0x00 8C00 0x00 9000 0x00 A000 0x00 C000 0x00 E000 0x01 0000 0x01 2000 L0 DPSARAM (2K x 16) (0-Wait, Secure Zone + ECSL) L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL) L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL) L3 DPSARAM (4K x 16) (0-Wait, Secure Zone + ECSL) L4 SARAM (8K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) L5 DPSARAM (8K x 16) (0-Wait, DMA RAM 0) L6 DPSARAM (8K x 16) (0-Wait, DMA RAM 1) L7 DPSARAM (8K x 16) (0-Wait, DMA RAM 2) L8 DPSARAM (8K x 16) (0-Wait, DMA RAM 3) 0x01 4000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7BFA 0x3D 7C80 0x3D 7CC0 0x3D 7CD0 0x3D 7E80 ADVANCE INFORMATION Peripheral Frame 2 (4K x 16, Protected) Reserved Calibration Data Get_mode function Reserved PARTID Calibration Data 0x3D 7EB0 0x3E 8000 Reserved FLASH (64K x 16, 8 Sectors, Secure Zone + ECSL) 0x3F 7FF8 128-Bit Password 0x3F 8000 Boot ROM (32K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 3-5. 28064 Memory Map Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 15 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Data Space Prog Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Peripheral Frame 0 0x00 1400 0x00 5000 Reserved Reserved Peripheral Frame 3 (4K x 16, Protected) DMA-Accessible 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) Reserved 0x00 7000 Peripheral Frame 2 (4K x 16, Protected) ADVANCE INFORMATION 0x00 8000 0x00 8800 0x00 8C00 0x00 9000 0x00 A000 0x00 C000 0x00 E000 L0 DPSARAM (2K x 16) (0-Wait, Secure Zone + ECSL) L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL) L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL) L3 DPSARAM (4K x 16) (0-Wait, Secure Zone + ECSL) L4 SARAM (8K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) L5 DPSARAM (8K x 16) (0-Wait, DMA RAM 0) L6 DPSARAM (8K x 16) (0-Wait, DMA RAM 1) 0x01 0000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7BFA 0x3D 7C80 0x3D 7CC0 0x3D 7CD0 0x3D 7E80 Reserved Calibration Data Get_mode function Reserved PARTID Calibration Data 0x3D 7EB0 0x3E 8000 Reserved FLASH (64K x 16, 8 Sectors, Secure Zone + ECSL) 0x3F 7FF8 128-Bit Password 0x3F 8000 Boot ROM (32K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 3-6. 28063 Memory Map 16 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Data Space Prog Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Peripheral Frame 0 0x00 1400 0x00 5000 Reserved Reserved Peripheral Frame 3 (4K x 16, Protected) DMA-Accessible 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) Reserved 0x00 7000 0x00 8000 0x00 8800 0x00 8C00 0x00 9000 0x00 A000 0x00 C000 L0 DPSARAM (2K x 16) (0-Wait, Secure Zone + ECSL) L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL) L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL) L3 DPSARAM (4K x 16) (0-Wait, Secure Zone + ECSL) L4 SARAM (8K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) L5 DPSARAM (8K x 16) (0-Wait, DMA RAM 0) 0x00 E000 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7BFA 0x3D 7C80 0x3D 7CC0 0x3D 7CD0 0x3D 7E80 ADVANCE INFORMATION Peripheral Frame 2 (4K x 16, Protected) Reserved Calibration Data Get_mode function Reserved PARTID Calibration Data 0x3D 7EB0 0x3E 8000 Reserved FLASH (64K x 16, 8 Sectors, Secure Zone + ECSL) 0x3F 7FF8 128-Bit Password 0x3F 8000 Boot ROM (32K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 3-7. 28062 Memory Map Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 17 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 3-2. Addresses of Flash Sectors in F28069/28068/28067/28066 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3D 8000 – 0x3D BFFF Sector H (16K x 16) 0x3D C000 – 0x3D FFFF Sector G (16K x 16) 0x3E 0000 – 0x3E 3FFF Sector F (16K x 16) 0x3E 4000 – 0x3E 7FFF Sector E (16K x 16) 0x3E 8000 – 0x3E BFFF Sector D (16K x 16) 0x3E C000 – 0x3E FFFF Sector C (16K x 16) 0x3F 0000 – 0x3F 3FFF Sector B (16K x 16) 0x3F 4000 – 0x3F 7F7F Sector A (16K x 16) 0x3F 7F80 – 0x3F 7FF5 Program to 0x0000 when using the Code Security Module 0x3F 7FF6 – 0x3F 7FF7 Boot-to-Flash Entry Point (program branch instruction here) 0x3F 7FF8 – 0x3F 7FFF Security Password (128-Bit) (Do not program to all zeros) ADVANCE INFORMATION Table 3-3. Addresses of Flash Sectors in F28065/28064/28063/28062 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3E 8000 – 0x3E 9FFF Sector H (8K x 16) 0x3E A000 – 0x3E BFFF Sector G (8K x 16) 0x3E C000 – 0x3E DFFF Sector F (8K x 16) 0x3E E000 – 0x3E FFFF Sector E (8K x 16) 0x3F 0000 – 0x3F 1FFF Sector D (8K x 16) 0x3F 2000 – 0x3F 3FFF Sector C (8K x 16) 0x3F 4000 – 0x3F 5FFF Sector B (8K x 16) 0x3F 6000 – 0x3F 7F7F Sector A (8K x 16) 0x3F 7F80 – 0x3F 7FF5 Program to 0x0000 when using the Code Security Module 0x3F 7FF6 – 0x3F 7FF7 Boot-to-Flash Entry Point (program branch instruction here) 0x3F 7FF8 – 0x3F 7FFF Security Password (128-Bit) (Do not program to all zeros) NOTE • When the code-security passwords are programmed, all addresses between 0x3F 7F80 and 0x3F 7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000. • If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may be used for code or data. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data and should not contain program code. Table 3-4 shows how to handle these memory locations. 18 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 3-4. Impact of Using the Code Security Module FLASH ADDRESS CODE SECURITY ENABLED 0x3F 7F80 – 0x3F 7FEF Fill with 0x0000 0x3F 7FF0 – 0x3F 7FF5 CODE SECURITY DISABLED Application code and data Reserved for data only Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The CPU supports a block protection mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it protects the selected zones. The wait-states for the various spaces in the memory map area are listed in Table 3-5. AREA WAIT-STATES (CPU) M0 and M1 SARAMs 0-wait Peripheral Frame 0 0-wait Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready. 2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur a 1-cycle stall (1-cycle delay). 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral. Peripheral Frame 2 COMMENTS Fixed 2-wait (reads) Peripheral Frame 3 0-wait (writes) Assumes no conflict between CPU and CLA/DMA cycles. The wait states can be extended by peripherals generated ready. 2-wait (reads) L0 SARAM 0-wait data and program Assumes no CPU conflicts L1 SARAM 0-wait data and program Assumes no CPU conflicts L2 SARAM 0-wait data and program Assumes no CPU conflicts L3 SARAM 0-wait data and program Assumes no CPU conflicts OTP FLASH Programmable Programmed via the Flash registers. 1-wait minimum 1-wait is minimum number of wait states allowed. Programmable Programmed via the Flash registers. 0-wait Paged min 1-wait Random min Random ≥ Paged FLASH Password 16-wait fixed Boot-ROM 0-wait Wait states of password locations are fixed. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 19 ADVANCE INFORMATION Table 3-5. Wait-States TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.3 www.ti.com Pin Assignments GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO GPIO7/EPWM4B/SCIRXDA/ECAP2 GPIO16/SPISIMOA/TZ2 GPIO8/EPWM5A/ADCSOCAO GPIO17/SPISOMIA/TZ3 GPIO18/SPICLKA/XCLKOUT 46 45 44 43 42 41 X1 X2 VDDIO 49 47 VSS 51 50 48 GPIO39 54 GPIO19/XCLKIN/SPISTEA/ECAP1 VDD 55 52 GPIO34/COMP2OUT/COMP3OUT GPIO38/XCLKIN/TCK 56 53 GPIO35/TDI GPIO37/TDO 57 GPIO11/EPWM6B/ECAP1 GPIO36/TMS 58 GPIO10/EPWM6A/ADCSOCBO 60 GPIO27/HRCAP2/SPISTEB 61 40 GPIO28/SCIRXDA/SDAA/TZ2 GPIO26/ECAP3/SPICLKB VDDIO 62 39 63 38 GPIO9/EPWM5B/ECAP3 VSS VSS 64 37 VDD3VFL VDD 65 36 TEST2 GPIO3/EPWM2B/SPISOMIA/COMP2OUT 66 35 GPIO12/TZ1/SCITXDA/SPISIMOB GPIO2/EPWM2A 67 34 GPIO1/EPWM1B/COMP1OUT 68 33 GPIO29/SCITXDA/SCLA/TZ3 GPIO30/CANRXA/EPWM7A A. 3 VSS 20 2 VDDA ADCINB0 VREFLO, VSSA 19 21 17 80 18 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO ADCINA1 ADCINA0, VREFHI 22 ADCINA2/COMP1A/AIO2 79 15 ADCINB1 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO 16 23 ADCINA5 78 ADCINA4/COMP2A/AIO4 ADCINB2/COMP1B/AIO10 GPIO22/EQEP1S/MCLKXA 14 24 ADCINA6/COMP3A/AIO6 ADCINB4/COMP2B/AIO12 77 13 25 VSS 76 12 ADCINB5 GPIO14/TZ3/SPICLKB GPIO24/ECAP1/SPISIMOB VDD 26 10 75 11 ADCINB6/COMP3B/AIO14 GPIO13/TZ2/SPISOMIB TRST VDDIO 27 8 74 9 VSS VDDIO XRS VDD 28 GPIO5/EPWM3B/SPISIMOA/ECAP1 29 73 6 72 VSS 7 GPIO25/ECAP2/SPISOMIB VDDIO GPIO4/EPWM3A 30 GPIO21/EQEP1B/MDRA/COMP2OUT 71 4 VREGENZ VDD 5 GPIO31/CANTXA/EPWM8A 31 VDDIO 32 70 GPIO20/EQEP1A/MDXA/COMP1OUT 69 1 GPIO0/EPWM1A GPIO15/ECAP2/SPISTEB GPIO23/EQEP1I/MFSXA VDD ADVANCE INFORMATION 59 Figure 3-8 shows the 80-pin PN/PFP Low-Profile Quad Flatpack (LQFP) pin assignments. Figure 3-9 shows the 100-pin PZ/PZP Low-Profile Quad Flatpack (LQFP) pin assignments. Pin 19: VREFHI and ADCINA0 share the same pin on the 80-pin PN/PFP device and their use is mutually exclusive to one another. Pin 21: VREFLO is always connected to VSSA on the 80-pin PN/PFP device. Figure 3-8. 80-Pin PN/PFP LQFP (Top View) 20 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 GPIO17/SPISOMIA/TZ3 GPIO18/SPICLKA/SCITXDB/XCLKOUT 52 51 GPIO41/EPWM7B/SCIRXDB 76 50 GPIO28/SCIRXDA/SDAA/TZ2 GPIO27/HRCAP2/EQEP2S/SPISTEB 77 49 GPIO9/EPWM5B/SCITXDB/ECAP3 GPIO26/ECAP3/EQEP2I/SPICLKB 78 48 GPIO51/EQEP1B/MDRA/TZ2 VDDIO 79 47 VSS VSS 80 46 VDD3VFL VDD 81 45 TEST2 GPIO40/EPWM7A/SCITXDB 82 44 GPIO12/TZ1/SCITXDA/SPISIMOB GPIO3/EPWM2B/SPISOMIA/COMP2OUT 83 43 GPIO29/SCITXDA/SCLA/TZ3 GPIO2/EPWM2A 84 42 GPIO50/EQEP1A/MDXA/TZ1 GPIO56/SPICLKA/EQEP2I/HRCAP3 85 41 GPIO30/CANRXA/EQEP2I/EPWM7A GPIO1/EPWM1B/COMP1OUT 86 40 GPIO31/CANTXA/EQEP2S/EPWM8A GPIO0/EPWM1A 87 39 GPIO25/ECAP2/EQEP2B/SPISOMIB GPIO15/ECAP2/SCIRXDB/SPISTEB 88 38 VDDIO GPIO57/SPISTEA/EQEP2S/HRCAP4 89 37 VDD VREGENZ 90 36 VSS VDD 91 35 ADCINB7 VSS 92 34 ADCINB6/COMP3B/AIO14 VDDIO 93 33 ADCINB5 GPIO58/MCLKRA/SCITXDB/EPWM7A 94 32 ADCINB4/COMP2B/AIO12 GPIO13/TZ2/SPISOMIB 95 31 ADCINB3 GPIO14/TZ3/SCITXDB/SPICLKB 96 30 ADCINB2/COMP1B/AIO10 ADCINB1 21 22 23 24 25 ADCINA2/COMP1A/AIO2 ADCINA1 ADCINA0 VREFHI VDDA 20 17 ADCINA6/COMP3A/AIO6 ADCINA3 16 ADCINA7 18 15 VSS 19 14 VDD ADCINA5 13 VDDIO ADCINA4/COMP2A/AIO4 11 12 XRS TRST GPIO4/EPWM3A 10 8 9 GPIO43/EPWM8B/TZ2/COMP2OUT GPIO5/EPWM3B/SPISIMOA/ECAP1 6 7 GPIO20/EQEP1A/MDXA/COMP1OUT VSSA GPIO21/EQEP1B/MDRA/COMP2OUT 26 5 100 VDDIO GPIO33/SCLA/EPWMSYNCO/ADCSOCBO 3 VREFLO 4 27 VSS 99 VDD ADCINB0 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO 1 28 2 29 98 GPIO23/EQEP1I/MFSXA/SCIRXDB 97 GPIO42/EPWM8A/TZ1/COMP1OUT GPIO24/ECAP1/EQEP2A/SPISIMOB GPIO22/EQEP1S/MCLKXA/SCITXDB Figure 3-9. 100-Pin PZ/PZP LQFP (Top View) Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 21 ADVANCE INFORMATION GPIO8/EPWM5A/ADCSOCAO GPIO52/EQEP1S/MCLKXA/TZ3 53 GPIO16/SPISIMOA/TZ2 55 54 GPIO7/EPWM4B/SCIRXDA/ECAP2 GPIO44/MFSRA/SCIRXDB/EPWM7B 56 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO 58 57 X1 X2 VDDIO 61 59 VSS 62 60 GPIO19/XCLKIN/SPISTEA/SCIRXDB/ECAP1 VDD 63 GPIO53/EQEP1I/MFSXA 65 64 GPIO38/XCLKIN/TCK GPIO39 66 GPIO34/COMP2OUT/COMP3OUT 68 67 GPIO37/TDO GPIO54/SPISIMOA/EQEP2A/HRCAP1 70 69 GPIO36/TMS GPIO35/TDI 71 GPIO11/EPWM6B/SCIRXDB/ECAP1 73 72 GPIO55/SPISOMIA/EQEP2B/HRCAP2 GPIO10/EPWM6A/ADCSOCBO 74 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 75 www.ti.com TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.4 www.ti.com Signal Descriptions Table 3-6 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 3-1 for details. Inputs are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do not have an internal pullup. NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins could glitch during power up. If this is unacceptable in an application, 1.8 V could be supplied externally. There is no power-sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the 1.9-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V. Table 3-6. Terminal Functions (1) ADVANCE INFORMATION TERMINAL NAME PZ/PZP PIN # PN/PFP PIN # I/O/Z DESCRIPTION JTAG TRST 12 10 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active-high test pin and must be maintained low at all times during normal device operation. An external pull-down resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (↓) TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup. (↑) TMS See GPIO36 I See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (↑) TDI See GPIO35 I See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑) TDO See GPIO37 O/Z See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (8-mA drive) FLASH VDD3VFL 46 37 TEST2 45 36 (1) 22 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. I/O Test Pin. Reserved for TI. Must be left unconnected. I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 3-6. Terminal Functions (continued) TERMINAL NAME PZ/PZP PIN # PN/PFP PIN # I/O/Z DESCRIPTION O/Z See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. I See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled via bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. NOTE: Designs that use the GPIO38/XCLKIN/TCK pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device. XCLKOUT XCLKIN See GPIO18 See GPIO19 and GPIO38 X1 60 48 I On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND. X2 59 47 O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected. RESET Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in power-on-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a reset pulse. During a power-on or brown-out condition, this pin is driven low by the device. See Section 5.3, Electrical Characteristics, for thresholds of the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin to assert a device reset. In this case, it is recommended that this pin be driven by an open-drain device. An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. XRS 11 9 I/O ADCINA7 16 – I ADC Group A, Channel 7 input ADCINA6 17 14 I ADC Group A, Channel 6 input I Comparator Input 3A ADC, COMPARATOR, ANALOG I/O COMP3A AIO6 I/O Digital AIO 6 ADCINA5 18 15 I ADC Group A, Channel 5 input ADCINA4 19 16 I ADC Group A, Channel 4 input I Comparator Input 2A COMP2A AIO4 I/O Digital AIO 4 ADCINA3 20 – I ADC Group A, Channel 3 input ADCINA2 21 17 I ADC Group A, Channel 2 input I Comparator Input 1A COMP1A AIO2 I/O Digital AIO 2 ADCINA1 22 18 I ADC Group A, Channel 1 input ADCINA0 23 19 I ADC Group A, Channel 0 input. NOTE: VREFHI and ADCINA0 share the same pin on the 80-pin PN/PFP device and their use is mutually exclusive to one another. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 23 ADVANCE INFORMATION CLOCK TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 3-6. Terminal Functions (continued) TERMINAL I/O/Z DESCRIPTION PZ/PZP PIN # PN/PFP PIN # VREFHI 24 19 ADCINB7 35 – I ADC Group B, Channel 7 input ADCINB6 34 27 I ADC Group B, Channel 6 input I Comparator Input 3B NAME COMP3B AIO14 ADC External Reference – only used when in ADC external reference mode. See Section 6.10.1, Analog-to-Digital Converter (ADC). NOTE: VREFHI and ADCINA0 share the same pin on the 80-pin PN/PFP device and their use is mutually exclusive to one another. I/O Digital AIO 14 ADCINB5 33 26 I ADC Group B, Channel 5 input ADCINB4 32 25 I ADC Group B, Channel 4 input I Comparator Input 2B COMP2B AIO12 I/O Digital AIO12 ADVANCE INFORMATION ADCINB3 31 – I ADC Group B, Channel 3 input ADCINB2 30 24 I ADC Group B, Channel 2 input I Comparator Input 1B COMP1B AIO10 I/O Digital AIO 10 ADCINB1 29 23 I ADC Group B, Channel 1 input ADCINB0 28 22 I ADC Group B, Channel 0 input VREFLO 27 21 NOTE: VREFLO is always connected to VSSA on the 80-pin PN/PFP device. VDDA 25 20 Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin. VSSA 26 21 Analog Ground Pin. NOTE: VREFLO is always connected to VSSA on the 80-pin PN/PFP device. CPU AND I/O POWER VDD 3 2 VDD 14 12 VDD 37 29 VDD 63 51 VDD 81 65 VDD 91 72 VDDIO 5 4 VDDIO 13 11 VDDIO 38 30 VDDIO 61 49 VDDIO 79 63 VDDIO 93 74 VSS 4 3 VSS 15 13 VSS 36 28 VSS 47 38 VSS 62 50 VSS 80 64 VSS 92 73 24 Device Overview CPU and Logic Digital Power Pins – no supply source needed when using internal VREG. Tie with 1.2 µF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used, but could impact supply-rail ramp-up time. Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled. Digital Ground Pins Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 3-6. Terminal Functions (continued) TERMINAL NAME PZ/PZP PIN # PN/PFP PIN # I/O/Z 90 71 I DESCRIPTION VOLTAGE REGULATOR CONTROL SIGNAL Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG. GPIO AND PERIPHERAL SIGNALS GPIO0 87 69 EPWM1A GPIO1 I/O/Z O 86 68 I/O/Z General-purpose input/output 0 Enhanced PWM1 Output A and HRPWM channel General-purpose input/output 1 EPWM1B O Enhanced PWM1 Output B COMP1OUT O Direct output of Comparator 1 GPIO2 84 67 I/O/Z 83 66 I/O/Z EPWM2A GPIO3 O General-purpose input/output 2 Enhanced PWM2 Output A and HRPWM channel General-purpose input/output 3 EPWM2B O Enhanced PWM2 Output B SPISOMIA I/O SPI-A slave out, master in COMP2OUT O Direct output of Comparator 2 GPIO4 9 7 I/O/Z 10 8 I/O/Z EPWM3A GPIO5 O General-purpose input/output 4 Enhanced PWM3 output A and HRPWM channel General-purpose input/output 5 EPWM3B O Enhanced PWM3 output B SPISIMOA I/O SPI-A slave in, master out I/O Enhanced Capture input/output 1 ECAP1 GPIO6 58 46 EPWM4A I/O/Z (1) General-purpose input/output 6 O Enhanced PWM4 output A and HRPWM channel EPWMSYNCI I External ePWM sync pulse input EPWMSYNCO O External ePWM sync pulse output GPIO7 57 45 I/O/Z General-purpose input/output 7 EPWM4B O Enhanced PWM4 output B SCIRXDA I SCI-A receive data ECAP2 GPIO8 I/O 54 43 I/O/Z Enhanced Capture input/output 2 General-purpose input/output 8 EPWM5A O Enhanced PWM5 output A and HRPWM channel Reserved – Reserved ADCSOCAO O ADC start-of-conversion A (1) ADVANCE INFORMATION VREGENZ The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18). Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 25 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 3-6. Terminal Functions (continued) TERMINAL NAME GPIO9 PZ/PZP PIN # PN/PFP PIN # I/O/Z 49 39 I/O/Z DESCRIPTION General-purpose input/output 9 EPWM5B O Enhanced PWM5 output B SCITXDB O SCI-B transmit data. NOTE: SCI-B is only available in the PZ and PZP packages. I/O Enhanced Capture input/output 3 I/O/Z General-purpose input/output 10 ECAP3 GPIO10 74 60 EPWM6A O Enhanced PWM6 output A and HRPWM channel Reserved – Reserved ADCSOCBO O ADC start-of-conversion B GPIO11 73 59 I/O/Z General-purpose input/output 11 EPWM6B O Enhanced PWM6 output B SCIRXDB I SCI-B receive data. NOTE: SCI-B is only available in the PZ and PZP packages. ADVANCE INFORMATION ECAP1 GPIO12 44 35 TZ1 I/O Enhanced Capture input/output 1 I/O/Z General-purpose input/output 12 I Trip Zone input 1 SCITXDA O SCI-A transmit data SPISIMOB I/O SPI-B slave in, master out GPIO13 95 75 I/O/Z General-purpose input/output 13 TZ2 I Trip Zone input 2 Reserved – Reserved SPISOMIB I/O GPIO14 96 76 I/O/Z SPI-B slave out, master in General-purpose input/output 14 TZ3 I Trip zone input 3 SCITXDB O SCI-B transmit data. NOTE: SCI-B is only available in the PZ and PZP packages. I/O SPI-B clock input/output SPICLKB GPIO15 88 70 ECAP2 SCIRXDB General-purpose input/output 15 I/O Enhanced Capture input/output 2 I SPISTEB GPIO16 I/O/Z I/O 55 44 I/O/Z SCI-B receive data. NOTE: SCI-B is only available in the PZ and PZP packages. SPI-B slave transmit enable input/output General-purpose input/output 16 SPISIMOA I/O Reserved – Reserved TZ2 I Trip Zone input 2 GPIO17 52 42 I/O/Z SPI-A slave in, master out General-purpose input/output 17 SPISOMIA I/O Reserved – Reserved TZ3 I Trip zone input 3 26 Device Overview SPI-A slave out, master in Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 3-6. Terminal Functions (continued) TERMINAL NAME GPIO18 PZ/PZP PIN # PN/PFP PIN # I/O/Z 51 41 I/O/Z DESCRIPTION General-purpose input/output 18 SPICLKA I/O SPI-A clock input/output SCITXDB O SCI-B transmit data. NOTE: SCI-B is only available in the PZ and PZP packages. XCLKOUT O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. I/O/Z General-purpose input/output 19 64 52 XCLKIN I SPISTEA I/O SCIRXDB I ECAP1 GPIO20 6 5 External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if it is being used for the other peripheral functions. SPI-A slave transmit enable input/output SCI-B receive data. NOTE: SCI-B is only available in the PZ and PZP packages. I/O Enhanced Capture input/output 1 I/O/Z General-purpose input/output 20 EQEP1A I Enhanced QEP1 input A MDXA O McBSP transmit serial data COMP1OUT O Direct output of Comparator 1 GPIO21 7 6 EQEP1B I/O/Z General-purpose input/output 21 I Enhanced QEP1 input B MDRA I McBSP receive serial data COMP2OUT O Direct output of Comparator 2 GPIO22 98 78 I/O/Z General-purpose input/output 22 EQEP1S I/O Enhanced QEP1 strobe MCLKXA I/O McBSP transmit clock SCITXDB O SCI-B transmit data. NOTE: SCI-B is only available in the PZ and PZP packages. GPIO23 2 1 I/O/Z General-purpose input/output 23 EQEP1I I/O Enhanced QEP1 index MFSXA I/O McBSP transmit frame synch SCIRXDB GPIO24 I 97 77 ECAP1 EQEP2A SPISIMOB GPIO25 ECAP2 EQEP2B SPISOMIB General-purpose input/output 24 I/O Enhanced Capture input/output 1 I/O 39 31 SCI-B receive data. NOTE: SCI-B is only available in the PZ and PZP packages. I/O/Z I Enhanced QEP2 input A. NOTE: eQEP2 is only available in the PZ and PZP packages. SPI-B slave in, master out I/O/Z General-purpose input/output 25 I/O Enhanced Capture input/output 2 I I/O Enhanced QEP2 input B. NOTE: eQEP2 is only available in the PZ and PZP packages. SPI-B slave out, master in Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated ADVANCE INFORMATION GPIO19 27 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 3-6. Terminal Functions (continued) TERMINAL NAME GPIO26 PZ/PZP PIN # PN/PFP PIN # I/O/Z 78 62 DESCRIPTION I/O/Z General-purpose input/output 26 ECAP3 I/O Enhanced Capture input/output 3 EQEP2I I/O Enhanced QEP2 index. NOTE: eQEP2 is only available in the PZ and PZP packages. I/O SPI-B clock input/output SPICLKB GPIO27 77 61 I/O/Z General-purpose input/output 27 HRCAP2 I High-Resolution Input Capture 2 EQEP2S I/O Enhanced QEP2 strobe. NOTE: eQEP2 is only available in the PZ and PZP packages. I/O SPI-B slave transmit enable input/output SPISTEB GPIO28 50 40 SCIRXDA I/O/Z I SDAA I/OD ADVANCE INFORMATION TZ2 I GPIO29 43 34 SCITXDA I/O/Z O SCLA I/OD TZ3 I GPIO30 41 33 I/O/Z General-purpose input/output 28 SCI-A receive data I2C data open-drain bidirectional port Trip zone input 2 General-purpose input/output 29 SCI-A transmit data I2C clock open-drain bidirectional port Trip zone input 3 General-purpose input/output 30 CANRXA I EQEP2I I/O Enhanced QEP2 index. NOTE: eQEP2 is only available in the PZ and PZP packages. EPWM7A O Enhanced PWM7 Output A and HRPWM channel GPIO31 40 32 I/O/Z CAN receive General-purpose input/output 31 CANTXA O CAN transmit EQEP2S I/O Enhanced QEP2 strobe. NOTE: eQEP2 is only available in the PZ and PZP packages. O Enhanced PWM8 Output A and HRPWM channel EPWM8A GPIO32 99 79 SDAA I/O/Z General-purpose input/output 32 I/OD I2C data open-drain bidirectional port EPWMSYNCI I Enhanced PWM external sync pulse input ADCSOCAO O ADC start-of-conversion A GPIO33 100 80 SCLA I/O/Z General-purpose input/output 33 I/OD I2C clock open-drain bidirectional port EPWMSYNCO O Enhanced PWM external synch pulse output ADCSOCBO O ADC start-of-conversion B GPIO34 68 55 I/O/Z General-purpose input/output 34 COMP2OUT O Direct output of Comparator 2 COMP3OUT O Direct output of Comparator 3 GPIO35 71 57 TDI I GPIO36 72 58 TMS I/O/Z I GPIO37 70 TDO 28 I/O/Z Device Overview 56 General-purpose input/output 35 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. General-purpose input/output 36 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. I/O/Z General-purpose input/output 37 O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive). Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 3-6. Terminal Functions (continued) TERMINAL GPIO38 PZ/PZP PIN # PN/PFP PIN # I/O/Z 67 54 I/O/Z XCLKIN TCK DESCRIPTION General-purpose input/output 38 I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if it is being used for the other functions. I JTAG test clock with internal pullup GPIO39 66 53 I/O/Z General-purpose input/output 39 GPIO40 82 – I/O/Z General-purpose input/output 40 EPWM7A O Enhanced PWM7 output A and HRPWM channel SCITXDB O SCI-B transmit data GPIO41 76 – I/O/Z General-purpose input/output 41 EPWM7B O Enhanced PWM7 output B SCIRXDB I SCI-B receive data GPIO42 1 – I/O/Z General-purpose input/output 42 EPWM8A O Enhanced PWM8 output A and HRPWM channel TZ1 I Trip zone input 1 COMP1OUT O Direct output of Comparator 1 GPIO43 8 – I/O/Z General-purpose input/output 43 EPWM8B O Enhanced PWM8 output B TZ2 I Trip zone input 2 O Direct output of Comparator 2 COMP2OUT GPIO44 56 – MFSRA I/O/Z I/O General-purpose input/output 44 McBSP receive frame synch SCIRXDB I SCI-B receive data EPWM7B O Enhanced PWM7 output B GPIO50 42 – I/O/Z General-purpose input/output 50 EQEP1A I Enhanced QEP1 input A MDXA O McBSP transmit serial data TZ1 I Trip zone input 1 GPIO51 48 – I/O/Z General-purpose input/output 51 EQEP1B I Enhanced QEP1 input B MDRA I McBSP receive serial data TZ2 I Trip zone input 2 GPIO52 53 – I/O/Z General-purpose input/output 52 EQEP1S I/O Enhanced QEP1 strobe MCLKXA I/O McBSP transmit clock TZ3 GPIO53 I 65 – I/O/Z Trip zone input 3 General-purpose input/output 53 EQEP1I I/O Enhanced QEP1 index MFSXA I/O McBSP transmit frame synch GPIO54 SPISIMOA 69 – I/O/Z I/O General-purpose input/output 54 SPI-A slave in, master out EQEP2A I Enhanced QEP2 input A HRCAP1 I High-Resolution Input Capture 1 Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated ADVANCE INFORMATION NAME 29 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 3-6. Terminal Functions (continued) TERMINAL NAME GPIO55 PZ/PZP PIN # PN/PFP PIN # I/O/Z 75 – I/O/Z SPISOMIA I/O DESCRIPTION General-purpose input/output 55 SPI-A slave out, master in EQEP2B I Enhanced QEP2 input B HRCAP2 I High-Resolution Input Capture 2 I/O/Z General-purpose input/output 56 GPIO56 85 – SPICLKA I/O SPI-A clock input/output EQEP2I I/O Enhanced QEP2 index HRCAP3 I High-Resolution Input Capture 3 I/O/Z General-purpose input/output 57 GPIO57 89 – ADVANCE INFORMATION SPISTEA I/O SPI-A slave transmit enable input/output EQEP2S I/O Enhanced QEP2 strobe HRCAP4 I High-Resolution Input Capture 4 I/O/Z General-purpose input/output 58 GPIO58 94 – MCLKRA I/O McBSP receive clock SCITXDB O SCI-B transmit data EPWM7A O Enhanced PWM7 output A and HRPWM channel 30 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 3.5 3.5.1 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Brief Descriptions CPU 3.5.2 Control Law Accelerator (CLA) The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be specified. Each task is started by software or a peripheral such as the ADC, an ePWM, or CPU Timer 0. The CLA executes one task at a time to completion. When a task completes the main CPU is notified by an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task. The CLA can directly access the ADC Result registers and the ePWM+HRPWM registers. Dedicated message RAMs provide a method to pass additional data between the main CPU and the CLA. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 31 ADVANCE INFORMATION The 2806x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x-based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very efficient C/C++ engine, enabling users to develop not only their system control software in a high-level language, but also enabling development of math algorithms using C/C++. The device is as efficient at MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance. TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.5.3 www.ti.com Viterbi, Complex Math, CRC Unit (VCU) The C28x VCU enhances the processing power of C2000™ devices by adding additional assembly instructions to target complex math, Viterbi decode, and CRC calculations. The VCU instructions accelerate many applications, including the following: • Orthogonal frequency-division multiplex (OFDM) used in the PRIME and G3 standards for power line communications • Short-range radar complex math calculations • Power calculations • Memory and data communication packet checks (CRC) ADVANCE INFORMATION The VCU features include: • Instructions to support Cyclic Redundancy Checks (CRCs), which is a polynomial code checksum. – CRC8 – CRC16 – CRC32 • Instructions to support a flexible software implementation of a Viterbi decoder – Branch metric calculations for a code rate of 1/2 or 1/3 – Add-Compare Select or Viterbi Butterfly in 5 cycles per butterfly – Traceback in 3 cycles per stage – Easily supports a constraint length of K = 7 used in PRIME and G3 standards • Complex math arithmetic unit – Single-cycle Add or Subtract – 2-cycle multiply – 2-cycle multiply and accumulate (MAC) – Single-cycle repeat MAC • Independent register space 3.5.4 Memory Bus (Harvard Bus Architecture) As with many MCU-type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows: Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.) Program Writes (Simultaneous data and program writes cannot occur on the memory bus.) Data Reads Lowest: 32 Device Overview Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.) Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.) Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 3.5.5 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral frame 1). Real-Time JTAG and Analysis The devices implement the standard IEEE 1149.1 JTAG (1) interface for in-circuit based debug. Additionally, the devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and register locations while the processor is running and executing code and servicing interrupts. The user can also single step through non-time-critical code while enabling time-critical interrupts to be serviced without interference. The device implements the real-time mode in hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable break events when a match occurs. These devices do not support boundary scan; however, IDCODE and BYPASS features are available if the following considerations are taken into account. The IDCODE does not come by default. The user needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For BYPASS instruction, the first shifted DR value would be 1. 3.5.7 Flash The F28069/68/67/66 devices contain 128K x 16 of embedded flash memory, segregated into eight 16K x 16 sectors. The F28065/64/63/62 devices contain 64K x 16 of embedded flash memory, segregated into eight 8K x 16 sectors. All devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data variables and should not contain program code. NOTE The Flash and OTP wait-states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait-states. Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18). (1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 33 ADVANCE INFORMATION 3.5.6 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.5.8 www.ti.com M0, M1 SARAMs All devices contain these two blocks of single-access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages. 3.5.9 L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs The device contains up to 48K x 16 of single-access RAM. To ascertain the exact size for a given device, see the device-specific memory map figures in Section 3.2. This block is mapped to both program and data space. L0 is 2K in size. L1 and L2 are each 1K in size. L3 is 4K in size. L4, L5, L6, L7, and L8 are each 8K in size. L0, L1, and L2 are shared with the CLA, which can utilize these blocks for its data space. L3 is shared with the CLA, which can utilize this block for its program space. L5, L6, L7, and L8 are shared with the DMA, which can utilize these blocks for its data space. DPSARAM refers to the dual-port configuration of these blocks. 3.5.10 Boot ROM ADVANCE INFORMATION The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related algorithms. Table 3-7. Boot Mode Selection MODE GPIO37/TDO GPIO34/COMP2OUT/ COMP3OUT TRST 3 1 1 0 GetMode 2 1 0 0 Wait (see Section 3.5.11 for description) 1 0 1 0 SCI 0 0 0 0 Parallel IO EMU x x 1 Emulation Boot MODE 3.5.10.1 Emulation Boot When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM locations in the PIE vector table to determine the boot mode. If the content of either location is invalid, then the Wait boot option is used. All boot mode options can be accessed in emulation boot. 3.5.10.2 GetMode The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP. 34 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.5.10.3 Peripheral Pins Used by the Bootloader Table 3-8 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if these conflict with any of the peripherals you would like to use in your application. Table 3-8. Peripheral Bootload Pins PERIPHERAL LOADER PINS SCIRXDA (GPIO28) SCITXDA (GPIO29) Parallel Boot Data (GPIO31,30,5:0) 28x Control (AIO6) Host Control (AIO12) SPI SPISIMOA (GPIO16) SPISOMIA (GPIO17) SPICLKA (GPIO18) SPISTEA (GPIO19) I2C SDAA (GPIO32) SCLA (GPIO33) CAN CANRXA (GPIO30) CANTXA (GPIO31) 3.5.11 Security The devices support high levels of security to protect the user firmware from being reverse-engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value that matches the value stored in the password locations within the Flash. In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, or L0 memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow emulation of secure code, while maintaining the CSM protection against secure memory reads, the user must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in the lower 64 bits of the password locations within the flash. Note that dummy reads of all 128 bits of the password in the flash must still be performed. If the lower 64 bits of the password locations are all ones (unprogrammed), then the KEY value does not need to match. When initially debugging a device with the password locations in flash programmed (i.e., secured), the CPU will start running and may execute an instruction that performs an access to a protected ECSL area. If this happens, the ECSL will trip and cause the emulator connection to be cut. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 35 ADVANCE INFORMATION BOOTLOADER SCI TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping security. Piccolo devices do not support a hardware wait-in-reset mode. NOTE • When the code-security passwords are programmed, all addresses between 0x3F 7F80 and 0x3F 7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000. • If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may be used for code or data. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data and should not contain program code. The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing so would permanently lock the device. Disclaimer ADVANCE INFORMATION Code Security Module Disclaimer THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. 3.5.12 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F2806x, 72 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block. 36 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.5.13 External Interrupts (XINT1–XINT3) The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled. These interrupts also contain a 16-bit free-running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time-stamp the interrupt. There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from GPIO0–GPIO31 pins. 3.5.14 Internal Zero Pin Oscillators, Oscillator, and PLL The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 16 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to Section 5, Electrical Specifications, for timing details. The PLL block can be set in bypass mode. A second PLL (PLL2) feeds the HRCAP module. Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either generate an interrupt or a device reset. 3.5.16 Peripheral Clocking The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to the CPU clock. 3.5.17 Low-power Modes The devices are full static CMOS devices. Three low-power modes are provided: IDLE: Places CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode. STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event HALT: This mode basically shuts down the device and places it in the lowest possible power-consumption mode. If the internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default. To keep these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip crystal oscillator is used as the clock source, it is shut down in this mode. A reset or an external signal (through a GPIO pin) or the CPU-watchdog can wake the device from this mode. The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put the device into HALT or STANDBY. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 37 ADVANCE INFORMATION 3.5.15 Watchdog TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 3.5.18 Peripheral Frames 0, 1, 2, 3 (PFn) The device segregates peripherals into four sections. The mapping of peripherals is as follows: PF0: PF1: ADVANCE INFORMATION PF2: PF3: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash: Flash Waitstate Registers Timers: CPU-Timers 0, 1, 2 Registers CSM: Code Security Module KEY Registers ADC: ADC Result Registers CLA: Control Law Accelrator Registers and Message RAMs GPIO: GPIO MUX Configuration and Control Registers eCAN: Enhanced Control Area Network Configuration and Control Registers ePWM: Enhanced Pulse Width Modulator Module and Registers eCAP: Enhanced Capture Module and Registers eQEP: Enhanced Quadrature Encoder Pulse Module and Registers Comparators: Comparator Modules SYS: System Control Registers SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Port Interface (SPI) Control and RX/TX Registers ADC: ADC Status, Control, and Configuration Registers I2C: Inter-Integrated Circuit Module and Registers XINT: External Interrupt Registers McBSP: Multichannel Buffered Serial Port Registers 3.5.19 General-Purpose Input/Output (GPIO) Multiplexer Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes. 3.5.20 32-Bit CPU-Timers (0, 1, 2) CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. It is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 2 can be clocked by any one of the following: • SYSCLKOUT (default) • Internal zero-pin oscillator 1 (INTOSC1) • Internal zero-pin oscillator 2 (INTSOC2) • External clock source 38 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.5.21 Control Peripherals ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the HRPWM high resolution duty and period features. The type 1 module found on 2806x devices also supports increased dead-band resolution, enhanced SOC and interrupt generation, and advanced triggering including trip functions based on comparator outputs. eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal. eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous edge transition in QEP signals. ADC: The ADC block is a 12-bit converter. It has up to 13 single-ended channels pinned out, depending on the device. It contains two sample-and-hold units for simultaneous sampling. Comparator: Each comparator block consists of one analog comparator along with an internal 10-bit reference for supplying one input of the comparator. 3.5.22 Serial Port Peripherals The devices support the following serial communication peripherals: SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. The SPI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. SCI: The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. The SCI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. I2C: The inter-integrated circuit (I2C) module provides an interface between a MCU and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the MCU through the I2C module. The I2C contains a 4-level receive-and-transmit FIFO for reducing interrupt servicing overhead. eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping of messages, and is CAN 2.0B-compliant. McBSP: The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality codecs for modem applications or high-quality stereo audio DAC devices. The McBSP receive and transmit registers are supported by the DMA to significantly reduce the overhead for servicing this peripheral. Each McBSP module can be configured as an SPI as required. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 39 ADVANCE INFORMATION The devices support the following peripherals that are used for embedded control and communication: TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.6 www.ti.com Register Map The devices contain four peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 3-9. Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table 3-10. Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 3-11. Peripheral Frame 3: McBSP registers are mapped to this. See Table 3-12. Table 3-9. Peripheral Frame 0 Registers (1) ADDRESS RANGE SIZE (×16) EALLOW PROTECTED (2) Device Emulation Registers 0x00 0880 – 0x00 0984 261 Yes System Power Control Registers 0x00 0985 – 0x00 0987 3 Yes FLASH Registers (3) 0x00 0A80 – 0x00 0ADF 96 Yes Code Security Module Registers 0x00 0AE0 – 0x00 0AEF 16 Yes ADC registers (0 wait read only) 0x00 0B00 – 0x00 0B0F 16 No CPU–TIMER0/1/2 Registers 0x00 0C00 – 0x00 0C3F 64 No PIE Registers 0x00 0CE0 – 0x00 0CFF 32 No PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 No DMA Registers 0x00 1000 – 0x00 11FF 512 Yes CLA Registers 0x00 1400 – 0x00 147F 128 Yes CLA to CPU Message RAM (CPU writes ignored) 0x00 1480 – 0x00 14FF 128 NA CPU to CLA Message RAM (CLA writes ignored) 0x00 1500 – 0x00 157F 128 NA NAME ADVANCE INFORMATION (1) (2) (3) 40 Registers in Frame 0 support 16-bit and 32-bit accesses. If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents. The Flash Registers are also protected by the Code Security Module (CSM). Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 3-10. Peripheral Frame 1 Registers NAME SIZE (×16) 0x00 6000 – 0x00 61FF 512 (1) Comparator 1 registers 0x00 6400 – 0x00 641F 32 (1) Comparator 2 registers 0x00 6420 – 0x00 643F 32 (1) Comparator 3 registers 0x00 6440 – 0x00 645F 32 (1) ePWM1 + HRPWM1 registers 0x00 6800 – 0x00 683F 64 (1) ePWM2 + HRPWM2 registers 0x00 6840 – 0x00 687F 64 (1) ePWM3 + HRPWM3 registers 0x00 6880 – 0x00 68BF 64 (1) ePWM4 + HRPWM4 registers 0x00 68C0 – 0x00 68FF 64 (1) ePWM5 + HRPWM5 registers 0x00 6900 – 0x00 693F 64 (1) ePWM6 + HRPWM6 registers 0x00 6940 – 0x00 697F 64 (1) ePWM7 + HRPWM7 registers 0x00 6980 – 0x00 69BF 64 (1) ePWM8 + HRPWM8 registers 0x00 69C0 – 0x00 69FF 64 (1) eCAP1 registers 0x00 6A00 – 0x00 6A1F 32 No eCAP2 registers 0x00 6A20 – 0x00 6A3F 32 No eCAP3 registers 0x00 6A40 – 0x00 6A57 32 No HRCAP1 registers 0x00 6AC0 – 0x00 6ADF 32 (1) HRCAP2 registers 0x00 6AE0 – 0x00 6AFF 32 (1) eQEP1 registers 0x00 6B00 – 0x00 6B3F 64 (1) eQEP2 registers 0x00 6B40 – 0x00 6B7F 64 (1) HRCAP3 registers 0x00 6C80 – 0x00 6C9F 32 (1) HRCAP4 registers 0x00 6CA0 – 0x00 6CBF 32 (1) GPIO registers 0x00 6F80 – 0x00 6FFF 128 (1) (1) EALLOW PROTECTED ADVANCE INFORMATION ADDRESS RANGE eCAN-A registers Some registers are EALLOW protected. See the module reference guide for more information. Table 3-11. Peripheral Frame 2 Registers ADDRESS RANGE SIZE (×16) EALLOW PROTECTED System Control Registers NAME 0x00 7010 – 0x00 702F 32 Yes SPI-A Registers 0x00 7040 – 0x00 704F 16 No SCI-A Registers 0x00 7050 – 0x00 705F 16 No NMI Watchdog Interrupt Registers 0x00 7060 – 0x00 706F 16 Yes External Interrupt Registers 0x00 7070 – 0x00 707F 16 Yes ADC Registers 0x00 7100 – 0x00 717F 128 SPI-B Registers 0x00 7740 – 0x00 774F 16 No SCI-B Registers 0x00 7750 – 0x00 775F 16 No I2C-A Registers 0x00 7900 – 0x00 793F 64 (1) (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. Table 3-12. Peripheral Frame 3 Registers NAME McBSP-A Registers ADDRESS RANGE SIZE (×16) EALLOW PROTECTED 0x00 5000 – 0x00 503F 64 No Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 41 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.7 www.ti.com Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-13. Table 3-13. Device Emulation Registers NAME ADDRESS RANGE SIZE (x16) 0x0880– 0x0881 2 Device Configuration Register 0x3D 7E80 1 Part ID Register DEVICECNF PARTID ADVANCE INFORMATION CLASSID 0x0882 REVID 42 0x0883 Device Overview 1 1 EALLOW PROTECTED DESCRIPTION Class ID Register Revision ID Register Yes TMS320F28069PZP/PZ 0x009E TMS320F28069PFP/PN 0x009C TMS320F28068PZP/PZ 0x008E TMS320F28068PFP/PN 0x008C TMS320F28067PZP/PZ 0x008A TMS320F28067PFP/PN 0x0088 TMS320F28066PZP/PZ 0x0086 TMS320F28066PFP/PN 0x0084 TMS320F28065PZP/PZ 0x007E TMS320F28065PFP/PN 0x007C TMS320F28064PZP/PZ 0x006E TMS320F28064PFP/PN 0x006C TMS320F28063PZP/PZ 0x006A TMS320F28063PFP/PN 0x0068 TMS320F28062PZP/PZ 0x0066 TMS320F28062PFP/PN 0x0064 TMS320F28069 0x009F TMS320F28068 0x008F TMS320F28067 0x008F TMS320F28066 0x008F TMS320F28065 0x007F TMS320F28064 0x006F TMS320F28063 0x006F TMS320F28062 0x006F 0x0000 - Silicon Rev. 0 - TMX No No No Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 3.8 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 VREG/BOR/POR Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and space of a second external regulator on an application board. Additionally, internal power-on reset (POR) and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode. 3.8.1 On-chip Voltage Regulator (VREG) A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the primary concern of the application. Using the On-chip VREG To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum) capacitance for proper regulation of the VREG. These capacitors should be located as close as possible to the VDD pins. 3.8.1.2 Disabling the On-chip VREG To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied high. 3.8.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is to create a clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled (VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their respective trip point. Additionally, when the internal voltage regulator is enabled, an over-voltage protection circuit will tie XRS low if the VDD rail rises above its trip point. See Section 5 for the various trip points as well as the delay time for the device to release the XRS pin after the under/over-voltage condition is removed. Figure 3-10 shows the VREG, POR, and BOR. To disable both the VDD and VDDIO BOR functions, a bit is provided in the BORCFG register. See the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18) for details. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 43 ADVANCE INFORMATION 3.8.1.1 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com In I/O Pin Out (Force Hi-Z When High) DIR (0 = Input, 1 = Output) SYSRS Internal Weak PU SYSCLKOUT Deglitch Filter XRS Sync RS MCLKRS ADVANCE INFORMATION PLL + Clocking Logic XRS Pin C28 Core JTAG TCK Detect Logic VREGHALT (A) WDRST (B) PBRS A. B. POR/BOR Generating Module On-Chip Voltage Regulator (VREG) VREGENZ WDRST is the reset signal from the CPU-watchdog. PBRS is the reset signal from the POR/BOR module. Figure 3-10. VREG + POR + BOR + Reset Signal Connectivity 44 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 3.9 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 System Control This section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes. Table 3-14. PLL, Clocking, Watchdog, and Low-Power Mode Registers DESCRIPTION (1) ADDRESS SIZE (x16) BORCFG 0x00 0985 1 BOR Configuration Register XCLK 0x00 7010 1 XCLKOUT Control PLLSTS 0x00 7011 1 PLL Status Register CLKCTL 0x00 7012 1 Clock Control Register PLLLOCKPRD 0x00 7013 1 PLL Lock Period INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register PCLKCR2 0x00 7019 1 Peripheral Clock Control Register 2 LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1 LPMCR0 0x00 701E 1 Low Power Mode Control Register 0 PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control and Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register WDKEY 0x00 7025 1 Watchdog Reset Key Register WDCR 0x00 7029 1 Watchdog Control Register PLL2CTL 0x00 7030 1 PLL2 Configuration Register PLL2MULT 0x00 7032 1 PLL2 Multiplier Register PLL2STS 0x00 7034 1 PLL2 Lock Status Register SYSCLK2CNTR 0x00 7036 1 SYSCLK2 Clock Counter Register EPWMCFG 0x00 703A 1 ePWM DMA/CLA Configuration Register (1) ADVANCE INFORMATION NAME All registers in this table are EALLOW protected. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 45 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Figure 3-11 shows the various clock domains that are discussed. Figure 3-12 shows the various clock sources (both internal and external) that can provide a clock for device operation. SYSCLKOUT LOSPCP (System Ctrl Regs) PCLKCR0/1/2/3 (System Ctrl Regs) Clock Enables I/O C28x Core CLKIN LSPCLK SPI-A, SPI-B, SCI-A, SCI-B Peripheral Registers PF2 LOSPCP (System Ctrl Regs) Clock Enables LSPCLK I/O McBSP ADVANCE INFORMATION Clock Enables I/O GPIO Mux eCAN-A Peripheral Registers PF3 /2 Peripheral Registers PF1 Peripheral Registers PF1 Peripheral Registers PF1 Peripheral Registers PF2 Peripheral Registers PF1 Clock Enables I/O eCAP1, eCAP2, eCAP3 eQEP1, eQEP2 Clock Enables I/O ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7, ePWM8 Clock Enables I/O I2C-A Clock Enables I/O HRCAP1, HRCAP2, HRCAP3, HRCAP4 Clock Enables 16 Ch ADC Registers PF2 PF0 Analog GPIO Mux Clock Enables 6 A. 12-Bit ADC COMP1/2/3 COMP Registers PF1 CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT). Figure 3-11. Clock and Reset Domains 46 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 CLKCTL[WDCLKSRCSEL] Internal OSC 1 (10 MHz) (A) INTOSC1TRIM Reg 0 OSC1CLK OSCCLKSRC1 WDCLK CPU-Watchdog (OSC1CLK on XRS reset) OSCE 1 CLKCTL[INTOSC1OFF] 1 = Turn OSC Off CLKCTL[OSCCLKSRCSEL] CLKCTL[INTOSC1HALT] WAKEOSC 1 = Ignore HALT 0 INTOSC2TRIM Reg OSCCLK PLL Missing-Clock-Detect Circuit (OSC1CLK on XRS reset) (B) ADVANCE INFORMATION Internal OSC2CLK OSC 2 (10 MHz) (A) 1 OSCE CLKCTL[TRM2CLKPRESCALE] CLKCTL[TMR2CLKSRCSEL] 1 = Turn OSC Off 10 CLKCTL[INTOSC2OFF] 11 1 = Ignore HALT Prescale /1, /2, /4, /8, /16 01, 10, 11 CPUTMR2CLK 01 1 00 CLKCTL[INTOSC2HALT] SYSCLKOUT OSCCLKSRC2 0 0 = GPIO38 1 = GPIO19 XCLK[XCLKINSEL] SYNC Edge Detect CLKCTL[OSCCLKSRC2SEL] CLKCTL[XCLKINOFF] 0 XCLKIN GPIO19 or GPIO38 1 0 XCLKIN X1 EXTCLK (Crystal) OSC XTAL WAKEOSC (Oscillators enabled when this signal is high) X2 CLKCTL[XTALOSCOFF] A. B. 0 = OSC on (default on reset) 1 = Turn OSC off Register loaded from TI OTP-based calibration function. See Section 3.9.4 for details on missing clock detection. Figure 3-12. Clock Tree Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 47 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.9.1 www.ti.com Internal Zero Pin Oscillators The F2806x devices contain two independent internal zero pin oscillators. By default both oscillators are turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused oscillators may be powered down by the user. The center frequency of these oscillators is determined by their respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See Section 6, Peripheral and Electrical Specifications, for more information on these oscillators. 3.9.2 Crystal Oscillator Option The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in Table 3-15. Furthermore, ESR range = 30 to 150 Ω. Table 3-15. Typical Specifications for External Quartz Crystal (1) ADVANCE INFORMATION (1) FREQUENCY (MHz) Rd (Ω) CL1 (pF) CL2 (pF) 5 2200 18 18 10 470 15 15 15 0 15 15 20 0 12 12 Cshunt should be less than or equal to 5 pF. XCLKIN/GPIO19/38 Turn off XCLKIN path in CLKCTL register X1 X2 Rd CL1 Crystal CL2 Figure 3-13. Using the On-chip Crystal Oscillator NOTE 1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and crystal. The value is usually approximately twice the value of the crystal's load capacitance. 2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers. 3. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range. XCLKIN/GPIO19/38 External Clock Signal (Toggling 0−VDDIO) X1 X2 NC Figure 3-14. Using a 3.3-V External Oscillator 48 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 3.9.3 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 PLL-Based Clock Module The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) is at least 50 MHz. Table 3-16. PLL Settings (1) (2) (3) SYSCLKOUT (CLKIN) (2) PLLSTS[DIVSEL] = 0 or 1 (3) PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3 00000 (PLL bypass) OSCCLK/4 (Default) (1) OSCCLK/2 OSCCLK 00001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 (OSCCLK * 1)/1 00010 (OSCCLK * 2)/4 (OSCCLK * 2)/2 (OSCCLK * 2)/1 00011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 (OSCCLK * 3)/1 00100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 (OSCCLK * 4)/1 00101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 (OSCCLK * 5)/1 00110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 (OSCCLK * 6)/1 00111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 (OSCCLK * 7)/1 01000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 (OSCCLK * 8)/1 01001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 (OSCCLK * 9)/1 01010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 (OSCCLK * 10)/1 01011 (OSCCLK * 11)/4 (OSCCLK * 11)/2 (OSCCLK * 11)/1 01100 (OSCCLK * 12)/4 (OSCCLK * 12)/2 (OSCCLK * 12)/1 01101 (OSCCLK * 13)/4 (OSCCLK * 13)/2 (OSCCLK * 13)/1 01110 (OSCCLK * 14)/4 (OSCCLK * 14)/2 (OSCCLK * 14)/1 01111 (OSCCLK * 15)/4 (OSCCLK * 15)/2 (OSCCLK * 15)/1 10000 (OSCCLK * 16)/4 (OSCCLK * 16)/2 (OSCCLK * 16)/1 The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog reset only. A reset issued by the debugger or the missing clock detect logic has no effect. This register is EALLOW protected. See the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18) for more information. By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1. Table 3-17. CLKIN Divide Options PLLSTS [DIVSEL] CLKIN DIVIDE 0 /4 1 /4 2 /2 3 /1 Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 49 ADVANCE INFORMATION PLLCR[DIV] VALUE (1) TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com The PLL-based clock module provides four modes of operation: • INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock for the Watchdog block, core and CPU-Timer 2 • INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen for the Watchdog block, core and CPU-Timer 2. • Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 3-6 for details. • External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input (forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable at boot time. ADVANCE INFORMATION Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock source must be disabled (using the CLKCTL register) before switching clocks. Table 3-18. Possible PLL Configuration Modes REMARKS PLLSTS[DIVSEL] CLKIN AND SYSCLKOUT Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block is disabled in this mode. This can be useful to reduce system noise and for low power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) before entering this mode. The CPU clock (CLKIN) is derived directly from the input clock on either X1/X2, X1 or XCLKIN. 0, 1 2 3 OSCCLK/4 OSCCLK/2 OSCCLK/1 PLL Bypass is the default PLL configuration upon power-up or after an external reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or PLL Bypass while the PLL locks to a new frequency after the PLLCR register has been modified. In this mode, the PLL itself is bypassed but the PLL is not turned off. 0, 1 2 3 OSCCLK/4 OSCCLK/2 OSCCLK/1 PLL Enable (1) 0, 1 2 3 OSCCLK * n/4 OSCCLK * n/2 OSCCLK * n/1 PLL MODE PLL Off (1) Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the PLLCR the device will switch to PLL Bypass mode until the PLL locks. PLLSTS[DIVSEL] should not be set to /1 mode while the PLL is enabled. 3.9.4 Loss of Input Clock (NMI Watchdog Function) The 2806x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz. When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt. Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock failure and initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a shut-down procedure for the system. If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a preprogrammed time interval. Figure 3-15 shows the interrupt mechanisms involved. 50 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 NMIFLG[NMINT] NMIFLGCLR[NMINT] Clear Latch Set Clear XRS NMINT Generate Interrupt Pulse When Input = 1 1 0 NMIFLG[CLOCKFAIL] Clear Latch Clear Set 0 NMIFLGCLR[CLOCKFAIL] CLOCKFAIL SYNC? SYSCLKOUT NMICFG[CLOCKFAIL] NMIFLGFRC[CLOCKFAIL] SYSCLKOUT SYSRS NMIWDPRD[15:0] NMIWDCNT[15:0] NMI Watchdog NMIRS See System Control Section Figure 3-15. NMI-Watchdog 3.9.5 CPU-Watchdog Module The CPU-watchdog module on the 2806x device is similar to the one used on the 281x/280x/283xx devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter. Figure 3-16 shows the various functional blocks within the watchdog module. Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock). NOTE The CPU-watchdog is different from the NMI watchdog. It is the legacy watchdog that is present in all 28x devices. NOTE Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the flash memory. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 51 ADVANCE INFORMATION XRS TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com WDCR (WDPS[2:0]) WDCR (WDDIS) WDCNTR(7:0) WDCLK Watchdog Prescaler /512 WDCLK 8-Bit Watchdog Counter CLR Clear Counter Internal Pullup WDKEY(7:0) Watchdog 55 + AA Key Detector WDRST Generate Output Pulse WDINT (512 OSCCLKs) Good Key XRS Core-reset WDCR (WDCHK[2:0]) ADVANCE INFORMATION WDRST(A) A. 1 0 Bad WDCHK Key SCSR (WDENINT) 1 The WDRST signal is driven low for 512 OSCCLK cycles. Figure 3-16. CPU-Watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.10, Low-power Modes Block, for more details. In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset. 52 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 3.10 Low-power Modes Block Table 3-19 summarizes the various modes. Table 3-19. Low-power Modes EXIT (1) MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT IDLE 00 On On On XRS, CPU-watchdog interrupt, any enabled interrupt STANDBY 01 On (CPU-watchdog still running) Off Off XRS, CPU-watchdog interrupt, GPIO Port A signal, debugger (2) 1X Off (on-chip crystal oscillator and PLL turned off, zero-pin oscillator and CPU-watchdog state dependent on user code.) Off Off XRS, GPIO Port A signal, debugger (2), CPU-watchdog HALT (3) (2) (3) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power mode will not be exited and the device will go back into the indicated low power mode. The JTAG port can still function even if the CPU clock (CLKIN) is turned off. The WDCLK must be active for the device to go into HALT mode. The various low-power modes operate as follows: IDLE Mode: This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0. STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register. HALT Mode: CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The user selects the signal in the GPIOLPMSEL register. NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18) for more details. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 53 ADVANCE INFORMATION (1) TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 4 Device and Documentation Support 4.1 Getting Started This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following: • Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0). • C2000 Getting Started Website (http://www.ti.com/c2000getstarted) • TMS320F28x MCU Development and Experimenter's Kits (http://www.ti.com/f28xkits) 4.2 Development Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of 2806x-based applications: ADVANCE INFORMATION Software Development Tools • Code Composer Studio™ Integrated Development Environment (IDE) – C/C++ Compiler – Code generation tools – Assembler/Linker – Cycle Accurate Simulator • Application algorithms • Sample applications code Hardware Development Tools • Development and evaluation boards • JTAG-based emulators - XDS510™ class, XDS560™ emulator, XDS100 • Flash programming tools • Power supply • Documentation and cables 4.3 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ MCU devices and support tools. Each TMS320™ MCU commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMX320F28069). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: 54 TMX Experimental device that is not necessarily representative of the final device's electrical specifications TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Device and Documentation Support Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PZP) and temperature range (for example, S). Figure 4-1 provides a legend for reading the complete device name for any family member. TMX 320 F 28069 PZP S PREFIX TMX = experimental device TMP = prototype device TMS = qualified device TEMPERATURE RANGE T = −40°C to 105°C S = −40°C to 125°C Q = −40°C to 125°C (Q refers to Q100 qualification for automotive applications.) DEVICE FAMILY 320 = TMS320 MCU Family PACKAGE TYPE 80-Pin PN Low-Profile Quad Flatpack (LQFP) TM 80-Pin PFP PowerPAD Low-Profile Quad Flatpack (LQFP) 100-Pin PZ Low-Profile Quad Flatpack (LQFP) 100-Pin PZP PowerPAD TM Low-Profile Quad Flatpack (LQFP) TECHNOLOGY F = Flash DEVICE 28069 28068 28067 28066 28065 28064 28063 28062 Figure 4-1. Device Nomenclature Device and Documentation Support Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 55 ADVANCE INFORMATION Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 4.4 www.ti.com Documentation Support Extensive documentation supports all of the TMS320™ MCU family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications. See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) for more information on types of peripherals. See the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18) for more information about each peripheral. The following documents can be downloaded from the TI website (www.ti.com): Data Manual/Errata SPRS698 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 Piccolo Microcontrollers Data Manual contains the pinout, signal descriptions, as well as electrical and timing specifications for the 2806x devices. SPRZ342 ADVANCE INFORMATION TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 Piccolo MCU Silicon Errata describes known advisories on silicon and provides workarounds. CPU User's Guides SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. Peripheral Guides and Technical Reference Manuals SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). SPRUH18 TMS320x2806x Piccolo Technical Reference Manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device. Tools Guides SPRU513 TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. 56 SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. SPRU608 TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core. Device and Documentation Support Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 4.5 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. ADVANCE INFORMATION TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. Device and Documentation Support Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 57 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 5 Device Operating Conditions 5.1 Absolute Maximum Ratings (1) (2) Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V Supply voltage range, VDD with respect to VSS –0.3 V to 2.5 V Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V Input voltage range, VIN (3.3 V) –0.3 V to 4.6 V Output voltage range, VO –0.3 V to 4.6 V Input clamp current, IIK (VIN < 0 or VIN > VDDIO) (3) ±20 mA Output clamp current, IOK (VO < 0 or VO > VDDIO) ±20 mA Junction temperature range, TJ (4) Storage temperature range, Tstg (1) ADVANCE INFORMATION (2) (3) (4) 5.2 –40°C to 150°C (4) –65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS, unless otherwise noted. Continuous clamp current per pin is ± 2 mA. Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963). Recommended Operating Conditions Device supply voltage, I/O, VDDIO (1) Device supply voltage CPU, VDD (When internal VREG is disabled and 1.8 V is supplied externally) MIN NOM 2.97 1.71 2.97 3.3 Supply ground, VSS Analog ground, VSSA High-level input voltage, VIH (3.3 V) Low-level input voltage, VIL (3.3 V) High-level output source current, VOH = VOH(MIN) , IOH Low-level output sink current, VOL = VOL(MAX), IOL 58 3.3 3.63 V 1.8 1.995 (3) V V 3.63 0 Device clock frequency (system clock) (1) (2) (3) UNIT 0 Analog supply voltage, VDDA (1) Junction temperature, TJ MAX V V 2 80 2 VDDIO + 0.3 VSS – 0.3 0.8 MHz V V All GPIO/AIO pins –4 mA Group 2 (2) –8 mA All GPIO/AIO pins 4 mA Group 2 (2) 8 mA T version –40 105 S version –40 125 Q version (Q100 qualification) –40 125 °C VDDIO and VDDA should be maintained within ~0.3 V of each other. Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37. TA (Ambient temperature) is product- and application-dependent and can go up to the specified TJ max of the device. Device Operating Conditions Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 5.3 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Electrical Characteristics (1) over recommended operating conditions (unless otherwise noted) PARAMETER High-level output voltage VOL Low-level output voltage IIL IIH Input current (low level) Input current (high level) IOH = IOH MAX MIN MAX UNIT 2.4 IOH = 50 μA V VDDIO – 0.2 IOL = IOL MAX 0.4 All GPIO/AIO –80 –140 –205 –230 –300 –375 Pin with pullup enabled VDDIO = 3.3 V, VIN = 0 V Pin with pulldown enabled VDDIO = 3.3 V, VIN = 0 V ±2 Pin with pullup enabled VDDIO = 3.3 V, VIN = VDDIO ±2 Pin with pulldown enabled VDDIO = 3.3 V, VIN = VDDIO IOZ Output current, pullup or pulldown disabled CI Input capacitance VDDIO BOR trip point XRS pin V μA μA 28 50 VO = VDDIO or 0 V 80 ±2 2 Falling VDDIO 2.50 VDDIO BOR hysteresis (1) TYP 2.78 pF 2.96 35 Supervisor reset release delay time Time after BOR/POR/OVR event is removed to XRS release VREG VDD output Internal VREG on 400 μA V mV 800 μs 1.9 V When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage (VDD) go out of range. Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 59 ADVANCE INFORMATION VOH TEST CONDITIONS TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6 Peripheral and Electrical Specifications 6.1 Parameter Information 6.1.1 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: ADVANCE INFORMATION 6.1.2 Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 6.2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. Tester Pin Electronics 42 W Data Sheet Timing Reference Point 3.5 nH Output Under Test Transmission Line (A) Z0 = 50 W 4.0 pF A. B. Device Pin 1.85 pF (B) Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Figure 6-1. 3.3-V Test Load Circuit 60 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 6.3 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the 2806x MCUs. Table 6-1 lists the cycle times of various clocks. Table 6-1. 2806x Clock Table and Nomenclature (80-MHz Devices) MIN tc(SCO), Cycle time SYSCLKOUT Frequency tc(LCO), Cycle time LSPCLK (1) tc(ADCCLK), Cycle time (1) (2) MAX UNIT 500 ns 2 80 MHz 80 MHz 16.67 66.67 (2) 15 (2) Frequency ADC clock NOM 16.67 ns 16.67 ns Frequency 80 MHz MAX UNIT Lower LSPCLK will reduce device power consumption. This is the default reset value if SYSCLKOUT = 80 MHz. MIN On-chip oscillator (X1/X2 pins) (Crystal/Resonator) tc(OSC), Cycle time External oscillator/clock source (XCLKIN pin) — PLL Enabled tc(CI), Cycle time (C8) External oscillator/clock source (XCLKIN pin) — PLL Disabled tc(CI), Cycle time (C8) Limp mode SYSCLKOUT (with /2 enabled) Frequency Frequency Frequency PLL lock time (1) 50 200 ns 5 20 MHz 33.3 200 ns MHz 5 30 33.33 250 ns 4 30 MHz Frequency range tc(XCO), Cycle time (C1) XCLKOUT (1) Frequency tp NOM 1 to 5 MHz 66.67 2000 0.5 15 MHz ns 1 ms The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum). Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 61 ADVANCE INFORMATION Table 6-2. Device Clocking Requirements/Characteristics TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-3. Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics PARAMETER MIN TYP MAX UNIT Internal zero-pin oscillator 1 (INTOSC1) at 30°C (1) (2) Frequency 10.000 MHz Internal zero-pin oscillator 2 (INTOSC2) at 30°C (1) (2) Frequency 10.000 MHz 55 kHz Step size (coarse trim) Step size (fine trim) 14 Temperature drift (3) 3.03 4.85 kHz/°C Voltage (VDD) drift (3) 175 Hz/mV (1) (2) (3) kHz In order to achieve better oscillator accuracy (10 MHz ± 1% or better) than shown, refer to the Oscillator Compensation Guide Application Report (literature number SPRAB84). Frequency range ensured only when VREG is enabled, VREGENZ = VSS. Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For example: • Increase in temperature will cause the output frequency to increase per the temperature coefficient. • Decrease in voltage (VDD) will cause the output frequency to decrease per the voltage coefficient. Zero-Pin Oscillator Frequency Movement With Temperature 10.5 10.4 Output Frequency (MHz) ADVANCE INFORMATION 10.6 10.3 10.2 10.1 10 9.9 9.8 9.7 9.6 –40 –30 –20 –10 0 Typical 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (°C) Max Figure 6-2. Zero-Pin Oscillator Frequency Movement With Temperature 62 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 6.4 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Clock Requirements and Characteristics Table 6-4. XCLKIN Timing Requirements - PLL Enabled NO. MIN MAX UNIT C9 tf(CI) Fall time, XCLKIN 6 ns C10 tr(CI) Rise time, XCLKIN 6 ns C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 % C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 % MIN MAX Table 6-5. XCLKIN Timing Requirements - PLL Disabled C9 tf(CI) Fall time, XCLKIN C10 tr(CI) Rise time, XCLKIN Up to 20 MHz 6 20 MHz to 30 MHz 2 Up to 20 MHz 6 20 MHz to 30 MHz 2 UNIT ns ns C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 % C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 % ADVANCE INFORMATION NO. The possible configuration modes are shown in Table 3-18. Table 6-6. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2) NO. (1) (2) PARAMETER MIN TYP MAX UNIT C3 tf(XCO) Fall time, XCLKOUT ns C4 tr(XCO) Rise time, XCLKOUT ns C5 tw(XCOL) Pulse duration, XCLKOUT low H–2 H+2 ns C6 tw(XCOH) Pulse duration, XCLKOUT high H–2 H+2 ns A load of 40 pF is assumed for these parameters. H = 0.5tc(XCO) C10 C9 C8 XCLKIN(A) C1 C6 C3 C4 C5 XCLKOUT(B) A. B. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate the timing parameters only and may differ based on actual configuration. XCLKOUT configured to reflect SYSCLKOUT. Figure 6-3. Clock Timing Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 63 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.5 www.ti.com Power Sequencing There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up/down. However, it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results. VDDIO, VDDA (3.3 V) VDD (1.8 V) INTOSC1 tINTOSCST X1/X2 ADVANCE INFORMATION tOSCST (B) (A) XCLKOUT User-code dependent tw(RSL1) XRS (D) Address/data valid, internal boot-ROM code execution phase Address/Data/ Control (Internal) td(EX) th(boot-mode)(C) Boot-Mode Pins User-code execution phase User-code dependent GPIO pins as input Peripheral/GPIO function Based on boot code Boot-ROM execution starts I/O Pins GPIO pins as input (state depends on internal PU/PD) User-code dependent A. B. C. D. Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that XCLKOUT will not be visible at the pin until explicitly configured by user code. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry. Figure 6-4. Power-on Reset 64 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-7. Reset (XRS) Timing Requirements MIN th(boot-mode) Hold time for boot-mode pins tw(RSL2) Pulse duration, XRS low on warm reset NOM MAX UNIT 1000tc(SCO) cycles 32tc(OSCCLK) cycles Table 6-8. Reset (XRS) Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS tw(RSL1) Pulse duration, XRS driven by device tw(WDRS) Pulse duration, reset pulse generated by watchdog td(EX) Delay time, address/data valid after XRS high tINTOSCST Start up time, internal zero-pin oscillator tOSCST (1) (1) MIN TYP MAX UNIT μs 600 On-chip crystal-oscillator start-up time 512tc(OSCCLK) cycles 32tc(OSCCLK) cycles 1 3 μs 10 ms Dependent on crystal/resonator and board design. ADVANCE INFORMATION INTOSC1 X1/X2 XCLKOUT User-Code Dependent tw(RSL2) XRS Address/Data/ Control (Internal) td(EX) User-Code Execution Boot-ROM Execution Starts Boot-Mode Pins User-Code Execution Phase Peripheral/GPIO Function GPIO Pins as Input th(boot-mode)(A) Peripheral/GPIO Function User-Code Execution Starts I/O Pins User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD) User-Code Dependent A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. Figure 6-5. Warm Reset Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 65 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Figure 6-6 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4. OSCCLK Write to PLLCR SYSCLKOUT OSCCLK * 2 (Current CPU Frequency) OSCCLK * 4 OSCCLK/2 (CPU frequency while PLL is stabilizing with the desired frequency. This period (PLL lock-up time tp) is 1 ms long.) (Changed CPU frequency) Figure 6-6. Example of Effect of Writing Into PLLCR Register ADVANCE INFORMATION 66 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 6.6 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Current Consumption Table 6-9. TMS320F2806x Current Consumption at 80-MHz SYSCLKOUT IDDIO (1) TEST CONDITIONS TYP (3) VREG DISABLED IDDA (2) MAX TYP (3) MAX IDDIO (1) IDD TYP (3) MAX TYP (3) MAX IDDA (2) TYP (3) Operational (Flash) The following peripheral clocks are enabled: • ePWM1/2/3/4/5/6/7/8 • eCAP1/2/3 • eQEP1/2 • eCAN • CLA • HRPWM • SCI-A/B • SPI-A/B • ADC • I2C • COMP1/2/3 • CPU-TIMER0/1/2 • McBSP • HRCAP All PWM pins are toggled at 60 kHz. All I/O pins are left unconnected. (4) (5) Code is running out of flash with 2 wait-states. XCLKOUT is turned off. 140 mA (6) 16 mA 130 mA (6) 7 mA 16 mA IDLE Flash is powered down. XCLKOUT is turned off. All peripheral clocks are turned off. 21 mA 300 µA 18 mA 400 µA 300 µA STANDBY Flash is powered down. Peripheral clocks are off. 7 mA 300 µA 6 mA 400 µA 300 µA HALT Flash is powered down. Peripheral clocks are off. Input clock is disabled. (7) 3 mA 300 µA 2 mA 120 µA 300 µA (1) (2) (3) (4) (5) (6) (7) MAX IDDIO current is dependent on the electrical loading on the I/O pins. In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register. The TYP numbers are applicable over room temperature and nominal voltage. The following is done in a loop: • Data is continuously transmitted out of SPI-A/B, SCI-A, eCAN-A, McBSP-A, and I2C ports. • The hardware multiplier is exercised. • Watchdog is reset. • ADC is performing continuous conversion. • COMP1/2 are continuously switching voltages. • GPIO17 is toggled. CLA is continuously performing polynomial calculations. For F2806x devices that do not have CLA, subtract the IDD current number for CLA (see Table 6-10) from the IDD (VREG disabled)/IDDIO (VREG enabled) current numbers shown in Table 6-9 for operational mode. If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator. NOTE The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 67 ADVANCE INFORMATION VREG ENABLED MODE TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.6.1 www.ti.com Reducing Current Consumption The 2806x devices incorporate a method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-10 indicates the typical reduction in current consumption achieved by turning off the clocks. Table 6-10. Typical Current Consumption by Various Peripherals (at 80 MHz) (1) ADVANCE INFORMATION (1) (2) (3) PERIPHERAL MODULE (2) IDD CURRENT REDUCTION (mA) ADC 2 (3) I2C 3 ePWM 2 eCAP 2 eQEP 2 SCI 2 SPI 2 COMP/DAC 1 HRPWM 3 CPU-TIMER 1 Internal zero-pin oscillator 0.5 CAN 2.5 CLA 20 McBSP 6 All peripheral clocks (except CPU Timer clock) are disabled upon reset. Writing to/reading from peripheral registers is possible only after the peripheral clocks are turned on. For peripherals with multiple instances, the current quoted is per module. For example, the 2 mA value quoted for ePWM is for one ePWM module. This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (IDDA) as well. NOTE IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off. NOTE The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is 40 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline IDD current. Following are other methods to reduce power consumption further: • The flash module may be powered down if code is run off SARAM. This results in a current reduction of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail. • Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function. 68 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 6.7 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Emulator Connection Without Signal Buffering for the MCU Figure 6-7 shows the connection between the MCU and JTAG header for a single-processor configuration. If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-7 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see Section 3.4, Signal Descriptions. 6 inches or less VDDIO VDDIO 14 2 TRST 1 TMS 3 TDI TDO TCK 7 11 9 EMU0 PD EMU1 TRST GND TMS GND TDI GND TDO GND TCK GND 5 4 ADVANCE INFORMATION 13 6 8 10 12 TCK_RET MCU JTAG Header A. See Figure 6-46 for JTAG/GPIO multiplexing. Figure 6-7. Emulator Connection Without Signal Buffering for the MCU NOTE The 2806x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header on-board, the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-kΩ (typical) resistor. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 69 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.8 www.ti.com Interrupts Figure 6-8 shows how the various interrupt sources are multiplexed. Peripherals DMA clear (SPI, SCI, McBSP, I2C, eCAN, ePWM, eCAP, eQEP, HRCAP, ADC, CLA) WDINT WAKEINT Sync C28x Core ADVANCE INFORMATION Up to 96 Interrupts XINT1 PIE Watchdog Low-Power Modes SYSCLKOUT DMA INT1 to INT12 LPMINT XINT1 Interrupt Control XINT1CR[15:0] XINT1CTR[15:0] DMA GPIOXINT1SEL[4:0] ADC XINT2 M U X XINT2SOC XINT2 Interrupt Control XINT2CR[15:0] XINT2CTR[15:0] M U X GPIOXINT2SEL[4:0] GPIO0.int DMA XINT3 XINT3 Interrupt Control XINT3CR[15:0] M U X GPIO MUX GPIO31.int XINT3CTR[15:0] GPIOXINT3SEL[4:0] DMA INT13 INT14 TINT0 CPU TIMER 0 TINT1 CPU TIMER 1 TINT2 CPU TIMER 2 TOUT1 Flash Wrapper CPUTMR2CLK CLOCKFAIL NMI NMI Interrupt With Watchdog Function (See the NMI Watchdog section.) NMIRS System Control (See the System Control section.) Figure 6-8. External and PIE Interrupt Sources 70 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. Table 6-11 shows the interrupts used by 2806x devices. The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior. When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth. IFR[12:1] IER[12:1] INTM INT1 INT2 1 CPU MUX INT11 INT12 (Flag) INTx INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 PIEACKx (Enable/Flag) Global Enable (Enable) MUX (Enable) (Flag) PIEIERx[8:1] PIEIFRx[8:1] ADVANCE INFORMATION 0 From Peripherals or External Interrupts Figure 6-9. Multiplexing of Interrupts Using the PIE Block Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 71 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-11. PIE MUXed Peripheral Interrupt Vector Table (1) INT1.y INT2.y INT3.y INT4.y INT5.y INT6.y ADVANCE INFORMATION INT7.y INT8.y INT9.y INT10.y INT11.y INT12.y (1) 72 INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1 (LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC) 0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40 EPWM8_TZINT EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT (ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50 EPWM8_INT EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT (ePWM8) (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1) 0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60 HRCAP2_INT HRCAP1_INT Reserved Reserved Reserved ECAP3_INT ECAP2_INT ECAP1_INT (HRCAP2) (HRCAP1) – – – (eCAP3) (eCAP2) (eCAP1) 0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70 Reserved Reserved Reserved HRCAP4_INT HRCAP3_INT Reserved EQEP2_INT EQEP1_INT (eQEP1) – – – (HRCAP4) (HRCAP3) – (eQEP2) 0xD8E 0xD8C 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80 Reserved Reserved MXINTA MRINTA SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA (SPI-A) – – (McBSP-A) (McBSP-A) (SPI-B) (SPI-B) (SPI-A) 0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90 Reserved Reserved DINTCH6 DINTCH5 DINTCH4 DINTCH3 DINTCH2 DINTCH1 – – (DMA) (DMA) (DMA) (DMA) (DMA) (DMA) 0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0 Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A – – – – – – (I2C-A) (I2C-A) 0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0 Reserved Reserved ECAN1_INTA ECAN0_INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA (SCI-A) – – (CAN-A) (CAN-A) (SCI-B) (SCI-B) (SCI-A) 0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1 (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) 0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0 CLA1_INT8 CLA1_INT7 CLA1_INT6 CLA1_INT5 CLA1_INT4 CLA1_INT3 CLA1_INT2 CLA1_INT1 (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) 0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0 LUF LVF Reserved Reserved Reserved Reserved Reserved XINT3 (CLA) (CLA) – – – – – Ext. Int. 3 0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0 Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts: • No peripheral within the group is asserting interrupts. • No peripheral interrupts are assigned to the group (e.g., PIE group 7). Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-12. PIE Configuration and Control Registers DESCRIPTION (1) ADDRESS SIZE (x16) PIECTRL 0x0CE0 1 PIE, Control Register PIEACK 0x0CE1 1 PIE, Acknowledge Register PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0CFA – 0x0CFF 6 Reserved (1) ADVANCE INFORMATION NAME The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 73 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.8.1 www.ti.com External Interrupts Table 6-13. External Interrupt Registers ADDRESS SIZE (x16) XINT1CR NAME 0x00 7070 1 XINT1 configuration register DESCRIPTION XINT2CR 0x00 7071 1 XINT2 configuration register XINT3CR 0x00 7072 1 XINT3 configuration register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register XINT3CTR 0x00 707A 1 XINT3 counter register Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and negative edge. For more information, see the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18). 6.8.1.1 External Interrupt Electrical Data/Timing ADVANCE INFORMATION tw(INT) XINT1, XINT2, XINT3 td(INT) Address bus (internal) Interrupt Vector Figure 6-10. External Interrupt Timing Table 6-14. External Interrupt Timing Requirements (1) TEST CONDITIONS tw(INT) (2) (1) (2) Pulse duration, INT input low/high MIN MAX UNIT Synchronous 1tc(SCO) cycles With qualifier 1tc(SCO) + tw(IQSW) cycles For an explanation of the input qualifier parameters, see Table 6-67. This timing is applicable to any GPIO pin configured for ADCSOC functionality. Table 6-15. External Interrupt Switching Characteristics (1) PARAMETER td(INT) (1) 74 Delay time, INT low/high to interrupt-vector fetch MIN MAX UNIT tw(IQSW) + 12tc(SCO) cycles For an explanation of the input qualifier parameters, see Table 6-67. Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com Control Law Accelerator (CLA) Overview The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks frees up the main CPU to perform other system and communication functions concurently. The following is a list of major features of the CLA. • Clocked at the same rate as the main CPU (SYSCLKOUT). • An independent architecture allowing CLA algorithm execution independent of the main C28x CPU. – Complete bus architecture: • Program address bus and program data bus • Data address bus, data read bus, and data write bus – Independent eight-stage pipeline. – 12-bit program counter (MPC) – Four 32-bit result registers (MR0–MR3) – Two 16-bit auxillary registers (MAR0, MAR1) – Status register (MSTF) • Instruction set includes: – IEEE single-precision (32-bit) floating-point math operations – Floating-point math with parallel load or store – Floating-point multiply with parallel add or subtract – 1/X and 1/sqrt(X) estimations – Data type conversions. – Conditional branch and call – Data load/store operations • The CLA program code can consist of up to eight tasks or interrupt service routines. – The start address of each task is specified by the MVECT registers. – No limit on task size as long as the tasks fit within the CLA program memory space. – One task is serviced at a time through to completion. There is no nesting of tasks. – Upon task completion, a task-specific interrupt is flagged within the PIE. – When a task finishes, the next highest-priority pending task is automatically started. • Task trigger mechanisms: – C28x CPU via the IACK instruction – Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example: • Task1: ADCINT1 or EPWM1_INT • Task2: ADCINT2 or EPWM2_INT • Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT • Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT – Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT. • Memory and Shared Peripherals: – Two dedicated message RAMs for communication between the CLA and the main CPU. – The C28x CPU can map CLA program and data memory to the main CPU space or CLA space. – The CLA has direct access to the ADC Result registers, comparator registers, and the eCAP, eQEP, and ePWM+HRPWM registers. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 75 ADVANCE INFORMATION 6.9 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com CLA Control Registers Peripheral Interrupts IACK ADCINT1 to ADCINT8 ECAP1_INT to ECAP3_INT EPWM1_INT to EPWM8_INT MPERINT1 to MPERINT8 CPU Timer 0 MIFR MIOVF MICLR MICLROVF MIFRC MIER MIRUN MPISRCSEL1 CLA Program Address Bus ADVANCE INFORMATION CLA Program Memory CLA Program Data Bus ain CPU BUS Map to CLA or CPU Space SYSCLKOUT CLAENCLK SYSRS CLA_INT1 to CLA_INT8 INT11 INT12 PIE LVF LUF Main CPU Read/Write Data Bus MVECT1 MVECT2 MVECT3 MVECT4 MVECT5 MVECT6 MVECT7 MVECT8 MMEMCFG Main 28x CPU CLA Data Memory Map to CLA or CPU Space MCTL CLA Shared Message RAMs ADC Result Registers Main CPU Read Data Bus MPC(12) MSTF(32) MR0(32) MR1(32) MR2(32) MR3(32) MAR0(32) MAR1(32) MEALLOW CLA Data Read Address Bus CLA Data Read Data Bus CLA Data Write Address Bus CLA Data Write Data Bus CLA Data Bus CLA Execution Registers ePWM and HRPWM Registers Main CPU Bus EQEP1_INT and EQEP2_INT Comparator Registers eCAP Registers eQEP Registers Figure 6-11. CLA Block Diagram 76 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-16. CLA Control Registers REGISTER NAME CLA1 ADDRESS SIZE (x16) EALLOW PROTECTED MVECT1 0x1400 1 Yes CLA Interrupt/Task 1 Start Address MVECT2 0x1401 1 Yes CLA Interrupt/Task 2 Start Address MVECT3 0x1402 1 Yes CLA Interrupt/Task 3 Start Address MVECT4 0x1403 1 Yes CLA Interrupt/Task 4 Start Address MVECT5 0x1404 1 Yes CLA Interrupt/Task 5 Start Address MVECT6 0x1405 1 Yes CLA Interrupt/Task 6 Start Address MVECT7 0x1406 1 Yes CLA Interrupt/Task 7 Start Address MVECT8 0x1407 1 Yes CLA Interrupt/Task 8 Start Address MCTL 0x1410 1 Yes CLA Control Register 0x1411 1 Yes CLA Memory Configure Register 0x1414 2 Yes Peripheral Interrupt Source Select Register 1 MIFR 0x1420 1 Yes Interrupt Flag Register MIOVF 0x1421 1 Yes Interrupt Overflow Register MIFRC 0x1422 1 Yes Interrupt Force Register MICLR 0x1423 1 Yes Interrupt Clear Register MICLROVF 0x1424 1 Yes Interrupt Overflow Clear Register MIER 0x1425 1 Yes Interrupt Enable Register MIRUN 0x1426 1 Yes Interrupt RUN Register MIPCTL 0x1427 1 Yes Interrupt Priority Control Register (2) 0x1428 1 – CLA Program Counter MAR0 (2) 0x142A 1 – CLA Aux Register 0 MAR1 (2) 0x142B 1 – CLA Aux Register 1 (2) MSTF 0x142E 2 – CLA STF Register MR0 (2) 0x1430 2 – CLA R0H Register MR1 (2) 0x1434 2 – CLA R1H Register (2) 0x1438 2 – CLA R2H Register MR3 (2) 0x143C 2 – CLA R3H Register MR2 All registers in this table are CSM protected The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes to this register. Table 6-17. CLA Message RAM ADDRESS RANGE SIZE (x16) DESCRIPTION 0x1480 – 0x14FF 128 CLA to CPU Message RAM 0x1500 – 0x157F 128 CPU to CLA Message RAM Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 77 ADVANCE INFORMATION MMEMCFG MPISRCSEL1 MPC (1) (2) DESCRIPTION (1) TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.10 Analog Block A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x. The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the timing control of start of conversions. Figure 6-12 shows the interaction of the analog module with the rest of the F2806x system. 80-Pin 100-Pin VDDA VDDA (3.3 V) VDDA (Agnd) VSSA VREFLO VREFLO VSSA Tied To VSSA VREFLO Interface Reference Diff VREFHI VREFHI Tied To A0 A0 A1 A1 A2 A2 VREFHI A0 B0 A1 B1 A3 A4 A5 A5 A6 A6 A7 ADVANCE INFORMATION B0 B0 B1 B1 B2 B2 B4 B4 B5 B5 B6 B6 B3 B7 Signal Pinout A2 Simultaneous Sampling Channels A4 B2 COMP1OUT AIO2 AIO10 10-Bit DAC Comp1 A3 B3 A4 B4 ADC COMP2OUT AIO4 AIO12 10-Bit DAC Comp2 B5 Temperature Sensor A5 A6 B6 COMP3OUT AIO6 AIO14 10-Bit DAC Comp3 A7 B7 Figure 6-12. Analog Pin Configurations 78 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.10.1 Analog-to-Digital Converter (ADC) 6.10.1.1 Features The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-and-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 16 analog input channels. The converter can be configured to run with an internal bandgap reference to create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to create ratiometric-based conversions. Functions of the ADC module include: • 12-bit ADC core with built-in dual sample-and-hold (S/H) • Simultaneous sampling or sequential sampling modes • Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input analog voltage is derived by: – Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or external reference modes.) Digital Value = 0, when input £ 0 V Digital Value = 4096 ´ Input Analog Voltage - VREFLO 3.3 Digital Value = 4095, when 0 V < input < 3.3 V when input ³ 3.3 V – External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA when using either internal or external reference modes.) when input £ 0 V Digital Value = 0, Digital Value = 4096 ´ Digital Value = 4095, • • • • • • Input Analog Voltage - VREFLO VREFHI - VREFLO when 0 V < input < VREFHI when input ³ VREFHI Runs at full system clock, no prescaling required Up to 16-channel, multiplexed inputs 16 SOCs, configurable for trigger, sample window, and channel 16 result registers (individually addressable) to store conversion values Multiple trigger sources – S/W – software immediate start – ePWM 1–8 – GPIO XINT2 – CPU Timers 0/1/2 – ADCINT1/2 9 flexible PIE interrupts, can configure interrupt request after any conversion Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 79 ADVANCE INFORMATION Contrary to previous ADC types, this ADC is not sequencer-based. It is easy for the user to create a series of conversions from a single trigger. However, the basic principle of operation is centered around the configurations of individual conversions, called SOCs, or Start-Of-Conversions. TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-18. ADC Configuration and Control Registers ADDRESS SIZE (x16) EALLOW PROTECTED ADCCTL1 0x7100 1 Yes Control 1 Register ADCINTFLG 0x7104 1 No Interrupt Flag Register ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register ADCINTOVF 0x7106 1 No Interrupt Overflow Register ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register ADCINTSEL1AND2 0x7108 1 Yes Interrupt 1 and 2 Selection Register ADCINTSEL3AND4 0x7109 1 Yes Interrupt 3 and 4 Selection Register ADCINTSEL5AND6 0x710A 1 Yes Interrupt 5 and 6 Selection Register ADCINTSEL7AND8 0x710B 1 Yes Interrupt 7 and 8 Selection Register ADCINTSEL9AND10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection) ADCSOCPRIORITYCTL 0x7110 1 Yes SOC Priority Control Register ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels) ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels) ADCSOCFLG1 0x7118 1 No SOC Flag 1 Register (for 16 channels) ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels) ADCSOCOVF1 0x711C 1 No SOC Overflow 1 Register (for 16 channels) ADCSOCOVFCLR1 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels) 0x7120 – 0x712F 1 Yes SOC0 Control Register to SOC15 Control Register ADCREFTRIM 0x7140 1 Yes Reference Trim Register ADCOFFTRIM 0x7141 1 Yes Offset Trim Register ADCREV 0x714F 1 No Revision Register REGISTER NAME ADVANCE INFORMATION ADCSOC0CTL to ADCSOC15CTL DESCRIPTION Table 6-19. ADC Result Registers (Mapped to PF0) REGISTER NAME ADCRESULT0 to ADCRESULT15 80 ADDRESS 0xB00 – 0xB0F Peripheral and Electrical Specifications SIZE (x16) EALLOW PROTECTED 1 No DESCRIPTION ADC Result 0 Register to ADC Result 15 Register Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 0-Wait Result Registers PF0 (CPU) PF2 (CPU) SYSCLKOUT ADCENCLK ADCINT 1 PIE ADCINT 9 ADCTRIG 2 ADCTRIG 3 AIO MUX ADC Channels ADC Core 12-Bit ADCTRIG 4 ADCTRIG 5 ADCTRIG 6 ADCTRIG 7 ADCTRIG 8 ADCTRIG 9 ADCTRIG 10 ADCTRIG 11 ADCTRIG 12 ADCTRIG 13 ADCTRIG 14 ADCTRIG 15 ADCTRIG 16 ADCTRIG 17 ADCTRIG 18 ADCTRIG 19 ADCTRIG 20 TINT 0 TINT 1 TINT 2 XINT 2SOC CPUTIMER 0 CPUTIMER 1 CPUTIMER 2 XINT 2 SOCA 1 SOCB 1 EPWM 1 SOCA 2 SOCB 2 EPWM 2 SOCA 3 SOCB 3 EPWM 3 SOCA 4 SOCB 4 EPWM 4 SOCA 5 SOCB 5 EPWM 5 SOCA 6 SOCB 6 EPWM 6 SOCA 7 SOCB 7 EPWM 7 SOCA 8 SOCB 8 EPWM 8 Figure 6-13. ADC Connections ADC Connections if the ADC is Not Used It is recommended that the connections for the analog power pins be kept, even if the ADC is not used. Following is a summary of how the ADC pins should be connected, if the ADC is not used in an application: • VDDA – Connect to VDDIO • VSSA – Connect to VSS • VREFLO – Connect to VSS • ADCINAn, ADCINBn, VREFHI – Connect to VSSA When the ADC module is used in an application, unused ADC input pins should be connected to analog ground (VSSA). NOTE: Unused ADCIN pins that are multiplexed with AIO function should not be directly connected to analog ground. They should be grounded through a 1-kΩ resistor. This is to prevent an errant code from configuring these pins as AIO outputs and driving grounded pins to a logic-high state. When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 81 ADVANCE INFORMATION ADCTRIG 1 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.10.1.2 ADC Start-of-Conversion Electrical Data/Timing Table 6-20. External ADC Start-of-Conversion Switching Characteristics PARAMETER tw(ADCSOCL) MIN Pulse duration, ADCSOCxO low MAX 32tc(HCO ) UNIT cycles tw(ADCSOCL) ADCSOCAO or ADCSOCBO Figure 6-14. ADCSOCAO or ADCSOCBO Timing 6.10.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing Table 6-21. ADC Electrical Characteristics PARAMETER MIN TYP MAX UNIT DC SPECIFICATIONS ADVANCE INFORMATION Resolution 12 ADC clock 80-MHz device Sample Window Bits 0.001 40 MHz 7 64 ADC Clocks ACCURACY INL (Integral nonlinearity) (1) 40-MHz clock (3 MSPS) ±2 LSB ±1 LSB Executing Device_Cal function 10 LSB Executing periodic self-recalibration (3) 10 DNL (Differential nonlinearity) Offset error (2) Overall gain error with internal reference 10 LSB Overall gain error with external reference 10 LSB Channel-to-channel offset variation ±4 LSB Channel-to-channel gain variation ±4 LSB ADC temperature coefficient with internal reference –50 ppm/°C ADC temperature coefficient with external reference –20 ppm/°C ANALOG INPUT Analog input voltage with internal reference 0 3.3 V Analog input voltage with external reference VREFLO VREFHI V VREFLO input voltage (4) VSSA 0.66 V VREFHI input voltage (5) 2.64 VDDA V with VREFLO = VSSA Input capacitance Input leakage current (1) (2) (3) (4) (5) 82 1.98 VDDA 5 pF ±2 μA INL will degrade when the ADC input voltage goes above VDDA. 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external reference. Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. VREFLO is always connected to VSSA on the 80-pin PN/PFP device. VREFHI must not exceed VDDA when using either internal or external reference modes. Since VREFHI is tied to ADCINA0 on the 80-pin PN/PFP device, the input signal on ADCINA0 must not exceed VDDA. Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-22. ADC Power Modes IDDA UNITS Mode A – Operating Mode ADC OPERATING MODE ADC Clock Enabled Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 1) ADC Powered Up (ADCPWRDN = 1) CONDITIONS 13 mA Mode B – Quick Wake Mode ADC Clock Enabled Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 1) ADC Powered Up (ADCPWRDN = 0) 4 mA Mode C – Comparator-Only Mode ADC Clock Enabled Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 0) ADC Powered Up (ADCPWRDN = 0) 1.5 mA Mode D – Off Mode ADC Clock Enabled Bandgap On (ADCBGPWD = 0) Reference On (ADCREFPWD = 0) ADC Powered Up (ADCPWRDN = 0) 0.075 mA ADVANCE INFORMATION 6.10.1.3.1 Internal Temperature Sensor Table 6-23. Temperature Sensor Coefficient PARAMETER (1) MIN TSLOPE Degrees C of temperature movement per measured ADC LSB change of the temperature sensor TOFFSET ADC output at 0°C of the temperature sensor (1) (2) (3) TYP MAX 0.18 (2) (3) UNIT °C/LSB 1750 LSB The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be adjusted accordingly in external reference mode to the external reference voltage. ADC temperature coeffieicient is accounted for in this specification Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values relative to an initial value. 6.10.1.3.2 ADC Power-Up Control Bit Timing Table 6-24. ADC Power-Up Delays PARAMETER (1) td(PWD) (1) Delay time for the ADC to be stable after power up MIN TYP MAX UNIT 1 ms Timings maintain compatibility to the ADC module. The 2806x ADC supports driving all 3 bits at the same time td(PWD) ms before first conversion. ADCPWDN/ ADCBGPWD/ ADCREFPWD/ ADCENABLE td(PWD) Request for ADC Conversion Figure 6-15. ADC Conversion Timing Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 83 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 ADCIN Rs Source Signal www.ti.com Ron 3.4 kW Switch Cp 5 pF ac Ch 1.6 pF 28x DSP Typical Values of the Input Circuit Components: Switch Resistance (Ron): 3.4 k W Sampling Capacitor (Ch): 1.6 pF Parasitic Capacitance (Cp): 5 pF Source Resistance (Rs): 50 W ADVANCE INFORMATION Figure 6-16. ADC Input Impedance Model 84 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.10.1.3.3 ADC Sequential and Simultaneous Timings Analog Input SOC0 Sample Window 0 2 SOC1 Sample Window 9 15 SOC2 Sample Window 22 24 37 ADCCLK ADCCTL 1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 ADCRESULT 0 SOC1 2 ADCCLKs SOC2 Result 0 Latched ADVANCE INFORMATION ADCRESULT 1 EOC0 Pulse EOC1 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 13 ADC Clocks 6 ADCCLKs Minimum 7 ADCCLKs 1 ADCCLK Conversion 1 13 ADC Clocks Figure 6-17. Timing Example for Sequential Mode / Late Interrupt Pulse Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 85 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Analog Input SOC0 Sample Window 0 2 SOC1 Sample Window 9 15 SOC2 Sample Window 22 24 37 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 SOC1 SOC2 Result 0 Latched ADCRESULT 0 ADCRESULT 1 ADVANCE INFORMATION EOC0 Pulse EOC1 Pulse EOC2 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 13 ADC Clocks 6 ADCCLKs Minimum 7 ADCCLKs 2 ADCCLKs Conversion 1 13 ADC Clocks Figure 6-18. Timing Example for Sequential Mode / Early Interrupt Pulse 86 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Analog Input A SOC0 Sample A Window SOC2 Sample A Window SOC0 Sample B Window SOC2 Sample B Window Analog Input B 0 2 9 22 24 37 50 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 SOC0 (A/B) ADCRESULT 0 SOC2 (A/B) 2 ADCCLKs Result 0 (A) Latched ADCRESULT 1 Result 0 (B) Latched ADVANCE INFORMATION S/H Window Pulse to Core ADCRESULT 2 EOC0 Pulse 1 ADCCLK EOC1 Pulse EOC2 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 (A) 13 ADC Clocks 19 ADCCLKs Conversion 0 (B) 13 ADC Clocks Minimum 7 ADCCLKs 2 ADCCLKs Conversion 1 (A) 13 ADC Clocks Figure 6-19. Timing Example for Simultaneous Mode / Late Interrupt Pulse Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 87 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Analog Input A SOC0 Sample A Window SOC2 Sample A Window Analog Input B SOC0 Sample B Window 0 2 SOC2 Sample B Window 9 22 24 37 50 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B) 2 ADCCLKs ADCRESULT 0 Result 0 (A) Latched ADCRESULT 1 Result 0 (B) Latched ADVANCE INFORMATION ADCRESULT 2 EOC0 Pulse EOC1 Pulse EOC2 Pulse ADCINTFLG .ADCINTx Minimum 7 ADCCLKs Conversion 0 (A) 13 ADC Clocks 19 ADCCLKs Conversion 0 (B) 13 ADC Clocks Minimum 7 ADCCLKs 2 ADCCLKs Conversion 1 (A) 13 ADC Clocks Figure 6-20. Timing Example for Simultaneous Mode / Early Interrupt Pulse 88 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.10.2 ADC MUX To COMPy A or B input To ADC Channel X Logic implemented in GPIO MUX block AIOx Pin SYSCLK AIOxIN 1 AIOxINE AIODAT Reg (Read) SYNC AIODAT Reg (Latch) AIOxDIR (1 = Input, 0 = Output) AIOMUX 1 Reg AIOSET, AIOCLEAR, AIOTOGGLE Regs AIODIR Reg (Latch) 1 (0 = Input, 1 = Output) 0 0 Figure 6-21. AIOx Pin Multiplexing The ADC channel and Comparator functions are always available. The digital I/O function is available only when the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects the actual pin state. The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode, reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer is disabled to prevent analog signals from generating noise. On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO function disabled for that pin. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 89 ADVANCE INFORMATION 0 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.10.3 Comparator Block Figure 6-22 shows the interaction of the Comparator modules with the rest of the system. COMP x A COMP x B + COMP - GPIO MUX COMP x + DAC x Wrapper AIO MUX TZ1/2/3 ePWM COMPxOUT DAC Core 10-Bit ADVANCE INFORMATION Figure 6-22. Comparator Block Diagram Table 6-25. Comparator Control Registers 90 REGISTER NAME COMP1 ADDRESS COMP2 ADDRESS COMP3 ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION COMPCTL 0x6400 0x6420 0x6440 1 Yes Comparator Control Register COMPSTS 0x6402 0x6422 0x6442 1 No Comparator Status Register DACVAL 0x6406 0x6426 0x6446 1 Yes DAC Value Register Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.10.3.1 On-Chip Comparator/DAC Electrical Data/Timing Table 6-26. Electrical Characteristics of the Comparator/DAC CHARACTERISTIC MIN TYP MAX UNITS Comparator Comparator Input Range VSSA – VDDA V Comparator response time to PWM Trip Zone (Async) 30 ns Input Offset ±5 mV 35 mV Input Hysteresis (1) DAC DAC Output Range VSSA – VDDA DAC resolution DAC settling time bits See Figure 6-23 DAC Gain DAC Offset –1.5 % 10 mV Yes INL ±3 ADVANCE INFORMATION Monotonic (1) V 10 LSB Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback resistance between the output of the comparator and the non-inverting input of the comparator. 1100 1000 900 800 Settling Time (ns) 700 600 500 400 300 200 100 0 0 50 100 150 200 250 300 350 400 450 500 DAC Step Size (Codes) DAC Accuracy 15 Codes 7 Codes 3 Codes 1 Code Figure 6-23. DAC Settling Time Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 91 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.11 Detailed Descriptions Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level one-half LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. Differential Nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes. Zero Offset The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point. Gain Error ADVANCE INFORMATION The first code transition should occur at an analog value one-half LSB above negative full scale. The last transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Signal-to-Noise Ratio + Distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following (SINAD - 1.76) N= 6.02 formula, it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Spurious Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. 92 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.12 Serial Peripheral Interface (SPI) Module The device includes the four-pin serial peripheral interface (SPI) module. Up to two SPI modules are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. NOTE: All four pins can be used as GPIO if the SPI module is not used. • Two operational modes: master and slave Baud rate: 125 different programmable rates. LSPCLK Baud rate = when SPIBRR = 3 to 127 (SPIBRR + 1) Baud rate = • • • • • LSPCLK 4 when SPIBRR = 0, 1, 2 Data word length: one to sixteen data bits Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Simultaneous receive and transmit operation (transmit function can be disabled in software) Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Enhanced feature: • 4-level transmit/receive FIFO • Delayed transmit control • Bi-directional 3 wire SPI mode support • Audio data receive support via SPISTE inversion Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 93 ADVANCE INFORMATION The SPI module features include: • Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com The SPI port operation is configured and controlled by the registers listed in Table 6-27 and Table 6-28. Table 6-27. SPI-A Registers ADVANCE INFORMATION (1) DESCRIPTION (1) NAME ADDRESS SIZE (x16) EALLOW PROTECTED SPICCR 0x7040 1 No SPI-A Configuration Control Register SPICTL 0x7041 1 No SPI-A Operation Control Register SPISTS 0x7042 1 No SPI-A Status Register SPIBRR 0x7044 1 No SPI-A Baud Rate Register SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register SPIDAT 0x7049 1 No SPI-A Serial Data Register SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register SPIFFCT 0x704C 1 No SPI-A FIFO Control Register SPIPRI 0x704F 1 No SPI-A Priority Control Register Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. Table 6-28. SPI-B Registers (1) 94 DESCRIPTION (1) NAME ADDRESS SIZE (x16) EALLOW PROTECTED SPICCR 0x7740 1 No SPI-B Configuration Control Register SPICTL 0x7741 1 No SPI-B Operation Control Register SPISTS 0x7742 1 No SPI-B Status Register SPIBRR 0x7744 1 No SPI-B Baud Rate Register SPIRXEMU 0x7746 1 No SPI-B Receive Emulation Buffer Register SPIRXBUF 0x7747 1 No SPI-B Serial Input Buffer Register SPITXBUF 0x7748 1 No SPI-B Serial Output Buffer Register SPIDAT 0x7749 1 No SPI-B Serial Data Register SPIFFTX 0x774A 1 No SPI-B FIFO Transmit Register SPIFFRX 0x774B 1 No SPI-B FIFO Receive Register SPIFFCT 0x774C 1 No SPI-B FIFO Control Register SPIPRI 0x774F 1 No SPI-B Priority Control Register Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Figure 6-24 is a block diagram of the SPI in slave mode. SPIFFENA SPIFFTX.14 Receiver Overrun Flag RX FIFO Registers SPISTS.7 Overrun INT ENA SPICTL.4 SPIRXBUF RX FIFO _0 RX FIFO _1 ----- SPIINT RX FIFO Interrupt RX FIFO _3 RX Interrupt Logic 16 SPIRXBUF Buffer Register SPIFFOVF FLAG SPIFFRX.15 To CPU TX FIFO Registers SPITXBUF TX FIFO _3 SPI INT ENA SPI INT FLAG SPITXBUF Buffer Register ADVANCE INFORMATION SPITX 16 16 TX Interrupt Logic TX FIFO Interrupt ----TX FIFO _1 TX FIFO _0 SPISTS.6 SPICTL.0 TRIWIRE SPIPRI.0 16 M M SPIDAT Data Register TW S S SPIDAT.15 - 0 SW1 SPISIMO M TW M TW SPISOMI S S STEINV SW2 SPIPRI.1 Talk STEINV SPICTL.1 SPISTE State Control Master/Slave SPICCR.3 - 0 SPI Char 3 2 SPICTL.2 S SW3 0 1 M SPI Bit Rate S SPIBRR.6 - 0 LSPCLK 6 A. 5 4 3 2 1 Clock Polarity Clock Phase SPICCR.6 SPICTL.3 SPICLK M 0 SPISTE is driven low by the master for a slave device. Figure 6-24. SPI Module Block Diagram (Slave Mode) 6.12.1 Serial Peripheral Interface (SPI) Master Mode Electrical Data/ Timing Table 6-29 lists the master mode timing (clock phase = 0) and Table 6-30 lists the master mode timing (clock phase = 1). Figure 6-25 and Figure 6-26 show the timing waveforms. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 95 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-29. SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. MIN UNIT MAX tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) td(SPCH-SIMO)M Delay time, SPICLK high to SPISIMO valid (clock polarity = 0) 10 10 td(SPCL-SIMO)M Delay time, SPICLK low to SPISIMO valid (clock polarity = 1) 10 10 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 0) 35 35 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 1) 35 35 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 ADVANCE INFORMATION 5 8 9 96 MIN 2 4 (5) MAX 1 3 (1) (2) (3) (4) SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 ns ns ns ns ns The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1) tc(LCO) = LSPCLK cycle time Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6). Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 Master In Data Must Be Valid ADVANCE INFORMATION SPISOMI (A) SPISTE A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-25. SPI Master Mode External Timing (Clock Phase = 0) Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 97 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-30. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. MIN tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns tw(SPCL))M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) tsu(SIMO-SPCH)M Setup time, SPISIMO data valid before SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tsu(SIMO-SPCL)M Setup time, SPISIMO data valid before SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 0) 35 35 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) 35 35 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 ADVANCE INFORMATION 7 10 11 98 UNIT MAX 2 6 (4) (5) MIN 1 3 (1) (2) (3) MAX SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 ns ns ns ns ns The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. tc(LCO) = LSPCLK cycle time The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 Master out data Is valid SPISIMO Data Valid 10 11 SPISOMI ADVANCE INFORMATION Master in data must be valid SPISTE(A) B. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-26. SPI Master Mode External Timing (Clock Phase = 1) Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 99 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.12.2 Serial Peripheral Interface (SPI) Slave Mode Electrical Data/ Timing Table 6-31 lists the slave mode external timing (clock phase = 0) and Table 6-32 lists the slave mode external timing (clock phase = 1). Figure 6-27 and Figure 6-28 show the timing waveforms. Table 6-31. SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5) NO. MIN MAX 12 tc(SPC)S Cycle time, SPICLK 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 35 td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 35 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75tc(SPC)S tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75tc(SPC)S tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 35 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 35 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 14 15 16 19 ADVANCE INFORMATION 20 (1) (2) (3) (4) (5) 4tc(LCO) UNIT ns ns ns ns ns ns ns The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. tc(LCO) = LSPCLK cycle time The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 15 16 SPISOMI SPISOMI data Is valid 19 20 SPISIMO SPISIMO data must be valid SPISTE(A) C. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-27. SPI Slave Mode External Timing (Clock Phase = 0) 100 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-32. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5) MIN MAX 12 tc(SPC)S Cycle time, SPICLK 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC) S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC) S tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 0.75tc(SPC)S tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 0.75tc(SPC) S tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 35 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 35 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 14 17 18 21 22 (1) (2) (3) (4) (5) 8tc(LCO) UNIT ns ns ns ns ns ns ns ADVANCE INFORMATION NO. The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) tc(LCO) = LSPCLK cycle time Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 17 18 SPISOMI SPISOMI data is valid Data Valid 21 22 SPISIMO SPISIMO data must be valid SPISTE(A) A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-28. SPI Slave Mode External Timing (Clock Phase = 1) Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 101 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.13 Serial Communications Interface (SCI) Module The devices include up to two serial communications interface (SCI) modules (SCI-A, SCI-B). The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register. Features of each SCI module include: • Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin NOTE: Both pins can be used as GPIO if not used for SCI. – Baud rate programmable to 64K different rates: LSPCLK Baud rate = when BRR ¹ 0 (BRR + 1) * 8 ADVANCE INFORMATION Baud rate = • • • • • • • • LSPCLK 16 when BRR = 0 Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits Four error-detection flags: parity, overrun, framing, and break detection Two wake-up multiprocessor modes: idle-line and address bit Half- or full-duplex operation Double-buffered receive and transmit functions Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) – Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions) Separate enable bits for transmitter and receiver interrupts (except BRKDT) NRZ (non-return-to-zero) format NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Enhanced features: • Auto baud-detect hardware logic • 4-level transmit/receive FIFO 102 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 The SCI port operation is configured and controlled by the registers listed in Table 6-33 and Table 6-34. Table 6-33. SCI-A Registers (1) ADDRESS SIZE (x16) EALLOW PROTECTED SCICCRA 0x7050 1 No SCI-A Communications Control Register SCICTL1A 0x7051 1 No SCI-A Control Register 1 SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits SCICTL2A 0x7054 1 No SCI-A Control Register 2 SCIRXSTA 0x7055 1 No SCI-A Receive Status Register SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register (2) 0x705A 1 No SCI-A FIFO Transmit Register SCIFFRXA (2) 0x705B 1 No SCI-A FIFO Receive Register SCIFFCTA (2) 0x705C 1 No SCI-A FIFO Control Register SCIPRIA 0x705F 1 No SCI-A Priority Control Register SCIFFTXA (1) (2) DESCRIPTION ADVANCE INFORMATION NAME Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. These registers are new registers for the FIFO mode. Table 6-34. SCI-B Registers (1) (1) (2) NAME ADDRESS SIZE (x16) SCICCRB 0x7750 1 SCI-B Communications Control Register DESCRIPTION SCICTL1B 0x7751 1 SCI-B Control Register 1 SCIHBAUDB 0x7752 1 SCI-B Baud Register, High Bits SCILBAUDB 0x7753 1 SCI-B Baud Register, Low Bits SCICTL2B 0x7754 1 SCI-B Control Register 2 SCIRXSTB 0x7755 1 SCI-B Receive Status Register SCIRXEMUB 0x7756 1 SCI-B Receive Emulation Data Buffer Register SCIRXBUFB 0x7757 1 SCI-B Receive Data Buffer Register SCITXBUFB 0x7759 1 SCI-B Transmit Data Buffer Register SCIFFTXB (2) 0x775A 1 SCI-B FIFO Transmit Register SCIFFRXB (2) 0x775B 1 SCI-B FIFO Receive Register SCIFFCTB (2) 0x775C 1 SCI-B FIFO Control Register SCIPRIB 0x775F 1 SCI-B Priority Control Register Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. These registers are new registers for the FIFO mode. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 103 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Figure 6-29 shows the SCI module block diagram. SCICTL1.1 SCITXD Frame Format and Mode TXSHF Register Parity Even/Odd Enable TXENA 8 SCICCR.6 SCICCR.5 TXRDY Transmitter-Data Buffer Register TXWAKE SCICTL1.3 8 TX INT ENA SCICTL2.7 SCICTL2.0 TX FIFO Interrupts TX FIFO _0 TX FIFO _1 1 TXINT TX Interrupt Logic To CPU ----- TX FIFO _3 WUT SCITXD TX EMPTY SCICTL2.6 SCI TX Interrupt select logic SCITXBUF.7-0 TX FIFO registers SCIFFENA AutoBaud Detect logic SCIFFTX.14 SCIHBAUD. 15 - 8 SCIRXD RXSHF Register ADVANCE INFORMATION Baud Rate MSbyte Register SCIRXD RXWAKE LSPCLK SCIRXST.1 SCILBAUD. 7 - 0 RXENA 8 Baud Rate LSbyte Register SCICTL1.0 SCICTL2.1 Receive Data Buffer register SCIRXBUF.7-0 RXRDY 8 BRKDT RX FIFO _3 ----- RX FIFO_1 RX FIFO _0 SCIRXBUF.7-0 RX/BK INT ENA SCIRXST.6 RX FIFO Interrupts SCIRXST.5 RX Interrupt Logic RX FIFO registers SCIRXST.7 SCIRXST.4 - 2 RX Error FE OE PE RXINT To CPU RXFFOVF SCIFFRX.15 RX Error RX ERR INT ENA SCICTL1.6 SCI RX Interrupt select logic Figure 6-29. Serial Communications Interface (SCI) Module Block Diagram 104 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 The McBSP module has the following features: • Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices • Full-duplex communication • Double-buffered data registers that allow a continuous data stream • Independent framing and clocking for receive and transmit • External shift clock generation or an internal programmable frequency shift clock • A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits • 8-bit data transfers with LSB or MSB first • Programmable polarity for both frame synchronization and data clocks • Highly programmable internal clock and frame generation • Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices • Works with SPI-compatible devices • The following application interfaces can be supported on the McBSP: – T1/E1 framers – IOM-2 compliant devices – AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.) – IIS-compliant devices – SPI • McBSP clock rate, CLKG = CLKSRG (1 + CLKGDV ) where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit. NOTE See Section 6 for maximum I/O pin toggling speed. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 105 ADVANCE INFORMATION 6.14 Multichannel Buffered Serial Port (McBSP) Module TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Figure 6-30 shows the block diagram of the McBSP module. TX Interrupt MXINT To CPU Peripheral Write Bus CPU TX Interrupt Logic 16 McBSP Transmit Interrupt Select Logic 16 DXR2 Transmit Buffer LSPCLK DXR1 Transmit Buffer MFSXx 16 16 MCLKXx DMA Bus ADVANCE INFORMATION Peripheral Bus CPU Bridge Compand Logic XSR2 XSR1 MDXx RSR2 RSR1 MDRx 16 MCLKRx 16 Expand Logic MFSRx RBR2 Register McBSP Receive Interrupt Select Logic MRINT RX Interrupt Logic RBR1 Register 16 16 DRR2 Receive Buffer DRR1 Receive Buffer 16 RX Interrupt 16 Peripheral Read Bus CPU To CPU Figure 6-30. McBSP Module 106 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-35 provides a summary of the McBSP registers. Table 6-35. McBSP Register Summary McBSP-A ADDRESS TYPE DRR2 0x5000 R 0x0000 McBSP Data Receive Register 2 DRR1 0x5001 R 0x0000 McBSP Data Receive Register 1 DXR2 0x5002 W 0x0000 McBSP Data Transmit Register 2 DXR1 0x5003 W 0x0000 McBSP Data Transmit Register 1 SPCR2 0x5004 R/W 0x0000 McBSP Serial Port Control Register 2 SPCR1 0x5005 R/W 0x0000 McBSP Serial Port Control Register 1 RCR2 0x5006 R/W 0x0000 McBSP Receive Control Register 2 RCR1 0x5007 R/W 0x0000 McBSP Receive Control Register 1 XCR2 0x5008 R/W 0x0000 McBSP Transmit Control Register 2 XCR1 0x5009 R/W 0x0000 McBSP Transmit Control Register 1 SRGR2 0x500A R/W 0x0000 McBSP Sample Rate Generator Register 2 SRGR1 0x500B R/W 0x0000 McBSP Sample Rate Generator Register 1 NAME RESET VALUE DESCRIPTION Data Registers, Receive, Transmit ADVANCE INFORMATION McBSP Control Registers Multichannel Control Registers MCR2 0x500C R/W 0x0000 McBSP Multichannel Register 2 MCR1 0x500D R/W 0x0000 McBSP Multichannel Register 1 RCERA 0x500E R/W 0x0000 McBSP Receive Channel Enable Register Partition A RCERB 0x500F R/W 0x0000 McBSP Receive Channel Enable Register Partition B XCERA 0x5010 R/W 0x0000 McBSP Transmit Channel Enable Register Partition A XCERB 0x5011 R/W 0x0000 McBSP Transmit Channel Enable Register Partition B PCR 0x5012 R/W 0x0000 McBSP Pin Control Register RCERC 0x5013 R/W 0x0000 McBSP Receive Channel Enable Register Partition C RCERD 0x5014 R/W 0x0000 McBSP Receive Channel Enable Register Partition D XCERC 0x5015 R/W 0x0000 McBSP Transmit Channel Enable Register Partition C XCERD 0x5016 R/W 0x0000 McBSP Transmit Channel Enable Register Partition D RCERE 0x5017 R/W 0x0000 McBSP Receive Channel Enable Register Partition E RCERF 0x5018 R/W 0x0000 McBSP Receive Channel Enable Register Partition F XCERE 0x5019 R/W 0x0000 McBSP Transmit Channel Enable Register Partition E XCERF 0x501A R/W 0x0000 McBSP Transmit Channel Enable Register Partition F RCERG 0x501B R/W 0x0000 McBSP Receive Channel Enable Register Partition G RCERH 0x501C R/W 0x0000 McBSP Receive Channel Enable Register Partition H XCERG 0x501D R/W 0x0000 McBSP Transmit Channel Enable Register Partition G XCERH 0x501E R/W 0x0000 McBSP Transmit Channel Enable Register Partition H MFFINT 0x5023 R/W 0x0000 McBSP Interrupt Enable Register Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 107 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.14.1 Multichannel Buffered Serial Port (McBSP) Electrical Data/Timing 6.14.1.1 McBSP Transmit and Receive Timing Table 6-36. McBSP Timing Requirements (1) (2) NO. MIN McBSP module clock (CLKG, CLKX, CLKR) range MAX UNIT 25 (3) MHz 1 McBSP module cycle time (CLKG, CLKX, CLKR) range kHz 40 ns 1 ms ADVANCE INFORMATION M11 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P M12 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P–7 M13 tr(CKRX) Rise time, CLKR/X CLKR/X ext 7 ns M14 tf(CKRX) Fall time, CLKR/X CLKR/X ext 7 ns M15 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR int 18 CLKR ext 2 M16 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR int 0 CLKR ext 6 CLKR int 18 CLKR ext 2 CLKR int 0 M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR low M18 th(CKRL-DRV) Hold time, DR valid after CLKR low M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low M20 (1) (2) (3) 108 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKR ext 6 CLKX int 18 CLKX ext 2 CLKX int 0 CLKX ext 6 ns ns ns ns ns ns ns ns Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG/(1 + CLKGDV). CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed. Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer speed limit (25 MHz). Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-37. McBSP Switching Characteristics (1) (2) PARAMETER MIN MAX UNIT M1 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P M2 tw(CKRXH) Pulse duration, CLKR/X high CLKR/X int D – 5 (3) D + 5 (3) ns ns M3 tw(CKRXL) Pulse duration, CLKR/X low CLKR/X int C – 5 (3) C + 5 (3) ns M4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int 0 4 ns CLKR ext 3 27 CLKX int 0 4 CLKX ext 3 27 M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid M6 tdis(CKXH-DXHZ) Disable time, CLKX high to DX high impedance following last data bit CLKX int 8 CLKX ext 14 Delay time, CLKX high to DX valid. CLKX int 9 This applies to all bits except the first bit transmitted. CLKX ext 28 Delay time, CLKX high to DX valid CLKX int 8 CLKX ext 14 M7 M8 M9 M10 td(CKXH-DXV) ten(CKXH-DX) td(FXH-DXV) ten(FXH-DX) Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 Enable time, CLKX high to DX driven DXENA = 0 Only applies to first bit transmitted when in Data Delay 1 or 2 (XDATDLY=01b or 10b) modes DXENA = 1 Delay time, FSX high to DX valid DXENA = 0 Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode. DXENA = 1 Enable time, FSX high to DX driven DXENA = 0 Only applies to first bit transmitted when in Data Delay 0 (XDATDLY=00b) mode (1) (2) (3) DXENA = 0 DXENA = 1 CLKX int P+8 CLKX ext P + 14 CLKX int 0 CLKX ext 6 CLKX int P CLKX ext P+6 8 FSX ext 14 FSX int P+8 FSX ext P + 14 0 FSX ext 6 FSX int P FSX ext P+6 ns ns ns FSX int FSX int ns ADVANCE INFORMATION NO. ns ns Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. 2P = 1/CLKG in ns. C = CLKRX low pulse width = P D = CLKRX high pulse width = P Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 109 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com M1, M11 M2, M12 M13 M3, M12 CLKR M4 M4 M14 FSR (int) M15 M16 FSR (ext) M18 M17 DR (RDATDLY=00b) Bit (n−1) (n−2) (n−3) M17 (n−4) M18 DR (RDATDLY=01b) Bit (n−1) (n−2) ADVANCE INFORMATION M17 (n−3) M18 DR (RDATDLY=10b) Bit (n−1) (n−2) Figure 6-31. McBSP Receive Timing M1, M11 M2, M12 M13 M3, M12 M14 CLKX M5 M5 FSX (int) M19 M20 FSX (ext) M9 M7 M10 DX (XDATDLY=00b) Bit 0 Bit (n−1) (n−2) (n−3) (n−4) (n−2) (n−3) M7 M8 DX (XDATDLY=01b) Bit (n−1) Bit 0 M7 M6 DX (XDATDLY=10b) M8 Bit 0 Bit (n−1) (n−2) Figure 6-32. McBSP Transmit Timing 110 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.14.1.2 McBSP as SPI Master or Slave Timing Table 6-38. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) NO. M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low M31 th(CKXL-DRV) Hold time, DR valid after CLKX low M32 tsu(BFXL-CKXH) Setup time, FSX low before CLKX high M33 (1) tc(CKX) Cycle time, CLKX MASTER SLAVE MIN MIN MAX MAX UNIT 30 8P – 10 ns 1 8P – 10 ns 8P + 10 ns 16P ns 2P (1) 2P = 1/CLKG Table 6-39. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) (1) MASTER PARAMETER MIN SLAVE MAX MIN MAX UNIT M24 th(CKXL-FXL) Hold time, FSX low after CLKX low 2P (1) M25 td(FXL-CKXH) Delay time, FSX low to CLKX high P M28 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 6 6P + 6 ns M29 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns ns ns 2P = 1/CLKG For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns. M32 LSB M33 MSB CLKX M25 M24 FSX M28 DX M29 Bit 0 Bit(n-1) M30 DR Bit 0 (n-2) (n-3) (n-4) M31 Bit(n-1) (n-2) (n-3) (n-4) Figure 6-33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 111 ADVANCE INFORMATION NO. TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-40. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) MASTER NO. MIN M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high M40 th(CKXH-DRV) Hold time, DR valid after CLKX high M41 tsu(FXL-CKXH) Setup time, FSX low before CLKX high M42 tc(CKX) Cycle time, CLKX (1) SLAVE MAX MIN MAX UNIT 30 8P – 10 ns 1 8P – 10 ns 16P + 10 ns 16P ns 2P (1) 2P = 1/CLKG Table 6-41. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) NO. MASTER PARAMETER M34 th(CKXL-FXL) MIN Hold time, FSX low after CLKX low P (1) SLAVE MAX MIN MAX UNIT ns ADVANCE INFORMATION M35 td(FXL-CKXH) Delay time, FSX low to CLKX high 2P M37 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low P+6 7P + 6 ns M38 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) ns 2P = 1/CLKG For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With a maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16; that is, 4.6875 MHz and P = 13.3 ns. LSB M42 MSB M41 CLKX M34 M35 FSX M37 DX M38 Bit 0 Bit(n-1) M39 DR Bit 0 (n-2) (n-3) (n-4) M40 Bit(n-1) (n-2) (n-3) (n-4) Figure 6-34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 112 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-42. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) NO. M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high M50 th(CKXH-DRV) Hold time, DR valid after CLKX high M51 tsu(FXL-CKXL) Setup time, FSX low before CLKX low M52 tc(CKX) Cycle time, CLKX (1) MASTER SLAVE MIN MIN MAX MAX UNIT 30 8P – 10 ns 1 8P – 10 ns 8P + 10 ns 16P ns 2P (1) 2P = 1/CLKG Table 6-43. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) PARAMETER MASTER SLAVE MIN MIN MAX MAX 2P (1) UNIT M43 th(CKXH-FXL) Hold time, FSX low after CLKX high M44 td(FXL-CKXL) Delay time, FSX low to CLKX low P M47 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 6 6P + 6 ns M48 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) ns ns 2P = 1/CLKG For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16; that is, 4.6875 MHz and P = 13.3 ns. M51 LSB M52 MSB CLKX M43 M44 FSX M47 DX M48 Bit 0 Bit(n-1) M49 DR Bit 0 (n-2) (n-3) (n-4) M50 Bit(n-1) (n-2) (n-3) (n-4) Figure 6-35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 113 ADVANCE INFORMATION NO. TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-44. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) MASTER NO. MIN M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low M59 th(CKXL-DRV) Hold time, DR valid after CLKX low M60 tsu(FXL-CKXL) Setup time, FSX low before CLKX low M61 tc(CKX) Cycle time, CLKX (1) SLAVE MAX MIN MAX UNIT 30 8P – 10 ns 1 8P – 10 ns 16P + 10 ns 16P ns 2P (1) 2P = 1/CLKG Table 6-45. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1) NO. MASTER PARAMETER M53 th(CKXH-FXL) MIN Hold time, FSX low after CLKX high SLAVE MAX MIN MAX P UNIT ns (1) ADVANCE INFORMATION M54 td(FXL-CKXL) Delay time, FSX low to CLKX low 2P M56 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high P+6 7P + 6 ns M57 td(FXL-DXV) Delay time, FSX low to DX valid 6 4P + 6 ns (1) ns 2P = 1/CLKG For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns. M60 LSB M61 MSB CLKX M53 M54 FSX M56 DX M55 M57 Bit 0 Bit(n-1) M58 DR Bit 0 (n-2) (n-3) (n-4) M59 Bit(n-1) (n-2) (n-3) (n-4) Figure 6-36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 114 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 The CAN module (eCAN-A) has the following features: • Fully compliant with CAN protocol, version 2.0B • Supports data rates up to 1 Mbps • Thirty-two mailboxes, each with the following properties: – Configurable as receive or transmit – Configurable with standard or extended identifier – Has a programmable receive mask – Supports data and remote frame – Composed of 0 to 8 bytes of data – Uses a 32-bit time stamp on receive and transmit message – Protects against reception of new message – Holds the dynamically programmable priority of transmit message – Employs a programmable interrupt scheme with two interrupt levels – Employs a programmable alarm on transmission or reception time-out • Low-power mode • Programmable wake-up on bus activity • Automatic reply to a remote request message • Automatic retransmission of a frame in case of loss of arbitration or error • 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16) • Self-test mode – Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit. NOTE For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 9.375 kbps. The F2806x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 115 ADVANCE INFORMATION 6.15 Enhanced Controller Area Network (eCAN) Module TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 eCAN0INT eCAN1INT www.ti.com Controls Address Data Enhanced CAN Controller 32 Message Controller Mailbox RAM (512 Bytes) Memory Management Unit 32-Message Mailbox of 4 x 32-Bit Words 32 CPU Interface, Receive Control Unit, Timer Management Unit 32 eCAN Memory (512 Bytes) Registers and Message Objects Control 32 eCAN Protocol Kernel Receive Buffer ADVANCE INFORMATION Transmit Buffer Control Buffer Status Buffer SN65HVD23x 3.3-V CAN Transceiver CAN Bus Figure 6-37. eCAN Block Diagram and Interface Circuit Table 6-46. 3.3-V eCAN Transceivers PART NUMBER SUPPLY VOLTAGE LOW-POWER MODE SLOPE CONTROL VREF OTHER TA SN65HVD230 3.3 V Standby Adjustable Yes – –40°C to 85°C SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C SN65HVD231 3.3 V Sleep Adjustable Yes – –40°C to 85°C SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C SN65HVD232 3.3 V None None None – –40°C to 85°C SN65HVD232Q 3.3 V None None None – –40°C to 125°C SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback –40°C to 125°C SN65HVD234 3.3 V Standby and Sleep Adjustable None – –40°C to 125°C SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback –40°C to 125°C ISO1050 3–5.5 V None None None Built-in Isolation Low Prop Delay Thermal Shutdown Failsafe Operation Dominant Time-Out –55°C to 105°C 116 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 eCAN-A Control and Status Registers Mailbox Enable - CANME Mailbox Direction - CANMD Transmission Request Set - CANTRS Transmission Request Reset - CANTRR Transmission Acknowledge - CANTA Abort Acknowledge - CANAA eCAN-A Memory (512 Bytes) 6000h Received Message Pending - CANRMP Control and Status Registers 603Fh 6040h 607Fh 6080h 60BFh 60C0h 60FFh Received Message Lost - CANRML Remote Frame Pending - CANRFP Local Acceptance Masks (LAM) (32 x 32-Bit RAM) Global Acceptance Mask - CANGAM Message Object Time Stamps (MOTS) (32 x 32-Bit RAM) Bit-Timing Configuration - CANBTC Message Object Time-Out (MOTO) (32 x 32-Bit RAM) Transmit Error Counter - CANTEC Master Control - CANMC Error and Status - CANES Receive Error Counter - CANREC ADVANCE INFORMATION Global Interrupt Flag 0 - CANGIF0 Global Interrupt Mask - CANGIM Global Interrupt Flag 1 - CANGIF1 eCAN-A Memory RAM (512 Bytes) 6100h-6107h Mailbox 0 6108h-610Fh Mailbox 1 6110h-6117h Mailbox 2 6118h-611Fh Mailbox 3 6120h-6127h Mailbox 4 Mailbox Interrupt Mask - CANMIM Mailbox Interrupt Level - CANMIL Overwrite Protection Control - CANOPC TX I/O Control - CANTIOC RX I/O Control - CANRIOC Time Stamp Counter - CANTSC Time-Out Control - CANTOC Time-Out Status - CANTOS 61E0h-61E7h Mailbox 28 61E8h-61EFh Mailbox 29 61F0h-61F7h Mailbox 30 61F8h-61FFh Mailbox 31 Reserved Message Mailbox (16 Bytes) 61E8h-61E9h Message Identifier - MSGID 61EAh-61EBh Message Control - MSGCTRL 61ECh-61EDh Message Data Low - MDL 61EEh-61EFh Message Data High - MDH Figure 6-38. eCAN-A Memory Map NOTE If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 117 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com The CAN registers listed in Table 6-47 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. Table 6-47. CAN Register Map (1) REGISTER NAME eCAN-A ADDRESS SIZE (x32) ADVANCE INFORMATION (1) 118 DESCRIPTION CANME 0x6000 1 Mailbox enable CANMD 0x6002 1 Mailbox direction CANTRS 0x6004 1 Transmit request set CANTRR 0x6006 1 Transmit request reset CANTA 0x6008 1 Transmission acknowledge CANAA 0x600A 1 Abort acknowledge CANRMP 0x600C 1 Receive message pending CANRML 0x600E 1 Receive message lost CANRFP 0x6010 1 Remote frame pending CANGAM 0x6012 1 Global acceptance mask CANMC 0x6014 1 Master control CANBTC 0x6016 1 Bit-timing configuration CANES 0x6018 1 Error and status CANTEC 0x601A 1 Transmit error counter CANREC 0x601C 1 Receive error counter CANGIF0 0x601E 1 Global interrupt flag 0 CANGIM 0x6020 1 Global interrupt mask CANGIF1 0x6022 1 Global interrupt flag 1 CANMIM 0x6024 1 Mailbox interrupt mask CANMIL 0x6026 1 Mailbox interrupt level CANOPC 0x6028 1 Overwrite protection control CANTIOC 0x602A 1 TX I/O control CANRIOC 0x602C 1 RX I/O control CANTSC 0x602E 1 Time stamp counter (Reserved in SCC mode) CANTOC 0x6030 1 Time-out control (Reserved in SCC mode) CANTOS 0x6032 1 Time-out status (Reserved in SCC mode) These registers are mapped to Peripheral Frame 1. Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.16 Inter-Integrated Circuit (I2C) The I2C module has the following features: • Compliance with the Philips Semiconductors I2C-bus specification (version 2.1): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit/receive and receive/transmit mode – Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate) • One 4-word receive FIFO and one 4-word transmit FIFO • One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave • An additional interrupt that can be used by the CPU when in FIFO mode • Module enable/disable capability • Free data format mode Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 119 ADVANCE INFORMATION The device contains one I2C Serial Port. Figure 6-39 shows how the I2C peripheral module interfaces within the device. TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com I2C Module I2CXSR I2CDXR TX FIFO FIFO Interrupt to CPU/PIE SDA RX FIFO Peripheral Bus I2CRSR SCL I2CDRR Clock Synchronizer Control/Status Registers CPU ADVANCE INFORMATION Prescaler Noise Filters Interrupt to CPU/PIE I2C INT Arbitrator A. B. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the SYSCLKOUT rate. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off. Figure 6-39. I2C Peripheral Module Interfaces The registers in Table 6-48 configure and control the I2C port operation. Table 6-48. I2C-A Registers 120 NAME ADDRESS EALLOW PROTECTED I2COAR 0x7900 No I2C own address register I2CIER 0x7901 No I2C interrupt enable register I2CSTR 0x7902 No I2C status register DESCRIPTION I2CCLKL 0x7903 No I2C clock low-time divider register I2CCLKH 0x7904 No I2C clock high-time divider register I2CCNT 0x7905 No I2C data count register I2CDRR 0x7906 No I2C data receive register I2CSAR 0x7907 No I2C slave address register I2CDXR 0x7908 No I2C data transmit register I2CMDR 0x7909 No I2C mode register I2CISRC 0x790A No I2C interrupt source register I2CPSC 0x790C No I2C prescaler register I2CFFTX 0x7920 No I2C FIFO transmit register I2CFFRX 0x7921 No I2C FIFO receive register I2CRSR – No I2C receive shift register (not accessible to the CPU) I2CXSR – No I2C transmit shift register (not accessible to the CPU) Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.16.1 Inter-Integrated Circuit (I2C) Electrical Data/Timing Table 6-49. I2C Timing MIN I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately MAX UNIT 400 kHz fSCL SCL clock frequency vil Low level input voltage Vih High level input voltage Vhys Input hysteresis Vol Low level output voltage 3 mA sink current tLOW Low period of SCL clock I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately 1.3 μs tHIGH High period of SCL clock I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately 0.6 μs lI Input current with an input voltage between 0.1 VDDIO and 0.9 VDDIO MAX 0.3 VDDIO V 0.05 VDDIO V 0 –10 0.4 10 Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated V 0.7 VDDIO V ADVANCE INFORMATION TEST CONDITIONS μA 121 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.17 Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1/2/3/4/5/6/7/8) The devices contain up to eight enhanced PWM Modules (ePWM). Figure 6-40 shows a block diagram of multiple ePWM modules. Figure 6-41 shows the signal interconnections with the ePWM. Table 6-50 and Table 6-51 show the complete ePWM register set per module. EPWMSYNCI EPWM1SYNCI EPWM1B EPWM1TZINT EPWM1 Module EPWM1INT EPWM2TZINT PIE TZ1 to TZ3 EQEP1ERR TZ4 EPWM2INT CLOCKFAIL TZ5 EPWMxTZINT EMUSTOP TZ6 EPWMxINT (A) EPWM1ENCLK TBCLKSYNC eCAPI EPWM1SYNCO EPWM1SYNCO ADVANCE INFORMATION EPWM2SYNCI COMPOUT1 COMPOUT2 TZ1 to TZ3 EPWM2B EPWM2 Module COMP TZ4 TZ5 TZ6 EQEP1ERR (A) EPWM1A H R P W M CLOCKFAIL EMUSTOP EPWM2ENCLK TBCLKSYNC EPWM2A EPWMxA G P I O ADC Peripheral Bus EPWM2SYNCO SOCA1 SOCB1 SOCA2 SOCB2 EPWMxSYNCI SOCAx EPWMx Module SOCBx M U X EPWMxB TZ1 to TZ3 TZ4 TZ5 TZ6 EQEP1ERR (A) EQEP1ERR CLOCKFAIL EMUSTOP eQEP1 EPWMxENCLK TBCLKSYNC System Control C28x CPU A. SOCA1 SOCA2 SPCAx Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output) ADCSOCAO SOCB1 SOCB2 SPCBx Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output) ADCSOCBO This signal exists only on devices with an eQEP1 module. Figure 6-40. ePWM 122 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-50. ePWM1–ePWM4 Control and Status Registers ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / #SHADOW TBCTL 0x6800 0x6840 0x6880 0x68C0 1/0 Time Base Control Register TBSTS 0x6801 0x6841 0x6881 0x68C1 1/0 Time Base Status Register TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1/0 Time Base Phase HRPWM Register TBPHS 0x6803 0x6843 0x6883 0x68C3 1/0 Time Base Phase Register TBCTR 0x6804 0x6844 0x6884 0x68C4 1/0 Time Base Counter Register TBPRD 0x6805 0x6845 0x6885 0x68C5 1/1 Time Base Period Register Set TBPRDHR 0x6806 0x6846 0x6886 0x68C6 1/1 Time Base Period High Resolution Register (1) CMPCTL 0x6807 0x6847 0x6887 0x68C7 1/0 Counter Compare Control Register CMPAHR 0x6808 0x6848 0x6888 0x68C8 1/1 Time Base Compare A HRPWM Register CMPA 0x6809 0x6849 0x6889 0x68C9 1/1 Counter Compare A Register Set CMPB 0x680A 0x684A 0x688A 0x68CA 1/1 Counter Compare B Register Set DESCRIPTION AQCTLA 0x680B 0x684B 0x688B 0x68CB 1/0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 0x68CC 1/0 Action Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 0x68CD 1/0 Action Qualifier Software Force Register AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1/1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x680F 0x684F 0x688F 0x68CF 1/1 Dead-Band Generator Control Register DBRED 0x6810 0x6850 0x6890 0x68D0 1/0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 0x68D1 1/0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 0x68D2 1/0 Trip Zone Select Register (1) TZDCSEL 0x6813 0x6853 0x6893 0x68D3 1/0 Trip Zone Digital Compare Register TZCTL 0x6814 0x6854 0x6894 0x68D4 1/0 Trip Zone Control Register (1) TZEINT 0x6815 0x6855 0x6895 0x68D5 1/0 Trip Zone Enable Interrupt Register (1) TZFLG 0x6816 0x6856 0x6896 0x68D6 1/0 Trip Zone Flag Register TZCLR 0x6817 0x6857 0x6897 0x68D7 1/0 Trip Zone Clear Register (1) TZFRC 0x6818 0x6858 0x6898 0x68D8 1/0 Trip Zone Force Register (1) (1) ETSEL 0x6819 0x6859 0x6899 0x68D9 1/0 Event Trigger Selection Register ETPS 0x681A 0x685A 0x689A 0x68DA 1/0 Event Trigger Prescale Register ETFLG 0x681B 0x685B 0x689B 0x68DB 1/0 Event Trigger Flag Register ETCLR 0x681C 0x685C 0x689C 0x68DC 1/0 Event Trigger Clear Register ETFRC 0x681D 0x685D 0x689D 0x68DD 1/0 Event Trigger Force Register PCCTL 0x681E 0x685E 0x689E 0x68DE 1/0 PWM Chopper Control Register HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1/0 HRPWM Configuration Register (1) (1) ADVANCE INFORMATION NAME Registers that are EALLOW protected. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 123 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-50. ePWM1–ePWM4 Control and Status Registers (continued) NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / #SHADOW DESCRIPTION HRMSTEP 0x6826 - - - 1/0 HRPWM MEP Step Register HRPCTL 0x6828 0x6868 0x68A8 0x68E8 1/0 High resolution Period Control Register (1) (2) TBPRDHRM 0x682A 0x686A 0x68AA 0x68EA 1/W TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1 / W (2) Time Base Period Register Mirror CMPAHRM 0x682C 0x686C 0x68AC 0x68EC 1 / W (2) Compare A HRPWM Register Mirror (2) CMPAM 0x682D 0x686D 0x68AD 0x68ED DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1/W 1/0 Time Base Period HRPWM Register Mirror Compare A Register Mirror Digital Compare Trip Select Register (1) ADVANCE INFORMATION (1) DCACTL 0x6831 0x6871 0x68B1 0x68F1 1/0 Digital Compare A Control Register DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1/0 Digital Compare B Control Register (1) DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1/0 Digital Compare Filter Control Register (1) DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1/0 Digital Compare Capture Control Register (1) DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1/1 Digital Compare Filter Offset Register DCFOFFSETCNT 0x6836 0x6876 0x68B6 0x68F6 1/0 Digital Compare Filter Offset Counter Register DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1/0 Digital Compare Filter Window Register DCFWINDOWCNT 0x6838 0x6878 0x68B8 0x68F8 1/0 Digital Compare Filter Window Counter Register DCCAP 0x6839 0x6879 0x68B9 0x68F9 1/1 Digital Compare Counter Capture Register (2) W = Write to shadow register Table 6-51. ePWM5–ePWM8 Control and Status Registers ePWM5 ePWM6 ePWM7 ePWM8 SIZE (x16) / #SHADOW TBCTL 0x6900 0x6940 0x6980 0x69C0 1/0 Time Base Control Register TBSTS 0x6901 0x6941 0x6981 0x69C1 1/0 Time Base Status Register TBPHSHR 0x6902 0x6942 0x6982 0x69C2 1/0 Time Base Phase HRPWM Register TBPHS 0x6903 0x6943 0x6983 0x69C3 1/0 Time Base Phase Register TBCTR 0x6904 0x6944 0x6984 0x69C4 1/0 Time Base Counter Register TBPRD 0x6905 0x6945 0x6985 0x69C5 1/1 Time Base Period Register Set TBPRDHR 0x6906 0x6946 0x6986 0x69C6 1/1 Time Base Period High Resolution Register (1) CMPCTL 0x6907 0x6947 0x6987 0x69C7 1/0 Counter Compare Control Register CMPAHR 0x6908 0x6948 0x6988 0x69C8 1/1 Time Base Compare A HRPWM Register CMPA 0x6909 0x6949 0x6989 0x69C9 1/1 Counter Compare A Register Set CMPB 0x690A 0x694A 0x698A 0x69CA 1/1 Counter Compare B Register Set NAME (1) 124 DESCRIPTION Registers that are EALLOW protected. Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-51. ePWM5–ePWM8 Control and Status Registers (continued) NAME ePWM5 ePWM6 ePWM7 ePWM8 SIZE (x16) / #SHADOW DESCRIPTION 0x690B 0x694B 0x698B 0x69CB 1/0 Action Qualifier Control Register For Output A AQCTLB 0x690C 0x694C 0x698C 0x69CC 1/0 Action Qualifier Control Register For Output B AQSFRC 0x690D 0x694D 0x698D 0x69CD 1/0 Action Qualifier Software Force Register AQCSFRC 0x690E 0x694E 0x698E 0x69CE 1/1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x690F 0x694F 0x698F 0x69CF 1/1 Dead-Band Generator Control Register DBRED 0x6910 0x6950 0x6990 0x69D0 1/0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6911 0x6951 0x6991 0x69D1 1/0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6912 0x6952 0x6992 0x69D2 1/0 Trip Zone Select Register (1) TZDCSEL 0x6913 0x6953 0x6993 0x69D3 1/0 Trip Zone Digital Compare Register TZCTL 0x6914 0x6954 0x6994 0x69D4 1/0 Trip Zone Control Register (1) TZEINT 0x6915 0x6955 0x6995 0x69D5 1/0 Trip Zone Enable Interrupt Register (1) TZFLG 0x6916 0x6956 0x6996 0x69D6 1/0 Trip Zone Flag Register TZCLR 0x6917 0x6957 0x6997 0x69D7 1/0 Trip Zone Clear Register (1) TZFRC 0x6918 0x6958 0x6998 0x69D8 1/0 Trip Zone Force Register (2) ETSEL 0x6919 0x6959 0x6999 0x69D9 1/0 Event Trigger Selection Register ETPS 0x691A 0x695A 0x699A 0x69DA 1/0 Event Trigger Prescale Register ETFLG 0x691B 0x695B 0x699B 0x69DB 1/0 Event Trigger Flag Register ETCLR 0x691C 0x695C 0x699C 0x69DC 1/0 Event Trigger Clear Register ETFRC 0x691D 0x695D 0x699D 0x69DD 1/0 Event Trigger Force Register PCCTL 0x691E 0x695E 0x699E 0x69DE 1/0 PWM Chopper Control Register HRCNFG 0x6920 0x6960 0x69A0 0x69E0 1/0 HRPWM Configuration Register (2) - - - - 1/0 HRPWM MEP Step Register 0x6928 0x6968 0x69A8 0x69E8 1/0 High resolution Period Control Register (2) HRMSTEP HRPCTL (3) TBPRDHRM 0x692A 0x696A 0x69AA 0x69EA 1/W TBPRDM 0x692B 0x696B 0x69AB 0x69EB 1 / W (3) (3) (1) Time Base Period HRPWM Register Mirror Time Base Period Register Mirror CMPAHRM 0x692C 0x696C 0x69AC 0x69EC 1/W CMPAM 0x692D 0x696D 0x69AD 0x69ED 1 / W (3) DCTRIPSEL 0x6930 0x6970 0x69B0 0x69F0 1/0 Digital Compare Trip Select Register DCACTL 0x6931 0x6971 0x69B1 0x69F1 1/0 Digital Compare A Control Register (2) DCBCTL 0x6932 0x6972 0x69B2 0x69F2 1/0 Digital Compare B Control Register (2) DCFCTL 0x6933 0x6973 0x69B3 0x69F3 1/0 Digital Compare Filter Control Register (2) (2) (3) ADVANCE INFORMATION AQCTLA Compare A HRPWM Register Mirror Compare A Register Mirror (2) Registers that are EALLOW protected. W = Write to shadow register Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 125 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-51. ePWM5–ePWM8 Control and Status Registers (continued) ePWM5 ePWM6 ePWM7 ePWM8 SIZE (x16) / #SHADOW DCCAPCT 0x6934 0x6974 0x69B4 0x69F4 1/0 Digital Compare Capture Control Register (2) DCFOFFSET 0x6935 0x6975 0x69B5 0x69F5 1/1 Digital Compare Filter Offset Register DCFOFFSETCNT 0x6936 0x6976 0x69B6 0x69F6 1/0 Digital Compare Filter Offset Counter Register DCFWINDOW 0x6937 0x6977 0x69B7 0x69F7 1/0 Digital Compare Filter Window Register DCFWINDOWCNT 0x6938 0x6978 0x69B8 0x69F8 1/0 Digital Compare Filter Window Counter Register DCCAP 0x6939 0x6979 0x69B9 0x69F9 1/1 Digital Compare Counter Capture Register NAME DESCRIPTION ADVANCE INFORMATION 126 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Time-Base (TB) CTR=ZERO TBPRD Shadow (24) TBPRD Active (24) Sync In/Out Select Mux CTR=CMPB TBPRDHR (8) Disabled EPWMxSYNCO 8 CTR=PRD TBCTL[SYNCOSEL] Counter Up/Down (16 Bit) TBCTL[SWFSYNC] (Software Forced Sync) CTR=ZERO TCBNT Active (16) CTR_Dir CTR=PRD CTR=ZERO CTR=PRD or ZERO CTR=CMPA TBPHSHR (8) 16 8 TBPHS Active (24) Phase Control CTR=CMPB CTR_Dir DCAEVT1.soc DCBEVT1.soc CTR=CMPA EPWMxSYNCI DCAEVT1.sync DCBEVT1.sync (A) EPWMxINT Event Trigger and Interrupt (ET) EPWMxSOCA EPWMxSOCB EPWMxSOCA ADC (A) EPWMxSOCB ADVANCE INFORMATION TBCTL[PHSEN] Action Qualifier (AQ) CMPAHR (8) 16 High-resolution PWM (HRPWM) CMPA Active (24) CMPA Shadow (24) Dead Band (DB) CTR=CMPB 16 EPWMxA EPWMA PWM Chopper (PC) Trip Zone (TZ) EPWMxB EPWMB EPWMxTZINT CMPB Active (16) TZ1 to TZ3 CMPB Shadow (16) CTR=ZERO DCAEVT1.inter DCBEVT1.inter DCAEVT2.inter DCBEVT2.inter EMUSTOP CLOCKFAIL EQEP1ERR (B) DCAEVT1.force DCAEVT2.force DCBEVT1.force DCBEVT2.force A. B. (A) (A) (A) (A) These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ signals. This signal exists only on devices with an eQEP1 module. Figure 6-41. ePWM Sub-Modules Showing Critical Internal Signal Interconnections Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 127 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.17.1 Enhanced Pulse Width Modulator (ePWM) Electrical Data/Timing PWM refers to PWM outputs on ePWM1–8. Table 6-52 shows the PWM timing requirements and Table 6-53, switching characteristics. Table 6-52. ePWM Timing Requirements (1) TEST CONDITIONS tw(SYCIN) Sync input pulse width MIN Asynchronous (1) UNIT cycles 2tc(SCO) cycles 1tc(SCO) + tw(IQSW) cycles Synchronous With input qualifier MAX 2tc(SCO) For an explanation of the input qualifier parameters, see Table 6-67. Table 6-53. ePWM Switching Characteristics PARAMETER ADVANCE INFORMATION tw(PWM) Pulse duration, PWMx output high/low tw(SYNCOUT) Sync output pulse width td(PWM)tza Delay time, trip input active to PWM forced high Delay time, trip input active to PWM forced low td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z TEST CONDITIONS MIN MAX 33.33 UNIT ns 8tc(SCO) cycles no pin load 25 ns 20 ns 6.17.2 Trip-Zone Input Timing Table 6-54. Trip-Zone Input Timing Requirements (1) MIN tw(TZ) Pulse duration, TZx input low UNIT Asynchronous 1tc(SCO) cycles Synchronous 2tc(SCO) cycles 1tc(SCO) + tw(IQSW) cycles With input qualifier (1) MAX For an explanation of the input qualifier parameters, see Table 6-67. XCLKOUT(A) tw(TZ) TZ td(TZ-PWM)HZ PWM(B) C. D. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6 PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Figure 6-42. PWM Hi-Z Characteristics 128 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.18 High-Resolution PWM (HRPWM) This module combines multiple delay lines in a single module and a simplified calibration system by using a dedicated calibration delay line. For each ePWM module there is one HR delay line. The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are: • Significantly extends the time resolution capabilities of conventionally derived digital PWM • This capability can be utilized in both single edge (duty cycle and phase-shift control) as well as dual edge control for frequency/period modulation. • Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase registers of the ePWM module. • HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA output). EPWMxB output has conventional PWM capabilities. NOTE NOTE When dual-edge high-resolution is enabled (high-resolution period mode), the PWMxB output is not available for use. 6.18.1 High-Resolution PWM (HRPWM) Electrical Data/Timing Table 6-55 shows the high-resolution PWM switching characteristics. Table 6-55. High-Resolution PWM Characteristics (1) MIN Micro Edge Positioning (MEP) step size (2) (1) (2) TYP MAX UNIT 150 310 ps The HRPWM operates at a minimum SYSCLKOUT frequency of 60 MHz. Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase with low voltage and high temperature and decrease with voltage and cold temperature. Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per SYSCLKOUT period dynamically while the HRPWM is in operation. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 129 ADVANCE INFORMATION The minimum SYSCLKOUT frequency allowed for HRPWM is 60 MHz. TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.19 Enhanced Capture Module (eCAP1) SYNC The device contains an enhanced capture (eCAP) module. Figure 6-43 shows a functional block diagram of a module. SYNCIn SYNCOut CTRPHS (phase register−32 bit) TSCTR (counter−32 bit) APWM mode OVF RST CTR_OVF CTR [0−31] Delta−mode PWM compare logic PRD [0−31] CMP [0−31] 32 CTR=PRD CTR [0−31] CTR=CMP 32 ADVANCE INFORMATION 32 CAP1 (APRD active) APRD shadow 32 32 LD LD1 MODE SELECT PRD [0−31] Polarity select 32 CMP [0−31] CAP2 (ACMP active) 32 LD LD2 32 CAP3 (APRD shadow) LD 32 CAP4 (ACMP shadow) LD Polarity select Event qualifier ACMP shadow eCAPx Event Pre-scale Polarity select LD3 LD4 Polarity select 4 Capture events 4 CEVT[1:4] to PIE Interrupt Trigger and Flag control CTR_OVF Continuous / Oneshot Capture Control CTR=PRD CTR=CMP Figure 6-43. eCAP Functional Block Diagram The eCAP module is clocked at the SYSCLKOUT rate. The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off. 130 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Table 6-56. eCAP Control and Status Registers eCAP1 eCAP2 eCAP3 SIZE (x16) 0x6A00 0x6A20 0x6A40 2 Time-Stamp Counter DESCRIPTION CTRPHS 0x6A02 0x6A22 0x6A42 2 Counter Phase Offset Value Register CAP1 0x6A04 0x6A24 0x6A44 2 Capture 1 Register CAP2 0x6A06 0x6A26 0x6A46 2 Capture 2 Register CAP3 0x6A08 0x6A28 0x6A48 2 Capture 3 Register CAP4 0x6A0A 0x6A2A 0x6A4A 2 Capture 4 Register Reserved 0x6A0C – 0x6A12 0x6A2C – 0x6A32 0x6A4C – 0x6A52 8 Reserved ECCTL1 0x6A14 0x6A34 0x6A54 1 Capture Control Register 1 ECCTL2 0x6A15 0x6A35 0x6A55 1 Capture Control Register 2 ECEINT 0x6A16 0x6A36 0x6A56 1 Capture Interrupt Enable Register ECFLG 0x6A17 0x6A37 0x6A57 1 Capture Interrupt Flag Register ECCLR 0x6A18 0x6A38 0x6A58 1 Capture Interrupt Clear Register ECFRC 0x6A19 0x6A39 0x6A59 1 Capture Interrupt Force Register Reserved 0x6A1A – 0x6A1F 0x6A3A – 0x6A3F 0x6A5A – 0x6A5F 6 Reserved 6.19.1 Enhanced Capture (eCAP) Electrical Data/Timing Table 6-57 shows the eCAP timing requirement and Table 6-58 shows the eCAP switching characteristics. Table 6-57. Enhanced Capture (eCAP) Timing Requirement (1) TEST CONDITIONS tw(CAP) Capture input pulse width MAX UNIT Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles 1tc(SCO) + tw(IQSW) cycles With input qualifier (1) MIN For an explanation of the input qualifier parameters, see Table 6-67. Table 6-58. eCAP Switching Characteristics PARAMETER tw(APWM) Pulse duration, APWMx output high/low TEST CONDITIONS MIN MAX 20 Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated UNIT ns 131 ADVANCE INFORMATION NAME TSCTR TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.20 High-Resolution Capture (HRCAP) Module The High-Resolution Capture (HRCAP) module measures the difference between external pulses with a typical resolution of 300 ps. Uses for the HRCAP include: • Capactive touch applications • High-resolution period and duty cycle measurements of pulse train cycles • Instantaneous speed measurements • Instantaneous frequency measurements • Reading the feedback across an isolation boundary • Distance/sonar measurement and scanning ADVANCE INFORMATION The HRCAP module features include: • Pulse width capture in either non-high-resolution or high-resolution modes • Difference (Delta) mode pulse width capture • Typical high-resolution capture on the order of 300 ps resolution • Interrupt on either falling or rising edge • Continuous mode capture of pulse widths in 2-deep buffer • Calibration logic for precision high-resolution capture • All of the above resources are dedicated to a single input pin • HRCAP calibration software library supplied by TI is used for both calibration and calculating fractional pulse widths The HRCAP module includes one capture channel in addition to a high-resolution calibration block, which connects internally to an HRPWM channel when calibrating. Each HRCAP channel has the following independent key resources: • Dedicated input capture pin • 16-bit HRCAP clock which is either equal to the PLL output frequency (asynchronous to SYSCLKOUT) or equal to the SYSCLKOUT frequency (synchronous to SYSCLKOUT) • High-resolution pulse width capture in a 2-deep buffer HRCAP Calibration Logic EPWMx HRCAPxENCLK EPWMxA HRPWM SYSCLK PLLCLK PIE HRCAPx Module HRCAP Calibration Signal (Internal) GPIO Mux HRCAPxINTn HRCAPx Figure 6-44. HRCAP Functional Block Diagram 132 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.21 Enhanced Quadrature Encoder Modules (eQEP1/2) The device contains up to two enhanced quadrature encoder (eQEP) modules. Table 6-59 provides a summary of the eQEP registers. Table 6-59. eQEP Control and Status Registers eQEP1 ADDRESS eQEP2 ADDRESS eQEP1 SIZE(x16)/ #SHADOW QPOSCNT 0x6B00 0x6B40 2/0 eQEP Position Counter QPOSINIT 0x6B02 0x6B42 2/0 eQEP Initialization Position Count QPOSMAX 0x6B04 0x6B44 2/0 eQEP Maximum Position Count QPOSCMP 0x6B06 0x6B46 2/1 eQEP Position-compare REGISTER DESCRIPTION QPOSILAT 0x6B08 0x6B48 2/0 eQEP Index Position Latch QPOSSLAT 0x6B0A 0x6B4A 2/0 eQEP Strobe Position Latch QPOSLAT 0x6B0C 0x6B4C 2/0 eQEP Position Latch QUTMR 0x6B0E 0x6B4E 2/0 eQEP Unit Timer QUPRD 0x6B10 0x6B50 2/0 eQEP Unit Period Register QWDTMR 0x6B12 0x6B52 1/0 eQEP Watchdog Timer QWDPRD 0x6B13 0x6B53 1/0 eQEP Watchdog Period Register QDECCTL 0x6B14 0x6B54 1/0 eQEP Decoder Control Register QEPCTL 0x6B15 0x6B55 1/0 eQEP Control Register QCAPCTL 0x6B16 0x6B56 1/0 eQEP Capture Control Register QPOSCTL 0x6B17 0x6B57 1/0 eQEP Position-compare Control Register QEINT 0x6B18 0x6B58 1/0 eQEP Interrupt Enable Register QFLG 0x6B19 0x6B59 1/0 eQEP Interrupt Flag Register QCLR 0x6B1A 0x6B5A 1/0 eQEP Interrupt Clear Register QFRC 0x6B1B 0x6B5B 1/0 eQEP Interrupt Force Register QEPSTS 0x6B1C 0x6B5C 1/0 eQEP Status Register QCTMR 0x6B1D 0x6B5D 1/0 eQEP Capture Timer QCPRD 0x6B1E 0x6B5E 1/0 eQEP Capture Period Register QCTMRLAT 0x6B1F 0x6B5F 1/0 eQEP Capture Timer Latch QCPRDLAT 0x6B20 0x6B60 1/0 eQEP Capture Period Latch 0x6B21 – 0x6B3F 0x6B61 – 0x6B7F 31/0 Reserved Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated ADVANCE INFORMATION NAME 133 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Figure 6-45 shows the block diagram of the eQEP module. System Control Registers To CPU EQEPxENCLK Data Bus SYSCLKOUT QCPRD QCAPCTL QCTMR 16 16 16 Quadrature Capture Unit (QCAP) QCTMRLAT ADVANCE INFORMATION QCPRDLAT Registers Used by Multiple Units QUTMR QWDTMR QUPRD QWDPRD 32 16 QEPCTL QEPSTS UTIME QFLG UTOUT QWDOG QDECCTL 16 WDTOUT PIE EQEPxAIN QCLK EQEPxINT 16 QPOSLAT EQEPxIIN QI Position Counter/ Control Unit (PCCU) QS Quadrature Decoder PHE (QDU) PCSOUT QPOSSLAT EQEPxA/XCLK EQEPxBIN QDIR QPOSILAT EQEPxB/XDIR EQEPxIOUT EQEPxIOE GPIO MUX EQEPxSIN EQEPxSOUT EQEPxSOE 32 32 QPOSCNT QPOSCMP EQEPxI EQEPxS 16 QEINT QPOSINIT QFRC QPOSMAX QCLR QPOSCTL Enhanced QEP (eQEP) Peripheral Figure 6-45. eQEP Functional Block Diagram 134 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 6.21.1 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 Enhanced Quadrature Encoder (eQEP) Electrical Data/Timing Table 6-60 shows the eQEP timing requirement and Table 6-61 shows the eQEP switching characteristics. Table 6-60. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1) QEP input period tw(INDEXH) QEP Index Input High time With input qualifier QEP Index Input Low time tw(STROBH) QEP Strobe High time tw(STROBL) QEP Strobe Input Low time cycles 2tc(SCO) cycles 2tc(SCO) +tw(IQSW) cycles 2tc(SCO) cycles 2tc(SCO) + tw(IQSW) cycles 2tc(SCO) cycles 2tc(SCO) + tw(IQSW) cycles 2tc(SCO) cycles 2tc(SCO) +tw(IQSW) cycles Asynchronous/synchronous With input qualifier (1) 2[1tc(SCO) + tw(IQSW)] Asynchronous/synchronous With input qualifier UNIT cycles Asynchronous/synchronous With input qualifier MAX 2tc(SCO) Asynchronous/synchronous With input qualifier tw(INDEXL) MIN Asynchronous/synchronous For an explanation of the input qualifier parameters, see Table 6-67. Table 6-61. eQEP Switching Characteristics PARAMETER TEST CONDITIONS MIN MAX UNIT td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SCO) cycles Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 135 ADVANCE INFORMATION TEST CONDITIONS tw(QEPP) TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.22 JTAG Port On the 2806x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins in Figure 6-46. During emulation/debug, the GPIO function of these pins are not available. If the GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used to clock the device during emulation/debug since this pin will be needed for the TCK function. NOTE In 2806x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in the board design to ensure that the circuitry connected to these pins do not affect the emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should not prevent the emulator from driving (or being driven by) the JTAG pins for successful debug. TRST = 0: JTAG Disabled (GPIO Mode) TRST = 1: JTAG Mode TRST ADVANCE INFORMATION TRST XCLKIN GPIO38_in TCK TCK/GPIO38 GPIO38_out C28x Core GPIO37_in TDO/GPIO37 1 0 TDO GPIO37_out GPIO36_in 1 TMS TMS/GPIO36 GPIO36_out 1 0 GPIO35_in 1 TDI TDI/GPIO35 GPIO35_out 1 0 Figure 6-46. JTAG/GPIO Multiplexing 136 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.23 General-Purpose Input/Output (GPIO) MUX The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability. The device supports 45 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-62 shows the GPIO register mapping. Table 6-62. GPIO Registers NAME ADDRESS SIZE (x16) DESCRIPTION GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31) GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15) GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31) GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15) GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31) GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31) GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31) GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 44) GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 44) GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 44) GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 44) GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 44) AIOMUX1 0x6FB6 2 Analog, I/O mux 1 register (AIO0 to AIO15) AIODIR 0x6FBA 2 Analog, I/O Direction Register (AIO0 to AIO15) ADVANCE INFORMATION GPIO CONTROL REGISTERS (EALLOW PROTECTED) GPIO DATA REGISTERS (NOT EALLOW PROTECTED) GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31) GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31) GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31) GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31) GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 44) GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 44) GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 44) GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle Register (GPIO32 to 44) AIODAT 0x6FD8 2 Analog I/O Data Register (AIO0 to AIO15) AIOSET 0x6FDA 2 Analog I/O Data Set Register (AIO0 to AIO15) AIOCLEAR 0x6FDC 2 Analog I/O Data Clear Register (AIO0 to AIO15) 0x6FDE 2 Analog I/O Data Toggle Register (AIO0 to AIO15) AIOTOGGLE GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED) GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31) GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31) GPIOXINT3SEL 0x6FE2 1 XINT3 GPIO Input Select Register (GPIO0 to 31) GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31) NOTE There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and GPxQSELn registers occurs to when the action is valid. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 137 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-63. GPIOA MUX (1) (2) ADVANCE INFORMATION DEFAULT AT RESET PRIMARY I/O FUNCTION PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 PERIPHERAL SELECTION 3 GPAMUX1 REGISTER BITS (GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 BITS = 11) 1-0 GPIO0 EPWM1A (O) Reserved Reserved 3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O) 5-4 GPIO2 EPWM2A (O) Reserved Reserved 7-6 GPIO3 EPWM2B (O) SPISOMIA (I/O) COMP2OUT (O) 9-8 GPIO4 EPWM3A (O) Reserved Reserved 11-10 GPIO5 EPWM3B (O) SPISIMOA (I/O) ECAP1 (I/O) 13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O) 15-14 GPIO7 EPWM4B (O) SCIRXDA (I) ECAP2 (I/O) 17-16 GPIO8 EPWM5A (O) Reserved ADCSOCAO (O) 19-18 GPIO9 EPWM5B (O) SCITXDB (3) (O) ECAP3 (I/O) 21-20 GPIO10 EPWM6A (O) Reserved ADCSOCBO (O) 23-22 GPIO11 EPWM6B (O) SCIRXDB (3) (I) ECAP1 (I/O) 25-24 GPIO12 TZ1 (I) SCITXDA (O) SPISIMOB (I/O) 27-26 GPIO13 TZ2 (I) Reserved SPISOMIB (I/O) 29-28 GPIO14 TZ3 (I) SCITXDB (3) (O) SPICLKB (I/O) 31-30 GPIO15 ECAP2 (I/O) SCIRXDB (3) (I) SPISTEB (I/O) GPAMUX2 REGISTER BITS (GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11) 1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I) 3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I) 5-4 GPIO18 SPICLKA (I/O) SCITXDB (3) (O) XCLKOUT (O) 7-6 GPIO19/XCLKIN SPISTEA (I/O) SCIRXDB (3) (I) ECAP1 (I/O) 9-8 GPIO20 EQEP1A (I) MDXA (O) COMP1OUT (O) 11-10 GPIO21 EQEP1B (I) MDRA (I) COMP2OUT (O) 13-12 GPIO22 EQEP1S (I/O) MCLKXA (I/O) SCITXDB (3) (O) 15-14 GPIO23 EQEP1I (I/O) MFSXA (I/O) SCIRXDB (3) (I) (1) (2) (3) 138 (3) 17-16 GPIO24 ECAP1 (I/O) EQEP2A (I) SPISIMOB (I/O) 19-18 GPIO25 ECAP2 (I/O) EQEP2B (3) (I) SPISOMIB (I/O) 21-20 GPIO26 ECAP3 (I/O) EQEP2I (3) (I/O) SPICLKB (I/O) EQEP2S (3) 23-22 GPIO27 HRCAP2 (I) 25-24 GPIO28 SCIRXDA (I) SDAA (I/OD) (I/O) SPISTEB (I/O) 27-26 GPIO29 SCITXDA (O) SCLA (I/OD) TZ3 (I) 29-28 GPIO30 CANRXA (I) EQEP2I (3) (I/O) EPWM7A (O) 31-30 GPIO31 CANTXA (O) EQEP2S (3) (I/O) EPWM8A (O) TZ2 (I) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion. I = Input, O = Output, OD = Open Drain The SCI-B and eQEP2 peripherals are not available on the 80-pin PN/PFP package. Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 DEFAULT AT RESET PRIMARY I/O FUNCTION PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 PERIPHERAL SELECTION 3 GPBMUX1 REGISTER BITS (GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11) 1-0 GPIO32 SDAA (I/OD) EPWMSYNCI (I) ADCSOCAO (O) 3-2 GPIO33 SCLA (I/OD) EPWMSYNCO (O) ADCSOCBO (O) 5-4 GPIO34 COMP2OUT (O) Reserved COMP3OUT (O) 7-6 GPIO35 (TDI) Reserved Reserved Reserved 9-8 GPIO36 (TMS) Reserved Reserved Reserved 11-10 GPIO37 (TDO) Reserved Reserved Reserved 13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved 15-14 GPIO39 Reserved Reserved Reserved 17-16 GPIO40 (3) EPWM7A (O) SCITXDB (O) Reserved 19-18 GPIO41 (3) EPWM7B (O) SCIRXDB (I) Reserved 21-20 GPIO42 (3) EPWM8A (O) TZ1 (I) COMP1OUT (O) 23-22 GPIO43 (3) EPWM8B (O) TZ2 (I) COMP2OUT (O) 25-24 GPIO44 (3) MFSRA (I/O) SCIRXDB (I) EPWM7B (O) 27-26 Reserved Reserved Reserved Reserved 29-28 Reserved Reserved Reserved Reserved 31-30 Reserved Reserved Reserved Reserved GPBMUX2 REGISTER BITS (GPBMUX2 BITS = 00) (GPBMUX2 BITS = 01) (GPBMUX2 BITS = 10) (GPBMUX2 BITS = 11) 1-0 Reserved Reserved Reserved Reserved 3-2 Reserved Reserved Reserved Reserved 5-4 GPIO50 (3) EQEP1A (I) MDXA (O) TZ1 (I) 7-6 GPIO51 (3) EQEP1B (I) MDRA (I) TZ2 (I) 9-8 GPIO52 (3) EQEP1S (I/O) MCLKXA (I/O) TZ3 (I) 11-10 GPIO53 (3) EQEP1I (I/O) MFSXA (I/O) Reserved 13-12 GPIO54 (3) SPISIMOA (I/O) EQEP2A (I) HRCAP1 (I) 15-14 GPIO55 (3) SPISOMIA (I/O) EQEP2B (I) HRCAP2 (I) 17-16 GPIO56 (3) SPICLKA (I/O) EQEP2I (I/O) HRCAP3 (I) 19-18 GPIO57 (3) SPISTEA (I/O) EQEP2S (I/O) HRCAP4 (I) 21-20 GPIO58 (3) MCLKRA (I/O) SCITXDB (O) EPWM7A (O) 23-22 Reserved Reserved Reserved Reserved 25-24 Reserved Reserved Reserved Reserved 27-26 Reserved Reserved Reserved Reserved 29-28 Reserved Reserved Reserved Reserved 31-30 Reserved Reserved Reserved Reserved (1) (2) (3) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion. I = Input, O = Output, OD = Open Drain This pin is not available in the 80-pin PN/PFP package. Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 139 ADVANCE INFORMATION Table 6-64. GPIOB MUX (1) (2) TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-65. Analog MUX (1) DEFAULT AT RESET ADVANCE INFORMATION (1) AIOx AND PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 AND PERIPHERAL SELECTION 3 AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x 1-0 ADCINA0 (I) ADCINA0 (I) 3-2 ADCINA1 (I) ADCINA1 (I) 5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I) 7-6 ADCINA3 (I) ADCINA3 (I) 9-8 AIO4 (I/O) ADCINA4 (I), COMP2A (I) 11-10 ADCINA5 (I) ADCINA5 (I) 13-12 AIO6 (I/O) ADCINA6 (I), COMP3A (I) 15-14 ADCINA7 (I) ADCINA7 (I) 17-16 ADCINB0 (I) ADCINB0 (I) 19-18 ADCINB1 (I) ADCINB1 (I) 21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I) 23-22 ADCINB3 (I) ADCINB3 (I) 25-24 AIO12 (I/O) ADCINB4 (I), COMP2B (I) 27-26 ADCINB5 (I) ADCINB5 (I) 29-28 AIO14 (I/O) ADCINB6 (I), COMP3B (I) 31-30 ADCINB7 (I) ADCINB7 (I) I = Input, O = Output The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices: • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT). • Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change. • The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode). • No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral). Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral. 140 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 GPIOXINT1SEL GPIOLMPSEL GPIOXINT2SEL LPMCR0 GPIOXINT3SEL External Interrupt MUX Low P ower Modes Block Asynchronous path PIE GPxDAT (read) GPxPUD Input Qualification Internal Pullup 00 N/C 01 Peripheral 1 Input 10 Peripheral 2 Input 11 Peripheral 3 Input ADVANCE INFORMATION GPxQSEL1/2 GPxCTRL GPxTOGGLE Asynchronous path GPIOx pin GPxCLEAR GPxSET 00 01 GPxDAT (latch) Peripheral 1 Output 10 Peripheral 2 Output 11 Peripheral 3 Output High Impedance Output Control 00 0 = Input, 1 = Output XRS = Default at Reset A. B. C. GPxDIR (latch) 01 Peripheral 1 Output Enable 10 Peripheral 2 Output Enable 11 Peripheral 3 Output Enable GPxMUX1/2 x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected. GPxDAT latch/read are accessed at the same memory location. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the "Systems Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18) for pin-specific variations. Figure 6-47. GPIO Multiplexing Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 141 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.23.1 General-Purpose Input/Output (GPIO) Electrical Data/Timing 6.23.1.1 GPIO Output Timing Table 6-66. General-Purpose Output Switching Characteristics MAX UNIT tr(GPO) Rise time, GPIO switching low to high PARAMETER All GPIOs 13 (1) ns tf(GPO) Fall time, GPIO switching high to low All GPIOs 13 (1) ns tfGPO Toggling frequency (1) MIN 15 MHz Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 6-66 are applicable for a 40-pF load on I/O pins. GPIO tr(GPO) tf(GPO) Figure 6-48. General-Purpose Output Timing ADVANCE INFORMATION 142 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.23.1.2 GPIO Input Timing Table 6-67. General-Purpose Input Timing Requirements MIN tw(SP) Sampling period tw(IQSW) Input qualifier sampling window tw(GPI) (1) (2) (2) UNIT 1tc(SCO) cycles QUALPRD ≠ 0 2tc(SCO) * QUALPRD cycles tw(SP) * (n (1) – 1) cycles 2tc(SCO) cycles tw(IQSW) + tw(SP) + 1tc(SCO) cycles Synchronous mode Pulse duration, GPIO low/high MAX QUALPRD = 0 With input qualifier "n" represents the number of qualification samples as defined by GPxQSELn register. For tw(GPI), pulse width is measured from VIL to VIL for an active-low signal and VIH to VIH for an active-high signal. (A) GPIO Signal GPxQSELn = 1,0 (6 samples) 1 0 0 0 0 0 0 0 1 tw(SP) 0 0 0 1 1 1 1 1 Sampling Window 1 1 1 Sampling Period determined by GPxCTRL[QUALPRD] tw(IQSW) 1 ADVANCE INFORMATION 1 [(SYSCLKOUT cycle * 2 * QUALPRD) * 5 (B) (C) ] SYSCLKOUT QUALPRD = 1 (SYSCLKOUT/2) (D) Output From Qualifier A. B. C. D. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled). The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition. Figure 6-49. Sampling Mode Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 143 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com 6.23.1.3 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT. Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0 Sampling frequency = SYSCLKOUT, if QUALPRD = 0 Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0 In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT. Sampling period = SYSCLKOUT cycle, if QUALPRD = 0 In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register. Case 1: ADVANCE INFORMATION Qualification using 3 samples Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0 Case 2: Qualification using 6 samples Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0 XCLKOUT GPIOxn tw(GPI) Figure 6-50. General-Purpose Input Timing 144 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.23.1.4 Low-Power Mode Wakeup Timing Table 6-68 shows the timing requirements, Table 6-69 shows the switching characteristics, and Figure 6-51 shows the timing diagram for IDLE mode. Table 6-68. IDLE Mode Timing Requirements (1) MIN tw(WAKE-INT) (1) Pulse duration, external wake-up signal Without input qualifier NOM MAX 2tc(SCO) With input qualifier UNIT cycles 5tc(SCO) + tw(IQSW) For an explanation of the input qualifier parameters, see Table 6-67. Table 6-69. IDLE Mode Switching Characteristics (1) TEST CONDITIONS • td(WAKE-IDLE) • • MIN Wake-up from Flash – Flash module in active state Without input qualifier Wake-up from Flash – Flash module in sleep state Without input qualifier Wake-up from SARAM Without input qualifier With input qualifier With input qualifier With input qualifier (1) (2) TYP MAX (2) UNIT cycles 20tc(SCO) cycles 20tc(SCO) + tw(IQSW) 1050tc(SCO) cycles 1050tc(SCO) + tw(IQSW) 20tc(SCO) cycles 20tc(SCO) + tw(IQSW) For an explanation of the input qualifier parameters, see Table 6-67. This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake-up) signal involves additional latency. td(WAKE−IDLE) Address/Data (internal) XCLKOUT tw(WAKE−INT) WAKE INT A. B. (A)(B) WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-51. IDLE Entry and Exit Timing Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 145 ADVANCE INFORMATION PARAMETER Delay time, external wake signal to program execution resume TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-70. STANDBY Mode Timing Requirements tw(WAKE-INT) (1) Pulse duration, external wake-up signal TEST CONDITIONS MIN Without input qualification 3tc(OSCCLK) With input qualification (1) NOM MAX UNIT cycles (2 + QUALSTDBY) * tc(OSCCLK) QUALSTDBY is a 6-bit field in the LPMCR0 register. Table 6-71. STANDBY Mode Switching Characteristics PARAMETER td(IDLE-XCOL) TEST CONDITIONS Delay time, IDLE instruction executed to XCLKOUT low MIN 32tc(SCO) TYP MAX UNIT 45tc(SCO) cycles Delay time, external wake signal to program execution resume (1) • td(WAKE-STBY) • Wake up from flash – Flash module in active state Without input qualifier Wake up from flash – Flash module in sleep state Without input qualifier With input qualifier With input qualifier ADVANCE INFORMATION Without input qualifier • (1) 146 Wake up from SARAM With input qualifier cycles 100tc(SCO) 100tc(SCO) + tw(WAKE-INT) cycles 1125tc(SCO) 1125tc(SCO) + tw(WAKE-INT) 100tc(SCO) 100tc(SCO) + tw(WAKE-INT) cycles cycles This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up signal) involves additional latency. Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 (C) (A) (B) Device Status (F) (D)(E) STANDBY (G) STANDBY Normal Execution Flushing Pipeline Wake-up (H) Signal tw(WAKE-INT) td(WAKE-STBY) X1/X2 or XCLKIN XCLKOUT A. B. C. D. E. F. G. H. ADVANCE INFORMATION td(IDLE−XCOL) IDLE instruction is executed to put the device into STANDBY mode. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off: • 16 cycles, when DIVSEL = 00 or 01 • 32 cycles, when DIVSEL = 10 • 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted. The external wake-up signal is driven active. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses. After a latency period, the STANDBY mode is exited. Normal execution resumes. The device will respond to the interrupt (if enabled). From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-52. STANDBY Entry and Exit Timing Diagram Table 6-72. HALT Mode Timing Requirements MIN NOM MAX UNIT tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) cycles tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles Table 6-73. HALT Mode Switching Characteristics PARAMETER td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low tp PLL lock-up time td(WAKE-HALT) Delay time, PLL lock to program execution resume • Wake up from flash – Flash module in sleep state • Wake up from SARAM MIN 32tc(SCO) TYP MAX UNIT 45tc(SCO) cycles 1 ms 1125tc(SCO) cycles 35tc(SCO) cycles Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 147 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com (C) (A) (F) (B) Device Status HALT Flushing Pipeline (H) (G) (D)(E) HALT PLL Lock-up Time Wake-up Latency Normal Execution (I) GPIOn td(WAKE−HALT ) tw(WAKE-GPIO) tp X1/X2 or XCLKIN Oscillator Start-up Time XCLKOUT td(IDLE−XCOL) ADVANCE INFORMATION A. B. C. D. E. F. G. H. I. IDLE instruction is executed to put the device into HALT mode. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off and the CLKIN to the core is stopped: • 16 cycles, when DIVSEL = 00 or 01 • 32 cycles, when DIVSEL = 10 • 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT mode. This is done by writing to the appropriate bits in the CLKCTL register. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited. Normal operation resumes. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-53. HALT Wake-Up Using GPIOn 148 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 6.24 Flash Timing Table 6-74. Flash/OTP Endurance for T Temperature Material (1) ERASE/PROGRAM TEMPERATURE Nf Flash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) (1) MIN TYP 20000 50000 MAX UNIT cycles 1 write Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 6-75. Flash/OTP Endurance for S Temperature Material (1) ERASE/PROGRAM TEMPERATURE Nf NOTP (1) Flash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) OTP endurance for the array (write cycles) 0°C to 30°C (ambient) MIN TYP 20000 50000 MAX UNIT cycles 1 write Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. ERASE/PROGRAM TEMPERATURE Nf Flash endurance for the array (write/erase cycles) –40°C to 125°C (ambient) NOTP OTP endurance for the array (write cycles) –40°C to 30°C (ambient) (1) MIN TYP 20000 50000 MAX UNIT cycles 1 write Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 6-77. Flash Parameters at 80-MHz SYSCLKOUT TEST CONDITIONS PARAMETER Program Time Erase Time MIN (1) UNIT μs 8K Sector 250 ms 4K Sector 125 ms 8K Sector 2 VDD current consumption during Erase/Program cycle IDDIOP (1) VDDIO current consumption during Erase/Program cycle IDDIOP (1) VDDIO current consumption during Erase/Program cycle (1) MAX 50 16-Bit Word 4K Sector IDDP TYP VREG disabled VREG enabled s 2 s 80 mA 60 120 mA Typical parameters as seen at room temperature including function call overhead, with all peripherals off. Table 6-78. Flash/OTP Access Timing PARAMETER MIN MAX UNIT ta(fp) Paged Flash access time 40 ns ta(fr) Random Flash access time 40 ns ta(OTP) OTP access time 60 ns Peripheral and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 149 ADVANCE INFORMATION Table 6-76. Flash/OTP Endurance for Q Temperature Material (1) TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 6-79. Minimum Required Flash/OTP Wait-States at Different Frequencies (1) SYSCLKOUT (MHz) SYSCLKOUT (ns) PAGE WAIT-STATE (1) RANDOM WAIT-STATE (1) OTP WAIT-STATE 60 16.67 2 2 3 55 18.18 2 2 3 50 20 1 1 2 45 22.22 1 1 2 40 25 1 1 2 35 28.57 1 1 2 30 33.33 1 1 1 Page and random wait-state must be ≥ 1. The equations to compute the Flash page wait-state and random wait-state in Table 6-79 are as follows: éæ t a(f ×p) ö ù ÷ - 1ú round up to the next highest integer, or 1, whichever is larger Flash Page Wait State = êç ç ÷ ëêè t c(SCO) ø ûú ADVANCE INFORMATION éæ t a(f ×r) ö ù ÷ - 1ú round up to the next highest integer, or 1, whichever is larger Flash Random Wait State = êç êëçè t c(SCO) ÷ø úû The equation to compute the OTP wait-state in Table 6-79 is as follows: éæ t a(OTP) ö ù ÷ - 1ú round up to the next highest integer, or 1, whichever is larger OTP Wait State = êç ç ÷ ëêè t c(SCO) ø ûú 150 Peripheral and Electrical Specifications Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 7 Mechanical Packaging and Orderable Information 7.1 Thermal Data Table 7-1 through Table 7-4 show the thermal data. See Section 7.1.1 for more information on thermal design considerations. Table 7-1. Thermal Model 100-Pin PZP Results 0 lfm 150 lfm 250 lfm 500 lfm θJA [°C/W] High k PCB 24.4 15.1 13.9 12.4 ΨJT [°C/W] 0.3 0.4 0.4 0.5 ΨJB 4.5 4.2 4.2 4.2 θJC 9.4 θJB 4.4 ADVANCE INFORMATION AIR FLOW PARAMETER Table 7-2. Thermal Model 100-Pin PZ Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA [°C/W] High k PCB 42.2 32.4 30.9 28.7 ΨJT [°C/W] 0.4 0.6 0.7 0.9 ΨJB 19.1 18.2 17.9 14.1 θJC 7.2 θJB 19.6 Table 7-3. Thermal Model 80-Pin PFP Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA [°C/W] High k PCB 25.8 16.3 15.2 13.6 ΨJT [°C/W] 0.3 0.4 0.4 0.5 ΨJB 4.6 4.4 4.3 4.3 θJC 9.4 θJB 4.6 Table 7-4. Thermal Model 80-Pin PN Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA [°C/W] High k PCB 41.1 31.2 29.7 27.5 ΨJT [°C/W] 0.4 0.6 0.7 0.9 ΨJB 15.3 14.6 14.4 14.1 θJC 7.9 θJB 15.6 Mechanical Packaging and Orderable Information Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 Copyright © 2010–2011, Texas Instruments Incorporated 151 TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698A – NOVEMBER 2010 – REVISED JANUARY 2011 7.1.1 www.ti.com Thermal Design Considerations Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal application reports IC Package Thermal Metrics (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices (literature number SPRA963) help to understand the thermal metrics and definitions. 7.2 Packaging Information The following packaging information and addendum reflect the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document. ADVANCE INFORMATION 152 Mechanical Packaging and Orderable Information Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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