TI TMS3637P

TMS3637
Remote Control Transmitter/Receiver
Data Manual
SCTS037B
JUNE 1997
i
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to
discontinue any semiconductor product or service without notice, and advises its
customers to obtain the latest version of relevant information to verify, before placing
orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the
specifications applicable at the time of sale in accordance with TI’s standard warranty.
Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not
necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the
customer. Use of TI products in such applications requires the written approval of an
appropriate TI officer. Questions concerning potential risk applications should be directed
to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design
and operating safeguards should be provided by the customer to minimize inherent or
procedural hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI
warrant or represent that any license, either express or implied, is granted under any
patent right, copyright, mask work right, or other intellectual property right of TI covering
or relating to any combination, machine, or process in which such semiconductor
products or services might be or are used.
Copyright  1997, Texas Instruments Incorporated
ii
Contents
Title
Page
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–1
1–1
1–2
1–2
1–3
2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . .
2.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage
and Operating Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.5 Write/Erase Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Timing Requirements Over Recommended Ranges of Supply Voltages
and Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Abort/Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 EEPROM Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3 EEPROM Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.4 Data Input Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Switching Characteristics Over Recommended Ranges of Supply Voltages
and Free-Air Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 Normal Transmission – Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 Modulated Transmission – Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1
2–1
2–1
2–2
2–2
2–2
2–2
2–2
2–2
2–3
2–3
2–3
2–3
2–3
2–3
2–3
2–3
3
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
4
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
5
Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 EEPROM Memory (31 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Program Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 Program Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Internal Oscillator Operation for Transmit and Receive Modes Setting
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Internal Oscillator Operation for Transmit and Receive Modes Sampling
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 External Oscillator Operation for Transmit and Receive Modes . . . . . . . . . . . . . . .
5.6 Internal Amplifier/Comparator, Description and Gain Setting . . . . . . . . . . . . . . . . .
5–1
5–1
5–1
5–1
5–2
5–3
5–4
5–4
5–4
iii
5.7
5.8
5.9
Internal Amplifier/Comparator Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Mode and Configuration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Transmitter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
5.9.1 Continuous Transmitter (CC = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
5.9.2 Triggered Transmitter (CC = 0, CI = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
5.9.3 Periodic Transmitter (CC = 0, CI = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
5.10 Transmitter Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
5.10.1 Normal Mode (CB = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
5.10.2 Modulated Mode (CB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
5.10.3 Code-Train Mode (CD, CE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
5.11 Receiver Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
5.11.1 Valid Transmission Receiver (CG = 1, CH = 0) . . . . . . . . . . . . . . . . . . . . 5–11
5.11.2 Train Receiver (CG = 1, CH = 1, CD, CE) . . . . . . . . . . . . . . . . . . . . . . . . 5–11
5.11.3 Q-State Receiver (CG = 0, CH = 0, CD, CE) . . . . . . . . . . . . . . . . . . . . . . 5–12
5.12 Receiver Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
5.12.1 Normal Mode (CB = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
5.12.2 Modulated Mode (CB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
5.12.3 Analog Mode (CF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
5.12.4 Logic Mode (CF = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14
5.12.5 Noninverting Mode (CI = 0) or Inverting Mode (CI = 1) . . . . . . . . . . . . . 5–14
6
iv
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.1 General Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.2 Direct-Wired Connection of Transmitter and Receiver . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.2.1
Two-Wire Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.2.2
Four-Wire Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
6.3 Infrared Coupling of Transmitter/Receiver – Normal Transmission Mode . . . . . . 6–5
6.4 Infrared Coupling of Transmitter/Receiver – Modulated Transmission Mode . . . 6–8
6.5 Radio Frequency (RF) Coupling of Transmitter and Receiver . . . . . . . . . . . . . . . 6–10
6.6 RF Receiver and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
6.7 Programming Station . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
6.8 TMS3637 Programming Station Parts Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
6.9 TMS3637 Edge-Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
List of Figures
Figure
Title
Page
3–1
3–2
3–3
3–4
3–5
3–6
3–7
Normal Transmission – External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VTR Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data In Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Transmission – Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modulated Transmission – Internal Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1
3–1
3–1
3–2
3–2
3–2
3–2
4–1
4–2
4–3
Oscillator Resistance Versus Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Oscillator Frequency Versus Oscillator Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
High-Voltage Programming Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
5–1
5–2
5–3
5–4
5–5
5–6
5–7
EEPROM Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
EEPROM Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Amplifier/Comparator Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
OUT Waveform in Normal Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
OUT Waveform in Modulated Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Transmitter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Receiver Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
6–1
6–2
6–3
6–4
6–5
6–6
6–7
6–8
6–9
Two-Wire Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Four-Wire Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Four-Wire Direct Connection Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
Infrared Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
Infrared Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Infrared Modulated Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Radio Frequency Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
TRF1400 RF Receiver and TMS3637 Decoder Circuit . . . . . . . . . . . . . . . . . . . . . . 6–12
Programming Station . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
v
List of Tables
Table
Title
Page
5–1
5–2
5–3
5–4
5–5
5–6
5–7
5–8
Mode and Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Transmitter Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
Receiver Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
Amplifier Test, Program, and Read Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
Code-Train Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Transmitter/Receiver Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Bits CD and CE in Train Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
Bits CD and CE in Q-State Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12
6–1
6–2
6–3
6–4
6–5
6–6
6–7
Two-Wire Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Four-Wire Direct Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Infrared Transmitter Component Functions (Normal Transmission Mode) . . . . . . . 6–6
Infrared Receiver Component Functions (Normal Transmission Mode) . . . . . . . . . 6–7
Infrared Receiver Component Functions (Modulated Tranmission Mode) . . . . . . . 6–9
RF Transmitter Component Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
TRF1400 RF Receiver and TCM3637 Decoder Parts List
(for 300 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
TMS3637 Programming Station Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18
Edge Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19
6–8
6–9
vi
1 Introduction
The TMS3637 is a versatile 3-V to 6-V remote control transmitter/receiver in a small package that requires
no external dual-in-line package (DIP) switches on the system circuit board. The device can be easily set
for one of many transmit/receive configurations using configuration codes along with the desired security
code, both of which are user programmable. When used as a transmitter, the device encodes the stored
security code, transmits it to the remote receiver using any transmission media such as direct wiring,
infrared, or radio frequency. When configured as a receiver, the TMS3637 continuously monitors and
decodes the transmitted security code (at speeds that can exceed 90 kHz) and activates the output of the
device when a match with its internally stored code has been found. All programmed data is stored in
nonvolatile EEPROM memory. With more than four million codes alterable only with a programming station,
the TMS3637 is well suited for remote control system designs that require high security and accuracy.
Schematics of the programming station and other suggested circuits are included in this data manual.
In addition to the device configuration and security code capabilities, the TMS3637 includes several internal
features that normally require additional circuitry in a system design. These include an amplifier/comparator
for detection and shaping of input signals as low as several millivolts (typically used when an RF link is
employed) and an internal oscillator (used to clock the transmitted or received security code).
The TMS3637 is characterized for operation from – 25°C to 85°C.
1.1
Features
•
Data Encoder (Transmitter) or Data Decoder (Receiver) for Use in Remote Control Applications
•
High Security
– 4,194,304 Unique Codes Available
– Codes Stored in Nonvolatile Memory (EEPROM)
– Codes Alterable Only With a Programming Station That Ensures No Security Code
Duplications
•
Versatile
– 48 Possible Configurations as a Receiver
– 18 Possible Configurations as a Transmitter
– Single, Multiple, or Continuous Cycling Transmission
•
Easy Circuit Interface With Various Transmission Media
– Direct Wired
– Infrared
– Radio Frequency
•
Minimal Board Space Required: 8-Pin (D or P) Package and No DIP Switches
•
Internal On-Chip Oscillator Included, No External Clock Required
•
CMOS 2-µm Process Used for Very Low-Power Consumption and 3-V to 6-V Supply Voltage
•
Well Suited for All Applications Requiring Remote-Control Operation
– Garage Door Openers
– Security Systems for Auto and Home
– Electronic Keys
– Consumer Electronics
– Cable Decoder Boxes
– Industrial Controls Requiring Precise Activation of Equipment
– Electronic Serial Number (ESN) Device Identification
1–1
1.2
Functional Block Diagram
IN
CEX
7
6
5
Amplifier
OUT
GND
Logic
Circuit
OSCR
OSCC
1
2
Oscillator
3
Power-On
Reset
Shift
Register
Test Mode
and
High Voltage
Interface
EEPROM
Memory
4
GND
1.3
8
VCC
Terminal Assignments
D OR P PACKAGE
(TOP VIEW)
OSCR
OSCC
TIME
GND
1–2
1
8
2
7
3
6
4
5
VCC
IN
CEX
OUT
TIME
1.4
Terminal Functions
TERMINAL
NAME
NO.
I/O
I
DESCRIPTION
CEX
6
Capacitor external. CEX is used for gain control of the internal analog amplifier. An external
capacitor connected from CEX to GND determines the gain of the amplifier. If the internal
amplifier is set for unity gain or the device is not used as a receiver, CEX is left unconnected.
GND
4
IN
7
I/O
Depending on the device configuration, IN provides inverted OUT data, is used as a receiver
input, or is used to enter data during programming.
– When the device is configured as a transmitter, IN provides the complement of the OUT
data stream and is considered to be noninverted. IN provides its own internal pullup, so
no external pullup is required when IN is used to transmit the data. It is cleared to 0 in
standby.
– When the device is configured as a receiver, IN is used to receive the code.
– When the device is in the program mode, IN is used to enter serial data into the device
shift registers that load into the EEPROM memory.
OSCC
2
I/O
Oscillator capacitor. Depending on the configuration, OSCC is used for external transmit/receive
clock input, control of the internal oscillator, to place the device into program mode, input for a
high-voltage EEPROM programming pulse, or the internal analog amplifier in the test mode.
– When the device is used as a transmitter or receiver using an external clock, the external
clock is connected directly to OSCC. (OSCR must be held low to use an external clock.)
– When the device is used as a transmitter or receiver and the internal oscillator is used,
a capacitor from OSCC to GND and a resistor from OSCR to GND determines the
free-running internal oscillator frequency. In addition, the internal oscillator triangular
waveform can be seen at OSCC in this configuration.
– When the device is in the data-loading phase of the programming mode, OSCC must be
held at VCC + 0.5 V.
– After the device has been loaded with data in the programming mode, the internal
registers transfer the data to the EEPROM permanently by applying a high-voltage
programming pulse to OSCC.
– When OSCC is held at VCC + 0.5 V and three or more low pulses are applied to OSCR,
the device is in the test mode and the output of the internal analog amplifier can be
measured at TIME.
OSCR
1
I
Oscillator resistor. Depending on the configuration, OSCR is used as an external program/
read clock input or to control the internal clock frequency.
– When the device is in the program/read mode, OSCR is connected to an external clock.
– When the device is in the transmit or receive mode, a resistor connected from OSCR to
GND (along with a capacitor from OSCC to GND) determines the frequency of the internal
clock.
OUT
5
O
OUT is an open-drain output. For that reason, it is necessary to connect a pullup resistor to OUT.
Depending on the configuration, OUT provides transmit data, acts as the output for the receiver,
or provides the serial output of the stored data in memory during the program and read modes.
– When the device is configured as a transmitter, the transmitted data is seen at OUT and
is in a 3-state output mode during standby (OUT is floating). While transmitting, the data
from OUT is considered inverted.
– When the device is configured as a valid transmission receiver (VTR) receiver, OUT
provides a VTR pulse and goes low in the standby mode.
– When the device is configured as a Q-state receiver, OUT toggles high and low each time
a valid code is received.
– During the program mode, OUT provides the current data from the EEPROM memory
when the new data is clocked into the device.
Ground
1–3
1.4
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TIME
3
VCC
8
1–4
I/O
DESCRIPTION
I/O
Depending on the configuration, TIME is used for measuring the internal analog-amplifier output
in the device test mode, putting the device into the transmit mode, or controlling an internal clock
oscillator for various transmitter and receiver configurations.
– When OSCC is held at VCC + 0.5 V and three or more low pulses are applied to OSCR,
the device is in the test mode and the output of the internal analog amplifier can be
measured at TIME.
– When the device is configured as a continuous transmitter, an internal pullup is connected
to TIME. If TIME is then forced low, the device transmits codes for the duration that TIME
is held low. (TIME must be connected to an external pullup.)
– When the device is configured as a triggered transmitter and if TIME is then forced low,
the device transmits one code or a code train. (TIME must be connected to an external
pullup.)
– When the device is configured as a periodic transmitter, connect an external resistor and
capacitor between TIME and VCC to transmit code after each RC time constant has
expired.
– When the device is configured as a VTR, TIME must be held high to receive codes. The
device produces a VTR pulse on OUT after confirmation of a correct received code.
Connecting a parallel resistor and capacitor between TIME and VCC lengthens the output
pulse (VTR) duration.
– Configured as a train receiver, connect an external parallel resistor and capacitor between
TIME and VCC, which are used to set the length of time the device is looking for two, four,
or eight correct received codes to output a valid VTR pulse on OUT.
– Configured as a Q-state receiver, TIME has the same function as the VTR receiver above,
except the detection of the correct code causes OUT to toggle between the low and high
states.
5-V supply voltage
2 Specifications
2.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
Input voltage range (except OSCC), VI . . . . . . . . . . . . . . . . . . . . . – 0.6 V to VCC + 0.5 V
Input voltage range, OSCC, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 15 V
Output voltage range, OUT, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 15 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTE 1: Voltage values are with respect to GND.
2.2
Recommended Operating Conditions
MIN
Supply voltage, VCC
High-level input voltage, VIH
Low-level input voltage, VIL
NOM
3
VCC – 0.5
0
MAX
UNIT
6
V
VCC
0.5
V
V
85
°C
Receiver supply current, analog, ICC(an)
2
mA
Receiver supply current, digital, ICC(dig)
200
µA
Transmitter supply current, standby, ICC(stdby)
13
µA
Transmitter supply current, code transmission,
ICC(code)
260
µA
Programming current at OSCC, IOSCC
100
µA
Operating free-air temperature, TA
– 25
µs
5
1/(fosc)
tp1
200
Pulse duration, logic 1 bit, tw1 (see Figure 3–1)
100
µs
Pulse duration, logic 0 bit, tw2 (see Figure 3–1)
35
3 x tp0 + 4 x tp1
700
µs
152
19 × tw1
(receiver)
48
6 × tw1
(receiver)
Oscillating period, tp0+ tp1 (see Figure 3–1)
Setup time, transmitter/receiver external clock on
OSCC↓ and before IN↑, tsu1 (see Figure 3–2)
Pulse duration, IN high, tw3 (see Figure 3–2)
10
µs
RTIME × CTIME
(see Note 2)
µs
NOTES: 2. RTIME is the value of the pullup resistor on TIME and CTIME is the value of the capacitor in parallel with
RTIME. CTIME should not exceed 3 µF.
2–1
2.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage
and Operating Free-Air Temperature (unless otherwise noted)
2.3.1
Signal Interface
PARAMETER
VOL
VOH
Low-level output voltage, OUT
High-level output voltage, OUT
Ci
Input capacitance
Co
Output capacitance
IOH < 5 mA
PARAMETER
0.6
0.7
VCC – 0.5
1.2
1.6
TEST CONDITIONS
VO
Output voltage, TIME
B
Bandwidth
V
µA
± 10
µA
pF
5
pF
MIN
TYP
MAX
External peak-to-peak noise voltage
1
VOL
VI = 3 mV
VI = 100 mVpeak to peak
VI = 200 mVpeak to peak
CEX (nF) > 900/fosc (kHz)
Flatband gain
UNIT
mV
mV
VOH
15
V
500
kHz
1000
200
CEX not connected
V/V
1
Internal Oscillator (see Note 3)
Receiver frequency
MIN
TYP
MAX
UNIT
500
kHz
fRX/10
fRX/5.5
± 20%
kHz
10
Transmitter frequency
fRX/10
Power-On Reset
PARAMETER
MIN
VCC level required to trigger power-on reset
Power-on reset duration
MAX
UNIT
2.7
V
40
ms
Write/Erase Endurance
PARAMETER
Number of program cycles
2–2
V
10
Frequency spread (temperature, VCC)
NOTE 3: Typical values are recommended whenever possible.
2.3.5
UNIT
± 10
3
PARAMETER
2.3.4
MAX
Amplifier
Peak-to-peak input voltage
fRX
fTX
TYP
VI = 0 V to 6 V
VO = 0 V to 12 V
Output current, OUT
VI(PP)
VN(PP)
2.3.3
0.5
High-level output voltage, OSCC
Input current, IN
AV
MIN
Low-level output voltage, OSCC
II
IO
2.3.2
TEST CONDITIONS
IOL < 5 mA
MIN
TYP
20
10 000
MAX
UNIT
2.4
Timing Requirements Over Recommended Ranges of Supply Voltages
and Free-Air Temperature
2.4.1
Abort/Retry
MIN
NOM
Time between consecutive codes
MAX
46 x tw (transmitter)
Time out for high-level bit to abort the code
3 x tw (receiver)
Time out for low-level bit to abort the code
25 x tw (receiver)
Time between aborted code and reading of new code
3 x tw (receiver)
2.4.2
EEPROM Read Mode (see Figure 3–3)
MIN
MAX
UNIT
tsu2
tw4
Setup time, OSCR high after VCC ↑
50
ms
Pulse width, OSCR high
10
µs
tw5
Pulse width, OSCR low
10
µs
2.4.3
EEPROM Write Mode (see Figure 3–3 and Figure 3–4)
MIN
tsu3
tw6
Setup time, OSCR high after VCC high
tw7
tv
Pulse duration, OSCR high
5
µs
Pulse duration, OSCR low
5
µs
10
µs
Data Input Setup and Hold Times (see Figure 3–5)
MIN
tsu4
th1
2.5
UNIT
ms
Valid time, data IN valid before OSCC↑
2.4.4
MAX
50
NOM
MAX
UNIT
Setup time, data in before OSCR↓
1
µs
Hold time, data in after OSCR↓
1
µs
Switching Characteristics Over Recommended Ranges of Supply
Voltages and Free-Air Temperature (unless otherwise noted)
2.5.1
Normal Transmission – Internal Clock (see Figure 3–6)
PARAMETER
MIN
TYP
MAX
UNIT
5
1/(2 x fosc)
100
µs
Pulse duration, logic bit 1 for IN
5
µs
35
tw
7 x tw
100
Pulse duration, logic bit 0 for IN
700
µs
tw8
tw9
Pulse duration, half-oscillating period for OSCC sawtooth ↑↓
tw10
2.5.2
Modulated Transmission – Internal Clock
PARAMETER
TEST
CONDITIOINS
fosc(t)
fosc(r)
Transmitter oscillator frequency
tw(H)
tc
Pulse duration, high-level modulation at IN
See Figure 3-7
Cycle time, IN
See Figure 3-7
tc(total)
tw11
Total cycle time, IN
See Figure 3-7
Pulse duration, logic bit 1 for IN
tw12
Pulse duration, logic bit 0 for IN
Receiver oscillator frequency
MIN
TYP
MAX
UNIT
100
110
120
kHz
400
440
480
kHz
10
µs
27
1/fosc(t)
3 x tw(H)
30
µs
135
5 x tc
150
µs
See Figure 3-7
135
5 x tc
150
µs
See Figure 3-7
945
7 x tw10
1050
µs
9
2–3
2–4
3 Parameter Measurement Information
VIH
OSCC
VIL
tp0
tp1
tw2
tw1
VIH
IN
VIL
Figure 3–1. Normal Transmission – External Clock
OSCC
tsu1
tw3
IN
Figure 3–2. VTR Generation
VCC
5V
5V
tsu2
5.5 V
OSCC
4 Reset Pulses
OSCR
(clock in)
tw4
tw5
Figure 3–3. EEPROM Read Mode
3–1
5V
5V
VCC
tsu3
C01– C22
22 Security Bits
4 Reset Pulses
CA– CI
9 Configuration Bits
OSCR
(clock in)
C01
tw6
C02
C03
C04
C22
CI
CA
tw7
IN
(data in)
tv
15 V
5.5 V
High-Voltage
Programming Pulse
OSCC
OUT
(previous data)
Figure 3–4. EEPROM Write Mode
OSCR
(clock)
IN
(data in)
th1
tsu4
Figure 3–5. Data In Setup and Hold Times
VIH
OSCC
VIL
tw8 tw8
tw9
tw10
VIH
IN
VIL
Figure 3–6. Normal Transmission – Internal Clock
IN
tw(H)
tc
tc (total)
tw12
tw11
Figure 3–7. Modulated Transmission – Internal Clock
3–2
4 Typical Characteristics
8
220 kΩ
7
5
4
3
22 kΩ
2
1
0
10
0
50
100
Rosc – Oscillator Resistance – kΩ
300
200
Figure 4–1. Oscillator Resistance Versus Supply Voltage
10 7
Rosc = 100 kΩ
10 6
f osc – Oscillator Frequency – Hz
VCC – Supply Voltage – V
6
Rosc = 47 kΩ
Rosc = 22 kΩ
10 5
10 4
10 3
10 2
10 1
10
10
100
1000
10 000
100 000
Cosc – Oscillator Capacitance – pF
1 000 000
Figure 4–2. Oscillator Frequency Versus Oscillator Capacitance
4–1
VI – Input Voltage at OSCC – V
15
15 V
10
5.5 V
ÁÁÁ
ÁÁÁ
5
> 1 ms
> 3 ms
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
t – Time – ms
Figure 4–3. High-Voltage Programming Pulse
4–2
14
15
16
5 Principles of Operation
5.1
Power-On Reset
The power-on reset function starts when VCC rises above 2.7 V and is completed after four clock periods.
After power-on reset, the nine configuration bits contained in the EEPROM memory are loaded into the logic
circuits, which determine the device mode and configuration of operation. For correct enabling of the
power-on reset operation, it is necessary for VCC to first fall below 2.3 V and remain in this condition for at
least 0.5 ms.
5.2
EEPROM Memory (31 Bits)
The EEPROM memory contains a total of 31 bits. The first 22 of the 31 bits contain the security code. These
22 bits are named C01, C02,...C22, and are user definable. The last 9 bits of the total 31 bits are
configuration bits named CA,CB,...CI, and are also user definable to select the mode of operation for the
device.
5.2.1
Program Read Mode
The procedure described in the following steps is used to read the current contents of the EEPROM memory.
This can verify that the correct 22 security codes and 9 configuration bits are stored in memory (see
Figure 5–1):
1.
Set VCC to 5 V.
2.
Apply VCC + 0.5 V to OSCC. Wait at least 50 ms to allow the device to assume the read mode
(tsu2 > 50 ms). This voltage on OSCC forces the device into the read mode, and the terminals
are in the following configuration:
•
OSCR: program/read external clock input
•
OUT: serial output of 31 data bits currently stored in EEPROM
3.
Apply four reset pulses to OSCR (tw4 = tw5 = 10 µs). This only needs to be done once during each
read operation.
4.
Apply 31 clock pulses to clock input OSCR (tw4 = tw5 = 10 µs min). This clocks out the 31 data
bits (C01,C02,...C22, and CA,CB,...CI) that are stored in memory. Output data changes state
only on falling edge of clock pulses, except on data bit C01. If used, data bit C01 goes high on
the rising edge of the clock pulse.
NOTE:
Each succeeding group of 31 clock pulses, when applied, clocks out the data again
without any reset pulses required.
5–1
5V
VCC
tsu2
C01 – C22
22 Security Bits
4 Reset Pulses
CA – C1
9 Configuration Bits
OSCR
(clock in)
C01
tw4
C03
C22
CI
tw5
C02
C04
CA
OUT
5.5 V
OSCC
Figure 5–1. EEPROM Read Mode
5.2.2
Program Write Mode
The procedure to write the 31 security code and configuration bits to memory is described below (see
Section 3 for timing diagram):
5–2
1.
Set VCC to 5 V.
2.
Apply VCC + 0.5 V to OSCC. This voltage on OSCC forces the device into the program mode,
and the terminals are in the following configuration:
•
OSCR: program/read external clock input
•
OSCC: input for high-voltage programming pulse used to permanently store data in memory
(see Figure 5–2).
•
OUT: serial output of 31 data bits currently stored in EEPROM
•
IN: serial input for 31 bits of data to be stored
3.
After applying VCC + 0.5 V to OSCC (step 2), wait at least 50 ms to allow device to go into the
program mode.
4.
Apply exactly four clock reset pulses to OSCR (clock input). These reset pulses are applied
before clock input pulses for the 31 data bits that contain the security code and configuration bits.
The minimum duration of the clock reset pulses must be tw6 = tw7 = > 5 µs, which equates to a
clock frequency <100 kHz.
5.
Apply exactly 31 clock input pulses to OSCR. This serves to clock in the 31 data bits that should
be applied to IN (C01,C02,...C22, and CA,CB,...CI). Each of the 31 data bits must be present
on the falling edges of the clock input pulses applied to OSCR with the setup and hold times being
1 µs minimum.
6.
The data at OUT is previous data that was stored in EEPROM before this operation. If the device
has never been programmed, this data is a random factory test code. The newly programmed
data can be read only after it is loaded.
7.
Apply a logic low to OSCR for at least 10 µs.
After a minimum valid time of tv = 10 µs, apply the high-voltage programming pulse to
permanently store the 31 code bits in EEPROM memory as shown in Figure 5–2. As stated in
steps 4 and 5, exactly 4 reset and 31 clock pulses must be applied for the device to successfully
program. The device does not transfer the code from its registers into the EEPROM if less than
or greater than 4 reset and 31 clock pulses are used before the programming pulse is applied.
8.
5V
5V
VCC
tsu3
C01– C22
22 Security Bits
4 Reset Pulses
CA– CI
9 Configuration Bits
OSCR
(clock in)
C01
tw6
C02
C03
C04
C22
CA
CI
tw7
IN
(data in)
tv
15 V
5.5 V
High-Voltage
Programming Pulse
OSCC
OUT
(previous data)†
OSCR
(clock)
IN
(data in)
tsu4 > 1 µs
th1 > 1 µs
† Previous data refers to data that was previously programmed into the device. If programmed for first time, this contains
a random test code from the factory.
Figure 5–2. EEPROM Write Mode
5.3
Internal Oscillator Operation for Transmit and Receive Modes Setting
Frequency
The TMS3637 has an internal oscillator that can be used in either the transmit or receive configurations of
the device. The oscillator free-running frequency (fosc) is controlled by an external resistor and capacitor
and is determined by:
fosc = 5 / (4 × Cosc × Rosc)
where
Cosc = capacitor from OSCC to GND
Rosc = resistor from OSCR to GND
(1)
The allowable oscillation range or Rosc versus VCC, and associated fosc values, and range versus Cosc for
three given values of Rosc are given in Section 4.
5–3
5.4
Internal Oscillator Operation for Transmit and Receive Modes Sampling
Frequency
The internal oscillator of the transmitter or receiver can be externally sampled at OSCC and OSCR. The
waveform at OSCC is triangular and the waveform at OSCR is square. The amplitude of these waveforms
depends on the capacitor and resistor values used.
5.5
External Oscillator Operation for Transmit and Receive Modes
Instead of using the internal oscillator (with an external resistor and capacitor) in the transmit or receive
modes, it is possible to externally drive the device by applying a logic level clock to OSCC. When an
externally driven oscillator is used, OSCR must be held to GND. To avoid entering the test/program modes,
ensure that the external clock applied to OSCC does not exceed VCC (for more information see
Section 5.12).
5.6
Internal Amplifier/Comparator, Description and Gain Setting
The TMS3637 has an internal amplifier that is designed to amplify received signals up to logic levels. In
addition, a comparator is cascaded with the amplifier to provide wave shaping of received signals. The
comparator also inverts the signal. The minimum received signal strength must be at least 3 mV
peak-to-peak (see Figure 5–3 for a schematic of the amplifier/comparator section). The amplifier is enabled
only when the TMS3637 is configured as an analog receiver. When the amplifier is not configured as an
analog receiver, it is disabled and bypassed to reduce power consumption in any of the three logic receiver
modes. A capacitor connected between CEX to GND determines the gain of the amplifier stage. When no
capacitor is connected from CEX to GND, the amplifier assumes unity gain and the comparator still functions
to shape the received signal. When the internal amplifier is used, it is usually run at the maximum gain of
200. The maximum gain is set by resistances internal to the device as shown in the equation 2. However,
to achieve this maximum gain, a low impedance from CEX to GND must exist. Equation 2 defines the
capacitance necessary at CEX for maximum gain at different oscillator frequencies (fosc):
CEX > 1 / (6.28 × fosc × R1)
(2)
where:
CEX = capacitance required for maximum gain
R1 = 178 Ω (set internally)
With a low impedance between GND and CEX, note that the maximum gain is derived from the noninverting
operational amplifier gain equation, (see Figure 5–3):
Gv = 1 + R2/R1 = 200
where:
R1 = 178 Ω (set internally)
R2 = 35.5 kΩ (set internally)
Ǹǒ
(3)
Ǔ
If a capacitor is used at CEX, but maximum gain is not desired, equation 4 can determine the gain for any
value of CEX:
Gv
+
1
) 4p2fosc2 CT2(R1 ) R2)2
1 ) 4p 2f osc2CT 2R1 2
where:
fosc = oscillator frequency of transmitter (it is the transmitted frequency that is being amplified)
CT = CEX + 0.15 nF (there is an internal capacitance of 0.15 nF at CEX)
R1 = 178 Ω (set internally)
R2 = 35.5 kΩ (set internally)
5–4
(4)
Amplifier
(Ao)
+
IN
(Ai)
Comparator
–
R1
R2
178 Ω
(internal)
+
CEX
35.5 kΩ
(internal)
+
_
+ 0.15 nF
(internal)
200-mV Reference
(internal)
Figure 5–3. Amplifier/Comparator Schematic
5.7
Internal Amplifier/Comparator Test Mode
Normally, the output of the amplifier/comparator section is fed directly to the logic circuitry internal to the
device; however, the output of the amplifier/comparator can be sampled external to the device during the
amplifier test mode to determine if the amplitude and shape of the received signal is acceptable for the
application. To enter the amplifier test mode, apply VCC + 0.5 V to OSCC and apply three or more low-level
pulses to OSCR. This can be done by simply brushing a wire connected from OSCR to GND. The output
of the amplifier stage is then connected internally to TIME, where it can be sampled for evaluation purposes.
5.8
Mode and Configuration Overview
The TMS3637 device is designed to function in many modes and configurations. The device has five primary
modes of operation as shown in Table 5–1.
Table 5–1. Mode and Test Configuration
MODE
DESCRIPTION
1
Amplifier Test
2
Program
3
Read
4
Transmitter
5
Receiver
In the transmitter and receiver modes (see Tables 5–2 and 5–3), there are a total of 66 configurations
available, 48 in the receiver mode and 18 in the transmitter mode.
5–5
Table 5–2. Transmitter Modes
OSCR
(PIN 1)
1
Normal
Continuous
11100000X
1
Normal
Triggered
110DE0001
1
Normal
Periodic
110DE0000
1
Modulated
Triggered
100DE0001
1
Modulated
Continuous
1
Modulated
Periodic
3
Code Train
Normal
Triggered
3
Code Train
Normal
Periodic
110DE0000
1
Code Train
Modulated
Triggered
100DE0001
3
Code Train
Modulated
Periodic
100DE0000
Capacitor to
C
GND
(internal
clock) and
output of the
i t
internal
l
clock
triangular
waveform
† X = don’t care and can be held high or low
5–6
TIME
(PIN 3)
OUT
(PIN 5)
CEX
(PIN 6)
IN
(PIN 7)
CA–CI
ABCDEFG
HI†
CONFIG.
External
clock or
resistor to
GND
(internal
clock)
OSCC
(PIN 2)
C1–C22
ABCDEFG
HI
NO. OF
MODES
10100000X
Starts
transmitting
h low
l
when
Serial output
of currently
d data
d
stored
N/C
N/C
Transmit
data from
memory
100000000
110DE0001
Table 5–3. Receiver Modes
NO. OF
MODES†
CONFIG.
2
Analog
Normal
VTR
6
Analog
Normal
Train
8
Analog
Normal
Q-state
2
Modulated
VTR
6
Modulated
Train
8
Modulated
Q-state
2
Logic
Normal
VTR
6
Logic
Normal
Train
8
Logic
Normal
Q-state
OSCR
(PIN 1)
External
clock or
resistor to
GND
(Internal
clock)
OSCC
(PIN 2)
TIME
(PIN 3)
OUT
(PIN 5)
Ca acitor
Capacitor
to GND
(Internal
clock)
l k)
Requires a
high-toenable
receiver
i
or
a resistor
and
capacitor
ca
acitor in
parallel
connected
between
VCC and
d
ground to
lengthen
the OUT
pulse.
When
operated in
eriodic
periodic
mode, a
resistor and
capacitor in
parallel
connected
between
VCC and
ground
causes a
reset.
CEX
(PIN 6)
C1–C22
ABCDEF
GHI
IN
(PIN 7)
CA–CI
ABCDEFG
HI‡
010XX010I
Serial output
of currently
stored data
and
configuration
data
010DE011I
Capacitor
to GND
for
receiver
g
analog
amplifier
gain
010DE000I
000XXX10I
R
i
Receive
signal
in
ut
input
Data
received
000DEX11I
000DEX00I
010XX110I
N/C
010DE111I
010DE100I
† Number of modes refers to total possible modes for that configuration: includes noninverting or inverting and number
of codes (train).
‡ X = don’t care and can be held high or low, I = 1 inverting, I = 0 for noninverting
The multitude of transmit and receive configurations are discussed in subsection 5.10.3 and Section 5.12.
A reference for the quick, correct programming of the device in the desired mode and configuration is
discussed in Section 5.12. Table 5–4 lists the signals required to set the amplifier test, program, and read
modes.
Table 5–4. Amplifier Test, Program, and Read Modes
MODE
NO. OF
MODES
†
CONFIG.
OSCR
(PIN 1)
OSCC
(PIN 2)
TIME
(PIN 3)
OUT
(PIN 5)
CEX
(PIN 6)
IN
(PIN 7)
C1–C22
ABCDE
FGHI
CA–CI
ABCDE
FGHI
Amplifier
Test
1
Amplifier
Test
3 or
more low
pulses
VCC + 0.5 V
Internal
amplifier
out
N/C
Capacitor
to GND
(for gain)
Receive
signal
input
X‡
X‡
Program
1
Program
External
clock
VCC + 0.5 V
and high
voltage
programming
pulse (ramp
to 15 V)
N/C
Serial
out of
previous
data
N/C
New
serial
data and
configuration
input
Data
to be
stored
Configuration
to be
stored
Read
1
Read
EEPROM
External
clock
VCC + 0.5 V
N/C
Serial
out of
stored
data
N/C
N/C
Stored
data
Stored
configuration
† Number of modes refers to total possible modes for that configuration; which includes noninverting mode or inverting
mode and number of train codes.
‡ X = don’t care and can be held high or low
5–7
5.9
Transmitter Configurations
Of the total 31 data bits that are stored by the TMS3637, the last nine (CA through CI) configure the device
in one of 18 possible transmitter configurations. The device can run continuous, triggered, or
periodic in transmission. In addition, each of these functions can have a single, pulse, or train output in both
normal and modulated configurations. (For a definition of which configuration bits to set for all possible 18
transmitter configurations, see subsection 5.10.3.) To enter any transmitter configuration, always start by
setting EEPROM bits CA = 1 and CF = CG = CH = 0.
When OUT transmits the code, the code is considered to be inverted. OUT also requires an external pullup
resistor. When IN transmits the code, the code is the complement of OUT and is considered noninverted.
An internal pullup resistor is connected to IN, so no external pullup is required when it transmits the code.
5.9.1
Continuous Transmitter (CC = 1)
When the device is configured as a transmitter (CA = 1, CF = CG = CH = 0) and the EEPROM bit CC is set
to 1, the chip is programmed to function as a continuous transmitter. In this condition, the TMS3637 serially
transmits the same code indefinitely. The transmit sequence is enabled by setting TIME to low. TIME is
externally connected to a pullup resistor, so a simple switch between TIME and GND can force TIME low.
The code transmission continues as long as TIME is kept low. When TIME returns to high, the transmission
of the code is completed and the transmitter is disabled. The oscillator is consequently inhibited, and the
power consumption is reduced to the standby value (13 µA). The time between two consecutive codes (tbc)
during the transmission is equal to 57 pulse durations (tbc = 57 tw8, see Figure 3–6). The continuous
transmitter must be operated in either the normal (CB = 1) or modulated (CB = 0) modes.
5.9.2
Triggered Transmitter (CC = 0, CI = 1)
When the chip is configured as a transmitter (CA = 1, CF = CG = CH = 0) and EEPROM bits CC and CI
low and high, respectively, the chip is programmed to work as a triggered transmitter. The TMS3637
transmits a single code or a code train when TIME is forced low, and then the device enters the standby
mode. In order to retransmit a code, TIME must be taken high (or opened) and then forced low again. The
triggered transmitter must be operated in either the normal (CB = 1) or modulated (CB = 0) modes.
5.9.3
Periodic Transmitter (CC = 0, CI = 0)
When the chip is configured as a transmitter (CA =1, CF = CG = CH = 0) and the EEPROM bits CC and CI
are cleared to 0, the chip is programmed to work as a periodic transmitter. In this case, the internal pullup
resistor on TIME is disconnected and TIME is externally connected to VCC through a parallel RC. The
TMS3637 transmits one code or a code train and goes into the standby mode. After a time equal to one RC
time constant, the TMS3637 is enabled and transmits the code again. The TMS3637 then enters the standby
mode and repeats the process. During the code transmission, the external capacitor is loaded by VCC.
During the standby mode, it is discharged through the resistor. The transmission cycle starts again when
the capacitor voltage falls below the trigger value of TIME. In this way, it is possible to obtain a very low
average value of ICC. Typically, it is possible to obtain ICC = 1.5 µA at a transmission frequency of 2 Hz. The
periodic transmitter must be operated in either the normal (CB = 1) or modulated (CB = 0) modes.
5.10 Transmitter Modes
In addition to the three transmitter configurations discussed previously, the TMS3637 transmitter can
operate in four modes: normal, continuous, triggered, and periodic. The following paragraphs describe the
configuration bit setting required to place the TMS3637 in each of the four modes.
5–8
5.10.1
Normal Mode (CB = 1)
When the chip is configured as a continuous transmitter (CA = 1, CF = CG = CH = 0, and CC = 1), as a
triggered transmitter (CA = 1, CF = CG = CH = 0, and CC = 0, CI = 1), or as a periodic transmitter
(CA = 1, CF = CG = CH = 0, and CC = 0, CI = 0), and EEPROM bit CB is set to 1, the TMS3637 operates
as a normal transmitter and emits the stored code on OUT (the open drain requires a pullup resistor). The
format for the code appearing on OUT is:
•
Each code transmission consists of a 3-bit precode (010) or sync word followed by 22 data bits
(C1 through C22) stored in the EEPROM.
•
A bit code 1 is represented high with a duration of t1, and a bit code 0 is represented high with
a duration of t2 = 7 t1.
An example of OUT is shown in Figure 5–4.
0
1
0
C01
C02
C03
C04
0
1
0
0
C22
1
1
0
0
1
1
1
OUT
t2
t1
Precode (3 bits)
Security Code (22 bits)
Figure 5–4. OUT Waveform in Normal Transmission
5.10.2
Modulated Mode (CB = 0)
When the chip is configured as a continuous transmitter (CA = 1, CF = CG = CH = 0, and CC = 1), as a
triggered transmitter (CA = 1, CF = CG = CH = 0, and CC = 0, CI = 1), or as a periodic transmitter (CA = 1,
CF = CG = CH = 0, and CC = 0, CI = 0), and EEPROM bit CB clears to 0, the device is programmed to
function as a modulated transmitter. The oscillator frequency must be 120 kHz.
In the modulated mode, a bit code 1 is represented high with a pulse width of t3 = t4. A bit code 0 is
represented by a high of t0 = 7 t4 as in the normal mode, except that the bit codes are each separated by
a pulse train composed of five elementary pulses. The total duration of t4 = 125 µs as shown in Figure 5–5.
25 µs
t3
Bit Code 1
t0 = 7 t4
Bit Code 0
t4 = 125 µs
Figure 5–5. OUT Waveform in Modulated Mode
5.10.3
Code-Train Mode (CD, CE)
When the chip is configured as a triggered transmitter (CA = 1, CF = CG = CH = 0, and CC = 0,
CI = 1) or as a periodic transmitter (CA = 1, CF = CG = CH = 0 and CC = 0, CI = 0), it can transmit
the stored code two, four, or eight times, depending on the values stored in bits CD and CE as shown
in Table 5–5 and Figure 5–6.
5–9
Table 5–5. Code-Train Modes
CD
CE
TRAIN
1
0
1
0
1
1
2 codes
4 codes
8 codes
TRAIN CODES
Transmitter
CA = 1, CF = CG = CH = 0
Triggered
CC = 0, CI = 1
Continuous
CC = 1
1 Code
CD, CE
Normal
CB = 1
Modulated
CB = 0
2 Codes
CD, CE
4 Codes
CD, CE
CD
CE
NO. OF
CODES
0
1
0
1
0
0
1
1
1
2
4
8
Periodic
CC = 0, CI = 0
8 Codes
CD, CE
1 Code
CD, CE
Normal Modulated
CB = 1
CB = 0
2 Codes
CD, CE
4 Codes
CD, CE
Normal
CB = 1
8 Codes
CD, CE
Modulated
CB = 0
Figure 5–6. Transmitter Configurations
5.11 Receiver Configurations
As with the transmitter configurations, the TMS3637 uses the last nine bits of the 31 data bits stored in
memory to program the device for a multitude of receiver configurations (48 possible configurations). The
configuration must match the transmitter when selecting the receiver configuration (see Table 5–6 to
determine compatible transmitter and receiver combinations). The definition of which configuration bits to
set for all the possible 48 receiver configurations is discussed in Section 5.12.
In the receive mode, the TMS3637 receives the transmitted code on IN and compares the code with the code
stored in memory. When the two codes are equal, a valid transmission pulse is sent to OUT. To have reliable
reception of the transmitted code, the receiver clock frequency must be approximately seven times greater
than the clock frequency for the transmitter clock. To set any receiver configuration in the receiver mode,
always start by clearing the EEPROM bits CA = CC = 0.
5–10
Table 5–6. Transmitter/Receiver Compatibility†
RCVR ANALOG ANALOG
NORMAL NORMAL
VTR
TRAIN
XMITTER
Normal
X
X
Continuous
ANALOG
NORMAL
Q-STATE
LOGIC
MODULATED MODULATED MODULATED NORMAL
VTR
TRAIN
Q-STATE
VTR
LOGIC
LOGIC
NORMAL NORMAL
TRAIN
Q-STATE
X
X
X
X
Normal
Triggered
X
X
X
X
X
X
Normal
Periodic
X
X
X
X
X
X
Modulated
Continuous
X
X
X
Modulated
Triggered
X
X
X
Modulated
Periodic
X
X
X
Code Train
Normal
Triggered
X
X
X
X
X
X
Code Train
Normal
Periodic
X
X
X
X
X
X
Code Train
Modulated
Triggered
X
X
X
Code Train
Modulated
Periodic
X
X
X
† X denotes compatible transmitter/receiver combinations.
5.11.1
Valid Transmission Receiver (CG = 1, CH = 0)
When the TMS3637 is configured as a receiver (CA = CC = 0) and the configuration bits CG = 1 and
CH = 0, the device is configured as a valid transmission receiver. Bits CB, CF, and CI must also be set to
specify modulated or normal modes, analog or logic (for normal mode only), and noninverting or inverting
format of the output code. Other receiver modes are discussed in Section 5.12.
In the valid transmission receiver (VTR) configuration, an external pullup resistor is connected to TIME.
When the TMS3637 recognizes the received code as correct, it produces a high pulse (VTR pulse) on OUT.
The VTR output pulse duration is equal to 48 times the pulse duration of the received data and is produced
after a delay time equal to 152 × 2/fosc from the end of the received code. If a capacitor is added in parallel
to the pullup resistor on TIME, the VTR pulse duration on the output terminal can be increased according
to a quantity determined by the time constant of RC. By choosing a large capacitor value (no greater than
1 µF), it is possible to have a VTR output pulse duration of up to several seconds. When the VTR duration
is longer than the repetition period of received codes, the VTR has a duration as long as that of the correct
received code.
5.11.2
Train Receiver (CG = 1, CH = 1, CD, CE)
When the TMS3637 is configured as a receiver (CA = CC = 0) and EEPROM bits CG and CH are both set
to 1, the device is configured as a train receiver. Bits CB, CF, and CI must also be set to specify modulated
or normal modes, analog or logic (for normal mode only), and noninverting or inverting format.
In the train-receiver configuration, the device outputs a VTR pulse on OUT only after the reception of two,
four, or eight received codes that occur within one period of the train code counter oscillator. This feature
5–11
further increases the security of the device by not recognizing the correct received code until it is repeated
two, four, or eight times within a period of time specified by an external RC combination described in the
following paragraphs.
When the TMS3637 is configured as a train receiver, connect an external resistor and capacitor in parallel
between TIME and VCC, which sets the length of time the device searches for two, four, or eight correct
received codes. When the device receives two, four, or eight correct codes (not necessarily in succession)
within the time constant of the external RC network, a valid VTR pulse is placed on OUT at the conclusion
of the RC time constant.
The number of codes in the train required is determined by the setting of bits CD and CE as shown in
Table 5–7.
Table 5–7. Bits CD and CE in Train Receiver
5.11.3
CD
CE
TRAIN
1
0
2 codes
0
1
4 codes
1
1
8 codes
Q-State Receiver (CG = 0, CH = 0, CD, CE)
When the TMS3637 is configured as a receiver (CA = CC = 0) and EEPROM bits CG and CH are both
cleared to 0, the device is configured as a Q-state receiver. Bits CB, CF, and CI must also be set to specify
modulated or normal modes, analog or logic (for normal mode only), and noninverting or inverting format
of the output code.
The Q-state receiver is similar to a train receiver, except that when a train of one, two, four or eight codes
are recognized as valid, OUT toggles. After power-on reset, OUT is floating, since OUT is an open-drain
output. As with the train receiver, OUT can change value only after the RC time constant present on TIME.
Use Table 5–8 to determine the setting of bits CD and CE.
Table 5–8. Bits CD and CE in Q-State Receiver
CD
CE
0
0
TRAIN
1 code
1
0
2 codes
0
1
4 codes
1
1
8 codes
5.12 Receiver Modes
Figure 5–7 shows all possible receiver combinations. The bit values are also shown that determine the mode
of operation.
5–12
TRAIN CODES
CD
CE
NO. OF
CODES
0
1
0
1
0
0
1
1
1
2
4
8
Receiver
CA = 0, CC = 0
VTR Receiver
CG = 1, CH = 0
2 Codes
CD,CE
Modulated
CB = 0
Normal Modulated
CB = 1
CB = 0
Analog Logic
CF = 0 CF = 1
Noninverting
Q-State Receiver
CG = 0, CH = 0
Train Receiver
CG = 1, CH = 1
4 Codes
CD, CE
8 Codes
CD, CE
1 Code
CD, CE
Normal
CB = 1
Analog
CF = 0
Logic
CF = 1
2 Codes
CD, CE
4 Codes
CD, CE
Modulated
CB = 0
Analog
CF = 0
8 Codes
CD, CE
Normal
CB = 1
Logic
CF = 1
Inverting
Figure 5–7. Receiver Configurations
5.12.1
Normal Mode (CB = 1)
The normal receiver function corresponds to a normal transmitter.
5.12.2
Modulated Mode (CB = 0)
The modulated receiver functions in a way that corresponds to a modulated transmitter. The oscillator
frequency of the receiver must be 480 kHz. The signal used as an input must be demodulated to the carrier
frequency of 40 kHz and then sent to IN.
5.12.3
Analog Mode (CF = 0)
In this configuration, the received code is sent directly to IN where it is amplified and passed through a
comparator to filter and square the received code waveform to logic levels. The phase of the output signal
of the internal amplifier section is reversed with respect to the input. The capacitor connected between CEX
and GND and the internal resistor of 178 Ω determines the cutoff frequency of the amplifier, which is in a
high-pass configuration.
5–13
5.12.4
Logic Mode (CF = 1)
In this configuration, the received code is at logic level. The analog amplifier and comparator connected
internally to IN is bypassed. This is typically the configuration used when the transmitter and receiver are
connected together by a hard line.
5.12.5
Noninverting Mode (CI = 0) or Inverting Mode (CI = 1)
The code input to IN is not inverted before passing to the logic circuitry. The following considerations must
be taken to determine if a noninverting or inverting receiver should be used:
•
Transmitting from OUT on the transmitter is considered inverted.
•
Transmitting from IN on the transmitter is considered noninverted.
•
Using the logic mode on the receiver (CF = 1) does not invert the signal.
•
Using the analog mode on the receiver (CF = 0) does invert the signal.
•
Determine whether the signal path between the transmitter and receiver inverts the signal.
The code input to IN is internally inverted before passing to the logic circuitry.
NOTE:
Do not use the TMS3637 in the log inverting modes CA = 0, CC = 0, CF = 0, or
CI = 1. The amplifier sensitivity is degraded in these modes.
5–14
6 Application Information
6.1
General Applications
In this section an example schematic is shown for each of the four transmission media categories for which
the device can be configured. These schematics help to define the capabilities of the TMS3637. When
configured for infrared, one transmitter works for both normal and modulated modes. In addition, a
recommended programming station is shown. The schematics are:
•
Direct-wired connection of transmitter/receiver
– Two wires
– Four wires
•
Infrared coupling of transmitter/receiver
– Normal transmission mode
– Modulated transmission mode
•
Radio frequency (RF) coupling of transmitter/receiver
•
RF receiver and decoder
•
Programming station used to program the TMS3637
–
6.2
Direct-Wire Connection of Transmitter and Receiver
The transmitter and receiver can be connected together by a direct two-wire or four-wire line. Both
configurations are described in the following paragraphs.
6.2.1
Two-Wire Direct Connection
Table 6–1 list the parts for the schematic of a two-wire direct connection of the transmitter and receiver
shown in Figure 6–1. Only two wires are required, primarily because the transmitted code is superimposed
on the source voltage delivered to the transmitter, and the transmitter uses its own internal oscillator. The
transmitter is configured as a normal continuous transmitter and the content of the configuration EEPROM
cells is:
CA CB CC CD CE CF CG CH CI
1
1
1
0
0
0
0
0
0
The device uses its internal oscillator to clock the data out (transmitter) and clock data in (receiver). The
oscillating frequency of the transmitter is approximately 5.7 kHz. With VCC = 5 V, the transmitted code on
OUT (point A) is a square waveform between 0 V (internal connection to GND) and 5 V. At point B, the
maximum value is 5 V (when OUT is open) and the minimum value is 4.8 × 10K/(10K+220) = 4.892 V (when
OUT is at 0 V). The voltage swing is then 5 V – 4.892 V = 108 mV. The voltage swing must not be much
greater than 100 mV because this is superimposed on the source voltage used to power the device. At point
C, the maximum value is VCC/2 = 2.5 V and the minimum value is 2.5 V – 0.108 V = 2.4 V due to the coupling
through capacitor C2. At point D, R6 and C4 act as a low-pass filter (with a cutoff frequency of approximately
11 kHz) so that the code passes but higher frequency noise is suppressed. The receiver is configured as
an analog normal 1-code Q-state noninverting receiver and the content of the EEPROM cells is:
CA CB CC CD CE CF CG CH CI
0
1
0
0
0
0
0
0
0
The receiver is used in the noninverting mode. Using OUT on the transmitter to transmit the code inverts
it, but the internal analog amplifier in the receiver (CF = 0) reinverts the signal. The signal path between the
transmitter and receiver does not invert the signal. The result is a signal that is noninverted at the internal
logic controller of the receiver, hence use CI = 0 for a noninverting receiver.
As required, the oscillating frequency of the receiver is about ten times greater than that of the 57 kHz
transmitter. This is easily set by keeping Rosc constant but reducing Cosc to one-tenth of its original value.
The signal on IN is internally amplified and the gain is calculated using equation 1:
G
+
Ǹǒ
1
1
) 39
) 39
32.5E6
32.5E6
103E-18
103E-18
Ǔ+
1.27E9
31.7E3
13
(1)
6–1
The input to the internal comparator has a voltage swing of approximately 1.4 V peak-to-peak (13 × 108 mV).
OUT on the receiver maintains the same status for approximately 0.5 s (1M × 470 nF).
Table 6–1. Two-Wire Direct Connection
DEVICE
6–2
FUNCTION
U1
TMS3637 configured as a normal continuous logic transmitter
U2
TMS3637 configured as a analog normal Q-state noninverting receiver
R1
Pullup resistor on OUT, an open drain
R2
Resistor on OSCR that, in conjunction with C1, determines the internal oscillator frequency of U1.
R3
Resistor that provides current limiting and isolation between VCC and transmitter OUT swing.
R4
Upper portion of voltage divider used to bias receiver output
R5
Lower portion of voltage divider used to bias receiver output
R6
Resistor that is part of RC low-pass network on front end of U2 receiver
R7
Resistor on TIME that, along with C5, determines OUT pulse duration on U2.
R8
Resistor on OSCR that, in conjunction with C7, determines internal oscillator frequency on U2.
R9
Current-limiting resistor for LED indicator
C1
Capacitor on OSCC that, in conjunction with R2, determines internal oscillator frequency of U1.
C2
AC-coupling capacitor for output logic pulses from U1
C3
Power-supply bypass capacitor
C4
Capacitor that is part of RC low-pass network used on front-end of U2 receiver.
C5
Capacitor on TIME that, in conjunction with R7, determines OUT pulse duration on U2.
C6
Capacitor that sets gain of internal receive amplifier in U2.
C7
Capacitor on OSCC that, in conjunction with R8, determines internal oscillator frequency of U2.
D1
LED for indication of Q-state output toggling on and off
VCC
B
VCC and Code
R3
220 Ω
R1
10 kΩ
8
7
VCC
IN
CEX
C6
10 nF
5
8
1
2
TIME
3
7
VCC
C2
0.1 nF
GND
IN
R7
1 MΩ
C
OSCC
D1
OUT
U1 (transmitter)
OSCR
C3
47 µF
R4
100 kΩ
A
6
+
R6
22 kΩ
D
4
6
5
CEX
OUT
R9
220 Ω
OUT
U2 (receiver)
OSCR
C5
470 nF
1
OSCC
TIME
GND
2
3
4
R2
22 kΩ
C1
10 nF
R5
100 kΩ
C4
680 pF
R8
22 kΩ
C7
1 nF
GND
Figure 6–1. Two-Wire Direct Connection
6.2.2
Four-Wire Direct Connection
Table 6–2 lists the parts for the schematic of a four-wire direct connection of the transmitter/receiver shown
in Figure 6–2. In this example, the VCC, code, clock, and GND are provided through four separate wires.
The transmitter is configured as a normal continuous transmitter and the content of the configuration
EEPROM cells is:
CA
1
CB
1
CC
1
CD
0
CE
0
CF
0
CG
0
CH
0
CI
0
The transmitter uses its external oscillator to clock the data out. This external oscillator is a simple inverting
(NOT) gate that has a positive feedback loop through a resistor. The frequency of the oscillator is
approximately 26 kHz.
The receiver is configured as a logic normal (1-code) Q-state inverting receiver, and the content of the
EEPROM cells is:
CA
0
CB
1
CC
0
CD
0
CE
0
CF
1
CG
0
CH
0
CI
1
The receiver is used in the inverting mode. The code is considered to be inverted when using OUT on the
transmitter to transmit the code. The signal path between the transmitter and receiver does not invert the
signal; using the logic mode (CF = 1) also does not invert the signal. The result is a signal that is inverted
at the internal logic controller of the receiver; then use CI = 1, and an inverting receiver is used. (When IN
transmits the code, the signal is not inverted; then use CI = 0. An external pullup is not required when IN
is used in this manner).
As required, the oscillating frequency is approximately 260 kHz, which is a frequency approximately ten
times greater than that of the transmitter. This is provided by the internal oscillator in the receiver. OUT on
the receiver maintains the same status for approximately 0.5 seconds (1M × 470 nF). A typical application
is an electronic key as shown in Figure 6–3.
6–3
Table 6–2. Four-Wire Direct Connection
DEVICE
FUNCTION
U1
TMS3637 configured as a normal continuous logic transmitter
U2
TMS3637 configured as an analog normal (1-code) Q-state noninverting receiver
U3
Inverter (NOT gate) used as external clock
R1
Feedback resistor for U3
R2
Resistor on TIME that, in conjunction with C2, determines OUT pulse duration on U2.
R3
Resistor on OSCR that, in conjunction with C3, determines internal oscillator frequency of U2.
R4
Pullup resistor for transmitter OUT, which is an open-drain output
R5
Current-limiting resistor for D1
C1
Part of feedback circuit used to cause U3 to oscillate
C2
Capacitor on TIME that, in conjunction with R2, determines OUT pulse duration on U2.
C3
Capacitor on OSCC that, in conjunction with R3, determines internal oscillator frequency of U2.
D1
LED for indication of received code
VCC
VCC
D1
R4
100 kΩ
R5
220 Ω
Code
8
7
VCC
IN
6
5
8
CEX
OUT
VCC
R2
1 MΩ
U1 (transmitter)
OSCR
1
OSCC
TIME
GND
2
3
4
C2
470 nF
Clock
R1
1.8 kΩ
IN
OSCR
5
CEX
OUT
OSCC
TIME
GND
2
3
4
R3
22 kΩ
C1
22 nF
GND
Figure 6–2. Four-Wire Direct Connection
6–4
6
U2 (receiver)
1
U3
74HC14
7
C3
220 pF
OUT
VCC
VCC
IN
CODE
GND
CLK
CEX OUT
U1 (transmitter)
OSCR OSCC GND TIME
Figure 6–3. Four-Wire Direct Connection Key
6.3
Infrared Coupling of Transmitter/Receiver — Normal Transmission Mode
Table 6-3 lists the parts for the schematic of an infrared transmitter working in the normal transmission
configuration as shown in Figure 6–4. Table 6–4 lists the parts for the infrared receiver shown in Figure 6–5.
The transmitter is configured as a normal continuous transmitter, and the content of the configuration
EEPROM cells is:
CA
1
CB
1
CC
1
CD
0
CE
0
CF
0
CG
0
CH
0
CI
0
The transmitter uses its internal oscillator to clock the data out. The frequency of the oscillator is
approximately 26 kHz.
The receiver is configured as a logic normal (1-code) Q-state inverting receiver and the content of the
EEPROM cells is:
CA
0
CB
1
CC
0
CD
0
CE
0
CF
1
CG
0
CH
0
CI
1
The receiver is used in the inverting mode. The code is considered to be inverted when using OUT on the
transmitter to transmit the code. The signal path between the transmitter and receiver does not invert the
signal. Using the logic mode (CF = 1) also does not invert the signal. The result is a signal that is inverted
at the internal logic controller of the receiver, then use CI = 1 for an inverting receiver.
As required, the oscillating frequency of the receiver is 260 kHz, which is approximately ten times greater
than that of the transmitter. This is provided by the internal oscillator in the receiver. OUT on the receiver
maintains the same status for approximately 0.5 seconds (1M × 470 nF).
6–5
Table 6–3. Infrared Transmitter Component Functions (Normal Transmission Mode)
DEVICE
FUNCTION
U1
TMS3637 configured as a normal continuous transmitter
R1
Resistor on OSCR that, in conjunction with C1, determines the internal oscillator frequency of U1.
R2
Current-limiting resistor for LED
R3
Current-limiting base-drive resistor for Q1
R4
Pullup resistor for OUT on U1 and bias for Q1
R5
Current-limiting collector resistor for Q1
R6
Pullup resistor for TIME
C1
Capacitor on OSCC that, in conjunction with R1, determines the internal oscillator frequency of U1.
C2
Power-supply bypass capacitor
D1
LED for visual indication of transmitted code
D2
Infrared LED used to transmit code
Q1
The pnp transistor that drives infrared LEDs
S1
S1 is closed for transmission.
VCC
R2
220 Ω
R4
10 kΩ
R5
3.9 Ω
D1
R6
10 kΩ
Q1
8
VCC
7
IN
6
5
CEX
OUT
R3
220 Ω
+
U1 (transmitter)
OSCR
1
OSCC
TIME
GND
3
4
2
R1
100 kΩ
C1
470 pF
R6
10 kΩ
Figure 6–4. Infrared Transmitter
6–6
D2
C2
100 µF
Table 6–4. Infrared Receiver Component Functions (Normal Transmission Mode)
DEVICE
FUNCTION
U1
TMS3637 configured as a logic normal (1-code) Q-state inverting receiver
R1
Current-limiting resistor for IR transistor Q1
R2
Base-bias resistor for Q1
R3
Collector current-limiting resistor for Q2
R4
Collector current-limiting resistor for Q3
R5
Emitter current-limiter for Q3
R6
Resistor on TIME that, in conjunction with C3, determines OUT pulse duration on U1.
R7
Resistor on OSCR that, in conjunction with C4, determines internal oscillator frequency of U1.
R8
Current-limiting resistor for LED indicator
C1
AC-coupling capacitor that passes fluctuating voltage from phototransistor Q1
C2
Power-supply bypass capacitor
C3
Capacitor on TIME that, in conjunction with R6, determines OUT pulse duration on U1.
C4
Capacitor on OSCC that, in conjunction with R7, determines the internal oscillator frequency of U1.
C5
Capacitor that determines the gain of the internal analog receive amplifier on U1.
D1
LED indicator that toggles on/off when valid code is received
VCC
+
R3
100 kΩ
C2
47 µF
R8
330 Ω
R4
10 kΩ
D1
R2
100 kΩ
R1
330 Ω
8
VCC
Q3
2N2222
C1
0.1 µF
R6
1 MΩ
Q2
2N2222
C3
470 nF
7
IN
6
5
CEX
OUT
OUT
U2 (receiver)
OSCR
1
OSCC
TIME
GND
3
4
2
Q1
NPN IR
Phototransistor
R5
2.7 kΩ
R7
100 kΩ
C4
47 pF
Figure 6–5. Infrared Receiver
6–7
6.4
Infrared Coupling of Transmitter/Receiver— Modulated Transmission
Mode
Table 6–5 lists the parts for the schematic of an infrared receiver working in the modulated continuous
configuration shown in Figure 6–6. This modulated receiver can be used with a normal infrared transmitter
(see Figure 6–4) provided that the following guide lines are observed.
The transmitter is configured as a modulated transmitter, and the content of the configuration EEPROM cells
is:
CA
1
CB
0
CC
1
CD
0
CE
0
CF
0
CG
0
CH
0
CI
0
The oscillating frequency of the transmitter must always be 120 kHz. This is accomplished by using a correct
combination of Rosc and Cosc.
The receiver is cascaded with a TDA3048 (or equivalent) to process the received signal and demodulate
it. The receiver is configured as a modulated (1-code) Q-state inverting receiver, and the content of the
EEPROM cells is:
CA
0
CB
0
CC
0
CD
0
CE
0
CF
0
CG
0
CH
0
CI
1
The receiver is used in the inverting mode. The code is considered to be inverted when using OUT on the
transmitter to transmit the code. The signal path between the transmitter and receiver does not invert the
signal; using the modulated mode (CB = 0) also does not invert the signal. The result is a signal that is
inverted at the internal logic controller of the receiver; then CI = 1 for an inverting receiver. The oscillating
frequency of the receiver is approximately 900 kHz. OUT on the receiver maintains the same status for
approximately 0.5 seconds (1M × 470 nF).
6–8
Table 6–5. Infrared Receiver Component Functions (Modulated Transmission Mode)
DEVICE
FUNCTION
U1
Demodulator TDA3048 (or equivalent)
U2
TMS3637 configured as a normal logic (1-code) Q-state inverting receiver
R1
Current-limiting resistor for U1
R2
Resistor on TIME that, in conjunction with C2, determines OUT pulse duration on U2.
R3
Resistor on OSCR that, in conjunction with C3, determines the internal oscillator frequency of U2.
R4
Power-supply current-limiting resistor
C1
Power-supply filter capacitor
C2
Capacitor on TIME that, in conjunction with R2, determines OUT pulse duration on U2.
C3
Capacitor on OSCC that, in conjunction with R3, determines the internal oscillator frequency of U2.
Q1
Infrared phototransistor for received code
D2
Diode that is used to prevent back-EMF in L2 from sourcing current to OUT.
L2
Coil of relay R1
RY1
Relay, 12 V, SPDT
VCC
R4
10 Ω
R1
22 Ω
+
12 V
C1
100 µF
D2
L2
RY1
10 kΩ
47 nF
47 nF
8
VCC
7
IN
6
5
CEX
OUT
47 nF
R2
1 MΩ
U1 (TDA3048)
Q1
47 nF
10 kΩ
1.5 nF
22 nF
C2
470 nF
U2 (receiver)
OSCR OSCC TIME
1
R2
22 kΩ
2
3
GND
4
C7
1 nF
10 nH
6.3 nF
Figure 6–6. Infrared Modulated Receiver
6–9
6.5
Radio Frequency (RF) Coupling of Transmitter and Receiver
Table 6–6 lists the parts for the schematic of a radio frequency transmitter and receiver shown in Figure 6–7.
In Figure 6–7, the transmitter is configured as a normal continuous transmitter and the content of the
configuration of the EEPROM cells is:
CA
1
CB
1
CC
1
CD
0
CE
0
CF
0
CG
0
CH
0
CI
0
The oscillating frequency of the transmitter is about 5.7 kHz, and the transmitter code is pulse modulated.
Table 6–6. RF Transmitter Component Functions
DEVICE
FUNCTION
U1
TMC3637 configured as a transmitter
R1
Resistor on OSCR that, in conjunction with C1, determines the internal oscillator frequency of U1.
R2
Base drive current-Limiting resistor for Q1
C1
Capacitor on OSCC that, in conjunction with R1, determines the internal oscillator frequency of U1.
C2
Capacitive part of LC tank circuit variable for frequency adjustment (2 pF – 10 pF)
C3
Power-supply bypass capacitor (to present low impedance to RF on VCC)
L1
Inductive part of LC tank circuit-strip-line type
L2
RF choke presents high impedance to RF between the tank and VCC.
Q1
The npn RF transistor turns on the LC circuit.
VCC
C3
10 pF
L2
10 µH
L1
8
VCC
7
IN
6
5
CEX
OUT
C2
10 pF
C4
2.2 pF
U1 (transmitter)
OSCR
OSCC
TIME
GND
1
2
3
4
R1
22 kΩ
Q1
R2
15 kΩ
C1
100 pF
S1
Figure 6–7. Radio Frequency Transmitter
Inductance L2 is an RF choke, while L1 is a strip-line 0.1-µH inductance that is 1.5-mm wide and 3.5-cm
long. The frequency range of the transmitter (tunable by C2–10 pF) is approximately 165 MHz – 370 MHz.
A good RF transistor with an HFE exceeding 500 MHz is recommended. No external antenna is required,
provided the recommended antenna is used on the receiver as described in the following paragraphs.
6–10
IN is used for the data out. IN provides the complement of the data out in the transmitter configuration.
In Figure 6–8, the receiver is configured as an analog normal noninverting VTR receiver, and the content
of the EEPROM cells is:
CA
CB
CC
CD
CE
CF
CG
CH
CI
0
1
0
0
0
0
1
0
0
The receiver is used in the noninverting mode. Using IN on the transmitter to transmit the code is considered
noninverted, but the internal analog amplifier in the receiver (CF = 0) inverts the signal. The signal path
between the transmitter and receiver also inverts the signal. The result is a signal that is noninverted at the
internal logic controller of the receiver, then C1 = 0, a noninverting receiver.
The receiver can be tuned from approximately 200 MHz – 430 MHz using the trim capacitor C4. The antenna
used is a metal wire that is 12 inches long. Inductances L1 and L2 are in the range of 0.2 µH – 2 µH.
The oscillating frequency of the receiver is 57 kHz, which is approximately ten times that of the transmitter,
and the gain of the internal analog amplifier is approximately 200. OUT on the receiver maintains the same
status for approximately 0.5 second (1M × 470 nF).
6–11
6–12
R8
RF Input
DOUT
C20
R7
C9
TRIG
C1
C8
L1
C19
R6
L4
C5
C7
BBOUT
C2
C4
R2
R1
14
2
3
4
5
8
DGND
VCC
6
7
9
R3
C10
C11
C12
AVCC
C13
10
11
6
CEX
12
1
R9
22 kΩ
R4
DVCC
R5
C16
C15
C14
Figure 6–8. TRF1400 RF Receiver and TMS3637 Decoder Circuit
5
OUT
OSCR OSCC TIME GND
2
3
DVCC
OSCC
OSCR
AGND
8
C24
470 nF
7
IN
U2 Decoder
TMS3637
R10
1 MΩ
C17
OFFSET
AGND
AVCC
AGND
AVCC
RFIN3
AGND
1
C22
100 nF
13
U1 RF Receiver
TRF1400
L3
C6
15
BBOUT
16
TRIG
RFIN1
17
DOUT
18
AGND
19
LNA1T
20
AGND
RFIN2
21
RFOUT1
SAW
Filter
22
LNA2T
RFOUT2
23
LPF
F1
24
C21
47 nF
C18
C3
L2
VCC
C23
1 nF
4
6.6
RF Receiver and Decoder
Table 6–7 lists the parts for the schematic shown in Figure 6–8. Figure 6–8 shows a Texas Instruments
TRF1400 RF receiver and a Texas Instruments TMS3637 receiver connected as an RF receiver and
decoder combination. Table 6–7 lists the components that comprise this circuit. As with any RF design, the
successful integration of these two devices relies heavily on the board layout and the quality of the external
components. This circuit demonstrates performance of the TRF1400 and TMS3637 at 300 MHz. Specified
component tolerances and, where applicable, Q should be observed during the selection of parts.
A complete set of Gerber photoplotter files for the TRF1400 circuit board can be obtained from any TI Field
Sales Office.
Table 6–7. TRF1400 RF Receiver and TCM3637 Decoder Parts List (for 300 MHz operation)
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DESIGNATORS
DESCRIPTION
VALUE
MANUFACTURER
C1
C2
MANUFACTURER P/N
Capacitor
4 pF
Murata
GRM40C0G040C050V
Capacitor
22 pF
Murata
GRM40C0G220J050BD
C3
Capacitor
22 pF
Murata
GRM40C0G220J050BD
C4
Capacitor
100 pF
Murata
GRM40C0G101J050BD
C5
Capacitor
5 pF
Murata
GRM40C0G050D050BD
C6
Capacitor
1.5 pF
Murata
GRM40C0G1R5C050BD
C7
Capacitor
100 pF
Murata
GRM40C0G101J050BD
C8
Capacitor
3 pF
Murata
GRM40C0G030C050BD
GRM40C0G180J050BD
C9
Capacitor
18 pF
Murata
C10
Capacitor
0.047 µF
Murata
GRM40X7R473K050
C11
Capacitor
2200 pF
Murata
GRM40X7R222K050BD
C12
Capacitor
2200 pF
Murata
GRM40X7R222K050BD
C13
Capacitor
0.022 µF
Murata
GRM40X7R223K050BL
C14
Capacitor, Tantalum†
4.7 µF
Sprague
293D475X9050D2T
C15
Capacitor
220 pF, 5%
Murata
GRM40C0G221J050BD
C16
Capacitor, Tantalum†
4.7 µF
Sprague
293D475X9050D2T
C17
Capacitor
2200 pF
Murata
GRM40X7R222K050BD
C18
Capacitor
0.022 µF
Murata
GRM40X7R223K050BL
C19
Capacitor
2200 pF
Murata
GRM40X7R222K050BD
C20
Capacitor
0.022 µF
Murata
GRM40X7R223K050BL
C21
Capacitor
47 µF
C22
Capacitor
100 µF
C23
Capacitor
1 nF
C24
E1§
Capacitor
470 nF
2-Pin Connector
3M
2340–6111–TN
E2§
E3§
2-Pin Connector
3M
2340–6111–TN
6-Pin Connector
3M
2340–6111–TN
S1–S2
Header shunts
SAW filter‡
3M
929952–10
RFM
RF1211
F1
† Tantalum capacitors are rated at 6.3 Vdc minimum
‡ SAW = surface acoustic wave
§ Not shown on schematic
RF1211
TI is a trademark of Texas Instruments Incorporated.
6–13
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ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Table 6–7. TRF1400 RF Receiver and TCM3637 Decoder Parts List
(for 300 MHz operation) (continued)
DESIGNATORS
DESCRIPTION
VALUE
MANUFACTURER
MANUFACTURER P/N
L1
Inductor
47 nH
Coilcraft
0805HS470TMBC
L2
Inductor
82 nH
Coilcraft
0805HS820TKBC
L3
Inductor
120 nH
Coilcraft
0805HS121TKBC
L4
Inductor
39 nH
Coilcraft
0805HS390TMBC
P1
RF SMA Connector
Johnson
142–0701–201
R1
Resistor
1200 Ω
R2
Resistor
1200 Ω
R3
Resistor
1M Ω
R4
Resistor
130 KΩ, 1%
R5
Resistor
0Ω
R6
Resistor
1 KΩ
R7
Resistor
100 Ω
R8
Resistor
1 KΩ
6.7
R9
Resistor
27 kΩ
R10
Resistor
1M Ω
U1
RF Receiver
Texas Instruments
TRF1400
U2
Decoder
Texas Instruments
TMS3637
Programming Station
A programming station schematic is shown in Figure 6–9. This station is made up of two major parts: 1)a
shift register/clock circuit that outputs exactly 35 bits serially (four reset pulses, 22 security bits, and 9
configuration bits), and 2) a transistor ramp generator that outputs the programming pulse required to store
data in the EEPROM. The following paragraphs detail the function of the circuit.
Before the momentary switch SW5 is pressed, the shift registers U9–U13 shift-load input is low so that they
are continually loading whatever code is present on the DIP switches SW1–SW4. In addition, the binary
counter U6 is in a clear state and its output is 00000000.
When momentary switch SW5 is pressed, the set-reset (S-R) latch on U1 acts as a debouncer and outputs
a logic level 1, which releases the clear on binary counter U6. It places a high on the shift input to the shift
registers
U9 – U13, allowing them to shift out the stored 35 bits as soon as a clock is applied to them. The output of
the S-R latch on U1 is also connected to the D input of the D flip-flop on U2. The D flip-flop is clocked by
the free-running 555 timer (U8) configured for astable operation on a 8-kHz clock. Therefore, on the next
rising edge of the U8 clock, the D flip-flop on U2 outputs a high signal. The output of the D flip-flop enables
the AND gate on U3 to pass the 8-kHz clock. The 8-kHz clock signal is routed to the dual 4-bit binary counters
(U6) that have had their CLR terminal released by the S-R latch (from pressing the momentary switch SW5).
The outputs of the U6 counters are connected to the counter-comparator U7, which outputs low when the
count reaches exactly 35 clock pulses (as defined by the code 11000100 on U7 Q inputs). The output of U7
then clears the D flip-flop on U2, the 8-kHz clock is no longer able to pass, and the counting stops.
During this entire counting sequence, the shift registers U9 through U13 are clocked with exactly 35 bits.
Due to the momentary switch being pressed, the S-R latch output is high on the shift-register shift enable,
allowing the registers to shift out the 35 bits of data to the code input of the TMS3637. The TMS3637 is
clocked synchronously with this data on OSCR.
Because the binary counter U6 is released from its cleared state and the U9–U13 registers are allowed to
shift data only during the time that the momentary switch is pressed, it is required that the switch be held
6–14
closed for the duration of the entire clocking sequence which is 4.4 ms or greater
(125 µs × 35 bits = 4.4 ms).
At the conclusion of the count, the one-shot timer U5 is edge triggered by the output of the
counter-comparator U7. The output from U5 enables the EEPROM programming-pulse ramp generator that
is made up of Q1 and Q2. When U5 goes high (for approximately 13 ms), transistor Q1 turns on. U5 goes
high and turns off Q2, and the voltage on OSCC of the TMS3637 is allowed to ramp from 5.5 V to 17 V using
the RC time constant established by R10 and C5. The required ramp characteristics to successfully program
the EEPROM are defined in this data manual (see Figure 3–4). After the U5 time expires, the voltage on
OSCC again returns to 5.5 V (approximately one diode drop above 5 V) and the TMS3637 is programmed.
The U5 timer normally outputs one pulse when the circuit is powered up. This is inherent of the timer device.
To prevent the timer from outputting this pulse and inadvertently programming the TMS3637, a power-on
reset RC combination is included. When power is first applied to the circuit, timer U5 remains in the clear
state until capacitor C3 can charge through resistor R6, preventing the generation of a programming pulse.
After the programming button is released, the circuit again returns to its steady-state mode where counter
U6 is held in a cleared state and the shift resisters U9 – U13 are always loaded with the current code on the
DIP switches SW1 – SW4.
6–15
5V
(A9), (B9)
U1
74LS279
5V
15
4
14
(B7) 12
74LS04
11
10
U4 B
4S
4R
3
R1
1 kΩ
6
5
3
2
1
(B8)
SW5
SPST Momentary
Push to Program
13
QA
3S2
3S1
3R
QB
2S
2R
QC
1S2
1S1
1R
QD
4Q
8 kHz
PR
D
Q
Q
U2A
7
74HC21
C6
1 µF
CK Q
CLR
4
U4 A
GND
(A1)
(B1)
(A6)
U5
74LS123
SN74ALS04
5V
5V
U8
TLC555I
R3
2.2 kΩ
C1
0.01 µF
R6
3.9 k Ω
R7
75 k Ω
Q
A
B
CLR
Q
C3
0.22 µF
C2
0.1 µF
5V
R12–R15
10 k Ω
CEXT
REXT/
CEXT
C4
0.47 µF
R5
10 k Ω
TRIG OUT
RSET
DSCH
THRES
CON
R4
7.5 kΩ
C1–C22 Security
Code (22 Bits)
RN1
10 k Ω
RN2
10 k Ω
CA–CI Conf.
Code (9 Bits)
C C C C C C C C
C C C C C C C C
C C C C C C C C
1
9 10 11 12 13 14 15 16
17 18 19 20 21 22 A B
2 3
4 5
6 7
8
SW1
SW2
UP
†
INH
U3 A
74HC74
9
D C
74HC165
U9
DN
B A SER
IN
CLK
LD
E F G H
QH
QH
UP
†
DN
H G F E D C B A SER
IN
INH
74HC164
U10
QH
CLK
QH
LD
SW3
†
UP
DN
H G F E D C B A SER
IN
INH
74HC165
U11
QH
CLK
QH
LD
† Notch in lower left corner of dip switches. Up is open = 1, down is closed = 0. All the chips are bypassed with 0.1-mF (C7 – C20) ceramic
capacitors.
Figure 6–9. Programming Station
6–16
2A
U6 B
74HC393
35
74HC682
2
4
6
8
11
13
15
17
A
QA
QB
QC
CLR QD
U6 A
74HC393
A
QA
QB
QC
CLR QD
1Q
R21, 10 k Ω
5V
R20, 10 k Ω
17 V
2Q
J1 IN: Prog
J1 OUT: Read
R19, 10 k Ω
R9
9.1 kΩ
R10
8.2 k Ω
IN414B
CR1
JP1
R8
6.2 kΩ
Q2
2N2222
Q1
2N2222
1
1
0
0
0
1
0
0
3
5
7
9
12
14
16
18
P0
P1
P2
P3
P4
P5
P6
P7
P=Q
P>Q
19
1
U7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
C5
0.1 µF
5V
RN3
10 k Ω
R16–R18
10 k Ω
C C C C C C C
C D E F G H I Unused
SW4
†
OSCC
UP
R11
1 kΩ
DN
1
2
3
4
H G F E D C B A SER
IN
INH
74HC165
U12
QH
CLK
QH
LD
H G F E D C B A SER
IN
INH
74HC165
U13
QH
CLK
QH
LD
OSCR VCC
OSCC
IN
TIME CEX
VSS OUT
8
7
6
5
TMC3637
† Notch in lower left corner of dip switches. Up is open = 1, down is closed = 0. All the chips are bypassed with 0.1-mF (C7 – C20) ceramic
capacitors.
Figure 6–9. Programming Station (continued)
6–17
6.8
TMS3637 Programming Station Parts Lists
Table 6–8 contains a listing of the parts that compose the TMS3637 programming stations (see Figure 6–9
for a schematic).
Table 6–8. TMS3637 Programming Station Parts List
PART
DESCRIPTION
FUNCTION
R1
Resistor, 1 kΩ,, 1/4 watt
R1 is an isolation resistor
R2
Resistor, 1 kΩ,, 1/4 watt
With C1 and R4, R2 sets U8 discharge time
R4
Resistor, 1 kΩ,, 1/4 watt
With C1, R2 sets U8 threshold level
R5
Resistor, 1 kΩ,, 1/4 watt
R5 is the output pullup resistor for U8
R6
Resistor, 1 kΩ,, 1/4 watt
With C3, R6 sets time constant for U5 CLR
terminal
R7
Resistor, 1 kΩ,, 1/4 watt
With C4, R7 sets time constant for U5 CERT
terminal
R8
Resistor, 1 kΩ,, 1/4 watt
R8 couples U5 dc output to base of Q2
R9
Resistor, 1 kΩ,, 1/4 watt
R9 is the load resistor for Q2
R10
Resistor, 1 kΩ,, 1/4 watt
With C5, R10 sets programming pulse ramp time
R11
Resistor, 1 kΩ,, 1/4 watt
R11 is the output pullup resistor for U14
R12 – R21
Resistor, 1 kΩ,, 1/4 watt
R12 – R21 are load resistors for the shift register
data input
RN1 – RN3
Resistor, 10 kΩ,, 1/4-watt 16-Pin DIP
RN1 – RN3 are Load resistors for the shift
register data
C1
Ceramic Capacitor, 0.01-µF
With R4, C1 sets U8 threshold level
C2
Ceramic Capacitor, 0.1-µF
C2 sets control voltage level on U8
C3
Electrolytic Capacitor, 0.22-µF
With R6, C3 prevents generation of program
pulse during initial power up
C4
Electrolytic Capacitor, 0.47-µF
With R7, C4 sets time constant for U5 CEXT
terminal
C5
Ceramic Capacitor, 0.1-µF
C5 couples high voltage programming pulse to
OSCC
C6
Electrolytic Capacitor, 1-µF
C6 is +5-V supply filter capacitor
C7 – C19
Ceramic Capacitor, 0.01-µF
C7 – C15 are bypass capacitors
U1
TI SN74LS279
Quadruple S-R Latches
The U1 latch acts as debouncer during reset
U2
TI SN74HC74
Dual D-Type
Positive-Edge-Triggered
Flip-Flops with Clear and Preset
U2 enables U3 to pass the 8-kHz clock
U3
TI SN74HC21
Dual 4-Input Positive-AND Gates
U3 is an 8-kHz gate to shift register and to U6
U4
TI SN7404
Hex Inverters
U4 is a buffer and inverter
U5
TI SN74LS123
Retriggerable Monostable
Multivibrators
U5 is a one-shot timer; its output enables
EEPROM programming pulse from Q1 and Q2
U6
TI SN47HC393
Dual 4-Bit Binary Counters
U6 is a dual binary 4-bit sequential counter
U7
TI SN74HC682
8-Bit Magnitude Counter
Comparators
U7 outputs low when the count reaches 35 clock
pulses as set by Q inputs
U8
TI TLC555I
Astable/Monostable Timer
U8 is a free-running timer (astable at 8 kHz)
U9 – U13
TI SN74HC165
Parallel-Load 8-Bit Shift Registers
U3 – U13 shift programming data into the
TMS3637
6–18
Table 6–8 TMS3637 Programming Station Parts List (continued)
PART
DESCRIPTION
FUNCTION
U14
TMC3637
Remote Control
Transmitter/Receiver
U14 transmits or receives specific
user-configuration code
Q1, Q2
TI 2N2222
npn Transistor
Q1 and Q2 are emitter followers that output the
programming pulse
CR1
1N4148
Silicon Diode
CR1 is a blocking diode when an external
oscillator is used
SW1 – SW4
16-Pin DIP switch
SW1 – SW4 select input coding
SW5
SPST Momentary Switch
SW5 when closed resets the device
6.9
TMS3637 Connector Pinout
TI recommends a ZIF socket to be used at location U14 for ease of programming the TMS3637. For
TMS3637P (DIP) packages, a 16-pin ZIF can be used (lower portion unused). For TMS3637N
surface-mount packages, use a clamshell with a latch cover and DIP footprint. This can be purchased from
EmMulation Technology (408-982-0660) part # AS-0808-015-3. The edge connector that is compatible with
the TMS3637 PCB is a Sullins part # EZC10DRTH or the equivalent as shown in Table 6–9. Ground
terminals A1, A6, and B1 are common, so only one is needed for ground connection.
Table 6–9. Edge-Connector Pinout
EDGE CONNECTOR
FUNCTION
A1
Ground
A2
N/C
A3
N/C
A4
N/C
A5
N/C
A6
Ground
A7
N/C
A8
N/C
A9
5 Vdc
A10
N/C
B1
Ground
B2
17 Vdc
B3
N/C
B4
N/C
B5
N/C
B6
N/C
B7
See Note 1
B8
See Note 1
B9
5 Vdc
B10
N/C (see Note 2)
NOTES: 1. Other edge connections are connected to various
parts of circuit. These are for testing purposes
only.
2. N/C = Not connected
6–19
6–20
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