FAIRCHILD ACE1101BVMT8X

ACE1101
Arithmetic Controller Engine (ACEx™)
for Low Power Applications
■ 16-bit multifunction timer
General Description
■ On-chip oscillator
— No external components
— 1µs instruction cycle time
The ACE1101 (Arithmetic Controller Engine) is a dedicated programmable monolithic integrated circuit for applications requiring
high performance, low power, and small size. It is a fully static part
fabricated using CMOS technology.
■ Instruction set geared for block encryption
■ On-chip power on reset
The ACE1101 has an 8-bit microcontroller core, 64 bytes of RAM,
64 bytes of data EEPROM and 1K bytes of code EEPROM. Its onchip peripherals include a multi-function 16-bit timer, watchdog/
idle timer, and programmable undervoltage detection circuitry.
On-chip clock and reset functions reduce the number of required
external components. The ACE1101 is available in an 8-pin
TSSOP package.
■ Programmable read and write disable functions
■ Memory mapped I/O
■ Multilevel Low Voltage Detection
■ Fully static CMOS
— Low power HALT mode (100nA @3.3V)
— Power saving IDLE mode
— Single supply operation (2.0-5.5V, 2.2-5.5V, 2.7-5.5V))
Features
■ 1K bytes on-board code EEPROM
■ Software selectable I/O options
— Push-pull outputs with tri-state option
— Weak pull-up or high impedance inputs
■ 64 bytes data EEPROM
■ 40 years data retention
■ 64 bytes RAM
■ 1,000,000 data changes
■ Watchdog
■ 8-pin TSSOP package
■ Multi-input wake-up all I/O pins
■ In-circuit programming
■ Arithmetic Controller Engine
Block and Connection Diagram
VCC
Power-on
Reset
Internal
Oscillator
Low Battery/Brown-out
Detect
Watchdog/
12-Bit Timer 0
GND
* 100nf Decoupling capacitor
recommended
G0 (CKO)
G1 (CKI)
G2 (T1)
G3(Input only)
G4
G5
© 1999 Fairchild Semiconductor Corporation
ACE1101 Rev. C.8
G port
general
purpose
I/O
with
multiinput
wakeup
16-Bit Timer 1
ACEx
Control
Unit
HALT/IDLE
Power saving
Modes
Programming
Interface
RAM block
64 bytes
1K bytes of CODE
EEPROM
64 bytes of DATA
EEPROM
1
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
PRELIMINARY
May 1999
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Input Voltage not including G3
-0.3V to VCC+0.3V
G3 Input Voltage
Ambient Operating Temperature:
ACE1101
ACE1101E
0.3V to 13V
Lead Temperature (10s max)
Electrostatic Discharge on all pins
0°C to 70°C
-40°C to +85°C
Operating Supply Voltage:
From -40°C to 85°C:
+300°C
2.2V to 5.5V
See table for EEPROM write limits
2000V min
Relative Humidity (non-condensing)
95%
ACE1101 DC Electrical Characteristics for VCC = 2.2 to 5.5V
All measurements valid for ambient operating temperature range unless otherwise stated.
Symbol
Parameter
Conditions
MIN
TYP
MAX
Units
0.5
1.0
1.6
1.0
1.5
2.0
mA
mA
mA
ICC
Supply Current –
no EEPROM write in
progress
2.2V
3.3V
5.5V
ICCH
HALT Mode current
3.3V, -40°C to 25°C
5.5V, -40°C to 25°C
3.3V, 25°C to +85°C
5.5V, 25°C to +85°C
3.3V, -40°C to +125°C
5.5V, -40°C to +125°C
10
200
50
400
350
1200
100
1000
1000
2500
5000
8000
nA
nA
nA
nA
nA
nA
ICCI
IDLE Mode Current
5.5V
3.3V
120
100
250
150
µA*
µA*
VCCW
EEPROM Write Voltage
Code EEPROM in
Programming Mode
4.5
5.0
5.5
V
Data EEPROM in
Operating Mode
2.4
5.5
V
10ms/V
SVCC
Power Supply Slope
1us/V
VIH
VIL
Inputs
Logic High
Logic Low
0.8VCC
IIP
Input Pull-up Current
VCC=5.5V, VIN=0V
ITL
TRI-STATE Leakage
VCC=5.5V
VOL
Output Low Voltage - VOL
G0, G1, G2, G4, G6, G7
G5
VOH
Output High Voltage - VOH
G0, G1, G2, G4, G6, G7
G5
0.2 VCC
V
V
65
350
µA
2
200
nA
VCC= 3.3V – 5.5V
5.0 mA sink
10.0 mA sink
0.2 VCC
0.2 VCC
V
V
VCC= 2.2V – 3.3V
3.0 mA sink
5.0 mA sink
0.2 VCC
0.2 VCC
V
V
30
VCC= 3.3V – 5.5V
0.4 mA source
1.0 mA source
0.8 VCC
0.8 VCC
V
V
VCC= 2.2V – 3.3V
0.4 mA source
0.8 mA source
0.8 VCC
0.8 VCC
V
V
* Based on continuous IDLE looping.
2
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Absolute Maximum Ratings
Parameter
Conditions
MIN
TYP
MAX
Units
0.9
1.00
1.1
µs
Instruction cycle time from
internal clock - setpoint
5.0V at 25°C
Internal clock voltage dependent
frequency variation
3.0V to 5.5V,
constant temperature
±5%
Internal clock temperature
dependent frequency variation
3.0V to 5.5V,
full temperature range
±10%
Internal clock frequency
deviation for 0.5V drop
3.0V to 4.5V for
ACE1101E, T=constant
±2%
Crystal oscillator frequency
(Note 1)
4
MHz
External clock frequency
(Note 2)
4
MHz
EEPROM write time
10
ms
Internal clock start up time
(Note 2)
3
2
ms
Oscillator start up time
(Note 2)
2400
cycles
Note 1: The maximum permissible frequency is guaranteed by design but not 100% tested.
Note 2: The parameter is guaranteed by design but not 100% tested.
ACE1101 Electrical Characteristics for programming
All data valid at ambient temperature between 4.5V and 5.5V. See “EEPROM write time” in the AC
characteristics for definition of the programming ready time. The following characteristics are guaranteed
by design but are not 100% tested.
Parameter
Description
MIN
MAX
Units
tHI
CLOCK high time
500
DC
ns
tLO
CLOCK low time
500
DC
ns
tDIS
SHIFT_IN setup time
100
ns
tDIH
SHIFT_IN hold time
100
ns
tDOS
SHIFT_OUT setup time
100
ns
tDOH
SHIFT_OUT hold time
900
ns
tSV1, tSV2
LOAD supervoltage timing
50
us
tLOAD1, tLOAD2, tLOAD3, tLOAD4
LOAD timing
VSUPERVOLTAGE
Supervoltage level
5
11.5
3
ACE1101 Rev. C.8
us
12.5
V
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Preliminary ACE1101 AC Electrical Characteristics for VCC = 2.2 to 5.5V
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Input Voltage not including G3
-0.3V to VCC+0.3V
G3 Input Voltage
Ambient Operating Temperature:
ACE1101B
ACE1101BE
ACE1101BV
0.3V to 13V
Lead Temperature (10s max)
Electrostatic Discharge on all pins
0°C to 70°C
-40°C to +85°C
-40°C to +125°C
Operating Supply Voltage:
From -40°C to 125°C:
+300°C
2000V min
2.7V to 5.5V
See table for EEPROM write limits
Relative Humidity (non-condensing)
95%
ACE1101B DC Electrical Characteristics for VCC = 2.7 to 5.5V
All measurements valid for ambient operating temperature range unless otherwise stated.
Symbol
Parameter
Conditions
MIN
TYP
MAX
Units
0.7
1.0
1.6
1.2
1.5
2.0
mA
mA
mA
ICC
Supply Current –
no EEPROM write in
progress
2.7V
3.3V
5.5V
ICCH
HALT Mode current
3.3V, -40°C to 25°C
5.5V, -40°C to 25°C
3.3V, 25°C to +85°C
5.5V, 25°C to +85°C
3.3V, -40°C to +125°C
5.5V, -40°C to +125°C
10
200
50
400
350
1200
100
1000
1000
2500
5000
8000
nA
nA
nA
nA
nA
nA
ICCI
IDLE Mode Current
5.5V
3.3V
120
100
250
150
µA*
µA*
VCCW
EEPROM Write Voltage
Code EEPROM in
Programming Mode
4.5
5.0
5.5
V
Data EEPROM in
Operating Mode
2.7
5.5
V
10ms/V
SVCC
Power Supply Slope
1us/V
VIH
VIL
Inputs
Logic High
Logic Low
0.8VCC
IIP
Input Pull-up Current
VCC=5.5V, VIN=0V
ITL
TRI-STATE Leakage
VCC=5.5V
VOL
Output Low Voltage - VOL
G0, G1, G2, G4, G6, G7
G5
VOH
Output High Voltage - VOH
G0, G1, G2, G4, G6, G7
G5
0.2 VCC
V
V
65
350
µA
2
200
nA
VCC= 3.3V – 5.5V
5.0 mA sink
10.0 mA sink
0.2 VCC
0.2 VCC
V
V
VCC= 2.7V – 3.3V
3.0 mA sink
5.0 mA sink
0.2 VCC
0.2 VCC
V
V
30
VCC= 3.3V – 5.5V
0.4 mA source
1.0 mA source
0.8 VCC
0.8 VCC
V
V
VCC= 2.7V – 3.3V
0.4 mA source
0.8 mA source
0.8 VCC
0.8 VCC
V
V
* Based on continuous IDLE looping.
4
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Absolute Maximum Ratings
Parameter
Conditions
MIN
TYP
MAX
Units
0.9
1.00
1.1
µs
Instruction cycle time from
internal clock - setpoint
5.0V at 25°C
Internal clock voltage dependent
frequency variation
3.0V to 5.5V,
constant temperature
±5%
Internal clock temperature
dependent frequency variation
3.0V to 5.5V,
full temperature range
±10%
Internal clock frequency
deviation for 0.5V drop
3.0V to 4.5V for
ACE1101BE, T=constant
±2%
Crystal oscillator frequency
(Note 1)
4
MHz
External clock frequency
(Note 2)
4
MHz
10
ms
EEPROM write time
3
Internal clock start up time
(Note 2)
2
ms
Oscillator start up time
(Note 2)
2400
cycles
Note 1: The maximum permissible frequency is guaranteed by design but not 100% tested.
Note 2: The parameter is guaranteed by design but not 100% tested.
ACE1101B Electrical Characteristics for programming
All data valid at ambient temperature between 4.5V and 5.5V. See “EEPROM write time” in the AC
characteristics for definition of the programming ready time. The following characteristics are guaranteed
by design but are not 100% tested.
Parameter
Description
MIN
MAX
Units
tHI
CLOCK high time
500
DC
ns
tLO
CLOCK low time
500
DC
ns
tDIS
SHIFT_IN setup time
100
ns
tDIH
SHIFT_IN hold time
100
ns
tDOS
SHIFT_OUT setup time
100
ns
tDOH
SHIFT_OUT hold time
900
ns
tSV1, tSV2
LOAD supervoltage timing
50
us
tLOAD1, tLOAD2, tLOAD3, tLOAD4
LOAD timing
5
us
VSUPERVOLTAGE
Supervoltage level
11.5
5
ACE1101 Rev. C.8
12.5
V
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Preliminary ACE1101B AC Electrical Characteristics for VCC = 2.7 to 5.5V
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Input Voltage not including G3
-0.3V to Vcc+0.3V
G3 Input Voltage
Operating Supply Voltage excluding EEPROM write:
0°C to +70°C
2.0V to 5.5V
(based on preliminary data)
0.3V to 13V
Lead Temperature (10s max)
Electrostatic Discharge on all pins
Relative Humidity (non-condensing)
95%
+300°C
2000V min
Preliminary ACE1101L DC Electrical Characteristics for VCC = 2.0 to 5.5V
All measurements valid for ambient operating temperature range unless otherwise stated.
Symbol
Parameter
Conditions
MIN
TYP
MAX
Units
ICC
Supply Current –
no EEPROM write in
progress
2.0V
0.4
0.5
mA
ICCH
HALT Mode Current
2.0V, 0°C to 70°C
10
100
nA
ICCI
IDLE Mode Current
2.0V
30
50
µA
VCCW
EEPROM Write Voltage
Write Not Allowed for
VCC < 2.4V
SVCC
Power Supply Slope
VIH
VIL
Inputs
Logic High
Logic Low
IIP
Input Pull-up Current
VCC=5.5V, VIN=0V
ITL
TRI-STATE Leakage
VCC=5.5V
VOL
Output Low Voltage
G0, G1, G2, G4, G6, G7
G5
VOH
1us/V
10ms/V
0.8 VCC
0.2 VCC
V
V
65
350
µA
2
200
nA
VCC= 3.3V – 5.5V
5.0 mA sink
10.0 mA sink
0.2 VCC
0.2 VCC
V
V
G0, G1, G2, G4, G6, G7
G5
VCC= 2.0V – 3.3V
0.8 mA sink
10.0 mA sink
0.36 VCC
0.36 VCC
V
V
Output High Voltage
G0, G1, G2, G4, G6, G7
G5
VCC= 3.3V – 5.5V
0.4 mA source
1.0 mA source
0.8 VCC
0.8 VCC
V
V
G0, G1, G2, G4, G6, G7
G5
VCC= 2.0V – 3.3V
0.1 mA source
0.2 mA source
1.44 VCC
1.44 VCC
V
V
6
ACE1101 Rev. C.8
V
30
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Absolute Maximum Ratings
Parameter
Conditions
MIN
TYP
MAX
Units
0.9
1.00
1.1
µs
Instruction cycle time from
internal clock - setpoint
5.0V at 25°C
Internal clock voltage dependent
frequency variation
3.0V to 5.5V,
constant temperature
±5%
Internal clock temperature
dependent frequency variation
3.0V to 5.5V,
full temperature range
±10%
Internal clock frequency
deviation for 0.5V drop
3.0V to 4.5V for
ACE1101E, T=constant
±2%
Crystal oscillator frequency
(Note 1)
4
MHz
External clock frequency
(Note 2)
4
MHz
EEPROM write time
10
ms
Internal clock start up time
(Note 2)
5
2
ms
Oscillator start up time
(Note 2)
2400
cycles
Note 1: The maximum permissible frequency is guaranteed by design but not 100% tested.
Note 2: The parameter is guaranteed by design but not 100% tested.
7
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Preliminary ACE1101L AC Electrical Characteristics for VCC = 2.0 to 5.5V
ACE1101 AC & DC Characteristic Graphs
The graphs in this section are for design guidance and are based on prelimintest data
Frequency (MHz)
Figure 2: RC Oscillator Frequency (VCC=5.0V)
2.600
2.400
2.200
2.000
1.800
1.600
1.400
1.200
1.000
Avg
Min
Max
3.3k/82pF
5.6k/100pF
6.8K/100pF
Resistor & Capacitor Values [k & pF]
Figure 3: RC Oscillator Frequency (VCC=2.5V)
Frequency (MHz)
1.600
1.400
Avg
Min
Max
1.200
1.000
0.800
0.600
3.3k/82pF
5.6k/100pF
6.8K/100pF
Resistor & Capacitor Values [k & pF]
Figure 4: Internal Oscillator Frequency
Frequency (KHz)
2200
5.0V
5.5V
2000
4.5V
1800
4.0V
3.5v
1600
-45
-5
25
90
130
2.2V
Temperature [°C]
8
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
3.0
ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 5: Power Supply Rise Time
VCC
VBATT
1V
tS min
tS actual
Name
tS max
Parameter
Unit
VCC
Supply Voltage
[V]
VBATT
Battery Voltage (Nominal Operating Voltage)
tS min
Minimum Time for VCC to Rise by 1V
[ms]
tS actual
Actual Time for VCC to Rise by 1V
[ms]
tS max
Maximum Time for VCC to Rise by 1V
[ms]
SVCC
Power Supply Slope
[V]
[ms/V]
9
ACE1101 Rev. C.8
time
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Current (mA)
0.520
0.500
0.480
0.460
0.440
0.420
0.400
0.380
Vcc=3.0V
130
95
25
-5
-20
-45
Current (mA)
Temperature [°C]
1.110
1.100
1.090
1.080
1.070
1.060
1.050
1.040
Vcc=4.5V
130
95
25
-5
-20
-45
Temperature [°C]
Current (mA)
1.340
1.320
1.300
Vcc=5.0V
1.280
1.260
1.240
130
95
25
-5
-20
-45
Current (mA)
Temperature [°C]
1.600
1.580
1.560
1.540
1.520
1.500
1.480
1.460
1.440
Vcc=5.5V
130
95
25
-5
-20
-45
Temperature [°C]
10
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 6: ICC Active
HALT Current (nA)
350
300
250
200
Vcc=3.3V
150
100
50
0
130
95
25
-5
Temperature [°C]
HALT Current (nA)
1400
1200
1000
800
Vcc=5.5V
600
400
200
0
130
95
25
-5
Temperature [°C]
11
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 7: HALT Current
[µ ]
Current (µA)
90
80
70
60
50
40
30
20
10
0
Vcc=2.2V
85
25
-40
Temperature [°C]
110
Current (µA)
105
100
95
Vcc=3.3V
90
85
80
75
85
25
-40
Temperature [°C]
130
Current (µµA)
125
120
Vcc=5.5V
115
110
105
100
85
25
-40
Temperature [°C]
12
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 8: IDLE Current
VCC
Optional
LED
G4
VCC
G3
G0
RF Interface
G5
G1
GND
RF Stage
G2
Figure 10: ACE1101 Pinout – Normal Operation
Figure 11: ACE1101 Pinout – Programming Mode
G3
1
8
VCC
LOAD
1
8
VCC
G4
2
7
GND
SFT_I
2
7
GND
G5
3
6
G2
G5
3
6
SFT_O
G0
4
5
G1
GO
4
5
CKI
*Note: 100 nf Decoupling capacitor recommended.
13
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 9: ACE1101 Application Example (Remote Keyless Entry)
The ACE1101 core is specifically designed for low cost applications involving bit manipulation, shifting and block encryption. It is
based on a modified Harvard architecture meaning peripheral,
I/O, and RAM locations are addressed separately from instruction
data.
4.1 CPU Registers
The ACE1101 has five general purpose registers. They are the A,
X, PC, SP, and SR. The X, SP and SR are memory mapped
registers.
The core differs from the traditional Harvard architecture by
aligning the data and instruction memory sequentially. This allows
the X-pointer (11-bits) to point to any memory location in either
Figure 12: Programming Model
7
A
0
8-bit accumulator register
X
10
0
11-bit X pointer register
PC
9
0
10-bit program counter
0
4-bit stack pointer
SP
SR
3
8-bit status register
R 0 0GZCHN
NEGATIVE flag
HALF CARRY flag (from bit 3)
CARRY flag (from MSB)
ZERO flag
GLOBAL Interrupt Mask
READY flag (from EEPROM)
14
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
segment of the memory map. This modification improves the
overall code efficiency of the ACE1101 and takes advantage of
the flexibility found on Von Neumann style machines.
4.0 Arithmetic Controller Core
Zero (Z)
Accumulator A is general-purpose 8-bit register that holds operands and results of arithmetic calculations or data manipulations.
The Z bit is set if the result of an arithmetic, logic, or data
manipulation operation is zero. Otherwise, the Z bit is cleared.
4.1.2 X Pointer
Negative (N)
The X register provides an 11-bit indexing value that can be added
to an 8-bit offset provided in an instruction to create an effective
address. The X register can also be used as a counter or as a
temporary storage register.
The N bit is set if the result of an arithmetic, logic, or data manipulation
operation is negative (MSB = 1). Otherwise, the N bit is cleared. A
result is said to be negative if its most significant bit (MSB) is a one.
Interrupt Mask (G)
4.1.3 Program Counter (PC)
The interrupt request mask (G) is a global mask that disables all
maskable interrupt sources. Until the G bit is set, interrupts can become
pending, but the operation of the CPU continues uninterrupted. After
any reset, the G bit is cleared by default and can only be set by a
software instruction. When an interrupt is recognized, the G bit is
cleared after the PC is stacked and the interrupt vector is fetched. After
the interrupt is serviced, a return from interrupt instruction is normally
executed to restore the PC to the value that was present before the
interrupt occurred. The G bit is set after a return from interrupt is
executed. Although the G bit can be set within an interrupt service
routine, “nesting” interrupts in this way should only be done when there
is a clear understanding of latency and of the arbitration mechanism.
The program counter, a 10-bit register, contains the address of the
next instruction to be executed. After reset, the program counter
is initialized to 0xC00 in normal mode.
4.1.4 Stack Pointer (SP)
The ACE1101 has an automatic program stack. This stack can be
initialized to any location between addresses 0x30-0x3F. By
default, the stack is initialized to 0x3F. Normally, the SP is
initialized by one of the first instructions in an application program.
The stack is configured as a data structure that decrements from
high memory to low memory. Each time a new address is pushed
onto the stack, the SP is decremented by two. Each time an
address is pulled from the stack, the SP is incremented by two. At
any given time, the SP points to the next free location in the stack.
4.2 Interrupt handling
When an interrupt is recognized, the current instruction completes its
execution. The return address (the current value in the program
counter) is pushed onto the stack and execution continues at the
address specified by the unique interrupt vector (see Table 9). This
process takes five instruction cycles. At the end of the interrupt
service routine, a RETI instruction is executed. The RETI instruction
causes the saved address to be pulled off the stack in reverse order.
The G bit is set and program execution resumes at the return address.
When a subroutine is called by a jump to subroutine (JSR), the
address of the instruction, after the JSR instruction, is automatically pushed onto the stack least significant byte first. When the
subroutine is finished, a return from subroutine (RET) instruction
is executed. The RET pulls the previously stacked return address
from the stack, and loads it into the program counter. Execution
then continues at this recovered return address.
The ACE1101 is capable of supporting four interrupts. Three are
maskable through the G bit of the Status register and the fourth
(software interrupt) is not inhibited by the G bit (see Figure 13). (See
Table 6 for the interrupt priority sequence.) The software interrupt
instruction is executed in a manner similar to other maskable
interrupts in that the program counter registers are stacked. However, with a software interrupt, the G bit is not effected. This means,
when returning from a software interrupt, a RET instruction should
be used rather than using the RETI instruction. The RETI instruction
will set the G bit.
4.1.5 Status Register (SR)
This 8-bit register contains four condition code indicators (C, H, Z,
and N), one interrupt masking bit (G), and an EEPROM write flag
(R). In the ACE1101, condition codes are automatically updated
by most instructions.
Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (ALU) performs a carry
or borrow during an arithmetic operation. The rotate instruction
operates with and through the carry bit to facilitate multiple-word
shift operations. The LDC and INVC instructions facilitate direct bit
manipulation using the carry flag.
4.3 Addressing Modes
The ACE1101 has seven addressing modes.
Half Carry (H)
Indexed
The half carry flag indicates whether an overflow has taken place
on the boundary between the two nibbles in the accumulator. It is
primarily used for BCD arithmetic calculation.
In this addressing mode, a 8-bit unsigned offset value is added to
the X-pointer yielding a new effective address. This mode can be
used to address any memory location (Instruction or Data).
Indirect
This is the “normal” addressing mode. The operand is the data
memory addressed by the X-pointer.
Table 6: Interrupt Priority Sequence
Interrupt
Priority (4 highest, 1 lowest)
MIW
4
Timer0
3
Timer1
2
Software
1
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.1.1 Accumulator
ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 13: ACE1101 Basic Interrupt Structure
Int. Source & Priority
SW
T1
T0
MiWu
GIE
Int. Pend. Flags
Int. Enable Bits
Global Int. Enable
16
ACE1101 Rev. C.8
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Absolute
The instruction contains an 8-bit address field that directly points
to the data memory for the operand.
This mode is used with the JMP and JSR instructions, with the
instruction field replacing the 10-bits in the program counter. This
allows jumping to any location in the memory map.
Immediate
Relative
The instruction contains an 8-bit immediate field as the operand.
This mode is used for the JP and the bit manipulation instructions,
where the instruction field being added to the program counter to
get the new program location.
Inherent
This instruction has no operand associated with it.
Table 7: Instruction Addressing Modes
Instruction
Immediate
Direct
Indexed
Indirect
ADC
A, #
A, M
A, [X]
ADD
A, #
A, M
A, [X]
AND
A, #
A, M
A, [X]
OR
A, #
A, M
A, [X]
SUBC
A, #
A, M
A, [X]
XOR
A, #
A, M
A, [X]
CLR
M
A
X
INC
M
A
X
DEC
M
A
X
IFEQ
A, #
X, #
IFGT
A, #
X, #
IFNE
A, #
IFLT
M,#
A, M
A, [X]
A, M
A, [X]
A, M
A, [X]
Inherent
no-op
RC
no-op
IFC
no-op
IFNC
no-op
INVC
no-op
LDC
#, M
STC
#, M
RLC
M
A
RRC
M
A
A, M
A, [00,X]
A, [X]
ST
A, M
A, [00,X]
A, [X]
LD
M, M
A, #
X, #
M, #
NOP
IFBIT
no-op
#, A
#, M
SBIT
#, M
#, [X]
RBIT
#, M
#, [X]
JP
Rel
JSR
M,M+1
JMP
M,M+1
RET
no-op
RETI
no-op
INTR
no-op
17
ACE1101 Rev. C.8
Absolute
X, #
SC
LD
Relative
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Direct
Mnemonic Operand Bytes Cycles
Flags
affected
Mnemonic Operand Bytes Cycles
ADC
A, [X]
1
1
C,H,Z,N
JMP
ADC
A, M
2
2
C,H,Z,N
JP
ADC
A, #
2
2
C,H,Z,N
JSR
ADD
A, [X]
1
1
Z,N
ADD
A, M
2
2
Z,N
ADD
A, #
2
2
Z,N
AND
A, [X]
1
1
AND
A, #
2
AND
A, M
CLR
CLR
3
4
None
1
1
None
M, M+1
3
5
None
LD
A, #
2
2
None
LD
A, [00,X]
2
3
None
LD
A, [X]
1
1
None
Z,N
LD
A, M
2
2
None
2
Z,N
LD
M, #
3
3
None
2
2
Z,N
LD
X, #
3
3
None
X
1
1
Z
LDC
#, M
2
2
C
A
1
1
Z,N,C
LD
M, M
3
3
None
CLR
M
2
1
Z,N,C
NOP
1
1
None
DEC
A
1
1
Z,N
OR
A, #
2
2
Z,N
DEC
M
2
2
Z,N
OR
A, [X]
1
1
Z,N
DEC
X
1
1
Z
OR
A, M
2
2
Z,N
IFBIT
#, A
1
1
None
RBIT
#, [X]
1
2
Z,N
IFBIT
#, M
2
2
None
RBIT
#, M
2
2
Z,N
1
1
None
IFC
M, M+1
Flags
affected
RC
1
1
C
IFEQ
A, [X]
1
1
None
RET
1
5
None
IFEQ
A, #
2
2
None
RETI
1
5
None
IFEQ
A, M
2
2
None
RLC
A
1
1
C,Z,N
IFEQ
M, #
3
3
None
RLC
M
2
2
C,Z,N
IFEQ
X, #
3
3
None
RRC
A
1
1
C,Z,N
IFGT
A, #
2
2
None
RRC
M
2
2
C,Z,N
IFGT
A, [X]
1
1
None
SBIT
#, [X]
1
2
Z,N
IFGT
A, M
2
2
None
SBIT
#, M
2
2
Z,N
IFGT
X, #
3
3
None
SC
1
1
C
IFNE
A, #
2
2
None
ST
A, [00,X]
2
3
None
IFNE
A, [X]
1
1
None
ST
A, [X]
1
1
None
IFNE
A, M
2
2
None
ST
A, M
2
2
None
IFLT
X, #
3
3
None
STC
#, M
2
2
Z,N
1
1
None
IFNC
SUBC
A, #
2
2
C,H,Z,N
INC
A
1
1
Z,N
SUBC
A, [X]
1
1
C,H,Z,N
INC
M
2
2
Z,N
SUBC
A, M
2
2
C,H,Z,N
INC
X
1
1
Z
XOR
A, #
2
2
Z,N
INTR
1
5
None
XOR
A, [X]
1
1
Z,N
INVC
1
1
C
XOR
A, M
2
2
Z,N
18
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Table 8: Instruction Cycles and Bytes
All I/O ports, peripheral registers and core registers, except the accumulator and the program counter are mapped into memory space.
Table 9: Memory Map
Address
Block
Contents
0x00 - 0x3F
SRAM
Data RAM
0x40 - 0x7F
Data EEPROM
Non-volatile parameters
0xAA
Timer1
T1RALO register
0xAB
Timer1
T1RAHI register
0xAC
Timer1
TMR1LO register
0xAD
Timer1
TMR1HI register
0xAE
Timer1
T1CNTRL register
0xAF
MIWU
WKEDG register
0xB0
MIWU
WKPND register
0xB1
MIWU
WKEN register
0xB2
I/O
PORTGD register
0xB3
I/O
PORTGC register
0xB4
I/O
PORTGP register
0xB5
Timer0
WDSVR register
0xB6
Timer0
T0CNTRL register
0xB7
Clock
HALT mode register
0xB8 - 0xBC
Reserved
0xBD
LBD
LBD register
0xBE
Core
XHI register
0xBF
Core
XLO register
0xC0
Core
Power mode clear (PMC) register
0xCE
Core
SP register
0xCF
Core
Status register
0xC00 - 0xFF5
Code EEPROM/ROM
Instruction data
0xFF6 - 0xFF7
Core
Timer0 Interrupt vector
0xFF8 - 0xFF9
Core
Timer1 Interrupt vector
0xFFA - 0xFFB
Core
MIWU Interrupt vector
0xFFC - 0xFFD
Core
Software Interrupt vector
0xFFE - 0xFFF
Reserved
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.4 Memory Map
The ACE1101 device has 64 bytes of SRAM and 64 bytes of
EEPROM available for data storage. The microcontroller also has
a 1K byte EEPROM block for program storage. The user can read/
write to RAM and data EEPROM but cannot perform writes to the
1K byte EEPROM array which is protected from writes during
normal mode operations. The instruction data in the program
EEPROM array can only be rewritten when the device is in
program mode and if the initialization register bit WDIS (write
disable) is not set.
4.6 Initialization Registers
The ACE1101 has two 8-bit wide initialization registers. These
registers are read from memory space on power-up and initializes
certain on-chip peripherals. Figure 14 provides a detailed description of Initialization Register 1. The Initialization Register 2 is used
to trim the internal oscillator. This register is pre-programmed in
the factory to yield a 1MHz internal clock.
While in normal mode, the user can write to the data EEPROM
array by 1) polling the R bit of the status register, then 2) executing
the appropriate write instruction. A "1" on the R bit indicates the
data EEPROM block is ready to perform the next write. A "0"
indicates the data EEPROM is busy. The data EEPROM array will
Both Initialization Registers 1 and 2 are read/writable in programming mode. However, retrimming the internal oscillator (writing to
the Initialization Register 2) is discouraged.
Figure 14: Initialization Register 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMODE0
CMODE1
WDEN
BOREN
LBDEN
UBD
WDIS
RDIS
(0) RDIS
If set, disables attempts to read any EEPROM contents in programming mode
(1) WDIS
If set, disables attempts to write any EEPROM contents in programming mode
(2) UBD
If set, the device will not allow writes to occur in the upper block of data EEPROM
(3) LBDEN
1 enables LBD, 0 disables LBD
(4) BOREN
If set, allows a brown-out reset to occur if Vcc is so low that a reliable
EEPROM write cannot take place
(5) WDEN
If set, enables the on-chip processor watchdog circuit
(6) CMODE1
Clock mode select bit one
(7) CMODE0
Clock mode select bit zero
Note 1: If WDIS and RDIS bits are both set, the device will no longer be able to be placed into program mode.
Note 2: If the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits could be reset.
20
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
reset the R bit on the completion of a write cycle. Attempts to read,
write, or enter HALT while the data EEPROM is busy (R bit = "0")
could affect the current data being written.
4.5 Memory
Timer1 is a versatile 16-bit timer which can operate in one of three
modes:
• Pulse Width Modulation (PWM) mode, which generates
pulses of a specified width and duty cycle
• External Event Counter mode, which counts occurrences
of an external event
There is one interrupt associated with the timer, designated the
Timer1 interrupt. When timer interrupt is enabled, the source of the
interrupt depends on the timer operating mode: either a timer
underflow, or a transfer of data to or from the T1RA register. By
default, the timer register is reset to FFFF and the reload register
is reset to 0000.
• Standard Input Capture mode, which measures the
elapsed time between occurrences of external events
Timer1 contains a 16-bit timer (counter) register, designated
TMR1, and one 16-bit autoreload (capture) register, designated
T1RA. These 16-bit registers are organized as a pair of 8-bit
memory mapped register bytes, TMR1HI and TMR1LO, and
T1RAHI and T1RALO.
5.1 Timer control bits
Timer1 is controlled by reading and writing to the T1CNTRL
register. By programming the control bits, the user can enable or
disable the timer interrupts, set the operating mode, and start or
stop the timer. The control bits operate as described in Tables 10
and 11.
The timer (counter) block uses one I/O pin, designated T1, which
is the alternate function of G2.
Table 10: TIMER1 Control Register Bits
T1CNTRL Register
Name
Function
Bit 7
T1C3
Timer TIMER1 control bit 3 (see Table 9)
Bit 6
T1C2
Timer TIMER1 control bit 2 (see Table 9)
Bit 5
T1C1
Timer TIMER1 control bit 1 (see Table 9)
Bit 4
T1C0
Timer TIMER1 run: 1 = Start timer, 0 = Stop timer;
or Timer TIMER1 underflow interrupt pending flag
in input capture mode
Bit 3
T1PND
Timer1 interrupt pending flag: 1 = Timer1 interrupt
pending, 0 = Timer1 interrupt not pending
Bit 2
T1EN
Bit 1
-----------
Reserved
Bit 0
-----------
Reserved
Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,
0 = Timer1 interrupt disabled
Table 11: TIMER1 Operating Modes
T1
C3
T1
C2
T1
C1
Timer Mode
Interrupt A
Source
0
0
0
MODE 2
TIMER1 Underflow
T1 Pos. Edge
0
0
1
MODE 2
TIMER1 Underflow
T1 Neg. Edge
1
0
1
MODE 1 T1 Toggle
Autoreload T1RA
Instruction Clock
1
0
0
MODE 1 No T1 Toggle
Autoreload T1RA
Instruction Clock
0
1
0
MODE 3 Captures: T1 Pos. edge
Pos. T1 Edge
Instruction Clock
0
1
1
MODE 3 Captures: T1 Neg. Edge
Neg. T1 Edge
Instruction Clock
21
ACE1101 Rev. C.8
Timer Counts On
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
The timer can be started or stopped under program control. When
running, the timer counts down (decrements). Depending on the
operating mode, the timer counts either instruction clock cycles or
transitions on the T1 pin. Occurrences of timer underflows (transitions from 0x0000 to 0xFFFF) can either generate an interrupt
and/or toggle the T1 pin, also depending on the operating mode.
5.0 Timer 1
The following steps can be used to operate the timer in the PWM
mode. In this example, the T1 output pin is toggled with every
timer underflow, and the “high” and “low” times for the T1 output
can be set to different values. The T1 output can start out either
high or low; the instructions below are for starting with the T1
output high. (Follow the instructions in parentheses to start the
T1 output low.)
In the Pulse Width Modulation (PWM) mode, the timer counts down
at the instruction clock rate. When an underflow occurs, the timer
register is reloaded from T1RA, and decrementing proceeds from
the loaded value. At every underflow interrupt, software should load
the T1RA register with the alternate PWM value.
The timer can be configured to toggle the T1 output bit upon
underflow. This results in the generation of a clock signal on T1 with
the width and duty cycle controlled by the values stored in the T1RA.
1. Configure the T1 pin as an output by setting bit 2 of
PORTGC.
2. Initialize the T1 pin value to 1 (or 0) by setting (or clearing)
bit 2 of PORTGD.
A block diagram of the timer operating in the PWM mode is shown
In Figure 15.
3. Load the PWM “high” or “low” time into the timer register.
There is one interrupt associated with the timer, designated the
Timer1 interrupt. The interrupt is maskable by the enable bit T1EN.
T1 will generate an interrupt with every timer underflow if the timer
interrupt is enabled by T1EN. The interrupt will be simultaneous
with every rising and falling edge of the PWM output. Generating
interrupts only on rising-, or falling edges of T1 is achievable
through appropriate handling of T1EN by the user software.
4. Load the PWM “low” or “high” time into the T1RA register.
5. Write the appropriate value to the timer control bits T1C3T1C2- T1C1 to select the PWM mode, and to toggle the T1
output with every timer underflow (see Table 11).
6. Set the T1C0 bit to start the timer.
7. Upon every underflow interrupt load T1RA with alternate
values, ON or OFF time.
When an underflow occurs that causes a timer reload from T1RA,
the interrupt pending flag bit T1PNDA is set. A CPU interrupt occurs
if T1EN bit and the G (Global Interrupt enable) bit of the Status
register is set. The interrupt service routine must reset the pending
bit and perform whatever processing is necessary at the interrupt
point.
If the user wishes to generate an interrupt on timer output
transitions, reset the pending flags and then enable the interrupt
using T1EN. The G bit must also be set. The interrupt service
routine must reset the pending flag and perform whatever
processing is desired.
Figure 15: Pulse Width Modulation Mode
Timer
Underflow
Interrupts
16-bit Autoreload
Register T1RA
BUS
T1
Data
Latch
16-bit Timer
Instruction
Clock
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.2 Mode 1: Pulse Width Modulation Mode
register. When this number of external events is detected, the
counter will reach zero, however, it will not underflow until the
next event is detected. To count N pulses, load the value N-1
into the registers. If it is only necessary to count the number of
occurrences and no action needs to be taken at a particular
count, load the value 0xFFFF into the registers.
The external event counter mode is similar to the PWM mode,
except that instead of counting instruction clock pulses, the timer
counts transitions received on the T1 pin (configured as an input).
The T1 pin should be connected to an external device that
generates a pulse for each event to be counted. The input signal
on T1 must have a pulse width equal to or greater than one
instruction cycle.
3. In order to generate an interrupt each time the timer
underflows, clear the T1PND pending flag and then enable
the interrupt by setting the T1EN bit. The G bit must also be
set.
The timer can be configured to sense either positive-going or
negative-going transitions on the T1 pin. The maximum frequency
at which transitions can be sensed is one-half the frequency of the
instruction clock.
4. Write the appropriate value to the timer control bits T1C3T1C2- T1C1 to select the external event counter mode, and
to select the type of transition to be sensed on the T1 pin
(positive-going or negative-going; see Table 11).
As with the PWM mode, when an underflow occurs, the timer
register is reloaded from the T1RA registers, and counting proceeds downward from the loaded value.
5. Set the T1C0 bit register to start the timer.
If interrupts are being used, the Timer1 interrupt service routine
must clear the T1PND flag and take whatever action is required
when the timer underflows. If the user wishes to merely count the
number of occurrences of an event, and anticipates that the
number of events may exceed 65,536, the interrupt service
routine should record the number of underflows by incrementing
a counter in memory. On each underflow, the timer (counter)
register is reloaded with the value from the T1RA register.
A block diagram of the timer operating in the external event
counter mode is shown in Figure 16.
The following steps can be used to operate the timer in the
external event counter mode.
1. Configure the T1 pin as an input by clearing bit 2 of PORTGC.
2. Load the initial count into the timer register and the T1RA
Figure 16: External Event Counter Mode
16-bit Autoreload
Register T1RA
Timer
Underflow
Interrupts
BUS
16-bit Timer (Counter)
T1
Edge Selector
Logic
23
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.3 Mode 2: External Event Counter Mode
interrupt service routine records the contents of the T1RA register
and also reprograms the input capture mode, changing the T1 pin
from positive to negative edge sensitivity. When the negative-going
edge appears on the T1 pin, another Timer1 interrupt is generated.
The interrupt service routine reads the T1RA register again. The
difference between the previous reading and the current reading
reflects the elapsed time between the positive edge and negative
edge on the T1 input pin, i.e., the width of the positive pulse.
In the input capture mode, the T1 pin is configured as input. The
timer counts down at the instruction clock rate. A transition
received on the T1 pin causes a transfer of the timer contents to
the T1RA register. The input signal on T1 must have a pulse width
equal to or greater than one instruction cycle. (Refer to the AC
Electrical Specifications for this device.) The values captured in
the T1RA register at different times reflect the elapsed time
between transitions on the T1 pin. The input pin can be configured
to sense either positive-going or negative-going transitions.
Remember that the Timer1 interrupt service routine must test the
T1C0 and T1PND flags to determine what caused the interrupt.
The software that measures elapsed time must take into account
the possibility that an underflow occurred between the first and
second readings. This can be managed by using the interrupt
triggered by each underflow. The Timer1 interrupt service routine,
after determining that an underflow caused the interrupt, should
record the occurrence of an underflow by incrementing a counter
in memory, or by some other means. The software that calculates
the elapsed time should check the status of the underflow counter
and take it into account in making the calculation.
A block diagram of the timer operating in the input capture mode
is shown in Figure 17.
There are two interrupt events associated with the input capture
mode: input capture in T1RA and timer underflow. If interrupts are
enabled, a Timer1 interrupt is triggered by either an input capture
in T1RA or a timer underflow.
In this operating mode, the T1C0 control bit serves as the timer
underflow interrupt pending flag. The Timer1 interrupt service
routine can look at this flag and the T1PND flag to determine what
caused the interrupt. A set T1C0 flag means that a timer underflow
occurred, whereas a set T1PND flag means that an input capture
occurred in T1RA. It is possible that both flags will be found set,
meaning that both events occurred at the same time. The interrupt
routine should take this possibility into consideration.
The following steps can be used to operate the timer in the input
capture mode.
1. Configure the T1 pin as input by clearing bit 2 of PORTG2.
2. With the timer configured to operate in the PWM or external
event counter mode (T1C2 equal to 0), reset the T1C0 bit.
This stops the timer register from counting.
Because the T1C0 bit is used as the underflow interrupt pending
flag, it is not available for use as a start/stop bit as in the other modes.
The timer register counts down continuously at the instruction clock
rate, starting from the time that the input capture mode is selected
with bits T1C3-T1C2-T1C1. To stop the timer from running, you
must change from the input capture mode to the PWM or external
event counter mode and reset the T1C0 bit.
3. Load the initial count into the timer register, typically the
value 0xFFFF to allow the maximum possible number of
counts before underflow.
4. Clear the T1PND interrupt pending flag, then set the T1EN
interrupt enable bit. The G bit should also be set. The
interrupt is now enabled.
5. Write the appropriate value to the timer control bits T1C3T1C2- T1C1 to select the input capture mode, and to select
the types of transitions to be sensed on the T1 pin (positivegoing or negative-going; see Table 11). As soon as the input
capture mode is enabled, the timer starts counting.
The input pins can be independently configured to sense positivegoing or negative-going transitions, resulting in two possible input
capture mode configurations. The edge sensitivity of pin T1 is
controlled by bit T1C1 as indicated in Table 11.
The edge sensitivity of a pin can be changed without leaving the input
capture mode by setting or clearing the appropriate control bit (T1C1),
even while the timer is running. This feature allows you to measure
the width of a pulse received on an input pin. For example, the T1 pin
can be programmed to be sensitive to a positive-going edge. When
the positive edge is sensed, the timer contents are transferred to the
T1RA register, and a Timer1 interrupt is generated. The Timer1
When the programmed type of edge is sensed on the T1 pin, the
T1RA register is loaded and a Timer1 interrupt is triggered. A
Timer1 interrupt is also triggered when an underflow occurs in the
timer register. The interrupt service routine tests both the T1PND
and T1C0 flags to determine the cause of the interrupt, resets the
pending bit, and performs the required task, such as recording the
T1RA register contents or incrementing an underflow counter.
Figure 17: Input Capture Mode
16-bit Timer
Internal
Bus
Instruction Clock
INT A
INT A
16-bit Input Capture
T1RA
Edge Selector
Logic
24
ACE1101 Rev. C.8
T1
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.4 Mode 3: Input Capture Mode
Timer 0 is a 12-bit idle timer. Upon power up or any reset, the timer
is reset to 0 and then counts up continuously based on the
instruction clock of 1MHz (1µs). Software cannot read from or
write to this timer. However, software can monitor the timer's
pending (T0PND) bit which is set every 8.192ms. The T0PND is
set each time the timer overflows (counts up to FFFh). After an
overflow, the timer will reset and restart its count up sequence.
Software can either poll the T0PND bit or vector to interrupt
routine. In order to interrupt on a T0PND, software will need to
make sure the interrupt enable (T0INTEN) bit is set in the
T0CNTRL register and also make sure the global interrupt bit (G)
is set in the status register. Once the timer interrupt is serviced,
software should reset the T0PND bit before exiting the routine.
The Timer 0 supports the following functions:
The WKINTEN bit is used in the Multi-input wakeup block. (See
Section 8 for details.)
7.0 Watchdog timer
The 12-bit Timer 0 is also used to clock the watchdog timer. If the
WDEN bit in the initialization register is asserted, the watchdog
timer must be updated at least every 65,536 cycles but no sooner
than 4096 cycles since the last watchdog update. The watchdog
is updated through software by writing the value 0x1bh to the
WDSVR register (see Figure 19). The part will be reset automatically if the watchdog is updated too frequently, or not frequently
enough. The WDEN bit can only be set while the device is in
programming mode. Once set, the watchdog will always be
powered up enabled. Software cannot disable the watchdog. The
watchdog timer can be disabled in programming mode by resetting the WDEN bit as long as the global write protect feature is not
enabled (WDIS).
1. Exit from IDLE mode. (See Section 17 for details.)
2. Start up delay from halt mode.
3. Watchdog prescaler. (See Section 7 for details.)
The Timer 0 interrupt enable (T0INTEN) bit is a read/write bit. If set
to 0, interrupt requests from the Timer 0 are ignored. If set to 1,
interrupt requests are accepted. The T0INTEN bit is set to zero at
reset.
WARNING
Ensure that the Watchdog timer has been updated before entering
IDLE mode.
Figure 18: Timer 0 Control Register (T0CNTRL)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WKINTEN
x
x
x
x
x
T0PND
T0INTEN
Figure 19: Watchdog Service Register (WDSVR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
1
0
1
1
25
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
The T0PND (Timer 0 pending) bit is a read/write bit. If set to "1,"
it indicates that a Timer 0 interrupt is pending. This bit is set by a
Timer 0 overflow and is reset by software or reset.
6.0 Timer 0
corresponding bit in the WKPND register. This brings the device
out of the HALT mode (if in that mode), and also triggers a
maskable interrupt if that interrupt is enabled. The interrupt
service routine can read the WKPND register to determine which
pin triggered the interrupt.
There are three memory-mapped registers associated with this
circuit: WKEDG (Wakeup Edge), WKEN (Wakeup Enable), and
WKPND (Wakeup Pending). Each register has eight bits, with the
six least significant bits corresponding to one of the input pins
shown in Figure 20. All three registers are initialized to zero with
a Reset.
The interrupt service routine or other software should clear the
pending bit. The device will not enter the HALT mode as long as
any WKPND pending bit is pending and enabled. The user has the
responsibility of clearing the pending flags before attempting to
enter the HALT mode.
The WKEDG register establishes the edge sensitivity for each of
the port input pins: either positive-going edges (0) or negativegoing edges (1).
The WKEN register enables (1) or disables (0) each of the port
pins for the Wakeup/Interrupt function. Any pin to be used for the
Wakeup/Interrupt function must also be configured as an input pin
in the PORTGC configuration register.
After Reset, the WKEDG register is configured to select positivegoing edge sensitivity for all Wakeup inputs. If the user wishes to
change the edge sensitivity of a port pin, use the following
procedure to avoid false triggering of a Wakeup/Interrupt condition.
The WKPND register contains the pending flags corresponding to
each of the port pins (1 for wakeup/interrupt pending, 0 for
wakeup/interrupt not pending).
1. Disable the pin by clearing the associated bit in the WKEN
register.
The T0CNTRL register is the Timer0 control register; however, bit
7 (WKINTEN) is used as the wakeup interrupt enable bit (see
Figure 18). By setting this bit the device can interrupt in the event
of a multi-input wakeup (if the global interrupt bit is set).
3. Clear the WKPND bit associated with the pin.
2. Write to the associated bit of the WKEDG register selecting
the new edge sensitivity of the pin.
4. Re-enable the pin by setting the associated WKEN bit.
PORTG provides the user with eight fully selectable, edge sensitive interrupts which are all vectored into the same service
subroutine.
To use the Multi-Input Wakeup/Interrupt circuit, perform the steps
listed below. Performing the steps in the order shown will prevent
false triggering of a Wakeup/Interrupt condition. This same procedure should be used following a Reset because the Wakeup
inputs will be set to high-impedence, resulting in unknown data on
the port inputs.
The interrupt from PORTG shares logic with the wake up circuitry.
The WKEN register allows interrupts from PORTG to be individually enabled or disabled. The WKEDG register specifies the
trigger condition to be either a positive or a negative edge. The
WKPND register latches the pending trigger conditions.
1. Clear the WKEN register.
2. Set the WKEN bit.
Since PORTG is also used for exiting the device from the HALT
mode, the user can elect to exit the HALT mode either with or
without the interrupt enabled. If the user elects to disable the
interrupt, then the device restarts execution from the point at which
it was stopped (first instruction cycle of the instruction following the
enter HALT mode instruction). In the other case, the device
finishes the instruction which was being executed when the part
was stopped (the NOP instruction following the enter HALT mode
instruction), and then branches to the interrupt service routine.
The device then reverts to normal operation.
3. If necessary, write to the port configuration register to
change the desired port pins from outputs to inputs.
4. Write the WKEDG register to select the desired type of edge
sensitivity for each of the pins used.
5. Clear the WKPND register to cancel any pending bits.
6. Set the WKEN bits associated with the pins to be used, thus
enabling those pins for the Wakeup/Interrupt function.
Once the Multi-Input Wakeup/Interrupt function has been set up,
a transition sensed on any of the enabled pins will set the
Figure 20: Multi-input Wakeup (MIWU) Block Diagram
Internal Data Bus
5
0
WKEN
G0
0
WKOUTINT
G5
5
WKEDG WKPND
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ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
8.0 Multi-Input Wakeup Block
I/O Port
data register (PORTGD), and a port input register (PORTGP).
PORTGC is used to configure the pins as inputs or outputs. A pin
may be configured as an input by writing a ‘0’ or as an output by
writing a ‘1’ to its corresponding PORTGC bit. If a pin is configured
as an output, its PORTGD bit represents the state of the pin (1 =
logic high, 0 = logic low). If the pin is configured as an input, its
PORTGD bit selects whether the pin is a weak pull-up or a highimpedence input. Table 12 provides details of the port configuration options. The port configuration and data registers are both
read/writeable. Reading PORTGP returns the value of the port
pins regardless of how the pins are configured. Since this device
supports multi-input wakeup/interrupt, PORTG inputs have Schmitt
triggers.
The six I/O pins are bi-directional (see Figure 21) with the
exception of G3 which is always an input with weak pull-up. The
bi-directional I/O pins can be individually configured by software
to operate as high-impedance inputs, inputs with weak pull-up, or
as push-pull outputs. The operating state is determined by the
contents of the corresponding bits in the data and configuration
registers. Each bi-directional I/O pin can be used for general
purpose I/O, or in some cases, for a specific alternate function
determined by the on-chip hardware.
9.1 I/O registers
The I/O pins (G0-G5) have three memory port registers associated with them: a port configuration register (PORTGC), a port
Table 12: I/O configuration options
Configuration Bit
Data Bit
Port Pin Configuration
0
0
High-impedence input (TRI-STATE output)
0
1
Input with pull-up (weak one output)
1
0
Push-pull zero output
1
1
Push-pull one output
Figure 21: PORTG Logic Diagram
Weak Pull-up Control
PORTGC
PINGX
PORTGD
PORTGP
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ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
9.0
After 32 bits have been shifted into the ACE1101, the external
programmer must set the LOAD signal to 0V, and then apply two
clock pulses as shown in Figure 22. When reading the device, the
external programmer must set the LOAD signal to 5V before it
sends a new command word. When writing to the ACE1101, the
SHIFT_OUT signal acts as the READY signal. The ACE1101 sets
SHIFT_OUT low by the time the programmer has sent the second
rising edge during the LOAD = 0V phase (if the timing specifications in Figure 22 are obeyed). The ACE1101 will set the R bit of
the Status register when the write operation has completed. The
external programmer must wait for the R bit to go high before
bringing the LOAD signal to 5V to initiate a new command cycle.
The ACE1101 supports in-circuit programming of the internal data
EEPROM, program EEPROM, and the initialization registers. An
externally controlled four wire interface consisting of a LOAD
control pin (G3), a serial data SHIFT_IN input pin (G4), a serial
data SHIFT_OUT output pin (G2), and a CLOCK pin (G1) is used
to access the on-chip memory locations. Communication between the ACE1101 and the external programmer is made through
a 32-bit command and response word described in Table 13.
The serial data timing for the four wire interface is shown in Figure
23. The programming protocol is shown in Figure 22.
The external programmer brings the ACE1101 into programming
mode by applying a supervoltage level (VSUPERVOLTAGE) to the
LOAD pin. The external programmer then needs to set the LOAD
pin to 5V before shifting in the 32-bit serial command word using
the SHIFT_IN and the CLOCK signals. By definition, bit 31 of the
command word is shifted in first. At the same time, the ACE1101
shifts out the 32-bit serial response to the last command on the
SHIFT_OUT pin. It is recommended that the external programmer
samples this signal tACCESS (850ns) after the rising edge of the
CLOCK signal. The serial response word sent immediately after
entering programming mode contains indeterminate data.
Powering down the device will cause the part to exit programming
mode.
Writing a series of bytes to the ACE1101 is achieved by sending
a series of command words with bit 24 set to 0. Reading a series
of bytes from the ACE1101 is achieved by sending a series of
command words with the desired addresses in sequence and
reading the following response words to verify the correct address
and reading the data contents.
The addresses for the data EEPROM and code EEPROM spaces
are the same as those used in normal operation.
Table 13: 32-Bit Command and Response Word
Bit number
Input command word
Output response word
bits 31 – 30
Must be set to 0
X
bit 29
Set to 1 to read/write data EEPROM,
0 otherwise
X
bit 28
Set to 1 to read/write code EEPROM,
Initialization registers 0 otherwise
X
bits 27 – 25
Must be set to 0
X
bit 24
Set to 1 to read, 0 to write
X
bits 23 – 18
Must be set to 0
X
bits 17 – 8
Address of the byte to be read or written
Same as Input command word
bits 7 – 0
Data to be programmed or zero if data is to be read
Programmed data or data read at specified address
NOTE 1: During in-circuit programming, pin 3 (G5) must be either not connected or driven high.
NOTE 2: For further information, see Application Note AN-8005.
28
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
10.0 In-circuit Programming Specification for ACE1101
tSV1
tSV2
tload1
tload2
tready
tload3
tload4
tload3 + ch1*
*in read mode
LOAD (G3)
enter programming mode
A: denotes start of
programming cycle
A
A
32 clock pulses
CLOCK (G1)
SHIFT_IN (G4)
bit 31
bit 30
bit 0
Busy low by 2nd
clock pulse
SHIFT_OUT (G2)
(in Write mode)
READY
BUSY
SHIFT_OUT (G2)
(in Read mode)
Figure 23: Serial Data Timing
tHI
tLO
CLOCK (G1)
tDIS
tDIH
SHIFT_IN (G4)
VALID
tDOS
SHIFT_OUT (G2)
tDOH
VALID
tACCESS
29
ACE1101 Rev. C.8
www.fairchildsemi.com
ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 22: Programming Protocol
The Low Battery Detect (LBD) circuit sets the LBD bit in the LBD
register (see Figure 24) when VCC drops below the selected
threshold voltage. The threshold voltage can be adjusted from
2.4V to 3.0V ±10% using the three most significant bits of the LBD
register. The LBDEN (Low Battery Detect enable) bit in the
initialization register is used to enable or disable the low battery
detection.
Brown-out is not supported on 2.2/2.7V devices.
13.0 RESET block
When a RESET sequence is initiated, all I/O registers will be reset,
setting all I/Os to high impedence inputs. The system clock is
restarted after the required clock start-up delay. A reset is generated by any one of the following three conditions:
The LBD bit is read only. If 0, it indicates that the VCC level is higher
than the desired threshold. If set to 1, it indicates that the VCC level
is below the desired threshold.
■ Power-on RESET (as described in Section 14)
■ Brown-out RESET (as described in Section 12)
■ Watchdog RESET (as described in Section 7)
The LBD circuit is disabled during HALT mode. On exiting HALT
mode, the software must wait 10µs before reading the LBD bit to
ensure that the circuit has stabilized.
Bat_trim2 Bat_trim1 Bat_trim0
14.0 Power-on Reset
The Power-on RESET circuit is guaranteed to work if the rate of
rise of VDD is no slower than 10ms/1 volt. It is also necessary that
VDD starts from 0V.
Voltage
Range
0
0
0
2.9 - 3.0
15.0 CLOCK
0
0
1
2.8 - 2.9
0
1
0
2.7 - 2.8
0
1
1
2.6 - 2.7
The ACE1101 has an on-board oscillator trimmed to a frequency
of 2MHz, yielding a 1MHz frequency and a tolerance over temperature, voltage, and device of ±10%. Upon power-up, the onchip oscillator runs continuously unless entering HALT mode.
1
0
0
2.5 - 2.6
1
0
1
2.4 - 2.5
If required, an external oscillator circuit may be used depending on
the states of the CMODE bits. (See Table 14.) When the device is
driven using an external clock, the clock input to the device (G1/
CKI) can range between DC to 4MHz. For crystal configuration,
the output clock (CKO) is on the G0 pin. If an external crystal or
external RC is used, it will be internally divided by four (input
frequency/4) to yield an instruction clock cycle time of the corresponding input frequency. If the device is configured for an
external square clock, it will not be divided. See Figure 26.
12.0 Brown-out detection circuit
The Brown-out detect circuit is used to reset the device when Vcc
falls below a 2.0V threshold. Once VCC rises above the 2.0V
threshold, a reset sequence will be generated. The Brown-out
Reset enable (BOREN) bit in the initialization register is used to
Table 14: CMODEx Bit Definition
CMODE1
CMODE0
0
0
Internal 1 MHz clock
Clock Type
0
1
External square clock
1
0
External crystal/resonator
1
1
External RC clock
Figure 24: LBD Register Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bat_trim2
Bat_trim1
Bat_trim0
undefined
undefined
Undefined
undefined
LBD
Figure 25: HALT Register Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
undefined
undefined
undefined
undefined
undefined
undefined
EIDLE
EHALT
30
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
enable or disable the brown-out detection. This bit must be set
after the device has been programmed.
11.0 Low battery detect circuit
a)
b)
CKI
(G1)
CKO
(G0)
CKI
(G1)
CKO
(G0)
1M
R
VCC
C
33pF
16.0
33pF
HALT Mode
17.0
The ACE1101 is placed into HALT by setting bit 0 of the HALT
mode register using the LD M, # instruction. The HALT enable bit
(Bit 0) is a write only bit and is automatically cleared on exiting halt.
Upon entering HALT, the internal oscillator, as well as all on-chip
systems, including Low battery detect and Brown out circuits, are
shut down. Prior to entering HALT, software should set the
appropriate wake-up I/O configuration. The device can only be
brought out of HALT by multi-input wake up. After wake up from
HALT, a 1ms startup delay is initiated to allow the internal
oscillator to stabilize before normal execution resumes.
IDLE Mode
In addition to HALT, the ACE1101 supports IDLE mode operation.
The IDLE mode is similar to HALT, except the internal oscillator,
Watchdog, and Timer0 remain active. Figure 28 shows the proper
sequence for software to initiate and recover from IDLE.
The ACE1101 is forced into IDLE by writing to bit 1 of the HALT
mode register using the LD M, # instruction. The idle enable bit (bit
1) is a write only bit and is automatically cleared on exiting IDLE.
The microcontroller resumes normal operation from the IDLE
mode when the T0PND bit (representing 8.192ms at an internal
clock frequency of 1MHz, tc = 1µs) of the IDLE timer is set.
Immediately after exiting HALT, software must clear the Power
mode clear register also using a LD M, # instruction. See Figure
27 below.
The user has the option to interrupt after IDLE. In order to interrupt
after idle, software will need to make sure the interrupt enable
(T0INTEN) bit is set in the T0CNTRL register and also make sure
the global interrupt bit (G) is set in the status register. Once the
interrupt is serviced, software should reset the T0PND bit before
exiting the routine.
Figure 27: Recommended HALT Flow
Immediately after coming out of IDLE, software must clear the
Power mode clear register by also using a LD M, # instruction.
Normal Mode
Figure 28: Recommended IDLE Flow
LD HALT, #01h
Normal Mode
Halt
LD HALT, #02h
Multi-Input Wakeup
IDLE
LD PMC, #00h
LD PMC, #00h
Resume
Normal Mode
Resume
Normal Mode
31
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 26: Crystal (a) and RC (b) Oscillator Diagrams
ACE
11
01
X
E
MT8
X
Letter
Description
X
Tape and Reel
MT8
8-pin TSSOP
Temp. Range
None
E
V
0 to 70°C
-40 to +85°C
-40 to +125°C
Operating Voltage Range
None
B
L
2.2V - 5.5V
2.7V - 5.5V
2.0V - 5.5V
01
1K Code EEPROM
11
8-bit Microcontroller Core Type
ACE
Arithmetic Controller
Engine
Package
Density
32
ACE1101 Rev. C.8
www.fairchildsemi.com
ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Ordering Information
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0098
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP (MT8)
Order Number ACE1101MT8/ACE1101EMT8/ACE1101VMT8
Package Number MTC08
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approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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Tel: 81-3-3818-8840
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
33
ACE1101 Rev. C.8
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ACE1101 Arithmetic Controller Engine (ACEx™) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted