TI TMX320C6745PTP2

TMS320C6745/6747 Floating-point Digital Signal Processor
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
1 TMS320C6745/6747 Floating-point Digital Signal Processor
1.1 Features
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Applications
– Industrial Control
– USB, Networking
– High-Speed Encoding
– Professional Audio
Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
300-MHz C674x VLIW DSP
C674x Instruction Set Features
– Superset of the C67x+™ and C64x+™ ISAs
– 2400/1800 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
– 1024K-Byte L2 ROM
Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
TMS320C674x Floating Point VLIW DSP Core
– Load-Store Architecture With Non-Aligned
Support
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
• Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2
Clocks
• Supports up to Two Floating Point (SP
or DP) Approximate Reciprocal or
Square Root Operations Per Cycle
– Two Multiply Functional Units
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Mixed-Precision IEEE Floating Point
Multiply Supported up to:
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
– 2 SP x DP -> DP Every Three Clocks
– 2 DP x DP -> DP Every Four Clocks
• Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies
per Clock Cycle, and Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
128K-Byte RAM Shared Memory (C6747 Only)
3.3V LVCMOS IOs (except for USB interfaces)
Two External Memory Interfaces:
– EMIFA
• NOR (8-/16-Bit-Wide Data)
• NAND (8-/16-Bit-Wide Data)
• 16-Bit SDRAM With 128MB Address
Space
– EMIFB
• 32-Bit or 16-Bit SDRAM With 256MB
Address Space (C6747)
• 16-Bit SDRAM With 256MB Address
Space (C6745)
Three Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
LCD Controller (C6747 Only)
Two Serial Peripheral Interfaces (SPI) Each
With One Chip-Select
Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Two Master/Slave Inter-Integrated Circuit (I2C
Bus™)
One Host-Port Interface (HPI) With 16-Bit-Wide
Muxed Address/Data Bus For High Bandwidth
(C6747 only)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
TMS320C6000, C6000 are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
Copyright © 2008–2008, Texas Instruments Incorporated
ADVANCE INFORMATION
•
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
•
•
ADVANCE INFORMATION
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2
USB 1.1 OHCI (Host) With Integrated PHY
(USB1) (C6747 Only)
USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client (C6747)
– USB 2.0 Full-Speed Client (C6745)
– USB 2.0 High-/Full-/Low-Speed Host
(C6747)
– USB 2.0 Full-/Low-Speed Host (C6745)
– High-speed Functionality Available on
C6747 Device Only
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt
or ISOC) Rx and Tx
Three Multichannel Audio Serial Ports:
– Transmit/Receive Clocks up to 50 MHz
– Six Clock Zones and 28 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable (McASP2)
– FIFO buffers for Transmit and Receive
10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media Independent Interface
– Management Data I/O (MDIO) Module
Real-Time Clock With 32 KHz Oscillator and
Separate Power Rail (C6747 Only)
One 64-Bit General-Purpose Timer
(Configurable as Two 32-Bit Timers)
TMS320C6745/6747 Floating-point Digital Signal Processor
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One 64-Bit General-Purpose Timer (Watch
Dog)
Three Enhanced Pulse Width Modulators
(eHRPWM):
– Dedicated 16-Bit Time-Base Counter With
Period And Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric or 3
Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
Three 32-Bit Enhanced Capture Modules
(eCAP):
– Configurable as 3 Capture Inputs or 3
Auxiliary Pulse Width Modulator (APWM)
outputs
– Single Shot Capture of up to Four Event
Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder
Pulse Modules (eQEP)
C6747 Device:
– 256-Ball Pb-Free Plastic Ball Grid Array
(PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
C6745 Device
– 176-Pin Thin Quad Flat Pack (TQFP) [PTP
Suffix], 0.5-mm Pin Pitch
Commercial or Automotive Temperature
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1.2 Trademarks
DSP/BIOS, TMS320C6000, C6000, TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas
Instruments.
ADVANCE INFORMATION
All trademarks are the property of their respective owners.
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TMS320C6745/6747 Floating-point Digital Signal Processor
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1.3 Description
The C6745/6747 is a Low-power digital signal processor based on C674x DSP core. It provides
significantly lower power than other members of the TMS320C6000™ platform of DSPs.
The C6745/6747 enables OEMs and ODMs to quickly bring to market devices featuring high processing
performance .
ADVANCE INFORMATION
The C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P)
is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache.
The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program
and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory, cache,
or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional
128KB RAM shared memory ( C6747 only) is available for use by other hosts without affecting DSP
performance.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output
(MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP)
with 16/9 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one
configurable as watchdog); a configurable 16-bit host port interface (HPI) [C6747 only]; up to 8 banks of
16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes,
multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced
high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module
peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM)
outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an
asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a
higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6745/6747
and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and
100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO)
interface is available for PHY configuration.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
4
TMS320C6745/6747 Floating-point Digital Signal Processor
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1.4 Functional Block Diagram
JTAG Interface
DSP Subsystem
System Control
C674x™
DSP CPU
PLL/Clock
Generator
w/OSC
AET
GeneralPurpose
Timer
GeneralPurpose
Timer
(Watchdog)
32 KB
L1 Pgm
Power/Sleep
Controller
32 KB
L1 RAM
256 KB L2 RAM
RTC/
Pin
32-KHz Multiplexing
OSC
1024 KB L2 ROM
ADVANCE INFORMATION
Input
Clock(s)
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
EDMA3
McASP
w/FIFO
(3)
I2C
(2)
eCAP
(3)
SPI
(2)
UART
(3)
LCD
Ctlr
Connectivity
Control Timers
eHRPWM
(3)
Display
Serial Interfaces
eQEP
(2)
USB2.0
OTG Ctlr
PHY
USB1.1
OHCI Ctlr
PHY
(10/100)
EMAC
(RMII)
MDIO
Internal Memory
128 KB
RAM
External Memory Interfaces
HPI
MMC/SD
(8b)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
EMIFB
SDRAM Only
(16b/32b)
Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device
components are available on each device.
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TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
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Contents
1
2
3
1.1
Features .............................................. 1
1.2
Trademarks ........................................... 3
1.3
Description ............................................ 4
1.4
Functional Block Diagram ............................ 5
Revision History ......................................... 7
Device Overview ......................................... 8
ADVANCE INFORMATION
5
6
6
Interrupts ............................................ 68
6.8
General-Purpose Input/Output (GPIO) .............. 74
...............................................
External Memory Interface B (EMIFB) .............. 92
MMC / SD / SDIO (MMCSD) ........................ 97
16
6.13
Ethernet Media Access Controller (EMAC) ........ 100
19
6.14
6.15
Management Data Input/Output (MDIO) ........... 106
Multichannel Audio Serial Ports (McASP0, McASP1,
and McASP2) ...................................... 108
38
6.16
Serial Peripheral Interface Ports (SPI0, SPI1) ..... 124
38
6.17
6.18
Enhanced Capture (eCAP) Peripheral ............. 142
Enhanced Quadrature Encoder (eQEP)
Peripheral .......................................... 145
Enhanced High-Resolution Pulse-Width Modulator
(eHRPWM) ......................................... 147
21
38
38
39
6.19
41
4.6
Chip Configuration Registers (CFGCHIP and
SUSPSRC) .......................................... 45
4.7
DSP Communication Registers ..................... 52
4.8
Device Support ...................................... 53
4.9
Documentation Support ............................. 54
Device Operating Conditions ........................ 56
Absolute Maximum Ratings Over Operating Case
Temperature Range
(Unless Otherwise Noted) .......................... 56
Recommended Operating Conditions ............... 57
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............ 58
Peripheral Information and Electrical
Specifications ........................................... 59
Parameter Information .............................. 59
Recommended Clock and Control Signal Transition
Contents
Clock PLLs .......................................... 65
6.7
6.12
DSP Subsystem ..................................... 10
6.1
6.2
Crystal Oscillator or External Clock Input ........... 64
6.6
6.11
Device Compatibility .................................. 9
5.2
5.3
Reset ................................................ 61
6.5
EDMA
3.3
5.1
6.4
External Memory Interface A (EMIFA) .............. 82
3.2
.............................
3.5
Pin Assignments ....................................
3.6
Terminal Functions ..................................
Device Configuration ..................................
4.1
Introduction ..........................................
4.2
Boot Modes Supported ..............................
4.3
SYSCFG Module ....................................
4.4
Pin Multiplexing Control Registers ..................
4.5
Bus Master Priority Configuration ...................
Power Supplies ...................................... 61
6.10
Device Characteristics ................................ 8
Memory Map Summary
6.3
6.9
3.1
3.4
4
Behavior ............................................. 60
TMS320C6745/6747 Floating-point Digital Signal
Processor ................................................. 1
7
77
6.20
LCD Controller ..................................... 151
6.21
Timers .............................................. 166
6.22
6.23
Inter-Integrated Circuit Serial Ports (I2C0, I2C1) .. 168
Universal Asynchronous Receiver/Transmitter
(UART) ............................................. 172
6.24
USB1 Host Controller Registers (USB1.1 OHCI) .. 174
6.25
USB0 OTG (USB2.0 OTG)
6.26
Host-Port Interface (UHPI) ......................... 183
6.27
Power and Sleep Controller (PSC)
6.28
Emulation Logic .................................... 192
6.29
Real Time Clock (RTC) ............................ 194
........................
................
175
190
Mechanical Packaging and Orderable
Information ............................................. 198
7.1
Thermal Data for ZKB.............................. 198
7.2
Thermal Data for PTP.............................. 199
7.3
Mechanical Drawings .............................. 199
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SPRS377A device-specific data
manual to make it an SPRS377B revision.
Table 2-1. Revision History
ADDITIONS/MODIFICATIONS/DELETIONS
Global: Document status updated from "Product Preview" To "Advance Information".
Global: Updated the document to correct typos.
ADVANCE INFORMATION
Global: Deleted references to PLLDIV9, SYSCLK9.
Global: Updates done to include RAM suppply for voltage scaling.
Global: Updated "ePWM" to "eHRPWM".
Global: Updates done to highlight the differences between C6745 and C6747.
Global: Updated SYSCLK dividers max frequency to 400mhz.
•
Added the following new sections:
– Section 6.4, Reset
– Section 6.26, UHPI
•
Updated the following tables and sections for Emulation related changes :
– Table 3-4, Reset and JTAG Terminal Function
– Table 6-99, DSP Debug Features
– Section 6.28.1, JTAG Port Description
– Table 4-10, SUSPSRC Field Descriptions
– Section 4.3, SYSCFG Module
Deleted Section 4.5 ( in the earlier revision), Pin Multiplexing Control Registers since it is covered in detail in the System Reference Guide
Section 1.1, Added a bullet - "3.3V LVCMOS IOs (except for USB interfaces)".
Figure 3-4, Pin Map (PTP) - Updated Pin 124 to "AXR0[11]/AXR2[0]/GP3[11]"
Table 3-4, Reset and JTAG Terminal Functions table - Updated TDO PULL from "IPU" to IPD"
Table 3-18, Multichannel Audio Serial Ports (McASPs) Terminal Functions - Updated "UART1_TXD/AXR2[0]AXR0[11]/GP3[11]" to
"UART1_TXD/AXR0[10]/GP3[10]"
Section 5.2, Recommended Operating Conditions - Updated the table with values for VIH
Updated Table 6-26, Timing requirements for MMCSD
Updated Table 6-27, Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
Table 6-85, UART Registers - Added Modem Status Register and Scratchpad Register
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Revision History
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3 Device Overview
3.1 Device Characteristics
Table 3-1 provides an overview of the C6745/6747 Low power digital signal processor. The table shows
significant features of the device, including the capacity of on-chip RAM, peripherals, and the package
type with pin count.
Table 3-1. Characteristics of the C6745/C6747 Processor
HARDWARE FEATURES
ADVANCE INFORMATION
C6745
C6747
EMIFB
SDRAM only, 16-bit bus width
SDRAM only, 16/32-bit bus width
EMIFA
Asynchronous (8-bit bus width) RAM,
Flash, NOR, NAND
Asynchronous (8/16-bit bus width) RAM,
Flash, 16-bit SDRAM, NOR, NAND
Flash Card Interface
MMC and SD cards supported.
EDMA3
32 independent channels, 8 QDMA channels, 2 Transfer controllers
Timers
2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as
Watch Dog)
UART
3 (one with RTS and CTS flow control)
SPI
2 (Each with one hardware chip select)
I2C
Peripherals
Not all peripherals pins
are available at the
same time (for more
detail, see the Device
Configurations section).
Multichannel Audio
Serial Port [McASP]
2 (both Master/Slave)
2 (each with transmit/receive, FIFO buffer,
16/9 serializers)
10/100 Ethernet MAC
with Management Data
I/O
eHRPWM
eCAP
1 (RMII Interface)
6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
eQEP
UHPI
2 32-bit QEP channels with 4 inputs/channel
-
1 (16-bit multiplexed address/data)
USB 2.0 (USB0)
Full Speed Host Or Device with On-Chip
PHY
High-Speed OTG Controller with on-chip
OTG PHY
USB 1.1 (USB1)
-
Full-Speed OHCI (as host) with on-chip
PHY
General-Purpose
Input/Output Port
8 banks of 16-bit
LCD Controller
-
1
RTC
-
1 (32 KHz oscillator and seperate power
trail. Provides time and date tracking and
alarm capability.)
Size (Bytes)
On-Chip Memory
3 (each with transmit/receive, FIFO buffer,
16/9 serializers)
Organization
488KB RAM, 1088KB ROM
DSP
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
256KB Unified Mapped RAM/Cache (L2)
1024KB ROM (L2)
DSP Memories can be made accessible to EDMA3, and other peripherals.
ADDITIONAL SHARED MEMORY
128KB RAM
C674x CPU ID + CPU
Rev ID
Control Status Register
(CSR.[31:16])
0x1400
C674x Megamodule
Revision
Revision ID Register
(MM_REVID[15:0])
0x0000
JTAG BSDL_ID
JTAGID Register
CPU Frequency
MHz
Cycle Time
ns
8
Device Overview
0x0B7D_F02F
674x DSP 300 MHz
674x DSP 3.33 ns
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Table 3-1. Characteristics of the C6745/C6747 Processor (continued)
Voltage
(1)
C6747
1.2 V
I/O (V)
3.3 V
24 mm x 24 mm, 176-Pin, 0.5 mm pitch,
TQFP (PTP)
Package
Product Status (1)
C6745
Core (V)
Product Preview (PP),
Advance Information
(AI),
or Production Data
(PD)
17 mm x 17 mm, 256-Ball 1 mm pitch,
PBGA (ZKB)
AI
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
3.2 Device Compatibility
The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both
the C64x+ and C67x+ DSP families.
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Device Overview
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ADVANCE INFORMATION
HARDWARE FEATURES
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3.3 DSP Subsystem
The DSP Subsystem includes the following features:
• C674x DSP CPU
• 32KB L1 Program (L1P)/Cache (up to 32KB)
• 32KB L1 Data (L1D)/Cache (up to 32KB)
• 256KB Unified Mapped RAM/Cache (L2)
• 1MB Mask-programmable ROM
• Little endian
ADVANCE INFORMATION
32K Bytes
L1P RAM/
Cache
256K Bytes
L2 RAM
256
256
256
Cache Control
Memory Protect
1M Byte
L2 ROM
256
Cache Control
Memory Protect
L1P
Bandwidth Mgmt
L2
Bandwidth Mgmt
256
256
256
Instruction Fetch
256
Power Down
Interrupt
Controller
C674x
Fixed/Floating Point CPU
IDMA
Register
File A
Register
File B
64
64
256
CFG
Bandwidth Mgmt
Memory Protect
Cache Control
8 x 32
EMC
L1D
MDMA
64
32K Bytes
L1D RAM/
Cache
32
Configuration
Peripherals
Bus
SDMA
64
64
64
High
Performance
Switch Fabric
Figure 3-1. C674x Megamodule Block Diagram
10
Device Overview
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3.3.1
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C674x DSP CPU Description
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the
C67x+ core.
Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on
a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C674x core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
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Device Overview
11
ADVANCE INFORMATION
The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain
32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be
data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit
data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are
stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or
32 MSBs in the next upper register (which is always an odd-numbered register).
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
•
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Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C674x CPU and its enhancements over the C64x architecture, see the following
documents:
• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)
• TMS320C64x Technical Overview (literature number SPRU395)
ADVANCE INFORMATION
12
Device Overview
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ÁÁ
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ÁÁ Á
ÁÁ Á
ÁÁ Á
Á
Á
Á
Á
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Á
Á
Á
Á
Á
Á
Á
Á Á
Á
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TMS320C6745/6747 Floating-point Digital Signal Processor
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
src1
Odd
register
file A
(A1, A3,
A5...A31)
src2
.L1
odd dst
Even
register
file A
(A0, A2,
A4...A30)
(D)
even dst
long src
ST1b
ST1a
32 MSB
32 LSB
long src
Data path A
.S1
8
8
even dst
odd dst
src1
(D)
LD1b
LD1a
32 LSB
DA2
32
32
src2
32 MSB
DA1
LD2a
LD2b
Á
Á
Á
Á
Á
Á
.M1
dst2
dst1
src1
ADVANCE INFORMATION
src2
(A)
(B)
(C)
dst
.D1
src1
src2
2x
1x
Odd
register
file B
(B1, B3,
B5...B31)
src2
.D2
32 LSB
32 MSB
src1
dst
src2
.M2
Even
register
file B
(B0, B2,
B4...B30)
(C)
src1
dst2
32
(B)
dst1
32
(A)
src2
src1
.S2 odd dst
even dst
long src
Data path B
ST2a
ST2b
32 MSB
32 LSB
long src
even dst
.L2
(D)
8
8
(D)
odd dst
src2
src1
Control Register
A.
B.
C.
D.
On .M unit, dst2 is 32 MSB.
On .M unit, dst1 is 32 LSB.
On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 3-2. TMS320C674x CPU (DSP Core) Data Paths
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TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
3.3.2
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DSP Memory Mapping
The DSP memory map is shown in Section 3.4.
3.3.2.1 External Memories
The DSP has access to the following External memories:
• Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA)
• SDRAM (EMIFB)
3.3.2.2 DSP Internal Memories
ADVANCE INFORMATION
The DSP has access to the following DSP memories:
• L2 RAM
• L1P RAM
• L1D RAM
3.3.2.3 C674x CPU
The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB
direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.
Table 3-2 shows a memory map of the C674x CPU cache registers for the device.
Table 3-2. C674x Cache Registers
HEX ADDRESS RANGE
REGISTER ACRONYM
0x0184 0000
L2CFG
0x0184 0020
L1PCFG
0x0184 0024
L1PCC
0x0184 0040
L1DCFG
0x0184 0044
L1DCC
0x0184 0048 - 0x0184 0FFC
-
0x0184 1000
EDMAWEIGHT
DESCRIPTION
L2 Cache configuration register
L1P Size Cache configuration register
L1P Freeze Mode Cache configuration register
L1D Size Cache configuration register
L1D Freeze Mode Cache configuration register
Reserved
L2 EDMA access control register
0x0184 1004 - 0x0184 1FFC
-
0x0184 2000
L2ALLOC0
Reserved
L2 allocation register 0
0x0184 2004
L2ALLOC1
L2 allocation register 1
0x0184 2008
L2ALLOC2
L2 allocation register 2
0x0184 200C
L2ALLOC3
L2 allocation register 3
0x0184 2010 - 0x0184 3FFF
-
0x0184 4000
L2WBAR
L2 writeback base address register
0x0184 4004
L2WWC
L2 writeback word count register
0x0184 4010
L2WIBAR
L2 writeback invalidate base address register
0x0184 4014
L2WIWC
L2 writeback invalidate word count register
14
Reserved
0x0184 4018
L2IBAR
L2 invalidate base address register
0x0184 401C
L2IWC
L2 invalidate word count register
0x0184 4020
L1PIBAR
L1P invalidate base address register
0x0184 4024
L1PIWC
L1P invalidate word count register
0x0184 4030
L1DWIBAR
L1D writeback invalidate base address register
0x0184 4034
L1DWIWC
L1D writeback invalidate word count register
0x0184 4038
-
0x0184 4040
L1DWBAR
L1D Block Writeback
0x0184 4044
L1DWWC
L1D Block Writeback
0x0184 4048
L1DIBAR
L1D invalidate base address register
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Reserved
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Table 3-2. C674x Cache Registers (continued)
REGISTER ACRONYM
0x0184 404C
L1DIWC
0x0184 4050 - 0x0184 4FFF
-
0x0184 5000
L2WB
0x0184 5004
L2WBINV
0x0184 5008
L2INV
DESCRIPTION
L1D invalidate word count register
Reserved
L2 writeback all register
L2 writeback invalidate all register
L2 Global Invalidate without writeback
0x0184 500C - 0x0184 5027
-
0x0184 5028
L1PINV
Reserved
0x0184 502C - 0x0184 5039
-
0x0184 5040
L1DWB
0x0184 5044
L1DWBINV
0x0184 5048
L1DINV
L1D Global Invalidate without writeback
0x0184 8000 – 0x0184 80FF
MAR0 - MAR63
Reserved 0x0000 0000 – 0x3FFF FFFF
0x0184 8100 – 0x0184 817F
MAR64 – MAR95
Memory Attribute Registers for EMIFA SDRAM Data (CS0) 0x4000 0000 –
0x5FFF FFFF
0x0184 8180 – 0x0184 8187
MAR96 - MAR97
Memory Attribute Registers for EMIFA Async Data (CS2) 0x6000 0000 –
0x61FF FFFF
0x0184 8188 – 0x0184 818F
MAR98 – MAR99
Memory Attribute Registers for EMIFA Async Data (CS3) 0x6200 0000 –
0x63FF FFFF
0x0184 8190 – 0x0184 8197
MAR100 – MAR101
Memory Attribute Registers for EMIFA Async Data (CS4) 0x6400 0000 –
0x65FF FFFF
0x0184 8198 – 0x0184 819F
MAR102 – MAR103
Memory Attribute Registers for EMIFA Async Data (CS5) 0x6600 0000 –
0x67FF FFFF
0x0184 81A0 – 0x0184 81FF
MAR104 – MAR127
Reserved 0x6800 0000 – 0x7FFF FFFF
0x0184 8200
MAR128
0x0184 8204 – 0x0184 82FF
MAR129 – MAR191
Reserved 0x8200 0000 – 0xBFFF FFFF
0x0184 8300 – 0x0184 837F
MAR192 – MAR223
Memory Attribute Registers for EMIFB SDRAM Data (CS2) 0xC000 0000 –
0xDFFF FFFF
0x0184 8380 – 0x0184 83FF
MAR224 – MAR255
Reserved 0xE000 0000 – 0xFFFF FFFF
L1P Global Invalidate
Reserved
L1D Global Writeback
L1D Global Writeback with Invalidate
Memory Attribute Register for Shared RAM 0x8000 0000 – 0x8001 FFFF
Reserved 0x8002 0000 – 0x81FF FFFF
See Table 3-3 for a detailed top level C6745/6747memory map that includes the DSP memory space.
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HEX ADDRESS RANGE
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
www.ti.com
3.4 Memory Map Summary
Table 3-3. C6745/6747 Top Level Memory Map
ADVANCE INFORMATION
16
Start Address
End Address
Size
DSP Mem Map
EDMA Mem Map
Master
Peripheral
Mem Map
0x0000 0000
0x006F FFFF
6M +
1024K
0x0070 0000
0x007F FFFF
1024K
DSP L2 ROM
-
0x0080 0000
0x0083 FFFF
256K
DSP L2 RAM
-
0x0084 0000
0x00DF FFFF
5M +
768K
0x00E0 0000
0x00E0 7FFF
32K
0x00E0 8000
0x00EF FFFF
992K
0x00F0 0000
0x00F0 7FFF
32K
0x00F0 8000
0x017F FFFF
8M +
992K
0x0180 0000
0x0180 FFFF
0x0181 0000
LCDC
Mem
Map
-
DSP L1P RAM
-
DSP L1D RAM
-
64K
DSP Interrupt
Controller
-
0x0181 0FFF
4K
DSP Powerdown
Controller
-
0x0181 1000
0x0181 1FFF
4K
DSP Security ID
-
0x0181 2000
0x0181 2FFF
4K
DSP Revision ID
-
0x0181 3000
0x0181 FFFF
52K
-
-
0x0182 0000
0x0182 FFFF
64K
DSP EMC
-
0x0183 0000
0x0183 FFFF
64K
DSP Internal
Reserved
-
0x0184 0000
0x0184 FFFF
64K
DSP Memory
System
-
0x0185 0000
0x01BB FFFF
3M +
600K
0x01BC 0000
0x01BC 0FFF
4K
-
0x01BC 1000
0x01BC 17FF
2K
-
0x01BC 1900
0x01BC 18FF
256
-
0x01BC 0500
0x01BF FFFF
260K
0x01C0 0000
0x01C0 7FFF
32K
EDMA3 CC
-
0x01C0 8000
0x01C0 83FF
1024
EDMA3 TC0
-
0x01C0 8400
0x01C0 87FF
1024
EDMA3 TC1
-
0x01C0 8800
0x01C0 FFFF
30K
0x01C1 0000
0x01C1 0FFF
4K
PSC 0
-
0x01C1 1000
0x01C1 1FFF
4K
PLL Controller
-
0x01C1 2000
0x01C1 3FFF
8K
0x01C1 4000
0x01C1 4FFF
4K
SYSCFG
-
0x01C1 5000
0x01C1 5FFF
4K
-
0x01C1 6000
0x01C1 6FFF
4K
-
0x01C1 7000
0x01C1 7FFF
4K
-
0x01C1 8000
0x01C1 FFFF
32K
-
0x01C2 0000
0x01C2 0FFF
4K
Timer64P 0
-
0x01C2 1000
0x01C2 1FFF
4K
Timer64P 1
-
0x01C2 2000
0x01C2 2FFF
4K
I2C 0
-
0x01C2 3000
0x01C2 3FFF
4K
RTC
-
0x01C2 4000
0x01C2 4FFF
4K
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
Table 3-3. C6745/6747 Top Level Memory Map (continued)
Start Address
End Address
Size
EDMA Mem Map
Master
Peripheral
Mem Map
LCDC
Mem
Map
0x01C2 5000
0x01C3 FFFF
110K
0x01C4 0000
0x01C4 0FFF
4K
MMC/SD 0
-
0x01C4 1000
0x01C4 1FFF
4K
SPI 0
-
0x01C4 2000
0x01C4 2FFF
4K
UART 0
-
0x01C4 3000
0x01CF FFFF
774K
0x01D0 0000
0x01D0 0FFF
4K
McASP 0 Control
-
0x01D0 1000
0x01D0 1FFF
4K
McASP 0 AFIFO Ctrl
-
0x01D0 2000
0x01D0 2FFF
4K
McASP 0 Data
-
0x01D0 3000
0x01D0 3FFF
4K
0x01D0 4000
0x01D0 4FFF
4K
McASP 1 Control
-
0x01D0 5000
0x01D0 5FFF
4K
McASP 1 AFIFO Ctrl
-
0x01D0 6000
0x01D0 6FFF
4K
McASP 1 Data
-
0x01D0 7000
0x01D0 7FFF
4K
0x01D0 8000
0x01D0 8FFF
4K
McASP 2 Control
-
-
-
-
-
0x01D0 9000
0x01D0 9FFF
4K
McASP 2 AFIFO Ctrl
-
0x01D0 A000
0x01D0 AFFF
4K
McASP 2 Data
-
0x01D0 B000
0x01D0 BFFF
4K
0x01D0 C000
0x01D0 CFFF
4K
UART 1
-
0x01D0 D000
0x01D0 DFFF
4K
UART 2
-
0x01D0 E000
0x01D0 EFFF
4K
IOPU 4
-
0x01D0 F000
0x01DF FFFF
964K
0x01E0 0000
0x01E0 FFFF
64K
USB0
0x01E1 0000
0x01E1 0FFF
4K
UHPI
0x01E1 1000
0x01E1 1FFF
4K
0x01E1 2000
0x01E1 2FFF
4K
SPI 1
0x01E1 3000
0x01E1 3FFF
4K
LCD Controller
0x01E1 4000
0x01E1 4FFF
4K
-
-
-
0x01E1 5000
0x01E1 5FFF
4K
0x01E1 6000
0x01E1 FFFF
40K
0x01E2 0000
0x01E2 1FFF
8K
EMAC Control Module RAM
-
0x01E2 2000
0x01E2 2FFF
4K
EMAC Control Module Registers
-
0x01E2 3000
0x01E2 3FFF
4K
EMAC Control Registers
-
0x01E2 4000
0x01E2 4FFF
4K
EMAC MDIO port
-
0x01E2 5000
0x01E2 5FFF
4K
USB1
-
0x01E2 6000
0x01E2 6FFF
4K
GPIO
-
0x01E2 7000
0x01E2 7FFF
4K
PSC 1
-
0x01E2 8000
0x01E2 8FFF
4K
I2C 1
-
0x01E2 9000
0x01E2 9FFF
4K
0x01E2 A000
0x01EF FFFF
856K
0x01F0 0000
0x01F0 0FFF
4K
0x01F0 1000
0x01F0 1FFF
0x01F0 2000
0x01F0 2FFF
0x01F0 3000
-
eHRPWM 0
-
4K
HRPWM 0
-
4K
eHRPWM 1
-
0x01F0 3FFF
4K
HRPWM 1
-
0x01F0 4000
0x01F0 4FFF
4K
eHRPWM 2
-
0x01F0 5000
0x01F0 5FFF
4K
HRPWM 2
-
0x01F0 6000
0x01F0 6FFF
4K
ECAP 0
-
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TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
www.ti.com
Table 3-3. C6745/6747 Top Level Memory Map (continued)
ADVANCE INFORMATION
18
Start Address
End Address
Size
DSP Mem Map
EDMA Mem Map
Master
Peripheral
Mem Map
LCDC
Mem
Map
0x01F0 7000
0x01F0 7FFF
4K
ECAP 1
-
0x01F0 8000
0x01F0 8FFF
4K
ECAP 2
-
0x01F0 9000
0x01F0 9FFF
4K
EQEP 0
-
0x01F0 A000
0x01F0 AFFF
4K
EQEP 1
-
0x01F0 B000
0x01F0 BFFF
4K
-
0x01F0 C000
0x116F FFFF
247M +
976K
-
0x1170 0000
0x117F FFFF
1024K
DSP L2 ROM
-
0x1180 0000
0x1183 FFFF
256K
DSP L2 RAM
-
0x1184 0000
0x11DF FFFF
5M +
768K
-
0x11E0 0000
0x11E0 7FFF
32K
0x11E0 8000
0x11EF FFFF
992K
0x11F0 0000
0x11F0 7FFF
32K
0x11F0 8000
0x3FFF FFFF
736M +
992K
0x4000 0000
0x5FFF FFFF
512M
EMIFA SDRAM data (CS0)
-
0x6000 0000
0x61FF FFFF
32M
EMIFA async data (CS2)
-
0x6200 0000
0x63FF FFFF
32M
EMIFA async data (CS3)
-
0x6400 0000
0x65FF FFFF
32M
EMIFA async data (CS4)
-
0x6600 0000
0x67FF FFFF
32M
EMIFA async data (CS5)
-
EMIFA Control Regs
-
0x6800 0000
0x6800 7FFF
32K
0x6800 8000
0x7FFF FFFF
383M +
992K
DSP L1P RAM
DSP L1D RAM
-
-
-
0x8000 0000
0x8001 FFFF
128K
0x8002 0000
0xAFFF FFFF
767M +
896K
-
0xB000 0000
0xB000 7FFF
32K
EMIFB Control Regs
0xB000 8000
0xBFFF FFFF
255M +
992K
-
0xC000 0000
0xDFFF FFFF
512M
EMIFB SDRAM Data
0xE000 0000
0xFFFC FFFF
511M +
832K
-
0xFFFD 0000
0xFFFD FFFF
64K
-
0xFFFE 0000
0xFFFE DFFF
56K
-
0xFFFE E000
0xFFFE FFFF
8K
-
0xFFFF 0000
0xFFFF 1FFF
8K
-
0xFFFF 2000
0xFFFF FFFF
56K
-
Device Overview
-
-
Shared RAM
-
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3.5 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
3.5.1
Pin Map (Bottom View)
1
2
4
5
6
7
8
9
10
AXR1[11]/
GP5[11]
SPI0_CLK/
EQEP1I/
GP5[2]/
BOOT[2]
SPI1_CLK/
EQEP1S/
GP5[7]/
BOOT[7]
EMA_CS[3]/
AMUTE2/
GP2[6]
EMA_CS[0]/
UHPI_HAS/
GP2[4]
EMA_A[0]/
LCD_D[7]/
GP1[0]
EMA_A[4]/
LCD_D[3]/
GP1[4]
3
T
VSS
VSS
AXR1[0]/
GP4[0]
R
DVDD
AXR1[1]/
GP4[1]
UART0_RXD/
I2C0_SDA/
TM64P0_IN12/
GP5[8]/
BOOT[8]
P
AXR1[3]/
EQEP1A/
GP4[3]
AXR1[2]/
GP4[2]
N
AXR1[5]/
EPWM2B/
GP4[5]
AXR1[4]/
EQEP1B/
GP4[4]
AXR1[10]/
GP5[10]
M
AXR1[9]/
GP4[9]
AXR1[8]/
EPWM1A/
GP4[8]
AXR1[7]/
EPWM1B/
GP4[7]
AXR1[6]/
EPWM2A/
GP4[6]
DVDD
VSS
VSS
L
AHCLKR1/
GP4[11]
ACLKR1/
ECAP2/
APWM2/
GP4[12]
AFSR1/
GP4[13]
AMUTE0/
RESETOUT
DVDD
CVDD
K
RTCK
AHCLKX1/
EPWM0B/
GP3[14]
ACLKX1/
EPWM0A/
GP3[15]
AFSX1/
EPWMSYNCI/
EPWMSYNCO/
GP4[10]
DVDD
J
TMS
TDI
TDO
TRST
H
RTC_XI
RTC_XO
TCK
G
RTC_CVDD
RTC_VSS
F
OSCOUT
E
SPI0_ENA/ SPIO_SOMI[0]/ EMA_OE/
SPI1_ENA/ UART0_CTS/
EQEPOI/
UHPI_HDS1/
UART2_RXD/ EQEP0A/
GP5[0]/
AXR0[13]/
GP5[3]/
GP5[12]
BOOT[0]
GP2[7]
BOOT[3]
11
12
13
14
EMA_D[0]/
EMA_D[9]/
EMA_A[8]/
EMA_SDCKE/ MMCSD_DAT[0]/ UHPI_HD[9]/
UHPI_HD[0]/
LCD_PCLK/
GP2[0]
LCD_D[9]/
GP0[0]/
GP1[8]
GP0[9]
BOOT[12]
EMA_CLK/
OBSCLK/
AHCLKR2/
GP1[15]
15
16
VSS
VSS
T
DVDD
R
EMA_A[1]/
EMA_BA[0]/
MMCSD_CLK/
LCD_D[4]/
UHPI_HCNTL0/
GP1[14]
GP1[1]
EMA_A[5]/
LCD_D[2]/
GP1[5]
EMA_A[9]/
LCD_HSYNC/
GP1[9]
EMA_D[2]/
EMA_D[10]/
EMA_D[1]/
MMCSD_DAT[2]/ UHPI_HD[10]/ MMCSD_DAT[1]/
UHPI_HD[2]/
LCD_D[10]/
UHPI_HD[1]/
GP0[2]
GP0[10]
GP0[1]
UART0_TXD/
EMA_A[2]/
SPI1_SOMI[0]/ SPI0_SIMO[0]/ EMA_CS[2]/ EMA_BA[1]/
SPI1_SCS[0]/
I2C0_SCL/
I2C1_SCL/
EQEP0S/
UHPI_HCS/ LCD_D[5]/ MMCSD_CMD/
TM64P0_OUT12/ UART2_TXD/
UHPI_HHWIL/ UHPI_HCNTL1/
GP5[5]/
GP5[1]/
GP2[5]/
GP5[9]/
GP5[13]
GP1[13]
GP1[2]
BOOT[5]
BOOT[1]
BOOT[15]
BOOT[9]
EMA_A[6]/
LCD_D[1]/
GP1[6]
EMA_A[11]/
LCD_AC_
ENB_CS/
GP1[11]
EMA_WE_
EMA_D[4]/
EMA_D[12]/
EMA_D[3]/
EMA_D[11]/
DQM[1]/
MMCSD_DAT[4]/ UHPI_HD[12]/ MMCSD_DAT[3]/ UHPI_HD[11]/
UHPI_HDS2/
UHPI_HD[4]/
LCD_D[12]/
UHPI_HD[3]/
LCD_D[11]
AXR0[14]/
GP0[4]
GP0[12]
GP0[3]
GP0[11]
GP2[8]
P
SPI0_SCS[0]/ SPI1_SIMO[0]/
UART0_RTS/ I2C1_SDA/ EMA_WAIT[0]/ EMA_RAS/ EMA_A[10]/
UHPI_HRDY/ EMA_CS[5]/ LCD_VSYNC/
EQEP0B/
GP5[6]/
GP5[4]/
GP2[10]
GP2[2]
GP1[10]
BOOT[6]
BOOT[4]
EMA_A[3]/
LCD_D[6]/
GP1[3]
EMA_A[7]/
LCD_D[0]/
GP1[7]
EMA_A[12]/
LCD_MCLK/
GP1[12]
EMA_D[8]/
EMA_D[6]/
EMA_D[14]/
EMA_D[5]/
EMA_D[13]/
UHPI_HD[8]/ MMCSD_DAT[6]/ UHPI_HD[14]/ MMCSD_DAT[5]/ UHPI_HD[13]/
LCD_D[8]/
UHPI_HD[6]/
LCD_D[14]/
UHPI_HD[5]/
LCD_D[13]/
GP0[14]
GP0[5]
GP0[13]
GP0[8]
GP0[6]
N
DVDD
DVDD
VSS
VSS
DVDD
EMA_WE/
UHPI_HRW/
AXR0[12]/
GP2[3]/
BOOT[14]]
EMA_D[7]/
EMA_WE_
EMA_D[15]/
MMCSD_DAT[7]/
DQM[0]/
UHPI_HD[15]/
UHPI_HINT/ UHPI_HD[7]/
LCD_D[15]/
AXR0[15]/
GP0[7]/
GP0[15]
GP2[9]
BOOT[13]
M
VSS
VSS
VSS
VSS
DVDD
DVDD
EMB_CAS
EMB_D[22]
EMB_D[23]
EMA_CAS/
EMA_CS[4]/
GP2[1]
L
CVDD
CVDD
VSS
VSS
CVDD
CVDD
DVDD
EMB_D[20]
EMB_WE_
DQM[0]/
GP5[15]
EMB_WE
EMB_D[21]
K
EMU0
CVDD
CVDD
VSS
VSS
CVDD
CVDD
CVDD
EMB_D[5]/
GP6[5]
EMB_D[19]
EMB_D[6]/
GP6[6]
EMB_D[7]/
GP6[7]
J
USB0_
VSSA33
USB0_
VDDA33
RVDD
CVDD
VSS
VSS
CVDD
CVDD
RVDD
EMB_D[3]/
GP6[3]
EMB_D[17]
EMB_D[18]
EMB_D[4]/
GP6[4]
H
RESET
USB0_DM
DVDD
CVDD
CVDD
VSS
VSS
CVDD
CVDD
DVDD
EMB_D[1]/
GP6[1]
EMB_D[31]
EMB_D[16]
EMB_D[2]/
GP6[2]
G
OSCIN
USB0_VSSA
USB0_DP
DVDD
CVDD
RSV1
VSS
VSS
VSS
DVDD
DVDD
EMB_D[15]/
GP6[15]
EMB_D[29]
EMB_D[30]
EMB_D[0]/
GP6[0]
F
PLL0_VSSA
OSCVSS
USB0_
VDDA18
USB0_
DRVVBUS/
GP4[15]
DVDD
VSS
VSS
DVDD
DVDD
VSS
VSS
DVDD
EMB_D[13]/
GP6[13]
EMB_D[27]
EMB_D[28]
EMB_D[14]/
GP6[14]
E
D
PLL0_VDDA
USB0_ID
C
USB1_
VDDA33
USB1_
VDDA18
USB0_
VDDA12
B
RSV2
VSS
A
VSS
1
AFSX0/
GP2[13]/
BOOT[10]
AXR0[6]/
UART1_TXD/
RMII_RXER/
AXR0[10]/
ACLKR2/
GP3[10]
GP3[6]
AXR0[2]/
RMII_TXEN/
AXR2[3]/
GP3[2]
EMB_CS[0]
EMB_A[0]/
GP7[2]
EMB_A[4]/
GP7[6]
EMB_A[8]/
GP7[10]
EMB_D[9]/
GP6[9]
EMB_D[10]/
GP6[10]
EMB_D[11]/
GP6[11]
EMB_D[12]/
GP6[12]
D
AFSR0/
GP3[12]
ACLKX0/
ECAP0/
APWM0/
GP2[12]
AXR0[5]/
AXR0[1]/
UART1_RXD/
RMII_RXD[1]/ RMII_TXD[1]/
AXR0[9]/
AFSX2/
ACLKX2/
GP3[9]
GP3[5]
GP3[1]
EMB_BA[0]/
GP7[1]
EMB_A[1]/
GP7[3]
EMB_A[5]/
GP7[7]
EMB_A[9]/
GP7[11]
EMB_SDCKE
EMB_CLK
EMB_WE_
DQM[1]/
GP5[14]
EMB_D[8]/
GP6[8]
C
USB1_DM
ACLKR0/
ECAP1/
APWM1/
GP2[15]
AHLKX0/
AHCLKX2/
USB_
REFCLKIN/
GP2[11]
AXR0[8]/
MDIO_D/
GP3[8]
AXR0[4]/
AXR0[0]/
RMII_RXD[0]/ RMII_TXD[0]/
AXR2[1]/
AFSR2/
GP3[4]
GP3[0]
EMB_BA[1]/
GP7[0]
EMB_A[2]/
GP7[4]
EMB_A[6]/
GP7[8]
EMB_A[11]/
GP7[13]
EMB_WE_
DQM[2]
EMB_D[25]
EMB_A[12]/
GP3[13]
DVDD
B
VSS
USB1_DP
AHCLKR0/
RMII_MHZ_
50_CLK/
GP2[14]/
BOOT[11]
AXR0[11]/
AXR2[0]/
GP3[11]
AXR0[7]/
MDIO_CLK/
GP3[7]
AXR0[3]/
RMII_CRS_DV/
AXR2[2]/
GP3[3]
EMB_RAS
EMB_A[10]/
GP7[12]
EMB_A[3]/
GP7[5]
EMB_A[7]/
GP7[9]
EMB_WE_
DQM[3]
EMB_D[24]
EMB_D[26]
VSS
VSS
A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AMUTE1/
USB0_VBUS EHRPWMTZ/
GP4[14]
ADVANCE INFORMATION
Figure 3-3 and Figure 3-4 show the pin assignments for BGA package and PTP package
respectively.Note that micro-vias are not required. Contact your TI representative for routing
recommendations.
Figure 3-3. Pin Map (BGA)
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Device Overview
19
RSV2
USB0_VDDA12
USB0_VDDA18
USB0_VSSA
USB0_DP
USB0_DM
USB0_VSSA33
USB0_VDDA33
PLL0_VDDA
PLL0_VSSA
OSCIN
OSCVSS
OSCOUT
RESET
CVDD
RSV4
RSV3
TRST
DVDD
TMS
TDI
CVDD
TCK
TDO
GP7[14]
DVDD
RVDD
AHCLKX1/EPWM0B/GP3[14]
CVDD
ACLKX1/EPWM0A/GP3[15]
AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10]
DVDD
ACLKR1/ECAP2/APWM2/GP4[12]
AFSR1/GP4[13]
CVDD
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
DVDD
AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]
AXR1[2]/GP4[2]
AXR1[1]/GP4[1]
20
Device Overview
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
CVDD
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
DVDD
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
EMA_WAIT[0]/GP2[10]
CVDD
EMA_CS[3]/GP2[6]
EMA_OE//AXR0[13]/GP2[7]
EMA_CS[2]/GP2[5]/BOOT[15]
DVDD
EMA_BA[0]/GP1[14]
EMA_BA[1]/GP1[13]
EMA_A[10]/GP1[10]
CVDD
EMA_A[0]/GP1[0]
EMA_A[1]/MMCSD_CLK/GP1[1]
EMA_A[2]/MMCSD_CMD/GP1[2]
EMA_A[3]/GP1[3]
DVDD
EMA_A[4]/GP1[4]
EMA_A[5]/GP1[5]
EMA_A[6]/GP1[6]
EMA_A[7]/GP1[7]
CVDD
EMA_A[8]/GP1[8]
EMA_A[9]/GP1[9]
EMA_A[11]/GP1[11]
EMA_A[12]/GP1[12]
DVDD
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ADVANCE INFORMATION
AXR1[0]/GP4[0]
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT8
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
GP5[10]
DVDD
GP5[11]
SPI1_ENA/UART2_RXD/GP5[12]
SPI1_SCS[0]/UART2_TXD/GP5[13]
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
AMUTE1/EHRPWMTZ/GP4[14]
AFSR0/GP3[12]
ACLKR0/ECAP1/APWM1/GP2[15]
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
DVDD
AFSX0/GP2[13]/BOOT[10]
ACLKX0/ECAP0/APWM0/GP2[12]
AHCLKX0/USB_REFCLKIN/GP2[11]
AXR0[11]/AXR2[0]/GP3[11]
UART1_TXD/AXR0[10]/GP3[10]
UART1_RXD/AXR0[9]/GP3[9]
AXR0[8]/MDIO_D/GP3[8]
AXR0[7]/MDIO_CLK/GP3[7]
DVDD
AXR0[6]/RMII_RXER/GP3[6]
AXR0[5]/RMII_RXD[1]/GP3[5]
AXR0[4]/RMII_RXD[0]/GP3[4]
AXR0[3]/RMII_CRS_DV/GP3[3]
CVDD
AXR0[2]/RMII_TXEN/GP3[2]
AXR0[1]/RMII_TXD[1]/GP3[1]
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0]
EMB_RAS
DVDD
EMB_CS[0]
EMB_BA[0]/GP7[1]
EMB_BA[1]/GP7[0]
EMB_A[10]/GP7[12]
CVDD
EMB_A[0]/GP7[2]
EMB_A[1]/GP7[3]
EMB_A[2]/GP7[4]
EMB_A[3]/GP7[5]
DVDD
EMB_A[4]/GP7[6]
EMB_A[5]/GP7[7]
EMB_A[6]/GP7[8]
EMB_A[7]/GP7[9]
EMB_A[8]/GP7[10]
CVDD
EMB_A[9]/GP7[11]
EMB_A[11]/GP7[13]
DVDD
EMB_A[12]/GP3[13]
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
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VSS
(177)
Thermal Pad
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
EMB_SDCKE
DVDD
EMB_CLK
EMB_WE_DQM[1]/GP5[14]
EMB_D[8]/GP6[8]
EMB_D[9]/GP6[9]
EMB_D[10]/GP6[10]
DVDD
EMB_D[11]/GP6[11]
EMB_D[12]/GP6[12]
EMB_D[13]/GP6[13]
CVDD
EMB_D[14]/GP6[14]
DVDD
EMB_D[15]/GP6[15]
EMB_D[0]/GP6[0]
EMB_D[1]/GP6[1]
DVDD
EMB_D2/GP6[2]
CVDD
EMB_D[3]/GP6[3]
RVDD
EMB_D[4]/GP6[4]
DVDD
EMB_D[5]/GP6[5]
EMB_D[6]/GP6[6]
EMB_D[7]/GP6[7]
CVDD
EMB_WE_DQM[0]/GP5[15]
EMB_WE
DVDD
EMB_CAS
CVDD
EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
DVDD
EMA_D[6]/MMCSD_DAT[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/GP0[5]
CVDD
EMA_D[4]/MMCSD_DAT[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/GP0[3]
DVDD
EMA_D[2]/MMCSD_DAT[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/GP0[1]
Figure 3-4. Pin Map (PTP)
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
3.6 Terminal Functions
to identify the external signal names, the associated pin/ball numbers along with the mechanical package
designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown
resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.
3.6.1
Device Reset and JTAG
Table 3-4. Reset and JTAG Terminal Functions
PIN NO
SIGNAL NAME
TYPE (1)
PULL (2)
DESCRIPTION
PTP
ZKB
146
G3
I
-
L4
O (3)
TMS
152
J1
I
IPU
JTAG test mode select
TDI
153
J2
I
IPU
JTAG test data input
TDO
156
J3
O
IPD
JTAG test data output
TCK
155
H3
I
IPU
JTAG test clock
TRST
150
J4
I
IPD
JTAG test reset
EMU[0]
-
J5
I/O
IPU
Miscellaneous emulation pin.
GP7[14]
157
K1
I/O
IPU
General-Purpose IO signal.
AMUTE0/RESETOUT
Device reset input
IPD
Reset output. Multiplexed with McASP0 mute output.
JTAG
(1)
(2)
(3)
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Open drain mode for RESETOUT function.
3.6.2
High-Frequency Oscillator and PLL
Table 3-5. High-Frequency Oscillator and PLL Terminal Functions
SIGNAL NAME
EMA_CLK/OBSCLK/AHCLKR
2/GP1[15]
PIN NO
PTP
ZKB
-
R12
TYPE (1)
PULL (2)
O
IPU
DESCRIPTION
PLL Observation Clock
1.2-V OSCILLATOR
OSCIN
143
F2
I
Oscillator input
OSCOUT
145
F1
O
Oscillator output
OSCVSS
144
E2
GND
PLL0_VDDA
141
D1
PWR
PLL analog VDD (1.2-V filtered supply)
PLL0_VSSA
142
E1
GND
PLL analog VSS (for filter)
Oscillator ground (for filter only)
1.2-V PLL
(1)
(2)
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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ADVANCE INFORMATION
RESET
RESET
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
3.6.3
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Real-Time Clock and 32-kHz Oscillator
Table 3-6. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions
SIGNAL NAME
PIN NO
TYPE (1)
PULL (2)
DESCRIPTION
PTP
ZKB
RTC_CVDD
-
G1
RTC_XI
-
H1
I
Low-frequency (32-kHz) oscillator receiver for real-time clock
RTC_XO
-
H2
O
Low-frequency (32-kHz) oscillator driver for real-time clock
RTC_Vss
-
G2
GND
(1)
ADVANCE INFORMATION
(2)
PWR
RTC module core power ( isolated from rest of chip CVDD)
Oscillator ground (for filter)
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.4
External Memory Interface A (ASYNC, SDRAM)
Table 3-7. External Memory Interface A (EMIFA) Terminal Functions
PIN NO
TYPE (1)
PULL (2)
M16
I/O
IPD
N14
I/O
IPD
-
N16
I/O
IPD
-
P14
I/O
IPD
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11]
-
P16
I/O
IPD
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10]
-
R14
I/O
IPD
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9]
-
T14
I/O
IPD
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8]
-
N12
I/O
IPD
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
54
M15
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
52
N13
I/O
IPU
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
51
N15
I/O
IPU
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
49
P13
I/O
IPU
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
48
P15
I/O
IPU
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
46
R13
I/O
IPU
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
45
R15
I/O
IPU
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12]
44
T13
I/O
IPU
SIGNAL NAME
PTP
ZKB
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15]
-
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]
-
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]
(1)
(2)
22
MUXED
DESCRIPTION
UHPI, LCD,
GPIO
MMC/SD,
UHPI, GPIO,
BOOT
EMIFA data bus
MMC/SD,
UHPI, GPIO
MMC/SD,
UHPI, GPIO,
BOOT
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
Table 3-7. External Memory Interface A (EMIFA) Terminal Functions (continued)
PULL (2)
N11
O
IPU
41
P11
O
IPU
27
N8
O
IPU
EMA_A[9]/LCD_HSYNC/GP1[9]
40
R11
O
IPU
EMA_A[8]/LCD_PCLK/GP1[8]
39
T11
O
IPU
EMA_A[7]/LCD_D[0]/GP1[7]
37
N10
O
IPD
EMA_A[6]/LCD_D[1]/GP1[6]
36
P10
O
IPD
EMA_A[5]/LCD_D[2]/GP1[5]
35
R10
O
IPD
EMA_A[4]/LCD_D[3]/GP1[4]
34
T10
O
IPD
EMA_A[3]/LCD_D[6]/GP1[3]
32
N9
O
IPD
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
31
P9
O
IPU
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
30
R9
O
EMA_A[0]/LCD_D[7]/GP1[0]
29
T9
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]
26
EMA_BA[0]/LCD_D[4]/GP1[14]
PTP
ZKB
EMA_A[12]/LCD_MCLK/GP1[12]
42
EMA_A[11]/LCD_AC_ENB_CS/GP1[11]
EMA_A[10]/LCD_VSYNC/GP1[10]
MUXED
DESCRIPTION
LCD, GPIO
EMIFA address bus
IPU
MMCSD,
UHPI, GPIO
EMIFA address bus.
O
IPD
LCD, GPIO
P8
O
IPU
LCD, UHPI,
GPIO
25
R8
O
IPU
LCD, GPIO
EMA_CLK/OBSCLK/AHCLKR2/GP1[15]
-
R12
O
IPU
McASP2,
GPIO
EMIFA clock.
EMA_SDCKE/GP2[0]
-
T12
O
IPU
GPIO
EMIFA SDRAM clock
enable.
EMA_RAS/EMA_CS[5]/GP2[2]
-
N7
O
IPU
EMA_CAS/EMA_CS[4]/GP2[1]
-
EMA_RAS/EMA_CS[5]/GP2[2]
EMA_CAS/EMA_CS[4]/GP2[1]
EMIFA bank address
EMIFA SDRAM row
address strobe.
EMIF A chip
select, GPIO
EMIFA SDRAM
column address
strobe.
L16
O
IPU
-
N7
O
IPU
-
L16
O
IPU
EMA_CS[3]/AMUTE2/GP2[6]
21
T7
O
IPU
McASP2,
GPIO
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
25
P7
O
IPU
UHPI, GPIO,
BOOT
-
T8
O
IPU
UHPI, GPIO
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
55
M13
O
IPU
UHPI,
EMIFA SDRAM write
MCASP0,
enable.
GOPIO, BOOT
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8]
-
P12
O
IPU
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9]
-
M14
O
IPU
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
22
R7
O
IPU
UHPI,
McASP0,
GPIO
EMIFA output enable.
EMA_WAIT[0]/UHPI_HRDY/GP2[10]
19
N6
I
IPU
UHPI, GPIO
EMIFA wait
input/interrupt.
EMA_CS[0]/UHPI_HAS/GP2[4]
Submit Documentation Feedback
EMIF A
SDRAM, GPIO
EMIFA Async Chip
Select
EMIFA write
enable/data mask for
UHPI, McASP, EMA_D[15:8]
GPIO
EMIFA write
enable/data mask for
EMA_D[7:0].
Device Overview
23
ADVANCE INFORMATION
PIN NO
TYPE (1)
SIGNAL NAME
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
3.6.5
www.ti.com
External Memory Interface B (only SDRAM )
Table 3-8. External Memory Interface B (EMIFB) Terminal Functions
PIN NO
TYPE (1)
PULL (2)
G14
I/O
IPD
-
F15
I/O
IPD
-
F14
I/O
IPD
EMB_D[28]
-
E15
I/O
IPD
EMB_D[27]
-
E14
I/O
IPD
EMB_D[26]
-
A14
I/O
IPD
EMB_D[25]
-
B14
I/O
IPD
EMB_D[24]
-
A13
I/O
IPD
EMB_D[23]
-
L15
I/O
IPD
EMB_D[22]
-
L14
I/O
IPD
EMB_D[21]
-
K16
I/O
IPD
EMB_D[20]
-
K13
I/O
IPD
EMB_D[19]
-
J14
I/O
IPD
EMB_D[18]
-
H15
I/O
IPD
EMB_D[17]
-
H14
I/O
IPD
SIGNAL NAME
PTP
ZKB
EMB_D[31]
-
EMB_D[30]
EMB_D[29]
ADVANCE INFORMATION
EMB_D[16]
-
G15
I/O
IPD
EMB_D[15]/GP6[15]
74
F13
I/O
IPD
EMB_D[14]/GP6[14]
76
E16
I/O
IPD
EMB_D[13]/GP6[13]
78
E13
I/O
IPD
EMB_D[12]/GP6[12]
79
D16
I/O
IPD
EMB_D[11]/GP6[11]
80
D15
I/O
IPD
EMB_D[10]/GP6[10]
82
D14
I/O
IPD
EMB_D[9]/GP6[9]
83
D13
I/O
IPD
EMB_D[8]/GP6[8]
84
C16
I/O
IPD
EMB_D[7]/GP6[7]
62
J16
I/O
IPD
EMB_D[6]/GP6[6]
63
J15
I/O
IPD
EMB_D[5]/GP6[5]
64
J13
I/O
IPD
EMB_D[4]/GP6[4]
66
H16
I/O
IPD
EMB_D[3]/GP6[3]
68
H13
I/O
IPD
EMB_D[2]/GP6[2]
70
G16
I/O
IPD
EMB_D[1]/GP6[1]
72
G13
I/O
IPD
EMB_D[0]/GP6[0]
73
F16
I/O
IPD
EMB_A[12]/GP3[13]
89
B15
O
IPD
EMB_A[11]/GP7[13]
91
B12
O
IPD
EMB_A[10]/GP7[12]
105
A9
O
IPD
EMB_A[9]/GP7[11]
92
C12
O
IPD
EMB_A[8]/GP7[10]
94
D12
O
IPD
EMB_A[7]/GP7[9]
95
A11
O
IPD
EMB_A[6]/GP7[8]
96
B11
O
IPD
EMB_A[5]/GP7[7]
97
C11
O
IPD
(1)
(2)
24
MUXED
DESCRIPTION
EMIFB SDRAM data bus.
GPIO
GPIO
EMIFB SDRAM row/column
address bus.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Device Overview
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
Table 3-8. External Memory Interface B (EMIFB) Terminal Functions (continued)
PULL (2)
D11
O
IPD
100
A10
O
IPD
101
B10
O
IPD
EMB_A[1]/GP7[3]
102
C10
O
IPD
EMB_A[0]/GP7[2]
103
D10
O
IPD
EMB_BA[1]/GP7[0]
106
B9
O
IPU
EMB_BA[0]/GP7[1]
107
C9
O
IPU
EMIFB SDRAM band
address.
EMB_CLK
86
C14
O
IPU
EMIF SDRAM clock.
EMB_SDCKE
88
C13
I/O
IPU
EMIFB SDRAM clock enable.
EMB_WE
59
K15
O
IPU
EMIFB write enable
EMB_RAS
110
A8
O
IPU
EMIFB SDRAM row address
strobe.
EMB_CAS
57
L13
O
IPU
EMIFB column address
strobe.
EMB_CS[0]
108
D9
O
IPU
EMIFB SDRAM chip select 0.
EMB_WE_DQM[3]
-
A12
O
IPU
EMB_WE_DQM[2]
-
B13
O
IPU
EMB_WE_DQM[1]/GP5[14]
85
C15
O
IPU
EMB_WE_DQM[0]/GP5[15]
60
K14
O
IPU
PTP
ZKB
EMB_A[4]/GP7[6]
98
EMB_A[3]/GP7[5]
EMB_A[2]/GP7[4]
3.6.6
MUXED
DESCRIPTION
EMIFB SDRAM row/column
address.
GPIO
EMIFB write enable/data
mask for EMB_D.
GPIO
Serial Peripheral Interface Modules (SPI0, SPI1)
Table 3-9. Serial Peripheral Interface (SPI) Terminal Functions
SIGNAL NAME
PIN NO
PTP
ZKB
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
SPI0
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
9
N4
I/O
IPU
UART0, EQEP0B,
GPIO, BOOT
SPI0 chip select.
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
12
R5
I/O
IPU
UART0, EQEP0A,
GPIO, BOOT
SPI0 enable.
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
11
T5
I/O
IPD
eQEP1, GPIO, BOOT SPI0 clock.
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
18
P6
I/O
IPD
eQEP0, GPIO, BOOT
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
17
R6
I/O
IPD
SPI0 data
slave-in-masterout.
SPI0 data
slave-out-masterin.
SPI1
SPI1_SCS[0]/UART2_TXD/GP5[13]
8
P4
I/O
IPU
SPI1_ENA/UART2_RXD/GP5[12]
7
R4
I/O
IPU
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
16
T6
I/O
IPD
(1)
(2)
UART2, GPIO
SPI1 chip select.
SPI1 enable.
eQEP1, GPIO, BOOT SPI1 clock.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Device Overview
25
ADVANCE INFORMATION
PIN NO
TYPE (1)
SIGNAL NAME
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
www.ti.com
Table 3-9. Serial Peripheral Interface (SPI) Terminal Functions (continued)
SIGNAL NAME
PIN NO
TYPE (1)
PULL (2)
N5
I/O
IPU
P5
I/O
IPU
PTP
ZKB
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
14
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
13
MUXED
I2C1, GPIO, BOOT
DESCRIPTION
SPI1 data
slave-in-masterout.
SPI1 data
slave-out-masterin.
ADVANCE INFORMATION
26
Device Overview
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3.6.7
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon
how the eCAP module is programmed.
Table 3-10. Enhanced Capture Module (eCAP) Terminal Functions
SIGNAL NAME
PIN NO
PTP
ZKB
TYPE (1)
PULL (2)
I/O
IPD
McASP0, GPIO
enhanced capture 0
input or auxiliary
PWM 0 output.
I/O
IPD
McASP0, GPIO
enhanced capture 1
input or auxiliary
PWM 1 output.
I/O
IPD
McASP1, GPIO
enhanced capture 2
input or auxiliary
PWM 2 output.
MUXED
DESCRIPTION
ACLKX0/ECAP0/APWM0/GP2[12]
126
C5
eCAP1
ACLKR0/ECAP1/APWM1/GP2[15]
130
B4
eCAP2
ACLKR1/ECAP2/APWM2/GP4[12]
(1)
(2)
165
L2
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.8
Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
Table 3-11. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions
SIGNAL NAME
PIN NO
PTP
ZKB
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
eHRPWM0
ACLKX1/EPWM0A/GP3[15]
162
K3
I/O
eHRPWM0 A output
(with
high-resolution).
IPD
McASP1, GPIO
eHRPWM0 B
output.
AHCLKX1/EPWM0B/GP3[14]
160
K2
I/O
IPD
AMUTE1/EPWMTZ/GP4[14]
-
D4
I/O
IPD
McASP1,
eHRPWM1, GPIO,
eHRPWM2
eHRPWM0 trip zone
input.
163
K4
I/O
IPD
McASP1,
eHRPWM0, GPIO
Sync input to
eHRPWM0 module
or sync output to
external PWM.
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
eHRPWM1
AXR1[8]/EPWM1A/GP4[8]
168
M2
I/O
IPD
AXR1[7]/EPWM1B/GP4[7]
169
M3
I/O
IPD
-
D4
I/O
IPD
eHRPWM1 A (with
high-resolution).
McASP1, GPIO
AMUTE1/EPWMTZ/GP4[14]
(1)
(2)
eHRPWM1 B
output.
McASP1,
eHRPWM0, GPIO,
eHRPWM2
eHRPWM1 trip zone
input.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Device Overview
27
ADVANCE INFORMATION
eCAP0
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
www.ti.com
Table 3-11. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions (continued)
PIN NO
SIGNAL NAME
PTP
TYPE (1)
ZKB
PULL (2)
MUXED
DESCRIPTION
eHRPWM2
AXR1[6]/EPWM2A/GP4[6]
170
M4
I/O
IPD
AXR1[5]/EPWM2B/GP4[5]
171
N1
I/O
IPD
-
D4
I/O
IPD
McASP1, GPIO
AMUTE1/EPWMTZ/GP4[14]
ADVANCE INFORMATION
3.6.9
McASP1,
eHRPWM0, GPIO,
eHRPWM2
eHRPWM2 A (with
high-resolution).
eHRPWM2 B
output.
eHRPWM2 trip zone
input.
Enhanced Quadrature Encoder Pulse Module (eQEP)
Table 3-12. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions
PIN NO
SIGNAL NAME
PTP
ZKB
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
eQEP0
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
12
R5
I
IPU
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
9
N4
I
IPU
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
17
R6
I
IPD
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
18
P6
I
IPD
SPIO, UART0,
GPIO, BOOT
SPI0, GPIO, BOOT
eQEP0A quadrature
input.
eQEP0B quadrature
input.
eQEP0 index.
eQEP0 strobe.
eQEP1
eQEP1A quadrature
input.
AXR1[3]/EQEP1A/GP4[3]
174
P1
I
IPD
AXR1[4]/EQEP1B/GP4[4]
173
N2
I
IPD
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
174
T5
I
IPD
SPI0, GPIO, BOOT
eQEP1 index.
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
16
T6
I
IPD
SPI1, GPIO, BOOT
eQEP1 strobe.
McASP1, GPIO
(1)
(2)
eQEP1B quadrature
input.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.10
Boot
Table 3-13. Boot Terminal Functions (1)
SIGNAL NAME
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
PIN NO
PTP
ZKB
23
P7
TYPE (2)
PULL (3)
MUXED
I
IPU
EMIFA, UHPI, GPIO
BOOT[15].
EMIFA, UHPI,
McASP0, GPIO
BOOT[14].
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
55
M13
I
IPU
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
54
M15
I
IPU
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12]
44
T13
I
IPU
(1)
(2)
(3)
28
EMIFA, MMC/SD,
UHPI, GPIO
DESCRIPTION
BOOT[13].
BOOT[12].
Boot decoding will be defined in the ROM datasheet.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
Table 3-13. Boot Terminal Functions (continued)
PIN NO
TYPE (2)
PULL (3)
A4
I
IPD
McASP0, EMAC,
GPIO
BOOT[11].
D5
I
IPD
McASP0, GPIO
BOOT[10].
BOOT[9].
PTP
ZKB
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
129
AFSX0/GP2[13]/BOOT[10]
127
MUXED
DESCRIPTION
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
3
P3
I
IPU
UART0, I2C0,
Timer0, GPIO
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
2
R3
I
IPU
UART0, I2C0,
Timer0, GPIO
BOOT[8].
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
16
T6
I
IPD
SPI1, eQEP1, GPIO
BOOT[7].
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
14
N5
I
IPU
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
13
P5
I
IPU
SPI1, I2C1, GPIO
BOOT[6].
BOOT[5].
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
9
N4
I
IPU
SPI0, UART0,
eQEP0, GPIO
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
12
R5
I
IPU
SPI0, UART0,
eQEP0, GPIO
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
11
T5
I
IPD
SPIO, eQEP1, GPIO BOOT[2].
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
18
P6
I
IPD
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
17
R6
I
IPD
SPI0, eQEP0, GPIO
ADVANCE INFORMATION
SIGNAL NAME
BOOT[4].
BOOT[3].
BOOT[1].
BOOT[0].
3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
Table 3-14. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions
SIGNAL NAME
PIN NO
PTP
ZKB
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
UART0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
2
R3
I
IPU
I2C0, BOOT,
Timer0, GPIO,
UART0 receive
data.
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
3
P3
O
IPU
I2C0, Timer0,
GPIO, BOOT
UART0 transmit
data.
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
9
N4
O
IPU
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
12
R5
I
IPU
UART0
clear-to-send input
UART1 receive
data.
UART0
ready-to-send
output
SPIO, eQEP0,
GPIO, BOOT
UART1
UART1_RXD/AXR0[9]/GP3[9]
122
C6
I
IPD
UART1_TXD/AXR0[10]/GP3[10]
123
D6
O
IPD
UART1 transmit
data.
UART2 receive
data.
McASP0, GPIO
UART2
SPI1_ENA/UART2_RXD/GP5[12]
7
R4
I
IPU
SPI1_SCS[0]/UART2_TXD/GP5[13]
8
P4
O
IPU
SPI1, GPIO
(1)
(2)
UART2 transmit
data.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.12 Inter-Integrated Circuit Modules(I2C0, I2C1)
Table 3-15. Inter-Integrated Circuit (I2C) Terminal Functions
PIN NO
SIGNAL NAME
PTP
ZKB
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
I2C0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
2
R3
I/O
IPU
UART0, Timer0,
GPIO, BOOT
I2C0 serial data.
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
3
P3
I/O
IPU
UART0, Timer0,
GPIO, BOOT
I2C0 serial clock.
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
14
N5
I/O
IPU
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
13
P5
I/O
IPU
I2C1
ADVANCE INFORMATION
(1)
(2)
SPI1, GPIO,
BOOT
I2C1 serial Data.
I2C1 serial clock.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.13 Timers
Table 3-16. Timers Terminal Functions
SIGNAL NAME
PIN NO
PTP
ZKB
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
TIMER0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
2
R3
I
IPU
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
3
P3
O
IPU
UART0, I2C0,
GPIO, BOOT
Timer0 lower
input.
Timer0 lower
output
TIMER1 (Watchdog )
No external pins. The Timer1 peripheral pins are not pinned out as external pins.
(1)
(2)
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.14
Universal Host-Port Interface (UHPI)
Note:
The UHPI module requires 16 data pins for the host port interface to function. Therefore on the PTP, only
the GPIO pin capability is supported on the UHPI peripherals.
30
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Table 3-17. Universal Host-Port Interface (UHPI) Terminal Functions
TYPE (
PULL (2)
M16
I/O
IPD
N14
I/O
IPD
-
N16
I/O
IPD
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]
-
P14
I/O
IPD
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11]
-
P16
I/O
IPD
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10]
-
R14
I/O
IPD
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9]
-
T14
I/O
IPD
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8]
-
N12
I/O
IPD
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/
BOOT[13]
-
M15
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
-
N13
I/O
IPU
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
-
N15
I/O
IPU
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
-
P13
I/O
IPU
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
-
P15
I/O
IPU
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
-
R13
I/O
IPU
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
-
R15
I/O
IPU
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/
BOOT[12]
-
T13
I/O
IPU
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
-
P9
I/O
IPU
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
-
R9
I/O
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]
-
P8
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
-
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15]
PTP
ZKB
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15]
-
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]
-
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]
MUXED
DESCRIPTION
EMIFA, LCD, GPIO
EMIFA, MMC/SD,
GPIO, BOOT
UHPI data bus.
EMIFA, MMC/SD,
GPIO
EMIFA, MMC/SD,
GPIO, BOOT
IPU
EMIFA,
MMCSD_CMD,
GPIO
UHPI access
control.
I/O
IPU
EMIFA, LCD, GPIO
UHPI half-word
identification control.
M13
I/O
IPU
EMIFA, McASP,
GPIO, BOOT
UHPI read/write.
-
P7
I/O
IPU
EMIFA, GPIO,
BOOT
UHPI chip select.
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8]
-
P12
I/O
IPU
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
-
R7
I/O
IPU
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9]
-
M14
I/O
IPU
EMA_WAIT[0]/UHPI_HRDY/GP2[10]
-
N6
I/O
IPU
EMA_CS[0]/UHPI_HAS/GP2[4]
(1)
(2)
-
T8
I/O
IPU
EMIFA, McASP0,
GPIO
UHPI data strobe.
UHPI host interrupt.
UHPI ready.
EMIFA, GPIO
UHPI address
strobe.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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PIN NO
1)
SIGNAL NAME
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
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3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
Table 3-18. Multichannel Audio Serial Ports (McASPs) Terminal Functions
SIGNAL NAME
PIN NO
PTP
ZKB
TYPE (1) PULL (2)
MUXED
DESCRIPTION
McASP0
ADVANCE INFORMATION
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9]
-
M14
I/O
IPU
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8]
-
P12
I/O
IPU
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7]
24
R7
I/O
IPU
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14]
55
M13
I/O
IPU
EMIFA, UHPI,
GPIO, BOOT
AXR0[11]/AXR2[0]/GP3[11]
124
A5
I/O
IPD
McASP2,
GPIO
AXR0[10]/UART1_TXD/GP3[10]
123
D6
I/O
IPD
GPIO
AXR0[9]/GP3[9]
122
C6
I/O
IPD
GPIO
AXR0[8]/MDIO_D/GP3[8]
121
B6
I/O
IPU
AXR0[7]/MDIO_CLK/GP3[7]
120
A6
I/O
IPD
AXR0[6]/RMII_RXER/ACLKR2/GP3[6]
118
D7
I/O
IPD
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5]
117
C7
I/O
IPD
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4]
116
B7
I/O
IPD
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3]
115
A7
I/O
IPD
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2]
113
D8
I/O
IPD
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1]
112
C8
I/O
IPD
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0]
111
B8
I/O
IPD
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
125
B5
I/O
IPD
McASP0
McASP2, USB,
transmit master
GPIO
clock.
ACLKX0/ECAP0/APWM0/GP2[12]
126
C5
I/O
IPD
eCAP0, GPIO
McASP0
transmit bit
clock.
AFSX0/GP2[13]/BOOT[10]
127
D5
I/O
IPD
GPIO, BOOT
McASP0
transmit frame
sync.
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
129
A4
I/O
IPD
EMAC, GPIO,
BOOT
McASP0 receive
master clock.
ACLKR0/ECAP1/APWM1/GP2[15]
130
B4
I/O
IPD
eCAP1, GPIO
McASP0 receive
bit clock.
AFSR0/GP3[12]
131
C4
I/O
IPD
GPIO
McASP0 receive
frame sync.
-
L4
O
IPD
RESETOUT
McASP0 mute
output.
AMUTE0/RESETOUT
(1)
(2)
32
EMIFA, UHPI,
GPIO
MDIO, GPIO
McASP0 serial
data.
EMAC,
McASP2,
GPIO
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-18. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)
SIGNAL NAME
PIN NO
PTP
ZKB
TYPE (1) PULL (2)
MUXED
DESCRIPTION
McASP1
AXR1[11]/GP5[11]
-
T4
I/O
IPU
AXR1[10]/GP5[10]
-
N3
I/O
IPU
AXR1[9]/GP4[9]
-
M1
I/O
IPD
AXR1[8]/EPWM1A/GP4[8]
168
M2
I/O
IPD
eHRPWM1 A,
GPIO
AXR1[7]/EPWM1B/GP4[7]
169
M3
I/O
IPD
eHRPWM1 B,
GPIO
AXR1[6]/EPWM2A/GP4[6]
170
M4
I/O
IPD
eHRPWM2 A,
GPIO
AXR1[5]/EPWM2B/GP4[5]
171
N1
I/O
IPD
eHRPWM2 B,
GPIO
AXR1[4]/EQEP1B/GP4[4]
173
N2
I/O
IPD
AXR1[3]/EQEP1A/GP4[3]
174
P1
I/O
IPD
AXR1[2]/GP4[2]
175
P2
I/O
IPD
AXR1[1]/GP4[1]
176
R2
I/O
IPD
AXR1[0]/GP4[0]
1
T3
I/O
IPD
AHCLKX1/EPWM0B/GP3[14]
160
K2
I/O
IPD
eHRPWM0,
GPIO
McASP1
transmit master
clock.
ACLKX1/EPWM0A/GP3[15]
162
K3
I/O
IPD
eHRPWM0,
GPIO
McASP1
transmit bit
clock.
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
163
K4
I/O
IPD
eHRPWM0,
GPIO
McASP1
transmit frame
sync.
-
L1
I/O
IPD
GPIO
McASP1 receive
master clock.
ACLKR1/ECAP2/APWM2/GP4[12]
165
L2
I/O
IPD
eCAP2, GPIO
McASP1 receive
bit clock.
AFSR1/GP4[13]
166
L3
I/O
IPD
GPIO
McASP1 receive
frame sync.
eHRPWM0,
eHRPWM1,
GPIO,
eHRPWM2
McASP1 mute
output.
McASP0,
EMAC, GPIO
McASP2 serial
data.
AMUTE1/EPWMTZ/GP4[14]
132
D4
O
IPD
McASP1 serial
data.
eQEP, GPIO
GPIO
McASP2
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2]
-
D8
I/O
IPD
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3]
-
A7
I/O
IPD
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4]
-
B7
I/O
IPD
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
-
B5
I/O
IPD
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1]
-
C8
I/O
IPD
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5]
-
C7
I/O
IPD
McASP0,
EMAC, GPIO
McASP2
transmit frame
sync.
EMA_CLK/OBSCLK/AHCLKR2/GP1[15]
-
R12
I/O
IPU
EMIFA, GPIO
McASP2 receive
master clock.
AXR0[6]/RMII_RXER/ACLKR2/GP3[6]
-
D7
I/O
IPD
McASP0,
EMAC, GPIO
McASP2 receive
bit clock.
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McASP2
transmit master
McASP0, USB, clock.
GPIO
McASP2
transmit bit
clock.
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AHCLKR1/GP4[11]
GPIO
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
www.ti.com
Table 3-18. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)
PIN NO
SIGNAL NAME
PTP
ZKB
-
T7
EMA_CS[3]/AMUTE2/GP2[6]
TYPE (1) PULL (2)
O
IPU
MUXED
DESCRIPTION
McASP2 mute
output.
EMIFA, GPIO
3.6.16 Universal Serial Bus Modules (USB0, USB1)
Table 3-19. Universal Serial Bus (USB) Terminal Functions
SIGNAL NAME
PIN NO
PTP
TYPE (1) PULL (2)
ZKB
DESCRIPTION
ADVANCE INFORMATION
USB0 2.0 OTG (USB0)
USB0_DM
138
USB0_DP
137
USB0_VDDA33
140
USB0_VSSA33
139
USB0_VDDA18
A
USB0 PHY data minus
F4
A
USB0 PHY data plus
H5
PWR
USB0 PHY 3.3-V supply
H4
PWR
USB0 PHY 3.3-V supply reference
135
E3
PWR
USB0 PHY 1.8-V supply input
134
C3
PWR
USB0 PHY 1.2-V LDO output for bypass cap
136
F3
PWR
USB0 PHY 1.8-V and 1.2-V supply reference
USB0_ID
-
D2
A
USB0 PHY identification (mini-A or mini-B plug)
USB0_VBUS
-
D3
A
USB0 bus voltage
USB0_DRVVBUS/GP4[15]
-
E4
0
IPD
USB0 controller VBUS control output. Multiplexed
with GPIO bank 4 pin 15.
125
B5
I
IPD
USB_REFCLKIN. Optional clock input.
USB0_VDDA12
(3)
USB0_VSSA
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
G4
USB1 1.1 OHCI (USB1)
USB1_DM
-
B3
A
USB1 PHY data minus
USB1_DP
-
A3
A
USB1 PHY data plus
USB1_VDDA33
-
C1
PWR
USB1_VDDA18
-
C2
PWR
125
B5
I
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
(1)
(2)
(3)
USB1 PHY 3.3-V supply
USB1 PHY 1.8-V supply
IPD
USB_REFCLKIN. Optional clock input.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Core power supply LDO output for USB PHY. This pin must be connected via a 0.22 -µF capacitor to VSS. When the USB peripheral is
not used, the USB_VDDA12 signal should still be connected via a 1-µF capacitor to VSS.
3.6.17 Ethernet Media Access Controller (EMAC)
Table 3-20. Ethernet Media Access Controller (EMAC) Terminal Functions
SIGNAL NAME
PIN NO
PTP
ZKB
TYPE (1) PULL (2)
MUXED
DESCRIPTION
RMII
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
(1)
(2)
34
129
A4
I/O
IPD
McASP0, GPIO, BOOT
EMAC 50-MHz
clock input or
output.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-20. Ethernet Media Access Controller (EMAC) Terminal Functions (continued)
PIN NO
TYPE (1) PULL (2)
PTP
ZKB
AXR0[6]/RMII_RXER/ACLKR2/GP3[6]
118
D7
I
IPD
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5]
117
C7
I
IPD
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4]
116
B7
I
IPD
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3]
115
A7
I
IPD
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2]
113
D8
O
IPD
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1]
112
C8
O
IPD
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0]
111
B8
O
IPD
MUXED
DESCRIPTION
EMAC RMII
receiver error.
EMAC RMII
receive data.
McASP0, McASP2, GPIO
EMAC RMII carrier
sense data valid.
EMAC RMII
transmit enable.
EMAC RMII trasmit
data.
MDIO
AXR0[8]/MDIO_D/GP3[8]
121
B6
I/O
IPU
AXR0[7]/MDIO_CLK/GP3[7]
120
A6
O
IPD
McASP0, GPIO
MDIO data clock.
3.6.18 Multimedia Card/Secure Digital (MMC/SD)
Table 3-21. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions
PIN NO
TYPE (1)
PULL (2)
R9
O
IPU
P9
I/O
IPU
54
M15
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
52
N13
I/O
IPU
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
51
N15
I/O
IPU
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
49
P13
I/O
IPU
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
48
P15
I/O
IPU
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
46
R13
I/O
IPU
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
45
R15
I/O
IPU
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12]
44
T13
I/O
IPU
SIGNAL NAME
PTP
ZKB
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
30
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
31
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13]
(1)
(2)
MUXED
DESCRIPTION
EMIFA, UHPI, GPIO
MMCSD_CLK.
MMCSD_CMD.
EMIFA, UHPI, GPIO,
BOOT
EMIFA, UHPI, GPIO
MMC/SD data.
EMIFA, UHPI, GPIO,
BOOT
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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SIGNAL NAME
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
3.6.19
www.ti.com
Liquid Crystal Display Controller(LCD)
Table 3-22. Liquid Crystal Display Controller (LCD) Terminal Functions
PIN NO
TYPE (1)
PULL (2)
M16
I/O
IPD
-
N14
I/O
IPD
-
N16
I/O
IPD
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12]
-
P14
I/O
IPD
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11]
-
P16
I/O
IPD
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10]
-
R14
I/O
IPD
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9]
-
T14
I/O
IPD
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8]
-
N12
I/O
IPD
EMA_A[0]/LCD_D[7]/GP1[0]
-
T9
I/O
IPD
EMA_A[3]/LCD_D[6]/GP1[3]
-
N9
I/O
IPD
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13]
-
P8
I/O
IPU
EMA_BA[0]/LCD_D[4]/GP1[14]
-
R8
I/O
IPU
EMA_A[4]/LCD_D[3]/GP1[4]
-
T10
I/O
IPD
EMA_A[5]/LCD_D[2]/GP1[5]
-
R10
I/O
IPD
EMA_A[6]/LCD_D[1]/GP1[6]
-
P10
I/O
IPD
EMA_A[7]/LCD_D[0]/GP1[7]
-
N10
I/O
IPD
EMA_A[8]/LCD_PCLK/GP1[8]
-
T11
O
IPU
EMA_A[9]/LCD_HSYNC/GP1[9]
-
R11
O
IPU
LCD horizontal sync.
EMA_A[10]/LCD_VSYNC/GP1[10]
-
N8
O
IPU
LCD vertical sync.
EMA_A[11]/LCD_AC_ENB_CS/GP1[11]
-
P11
O
IPU
LCD AC bias enable
chip select.
EMA_A[12]/LCD_MCLK/GP1[12]
-
N11
O
IPU
LCD memory clock.
SIGNAL NAME
PTP
ZKB
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15]
-
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14]
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13]
ADVANCE INFORMATION
(1)
(2)
MUXED
DESCRIPTION
EMIFA, UHPI,
GPIO
LCD data bus.
EMIFA, GPIO
EMIFA, UHPI,
GPIO
EMIFA, GPIO
LCD pixel clock.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.20 Reserved
Table 3-23. Reserved Terminal Functions
SIGNAL NAME
PIN NO
TYPE (1)
DESCRIPTION
PTP
ZKB
RSV1
-
F7
PWR
Reserved. (Leave unconnected, do not connect to power or
ground.)
RSV2
133
B1
PWR
Reserved. For proper device operation, this pin must be tied
directly to CVDD.
RSV3
149
-
PWR
Reserved. For proper device operation, this pin must be tied
directly to CVDD.
RSV4
148
-
PWR
Reserved. For proper operation, this pin must be tied low."
(1)
PWR = Supply voltage.
36
Device Overview
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
3.6.21 Supply and Ground
Table 3-24. Supply and Ground Terminal Functions
PTP
ZKB
F6,G6, G7,
G10, G11,
H7, H10,
H11, J6, J7,
J10, J11,
J12, K6, K7,
K10, K11,L6
CVDD (Core supply)
10, 20, 28,
38, 50, 56,
61, 69, 77,
93, 104, 114,
147, 154,
161, 167,
RVDD (Internal RAM supply)
67, 159
DVDD (I/O supply)
5, 15, 24, 33,
43, 47, 53,
58, 65, 71,
75, 81, 87,
90, 99, 109,
119, 128,
151, 158,
164, 172,
177
A1, A2, A15,
A16,
B2,
E6, E7, E10,
E11,
F8, F9, F10,
G8, G9,
H8, H9,
J8, J9,
K8, K9,
L7, L8, L9,
L10,
M6, M7, M10,
M11,
T1, T2, T15,
T16
VSS (Ground)
(1)
TYPE (1)
DESCRIPTION
PWR
1.2-V core supply voltage pins
H6, H12
PWR
1.2V internal ram supply voltage pins
B16, E5, E8,
E9, E12, F5,
F11, F12,
G5, G12, K5,
K12, L5, L11,
L12, M5, M8,
M9, M12, R1,
R16
PWR
3.3-V I/O supply voltage pins.
GND
Ground pins.
ADVANCE INFORMATION
PIN NO
SIGNAL NAME
PWR = Supply voltage, GND - Ground.
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TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
www.ti.com
4 Device Configuration
4.1 Introduction
This device supports a variety of boot modes through an internal DSP ROM bootloader. This device does
not support dedicated hardware boot modes; therefore, all boot modes utilize the internal DSP ROM. The
input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the
system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is
determined by the values of the BOOT pins.
See Using the D800K001 Bootloader Application Report (SPRAB04) for more details on the ROM Boot
Loader.
ADVANCE INFORMATION
4.2 Boot Modes Supported
The following boot modes are supported:
• NAND Flash boot
– 8-bit NAND
– 16-bit NAND
• NOR Flash boot
– NOR Direct boot
– NOR Legacy boot
– NOR AIS boot
• HPI Boot
• I2C0/I2C1 Boot
– Master boot
– Slave boot
• SPI0/SPI1 Boot
– Master boot
– Slave boot
For more details on the boot mode selection, see TMS320C6745/C6747 DSP System Reference Guide
SPRUFK4.
4.3 SYSCFG Module
The following system level features of the chip are controlled by the SYSCFG peripheral:
• Readable Device, Die, and Chip Revision ID
• Control of Pin Multiplexing
• Priority of bus accesses different bus masters in the system
• Capture at power on reset the chip BOOT[15:0] pin values and make them available to software
• Special case settings for peripherals:
– Locking of PLL controller settings
– Default burst sizes for EDMA3 TC0 and TC1
– Selection of the source for the eCAP module input capture (including on chip sources)
– McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals
– Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
– Clock source selection for EMIFA and EMIFB
• Selects the source of emulation suspend signal (from DSP) of peripherals supporting this function. The
emulation suspend signal is active anytime the core processor is halted. Some peripherals support
operation options when the emulation suspend signal is active, such as halting with the processor,
38
Device Configuration
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Since the SYSCFG peripheral controls global operation of the device, its registers are protected against
erroneous accesses by several mechanisms:
• A special key sequence must be written to KICK0, KICK1 registers before any other registers are
writeable.
– Unlock sequence: write 0x83e70b13 to KICK0, then write 0x95A4F1E0 to KICK1
– SYSCFG remains unlocked after the unlock sequence until locked again.
– Any number of accesses may be performed while the module is unlocked
– Locking the module is accomplished by writing any other value to either KICK0 or KICK1
• Additionally, many registers are accessible only by a host (DSP) when it is operating in its privileged
mode. (ex. from the kernel, but not from user space code).
Table 4-1. System Configuration (SYSCFG) Module Register Access
Acronym
Register Description
0x01C1 4000
Offset
REVID
Revision Identification Register
Access
—
0x01C14008 –
0x01C1 4014
DIEIDR0-DIEDR3
Device Identification Register 0 - 3
—
0x01C1 4020
BOOTCFG
Boot Configuration Register
Privileged mode
0x01C1 4038
KICK0R
Kick 0 Register
Privileged mode
0x01C1 403C
KICK1R
Kick 1 Register
Privileged mode
0x01C1 4040
HOST0CFG
Host 0 Configuration Register
0x01C1 4044
HOST1CFG
Host 1 Configuration Register
0x01C1 40E0
IRAWSTAT
Interrupt Raw Status/Set Register
Privileged mode
0x01C1 40E4
IENSTAT
Interrupt Enable Status/Clear Register
Privileged mode
—
—
0x01C1 40E8
IENSET
Interrupt Enable Register
Privileged mode
0x01C1 40EC
IENCLR
Interrupt Enable Clear Register
Privileged mode
0x01C1 40F0
EOI
End of Interrupt Register
Privileged mode
0x01C1 40F4
FLTADDRR
Fault Address Register
Privileged mode
0x01C1 40F8
FLTSTAT
Fault Status Register
—
0x01C1
MSTPRI0-MSTPRI2
4110-0x01C1 4118
Master Priority 0-2 Registers
Privileged mode
0x01C1
PINMUX0-PINMUX19
4120-0x01C1 416C
Pin Multiplexing Control 0-19 Registers
Privileged mode
Privileged mode
0x01C1 4170
SUSPSRC
Suspend Source Register
0x01C1 4174
CHIPSIG
Chip Signal Register
0x01C1 4178
CHIPSIG_CLR
Chip Signal Clear Register
0x01C1
417C-0x01C1
418C
CFGCHIP0-CFGCHIP4
Chip Configuration 0-4 Registers
—
—
Privileged mode
4.4 Pin Multiplexing Control Registers
Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module.
For the 674x device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is
multiplexed with several different functions has a corresponding 4-bit field in one of the PINMUX registers.
Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data
and output enable values only. The default pin multiplexing control for almost every pin is to select 'none'
of the peripheral functions in which case the pin's IO buffer is held tri-stated.
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completing the current operation then halting, or continuing operation. See the appropriate peripheral
documentation for specific details.
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
www.ti.com
Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX
registers have no effect on input from a pin. This feature allows a pin such as
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] to be used as both the McASP0 AHCLKX0 (output) pin,
and the McASP2 AHCLKX2 master clock (input) pin simultaneously.
For more details, refer TMS320C6745/C6747 DSP System Reference Guide, Literature Number SPRUFK4
ADVANCE INFORMATION
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4.5 Bus Master Priority Configuration
ADVANCE INFORMATION
The on chip switch fabric performs priority based arbitration among the various bus masters on the device.
The priority of each master is controlled by the MSTPRI0, MSTPRI1, and MSTPRI2 registers and may be
adjusted as required to suite a particular application. Section 4.5.1 through Section 4.5.3 give provide a
detailed description of these registers.
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TMS320C6745/6747 Floating-point Digital Signal Processor
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4.5.1
31
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MSTPRI0 Register Definition (0x01C1 4110)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
R/W-0
R/W-100
R/W-0
R/W-100
R/W-0
R/W-100
R/W-0
R/W-100
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RSV
DSP_CFG
RSV
DSP_MDMA
RSV
RSV
RSV
RSV
R/W-0
R/W-010
R/W-0
R/W-010
R/W-0
R/W-010
R/W-0
R/W-010
16
0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-1. MSTPRI0 Bit Description
ADVANCE INFORMATION
Table 4-2. MSTPRI0 Field Descriptions
Bit
Field
Description
31
RSV
Reserved - Write 0 to this Field when modifying this register.
30:28
RSV
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
27
RSV
Reserved - Write 0 to this Field when modifying this register.
26:24
RSV
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
23
RSV
Reserved - Write 0 to this Field when modifying this register.
22:20
RSV
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
19
RSV
Reserved - Write 0 to this Field when modifying this register.
18:16
RSV
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
15
14:12
11
10:8
42
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
RSV
Reserved - Write 0 to this Field when modifying this register.
DSP_CFG
Bus Priority for Bus Master DSP - Configuration Bus - Default Value is 010
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
RSV
Reserved - Write 0 to this Field when modifying this register.
DSP_MDMA
Bus Priority for Bus Master DSP - DMA Bus - Default Value is 010
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
7
RSV
Reserved - Write 0 to this Field when modifying this register.
6:0
RSV
Reserved - Write 0 to this Field when modifying this register.
Device Configuration
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4.5.2
31
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
MSTPRI1 Register Definition (0x01C1 4114)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
R/W-0
R/W-100
R/W-0
R/W-100
R/W-0
R/W-100
R/W-0
R/W-100
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RSV
TC1
RSV
TC0
RSV
RSV
RSV
RSV
R/W-0
R/W-000
R/W-0
R/W-000
R/W-0
R/W-000
R/W-0
R/W-000
16
0
Figure 4-2. MSTPRI1 Bit Description
Table 4-3. MSTPRI1 Field Descriptions
Bit
Field
Description
31
RSV
Reserved - Write 0 to this Field when modifying this register.
30:28
RSV
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
27
RSV
Reserved - Write 0 to this Field when modifying this register.
26:24
RSV
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
23
RSV
Reserved - Write 0 to this Field when modifying this register.
22:20
RSV
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
19
RSV
Reserved - Write 0 to this Field when modifying this register.
18:16
RSV
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
15
RSV
Reserved - Write 0 to this Field when modifying this register.
14:12
TC1
Bus Priority for Bus Master EDMA3 TC1 - Default Value is 000
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
11
RSV
Reserved - Write 0 to this Field when modifying this register.
10:8
TC0
Bus Priority for Bus Master EDMA3 TC0 - Default Value is 000
7:0
RSV
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
Reserved - Write 0 to this Field when modifying this register.
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ADVANCE INFORMATION
LEGEND: R = Read, W = Write, n = value at reset
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
4.5.3
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MSTPRI2 Register Definition (0x01C1 4118)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RSV
LCDC
RSV
USB1
RSV
UHPI
RSV
RSV
R/W-0
R/W-101
R/W-0
R/W-100
R/W-0
R/W-110
R/W-0
R/W-000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RSV
USB0CDMA
RSV
USB0VBUSP
RSV
RSV
RSV
EMAC
R/W-0
R/W-100
R/W-0
R/W-100
R/W-0
R/W-000
R/W-0
R/W-100
16
0
LEGEND: R = Read, W = Write, n = value at reset. In a loaded system, the LCDC default priority value of 5 might not be a good default and
may need to be changed.
ADVANCE INFORMATION
Figure 4-3. MSTPRI2 Bit Description
Table 4-4. MSTPRI2 Field Descriptions
Bit
Field
Description
31
RSV
Reserved - Write 0 to this Field when modifying this register.
LCDC
Bus Priority for Bus Master LCDC - Default Value is 101
30:28
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
27
RSV
Reserved - Write 0 to this Field when modifying this register.
26:24
USB1
Bus Priority for Bus Master USB1 - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
23
RSV
Reserved - Write 0 to this Field when modifying this register.
22:20
UHPI
Bus Priority for Bus Master UHPI - Default Value is 110
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
19
RSV
Reserved - Write 0 to this Field when modifying this register.
18:16
RSV
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 000
15
14:12
11
10:8
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
RSV
Reserved - Write 0 to this Field when modifying this register.
USB0CDMA
Bus Priority for Bus Master USB0 - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
RSV
Reserved - Write 0 to this Field when modifying this register.
USB0VBUSP
Bus Priority for Bus Master USB0 - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
7
RSV
Reserved - Write 0 to this Field when modifying this register.
6:4
RSV
Reserved For Future Use - Write Default Value to Maintain Compatibility - Default Value is 000
3
2:0
44
000 = Priority 0 (Highest)
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
RSV
Reserved - Write 0 to this Field when modifying this register.
EMAC
Bus Priority for Bus Master EMAC - Default Value is 100
000 = Priority 0 (Highest)
010 = Priority 2
100 = Priority 4
110 = Priority 6
001 = Priority 1
011 = Priority 3
101 = Priority 5
111 = Priority 7 (lowest)
Device Configuration
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4.6 Chip Configuration Registers (CFGCHIP and SUSPSRC)
These registers control EDMA3 default transfer burst sizes, clock muxing, McASP AMUTE and eCAP
sources, UHPI enable and configuration, and USB PHY settings
4.6.1
31
CFGCHIP0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
0
Reserved
R-n/a
14
13
12
11
10
9
8
7
Reserved
6
5
Reserved
R-n/a
R/W-1
4
3
PLL_MASTER_LOCK
R/W-000
R/W-0
2
TC1DBS
R/W-00
TC0DBS
ADVANCE INFORMATION
15
R/W-00
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-4. CFGCHIP0 Register Bit Layout
Table 4-5. CFGCHIP0 Field Description
Bit
Field
31:5
Reserved
Reserved
Description
4
PLL_MASTER_LOCK
This bit is used to lock the PLL MMRs
0 = PLLCTRL MMR registers are freely accessible.
1 = PLLCTRL MMR registers are locked.
3:2
TC1DBS
EDMA3 TC1 Default Burst Size
00
01
10
11
1:0
TC0DBS
16 byte
32 byte
64 byte
Reserved
EDMA3 TC1 Default Burst Size
00
01
10
11
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=
=
=
=
=
=
=
=
16 byte
32 byte
64 byte
Reserved
Device Configuration
45
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
4.6.2
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CFGCHIP1
31
30
29
28
27
26
25
CAP2SRC
24
R/W-0
15
14
HPIENA
R/W-0
22
21
20
19
13
12
11
TBCLKSYNC
R/W-0
10
18
17
16
CAP0SRC
R/W-0
Rsvd
R/W-0
23
CAP1SRC
HPIBYTEAD
R/W-0
9
8
AMUTESEL2
7
6
5
4
AMUTESEL1
R/W-0
R/W-0
3
2
1
0
AMUTESEL0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-5. CFGCHIP1 Register Bit Layout
ADVANCE INFORMATION
Table 4-6. CFGCHIP1 Field Description
Bit
Field
31:27
CAP2SRC
eCAP2 Module Event Input Select
Description
26:22
CAP1SRC
eCAP1 Module Event Input Select
21:17
CAP0SRC
eCAP0 Module Event Input Select
For each eCAPx (x=0,1,2):
00000 = eCAPx Pin Input
00001 = McASP0 TX DMA Event
00010 = McASP0 RX DMA Event
00011 = McASP1 TX DMA Event
00100 = McASP1 RX DMA Event
00101 = McASP2 TX DMA Event
00110 = McASP2 RX DMA Event
00111 = EMAC C0 RX Threshold Pulse Interrupt
01000 = EMAC C0 RX Pulse Interrupt
01001 = EMAC C0 TX Pulse Interrupt
01010 = EMAC C0 Misc Interrupt01011 = EMAC C1 RX Threshold Pulse Interrupt
01100 = EMAC C1 RX Pulse Interrupt
01101 = EMAC C1 TX Pulse Interrupt
01110 = EMAC C1 Misc Interrupt
01111 = EMAC C2 RX Threshold Pulse Interrupt
10000 = EMAC C2 RX Pulse Interrupt
10001 = EMAC C2 TX Pulse Interrupt
10010 = EMAC C2 Misc Interrupt
10011 - 11111 = Reserved
16
HPIBYTEAD
HPI Module Byte / Word Address Mode
15
HPIENA
14:13
Reserved
Reserved
12
TBCLKSYNC
eHRPWM Module Time Base Clock Sync
0 = Host Address is a word address
0 = HPI Disabled
0 (default) = The TBCLK (Time Base
Clock) within each enabled
eHRPWM is stopped.
11:8
AMUTESEL2
Selects the source of the McASP2 AMUTEIN signal
7:4
AMUTESEL1
Selects the source of the McASP1 AMUTEIN signal
3:0
AMUTESEL0
Selects the source of the McASP0 AMUTEIN signal
46
1 = Host Address is a byte address
HPI Enable Bit
Device Configuration
1 = HPI Enabled
1 = All enabled eHRPWM module
clocks are started with the first
rising edge of TBCLK aligned.
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Table 4-6. CFGCHIP1 Field Description (continued)
Bit
Field
Description
ADVANCE INFORMATION
For each McASPx (x=0,1,2)
0000 = Drive McASPx AMUTEIN Low
0001 = McASPx AMUTEIN source is GPIO Interrupt from Bank 0
0010 = McASPx AMUTEIN source is GPIO Interrupt from Bank 1
0011 = McASPx AMUTEIN source is GPIO Interrupt from Bank 2
0100 = McASPx AMUTEIN source is GPIO Interrupt from Bank 3
0101 = McASPx AMUTEIN source is GPIO Interrupt from Bank 4
0110 = McASPx AMUTEIN source is GPIO Interrupt from Bank 5
0111 =McASPx AMUTEIN source is GPIO Interrupt from Bank 6
1000 = McASPx AMUTEIN source is GPIO Interrupt from Bank 7
1001 - 1111 are reserved
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4.6.3
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CFGCHIP2
31
30
29
28
27
26
25
24
RESERVED
R-n/a
23
22
21
20
19
18
RESERVED
17
16
USB0PHYCLKGD
USB0VBUSSENSE
R-n/a
15
14
ADVANCE INFORMATION
RESET
13
USB0OTGMODE
R/W-1
12
R/W-11
7
11
USB1PHYCLKMUX
R/W-0
6
USB1SUSPENDM
USB0PHY_PLLON
R/W-0
R/W-0
10
USB0PHYCLKMUX
R/W-1
5
USB0SESNDEN
9
R/W-1
4
3
R/W-1
2
USB0VBDTCTEN
R/W-0
8
USB0PHYPWDN USB0OTGPWRDN USB0DATPO
L
R/W-1
1
0
USB0REF-FREQ[3:0]
R/W-0
R/W-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-6. CFGCHIP2 Register Bit Layout
Table 4-7. CFGCHIP2 Field Description
Bit
Field
31:8
Reserved
Reserved
Description
17
USB0PHYCLKGD
Indicates clock is present, power is good and phy PLL is locked.
16
USB0VBUSSENSE
Indicates status of VBUS detection.
15
RESET
When '1' drives 'phy_reset' active to put the phy UTMI+ interface in reset.
14:13
USB0OTGMODE
OTGMODE = 00. Do not override phy values. Let PHY drive signals to controller based
on its comparators for the VBUS and ID pins.
OTGMODE = 01. Override phy values to force USB Host Operation.
Force VBUSVALID = 1, SESSVALID = 1, SESSEND = 0, IDDIG = 0
OTGMODE = 10. Override phy values to force USB Device Operation.
Force VBUSVALID = 1, SESSVALID = 1, SESSEND = 0, IDDIG = 1
OTGMODE = 11. Override phy values to force USB Host Operation with VBUS low.
Force VBUSVALID = 0, SESSVALID = 0, SESSEND = 1, IDDIG = 0
12
USB1PHYCLKMUX
USB1 PHY Clock Source.
1 = USB1 Phy Clock (48 MHz) is sourced by an external pin.
0 = USB1 Phy Clock (48 MHz) is sourced by the 48 MHz output of the USB0 PHY.
11
USB0PHYCLKMUX
USB0 PHY Clock Source.
1 = USB0 Phy reference clock internally generated.
0 = USB0 Phy reference clock comes from pin.
10
USB0PHYPWDN
Phy Powerdown, 0=Phy is powered up, 1=Phy is powered down.
9
USB0OTGPWRDN
OTG Analog Module Powerdown, 0=OTG Analog Module is powered up, 1=OTG Analog
Module is powered down.
8
USB0DATPOL
USB0 Data Polarity, 0 = Reversed DP/DM polarity, 1 = Normal DP/DM polarity.
7
USB1SUSPENDM
USB1 Phy Suspend, Program to '0' if USB1 is not used, Program to '1' if USB1 is used.
6
USB0PHY_PLLON
USB0 Phy PLL On, 0 = Normal USB Behavior, 1 = Override USB SUSPEND behavior
and release PLL from SUSPEND state.
5
USB0SESNDEN
Turns on session end comparator.
4
USB0VBDTCTEN
Turns on all VBUS line comparators.
48
Device Configuration
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Table 4-7. CFGCHIP2 Field Description (continued)
Field
3:0
USB0REF-FREQ[3:0]
4.6.4
31
Description
USB0 Phy Clock Input Select.
0000 = Reserved
0001 = 12 MHz
0010 = 24 MHz
0011 = 48 MHz
0100 = 19.2 MHz
0101 = 38.4 MHz
0110 = 13 MHz
0111 = 26 MHz
1000 = 20 MHz
1001 = 40 MHz
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
CFGCHIP3
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
R-n/a
15
14
13
12
2
1
0
Reserved
11
10
9
8
7
6
Reserved
5
4
3
DIV4P5EN
A
EMA_CL
KSRC
EMB_C
LKSRC
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-7. CFGCHIP3 Register Bit Layout
Table 4-8. CFGCHIP3 Field Description
Bit
Field
31:16
Reserved
Reserved
15:8
Reserved
Reserved
7:3
Reserved
Reserved
2
DIV4P5ENA
Fixed 4.5 divider Enable.
0 = Divide by 4.5 is Disabled. 1 = Divide by 4.5 is Enabled.
1
EMA_CLKSRC
EMIF A Memory Clock Source Select.
0 = EMIFA clock domain is driven by the PLLCTRL SYSCLK3 output.
1 = EMIFA clock domain is driven by the fixed / 4.5 PLL output.
0
EMB_CLKSRC
EMIF B Memory Clock Source Select.
0 = EMIFB SDRAM clock domain is driven by the PLLCTRL SYSCLK5 output.
1 = EMIFB SDRAM clock domain is driven by the fixed / 4.5 PLL output.
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Description
Device Configuration
49
ADVANCE INFORMATION
Bit
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
4.6.5
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CFGCHIP4
31
30
29
28
27
26
25
24
23
22
21
20
19
5
4
3
18
17
16
Reserved
R-n/a
15
14
13
12
2
1
0
Reserved
11
10
9
8
7
6
Reserved
AMUT
ECLR
2
AMUT
ECLR
1
AMUT
ECLR
0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write, n = value at reset
ADVANCE INFORMATION
Figure 4-8. CFGCHIP4 Register Bit Layout
Table 4-9. CFGCHIP4 Field Description
Bit
Field
31:16
Reserved
Reserved
15:8
Reserved
Reserved
7:3
Reserved
Reserved
2
AMUTECLR2
Write 1 causes a single pulse that clears the 'latched' GPIO interrupt for AMUTEIN of McASP2
when '1'. Always reads back '0'.
1
AMUTECLR1
Write 1 causes a single pulse that clears the 'latched' GPIO interrupt for AMUTEIN of McASP1
when '1'. Always reads back '0'.
0
AMUTECLR0
Write 1 causes a single pulse that clears the 'latched' GPIO interrupt for AMUTEIN of McASP1
when '1'. Always reads back '0'.
4.6.6
Description
SUSPSRC
The SUSPSRC register allows selection of the emulation suspend signal assigned to a peripheral. The
emulation suspend signal is active anytime the core processor is halted. Some peripherals support
operation options when the emulation suspend signal is active, such as halting with the processor,
completing the current operation then halting, or continuing operation. See the appropriate peripheral
documentation for specific details.
31
30
29
Reserved
28
27
26
25
24
23
TIMER TIMER GPIOS ePWM ePWM ePWM
64P1
64P0
RC
2SRC 1SRC 0SRC
22
21
20
19
18
17
16
SPI1
SRC
SPI0
SRC
UART
2SRC
UART
1 SRC
UART
0SRC
I2C1
SRC
I2C0
SRC
4
3
2
1
0
R/W-1
15
14
MMC /
SD /
SRC
13
Reserved
12
11
10
9
HPI
SRC
RSV
USB1
SRC
USB0
SRC
8
7
Reserved
6
5
RSV
EMAC
SRC
eQEP eQEP eCAP2 eCAP1 eCAP0
1 SRC 0 SRC SRC
SRC
SRC
R/W-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-9. SUSPSRC Register Bit Layout
Table 4-10. SUSPSRC Field Descriptions
Bit Field
Description
31: RSV
29
Reserved
50
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Table 4-10. SUSPSRC Field Descriptions (continued)
Bit Field
Description
28
TIMER64P1 Suspend Source.
TIMER64P1
0 = NO emulation suspend, 1 = DSP emulation suspend
27
TIMER64P0
26
GPIOSRC
25
ePWM2SRC
24
ePWM1SRC
23
ePWM0SRC
TIMER64P0 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
GPIO Module Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
ePWM2 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
ADVANCE INFORMATION
ePWM1 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
ePWM0 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
22
SPI1 SRC
21
SPI0 SRC
20
UART2 SRC
19
UART1 SRC
18
UART0 SRC
SPI1 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
SPI0 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
UART2 SRC Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
UART1 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
UART0 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
17
I2C1 SRC
16
I2C0 SRC
15
MMC/SD SRC
I2C1 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
I2C0 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
MMC /SD Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
14: Reserved
13
Reserved
12
HPI Suspend Source
HPI SRC
0 = NO emulation suspend, 1 = DSP emulation suspend
11
Reserved
Reserved
10
USB1 SRC
USB1 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
9
USB0 SRC
USB0 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
8:6 Reserved
5
EMACSRC
4
eQEP1SRC
Reserved
EMAC Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
eQEP1 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
3
eQEP0SRC
2
eCAP2SRC
eQEP0 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
eCAP2 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
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Table 4-10. SUSPSRC Field Descriptions (continued)
Bit Field
1
Description
eCAP1SRC
eCAP1 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
0
eCAP0SRC
eCAP0 Suspend Source
0 = NO emulation suspend, 1 = DSP emulation suspend
4.7 DSP Communication Registers
4.7.1
CHIPSIG
ADVANCE INFORMATION
The CHIPSIG register provides a signaling mechanism for the DSP.Writing a '1' to a bit causes the
corresponding interrupt to be asserted. Writing a '0' has no effect. Reads return the value of the bit.
31
30
29
28
27
26
25
24
23
22
21
20
19
7
6
5
4
3
18
17
16
2
1
0
Rsvd
R-0
15
14
13
12
11
10
9
8
Rsvd
CHIPSIG[4:0]
R-0
W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-10. CHIPSIG Register Bit Layout
Table 4-11. CHIPSIG Field Description
Bit
Field
31:5
Reserved
Reserved
4
CHIPSIG[4]
Asserts DSP NMI Interrupt.
3
CHIPSIG[3]
Asserts DSP Interrupt CHIPSIG[3].
2
CHIPSIG[2]
Asserts DSP Interrupt CHIPSIG[2].
1
CHIPSIG[1]
Reserved.
0
CHIPSIG[0]
Reserved.
4.7.2
Description
CHIPSIG_CLR
The CHIPSIG_CLR register clears interrupts that have been initiated using the CHIPSIG register. Writing
a '1' to a bit clears the corresponding interrupt. Writing a '0' has no effect. Reads return the value of the
bit.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
7
6
5
4
3
2
1
0
Rsvd
R-0
15
14
13
12
11
10
9
8
Rsvd
CHIPSIG[4:0]
R-0
W-0
LEGEND: R = Read, W = Write, n = value at reset
Figure 4-11. CHIPSIG_CLR Register Bit Layout
52
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Table 4-12. CHIPSIG_CLR Field Description
Bit
Field
31:5
Reserved
Reserved
Description
4
CHIPSIG[4]
Clears DSP NMI Interrupt.
3
CHIPSIG[3]
Clears DSP Interrupt CHIPSIG[3].
2
CHIPSIG[2]
Clears DSP Interrupt CHIPSIG[2].
1
CHIPSIG[1]
Reserved.
0
CHIPSIG[0]
Reserved.
4.8.1
Development Support
TI offers an extensive line of development tools for the TMS320C6745/47 platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tool's support documentation is electronically
available within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of TMS320C6745/47 applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for TMS320C6745/47 , visit the Texas Instruments
web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information
on pricing and availability, contact the nearest TI field sales office or authorized distributor.
4.8.2
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMS320C6745). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical
specifications.
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
TMS
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
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53
ADVANCE INFORMATION
4.8 Device Support
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
www.ti.com
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
ADVANCE INFORMATION
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, "Blank" is the default).
Figure 4-12 provides a legend for reading the complete device name for any TMS320C674x member.
TMS
320
C6747
( )
ZKB
( )
( )
PREFIX
TMX = Experimental Device
TMS = Qualified Device
DEVICE FAMILY
320 = TMS320™ DSP Family
DEVICE
C64x+™ C6747
C6745
SILICON REVISION
Blank = Revision 1.0
DEVICE SPEED RANGE
2 = 200 MHz
3 = 300 MHz(B)
TEMPERATURE RANGE (JUNCTION)
Blank = 0°C to 85°C, Commercial Grade
T
= –40°C to 105°C, Automotive Grade
PACKAGE TYPE(A)
ZKB = 256-Pin Plastic BGA, with Pb-free Soldered
Balls [Green]
PTP = 176-Pin Thin Quad Flat Pack (TQFP)
[PTP Suffix], 0.5 mm Pin Pitch
A.
BGA = Ball Grid Array
B.
The device speed range symbolization indicates the maximum CPU frequency when the core voltage CVDD is set to
1.2 V.
Figure 4-12. Device Nomenclature
4.9 Documentation Support
4.9.1
Related Documentation From Texas Instruments
The following documents describe the TMS320C6745/47 Low-power digital signal processor. Copies of
these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the
search box provided at www.ti.com.
DSP Reference Guides
SPRUG82
TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the
TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications.
Shows how to maintain coherence with external memory, how to use DMA to reduce
memory latencies, and how to optimize your code to improve cache efficiency. The internal
memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a
dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level.
Accesses by the CPU to the these first level caches can complete without CPU pipeline
stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next
lower memory level, L2 or external memory.
54
Device Configuration
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SPRUFE8
TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal
processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with
added functionality and an expanded instruction set.
SPRUFK4
TMS320C6747 DSP System Reference Guide. Describes the System-on-Chip (SoC)
including the DSP subsystem, system memory, device clocking, phase-locked loop controller
(PLLC), power and sleep controller (PSC), power management, and system configuration
module.
SPRUG83
TMS320C6745 DSP System Reference Guide. Describes the System-on-Chip (SoC)
including the DSP subsystem, system memory, device clocking, phase-locked loop controller
(PLLC), power and sleep controller (PSC), power management, and system configuration
module.
SPRUFK5
TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
SPRUFK9
TMS320C6745/C6747 DSP Peripherals Overview Reference Guide. Provides an
overview and briefly describes the peripherals available on the TMS320C6745/C6747 DSP.
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TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Case Temperature Range
(Unless Otherwise Noted) (1)
Core
(CVDD, RVDD, RTC_CVDD, PLL0_VDDA , USB0_VDDA12 (2), )
Supply voltage ranges
I/O, 1.8V
(USB0_VDDA18, USB1_VDDA18)
-0.5 V to 3.8V
(3)
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VI I/O, 1.2V
(OSCIN, RTC_XI)
-0.3 V to CVDD + 0.3V
VI I/O, 3.3V
(Steady State)
-0.3V to DVDD + 0.3V
VI I/O, 3.3V
(Transient)
DVDD + 20%
up to 20% of Signal
Period
VI I/O, USB 5V Tolerant Pins:
(USB0_DM, USB0_DP, USB0_ID, USB1_DM, USB1_DP)
5.25V (4)
VI I/O, USB0 VBUS
5.50V (4)
VO I/O, 3.3V
(Steady State)
Output voltage ranges
Clamp Current
-0.5 V to 1.4 V
-0.5 V to 2 V
(3)
I/O, 3.3V
(DVDD, USB0_VDDA33, USB1_VDDA33)
Input voltage ranges
(3)
-0.5 V to DVDD + 0.3V
VO I/O, 3.3V
(Transient)
DVDD + 20%
up to 20% of Signal
Period
Input or Output Voltages 0.3V above or below their respective power
rails. Limit clamp current that flows through the I/O's internal diode
protection cells.
±20mA
Operating Junction Temperature ranges,
TJ
(default)
(T version)
-40°C to 125°C
Storage temperature range, Tstg
(default)
-55°C to 150°C
(1)
(2)
(3)
(4)
56
0°C to 105°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This pin is an internal LDO output and connected via 0.22 F capacitor to VSS
All voltage values are with respect to VSS, USB0_VSSA33, USB0_VSSA, PLL0_VSSA, OSCVSS, RTC_VSS
Up to a max of 24 hours.
Device Operating Conditions
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MIN
NOM
MAX
UNIT
1.14
1.2 or 1.26
1.32
V
CVDD
Supply voltage, Core
(CVDD, RTC_CVDD, PLL0_VDDA , USB0_VDDA12 (1))
RVDD
Supply Voltage, Internal RAM
1.14
1.2 or 1.26
1.32
V
Supply voltage, I/O, 1.8V
(USB0_VDDA18, USB1_VDDA18)
1.71
1.8
1.89
V
Supply voltage, I/O, 3.3V
(DVDD, USB0_VDDA33, USB1_VDDA33)
3.15
3.3
3.45
V
0
0
0
V
DVDD
(2)
Supply ground
(VSS, USB0_VSSA33, USB0_VSSA, PLL0_VSSA, OSCVSS (3),
RTC_VSS (3))
VSS
High-level input voltage, I/O, 3.3V
VIH
High-level input voltage, RTC_XI
High-level input voltage, OSCIN
2
V
0.8*RTC_CVDD
V
0.8*CVDD
Low-level input voltage, I/O, 3.3V
VIL
Low-level input voltage, RTC_XI
Low-level input voltage, OSCIN
VHYS
Input Hysteresis
tt
Transition time, 10%-90%, All Inputs
Operating ambient temperature range
FSYSCLK1,6
DSP and ARM Operating Frequency
(SYSCLK1,6)
(1)
(2)
(3)
V
V
0.2*CVDD
0.1DVDD
10
ns
0
70
°C
-40
105
°C
Default
0
300
MHz
Automotive (T
suffix)
0
300
MHz
Default
TA
0.8
0.2*RTC_CVDD
Automotive (T
suffix)
This pin is an internal LDO output and connected via 0.22 F capacitor to VSS
Future variants of TI devices may operate at CVDD voltages ranging from 1.0 V to 1.32 V to provide a range of system power/
performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V,
1.1 V, 1.2, 1.26 V with ±5% tolerances) by implementing simple board changes such as reference resistor values or input pin
configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI
devices. RVDD and PLL0_VDDA must always be maintained at the voltages shown. (1.14 V - 1.32 V).
Oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected directly to the crystal load capacitor
ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit board.
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5.2 Recommended Operating Conditions
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
PARAMETER
VOH
ADVANCE INFORMATION
(1)
TYP
MAX
USB0_VDDA33
High speed:
USB_DM and USB_DP
360
440
Low/full speed:
USB1_DM and USB1_DP
2.8
USB1_VDDA33
DVDD = 3.15V, IOH = -4 mA
DVDD = 3.15V, IOH = -100 µA
UNIT
V
mV
V
2.4
V
2.95
V
Low/full speed:
USB_DM and USB_DP
0.0
0.3
V
High speed:
USB_DM and USB_DP
-10
10
mV
DVDD = 3.15V, IOL = 4mA
0.4
V
DVDD = 3.15V, IOL = -100 µA
0.2
V
VI = VSS to DVDD without opposing
internal resistor
±35
µA
Low-level output voltage (3.3V I/O)
II
MIN
2.8
High-level output voltage (3.3V I/O)
VOL
TEST CONDITIONS
Low/full speed:
USB0_DM and USB0_DP
Input current
VI = VSS to DVDD with opposing
internal pullup resistor (2)
30
200
µA
VI = VSS to DVDD with opposing
internal pulldown resistor (2)
-50
-250
µA
IOH
High-level output current
All peripherals
-4
mA
IOL
Low-level output current
All peripherals
4
mA
(1)
(2)
58
II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
Device Operating Conditions
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6 Peripheral Information and Electrical Specifications
6.1 Parameter Information
Parameter Information Device-Specific Information
Tester Pin Electronics
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see note)
4.0 pF
A.
1.85 pF
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see note)
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1.1
Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.
Vref
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
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6.1.1
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6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
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Peripheral Information and Electrical Specifications
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6.3 Power Supplies
6.3.1
Power-on Sequence
674x devices include on chip logic that ensures I/O pins are tri-stated during the power on ramp, as long
as the RESET pin is asserted. This is true even if the core voltage (CVDD) has not yet ramped.
However, if the on chip USB modules are used; then to limit any noise on the USB0_DM, USB0_DP,
USB1_DM, and USB1_DP pins to less than 200mV during the power on ramp, the sequence illustrated in
Figure 6-4 must be followed. The requirement is that the core supply (CVDD) must ramp to at least 0.9V
(1) before the IO supply (DVDD) reaches the 1.65V point in its ramp (2). And as is always the case,
RESET and TRST must remain asserted during the power on ramp and released only after CVDD and
DVDD are within their specified ranges.
(2)
1.65 V
DVDD
(3)
(1)
CVDD
RESET, TRST
USB0_DM, USB0_DP
USB1_DM, USB1_DP
900 mV
VIL
200 mV
Figure 6-4. Power Sequence
6.4 Reset
6.4.1
Power-On Reset (POR)
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are tri-stated with the exception of RESETOUT which remains active
through the reset sequence. RESETOUT is an output for use by other controllers in the system that
indicates the device is currently in reset.
A summary of the effects of Power-On Reset is given below:
• All internal logic (including emulation logic and the PLL logic) is reset to its default state
• Internal memory is not maintained through a POR
• RESETOUT goes active
• All device pins go to a high-impedance state
• The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC
A watchdog reset triggers a POR.
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Normally, the only requirement during the power on ramp is that both the RESET and TRST pins remain
asserted (low) until after the power supply rails have fully ramped.
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
6.4.2
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Warm Reset
A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low
(TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their
default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT which
remains active through the reset sequence. RESETOUT is an output for use by other controllers in the
system that indicates the device is currently in reset.
ADVANCE INFORMATION
A summary of the effects of Warm Reset is given below:
• All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
• Internal memory is maintained through a warm reset
• RESETOUT goes active
• All device pins go to a high-impedance state
• The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the
RTC
6.4.3
Reset Electrical Data Timings
Table 6-1 assumes testing over the recommended operating conditions.
Table 6-1. Reset Timing Requirements ( (1),
(2)
NO
)
MIN
1
tw(RSTL)
Pulse width, RESET/TRST low
2
tsu(BPV-RSTH)
Setup time, boot pins valid before RESET/TRST high
3
th(RSTH-BPV)
Hold time, boot pins valid after RESET/TRST high
4
td(RSTH-
RESET high to RESETOUT high; Warm reset
4096
RESETOUTH)
RESET high to RESETOUT high; Power-on Reset
6192
5
(1)
(2)
(3)
MAX
UNIT
100
ns
20
ns
20
td(RSTL-RESETOUTL) Delay time, RESET/TRST low to RESETOUT low
ns
cycles (3)
TBD
ns
RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-4 for details.
For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this
table refer to RESET only (TRST is held high).
OSCIN cycles.
Power
Supplies
Ramping
Power Supplies Stable
Clock Source Stable
OSCIN
1
RESET
TRST
4
RESETOUT
3
2
Boot Pins
Config
Figure 6-5. Power-On Reset (RESET and TRST active) Timing
62
Peripheral Information and Electrical Specifications
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Power Supplies Stable
OSCIN
TRST
1
RESET
5
4
3
2
Boot Pins
Driven or Hi-Z
ADVANCE INFORMATION
RESETOUT
Config
Figure 6-6. Warm Reset (RESET active, TRST high) Timing
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6.5 Crystal Oscillator or External Clock Input
The C6745/6747 device includes two choices to provide an external clock input, which is fed to the
on-chip PLL to generate high-frequency system clocks. These options are illustrated in Figure 6-7 and
Figure 6-8.
• Figure 6-7 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit.
• Figure 6-8 illustrates the option that uses an external 1.2V clock input.
C2
OSCIN
Clock Input
to PLL
X1
ADVANCE INFORMATION
OSCOUT
C1
OSCVSS
Figure 6-7. On-Chip 1.2V Oscillator
OSCIN
NC
Clock
Input
to PLL
OSCOUT
OSCVSS
Figure 6-8. External 1.2V Clock Source
Table 6-2. CLKIN Timing Requirements
MIN
MAX
UNIT
fosc
Oscillator frequency range (OSCIN/OSCOUT)
12
30
MHz
fPLL
Freuency range of PLL input , external clock source only
12
50
MHz
tc(CLKIN)
Cycle time, external clock driven on OSCIN
20
ns
tw(CLKINH)
Pulse width high, external clock on OSCIN
0.4
ns
tc(CLKIN)
tw(CLKINL)
Pulse width low, external clock on OSCIN
tt(CLKIN)
Transition time, CLKIN
64
Peripheral Information and Electrical Specifications
0.4
tc(CLKIN)
ns
5
ns
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6.6 Clock PLLs
The C6745/6747 has one PLL controller that provides clock to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device.
The various clock outputs given by the controller are as follows:
• Domain Clocks: SYSCLK [1:n]
• Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
• Post-PLL Divider: POSTDIV
• SYSCLK Divider: D1, , Dn
Various other controls supported are as follows:
• PLL Multiplier Control: PLLM
• Software programmable PLL Bypass: PLLEN
6.6.1
PLL Device-Specific Information
The C6745/6747 DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The PLL requires some external filtering components to reduce power supply noise as shown in
Figure 6-9.
1.14V - 1.32V
50R
PLL0_VDDA
0.1
µF
VSS
50R
0.01
µF
PLL0_VSSA
Ferrite Bead: Murata BLM31PG500SN1L or Equivalent
Figure 6-9. PLL External Filtering Components
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
CLKIN pin. The PLL outputs seven clocks that have programmable divider options. Figure 6-10 illustrates
the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in Table 6-3 before enabling the DSP to run from the PLL by setting
PLLEN = 1.
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The PLL controller provides the following:
• Glitch-Free Transitions (on changing clock settings)
• Domain Clocks Alignment
• Clock Gating
• PLL power down
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DIV4p5
(/4.5)
Clock Input
from CLKIN
or OSCIN
PREDIV
(/1 to /32)
PLLREF
PLLOUT
PLLM
(x4 to x32)
POSTDIV
(/2 to /32)
1
0
PLLEN
(PLL_CSR[0])
ADVANCE INFORMATION
PLLDIV1
(/1, /2,
... /32)
SYSCLK1
PLLDIV2
(/1, /2,
... /32)
SYSCLK2
PLLDIV3
(/1, /2,
... /32)
SYSCLK3
PLLDIV4
(/1, /2,
... /32)
SYSCLK4
PLLDIV7
(/1, /2,
... /32)
SYSCLK7
AUXCLK
Figure 6-10. PLL Topology
Table 6-3. Allowed PLL Operating Conditions
NO
PARAMETER
MIN
MAX
UNIT
1
PLLRST: Assertion time during initialization
125
N/A
ns
2
Lock time: The time that the application has to wait for the
PLL to acquire locks before setting PLLEN, after changing
PREDIV, PLLM, or OSCIN
N/A
3
PLL input frequency
( PLLREF after D0)
12
50
x4
x32
400
600 (2)
4
5
(1)
(2)
66
PLL multiplier values (PLLM)
(1)
PLL output frequency. ( PLLOUT before dividers D1, D2, D3,
....)
2000 N
m
where N = Pre-Divider Ratio
M = PLL Multiplier
Max PLL Lock Time =
ns
MHz
MHz
The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 400 and 1000 MHz, but the
frequency going into the SYSCLK dividers (after the post divider) cannot exceed 400 MHz. If the PLLOUT exceeds 400 MHz the post
divider must be used to divide it down. The Post Divider and SYSCLK divider values must be chosen such that the CPU clocks do not
exceed 300 MHz.
PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL
output clock.
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6.6.2
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
Device Clock Generation
PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the
system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software,
in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the
chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock
alignment, and test points.
PLLC0 generates several clocks from the PLL0 output clock for use by the various processors and
modules. These are summarized in Table 6-4. The clock ratios between SYSCLK1, SYSCLK2, SYSCLK4
and SYSCLK6 must always be maintained as shown in the table.
Output
Clock
Used by
Default Ratio (relative to
SYSCLK1)
Notes
SYSCLK1
DSP
/1
No Required Ratio
SYSCLK2
EDMA, DSP ports, EMIFB (ports to switch fabric), ECAP 0/1/2,
EHRPWM 0/1/2, EQEP 0/1, Shared RAM, LCDC, McASP/FIFO
0/1/2, SPI 1, UHPI, USB2.0 (logic), UART 1/2, HRPWM 0/1/2
/2
SYSCLK1 / 2
SYSCLK3
EMIFA
/3
No Required Ratio
SYSCLK4
SYSCFG, Interrupt Controller, PLLC0, PSC 0, EMAC/MDIO, GPIO,
I2C 1, PSC 1, USB1.1
/4
SYSCLK1 / 4
SYSCLK5
EMIFB
/3
No Required Ratio
SYSCLK7
RMII clock to EMAC
/6
No Required Ratio ;
Should be set to 50 MHz
AUXCLK
McASP AuxClk,RTC,Timer64P0,Timer64P1
N/A
No Required Ratio
USB48
USB2.0 Phy, USB1.1 logic
N/A
No Required Ratio; Should
be set to 48 MHz
USB12
USB2.0 Phy, USB1.1 logic
N/A
No Required Ratio; 12
MHz, generated by the
USB1 Module by dividing
USB48 by 4.
DIV4p5
133MHz clock source for EMIFB
PLL output/4.5
No Required Ratio
•
•
•
The divide values in the PLL Controller 0 for SYSCLK1/SYSCLK6, SYSCLK2 and SYSCLK4 are not
fixed so that user can change the divide values for power saving reasons. But users are responsible to
guarantee that the divide ratios between these clock domains must be fixed to 1:2:4.
Although the PLL is capable of running at 600 MHz, the SYSCLK dividers in the PLLC0 are not
(maximum 400 MHz). For this reason, the post-divider in the PLLC0 should be configured for /2 to
provide 300 MHz to each of the SYSCLK dividers.
The DIV4p5 (/4.5) hardware clock divider is provided to generate 133 MHz from the 600 MHz PLL
clock for use as clocks to the EMIFs.
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Table 6-4. System PLLC0 Output Clocks
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6.7 Interrupts
The C6745/6747devices have a large number of interrupts to service the needs of its many peripherals
and subsystems.
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6.7.1
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DSP Interrupts
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The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 6-5. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 6-6
summarizes the C674x interrupt controller registers and memory locations.
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Table 6-5. C6745/6747 DSP Interrupts
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70
EVT#
Interrupt Name
0
EVT0
Source
C674x Int Ctl 0
1
EVT1
C674x Int Ctl 1
2
EVT2
C674x Int Ctl 2
3
EVT3
C674x Int Ctl 3
4
T64P0_TINT12
5
SYSCFG_CHIPINT2
Timer64P0 - TINT12
6
-
7
EHRPWM0
8
EDMA3_CC0_INT1
9
EMU-DTDMA
C674x-ECM
10
EHRPWM0TZ
HiResTimer/PWM0 Trip Zone Interrupt
11
EMU-RTDXRX
C674x-RTDX
12
EMU-RTDXTX
C674x-RTDX
13
IDMAINT0
C674x-EMC
14
IDMAINT1
C674x-EMC
15
MMCSD_INT0
MMCSD MMC/SD Interrupt
16
MMCSD_INT1
MMCSD SDIO Interrupt
17
-
18
EHRPWM1
HiResTimer/PWM1 Interrupt
19
USB0_INT
USB0 Interrupt
20
USB1_HCINT
21
USB1_RWAKEUP
22
-
23
EHRPWM1TZ
SYSCFG_CHIPSIG Register
Reserved
HiResTimer/PWM0 Interrupt
EDMA3 CC0 Region 1 interrupt
Reserved
USB1 OHCI Host Controller Interrupt
USB1 Remote Wakeup Interrupt
Reserved
HiResTimer/PWM1 Trip Zone Interrupt
24
EHRPWM2
25
EHRPWM2TZ
HiResTimer/PWM2 Interrupt
26
EMAC_C0RXTHRESH
27
EMAC_C0RX
EMAC - Core 0 Receive Interrupt
28
EMAC_C0TX
EMAC - Core 0 Transmit Interrupt
29
EMAC_C0MISC
30
EMAC_C1RXTHRESH
31
EMAC_C1RX
EMAC - Core 1 Receive Interrupt
32
EMAC_C1TX
EMAC - Core 1 Transmit Interrupt
33
EMAC_C1MISC
34
UHPI_DSPINT
35
-
36
IIC0_INT
I2C0
37
SP0_INT
SPI0
38
UART0_INT
39
-
40
T64P1_TINT12
Timer64P1 Interrupt 12
41
GPIO_B1INT
GPIO Bank 1 Interrupt
42
IIC1_INT
I2C1
43
SPI1_INT
SPI1
HiResTimer/PWM2 Trip Zone Interrupt
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Miscellaneous Interrupt
UHPI DSP Interrupt
Reserved
UART0
Reserved
44
-
45
ECAP0
ECAP0
46
UART_INT1
UART1
Peripheral Information and Electrical Specifications
Reserved
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Table 6-5. C6745/6747 DSP Interrupts (continued)
EVT#
Interrupt Name
Source
47
ECAP1
ECAP1
48
T64P1_TINT34
Timer64P1 Interrupt 34
49
GPIO_B2INT
GPIO Bank 2 Interrupt
50
-
51
ECAP2
52
GPIO_B3INT
53
EQEP1
54
GPIO_B4INT
55
EMIFA_INT
56
EDMA3_CC0_ERRINT
EDMA3 Channel Controller 0
57
EDMA3_TC0_ERRINT
EDMA3 Transfer Controller 0
58
EDMA3_TC1_ERRINT
EDMA3 Transfer Controller 1
59
GPIO_B5INT
60
EMIFB_INT
EMIFB Memory Error Interrupt
61
MCASP_INT
McASP0,1,2 Combined RX/TX Interrupts
62
GPIO_B6INT
GPIO Bank 6 Interrupt
63
RTC_IRQS
64
T64P0_TINT34
Timer64P0 Interrupt 34
65
GPIO_B0INT
GPIO Bank 0 Interrupt
Reserved
ECAP2
GPIO Bank 3 Interrupt
EQEP1
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
RTC Combined
66
-
67
SYSCFG_CHIPINT3
68
EQEP0
EQEP0
69
UART2_INT
UART2
70
PSC0_ALLINT
PSC0
71
PSC1_ALLINT
PSC1
72
GPIO_B7INT
73
LCDC_INT
LDC Controller
74
PROTERR
SYSCFG Protection Shared Interrupt
75
-
Reserved
76
-
Reserved
77
-
Reserved
78
T64P0_CMPINT0
Timer64P0 - Compare 0
79
T64P0_CMPINT1
Timer64P0 - Compare 1
80
T64P0_CMPINT2
Timer64P0 - Compare 2
81
T64P0_CMPINT3
Timer64P0 - Compare 3
82
T64P0_CMPINT4
Timer64P0 - Compare 4
83
T64P0_CMPINT5
Timer64P0 - Compare 5
84
T64P0_CMPINT6
Timer64P0 - Compare 6
85
T64P0_CMPINT7
Timer64P0 - Compare 7
86
T64P1_CMPINT0
Timer64P1 - Compare 0
87
T64P1_CMPINT1
Timer64P1 - Compare 1
88
T64P1_CMPINT2
Timer64P1 - Compare 2
89
T64P1_CMPINT3
Timer64P1 - Compare 3
90
T64P1_CMPINT4
Timer64P1 - Compare 4
91
T64P1_CMPINT5
Timer64P1 - Compare 5
92
T64P1_CMPINT6
Timer64P1 - Compare 6
93
T64P1_CMPINT7
Timer64P1 - Compare 7
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EMIFA
Reserved
SYSCFG_CHIPSIG Register
GPIO Bank 7 Interrupt
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Table 6-5. C6745/6747 DSP Interrupts (continued)
ADVANCE INFORMATION
72
EVT#
Interrupt Name
94
-
Source
Reserved
95
-
Reserved
96
INTERR
C674x-Int Ctl
97
EMC_IDMAERR
C674x-EMC
98
-
Reserved
99
-
Reserved
100
-
Reserved
101
-
Reserved
102
-
Reserved
103
-
Reserved
104
-
Reserved
105
-
Reserved
106
-
Reserved
107
-
Reserved
108
-
Reserved
109
-
Reserved
110
-
Reserved
111
-
Reserved
112
-
Reserved
113
PMC_ED
114
-
Reserved
115
-
Reserved
116
UMC_ED1
C674x-UMC
117
UMC_ED2
C674x-UMC
118
PDC_INT
C674x-PDC
119
SYS_CMPA
C674x-SYS
120
PMC_CMPA
C674x-PMC
121
PMC_CMPA
C674x-PMC
122
DMC_CMPA
C674x-DMC
123
DMC_CMPA
C674x-DMC
124
UMC_CMPA
C674x-UMC
125
UMC_CMPA
C674x-UMC
126
EMC_CMPA
C674x-EMC
127
EMC_BUSERR
C674x-EMC
Peripheral Information and Electrical Specifications
C674x-PMC
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BYTE ADDRESS
REGISTER NAME
DESCRIPTION
0x0180 0000
EVTFLAG0
Event flag register 0
0x0180 0004
EVTFLAG1
Event flag register 1
0x0180 0008
EVTFLAG2
Event flag register 2
0x0180 000C
EVTFLAG3
Event flag register 3
0x0180 0020
EVTSET0
Event set register 0
0x0180 0024
EVTSET1
Event set register 1
0x0180 0028
EVTSET2
Event set register 2
0x0180 002C
EVTSET3
Event set register 3
0x0180 0040
EVTCLR0
Event clear register 0
0x0180 0044
EVTCLR1
Event clear register 1
0x0180 0048
EVTCLR2
Event clear register 2
0x0180 004C
EVTCLR3
Event clear register 3
0x0180 0080
EVTMASK0
Event mask register 0
0x0180 0084
EVTMASK1
Event mask register 1
0x0180 0088
EVTMASK2
Event mask register 2
0x0180 008C
EVTMASK3
Event mask register 3
0x0180 00A0
MEVTFLAG0
Masked event flag register 0
0x0180 00A4
MEVTFLAG1
Masked event flag register 1
0x0180 00A8
MEVTFLAG2
Masked event flag register 2
0x0180 00AC
MEVTFLAG3
Masked event flag register 3
0x0180 00C0
EXPMASK0
Exception mask register 0
0x0180 00C4
EXPMASK1
Exception mask register 1
0x0180 00C8
EXPMASK2
Exception mask register 2
0x0180 00CC
EXPMASK3
Exception mask register 3
0x0180 00E0
MEXPFLAG0
Masked exception flag register 0
0x0180 00E4
MEXPFLAG1
Masked exception flag register 1
0x0180 00E8
MEXPFLAG2
Masked exception flag register 2
0x0180 00EC
MEXPFLAG3
Masked exception flag register 3
0x0180 0104
INTMUX1
Interrupt mux register 1
0x0180 0108
INTMUX2
Interrupt mux register 2
0x0180 010C
INTMUX3
Interrupt mux register 3
0x0180 0140 - 0x0180 0144
-
Reserved
0x0180 0180
INTXSTAT
Interrupt exception status
0x0180 0184
INTXCLR
Interrupt exception clear
0x0180 0188
INTDMASK
Dropped interrupt mask register
0x0180 01C0
EVTASRT
Event assert register
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Peripheral Information and Electrical Specifications
ADVANCE INFORMATION
Table 6-6. C674x DSP Interrupt Controller Registers
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6.8 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
ADVANCE INFORMATION
The C6745/6747 GPIO peripheral supports the following:
• Up to 128 Pins on ZKB and up to 109 Pins on PTP package configurable as GPIO
• External Interrupt and DMA request Capability
– Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or
falling edges on the pin.
– The interrupt requests within each bank are combined (logical or) to create eight unique bank level
interrupt requests.
– The bank level interrupt service routine may poll the INTSTATx register for its bank to determine
which pin(s) have triggered the interrupt.
– GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59, 62
and 72 respectively
– Additionally, GPIO Banks 0, 1, 2, 3, 4, and 5 Interrupts assigned to EDMA events 6, 7, 22, 23, 28,
and 29 respectively.
• Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
• Separate Input/Output registers
• Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 6-7. See the TMS320C6745/C6747 DSP
Peripherals Overview Reference Guide. – Literature Number SPRUFK9 for more details.
6.8.1
GPIO Register Description(s)
Table 6-7. GPIO Registers
GPIO
BYTE ADDRESS
Acronym
Register Description
0x01E2 6000
REV
Peripheral Revision Register
0x01E2 6004
RESERVED
Reserved
0x01E2 6008
BINTEN
GPIO Interrupt Per-Bank Enable Register
GPIO Banks 0 and 1
74
0x01E2 6010
DIR01
GPIO Banks 0 and 1 Direction Register
0x01E2 6014
OUT_DATA01
GPIO Banks 0 and 1 Output Data Register
0x01E2 6018
SET_DATA01
GPIO Banks 0 and 1 Set Data Register
0x01E2 601C
CLR_DATA01
GPIO Banks 0 and 1 Clear Data Register
0x01E2 6020
IN_DATA01
GPIO Banks 0 and 1 Input Data Register
0x01E2 6024
SET_RIS_TRIG01
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
0x01E2 6028
CLR_RIS_TRIG01
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
0x01E2 602C
SET_FAL_TRIG01
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
Peripheral Information and Electrical Specifications
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Table 6-7. GPIO Registers (continued)
GPIO
BYTE ADDRESS
Acronym
Register Description
0x01E2 6030
CLR_FAL_TRIG01
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
0x01E2 6034
INTSTAT01
GPIO Banks 0 and 1 Interrupt Status Register
0x01E2 6038
DIR23
GPIO Banks 2 and 3 Direction Register
0x01E2 603C
OUT_DATA23
GPIO Banks 2 and 3 Output Data Register
0x01E2 6040
SET_DATA23
GPIO Banks 2 and 3 Set Data Register
0x01E2 6044
CLR_DATA23
GPIO Banks 2 and 3 Clear Data Register
0x01E2 6048
IN_DATA23
GPIO Banks 2 and 3 Input Data Register
0x01E2 604C
SET_RIS_TRIG23
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
0x01E2 6050
CLR_RIS_TRIG23
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
0x01E2 6054
SET_FAL_TRIG23
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
0x01E2 6058
CLR_FAL_TRIG23
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
0x01E2 605C
INTSTAT23
ADVANCE INFORMATION
GPIO Banks 2 and 3
GPIO Banks 2 and 3 Interrupt Status Register
GPIO Banks 4 and 5
0x01E2 6060
DIR45
GPIO Banks 4 and 5 Direction Register
0x01E2 6064
OUT_DATA45
GPIO Banks 4 and 5 Output Data Register
0x01E2 6068
SET_DATA45
GPIO Banks 4 and 5 Set Data Register
0x01E2 606C
CLR_DATA45
GPIO Banks 4 and 5 Clear Data Register
0x01E2 6070
IN_DATA45
GPIO Banks 4 and 5 Input Data Register
0x01E2 6074
SET_RIS_TRIG45
GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
0x01E2 6078
CLR_RIS_TRIG45
GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
0x01E2 607C
SET_FAL_TRIG45
GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
0x01E2 6080
CLR_FAL_TRIG45
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
0x01E2 6084
INTSTAT45
GPIO Banks 4 and 5 Interrupt Status Register
0x01E2 6088
DIR67
GPIO Banks 6 and 7 Direction Register
0x01E2 608C
OUT_DATA67
GPIO Banks 6 and 7 Output Data Register
0x01E2 6090
SET_DATA67
GPIO Banks 6 and 7 Set Data Register
0x01E2 6094
CLR_DATA67
GPIO Banks 6 and 7 Clear Data Register
0x01E2 6098
IN_DATA67
GPIO Banks 6 and 7 Input Data Register
0x01E2 609C
SET_RIS_TRIG67
GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
0x01E2 60A0
CLR_RIS_TRIG67
GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
0x01E2 60A4
SET_FAL_TRIG67
GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
0x01E2 60A8
CLR_FAL_TRIG67
GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
0x01E2 60AC
INTSTAT67
GPIO Banks 6 and 7 Interrupt Status Register
GPIO Banks 6 and 7
6.8.2
GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-8. Timing Requirements for GPIO Inputs (1) (see Figure 6-11)
NO.
(1)
(2)
MIN MAX
UNIT
(1) (2)
ns
ns
1
tw(GPIH)
Pulse duration, GPIx high
2C
2
tw(GPIL)
Pulse duration, GPIx low
2C (1) (2)
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have C6745/6747
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow C6745/6747
enough time to access the GPIO register through the internal bus.
C=SYSCLK4 period in ns. For example, when running parts at 300 MHz, C=13.33 ns
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Table 6-9. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-11)
NO.
3
4
(1)
PARAMETER
tw(GPOH)
tw(GPOL)
MIN
2C (1)
Pulse duration, GPOx high
Pulse duration, GPOx low
2C
MAX
UNIT
(2)
ns
(1) (2)
ns
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
C=SYSCLK4 period in ns. For example, when running parts at 300 MHz, C=13.33 ns
(2)
2
1
GPIx
ADVANCE INFORMATION
4
3
GPOx
Figure 6-11. GPIO Port Timing
6.8.3
GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-10. Timing Requirements for External Interrupts (1) (see Figure 6-12)
NO.
MIN
1
tw(ILOW)
Width of the external interrupt pulse low
2C
(1) (2)
ns
2
tw(IHIGH)
Width of the external interrupt pulse high
2C
(1) (2)
ns
(1)
(2)
MAX
UNIT
The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have C6745/6747 recognize
the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow C6745/6747 enough time
to access the GPIO register through the internal bus.
C=SYSCLK4 period in ns. For example, when running parts at 300 MHz, C=13.33 ns
2
1
EXT_INTx
Figure 6-12. GPIO External Interrupt Timing
76
Peripheral Information and Electrical Specifications
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6.9 EDMA
Table 6-11 is the list of EDMA3 Channel Contoller Registers and Table 6-12 is the list of EDMA3 Transfer
Controller registers.
Table 6-11. EDMA3 Channel Controller (EDMA3CC) Registers
BYTE ADDRESS
Acronym
Register Description
0x01C0 0000
PID
Peripheral Identification Register
0x01C0 0004
CCCFG
EDMA3CC Configuration Register
0x01C0 0200
QCHMAP0
QDMA Channel 0 Mapping Register
0x01C0 0204
QCHMAP1
QDMA Channel 1 Mapping Register
0x01C0 0208
QCHMAP2
QDMA Channel 2 Mapping Register
0x01C0 020C
QCHMAP3
QDMA Channel 3 Mapping Register
0x01C0 0210
QCHMAP4
QDMA Channel 4 Mapping Register
0x01C0 0214
QCHMAP5
QDMA Channel 5 Mapping Register
0x01C0 0218
QCHMAP6
QDMA Channel 6 Mapping Register
0x01C0 021C
QCHMAP7
QDMA Channel 7 Mapping Register
0x01C0 0240
DMAQNUM0
DMA Channel Queue Number Register 0
0x01C0 0244
DMAQNUM1
DMA Channel Queue Number Register 1
0x01C0 0248
DMAQNUM2
DMA Channel Queue Number Register 2
0x01C0 024C
DMAQNUM3
DMA Channel Queue Number Register 3
0x01C0 0260
QDMAQNUM
QDMA Channel Queue Number Register
0x01C0 0284
QUEPRI
Queue Priority Register (1)
0x01C0 0300
EMR
Event Missed Register
0x01C0 0308
EMCR
Event Missed Clear Register
0x01C0 0310
QEMR
QDMA Event Missed Register
0x01C0 0314
QEMCR
QDMA Event Missed Clear Register
0x01C0 0318
CCERR
EDMA3CC Error Register
0x01C0 031C
CCERRCLR
EDMA3CC Error Clear Register
0x01C0 0320
EEVAL
Error Evaluate Register
0x01C0 0340
DRAE0
DMA Region Access Enable Register for Region 0
0x01C0 0348
DRAE1
DMA Region Access Enable Register for Region 1
0x01C0 0350
DRAE2
DMA Region Access Enable Register for Region 2
0x01C0 0358
DRAE3
DMA Region Access Enable Register for Region 3
0x01C0 0380
QRAE0
QDMA Region Access Enable Register for Region 0
0x01C0 0384
QRAE1
QDMA Region Access Enable Register for Region 1
0x01C0 0388
QRAE2
QDMA Region Access Enable Register for Region 2
0x01C0 038C
QRAE3
QDMA Region Access Enable Register for Region 3
0x01C0 0400 - 0x01C0 043C
Q0E0-Q0E15
Event Queue Entry Registers Q0E0-Q0E15
0x01C0 0440 - 0x01C0 047C
Q1E0-Q1E15
Event Queue Entry Registers Q1E0-Q1E15
0x01C0 0600
QSTAT0
Queue 0 Status Register
0x01C0 0604
QSTAT1
Queue 1 Status Register
0x01C0 0620
QWMTHRA
Queue Watermark Threshold A Register
0x01C0 0640
CCSTAT
ADVANCE INFORMATION
Global Registers
EDMA3CC Status Register
Global Channel Registers
(1)
0x01C0 1000
ER
Event Register
0x01C0 1008
ECR
Event Clear Register
On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC
memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
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Table 6-11. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
Acronym
0x01C0 1010
ESR
Register Description
Event Set Register
0x01C0 1018
CER
Chained Event Register
0x01C0 1020
EER
Event Enable Register
0x01C0 1028
EECR
Event Enable Clear Register
0x01C0 1030
EESR
Event Enable Set Register
0x01C0 1038
SER
Secondary Event Register
0x01C0 1040
SECR
Secondary Event Clear Register
ADVANCE INFORMATION
0x01C0 1050
IER
Interrupt Enable Register
0x01C0 1058
IECR
Interrupt Enable Clear Register
0x01C0 1060
IESR
Interrupt Enable Set Register
0x01C0 1068
IPR
Interrupt Pending Register
0x01C0 1070
ICR
Interrupt Clear Register
0x01C0 1078
IEVAL
Interrupt Evaluate Register
0x01C0 1080
QER
QDMA Event Register
0x01C0 1084
QEER
QDMA Event Enable Register
0x01C0 1088
QEECR
QDMA Event Enable Clear Register
0x01C0 108C
QEESR
QDMA Event Enable Set Register
0x01C0 1090
QSER
QDMA Secondary Event Register
0x01C0 1094
QSECR
QDMA Secondary Event Clear Register
0x01C0 2000
ER
Event Register
0x01C0 2008
ECR
Event Clear Register
Shadow Region 0 Channel Registers
0x01C0 2010
ESR
Event Set Register
0x01C0 2018
CER
Chained Event Register
0x01C0 2020
EER
Event Enable Register
0x01C0 2028
EECR
Event Enable Clear Register
0x01C0 2030
EESR
Event Enable Set Register
0x01C0 2038
SER
Secondary Event Register
0x01C0 2040
SECR
Secondary Event Clear Register
0x01C0 2050
IER
Interrupt Enable Register
0x01C0 2058
IECR
Interrupt Enable Clear Register
0x01C0 2060
IESR
Interrupt Enable Set Register
0x01C0 2068
IPR
Interrupt Pending Register
0x01C0 2070
ICR
Interrupt Clear Register
0x01C0 2078
IEVAL
Interrupt Evaluate Register
0x01C0 2080
QER
QDMA Event Register
0x01C0 2084
QEER
QDMA Event Enable Register
0x01C0 2088
QEECR
QDMA Event Enable Clear Register
0x01C0 208C
QEESR
QDMA Event Enable Set Register
0x01C0 2090
QSER
QDMA Secondary Event Register
0x01C0 2094
QSECR
QDMA Secondary Event Clear Register
Shadow Region 1 Channel Registers
78
0x01C0 2200
ER
Event Register
0x01C0 2208
ECR
Event Clear Register
0x01C0 2210
ESR
Event Set Register
0x01C0 2218
CER
Chained Event Register
0x01C0 2220
EER
Event Enable Register
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BYTE ADDRESS
Acronym
Register Description
0x01C0 2228
EECR
Event Enable Clear Register
0x01C0 2230
EESR
Event Enable Set Register
0x01C0 2238
SER
Secondary Event Register
0x01C0 2240
SECR
Secondary Event Clear Register
0x01C0 2250
IER
Interrupt Enable Register
0x01C0 2258
IECR
Interrupt Enable Clear Register
0x01C0 2260
IESR
Interrupt Enable Set Register
0x01C0 2268
IPR
Interrupt Pending Register
0x01C0 2270
ICR
Interrupt Clear Register
0x01C0 2278
IEVAL
Interrupt Evaluate Register
0x01C0 2280
QER
QDMA Event Register
0x01C0 2284
QEER
QDMA Event Enable Register
0x01C0 2288
QEECR
QDMA Event Enable Clear Register
0x01C0 228C
QEESR
QDMA Event Enable Set Register
0x01C0 2290
QSER
QDMA Secondary Event Register
0x01C0 2294
QSECR
QDMA Secondary Event Clear Register
0x01C0 4000 - 0x01C0 4FFF
—
Parameter RAM (PaRAM)
ADVANCE INFORMATION
Table 6-11. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
Table 6-12. EDMA3 Transfer Controller (EDMA3TC) Registers
Offset
Transfer Controller
0
BYTE ADDRESS
Transfer Controller
1
BYTE ADDRESS
Acronym
Register Description
0h
0x01C0 8000
0x01C0 8400
PID
Peripheral Identification Register
4h
0x01C0 8004
0x01C0 8404
TCCFG
EDMA3TC Configuration Register
100h
0x01C0 8100
0x01C0 8500
TCSTAT
EDMA3TC Channel Status Register
120h
0x01C0 8120
0x01C0 8520
ERRSTAT
Error Status Register
124h
0x01C0 8124
0x01C0 8524
ERREN
Error Enable Register
128h
0x01C0 8128
0x01C0 8528
ERRCLR
Error Clear Register
12Ch
0x01C0 812C
0x01C0 852C
ERRDET
Error Details Register
130h
0x01C0 8130
0x01C0 8530
ERRCMD
Error Interrupt Command Register
140h
0x01C0 8140
0x01C0 8540
RDRATE
Read Command Rate Register
240h
0x01C0 8240
0x01C0 8640
SAOPT
Source Active Options Register
244h
0x01C0 8244
0x01C0 8644
SASRC
Source Active Source Address Register
248h
0x01C0 8248
0x01C0 8648
SACNT
Source Active Count Register
24Ch
0x01C0 824C
0x01C0 864C
SADST
Source Active Destination Address Register
250h
0x01C0 8250
0x01C0 8650
SABIDX
Source Active B-Index Register
254h
0x01C0 8254
0x01C0 8654
SAMPPRXY
Source Active Memory Protection Proxy Register
258h
0x01C0 8258
0x01C0 8658
SACNTRLD
Source Active Count Reload Register
25Ch
0x01C0 825C
0x01C0 865C
SASRCBREF
Source Active Source Address B-Reference Register
260h
0x01C0 8260
0x01C0 8660
SADSTBREF
Source Active Destination Address B-Reference Register
280h
0x01C0 8280
0x01C0 8680
DFCNTRLD
284h
0x01C0 8284
0x01C0 8684
DFSRCBREF
Destination FIFO Set Source Address B-Reference Register
288h
0x01C0 8288
0x01C0 8688
DFDSTBREF
Destination FIFO Set Destination Address B-Reference
Register
300h
0x01C0 8300
0x01C0 8700
DFOPT0
Destination FIFO Options Register 0
304h
0x01C0 8304
0x01C0 8704
DFSRC0
Destination FIFO Source Address Register 0
Destination FIFO Set Count Reload Register
308h
0x01C0 8308
0x01C0 8708
DFCNT0
Destination FIFO Count Register 0
30Ch
0x01C0 830C
0x01C0 870C
DFDST0
Destination FIFO Destination Address Register 0
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Table 6-12. EDMA3 Transfer Controller (EDMA3TC) Registers (continued)
Offset
Transfer Controller
0
BYTE ADDRESS
Transfer Controller
1
BYTE ADDRESS
Acronym
Register Description
310h
0x01C0 8310
314h
0x01C0 8314
0x01C0 8710
DFBIDX0
Destination FIFO B-Index Register 0
0x01C0 8714
DFMPPRXY0
340h
0x01C0 8340
0x01C0 8740
DFOPT1
344h
Destination FIFO Options Register 1
0x01C0 8344
0x01C0 8744
DFSRC1
Destination FIFO Source Address Register 1
Destination FIFO Memory Protection Proxy Register 0
ADVANCE INFORMATION
348h
0x01C0 8348
0x01C0 8748
DFCNT1
Destination FIFO Count Register 1
34Ch
0x01C0 834C
0x01C0 874C
DFDST1
Destination FIFO Destination Address Register 1
350h
0x01C0 8350
0x01C0 8750
DFBIDX1
Destination FIFO B-Index Register 1
354h
0x01C0 8354
0x01C0 8754
DFMPPRXY1
380h
0x01C0 8380
0x01C0 8780
DFOPT2
Destination FIFO Options Register 2
384h
0x01C0 8384
0x01C0 8784
DFSRC2
Destination FIFO Source Address Register 2
Destination FIFO Memory Protection Proxy Register 1
388h
0x01C0 8388
0x01C0 8788
DFCNT2
Destination FIFO Count Register 2
38Ch
0x01C0 838C
0x01C0 878C
DFDST2
Destination FIFO Destination Address Register 2
390h
0x01C0 8390
0x01C0 8790
DFBIDX2
Destination FIFO B-Index Register 2
394h
0x01C0 8394
0x01C0 8794
DFMPPRXY2
3C0h
0x01C0 83C0
0x01C0 87C0
DFOPT3
Destination FIFO Options Register 3
3C4h
0x01C0 83C4
0x01C0 87C4
DFSRC3
Destination FIFO Source Address Register 3
3C8h
0x01C0 83C8
0x01C0 87C8
DFCNT3
Destination FIFO Count Register 3
3CCh
0x01C0 83CC
0x01C0 87CC
DFDST3
Destination FIFO Destination Address Register 3
3D0h
0x01C0 83D0
0x01C0 87D0
DFBIDX3
Destination FIFO B-Index Register 3
3D4h
0x01C0 83D4
0x01C0 87D4
DFMPPRXY3
Destination FIFO Memory Protection Proxy Register 2
Destination FIFO Memory Protection Proxy Register 3
Table 6-13 shows an abbreviation of the set of registers which make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-14 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
Table 6-13. EDMA Parameter Set RAM
HEX ADDRESS RANGE
DESCRIPTION
0x01C0 4000 - 0x01C0 401F
Parameters Set 0 (8 32-bit words)
0x01C0 4020 - 0x01C0 403F
Parameters Set 1 (8 32-bit words)
0x01C0 4040 - 0x01cC0 405F
Parameters Set 2 (8 32-bit words)
0x01C0 4060 - 0x01C0 407F
Parameters Set 3 (8 32-bit words)
0x01C0 4080 - 0x01C0 409F
Parameters Set 4 (8 32-bit words)
0x01C0 40A0 - 0x01C0 40BF
Parameters Set 5 (8 32-bit words)
...
...
0x01C0 4FC0 - 0x01C0 4FDF
Parameters Set 126 (8 32-bit words)
0x01C0 4FE0 - 0x01C0 4FFF
Parameters Set 127 (8 32-bit words)
Table 6-14. Parameter Set Entries
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
80
ACRONYM
PARAMETER ENTRY
0x0000
OPT
Option
0x0004
SRC
Source Address
0x0008
A_B_CNT
A Count, B Count
0x000C
DST
0x0010
SRC_DST_BIDX
Source B Index, Destination B Index
0x0014
LINK_BCNTRLD
Link Address, B Count Reload
Peripheral Information and Electrical Specifications
Destination Address
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Table 6-14. Parameter Set Entries (continued)
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
0x0018
SRC_DST_CIDX
0x001C
CCNT
PARAMETER ENTRY
Source C Index, Destination C Index
C Count
Table 6-15. EDMA Events
Event Name / Source
Event
0
McASP0 Receive
16
MMCSD Receive
1
McASP0 Transmit
17
MMCSD Transmit
2
McASP1 Receive
18
SPI1 Receive
3
McASP1 Transmit
19
SPI1 Transmit
4
McASP2 Receive
20
Reserved
5
McASP2 Transmit
21
Reserved
6
GPIO Bank 0 Interrupt
22
GPIO Bank 2 Interrupt
7
GPIO Bank 1 Interrupt
23
GPIO Bank 3 Interrupt
8
UART0 Receive
24
I2C0 Receive
9
UART0 Transmit
25
I2C0 Transmit
10
Timer64P0 Event Out 12
26
I2C1 Receive
11
Timer64P0 Event Out 34
27
I2C1 Transmit
12
UART1 Receive
28
GPIO Bank 4 Interrupt
13
UART1 Transmit
29
GPIO Bank 5 Interrupt
14
SPI0 Receive
30
UART2 Receive
15
SPI0 Transmit
31
UART2 Transmit
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Event
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6.10 External Memory Interface A (EMIFA)
EMIFA is one of two external memory interfaces supported on the C6745/6747. It is primarily intended to
support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However
on C6745/6747 EMIFA also provides a secondary interface to SDRAM.
6.10.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
• SRAM memories
• NAND Flash memories
• NOR Flash memories
ADVANCE INFORMATION
The EMIFA data bus width is up to 16-bits on the ZKB package and 8 bits on the PTP package. Both
devices support up to fifteen address lines and an external wait/interrupt input. Up to four asynchronous
chip selects are supported by EMIFA (EMA_CS[5:2]) . All four chip selects are available on the ZKB
package. Two of the four are available on the PTP package (EMA_CS[3:2]).
Each chip select has the following individually programmable attributes:
• Data Bus Width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turn around time
• Extended Wait Option With Programmable Timeout
• Select Strobe Option
• NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
6.10.2 EMIFA Synchronous DRAM Memory Support
The C6745/6747 ZKB package supports 16-bit SDRAM in addition to the asynchronous memories listed in
Section 6.10.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are
supported are:
• One, Two, and Four Bank SDRAM devices
• Devices with Eight, Nine, Ten, and Eleven Column Address
• CAS Latency of two or three clock cycles
• Sixteen Bit Data Bus Width
• 3.3V LVCMOS Interface
Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown
Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory
contents; since the SDRAM will continue to refresh itself even without clocks from the DSP. Powerdown
mode achieves even lower power, except the DSP must periodically wake the SDRAM up and issue
refreshes if data retention is required.
Finally, note that the EMIFA does not support Mobile SDRAM devices.
6.10.3 EMIFA Connection Examples
Figure 6-13 illustrates an example of how SDRAM, NOR, and NAND flash devices might be connected to
EMIFA of a C6745/6747 device simultaneously. The SDRAM chip select must be EMA_CS[0]. Note that
the NOR flash is connected to EMA_CS[2] and the NAND flash is connected to EMA_CS[3] in this
example. Note that any type of asynchronous memory may be connected to EMA_CS[5:2].
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EMA_CS[0]
EMA_CAS
EMIFA
EMA_RAS
EMA_WE
EMA_CLK
EMA_SDCKE
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[0]
EMA_WE_DQM[1]
EMA_D[15:0]
EMA_CS[2]
EMA_CS[3]
EMA_WAIT
EMA_OE
RESET
EMA_BA[1]
A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 6-14.
This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the
EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND
area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions
selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to
bootload it. Note that this example could also apply to the C6745 device; except only one multiplane
NAND could be supported with only EMA_CS[3:2] available.
GPIO
(6 Pins)
RESET
...
CE
CAS
RAS
WE
SDRAM
2M x 16 x 4
CLK
Bank
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
A[0]
A[12:1]
DQ[15:0]
NOR
CE
FLASH
WE
512K x 16
OE
RESET
A[18:13]
RY/BY
EMA_A[1]
EMA_A[2]
DVDD
ALE
CLE
DQ[15:0]
NAND
FLASH
CE
1Gb x 16
WE
RE
RB
Figure 6-13. C6745/6747 Connection Diagram: SDRAM, NOR, NAND
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ADVANCE INFORMATION
The on-chip bootloader makes some assumptions on which chip select the contains the boot image, and
this depends on the boot mode. For NOR boot mode; the on-chip bootloader requires that the image be
stored in NOR flash on EMA_CS[2]. For NAND boot mode, the bootloader requires that the boot image is
stored in NAND flash on EMA_CS[3]. It is always possible to have the image span multiple chip selects,
but this must be supported by second stage boot code stored in the external flash.
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EMA_A[1]
EMA_A[2]
EMA_D[7:0]
EMA_CS[2]
EMA_CS[3]
EMA_WE
EMA_OE
EMIFA
EMA_WAIT
ADVANCE INFORMATION
ALE
CLE
DQ[7:0]
CE1
CE2
WE
RE
R/B1
R/B2
NAND
FLASH
x8,
MultiPlane
ALE
CLE
DQ[7:0]
CE1
CE2
WE
RE
R/B1
R/B2
NAND
FLASH
x8,
MultiPlane
DVDD
EMA_CS[4]
EMA_CS[5]
Figure 6-14. C6745/6747 EMIFA Connection Diagram: Multiple NAND Flash Planes
6.10.4 External Memory Interface (EMIF)
Table 6-16 is a list of the EMIF registers. For more information about these registers, see the C674x DSP
External Memory Interface (EMIF) User's Guide (literature number SPRU711).
Table 6-16. External Memory Interface (EMIFA) Registers
BYTE ADDRESS
84
Register Name
Register Description
0x6800 0000
MIDR
Module ID Register
0x6800 0004
AWCC
Asynchronous Wait Cycle Configuration Register
0x6800 0008
SDCR
SDRAM Configuration Register
0x6800 000C
SDRCR
SDRAM Refresh Control Register
0x6800 0010
CE2CFG
Asynchronous 1 Configuration Register
0x6800 0014
CE3CFG
Asynchronous 2 Configuration Register
0x6800 0018
CE4CFG
Asynchronous 3 Configuration Register
0x6800 001C
CE5CFG
Asynchronous 4 Configuration Register
0x6800 0020
SDTIMR
SDRAM Timing Register
0x6800 003C
SDSRETR
SDRAM Self Refresh Exit Timing Register
0x6800 0040
INTRAW
EMIFA Interrupt Raw Register
0x6800 0044
INTMSK
EMIFA Interrupt Mask Register
0x6800 0048
INTMSKSET
EMIFA Interrupt Mask Set Register
0x6800 004C
INTMSKCLR
EMIFA Interrupt Mask Clear Register
0x6800 0060
NANDFCR
NAND Flash Control Register
0x6800 0064
NANDFSR
NAND Flash Status Register
0x6800 0070
NANDF1ECC
NAND Flash 1 ECC Register (CS2 Space)
0x6800 0074
NANDF2ECC
NAND Flash 2 ECC Register (CS3 Space)
0x6800 0078
NANDF3ECC
NAND Flash 3 ECC Register (CS4 Space)
0x6800 007C
NANDF4ECC
NAND Flash 4 ECC Register (CS5 Space)
0x6800 00BC
NAND4BITECCLOAD
NAND Flash 4-Bit ECC Load Register
0x6800 00C0
NAND4BITECC1
NAND Flash 4-Bit ECC Register 1
0x6800 00C4
NAND4BITECC2
NAND Flash 4-Bit ECC Register 2
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Table 6-16. External Memory Interface (EMIFA) Registers (continued)
Register Name
Register Description
0x6800 00C8
NAND4BITECC3
NAND Flash 4-Bit ECC Register 3
0x6800 00CC
NAND4BITECC4
NAND Flash 4-Bit ECC Register 4
0x6800 00D0
NANDERRADD1
NAND Flash 4-Bit ECC Error Address Register 1
0x6800 00D4
NANDERRADD2
NAND Flash 4-Bit ECC Error Address Register 2
0x6800 00D8
NANDERRVAL1
NAND Flash 4-Bit ECC Error Value Register 1
0x6800 00DC
NANDERRVAL2
NAND Flash 4-Bit ECC Error Value Register 2
ADVANCE INFORMATION
BYTE ADDRESS
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6.10.5 EMIFA Electrical Data/Timing
Table 6-17 through Table 6-20 assume testing over recommended operating conditions.
Table 6-17. EMIFA SDRAM Interface Timing Requirements
NO.
MIN
19
tsu(EMA_DV-EM_CLKH)
Input setup time, read data valid on EMA_D[31:0] before EMA_CLK
rising
20
th(CLKH-DIV)
Input hold time, read data valid on EMA_D[31:0] after EMA_CLK
rising
MAX UNIT
1
ns
1.5
ns
Table 6-18. EMIFA SDRAM Interface Switching Characteristics
ADVANCE INFORMATION
NO.
PARAMETER
MIN
1
tc(CLK)
Cycle time, EMIF clock EMA_CLK
2
tw(CLK)
Pulse width, EMIF clock EMA_CLK high or low
3
td(CLKH-CSV)
Delay time, EMA_CLK rising to EMA_CS[0] valid
4
toh(CLKH-CSIV)
Output hold time, EMA_CLK rising to EMA_CS[0] invalid
5
td(CLKH-DQMV)
Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid
6
toh(CLKH-DQMIV)
Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid
7
td(CLKH-AV)
Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0]
valid
8
toh(CLKH-AIV)
Output hold time, EMA_CLK rising to EMA_A[12:0] and
EMA_BA[1:0] invalid
9
td(CLKH-DV)
Delay time, EMA_CLK rising to EMA_D[15:0] valid
10
toh(CLKH-DIV)
Output hold time, EMA_CLK rising to EMA_D[15:0] invalid
11
td(CLKH-RASV)
Delay time, EMA_CLK rising to EMA_RAS valid
12
toh(CLKH-RASIV)
Output hold time, EMA_CLK rising to EMA_RAS invalid
13
td(CLKH-CASV)
Delay time, EMA_CLK rising to EMA_CAS valid
14
toh(CLKH-CASIV)
Output hold time, EMA_CLK rising to EMA_CAS invalid
15
td(CLKH-WEV)
Delay time, EMA_CLK rising to EMA_WE valid
16
toh(CLKH-WEIV)
Output hold time, EMA_CLK rising to EMA_WE invalid
17
tdis(CLKH-DHZ)
Delay time, EMA_CLK rising to EMA_D[15:0] tri-stated
18
tena(CLKH-DLZ)
Output hold time, EMA_CLK rising to EMA_D[15:0] driving
MAX UNIT
10
ns
3
ns
7
1
ns
ns
7
1
ns
ns
7
1
ns
ns
7
1
ns
ns
7
1
ns
ns
7
1
ns
ns
7
1
ns
ns
7
1
ns
ns
Table 6-19. EMIFA Asynchronous Memory Timing Requirements (1)
C6745/6747
NO
.
MIN
Nom
MAX
UNIT
READS and WRITES
2
tw(EM_WAIT)
Pulse duration, EM_WAIT assertion and
deassertion
2E
ns
READS
12
tsu(EMDV-EMOEH)
Setup time, EM_D[15:0] valid before EM_OE high
3
ns
13
th(EMOEH-EMDIV)
Hold time, EM_D[15:0] valid after EM_OE high
0.5
ns
14
tsu(EMOEL-
Setup Time, EM_WAIT asserted before end of
Strobe Phase (2)
4E+3
ns
EMWAIT)
WRITES
(1)
(2)
86
E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-19 and Figure 6-20 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Table 6-19. EMIFA Asynchronous Memory Timing Requirements (continued)
C6745/6747
NO
.
28
MIN
tsu(EMWEL-
Setup Time, EM_WAIT asserted before end of
Strobe Phase (2)
EMWAIT)
Nom
UNIT
MAX
4E+3
ns
Table 6-20. EMIFA Asynchronous Memory Switching Characteristics (1) (2) (3)
NO
.
C6745/6747
PARAMETER
UNIT
MIN
Nom
MAX
(TA)*E - 3
(TA)*E
(TA)*E + 3
ns
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E
-3
(RS+RST+RH)*E
(RS+RST+RH)*E
+3
ns
EMIF read cycle time (EW = 1)
(RS+RST+RH+(E
WC*16))*E - 3
(RS+RST+RH+(EW (RS+RST+RH+(E
C*16))*E
WC*16))*E + 3
ns
td(TURNAROUND)
Turn around time
ADVANCE INFORMATION
READS and WRITES
1
READS
3
4
5
tc(EMRCYCLE)
tsu(EMCEL-EMOEL)
th(EMOEH-EMCEH)
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 0)
(RS)*E-3
(RS)*E
(RS)*E+3
ns
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 1)
-3
0
+3
ns
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 0)
(RH)*E - 3
(RH)*E
(RH)*E + 3
ns
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 1)
-3
0
+3
ns
6
tsu(EMBAV-EMOEL)
Output setup time, EMA_BA[1:0] valid to
EMA_OE low
(RS)*E-3
(RS)*E
(RS)*E+3
ns
7
th(EMOEH-EMBAIV)
Output hold time, EMA_OE high to
EMA_BA[1:0] invalid
(RH)*E-3
(RH)*E
(RH)*E+3
ns
8
tsu(EMBAV-EMOEL)
Output setup time, EMA_A[13:0] valid to
EMA_OE low
(RS)*E-3
(RS)*E
(RS)*E+3
ns
9
th(EMOEH-EMAIV)
Output hold time, EMA_OE high to
EMA_A[13:0] invalid
(RH)*E-3
(RH)*E
(RH)*E+3
ns
EMA_OE active low width (EW = 0)
(RST)*E-3
(RST)*E
(RST)*E+3
ns
10
tw(EMOEL)
EMA_OE active low width (EW = 1)
(RST+(EWC*16))
*E-3
(RST+(EWC*16))*E
(RST+(EWC*16))
*E+3
ns
11
td(EMWAITH-
3E-3
4E
4E+3
ns
EMIF write cycle time (EW = 0)
(WS+WST+WH)*
E-3
(WS+WST+WH)*E
(WS+WST+WH)*
E+3
ns
EMIF write cycle time (EW = 1)
(WS+WST+WH+(
EWC*16))*E - 3
(WS+WST+WH+(E (WS+WST+WH+(
WC*16))*E
EWC*16))*E + 3
ns
EMOEH)
Delay time from EMA_WAIT deasserted to
EMA_OE high
WRITES
15
16
(1)
(2)
(3)
tc(EMWCYCLE)
tsu(EMCEL-EMWEL)
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 0)
(WS)*E - 3
(WS)*E
(WS)*E + 3
ns
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 1)
-3
0
+3
ns
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256]. See the C6745/6747 Asynchronous External Memory Interface (EMIF) User's Guide (SPRUED1) for more
information.
E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
C6745/6747 Asynchronous External Memory Interface (EMIF) User's Guide (SPRUED1) for more information.
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Table 6-20. EMIFA Asynchronous Memory Switching Characteristics (continued)
NO
.
17
18
th(EMWEH-EMCEH)
tsu(EMDQMVEMWEL)
19
C6745/6747
PARAMETER
th(EMWEHEMDQMIV)
UNIT
MIN
Nom
MAX
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 0)
(WH)*E-3
(WH)*E
(WH)*E+3
ns
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 1)
-3
0
+3
ns
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
(WS)*E-3
(WS)*E
(WS)*E+3
ns
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
ADVANCE INFORMATION
20
tsu(EMBAV-EMWEL)
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
(WS)*E-3
(WS)*E
(WS)*E+3
ns
21
th(EMWEH-EMBAIV)
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
22
tsu(EMAV-EMWEL)
Output setup time, EMA_A[13:0] valid to
EMA_WE low
(WS)*E-3
(WS)*E
(WS)*E+3
ns
23
th(EMWEH-EMAIV)
Output hold time, EMA_WE high to
EMA_A[13:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
EMA_WE active low width (EW = 0)
(WST)*E-3
(WST)*E
(WST)*E+3
ns
24
tw(EMWEL)
EMA_WE active low width (EW = 1)
(WST+(EWC*16))
*E-3
(WST+(EWC*16))
(WST+(EWC*16))*E
*E+3
ns
25
td(EMWAITHEMWEH)
Delay time from EMA_WAIT deasserted to
EMA_WE high
3E-3
4E
4E+3
ns
26
tsu(EMDV-EMWEL)
Output setup time, EMA_D[15:0] valid to
EMA_WE low
(WS)*E-3
(WS)*E
(WS)*E+3
ns
27
th(EMWEH-EMDIV)
Output hold time, EMA_WE high to
EMA_D[15:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
BASIC SDRAM
WRITE OPERATION
1
2
2
EMA_CLK
3
4
EMA_CS[0]
5
6
EMA_WE_DQM[1:0]
7
8
7
8
EMA_BA[1:0]
EMA_A[12:0]
9
10
EMA_D[15:0]
11
12
EMA_RAS
13
EMA_CAS
15
16
EMA_WE
Figure 6-15. EMIFA Basic SDRAM Write Operation
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BASIC SDRAM
READ OPERATION
1
2
2
EMA_CLK
3
4
EMA_CS[0]
5
6
EMA_WE_DQM[1:0]
7
8
7
8
ADVANCE INFORMATION
EMA_BA[1:0]
EMA_A[12:0]
19
17
2 EM_CLK Delay
20
18
EMA_D[15:0]
11
12
EMA_RAS
13
14
EMA_CAS
EMA_WE
Figure 6-16. EMIFA Basic SDRAM Read Operation
3
1
EMA_CE[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
4
8
5
9
6
29
7
30
10
EMA_OE
13
12
EMA_D[15:0]
EMA_WE
Figure 6-17. Asynchronous Memory Read Timing for EMIFA
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15
1
EMA_CE[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
ADVANCE INFORMATION
16
17
18
19
20
21
24
22
23
EMA_WE
27
26
EMA_D[15:0]
EMA_OE
Figure 6-18. Asynchronous Memory Write Timing for EMIFA
EMA_CE[5:2]
SETUP
STROBE
Extended Due to EMA_WAIT
STROBE HOLD
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
14
11
EMA_OE
2
EMA_WAIT
Asserted
2
Deasserted
Figure 6-19. EMA_WAIT Read Timing Requirements
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EMA_CE[5:2]
SETUP
STROBE
Extended Due to EMA_WAIT
STROBE HOLD
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
28
25
2
EMA_WAIT
Asserted
ADVANCE INFORMATION
EMA_WE
2
Deasserted
Figure 6-20. EMA_WAIT Write Timing Requirements
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6.11 External Memory Interface B (EMIFB)
Figure 6-21, EMIFB Functional Block Diagram illustrates a high-level view of the EMIFB and its
connections within the device. Multiple requesters have access to EMIFB through a switched central
resource (indicated as crossbar in the figure). The EMIFB implements a split transaction internal bus,
allowing concurrence between reads and writes from the various requesters.
EMIFB
Registers
CPU
ADVANCE INFORMATION
EDMA
Crossbar
Master
Peripherals
(USB, UHPI...)
EMB_CS
EMB_CAS
Cmd/Write
EMB_RAS
FIFO
EMB_WE
EMB_CLK
EMB_SDCKE
Read
EMB_BA[1:0]
FIFO
EMB_A[x:0]
EMB_D[x:0]
EMB_WE_DQM[x:0]
SDRAM
Interface
Figure 6-21. EMIFB Functional Block Diagram
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6.11.1 Interfacing to SDRAM
Figure 6-22 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. In addition,
Figure 6-23 shows an interface between the EMIFB and a 2M × 32 × 4 bank SDRAM device and
Figure 6-24 shows an interface between the EMIFB and two 4M × 16 × 4 bank SDRAM devices. Refer to
Table 6-21, as an example that shows additional list of commonly-supported SDRAM devices and the
required connections for the address pins. Note that in Table 6-21, page size/column size (not indicated in
the table) is varied to get the required addressability range.
EMIFB
EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
SDRAM
2M x 16 x 4
Bank
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
Figure 6-22. EMIFB to 2M × 16 × 4 bank SDRAM Interface
EMIFB
EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[3:0]
EMB_D[31:0]
SDRAM
2M x 32 x 4
Bank
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[11:0]
DQM[3:0]
DQ[31:0]
Figure 6-23. EMIFB to 2M × 32 × 4 bank SDRAM Interface
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ADVANCE INFORMATION
The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:
• Pre-charge bit is A[10]
• The number of column address bits is 8, 9, 10 or 11
• The number of row address bits is 13 (in case of mobile SDR, number of row address bits can be 9,
10, 11, 12, or 13)
• The number of internal banks is 1, 2 or 4
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SDRAM
4M x 16 x 4
Bank
EMIFB
ADVANCE INFORMATION
EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[12:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
EMB_WE_DQM[2]
EMB_WE_DQM[3]
EMB_D[31:16]
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
SDRAM
4M x 16 x 4
Bank
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
Figure 6-24. EMIFB to Dual 4M × 16 × 4 bank SDRAM Interface
Table 6-21. Example of 16/32-bit EMIFB Address Pin Connections
SDRAM Size
Width
Banks
64M bits
×16
4
×32
128M bits
256M bits
×16
4
SDRAM
A[11:0]
EMIFB
EMB_A[11:0]
SDRAM
A[10:0]
EMIFB
EMB_A[10:0]
SDRAM
A[11:0]
EMIFB
EMB_A[11:0]
×32
4
SDRAM
A[11:0]
EMIFB
EMB_A[11:0]
×16
4
SDRAM
A[12:0]
EMIFB
EMB_A[12:0]
×32
512M bits
4
Address Pins
×16
×32
4
4
4
SDRAM
A[11:0]
EMIFB
EMB_A[11:0]
SDRAM
A[12:0]
EMIFB
EMB_A[12:0]
SDRAM
A[12:0]
EMIFB
EMB_A[12:0]
Table 6-22 is a list of the EMIFB registers.
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BYTE ADDRESS
Acronym
Register
0xB000 0000
MIDR
Module ID Register
0xB000 0008
SDCFG
SDRAM Configuration Register
0xB000 000C
SDRFC
SDRAM Refresh Control Register
0xB000 0010
SDTIM1
SDRAM Timing Register 1
0xB000 0014
SDTIM2
SDRAM Timing Register 2
0xB000 001C
SDCFG2
SDRAM Configuration 2 Register
0xB000 0020
BPRIO
Peripheral Bus Burst Priority Register
0xB000 0040
PC1
Performance Counter 1 Register
0xB000 0044
PC2
Performance Counter 2 Register
0xB000 0048
PCC
Performance Counter Configuration Register
0xB000 004C
PCMRS
Performance Counter Master Region Select Register
0xB000 0050
PCT
Performance Counter Time Register
0xB000 00C0
IRR
Interrupt Raw Register
0xB000 00C4
IMR
Interrupt Mask Register
0xB000 00C8
IMSR
Interrupt Mask Set Register
0xB000 00CC
IMCR
Interrupt Mask Clear Register
6.11.2 EMIFB Electrical Data/Timing
Table 6-23. EMIFB SDRAM Interface Timing Requirements
NO.
MIN
19
tsu(EMA_DV-EM_CLKH)
Input setup time, read data valid on EMB_D[31:0] before EMB_CLK
rising
20
th(CLKH-DIV)
Input hold time, read data valid on EMB_D[31:0] after EMB_CLK
rising
MAX UNIT
0.5
ns
1.5
ns
Table 6-24. EMIFB SDRAM Interface Switching Characteristics
NO.
PARAMETER
MIN
1
tc(CLK)
Cycle time, EMIF clock EMB_CLK
2
tw(CLK)
Pulse width, EMIF clock EMB_CLK high or low
3
td(CLKH-CSV)
Delay time, EMB_CLK rising to EMB_CS[0] valid
4
toh(CLKH-CSIV)
Output hold time, EMB_CLK rising to EMB_CS[0] invalid
5
td(CLKH-DQMV)
Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid
6
toh(CLKH-DQMIV)
Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0] invalid
7
td(CLKH-AV)
Delay time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0]
valid
8
toh(CLKH-AIV)
Output hold time, EMB_CLK rising to EMB_A[12:0] and
EMB_BA[1:0] invalid
7.5
9
td(CLKH-DV)
Delay time, EMB_CLK rising to EMB_D[31:0] valid
10
toh(CLKH-DIV)
Output hold time, EMB_CLK rising to EMB_D[31:0] invalid
11
td(CLKH-RASV)
Delay time, EMB_CLK rising to EMB_RAS valid
12
toh(CLKH-RASIV)
Output hold time, EMB_CLK rising to EMB_RAS invalid
13
td(CLKH-CASV)
Delay time, EMB_CLK rising to EMB_CAS valid
14
toh(CLKH-CASIV)
Output hold time, EMB_CLK rising to EMB_CAS invalid
15
td(CLKH-WEV)
Delay time, EMB_CLK rising to EMB_WE valid
16
toh(CLKH-WEIV)
Output hold time, EMB_CLK rising to EMB_WE invalid
17
tdis(CLKH-DHZ)
Delay time, EMB_CLK rising to EMB_D[31:0] tri-stated
18
tena(CLKH-DLZ)
Output hold time, EMB_CLK rising to EMB_D[31:0] driving
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MAX UNIT
ns
3
ns
5.1
0.9
ns
ns
5.1
0.9
ns
ns
5.1
0.9
ns
ns
5.1
0.9
ns
ns
5.1
0.9
ns
ns
5.1
0.9
ns
ns
5.1
0.9
ns
ns
5.1
0.9
Peripheral Information and Electrical Specifications
ns
ns
95
ADVANCE INFORMATION
Table 6-22. EMIFB Base Controller Registers
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMB_CLK
3
4
EMB_CS[0]
5
6
EMB_WE_DQM[3:0]
7
8
7
8
EMB_BA[1:0]
ADVANCE INFORMATION
EMB_A[12:0]
9
10
EMB_D[31:0]
11
12
EMB_RAS
13
EMB_CAS
15
16
EMB_WE
Figure 6-25. EMIFB Basic SDRAM Write Operation
BASIC SDRAM
READ OPERATION
1
2
2
EMB_CLK
3
4
EMB_CS[0]
5
6
EMB_WE_DQM[3:0]
7
8
7
8
EMB_BA[1:0]
EMB_A[12:0]
19
17
20
2 EM_CLK Delay
18
EMB_D[31:0]
11
12
EMB_RAS
13
14
EMB_CAS
EMB_WE
Figure 6-26. EMIFB Basic SDRAM Read Operation
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6.12 MMC / SD / SDIO (MMCSD)
6.12.1 MMCSD Peripheral Description
The C6745/6747 includes an MMCSD controller which is compliant with MMC V3.31, Secure Digital Part 1
Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.
ADVANCE INFORMATION
The MMC/SD Controller has following features:
• MultiMediaCard (MMC).
• Secure Digital (SD) Memory Card.
• MMC/SD protocol support.
• SDIO protocol support.
• Programmable clock frequency.
• 512 bit Read/Write FIFO to lower system overhead.
• Slave EDMA transfer capability.
The C6745/6747 MMC/SD Controller does not support SPI mode.
6.12.2
MMCSD Peripheral Register Description(s)
Table 6-25. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
Offset
Acronym
Register Description
0x01C4 0000
MMCCTL
MMC Control Register
0x01C4 0004
MMCCLK
MMC Memory Clock Control Register
MMC Status Register 0
0x01C4 0008
MMCST0
0x01C4 000C
MMCST1
MMC Status Register 1
0x01C4 0010
MMCIM
MMC Interrupt Mask Register
0x01C4 0014
MMCTOR
MMC Response Time-Out Register
0x01C4 0018
MMCTOD
MMC Data Read Time-Out Register
0x01C4 001C
MMCBLEN
MMC Block Length Register
0x01C4 0020
MMCNBLK
MMC Number of Blocks Register
0x01C4 0024
MMCNBLC
MMC Number of Blocks Counter Register
0x01C4 0028
MMCDRR
MMC Data Receive Register
0x01C4 002C
MMCDXR
MMC Data Transmit Register
0x01C4 0030
MMCCMD
MMC Command Register
0x01C4 0034
MMCARGHL
MMC Argument Register
0x01C4 0038
MMCRSP01
MMC Response Register 0 and 1
0x01C4 003C
MMCRSP23
MMC Response Register 2 and 3
0x01C4 0040
MMCRSP45
MMC Response Register 4 and 5
0x01C4 0044
MMCRSP67
MMC Response Register 6 and 7
0x01C4 0048
MMCDRSP
MMC Data Response Register
0x01C4 0050
MMCCIDX
MMC Command Index Register
0x01C4 0064
SDIOCTL
SDIO Control Register
0x01C4 0068
SDIOST0
SDIO Status Register 0
0x01C4 006C
SDIOIEN
SDIO Interrupt Enable Register
0x01C4 0070
SDIOIST
SDIO Interrupt Status Register
0x01C4 0074
MMCFIFOCTL
MMC FIFO Control Register
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6.12.3 MMC/SD Electrical Data/Timing
Table 6-26. Timing Requirements for MMC/SD Module
(see Figure 6-28 and Figure 6-30)
NO.
MIN
MAX
UNIT
1
tsu(CMDV-CLKH)
Setup time, MMCSD_CMD valid before MMCSD_CLK high
3.2
ns
2
th(CLKH-CMDV)
Hold time, MMCSD_CMD valid after MMCSD_CLK high
1.5
ns
3
tsu(DATV-CLKH)
Setup time, MMCSD_DATx valid before MMCSD_CLK high
3.2
ns
4
th(CLKH-DATV)
Hold time, MMCSD_DATx valid after MMCSD_CLK high
1.5
ns
ADVANCE INFORMATION
Table 6-27. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 6-27 through Figure 6-30)
NO.
PARAMETER
MIN
MAX
UNIT
7
f(CLK)
Operating frequency, MMCSD_CLK
0
52
MHz
8
f(CLK_ID)
Identification mode frequency, MMCSD_CLK
0
400
KHz
9
tW(CLKL)
Pulse width, MMCSD_CLK low
6.5
10
tW(CLKH)
Pulse width, MMCSD_CLK high
6.5
ns
11
tr(CLK)
Rise time, MMCSD_CLK
3
ns
12
tf(CLK)
Fall time, MMCSD_CLK
3
ns
13
td(CLKL-CMD)
Delay time, MMCSD_CLK low to MMCSD_CMD transition
-4.5
2
ns
14
td(CLKL-DAT)
Delay time, MMCSD_CLK low to MMCSD_DATx transition
-4.5
2
ns
ns
10
9
7
MMCSD_CLK
13
13
START
MMCSD_CMD
13
XMIT
Valid
Valid
13
Valid
END
Figure 6-27. MMC/SD Host Command Timing
9
7
10
MMCSD_CLK
1
2
START
MMCSD_CMD
XMIT
Valid
Valid
Valid
END
Figure 6-28. MMC/SD Card Response Timing
10
9
7
MMCSD_CLK
14
MMCSD_DATx
14
START
14
D0
D1
Dx
14
END
Figure 6-29. MMC/SD Host Write Timing
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9
10
7
MMCSD_CLK
4
4
3
Start
MMCSD_DATx
3
D0
D1
Dx
End
ADVANCE INFORMATION
Figure 6-30. MMC/SD Host Read and Card CRC Status Timing
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6.13 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between C6745/6747 and
the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100
Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The EMAC controls the flow of packet data from the C6745/6747 device to the PHY. The MDIO module
controls PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the C6745/6747 device through a custom interface
that allows efficient data transmission and reception. This custom interface is referred to as the EMAC
control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used
to multiplex and control interrupts.
ADVANCE INFORMATION
6.13.1
EMAC Peripheral Register Description(s)
Table 6-28. Ethernet Media Access Controller (EMAC) Registers
Offset
BYTE ADDRESS
REGISTER
Register Description
0h
0x01E2 3000
TXREV
Transmit Revision Register
4h
0x01E2 3004
TXCONTROL
Transmit Control Register
8h
0x01E2 3008
TXTEARDOWN
Transmit Teardown Register
10h
0x01E2 3010
RXREV
Receive Revision Register
14h
0x01E2 3014
RXCONTROL
Receive Control Register
18h
0x01E2 3018
RXTEARDOWN
Receive Teardown Register
80h
0x01E2 3080
TXINTSTATRAW
Transmit Interrupt Status (Unmasked) Register
84h
0x01E2 3084
TXINTSTATMASKED
Transmit Interrupt Status (Masked) Register
88h
0x01E2 3088
TXINTMASKSET
Transmit Interrupt Mask Set Register
8Ch
0x01E2 308C
TXINTMASKCLEAR
Transmit Interrupt Clear Register
90h
0x01E2 3090
MACINVECTOR
MAC Input Vector Register
94h
0x01E2 3094
MACEOIVECTOR
MAC End Of Interrupt Vector Register
A0h
0x01E2 30A0
RXINTSTATRAW
Receive Interrupt Status (Unmasked) Register
A4h
0x01E2 30A4
RXINTSTATMASKED
Receive Interrupt Status (Masked) Register
A8h
0x01E2 30A8
RXINTMASKSET
Receive Interrupt Mask Set Register
ACh
0x01E2 30AC
RXINTMASKCLEAR
Receive Interrupt Mask Clear Register
B0h
0x01E2 30B0
MACINTSTATRAW
MAC Interrupt Status (Unmasked) Register
B4h
0x01E2 30B4
MACINTSTATMASKED
MAC Interrupt Status (Masked) Register
B8h
0x01E2 30B8
MACINTMASKSET
MAC Interrupt Mask Set Register
BCh
0x01E2 30BC
MACINTMASKCLEAR
MAC Interrupt Mask Clear Register
100h
0x01E2 3100
RXMBPENABLE
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
104h
0x01E2 3104
RXUNICASTSET
Receive Unicast Enable Set Register
108h
0x01E2 3108
RXUNICASTCLEAR
Receive Unicast Clear Register
10Ch
0x01E2 310C
RXMAXLEN
Receive Maximum Length Register
110h
0x01E2 3110
RXBUFFEROFFSET
Receive Buffer Offset Register
114h
0x01E2 3114
RXFILTERLOWTHRESH
Receive Filter Low Priority Frame Threshold Register
120h
0x01E2 3120
RX0FLOWTHRESH
Receive Channel 0 Flow Control Threshold Register
124h
0x01E2 3124
RX1FLOWTHRESH
Receive Channel 1 Flow Control Threshold Register
128h
0x01E2 3128
RX2FLOWTHRESH
Receive Channel 2 Flow Control Threshold Register
12Ch
0x01E2 312C
RX3FLOWTHRESH
Receive Channel 3 Flow Control Threshold Register
130h
0x01E2 3130
RX4FLOWTHRESH
Receive Channel 4 Flow Control Threshold Register
134h
0x01E2 3134
RX5FLOWTHRESH
Receive Channel 5 Flow Control Threshold Register
138h
0x01E2 3138
RX6FLOWTHRESH
Receive Channel 6 Flow Control Threshold Register
13Ch
0x01E2 313C
RX7FLOWTHRESH
Receive Channel 7 Flow Control Threshold Register
100
Peripheral Information and Electrical Specifications
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Offset
BYTE ADDRESS
REGISTER
Register Description
140h
0x01E2 3140
RX0FREEBUFFER
Receive Channel 0 Free Buffer Count Register
144h
0x01E2 3144
RX1FREEBUFFER
Receive Channel 1 Free Buffer Count Register
148h
0x01E2 3148
RX2FREEBUFFER
Receive Channel 2 Free Buffer Count Register
14Ch
0x01E2 314C
RX3FREEBUFFER
Receive Channel 3 Free Buffer Count Register
150h
0x01E2 3150
RX4FREEBUFFER
Receive Channel 4 Free Buffer Count Register
154h
0x01E2 3154
RX5FREEBUFFER
Receive Channel 5 Free Buffer Count Register
158h
0x01E2 3158
RX6FREEBUFFER
Receive Channel 6 Free Buffer Count Register
15Ch
0x01E2 315C
RX7FREEBUFFER
Receive Channel 7 Free Buffer Count Register
160h
0x01E2 3160
MACCONTROL
MAC Control Register
164h
0x01E2 3164
MACSTATUS
MAC Status Register
168h
0x01E2 3168
EMCONTROL
Emulation Control Register
16Ch
0x01E2 316C
FIFOCONTROL
FIFO Control Register
170h
0x01E2 3170
MACCONFIG
MAC Configuration Register
174h
0x01E2 3174
SOFTRESET
Soft Reset Register
1D0h
0x01E2 31D0
MACSRCADDRLO
MAC Source Address Low Bytes Register
1D4h
0x01E2 31D4
MACSRCADDRHI
MAC Source Address High Bytes Register
1D8h
0x01E2 31D8
MACHASH1
MAC Hash Address Register 1
1DCh
0x01E2 31DC
MACHASH2
MAC Hash Address Register 2
1E0h
0x01E2 31E0
BOFFTEST
Back Off Test Register
1E4h
0x01E2 31E4
TPACETEST
Transmit Pacing Algorithm Test Register
1E8h
0x01E2 31E8
RXPAUSE
Receive Pause Timer Register
1ECh
0x01E2 31EC
TXPAUSE
Transmit Pause Timer Register
0x01E2 3200 - 0x01E2
32FC
(see Table 6-29)
0x01E2 3500
MACADDRLO
MAC Address Low Bytes Register, Used in Receive Address Matching
MACADDRHI
MAC Address High Bytes Register, Used in Receive Address
Matching
500h
504h
0x01E2 3504
EMAC Statistics Registers
508h
0x01E2 3508
MACINDEX
MAC Index Register
600h
0x01E2 3600
TX0HDP
Transmit Channel 0 DMA Head Descriptor Pointer Register
604h
0x01E2 3604
TX1HDP
Transmit Channel 1 DMA Head Descriptor Pointer Register
608h
0x01E2 3608
TX2HDP
Transmit Channel 2 DMA Head Descriptor Pointer Register
60Ch
0x01E2 360C
TX3HDP
Transmit Channel 3 DMA Head Descriptor Pointer Register
610h
0x01E2 3610
TX4HDP
Transmit Channel 4 DMA Head Descriptor Pointer Register
614h
0x01E2 3614
TX5HDP
Transmit Channel 5 DMA Head Descriptor Pointer Register
618h
0x01E2 3618
TX6HDP
Transmit Channel 6 DMA Head Descriptor Pointer Register
61Ch
0x01E2 361C
TX7HDP
Transmit Channel 7 DMA Head Descriptor Pointer Register
620h
0x01E2 3620
RX0HDP
Receive Channel 0 DMA Head Descriptor Pointer Register
624h
0x01E2 3624
RX1HDP
Receive Channel 1 DMA Head Descriptor Pointer Register
628h
0x01E2 3628
RX2HDP
Receive Channel 2 DMA Head Descriptor Pointer Register
62Ch
0x01E2 362C
RX3HDP
Receive Channel 3 DMA Head Descriptor Pointer Register
630h
0x01E2 3630
RX4HDP
Receive Channel 4 DMA Head Descriptor Pointer Register
634h
0x01E2 3634
RX5HDP
Receive Channel 5 DMA Head Descriptor Pointer Register
638h
0x01E2 3638
RX6HDP
Receive Channel 6 DMA Head Descriptor Pointer Register
63Ch
0x01E2 363C
RX7HDP
Receive Channel 7 DMA Head Descriptor Pointer Register
640h
0x01E2 3640
TX0CP
Transmit Channel 0 Completion Pointer Register
644h
0x01E2 3644
TX1CP
Transmit Channel 1 Completion Pointer Register
648h
0x01E2 3648
TX2CP
Transmit Channel 2 Completion Pointer Register
64Ch
0x01E2 364C
TX3CP
Transmit Channel 3 Completion Pointer Register
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ADVANCE INFORMATION
Table 6-28. Ethernet Media Access Controller (EMAC) Registers (continued)
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
www.ti.com
Table 6-28. Ethernet Media Access Controller (EMAC) Registers (continued)
Offset
BYTE ADDRESS
REGISTER
Register Description
650h
0x01E2 3650
TX4CP
Transmit Channel 4 Completion Pointer Register
654h
0x01E2 3654
TX5CP
Transmit Channel 5 Completion Pointer Register
ADVANCE INFORMATION
658h
0x01E2 3658
TX6CP
Transmit Channel 6 Completion Pointer Register
65Ch
0x01E2 365C
TX7CP
Transmit Channel 7 Completion Pointer Register
660h
0x01E2 3660
RX0CP
Receive Channel 0 Completion Pointer Register
664h
0x01E2 3664
RX1CP
Receive Channel 1 Completion Pointer Register
668h
0x01E2 3668
RX2CP
Receive Channel 2 Completion Pointer Register
66Ch
0x01E2 366C
RX3CP
Receive Channel 3 Completion Pointer Register
670h
0x01E2 3670
RX4CP
Receive Channel 4 Completion Pointer Register
674h
0x01E2 3674
RX5CP
Receive Channel 5 Completion Pointer Register
678h
0x01E2 3678
RX6CP
Receive Channel 6 Completion Pointer Register
67Ch
0x01E2 367C
RX7CP
Receive Channel 7 Completion Pointer Register
Table 6-29. EMAC Statistics Registers
102
HEX ADDRESS RANGE
ACRONYM
0x01E2 3200
RXGOODFRAMES
REGISTER NAME
Good Receive Frames Register
0x01E2 3204
RXBCASTFRAMES
Broadcast Receive Frames Register
(Total number of good broadcast frames received)
0x01E2 3208
RXMCASTFRAMES
Multicast Receive Frames Register
(Total number of good multicast frames received)
0x01E2 320C
RXPAUSEFRAMES
Pause Receive Frames Register
0x01E2 3210
RXCRCERRORS
0x01E2 3214
RXALIGNCODEERRORS
0x01E2 3218
RXOVERSIZED
0x01E2 321C
RXJABBER
0x01E2 3220
RXUNDERSIZED
Receive Undersized Frames Register
(Total number of undersized frames received)
0x01E2 3224
RXFRAGMENTS
Receive Frame Fragments Register
0x01E2 3228
RXFILTERED
0x01E2 322C
RXQOSFILTERED
0x01E2 3230
RXOCTETS
0x01E2 3234
TXGOODFRAMES
Good Transmit Frames Register
(Total number of good frames transmitted)
Receive CRC Errors Register (Total number of frames received with
CRC errors)
Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
Receive Oversized Frames Register
(Total number of oversized frames received)
Receive Jabber Frames Register
(Total number of jabber frames received)
Filtered Receive Frames Register
Received QOS Filtered Frames Register
Receive Octet Frames Register
(Total number of received bytes in good frames)
0x01E2 3238
TXBCASTFRAMES
Broadcast Transmit Frames Register
0x01E2 323C
TXMCASTFRAMES
Multicast Transmit Frames Register
0x01E2 3240
TXPAUSEFRAMES
Pause Transmit Frames Register
0x01E2 3244
TXDEFERRED
Deferred Transmit Frames Register
0x01E2 3248
TXCOLLISION
Transmit Collision Frames Register
0x01E2 324C
TXSINGLECOLL
0x01E2 3250
TXMULTICOLL
0x01E2 3254
TXEXCESSIVECOLL
0x01E2 3258
TXLATECOLL
0x01E2 325C
TXUNDERRUN
0x01E2 3260
TXCARRIERSENSE
0x01E2 3264
TXOCTETS
Peripheral Information and Electrical Specifications
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
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Table 6-29. EMAC Statistics Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x01E2 3268
FRAME64
Transmit and Receive 64 Octet Frames Register
0x01E2 326C
FRAME65T127
Transmit and Receive 65 to 127 Octet Frames Register
0x01E2 3270
FRAME128T255
Transmit and Receive 128 to 255 Octet Frames Register
0x01E2 3274
FRAME256T511
Transmit and Receive 256 to 511 Octet Frames Register
0x01E2 3278
FRAME512T1023
Transmit and Receive 512 to 1023 Octet Frames Register
0x01E2 327C
FRAME1024TUP
Transmit and Receive 1024 to 1518 Octet Frames Register
0x01E2 3280
NETOCTETS
0x01E2 3284
RXSOFOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
0x01E2 3288
RXMOFOVERRUNS
Receive FIFO or DMA Middle of Frame Overruns Register
0x01E2 328C
RXDMAOVERRUNS
Receive DMA Start of Frame and Middle of Frame Overruns
Register
Table 6-30. EMAC Control Module Registers
BYTE ADDRESS
Acronym
Register Description
0x01E2 2000
REV
EMAC Control Module Revision Register
0x01E2 2004
SOFTRESET
EMAC Control Module Software Reset Register
0x01E2 200C
INTCONTROL
EMAC Control Module Interrupt Control Register
0x01E2 2010
C0RXTHRESHEN
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable
Register
0x01E2 2014
C0RXEN
EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
0x01E2 2018
C0TXEN
EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
0x01E2 201C
C0MISCEN
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable
Register
0x01E2 2020
C1RXTHRESHEN
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable
Register
0x01E2 2024
C1RXEN
EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
0x01E2 2028
C1TXEN
EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
0x01E2 202C
C1MISCEN
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable
Register
0x01E2 2030
C2RXTHRESHEN
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable
Register
0x01E2 2034
C2RXEN
EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
0x01E2 2038
C2TXEN
EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
0x01E2 203C
C2MISCEN
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable
Register
0x01E2 2040
C0RXTHRESHSTAT
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status
Register
0x01E2 2044
C0RXSTAT
EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
0x01E2 2048
C0TXSTAT
EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
0x01E2 204C
C0MISCSTAT
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status
Register
0x01E2 2050
C1RXTHRESHSTAT
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status
Register
0x01E2 2054
C1RXSTAT
EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
0x01E2 2058
C1TXSTAT
EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
0x01E2 205C
C1MISCSTAT
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status
Register
0x01E2 2060
C2RXTHRESHSTAT
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status
Register
0x01E2 2064
C2RXSTAT
EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
0x01E2 2068
C2TXSTAT
EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
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ADVANCE INFORMATION
Network Octet Frames Register
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
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Table 6-30. EMAC Control Module Registers (continued)
BYTE ADDRESS
ADVANCE INFORMATION
Acronym
Register Description
0x01E2 206C
C2MISCSTAT
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status
Register
0x01E2 2070
C0RXIMAX
EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond
Register
0x01E2 2074
C0TXIMAX
EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond
Register
0x01E2 2078
C1RXIMAX
EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond
Register
0x01E2 207C
C1TXIMAX
EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond
Register
0x01E2 2080
C2RXIMAX
EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond
Register
0x01E2 2084
C2TXIMAX
EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond
Register
Table 6-31. EMAC Control Module RAM
HEX ADDRESS RANGE
ACRONYM
0x01E2 0000 - 0x01E2 1FFF
REGISTER NAME
EMAC Local Buffer Descriptor Memory
Table 6-32. RMII Timing Requirements
NO.
PARAMETER
MIN
TYP
MAX
20
UNIT
1
tc(REFCLK)
Cycle Time, REF_CLK
2
tw(REFCLKH)
Pulse Width, REF_CLK High
7
13
ns
ns
3
tw(REFCLKL)
Pulse Width, REF_CLK Low
7
13
ns
6
tsu(RXD-REFCLK)
Input Setup Time, RXD Valid before REF_CLK
High
4
ns
7
th(REFCLK-RXD)
Input Hold Time, RXD Valid after REF_CLK High
2
ns
8
tsu(CRSDV-REFCLK)
Input Setup Time, CRSDV Valid before
REF_CLK High
4
ns
9
th(REFCLK-CRSDV)
Input Hold Time, CRSDV Valid after REF_CLK
High
2
ns
10
tsu(RXER-REFCLK)
Input Setup Time, RXER Valid before REF_CLK
High
4
ns
11
th(REFCLKR-RXER)
Input Hold Time, RXER Valid after REF_CLK
High
2
ns
Table 6-33. RMII Timing Requirements
NO.
104
PARAMETER
MIN
TYP
MAX
UNIT
4
td(REFCLK-TXD)
Output Delay Time, REF_CLK High to TXD Valid
2.5
13
ns
5
td(REFCLK-TXEN)
Output Delay Time, REF_CLK High to TXEN
Valid
2.5
13
ns
Peripheral Information and Electrical Specifications
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1
2
3
RMII_MHz_50_CLK
5
5
RMII_TXEN
4
RMII_TXD[1:0]
6
7
8
ADVANCE INFORMATION
RMII_RXD[1:0]
9
RMII_CRS_DV
10
11
RMII_RXER
Figure 6-31. RMII Timing Diagram
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6.14 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
ADVANCE INFORMATION
For more detailed information on the MDIO peripheral, see the TMS320C6745/C6747 DSP Peripherals
Overview Reference Guide. – Literature Number SPRUFK9.
6.14.1 MDIO Registers
For a list of supported MDIO registers see Table 6-34 [MDIO Registers].
Table 6-34. MDIO Register Memory Map
HEX ADDRESS RANGE
ACRONYM
0x01E2 4000
REV
0x01E2 4004
CONTROL
REGISTER NAME
Revision Identification Register
MDIO Control Register
0x01E2 4008
ALIVE
MDIO PHY Alive Status Register
0x01E2 400C
LINK
MDIO PHY Link Status Register
0x01E2 4010
LINKINTRAW
0x01E2 4014
LINKINTMASKED
0x01E2 4018
–
0x01E2 4020
USERINTRAW
0x01E2 4024
USERINTMASKED
MDIO User Command Complete Interrupt (Masked) Register
MDIO User Command Complete Interrupt Mask Set Register
MDIO Link Status Change Interrupt (Unmasked) Register
MDIO Link Status Change Interrupt (Masked) Register
Reserved
MDIO User Command Complete Interrupt (Unmasked) Register
0x01E2 4028
USERINTMASKSET
0x01E2 402C
USERINTMASKCLEAR
0x01E2 4030 - 0x01E2 407C
–
0x01E2 4080
USERACCESS0
MDIO User Access Register 0
0x01E2 4084
USERPHYSEL0
MDIO User PHY Select Register 0
0x01E2 4088
USERACCESS1
MDIO User Access Register 1
0x01E2 408C
USERPHYSEL1
MDIO User PHY Select Register 1
0x01E2 4090 - 0x01E2 47FF
–
MDIO User Command Complete Interrupt Mask Clear Register
Reserved
Reserved
6.14.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-35. Timing Requirements for MDIO Input (see Figure 6-32 and Figure 6-33)
NO.
MIN
MAX
UNIT
1
tc(MDCLK)
Cycle time, MDCLK
400
ns
2
tw(MDCLK)
Pulse duration, MDCLK high/low
180
ns
3
tt(MDCLK)
Transition time, MDCLK
4
tsu(MDIO-MDCLKH)
Setup time, MDIO data input valid before MDCLK high
10
ns
5
th(MDCLKH-MDIO)
Hold time, MDIO data input valid after MDCLK high
10
ns
106
Peripheral Information and Electrical Specifications
5
ns
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1
3
3
MDCLK
4
5
MDIO
(input)
Table 6-36. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-33)
NO.
7
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
MIN
MAX
UNIT
0
100
ns
1
MDCLK
7
MDIO
(output)
Figure 6-33. MDIO Output Timing
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Figure 6-32. MDIO Input Timing
TMS320C6745/6747 Floating-point Digital Signal Processor
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
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6.15 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
ADVANCE INFORMATION
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
• Flexible clock and frame sync generation logic and on-chip dividers
• Up to sixteen transmit or receive data pins and serializers
• Large number of serial data format options, including:
– TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
– Time slots of 8,12,16, 20, 24, 28, and 32 bits
– First bit delay 0, 1, or 2 clocks
– MSB or LSB first bit order
– Left- or right-aligned data words within time slots
• DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers
• Extensive error checking and mute generation logic
• All unused pins GPIO-capable
Additionally, while the 674x McASP modules are backward compatible with the McASP on previous
devices; the 674x McASP includes the following new features:
• Transmit & Receive FIFO Buffers for each McASP. Allows the McASP to operate at a higher sample
rate by making it more tolerant to DMA latency.
• Dynamic Adjustment of Clock Dividers
– Clock Divider Value may be changed without resetting the McASP
The three McASPs on the C6745/6747 are configured with the following options:
Table 6-37. C6745/6747 McASP Configurations (1)
Module
(1)
Serializers
AFIFO
DIT
C6745/6747 Pins
N
AXR0[15:0], AHCLKR0, ACLKR0, AFSR0, AHCLKX0, ACLKX0,
AFSX0, AMUTE0
McASP0
16
64 Word RX
64 Word TX
McASP1
12
64 Word RX
64 Word TX
N
AXR1[11:10], AXR1[8:0], AHCLKR1, ACLKR1, AFSR1, AHCLKX1,
ACLKX1, AFSX1, AMUTE1
McASP2
4
16 Word RX
16 Word TX
Y
AXR2[3:0], AHCLKR2, ACLKR2, AFSR2, AHCLKX2, ACLKX2,
AFSX2, AMUTE2
Pins available are the maximum number of pins that may be configured for a particular McASP; not including pin multiplexing.
Pins
Peripheral
Configuration
Bus
GIO
Control
DIT RAM
384 C
384 U
Optional
McASP
DMA Bus
(Dedicated)
Transmit
Formatter
Receive
Formatter
Function
Receive Logic
Clock/Frame Generator
State Machine
AHCLKRx
ACLKRx
AFSRx
Receive Master Clock
Receive Bit Clock
Receive Left/Right Clock or Frame Sync
Clock Check and
Error Detection
AMUTEINx
AMUTEx
The McASPs DO NOT have
dedicated AMUTEINx pins.
Transmit Logic
Clock/Frame Generator
State Machine
AFSXx
ACLKXx
AHCLKXx
Transmit Left/Right Clock or Frame Sync
Transmit Bit Clock
Transmit Master Clock
Serializer 0
AXRx[0]
Transmit/Receive Serial Data Pin
Serializer 1
AXRx[1]
Transmit/Receive Serial Data Pin
Serializer y
AXRx[y]
Transmit/Receive Serial Data Pin
McASPx (x = 0, 1, 2)
Figure 6-34. McASP Block Diagram
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Peripheral Information and Electrical Specifications
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6.15.1 McASP Peripheral Registers Description(s)
Registers for the McASP are summarized in Table 6-38. The registers are accessed through the
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can
also be accessed through the DMA port, as listed in Table 6-39
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-40. Note that the AFIFO Write
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control
registers are accessed through the peripheral configuration port.
Table 6-38. McASP Registers Accessed Through Peripheral Configuration Port
McASP0
BYTE
ADDRESS
McASP1
BYTE
ADDRESS
McASP2
BYTE
ADDRESS
Acronym
Register Description
0h
0x01D0 0000
0x01D0 4000
0x01D0 8000
REV
10h
0x01D0 0010
0x01D0 4010
0x01D0 8010
PFUNC
Revision identification register
Pin function register
14h
0x01D0 0014
0x01D0 4014
0x01D0 8014
PDIR
Pin direction register
18h
0x01D0 0018
0x01D0 4018
0x01D0 8018
PDOUT
1Ch
0x01D0 001C
0x01D0 401C
0x01D0 801C
PDIN
1Ch
0x01D0 001C
0x01D0 401C
0x01D0 801C
PDSET
Writes affect: Pin data set register (alternate write
address: PDOUT)
20h
0x01D0 0020
0x01D0 4020
0x01D0 8020
PDCLR
Pin data clear register (alternate write address: PDOUT)
44h
0x01D0 0044
0x01D0 4044
0x01D0 8044
GBLCTL
Global control register
48h
0x01D0 0048
0x01D0 4048
0x01D0 8048
AMUTE
Audio mute control register
4Ch
0x01D0 004C
0x01D0 404C
0x01D0 804C
DLBCTL
Digital loopback control register
50h
0x01D0 0050
0x01D0 4050
0x01D0 8050
DITCTL
60h
0x01D0 0060
0x01D0 4060
0x01D0 8060
RGBLCTL
64h
0x01D0 0064
0x01D0 4064
0x01D0 8064
RMASK
68h
0x01D0 0068
0x01D0 4068
0x01D0 8068
RFMT
6Ch
0x01D0 006C
0x01D0 406C
0x01D0 806C
AFSRCTL
70h
0x01D0 0070
0x01D0 4070
0x01D0 8070
ACLKRCTL
74h
0x01D0 0074
0x01D0 4074
0x01D0 8074
AHCLKRCTL
78h
0x01D0 0078
0x01D0 4078
0x01D0 8078
RTDM
7Ch
0x01D0 007C
0x01D0 407C
0x01D0 807C
RINTCTL
80h
0x01D0 0080
0x01D0 4080
0x01D0 8080
RSTAT
Receiver status register
84h
0x01D0 0084
0x01D0 4084
0x01D0 8084
RSLOT
Current receive TDM time slot register
Pin data output register
Read returns: Pin data input register
DIT mode control register
Receiver global control register: Alias of GBLCTL, only
receive bits are affected - allows receiver to be reset
independently from transmitter
Receive format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
Receive high-frequency clock control register
Receive TDM time slot 0-31 register
Receiver interrupt control register
88h
0x01D0 0088
0x01D0 4088
0x01D0 8088
RCLKCHK
Receive clock check control register
8Ch
0x01D0 008C
0x01D0 408C
0x01D0 808C
REVTCTL
Receiver DMA event control register
ACh
0x01D0 00A0
0x01D0 40A0
0x01D0 80A0
XGBLCTL
Transmitter global control register. Alias of GBLCTL,
only transmit bits are affected - allows transmitter to be
reset independently from receiver
A4h
0x01D0 00A4
0x01D0 40A4
0x01D0 80A4
XMASK
A8h
0x01D0 00A8
0x01D0 40A8
0x01D0 80A8
XFMT
ACh
0x01D0 00AC
0x01D0 40AC
0x01D0 80AC
AFSXCTL
B0h
0x01D0 00B0
0x01D0 40B0
0x01D0 80B0
ACLKXCTL
B4h
0x01D0 00B4
0x01D0 40B4
0x01D0 80B4
AHCLKXCTL
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
Transmit high-frequency clock control register
B8h
0x01D0 00B8
0x01D0 40B8
0x01D0 80B8
XTDM
Transmit TDM time slot 0-31 register
BCh
0x01D0 00BC
0x01D0 40BC
0x01D0 80BC
XINTCTL
Transmitter interrupt control register
C0h
0x01D0 00C0
0x01D0 40C0
0x01D0 80C0
XSTAT
Transmitter status register
C4h
0x01D0 00C4
0x01D0 40C4
0x01D0 80C4
XSLOT
Current transmit TDM time slot register
C8h
0x01D0 00C8
0x01D0 40C8
0x01D0 80C8
XCLKCHK
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Transmit clock check control register
Peripheral Information and Electrical Specifications
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Offset
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Table 6-38. McASP Registers Accessed Through Peripheral Configuration Port (continued)
Offset
McASP0
BYTE
ADDRESS
McASP1
BYTE
ADDRESS
McASP2
BYTE
ADDRESS
Acronym
Register Description
ADVANCE INFORMATION
CCh
0x01D0 00CC
0x01D0 40CC
0x01D0 80CC
XEVTCTL
Transmitter DMA event control register
100h
0x01D0 0100
0x01D0 4100
0x01D0 8100
DITCSRA0
Left (even TDM time slot) channel status register (DIT
mode) 0
104h
0x01D0 0104
0x01D0 4104
0x01D0 8104
DITCSRA1
Left (even TDM time slot) channel status register (DIT
mode) 1
108h
0x01D0 0108
0x01D0 4108
0x01D0 8108
DITCSRA2
Left (even TDM time slot) channel status register (DIT
mode) 2
10Ch
0x01D0 010C
0x01D0 410C
0x01D0 810C
DITCSRA3
Left (even TDM time slot) channel status register (DIT
mode) 3
110h
0x01D0 0110
0x01D0 4110
0x01D0 8110
DITCSRA4
Left (even TDM time slot) channel status register (DIT
mode) 4
114h
0x01D0 0114
0x01D0 4114
0x01D0 8114
DITCSRA5
Left (even TDM time slot) channel status register (DIT
mode) 5
118h
0x01D0 0118
0x01D0 4118
0x01D0 8118
DITCSRB0
Right (odd TDM time slot) channel status register (DIT
mode) 0
11Ch
0x01D0 011C
0x01D0 411C
0x01D0 811C
DITCSRB1
Right (odd TDM time slot) channel status register (DIT
mode) 1
120h
0x01D0 0120
0x01D0 4120
0x01D0 8120
DITCSRB2
Right (odd TDM time slot) channel status register (DIT
mode) 2
124h
0x01D0 0124
0x01D0 4124
0x01D0 8124
DITCSRB3
Right (odd TDM time slot) channel status register (DIT
mode) 3
128h
0x01D0 0128
0x01D0 4128
0x01D0 8128
DITCSRB4
Right (odd TDM time slot) channel status register (DIT
mode) 4
12Ch
0x01D0 012C
0x01D0 412C
0x01D0 812C
DITCSRB5
Right (odd TDM time slot) channel status register (DIT
mode) 5
130h
0x01D0 0130
0x01D0 4130
0x01D0 8130
DITUDRA0
Left (even TDM time slot) channel user data register
(DIT mode) 0
134h
0x01D0 0134
0x01D0 4134
0x01D0 8134
DITUDRA1
Left (even TDM time slot) channel user data register
(DIT mode) 1
138h
0x01D0 0138
0x01D0 4138
0x01D0 8138
DITUDRA2
Left (even TDM time slot) channel user data register
(DIT mode) 2
13Ch
0x01D0 013C
0x01D0 413C
0x01D0 813C
DITUDRA3
Left (even TDM time slot) channel user data register
(DIT mode) 3
140h
0x01D0 0140
0x01D0 4140
0x01D0 8140
DITUDRA4
Left (even TDM time slot) channel user data register
(DIT mode) 4
144h
0x01D0 0144
0x01D0 4144
0x01D0 8144
DITUDRA5
Left (even TDM time slot) channel user data register
(DIT mode) 5
148h
0x01D0 0148
0x01D0 4148
0x01D0 8148
DITUDRB0
Right (odd TDM time slot) channel user data register
(DIT mode) 0
14Ch
0x01D0 014C
0x01D0 414C
0x01D0 814C
DITUDRB1
Right (odd TDM time slot) channel user data register
(DIT mode) 1
150h
0x01D0 0150
0x01D0 4150
0x01D0 8150
DITUDRB2
Right (odd TDM time slot) channel user data register
(DIT mode) 2
154h
0x01D0 0154
0x01D0 4154
0x01D0 8154
DITUDRB3
Right (odd TDM time slot) channel user data register
(DIT mode) 3
158h
0x01D0 0158
0x01D0 4158
0x01D0 8158
DITUDRB4
Right (odd TDM time slot) channel user data register
(DIT mode) 4
15Ch
0x01D0 015C
0x01D0 415C
0x01D0 815C
DITUDRB5
Right (odd TDM time slot) channel user data register
(DIT mode) 5
180h
0x01D0 0180
0x01D0 4180
0x01D0 8180
SRCTL0
Serializer control register 0
184h
0x01D0 0184
0x01D0 4184
0x01D0 8184
SRCTL1
Serializer control register 1
188h
0x01D0 0188
0x01D0 4188
0x01D0 8188
SRCTL2
Serializer control register 2
18Ch
0x01D0 018C
0x01D0 418C
0x01D0 818C
SRCTL3
Serializer control register 3
110
Peripheral Information and Electrical Specifications
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Offset
McASP0
BYTE
ADDRESS
McASP1
BYTE
ADDRESS
McASP2
BYTE
ADDRESS
Acronym
Register Description
190h
0x01D0 0190
0x01D0 4190
0x01D0 8190
SRCTL4
Serializer control register 4
194h
0x01D0 0194
0x01D0 4194
0x01D0 8194
SRCTL5
Serializer control register 5
198h
0x01D0 0198
0x01D0 4198
0x01D0 8198
SRCTL6
Serializer control register 6
19Ch
0x01D0 019C
0x01D0 419C
0x01D0 819C
SRCTL7
Serializer control register 7
1A0h
0x01D0 01A0
0x01D0 41A0
0x01D0 81A0
SRCTL8
Serializer control register 8
1A4h
0x01D0 01A4
0x01D0 41A4
0x01D0 81A4
SRCTL9
Serializer control register 9
1A8h
0x01D0 01A8
0x01D0 41A8
0x01D0 81A8
SRCTL10
Serializer control register 10
1ACh
0x01D0 01AC
0x01D0 41AC
0x01D0 81AC
SRCTL11
Serializer control register 11
1B0h
0x01D0 01B0
0x01D0 41B0
0x01D0 81B0
SRCTL12
Serializer control register 12
1B4h
0x01D0 01B4
0x01D0 41B4
0x01D0 81B4
SRCTL13
Serializer control register 13
Serializer control register 14
(1)
(2)
1B8h
0x01D0 01B8
0x01D0 41B8
0x01D0 81B8
SRCTL14
1BCh
0x01D0 01BC
0x01D0 41BC
0x01D0 81BC
SRCTL15
Serializer control register 15
200h
0x01D0 0200
0x01D0 4200
0x01D0 8200
XBUF0 (1)
Transmit buffer register for serializer 0
204h
0x01D0 0204
0x01D0 4204
0x01D0 8204
XBUF1 (1)
Transmit buffer register for serializer 1
(1)
Transmit buffer register for serializer 2
208h
0x01D0 0208
0x01D0 4208
0x01D0 8208
XBUF2
20Ch
0x01D0 020C
0x01D0 420C
0x01D0 820C
XBUF3 (1)
Transmit buffer register for serializer 3
210h
0x01D0 0210
0x01D0 4210
0x01D0 8210
XBUF4 (1)
Transmit buffer register for serializer 4
(1)
Transmit buffer register for serializer 5
214h
0x01D0 0214
0x01D0 4214
0x01D0 8214
XBUF5
218h
0x01D0 0218
0x01D0 4218
0x01D0 8218
XBUF6 (1)
Transmit buffer register for serializer 6
21Ch
0x01D0 021C
0x01D0 421C
0x01D0 821C
XBUF7 (1)
Transmit buffer register for serializer 7
(1)
Transmit buffer register for serializer 8
220h
0x01D0 0220
0x01D0 4220
0x01D0 8220
XBUF8
224h
0x01D0 0224
0x01D0 4224
0x01D0 8224
XBUF9 (1)
Transmit buffer register for serializer 9
228h
0x01D0 0228
0x01D0 4228
0x01D0 8228
XBUF10 (1)
Transmit buffer register for serializer 10
22Ch
0x01D0 022C
0x01D0 422C
0x01D0 822C
XBUF11 (1)
Transmit buffer register for serializer 11
(1)
Transmit buffer register for serializer 12
230h
0x01D0 0230
0x01D0 4230
0x01D0 8230
XBUF12
234h
0x01D0 0234
0x01D0 4234
0x01D0 8234
XBUF13 (1)
Transmit buffer register for serializer 13
238h
0x01D0 0238
0x01D0 4238
0x01D0 8238
XBUF14 (1)
Transmit buffer register for serializer 14
(1)
Transmit buffer register for serializer 15
23Ch
0x01D0 023C
0x01D0 423C
0x01D0 823C
XBUF15
280h
0x01D0 0280
0x01D0 4280
0x01D0 8280
RBUF0 (2)
Receive buffer register for serializer 0
284h
0x01D0 0284
0x01D0 4284
0x01D0 8284
RBUF1 (2)
Receive buffer register for serializer 1
(2)
Receive buffer register for serializer 2
288h
0x01D0 0288
0x01D0 4288
0x01D0 8288
RBUF2
28Ch
0x01D0 028C
0x01D0 428C
0x01D0 828C
RBUF3 (2)
Receive buffer register for serializer 3
290h
0x01D0 0290
0x01D0 4290
0x01D0 8290
RBUF4 (2)
Receive buffer register for serializer 4
294h
0x01D0 0294
0x01D0 4294
0x01D0 8294
RBUF5 (2)
Receive buffer register for serializer 5
(2)
Receive buffer register for serializer 6
298h
0x01D0 0298
0x01D0 4298
0x01D0 8298
RBUF6
29Ch
0x01D0 029C
0x01D0 429C
0x01D0 829C
RBUF7 (2)
Receive buffer register for serializer 7
2A0h
0x01D0 02A0
0x01D0 42A0
0x01D0 82A0
RBUF8 (2)
Receive buffer register for serializer 8
(2)
2A4h
0x01D0 02A4
0x01D0 42A4
0x01D0 82A4
RBUF9
2A8h
0x01D0 02A8
0x01D0 42A8
0x01D0 82A8
RBUF10 (2)
Receive buffer register for serializer 10
2ACh
0x01D0 02AC
0x01D0 42AC
0x01D0 82AC
RBUF11 (2)
Receive buffer register for serializer 11
(2)
Receive buffer register for serializer 12
ADVANCE INFORMATION
Table 6-38. McASP Registers Accessed Through Peripheral Configuration Port (continued)
Receive buffer register for serializer 9
2B0h
0x01D0 02B0
0x01D0 42B0
0x01D0 82B0
RBUF12
2B4h
0x01D0 02B4
0x01D0 42B4
0x01D0 82B4
RBUF13 (2)
Receive buffer register for serializer 13
2B8h
0x01D0 02B8
0x01D0 42B8
0x01D0 82BB
RBUF14 (2)
Receive buffer register for serializer 14
2BCh
0x01D0 02BC
0x01D0 42BC
0x01D0 82BC
RBUF15 (2)
Receive buffer register for serializer 15
Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
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Table 6-39. McASP Registers Accessed Through DMA Port
Hex Address
Register Name
Register Description
Read Accesses
RBUF
Receive buffer DMA port address. Cycles through receive serializers, skipping over transmit
serializers and inactive serializers. Starts at the lowest serializer at the beginning of each time slot.
Reads from DMA port only if XBUSEL = 0 in XFMT.
Write Accesses
XBUF
Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and
inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA
port only if RBUSEL = 0 in RFMT.
Table 6-40. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
ADVANCE INFORMATION
112
McASP0
BYTE ADDRESS
McASP0
BYTE ADDRESS
McASP0
BYTE ADDRESS
Acronym
Register Description
0x01D0 1000
0x01D0 5000
0x01D0 9000
AFIFOREV
AFIFO revision identification register
0x01D0 1010
0x01D0 1014
0x01D0 5010
0x01D0 9010
WFIFOCTL
Write FIFO control register
0x01D0 5014
0x01D0 9014
WFIFOSTS
Write FIFO status register
0x01D0 1018
0x01D0 5018
0x01D0 9018
RFIFOCTL
Read FIFO control register
0x01D0 101C
0x01D0 501C
0x01D0 901C
RFIFOSTS
Read FIFO status register
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6.15.2 McASP Electrical Data/Timing
6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-41 and Table 6-42 assume testing over recommended operating conditions (see Figure 6-35 and
Figure 6-36).
Table 6-41. McASP0 Timing Requirements (1) (2)
MIN
1
tc(AHCLKRX)
2
tw(AHCLKRX)
3
tc(ACLKRX)
4
tw(ACLKRX)
Cycle time, AHCLKR0 external, AHCLKR0 input
20
Cycle time, AHCLKX0 external, AHCLKX0 input
20
Pulse duration, AHCLKR0 external, AHCLKR0 input
10
Pulse duration, AHCLKX0 external, AHCLKX0 input
10
Cycle time, ACLKR0 external, ACLKR0 input
greater of 2P or 20
Cycle time, ACLKX0 external, ACLKX0 input
greater of 2P or 20
Pulse duration, ACLKR0 external, ACLKR0 input
10
Pulse duration, ACLKX0 external, ACLKX0 input
10
Setup time, AFSR0 input to ACLKR0 internal (3)
9.4
Setup time, AFSR0 input to ACLKX0 internal (4)
9.4
Setup time, AFSX0 input to ACLKX0 internal
tsu(AFSRX-ACLKRX)
2.9
Setup time, AFSR0 input to ACLKX0 external input (4)
2.9
Setup time, AFSX0 input to ACLKX0 external input
2.9
Setup time, AFSR0 input to ACLKR0 external output (3)
2.9
Setup time, AFSR0 input to ACLKX0 external output (4)
2.9
Setup time, AFSX0 input to ACLKX0 external output
2.9
(3)
-2.1
Hold time, AFSR0 input after ACLKX0 internal (4)
-2.1
Hold time, AFSX0 input after ACLKX0 internal
-2.1
Hold time, AFSR0 input after ACLKR0 internal
Hold time, AFSR0 input after ACLKR0 external input (3)
0.4
(4)
0.4
Hold time, AFSR0 input after ACLKX0 external input
6
th(ACLKRX-AFSRX)
Hold time, AFSX0 input after ACLKX0 external input
0.4
Hold time, AFSR0 input after ACLKR0 external
output (3)
0.4
Hold time, AFSR0 input after ACLKX0 external
output (4)
0.4
Hold time, AFSX0 input after ACLKX0 external output
0.4
(3)
9.4
Setup time, AXR0[n] input to ACLKX0 internal (4)
9.4
Setup time, AXR0[n] input to ACLKR0 internal
7
(1)
(2)
(3)
(4)
tsu(AXR-ACLKRX)
UNIT
ns
ns
ns
ns
9.4
(3)
Setup time, AFSR0 input to ACLKR0 external input
5
MAX
ADVANCE INFORMATION
NO.
Setup time, AXR0[n] input to ACLKR0 external input (3)
2.9
(4)
2.9
Setup time, AXR0[n] input to ACLKX0 external input
Setup time, AXR0[n] input to ACLKR0 external
output (3)
2.9
Setup time, AXR0[n] input to ACLKX0 external
output (4)
2.9
ns
ns
ns
ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
P = SYSCLK2 period
McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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Table 6-41. McASP0 Timing Requirements (continued)
NO.
8
MIN
th(ACLKRX-AXR)
Hold time, AXR0[n] input after ACLKR0 internal (3)
-2.1
Hold time, AXR0[n] input after ACLKX0 internal (4)
-2.1
Hold time, AXR0[n] input after ACLKR0 external
input (3)
0.4
Hold time, AXR0[n] input after ACLKX0 external
input (4)
0.4
Hold time, AXR0[n] input after ACLKR0 external
output (3)
0.4
Hold time, AXR0[n] input after ACLKX0 external
output (4)
0.4
MAX
UNIT
ns
ADVANCE INFORMATION
114
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Table 6-42. McASP0 Switching Characteristics (1)
9
10
11
12
PARAMETER
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
20
Cycle time, AHCLKR0 external, AHCLKR0 output
20
Cycle time, AHCLKX0 internal, AHCLKX0 output
20
Cycle time, AHCLKX0 external, AHCLKX0 output
20
Pulse duration, AHCLKR0 internal, AHCLKR0
output
(AHR/2) – 2.5 (2)
Pulse duration, AHCLKR0 external, AHCLKR0
output
(AHR/2) – 2.5 (2)
Pulse duration, AHCLKX0 internal, AHCLKX0
output
(AHX/2) – 2.5 (3)
Pulse duration, AHCLKX0 external, AHCLKX0
output
(AHX/2) – 2.5 (3)
Cycle time, ACLKR0 internal, ACLKR0 output
greater of 2P or 20 ns (4)
Cycle time, ACLKR0 external, ACLKR0 output
greater of 2P or 20 ns (4)
Cycle time, ACLKX0 internal, ACLKX0 output
greater of 2P or 20 ns (4)
Cycle time, ACLKX0 external, ACLKX0 output
greater of 2P or 20 ns (4)
14
15
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
td(ACLKRX-AFSRX)
td(ACLKX-AXRV)
tdis(ACLKX-AXRHZ)
MAX
UNIT
ns
ns
Pulse duration, ACLKR0 internal, ACLKR0 output
(AR/2) – 2.5 (5)
Pulse duration, ACLKR0 external, ACLKR0 output
(AR/2) – 2.5 (5)
Pulse duration, ACLKX0 internal, ACLKX0 output
(AX/2) – 2.5 (6)
Pulse duration, ACLKX0 external, ACLKX0 output
(AX/2) – 2.5 (6)
ns
ns
(7)
0
5.8
Delay time, ACLKX0 internal, AFSR output (8)
0
5.8
Delay time, ACLKX0 internal, AFSX output
0
5.8
Delay time, ACLKR0 external input, AFSR output (7)
3
11.6
Delay time, ACLKX0 external input, AFSR output (8)
3
11.6
Delay time, ACLKX0 external input, AFSX output
3
11.6
Delay time, ACLKR0 external output, AFSR
output (7)
3
11.6
Delay time, ACLKX0 external output, AFSR
output (8)
3
11.6
Delay time, ACLKX0 external output, AFSX output
3
11.6
Delay time, ACLKX0 internal, AXR0[n] output
0
5.8
Delay time, ACLKX0 external input, AXR0[n] output
3
11.6
Delay time, ACLKX0 external output, AXR0[n]
output
3
11.6
Disable time, ACLKX0 internal, AXR0[n] output
0
5.8
Disable time, ACLKX0 external input, AXR0[n]
output
3
11.6
Disable time, ACLKX0 external output, AXR0[n]
output
3
11.6
Delay time, ACLKR0 internal, AFSR output
13
MIN
Cycle time, AHCLKX0 internal, AHCLKR0 output
ADVANCE INFORMATION
NO.
ns
ns
ns
McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
AHR - Cycle time, AHCLKR0.
AHX - Cycle time, AHCLKX0.
P = SYSCLK2 period
AR - ACLKR0 period.
AX - ACLKX0 period.
McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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6.15.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
Table 6-43 and Table 6-44 assume testing over recommended operating conditions (see Figure 6-35 and
Figure 6-36).
Table 6-43. McASP1 Timing Requirements (1) (2)
NO.
MIN
ADVANCE INFORMATION
1
tc(AHCLKRX)
2
tw(AHCLKRX)
3
tc(ACLKRX)
4
tw(ACLKRX)
Cycle time, AHCLKR1 external, AHCLKR1 input
20
Cycle time, AHCLKX1 external, AHCLKX1 input
20
Pulse duration, AHCLKR1 external, AHCLKR1 input
10
Pulse duration, AHCLKX1 external, AHCLKX1 input
10
Cycle time, ACLKR1 external, ACLKR1 input
greater of 2P or 20
Cycle time, ACLKX1 external, ACLKX1 input
greater of 2P or 20
Pulse duration, ACLKR1 external, ACLKR1 input
10
Pulse duration, ACLKX1 external, ACLKX1 input
10
Setup time, AFSR1 input to ACLKR1 internal (3)
10.4
(4)
10.4
Setup time, AFSR1 input to ACLKX1 internal
Setup time, AFSX1 input to ACLKX1 internal
5
tsu(AFSRX-ACLKRX)
th(ACLKRX-AFSRX)
2.6
Setup time, AFSR1 input to ACLKX1 external input (4)
2.6
Setup time, AFSX1 input to ACLKX1 external input
2.6
Setup time, AFSR1 input to ACLKR1 external output (3)
2.6
Setup time, AFSR1 input to ACLKX1 external output (4)
2.6
-2.6
Hold time, AFSR1 input after ACLKX1 internal (4)
-2.6
Hold time, AFSX1 input after ACLKX1 internal
-2.6
Hold time, AFSR1 input after ACLKR1 external input (3)
0.3
Hold time, AFSR1 input after ACLKX1 external input (4)
0.3
Hold time, AFSX1 input after ACLKX1 external input
0.3
Hold time, AFSR1 input after ACLKR1 external
output (3)
0.3
Hold time, AFSR1 input after ACLKX1 external
output (4)
0.3
Hold time, AFSX1 input after ACLKX1 external output
Setup time, AXR1[n] input to ACLKR1 internal (3)
(1)
(2)
(3)
(4)
116
tsu(AXR-ACLKRX)
ns
ns
ns
ns
ns
0.3
10.4
Setup time, AXR1[n] input to ACLKX1 internal (4)
7
ns
2.6
Hold time, AFSR1 input after ACLKR1 internal (3)
10.4
(3)
2.6
Setup time, AXR1[n] input to ACLKX1 external input (4)
2.6
Setup time, AXR1[n] input to ACLKR1 external
output (3)
2.6
Setup time, AXR1[n] input to ACLKX1 external
output (4)
2.6
Setup time, AXR1[n] input to ACLKR1 external input
UNIT
10.4
Setup time, AFSR1 input to ACLKR1 external input (3)
Setup time, AFSX1 input to ACLKX1 external output
6
MAX
ns
ACLKX1 internal – McASP1 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX1 external input – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX1 external output – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR1 internal – McASP1 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR1 external input – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR1 external output – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
P = SYSCLK2 period
McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
Peripheral Information and Electrical Specifications
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Table 6-43. McASP1 Timing Requirements (continued)
NO.
th(ACLKRX-AXR)
-2.6
Hold time, AXR1[n] input after ACLKX1 internal (4)
-2.6
Hold time, AXR1[n] input after ACLKR1 external
input (3)
0.3
Hold time, AXR1[n] input after ACLKX1 external
input (4)
0.3
Hold time, AXR1[n] input after ACLKR1 external
output (3)
0.3
Hold time, AXR1[n] input after ACLKX1 external
output (4)
0.3
MAX
UNIT
ns
ADVANCE INFORMATION
8
MIN
Hold time, AXR1[n] input after ACLKR1 internal (3)
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Table 6-44. McASP1 Switching Characteristics (1)
NO.
9
10
ADVANCE INFORMATION
11
12
PARAMETER
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
20
Cycle time, AHCLKR1 external, AHCLKR1 output
20
Cycle time, AHCLKX1 internal, AHCLKX1 output
20
Cycle time, AHCLKX1 external, AHCLKX1 output
20
Pulse duration, AHCLKR1 internal, AHCLKR1
output
(AHR/2) – 2.5 (2)
Pulse duration, AHCLKR1 external, AHCLKR1
output
(AHR/2) – 2.5 (2)
Pulse duration, AHCLKX1 internal, AHCLKX1
output
(AHX/2) – 2.5 (3)
Pulse duration, AHCLKX1 external, AHCLKX1
output
(AHX/2) – 2.5 (3)
Cycle time, ACLKR1 internal, ACLKR1 output
greater of 2P or 20 ns (4)
Cycle time, ACLKR1 external, ACLKR1 output
greater of 2P or 20 ns (4)
Cycle time, ACLKX1 internal, ACLKX1 output
greater of 2P or 20 ns (4)
Cycle time, ACLKX1 external, ACLKX1 output
greater of 2P or 20 ns (4)
14
15
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
118
td(ACLKRX-AFSRX)
td(ACLKX-AXRV)
tdis(ACLKX-AXRHZ)
MAX
UNIT
ns
ns
Pulse duration, ACLKR1 internal, ACLKR1 output
(AR/2) – 2.5 (5)
Pulse duration, ACLKR1 external, ACLKR1 output
(AR/2) – 2.5 (5)
Pulse duration, ACLKX1 internal, ACLKX1 output
(AX/2) – 2.5 (6)
Pulse duration, ACLKX1 external, ACLKX1 output
(AX/2) – 2.5 (6)
ns
ns
(7)
0.5
6.7
Delay time, ACLKX1 internal, AFSR output (8)
0.5
6.7
Delay time, ACLKX1 internal, AFSX output
0.5
6.7
Delay time, ACLKR1 external input, AFSR output (7)
3.9
13.8
Delay time, ACLKX1 external input, AFSR output (8)
3.9
13.8
Delay time, ACLKX1 external input, AFSX output
3.9
13.8
Delay time, ACLKR1 external output, AFSR
output (7)
3.9
13.8
Delay time, ACLKX1 external output, AFSR
output (8)
3.9
13.8
Delay time, ACLKX1 external output, AFSX output
3.9
13.8
Delay time, ACLKX1 internal, AXR1[n] output
0.5
6.7
Delay time, ACLKX1 external input, AXR1[n] output
3.9
13.8
Delay time, ACLKX1 external output, AXR1[n]
output
3.9
13.8
Disable time, ACLKX1 internal, AXR1[n] output
0.5
6.7
Disable time, ACLKX1 external input, AXR1[n]
output
3.9
13.8
Disable time, ACLKX1 external output, AXR1[n]
output
3.9
13.8
Delay time, ACLKR1 internal, AFSR output
13
MIN
Cycle time, AHCLKX1 internal, AHCLKR1 output
ns
ns
ns
McASP1 ACLKX1 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP1 ACLKX1 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP1 ACLKX1 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP1 ACLKR1 internal – ACLKR1CTL.CLKRM = 1, PDIR.ACLKR =1
McASP1 ACLKR1 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP1 ACLKR1 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
AHR - Cycle time, AHCLKR1.
AHX - Cycle time, AHCLKX1.
P = SYSCLK2 period
AR - ACLKR1 period.
AX - ACLKX1 period.
McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
Peripheral Information and Electrical Specifications
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6.15.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
Table 6-45 and Table 6-46 assume testing over recommended operating conditions (see Figure 6-35 and
Figure 6-36).
Table 6-45. McASP2 Timing Requirements (1) (2)
MIN
1
tc(AHCLKRX)
2
tw(AHCLKRX)
3
tc(ACLKRX)
4
tw(ACLKRX)
Cycle time, AHCLKR2 external, AHCLKR2 input
13
Cycle time, AHCLKX2 external, AHCLKX2 input
13
Pulse duration, AHCLKR2 external, AHCLKR2 input
6.5
Pulse duration, AHCLKX2 external, AHCLKX2 input
6.5
Cycle time, ACLKR2 external, ACLKR2 input
greater of 2P or 13
Cycle time, ACLKX2 external, ACLKX2 input
greater of 2P or 13
Pulse duration, ACLKR2 external, ACLKR2 input
6.5
Pulse duration, ACLKX2 external, ACLKX2 input
6.5
Setup time, AFSR2 input to ACLKR2 internal (3)
10
(4)
10
Setup time, AFSR2 input to ACLKX2 internal
5
tsu(AFSRX-ACLKRX)
Setup time, AFSX2 input to ACLKX2 internal
10
Setup time, AFSR2 input to ACLKR2 external input (3)
1.6
Setup time, AFSR2 input to ACLKX2 external input (4)
1.6
Setup time, AFSX2 input to ACLKX2 external input
1.6
Setup time, AFSR2 input to ACLKR2 external output (3)
1.6
Setup time, AFSR2 input to ACLKX2 external output (4)
1.6
Setup time, AFSX2 input to ACLKX2 external output
6
th(ACLKRX-AFSRX)
-2.2
Hold time, AFSR2 input after ACLKX2 internal (4)
-2.2
Hold time, AFSX2 input after ACLKX2 internal
-2.2
Hold time, AFSR2 input after ACLKR2 external input (3)
1.3
Hold time, AFSR2 input after ACLKX2 external input (4)
1.3
Hold time, AFSX2 input after ACLKX2 external input
1.3
Hold time, AFSR2 input after ACLKR2 external
output (3)
1.3
Hold time, AFSR2 input after ACLKX2 external
output (4)
1.3
Hold time, AFSX2 input after ACLKX2 external output
1.3
Setup time, AXR2[n] input to ACLKR2 internal (3)
10
Setup time, AXR2[n] input to ACLKX2 internal (4)
7
(1)
(2)
(3)
(4)
tsu(AXR-ACLKRX)
UNIT
ns
ns
ns
ns
ns
1.6
Hold time, AFSR2 input after ACLKR2 internal (3)
ns
10
(3)
1.6
Setup time, AXR2[n] input to ACLKX2 external input (4)
1.6
Setup time, AXR2[n] input to ACLKR2 external
output (3)
1.6
Setup time, AXR2[n] input to ACLKX2 external
output (4)
1.6
Setup time, AXR2[n] input to ACLKR2 external input
MAX
ADVANCE INFORMATION
NO.
ns
ACLKX2 internal – McASP2 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX2 external input – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX2 external output – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR2 internal – McASP2 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR2 external input – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR2 external output – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
P = SYSCLK2 period
McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
McASP2 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX2
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Table 6-45. McASP2 Timing Requirements (continued)
NO.
8
MIN
th(ACLKRX-AXR)
Hold time, AXR2[n] input after ACLKR2 internal (3)
-2.2
Hold time, AXR2[n] input after ACLKX2 internal (4)
-2.2
Hold time, AXR2[n] input after ACLKR2 external
input (3)
1.3
Hold time, AXR2[n] input after ACLKX2 external
input (4)
1.3
Hold time, AXR2[n] input after ACLKR2 external
output (3)
1.3
Hold time, AXR2[n] input after ACLKX2 external
output (4)
1.3
MAX
UNIT
ns
ADVANCE INFORMATION
120
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Table 6-46. McASP2 Switching Characteristics (1)
9
10
11
12
PARAMETER
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
13
Cycle time, AHCLKR2 external, AHCLKR2 output
13
Cycle time, AHCLKX2 internal, AHCLKX2 output
13
Cycle time, AHCLKX2 external, AHCLKX2 output
13
Pulse duration, AHCLKR2 internal, AHCLKR2
output
(AHR/2) – 2.5 (2)
Pulse duration, AHCLKR2 external, AHCLKR2
output
(AHR/2) – 2.5 (2)
Pulse duration, AHCLKX2 internal, AHCLKX2
output
(AHX/2) – 2.5 (3)
Pulse duration, AHCLKX2 external, AHCLKX2
output
(AHX/2) – 2.5 (3)
Cycle time, ACLKR2 internal, ACLKR2 output
greater of 2P or 13 ns (4)
Cycle time, ACLKR2 external, ACLKR2 output
greater of 2P or 13 ns (4)
Cycle time, ACLKX2 internal, ACLKX2 output
greater of 2P or 13 ns (4)
Cycle time, ACLKX2 external, ACLKX2 output
greater of 2P or 13 ns (4)
td(ACLKRX-AFSRX)
(AR/2) – 2.5 (5)
Pulse duration, ACLKR2 external, ACLKR2 output
(AR/2) – 2.5 (5)
Pulse duration, ACLKX2 internal, ACLKX2 output
(AX/2) – 2.5 (6)
Pulse duration, ACLKX2 external, ACLKX2 output
(AX/2) – 2.5 (6)
15
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
tdis(ACLKX-AXRHZ)
ns
ns
-1.4
2.8
Delay time, ACLKX2 internal, AFSR output (8)
-1.4
2.8
Delay time, ACLKX2 internal, AFSX output
-1.4
2.8
Delay time, ACLKR2 external input, AFSR output (7)
2.9
10
Delay time, ACLKX2 external input, AFSR output (8)
2.9
10
Delay time, ACLKX2 external input, AFSX output
2.9
10
Delay time, ACLKR2 external output, AFSR
output (7)
2.9
10
Delay time, ACLKX2 external output, AFSR
output (8)
2.9
10
2.9
10
-1.4
2.8
Delay time, ACLKX2 external input, AXR2[n] output
2.9
10
Delay time, ACLKX2 external output, AXR2[n]
output
2.9
10
Disable time, ACLKX2 internal, AXR2[n] output
-1.4
2.8
Disable time, ACLKX2 external input, AXR2[n]
output
2.9
10
Disable time, ACLKX2 external output, AXR2[n]
output
2.9
10
Delay time, ACLKX2 internal, AXR2[n] output
td(ACLKX-AXRV)
UNIT
ns
(7)
Delay time, ACLKX2 external output, AFSX output
14
MAX
ns
Pulse duration, ACLKR2 internal, ACLKR2 output
Delay time, ACLKR2 internal, AFSR output
13
MIN
Cycle time, AHCLKX2 internal, AHCLKR2 output
ADVANCE INFORMATION
NO.
ns
ns
ns
McASP2 ACLKX2 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP2 ACLKX2 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP2 ACLKX2 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP2 ACLKR2 internal – ACLKR2CTL.CLKRM = 1, PDIR.ACLKR =1
McASP2 ACLKR2 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP2 ACLKR2 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
AHR - Cycle time, AHCLKR2.
AHX - Cycle time, AHCLKX2.
P = SYSCLK2 period
AR - ACLKR2 period.
AX - ACLKX2 period.
McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
McASP2 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX2
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
ACLKR/X (CLKRP = CLKXP = 0)(A)
ACLKR/X (CLKRP = CLKXP = 1)(B)
ADVANCE INFORMATION
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0
A1
A30 A31 B0 B1
B30 B31 C0 C1
C2 C3
C31
A.
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B.
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 6-35. McASP Input Timings
122
Peripheral Information and Electrical Specifications
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10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
ACLKR/X (CLKRP = CLKXP = 1)(A)
ADVANCE INFORMATION
ACLKR/X (CLKRP = CLKXP = 0)(B)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
13
13
13
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
14
15
AXR[n] (Data Out/Transmit)
A0
A1
A30 A31 B0 B1
B30 B31 C0
C1 C2 C3
A.
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B.
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
C31
Figure 6-36. McASP Output Timings
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6.16 Serial Peripheral Interface Ports (SPI0, SPI1)
Figure 6-37 is a block diagram of the SPI module, which is a simple shift register and buffer plus control
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end
of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives
the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many
data formatting options.
SPIx_SIMO
SPIx_SOMI
Peripheral
Configuration Bus
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Interrupt and
DMA Requests
16-Bit Shift Register
16-Bit Buffer
SPIx_ENA
State
GPIO
Machine SPIx_SCS
Control
(all pins) Clock SPIx_CLK
Control
Figure 6-37. Block Diagram of SPI Module
The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and
SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).
The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are
other slave devices on the same SPI port. The C6745/6747 will only shift data and drive the SPIx_SOMI
pin when SPIx_SCS is held low.
In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain
manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In
four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating
that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified
by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the
same SPI bus.
In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start
of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI
communications and, on average, increases SPI bus throughput since the master does not need to delay
each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer
can begin as soon as both the master and slave have actually serviced the previous SPI transfer.
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Optional − Slave Chip Select
SPIx_SCS
SPIx_SCS
SPIx_ENA
SPIx_ENA
SPIx_CLK
SPIx_CLK
SPIx_SOMI
SPIx_SOMI
SPIx_SIMO
SPIx_SIMO
MASTER SPI
SLAVE SPI
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Optional Enable (Ready)
Figure 6-38. Illustration of SPI Master-to-SPI Slave Connection
6.16.1 SPI Peripheral Registers Description(s)
Table 6-47 is a list of the SPI registers.
Table 6-47. SPIx Configuration Registers
SPI0
BYTE ADDRESS
SPI1
BYTE ADDRESS
0x01C4 1000
0x01E1 2000
SPIGCR0
Global Control Register 0
0x01C4 1004
0x01E1 2004
SPIGCR1
Global Control Register 1
0x01C4 1008
0x01E1 2008
SPIINT0
Interrupt Register
0x01C4 100C
0x01E1 200C
SPILVL
Interrupt Level Register
0x01C4 1010
0x01E1 2010
SPIFLG
Flag Register
0x01C4 1014
0x01E1 2014
SPIPC0
Pin Control Register 0 (Pin Function)
REGISTER NAME
DESCRIPTION
0x01C4 1018
0x01E1 2018
SPIPC1
Pin Control Register 1 (Pin Direction)
0x01C4 101C
0x01E1 201C
SPIPC2
Pin Control Register 2 (Pin Data In)
0x01C4 1020
0x01E1 2020
SPIPC3
Pin Control Register 3 (Pin Data Out)
0x01C4 1024
0x01E1 2024
SPIPC4
Pin Control Register 4 (Pin Data Set)
0x01C4 1028
0x01E1 2028
SPIPC5
Pin Control Register 5 (Pin Data Clear)
0x01C4 102C
0x01E1 202C
Reserved
Reserved - Do not write to this register
0x01C4 1030
0x01E1 2030
Reserved
Reserved - Do not write to this register
0x01C4 1034
0x01E1 2034
Reserved
Reserved - Do not write to this register
0x01C4 1038
0x01E1 2038
SPIDAT0
Shift Register 0 (without format select)
0x01C4 103C
0x01E1 203C
SPIDAT1
Shift Register 1 (with format select)
0x01C4 1040
0x01E1 2040
SPIBUF
Buffer Register
0x01C4 1044
0x01E1 2044
SPIEMU
Emulation Register
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Table 6-47. SPIx Configuration Registers (continued)
SPI0
BYTE ADDRESS
SPI1
BYTE ADDRESS
0x01C4 1048
0x01E1 2048
SPIDELAY
Delay Register
0x01C4 104C
0x01E1 204C
SPIDEF
Default Chip Select Register
0x01C4 1050
0x01E1 2050
SPIFMT0
Format Register 0
0x01C4 1054
0x01E1 2054
SPIFMT1
Format Register 1
REGISTER NAME
DESCRIPTION
0x01C4 1058
0x01E1 2058
SPIFMT2
Format Register 2
0x01C4 105C
0x01E1 205C
SPIFMT3
Format Register 3
0x01C4 1060
0x01E1 2060
INTVEC0
Interrupt Vector for SPI INT0
0x01C4 1064
0x01E1 2064
INTVEC1
Interrupt Vector for SPI INT1
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6.16.2 SPI Electrical Data/Timing
6.16.2.1 Serial Peripheral Interface (SPI) Timing
Table 6-48 through Table 6-63 assume testing over recommended operating conditions (see Figure 6-39
through Figure 6-42).
Table 6-48. General Timing Requirements for SPI0 Master Modes (1)
Cycle Time, SPI0_CLK, All Master Modes
2
tw(SPCH)M
Pulse Width High, SPI0_CLK, All Master Modes
0.5tc(SPC)M - 1
ns
3
tw(SPCL)M
Pulse Width Low, SPI0_CLK, All Master Modes
0.5tc(SPC)M - 1
ns
5
6
7
8
td(SIMO_SPC)M
td(SPC_SIMO)M
toh(SPC_SIMO)M
tsu(SOMI_SPC)M
tih(SPC_SOMI)M
Delay, initial data bit valid
on SPI0_SIMO to initial
edge on SPI0_CLK (2)
Delay, subsequent bits
valid on SPI0_SIMO after
transmit edge of SPI0_CLK
Output hold time,
SPI0_SIMO valid after
receive edge of SPI0_CLK
Input Setup Time,
SPI0_SOMI valid before
receive edge of SPI0_CLK
Input Hold Time,
SPI0_SOMI valid after
receive edge of SPI0_CLK
greater of 2P or 20 ns
MAX UNIT
tc(SPC)M
4,5
(1)
(2)
MIN
1
Polarity = 0, Phase = 0,
to SPI0_CLK rising
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M - 5
Polarity = 1, Phase = 0,
to SPI0_CLK falling
5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M - 5
256P
ns
ns
Polarity = 0, Phase = 0,
from SPI0_CLK rising
5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
5
Polarity = 1, Phase = 0,
from SPI0_CLK falling
5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
5
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0
Polarity = 1, Phase = 0,
to SPI0_CLK rising
0
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0
Polarity = 0, Phase = 0,
from SPI0_CLK falling
5
Polarity = 0, Phase = 1,
from SPI0_CLK rising
5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
5
Polarity = 1, Phase = 1,
from SPI0_CLK falling
5
ns
ns
ns
P = SYSCLK2 period
First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
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Table 6-49. General Timing Requirements for SPI0 Slave Modes (1)
NO.
MIN
greater of 2P or
20 ns
MAX UNIT
9
tc(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
10
tw(SPCH)S
Pulse Width High, SPI0_CLK, All Slave Modes
10
ns
11
tw(SPCL)S
Pulse Width Low, SPI0_CLK, All Slave Modes
10
ns
12
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13
14
15
16
(1)
(2)
(3)
128
tsu(SOMI_SPC)S
td(SPC_SOMI)S
toh(SPC_SOMI)S
tsu(SIMO_SPC)S
tih(SPC_SIMO)S
Setup time, transmit data
written to SPI before initial
clock edge from
master. (2) (3)
Delay, subsequent bits
valid on SPI0_SOMI after
transmit edge of SPI0_CLK
Output hold time,
SPI0_SOMI valid after
receive edge of SPI0_CLK
Input Setup Time,
SPI0_SIMO valid before
receive edge of SPI0_CLK
Input Hold Time,
SPI0_SIMO valid after
receive edge of SPI0_CLK
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P
Polarity = 0, Phase = 1,
to SPI0_CLK rising
2P
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P
Polarity = 1, Phase = 1,
to SPI0_CLK falling
2P
256P
ns
ns
Polarity = 0, Phase = 0,
from SPI0_CLK rising
9
Polarity = 0, Phase = 1,
from SPI0_CLK falling
9
Polarity = 1, Phase = 0,
from SPI0_CLK falling
9
Polarity = 1, Phase = 1,
from SPI0_CLK rising
9
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0
Polarity = 1, Phase = 0,
to SPI0_CLK rising
0
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0
Polarity = 0, Phase = 0,
from SPI0_CLK falling
5
Polarity = 0, Phase = 1,
from SPI0_CLK rising
5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
5
Polarity = 1, Phase = 1,
from SPI0_CLK falling
5
ns
ns
ns
P = SYSCLK2 period
First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
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Table 6-50. Additional (1) SPI0 Master Timings, 4-Pin Enable Option (2) (3)
17
td(ENA_SPC)M
18
(1)
(2)
(3)
(4)
(5)
MIN
td(SPC_ENA)M
Delay from slave assertion of
SPI0_ENA active to first
SPI0_CLK from master. (4)
Max delay for slave to deassert
SPI0_ENA after final SPI0_CLK
edge to ensure master does not
begin the next transfer. (5)
MAX UNIT
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 3P + 5
Polarity = 1, Phase = 0,
to SPI0_CLK falling
3P + 5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI0_CLK falling
0
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M
Polarity = 1, Phase = 1,
from SPI0_CLK rising
0
ns
ns
These parameters are in addition to the general timings for SPI master modes (Table 6-48).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI0_ENA assertion.
In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
Table 6-51. Additional (1) SPI0 Master Timings, 4-Pin Chip Select Option (2) (3)
NO.
19
20
(1)
(2)
(3)
(4)
(5)
(6)
(7)
MIN
td(SCS_SPC)M
td(SPC_SCS)M
Delay from SPI0_SCS active to
first SPI0_CLK (4) (5)
Delay from final SPI0_CLK edge
to master deasserting SPI0_SCS
(6) (7)
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P -3
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 2P -3
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P -3
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P -3
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI0_CLK falling
0
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M
Polarity = 1, Phase = 1,
from SPI0_CLK rising
0
MAX UNIT
ns
ns
These parameters are in addition to the general timings for SPI master modes (Table 6-48).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI0_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Table 6-52. Additional (1) SPI0 Master Timings, 5-Pin Option (2) (3)
NO.
18
ADVANCE INFORMATION
20
21
22
23
MIN
td(SPC_ENA)M
td(SPC_SCS)M
td(SCSL_ENAL)M
td(SCS_SPC)M
td(ENA_SPC)M
Max delay for slave to
deassert SPI0_ENA after
final SPI0_CLK edge to
ensure master does not
begin the next
transfer. (4)
Delay from final
SPI0_CLK edge to
master deasserting
SPI0_SCS (5) (6)
P+5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)M + P + 5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
P+5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)M + P + 5
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI0_CLK falling
0
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M
Polarity = 1, Phase = 1,
from SPI0_CLK rising
0
ns
Max delay for slave SPI to drive SPI0_ENA valid
after master asserts SPI0_SCS to delay the
master from beginning the next transfer,
Delay from SPI0_SCS
active to first
SPI0_CLK (7) (8) (9)
Delay from assertion of
SPI0_ENA low to first
SPI0_CLK edge. (10)
MAX UNIT
Polarity = 0, Phase = 0,
from SPI0_CLK falling
C2TDELAY + P
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P -3
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 2P -3
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P -3
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P -3
ns
ns
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 3P + 5
Polarity = 1, Phase = 0,
to SPI0_CLK falling
3P + 5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 5
ns
(1)
(2)
(3)
(4)
(5)
These parameters are in addition to the general timings for SPI master modes (Table 6-49).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
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Table 6-53. Additional (1) SPI0 Slave Timings, 4-Pin Enable Option (2) (3)
NO.
(1)
(2)
(3)
Delay from final
SPI0_CLK edge to slave
deasserting SPI0_ENA.
td(SPC_ENAH)S
MAX UNIT
1.5 P -3
2.5 P + 9
Polarity = 0, Phase = 1,
from SPI0_CLK falling
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 9
Polarity = 1, Phase = 0,
from SPI0_CLK rising
1.5 P -3
2.5 P + 9
Polarity = 1, Phase = 1,
from SPI0_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 9
ns
These parameters are in addition to the general timings for SPI slave modes (Table 6-49).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-54. Additional (1) SPI0 Slave Timings, 4-Pin Chip Select Option (2) (3)
NO.
25
26
(1)
(2)
(3)
MIN
td(SCSL_SPC)S
td(SPC_SCSH)S
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
Required delay from final
SPI0_CLK edge before
SPI0_SCS is deasserted.
MAX
P
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
from SPI0_CLK falling
0
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + 0
Polarity = 1, Phase = 1,
from SPI0_CLK rising
0
UNIT
ns
ns
27
tena(SCSL_SOMI)S
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
P+9
ns
28
tdis(SCSH_SOMI)S
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
P+9
ns
These parameters are in addition to the general timings for SPI slave modes (Table 6-49).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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MIN
Polarity = 0, Phase = 0,
from SPI0_CLK falling
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Table 6-55. Additional (1) SPI0 Slave Timings, 5-Pin Option (2) (3)
NO.
25
26
MIN
td(SCSL_SPC)S
td(SPC_SCSH)S
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
Required delay from final
SPI0_CLK edge before
SPI0_SCS is deasserted.
MAX
UNIT
P
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
from SPI0_CLK falling
0
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + 0
Polarity = 1, Phase = 1,
from SPI0_CLK rising
0
ns
ns
ADVANCE INFORMATION
27
tena(SCSL_SOMI)S
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
P+9
ns
28
tdis(SCSH_SOMI)S
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
P+9
ns
29
tena(SCSL_ENA)S
Delay from master deasserting SPI0_SCS to slave driving
SPI0_ENA valid
9
ns
30
(1)
(2)
(3)
(4)
tdis(SPC_ENA)S
Delay from final clock receive
edge on SPI0_CLK to slave
3-stating or driving high
SPI0_ENA. (4)
Polarity = 0, Phase = 0,
from SPI0_CLK falling
2.5 P + 9
Polarity = 0, Phase = 1,
from SPI0_CLK rising
2.5 P + 9
Polarity = 1, Phase = 0,
from SPI0_CLK rising
2.5 P + 9
Polarity = 1, Phase = 1,
from SPI0_CLK falling
2.5 P + 9
ns
These parameters are in addition to the general timings for SPI slave modes (Table 6-49).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
Table 6-56. General Timing Requirements for SPI1 Master Modes (1)
NO.
MIN
1
tc(SPC)M
Cycle Time, SPI1_CLK, All Master Modes
2
tw(SPCH)M
Pulse Width High, SPI1_CLK, All Master Modes
0.5tc(SPC)M - 1
ns
3
tw(SPCL)M
Pulse Width Low, SPI1_CLK, All Master Modes
0.5tc(SPC)M - 1
ns
4,5
5
(1)
(2)
132
td(SIMO_SPC)M
td(SPC_SIMO)M
Delay, initial data bit valid
on SPI1_SIMO to initial
edge on SPI1_CLK (2)
Delay, subsequent bits
valid on SPI1_SIMO after
transmit edge of SPI1_CLK
greater of 2P or 20 ns
MAX UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M - 5
Polarity = 1, Phase = 0,
to SPI1_CLK falling
5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M - 5
256P
ns
ns
Polarity = 0, Phase = 0,
from SPI1_CLK rising
5
Polarity = 0, Phase = 1,
from SPI1_CLK falling
5
Polarity = 1, Phase = 0,
from SPI1_CLK falling
5
Polarity = 1, Phase = 1,
from SPI1_CLK rising
5
ns
P = SYSCLK2 period
First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
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Table 6-56. General Timing Requirements for SPI1 Master Modes (continued)
6
MIN
toh(SPC_SIMO)M
7
tsu(SOMI_SPC)M
8
tih(SPC_SOMI)M
Output hold time,
SPI1_SIMO valid after
receive edge of SPI1_CLK
Input Setup Time,
SPI1_SOMI valid before
receive edge of SPI1_CLK
Input Hold Time,
SPI1_SOMI valid after
receive edge of SPI1_CLK
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 0,
to SPI1_CLK falling
0
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0
Polarity = 1, Phase = 0,
to SPI1_CLK rising
0
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0
Polarity = 0, Phase = 0,
from SPI1_CLK falling
5
Polarity = 0, Phase = 1,
from SPI1_CLK rising
5
Polarity = 1, Phase = 0,
from SPI1_CLK rising
5
Polarity = 1, Phase = 1,
from SPI1_CLK falling
5
MAX UNIT
ns
ns
ns
Table 6-57. General Timing Requirements for SPI1 Slave Modes (1)
NO.
MIN
greater of 2P or
20 ns
MAX UNIT
9
tc(SPC)S
Cycle Time, SPI1_CLK, All Slave Modes
10
tw(SPCH)S
Pulse Width High, SPI1_CLK, All Slave Modes
10
ns
11
tw(SPCL)S
Pulse Width Low, SPI1_CLK, All Slave Modes
10
ns
12
13
(1)
(2)
(3)
tsu(SOMI_SPC)S
td(SPC_SOMI)S
Setup time, transmit data
written to SPI before initial
clock edge from
master. (2) (3)
Delay, subsequent bits
valid on SPI1_SOMI after
transmit edge of SPI1_CLK
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P
Polarity = 0, Phase = 1,
to SPI1_CLK rising
2P
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P
Polarity = 1, Phase = 1,
to SPI1_CLK falling
2P
256P
ns
ns
Polarity = 0, Phase = 0,
from SPI1_CLK rising
9.7
Polarity = 0, Phase = 1,
from SPI1_CLK falling
9.7
Polarity = 1, Phase = 0,
from SPI1_CLK falling
9.7
Polarity = 1, Phase = 1,
from SPI1_CLK rising
9.7
ns
P = SYSCLK2 period
First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
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Table 6-57. General Timing Requirements for SPI1 Slave Modes (continued)
NO.
14
MIN
toh(SPC_SOMI)S
ADVANCE INFORMATION
15
tsu(SIMO_SPC)S
16
tih(SPC_SIMO)S
Output hold time,
SPI1_SOMI valid after
receive edge of SPI1_CLK
Input Setup Time,
SPI1_SIMO valid before
receive edge of SPI1_CLK
Input Hold Time,
SPI1_SIMO valid after
receive edge of SPI1_CLK
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI1_CLK falling
0
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0
Polarity = 1, Phase = 0,
to SPI1_CLK rising
0
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0
Polarity = 0, Phase = 0,
from SPI1_CLK falling
5
Polarity = 0, Phase = 1,
from SPI1_CLK rising
5
Polarity = 1, Phase = 0,
from SPI1_CLK rising
5
Polarity = 1, Phase = 1,
from SPI1_CLK falling
5
MAX UNIT
ns
ns
ns
Table 6-58. Additional (1) SPI1 Master Timings, 4-Pin Enable Option (2) (3)
NO.
17
18
(1)
(2)
(3)
(4)
(5)
134
MIN
td(EN
A_SPC)M
td(SPC_ENA)M
Delay from slave assertion of
SPI1_ENA active to first
SPI1_CLK from master. (4)
Max delay for slave to deassert
SPI1_ENA after final SPI1_CLK
edge to ensure master does not
begin the next transfer. (5)
MAX UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 3P + 5
Polarity = 1, Phase = 0,
to SPI1_CLK falling
3P + 5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M
Polarity = 1, Phase = 1,
from SPI1_CLK rising
0
ns
ns
These parameters are in addition to the general timings for SPI master modes (Table 6-56).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI1_ENA assertion.
In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
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Table 6-59. Additional (1) SPI1 Master Timings, 4-Pin Chip Select Option (2) (3)
NO.
td(SCS_SPC)M
20
(1)
(2)
(3)
(4)
(5)
(6)
(7)
td(SPC_SCS)M
Delay from SPI1_SCS active to
first SPI1_CLK (4) (5)
Delay from final SPI1_CLK edge
to master deasserting SPI1_SCS
(6) (7)
2P -3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 2P -3
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P -3
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -3
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M
Polarity = 1, Phase = 1,
from SPI1_CLK rising
0
MAX UNIT
ns
ns
These parameters are in addition to the general timings for SPI master modes (Table 6-56).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI1_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
Table 6-60. Additional (1) SPI1 Master Timings, 5-Pin Option (2) (3)
NO.
18
20
21
(1)
(2)
(3)
(4)
(5)
(6)
MIN
td(SPC_ENA)M
td(SPC_SCS)M
td(SCSL_ENAL)M
Max delay for slave to
deassert SPI1_ENA after
final SPI1_CLK edge to
ensure master does not
begin the next
transfer. (4)
Delay from final
SPI1_CLK edge to
master deasserting
SPI1_SCS (5) (6)
MAX UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
P+5
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0.5tc(SPC)M + P + 5
Polarity = 1, Phase = 0,
from SPI1_CLK rising
P+5
Polarity = 1, Phase = 1,
from SPI1_CLK rising
0.5tc(SPC)M + P + 5
ns
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M
Polarity = 1, Phase = 1,
from SPI1_CLK rising
0
Max delay for slave SPI to drive SPI1_ENA valid
after master asserts SPI1_SCS to delay the
master from beginning the next transfer,
ns
C2TDELAY + P
ns
These parameters are in addition to the general timings for SPI master modes (Table 6-57).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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19
MIN
Polarity = 0, Phase = 0,
to SPI1_CLK rising
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Table 6-60. Additional SPI1 Master Timings, 5-Pin Option (continued)
NO.
22
Delay from SPI1_SCS
active to first
SPI1_CLK (7) (8) (9)
td(SCS_SPC)M
ADVANCE INFORMATION
23
(7)
(8)
(9)
(10)
MIN
Delay from assertion of
SPI1_ENA low to first
SPI1_CLK edge. (10)
td(ENA_SPC)M
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P -3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 2P -3
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P -3
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -3
MAX UNIT
ns
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 3P + 5
Polarity = 1, Phase = 0,
to SPI1_CLK falling
3P + 5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 5
ns
If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
In the case where the master SPI is ready with new data before SPI1_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
Table 6-61. Additional (1) SPI1 Slave Timings, 4-Pin Enable Option (2) (3)
NO.
24
(1)
(2)
(3)
MIN
Delay from final
SPI1_CLK edge to slave
deasserting SPI1_ENA.
td(SPC_ENAH)S
MAX UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
1.5 P -3
2.5 P + 9.7
Polarity = 0, Phase = 1,
from SPI1_CLK falling
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 9.7
Polarity = 1, Phase = 0,
from SPI1_CLK rising
1.5 P -3
2.5 P + 9.7
Polarity = 1, Phase = 1,
from SPI1_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 9.7
ns
These parameters are in addition to the general timings for SPI slave modes (Table 6-57).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-62. Additional (1) SPI1 Slave Timings, 4-Pin Chip Select Option (2) (3)
NO.
25
26
MIN
td(SCSL_SPC)S
td(SPC_SCSH)S
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
Required delay from final
SPI1_CLK edge before
SPI1_SCS is deasserted.
MAX
P
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M + 0
Polarity = 1, Phase = 1,
from SPI1_CLK rising
0
UNIT
ns
ns
27
tena(SCSL_SOMI)S
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
P + 9.7
ns
28
tdis(SCSH_SOMI)S
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
P + 9.7
ns
(1)
(2)
(3)
136
These parameters are in addition to the general timings for SPI slave modes (Table 6-57).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Table 6-63. Additional (1) SPI1 Slave Timings, 5-Pin Option (2) (3)
25
26
td(SCSL_SPC)S
td(SPC_SCSH)S
Required delay from final
SPI1_CLK edge before
SPI1_SCS is deasserted.
MAX
P
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + 0
Polarity = 0, Phase = 1,
from SPI1_CLK falling
0
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M + 0
Polarity = 1, Phase = 1,
from SPI1_CLK rising
0
UNIT
ns
ns
27
tena(SCSL_SOMI)S
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
P + 9.7
ns
28
tdis(SCSH_SOMI)S
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
P + 9.7
ns
29
tena(SCSL_ENA)S
Delay from master deasserting SPI1_SCS to slave driving
SPI1_ENA valid
9.7
ns
30
(1)
(2)
(3)
(4)
MIN
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
tdis(SPC_ENA)S
Delay from final clock receive
edge on SPI1_CLK to slave
3-stating or driving high
SPI1_ENA. (4)
Polarity = 0, Phase = 0,
from SPI1_CLK falling
2.5 P + 9.7
Polarity = 0, Phase = 1,
from SPI1_CLK rising
2.5 P + 9.7
Polarity = 1, Phase = 0,
from SPI1_CLK rising
2.5 P + 9.7
Polarity = 1, Phase = 1,
from SPI1_CLK falling
2.5 P + 9.7
ns
These parameters are in addition to the general timings for SPI slave modes (Table 6-57).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
tri-stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
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1
2
MASTER MODE
POLARITY = 0 PHASE = 0
3
SPIx_CLK
5
4
SPIx_SIMO
MO(0)
7
SPIx_SOMI
6
MO(1)
MO(n−1)
MO(n)
8
MI(0)
MI(1)
MI(n−1)
MI(n)
ADVANCE INFORMATION
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
6
5
SPIx_SIMO
MO(0)
7
SPIx_SOMI
MO(1)
MO(n−1)
MI(1)
MI(n−1)
MO(n)
8
MI(0)
MI(n)
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
5
SPIx_SIMO
6
MO(0)
7
SPIx_SOMI
MO(1)
MO(n−1)
MO(n)
8
MI(0)
MI(1)
MI(n−1)
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
5
4
SPIx_SIMO
MO(0)
7
SPIx_SOMI
MI(0)
6
MO(1)
MO(n−1)
MI(1)
MI(n−1)
MO(n)
8
MI(n)
Figure 6-39. SPI Timings—Master Mode
138
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9
12
10
SLAVE MODE
POLARITY = 0 PHASE = 0
11
SPIx_CLK
16
SI(0)
SI(1)
SI(n−1)
13
SPIx_SOMI
SO(0)
SI(n)
14
SO(1)
SO(n−1)
12
SO(n)
ADVANCE INFORMATION
15
SPIx_SIMO
SLAVE MODE
POLARITY = 0 PHASE = 1
SPIx_CLK
15
SPIx_SIMO
16
SI(0)
SI(1)
13
SPIx_SOMI
SO(0)
SI(n−1)
SI(n)
SO(n−1)
SO(n)
14
SO(1)
SLAVE MODE
POLARITY = 1 PHASE = 0
12
SPIx_CLK
15
SPIx_SIMO
16
SI(0)
SI(1)
SI(n−1)
13
SPIx_SOMI
SO(0)
SI(n)
14
SO(1)
SO(n−1)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 1
12
SPIx_CLK
15
16
SPIx_SIMO
SI(0)
SPIx_SOMI
SO(0)
SI(1)
13
SO(1)
SI(n−1)
SI(n)
14
SO(n−1)
SO(n)
Figure 6-40. SPI Timings—Slave Mode
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MASTER MODE 4 PIN WITH ENABLE
17
18
SPIx_CLK
SPIx_SIMO
MO(0)
SPIx_SOMI
MI(0)
MO(1)
MO(n−1)
MI(1)
MI(n−1)
MO(n)
MI(n)
SPIx_ENA
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
ADVANCE INFORMATION
SPIx_SIMO
MO(0)
SPIx_SOMI
MI(0)
MO(1)
MO(n−1)
MO(n)
MI(1)
MI(n−1)
MI(n)
SPIx_SCS
MASTER MODE 5 PIN
22
20
MO(1)
23
18
SPIx_CLK
SPIx_SIMO
MO(0)
MO(n−1)
MO(n)
SPIx_SOMI
21
SPIx_ENA
MI(0)
MI(1)
MI(n−1)
MI(n)
DESEL(A)
DESEL(A)
SPIx_SCS
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 6-41. SPI Timings—Master Mode (4-Pin and 5-Pin)
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SLAVE MODE 4 PIN WITH ENABLE
24
SPIx_CLK
SPIx_SOMI
SO(0)
SO(1)
SO(n−1)
SO(n)
SPIx_SIMO
SI(0)
SPIx_ENA
SI(1)
SI(n−1) SI(n)
SLAVE MODE 4 PIN WITH CHIP SELECT
26
25
SPIx_CLK
SPIx_SOMI
28
SO(n−1)
SO(0)
SO(1)
ADVANCE INFORMATION
27
SO(n)
SPIx_SIMO
SI(0)
SPIx_SCS
SI(1)
SI(n−1)
SI(n)
SLAVE MODE 5 PIN
26
30
25
SPIx_CLK
27
SPIx_SOMI
28
SO(1)
SO(0)
SO(n−1)
SO(n)
SPIx_SIMO
29
SPIx_ENA
DESEL(A)
SI(0)
SI(1)
SI(n−1)
SI(n)
DESEL(A)
SPIx_SCS
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 6-42. SPI Timings—Slave Mode (4-Pin and 5-Pin)
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6.17 Enhanced Capture (eCAP) Peripheral
The C6745/6747 device contains up to three enhanced capture (eCAP) modules. Figure 6-43 shows a
functional block diagram of a module. See the TMS320C6745/C6747 DSP Peripherals Overview
Reference Guide. – Literature Number SPRUFK9 for more details.
Uses for ECAP include:
• Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor triggers
• Period and duty cycle measurements of Pulse train signals
• Decoding current or voltage amplitude derived from cuty cycle encoded current/voltage sensors
ADVANCE INFORMATION
The ECAP module described in this specification includes the following features:
• 32 bit time base
• 4 event time-stamp registers (each 32 bits)
• Edge polarity selection for up to 4 sequenced time-stamp capture events
• Interrupt on either of the 4 events
• Single shot capture of up to 4 event time-stamps
• Continuous mode capture of time-stamps in a 4 deep circular buffer
• Absolute time-stamp capture
• Difference mode time-stamp capture
• All the above resources are dedicated to a single input pin
The eCAP modules are clocked at the SYSCLK2 rate.
The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP
modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK,
ECAP3ENCLK, and ECAP4EN CLK are set to low, indicating that the peripheral clock is off.
142
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SYNCIn
SYNCOut
CTRPHS
(phase register−32 bit)
TSCTR
(counter−32 bit)
APWM mode
OVF
RST
CTR_OVF
CTR [0−31]
Delta−mode
PWM
compare
logic
PRD [0−31]
CMP [0−31]
32
CTR=PRD
CTR [0−31]
CTR=CMP
32
LD1
CAP1
(APRD active)
APRD
shadow
32
32
Polarity
select
LD
32
CMP [0−31]
CAP2
(ACMP active)
32
LD
LD2
Polarity
select
Event
qualifier
ACMP
shadow
32
CAP3
(APRD shadow)
LD
32
CAP4
(ACMP shadow)
LD
eCAPx
Event
Pre-scale
Polarity
select
LD3
LD4
Polarity
select
4
Capture events
4
CEVT[1:4]
to Interrupt
Controller
Interrupt
Trigger
and
Flag
control
CTR_OVF
Continuous /
Oneshot
Capture Control
CTR=PRD
CTR=CMP
Figure 6-43. eCAP Functional Block Diagram
Table 6-64 is the list of the ECAP registers.
Table 6-64. ECAPx Configuration Registers
ECAP0
BYTE ADDRESS
ECAP1
BYTE ADDRESS
ECAP2
BYTE ADDRESS
REGISTER NAME
0x01F0 6000
0x01F0 7000
0x01F0 8000
TSCTR
0x01F0 6004
0x01F0 7004
0x01F0 8004
CTRPHS
0x01F0 6008
0x01F0 7008
0x01F0 8008
CAP1
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DESCRIPTION
Time-Stamp Counter
Counter Phase Offset Value Register
Capture 1 Register
Peripheral Information and Electrical Specifications
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ADVANCE INFORMATION
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MODE SELECT
PRD [0−31]
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Table 6-64. ECAPx Configuration Registers (continued)
ECAP0
BYTE ADDRESS
ECAP1
BYTE ADDRESS
ECAP2
BYTE ADDRESS
REGISTER NAME
0x01F0 600C
0x01F0 700C
0x01F0 800C
CAP2
Capture 2 Register
0x01F0 6010
0x01F0 7010
0x01F0 8010
CAP3
Capture 3 Register
0x01F0 6014
0x01F0 7014
0x01F0 8014
CAP4
Capture 4 Register
0x01F0 6028
0x01F0 7028
0x01F0 8028
ECCTL1
Capture Control Register 1
DESCRIPTION
0x01F0 602A
0x01F0 702A
0x01F0 802A
ECCTL2
Capture Control Register 2
0x01F0 602C
0x01F0 702C
0x01F0 802C
ECEINT
Capture Interrupt Enable Register
0x01F0 602E
0x01F0 702E
0x01F0 802E
ECFLG
Capture Interrupt Flag Register
0x01F0 6030
0x01F0 7030
0x01F0 8030
ECCLR
Capture Interrupt Clear Register
ADVANCE INFORMATION
0x01F0 6032
0x01F0 7032
0x01F0 8032
ECFRC
Capture Interrupt Force Register
0x01F0 605C
0x01F0 705C
0x01F0 805C
REVID
Revision ID
Table 6-65 shows the eCAP timing requirement and Table 6-66 shows the eCAP switching characteristics.
Table 6-65. Enhanced Capture (eCAP) Timing Requirement
TEST CONDITIONS
tw(CAP)
Capture input pulse width
MIN
MAX
UNIT
Asynchronous
2tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
With input qualifier
Table 6-66. eCAP Switching Characteristics
PARAMETER
tw(APWM)
144
Pulse duration, APWMx output high/low
Peripheral Information and Electrical Specifications
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
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6.18 Enhanced Quadrature Encoder (eQEP) Peripheral
The C6745/6747 device contains up to two enhanced quadrature encoder (eQEP) modules. See the
TMS320C6745/C6747 DSP Peripherals Overview Reference Guide. – Literature Number SPRUFK9. for
more details.
System
control registers
To CPU
EQEPxENCLK
ADVANCE INFORMATION
Data bus
SYSCLK2
QCPRD
QCTMR
QCAPCTL
16
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
Registers
used by
multiple units
QUTMR
QWDTMR
QUPRD
QWDPRD
32
16
QEPCTL
QEPSTS
UTIME
Interrupt Controller
QFLG
UTOUT
QWDOG
QDECCTL
16
WDTOUT
EQEPxINT
EQEPxAIN
QCLK
16
QI
Position counter/
control unit
(PCCU)
QPOSLAT
QS
PHE
QPOSSLAT
PCSOUT
QPOSILAT
EQEPxIIN
Quadrature
decoder
(QDU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
32
32
QPOSCNT
QPOSCMP
EQEPxA/XCLK
EQEPxBIN
QDIR
EQEPxB/XDIR
GPIO
MUX
EQEPxI
EQEPxS
16
QEINT
QPOSINIT
QFRC
QPOSMAX
QCLR
QPOSCTL
Enhanced QEP (eQEP) peripheral
Figure 6-44. eQEP Functional Block Diagram
Table 6-67 is the list of the EQEP registers.
Table 6-68 shows the eQEP timing requirement and Table 6-69 shows the eQEP switching
characteristics.
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Table 6-67. EQEP Registers
EQEP0
BYTE ADDRESS
EQEP1
BYTE ADDRESS
0x01F0 9000
0x01F0 9004
ADVANCE INFORMATION
REGISTER NAME
DESCRIPTION
0x01F0 A000
QPOSCNT
eQEP Position Counter
0x01F0 A004
QPOSINIT
eQEP Initialization Position Count
0x01F0 9008
0x01F0 A008
QPOSMAX
eQEP Maximum Position Count
0x01F0 900C
0x01F0 A00C
QPOSCMP
eQEP Position-compare
0x01F0 9010
0x01F0 A010
QPOSILAT
eQEP Index Position Latch
0x01F0 9014
0x01F0 A014
QPOSSLAT
eQEP Strobe Position Latch
0x01F0 9018
0x01F0 A018
QPOSLAT
eQEP Position Latch
0x01F0 901C
0x01F0 A01C
QUTMR
eQEP Unit Timer
0x01F0 9020
0x01F0 A020
QUPRD
eQEP Unit Period Register
0x01F0 9024
0x01F0 A024
QWDTMR
eQEP Watchdog Timer
0x01F0 9026
0x01F0 A026
QWDPRD
eQEP Watchdog Period Register
0x01F0 9028
0x01F0 A028
QDECCTL
eQEP Decoder Control Register
0x01F0 902A
0x01F0 A02A
QEPCTL
eQEP Control Register
0x01F0 902C
0x01F0 A02C
QCAPCTL
eQEP Capture Control Register
0x01F0 902E
0x01F0 A02E
QPOSCTL
eQEP Position-compare Control Register
0x01F0 9030
0x01F0 A030
QEINT
eQEP Interrupt Enable Register
0x01F0 9032
0x01F0 A032
QFLG
eQEP Interrupt Flag Register
0x01F0 9034
0x01F0 A034
QCLR
eQEP Interrupt Clear Register
0x01F0 9036
0x01F0 A036
QFRC
eQEP Interrupt Force Register
0x01F0 9038
0x01F0 A038
QEPSTS
eQEP Status Register
0x01F0 903A
0x01F0 A03A
QCTMR
eQEP Capture Timer
0x01F0 903C
0x01F0 A03C
QCPRD
eQEP Capture Period Register
0x01F0 903E
0x01F0 A03E
QCTMRLAT
eQEP Capture Timer Latch
0x01F0 9040
0x01F0 A040
QCPRDLAT
eQEP Capture Period Latch
0x01F0 905C
0x01F0 A05C
REVID
eQEP Revision ID
Table 6-68. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
TEST CONDITIONS
tw(QEPP)
QEP input period
tw(INDEXH)
QEP Index Input High time
tw(INDEXL)
QEP Index Input Low time
With input qualifier
QEP Strobe High time
tw(STROBL)
QEP Strobe Input Low time
2(1tc(SCO) + tw(IQSW))
cycles
2tc(SCO)
cycles
2tc(SCO) +tw(IQSW)
cycles
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
cycles
Asynchronous/synchronous
With input qualifier
2tc(SCO)
cycles
2tc(SCO) + tw(IQSW)
cycles
2tc(SCO)
cycles
2tc(SCO) +tw(IQSW)
cycles
Asynchronous/synchronous
With input qualifier
UNIT
cycles
Asynchronous/synchronous
With input qualifier
MAX
2tc(SCO)
Asynchronous/synchronous
With input qualifier
tw(STROBH)
MIN
Asynchronous/synchronous
Table 6-69. eQEP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
4tc(SCO)
cycles
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
6tc(SCO)
cycles
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6.19 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
The C6745/6747 device contains up to three enhanced PWM Modules (eHRPWM). Figure 6-45 shows a
block diagram of multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the
eHRPWM. See the TMS320C6745/C6747 DSP Peripherals Overview Reference Guide. – Literature
Number SPRUFK9 for more details.
EPWMSYNCI
EPWM0SYNCI
EPWM0A
ePWM0 module
ADVANCE INFORMATION
EPWM0INT
EPWM0B
TZ
EPWM0SYNCO
EPWM1SYNCI
EPWM1INT
EPWM1A
ePWM1 module
EPWM1B
GPIO
MUX
EPWM1SYNCO
TZ
EPWM2SYNCI
EPWM2INT
Interrupt
Controllers
EPWM2A
ePWM2 module
EPWM2SYNCO
To eCAP0
module
(sync in)
EPWM2B
TZ
EPWMSYNCO
Peripheral Bus
Figure 6-45. Multiple PWM Modules in a C6745/6747 System
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Time−base (TB)
Sync
in/out
select
Mux
CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
CTR=PRD
EPWMSYNCO
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMSYNCI
Counter
up/down
(16 bit)
CTR=ZERO
CTR_Dir
ADVANCE INFORMATION
TBCNT
active (16)
TBPHSHR (8)
16
8
TBPHS active (24)
CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
control
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
16
TBCTL[SWFSYNC]
(software forced sync)
Action
qualifier
(AQ)
8
Event
trigger
and
interrupt
(ET)
EPWMxINT
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMxA
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
16
PWM
chopper
(PC)
Trip
zone
(TZ)
EPWMB
EPWMxB
CMPB active (16)
EPWMxTZINT
CMPB shadow (16)
CTR = ZERO
TZ
Figure 6-46. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections
Table 6-70. eHRPWM Module Control and Status Registers Grouped by Submodule
eHRPWM0
BYTE ADDRESS
eHRPWM1
BYTE ADDRESS
eHRPWM2
BYTE ADDRESS
0x01F0 0000
0x01F0 2000
0x01F0 4000
TBCTL
1
No
Time-Base Control Register
0x01F0 0002
0x01F0 2002
0x01F0 4002
TBSTS
1
No
Time-Base Status Register
0x01F0 0004
0x01F0 2004
0x01F0 4004
TBPHSHR
1
No
Extension for HRPWM Phase Register
0x01F0 0006
0x01F0 2006
0x01F0 4006
TBPHS
1
No
Time-Base Phase Register
0x01F0 0008
0x01F0 2008
0x01F0 4008
TBCNT
1
No
Time-Base Counter Register
0x01F0 000A
0x01F0 200A
0x01F0 400A
TBPRD
1
Yes
Time-Base Period Register
Acronym
Size
(×16)
Shad
ow
Register Description
Time-Base Submodule Registers
(1)
Counter-Compare Submodule Registers
0x01F0 000E
0x01F0 200E
0x01F0 400E
CMPCTL
1
No
Counter-Compare Control Register
0x01F0 0010
0x01F0 2010
0x01F0 4010
CMPAHR
1
No
Extension for HRPWM
Counter-Compare A Register
0x01F0 0012
0x01F0 2012
0x01F0 4012
CMPA
1
Yes
Counter-Compare A Register
0x01F0 0014
0x01F0 2014
0x01F0 4014
CMPB
1
Yes
Counter-Compare B Register
(1)
148
(1)
These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
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Table 6-70. eHRPWM Module Control and Status Registers Grouped by Submodule (continued)
eHRPWM0
BYTE ADDRESS
eHRPWM1
BYTE ADDRESS
eHRPWM2
BYTE ADDRESS
Size
(×16)
Acronym
Shad
ow
Register Description
Action-Qualifier Submodule Registers
0x01F0 0016
0x01F0 2016
0x01F0 4016
AQCTLA
1
No
Action-Qualifier Control Register for
Output A (eHRPWMxA)
0x01F0 0018
0x01F0 2018
0x01F0 4018
AQCTLB
1
No
Action-Qualifier Control Register for
Output B (eHRPWMxB)
0x01F0 001A
0x01F0 201A
0x01F0 401A
AQSFRC
1
No
Action-Qualifier Software Force Register
0x01F0 001C
0x01F0 201C
0x01F0 401C
AQCSFRC
1
Yes
Action-Qualifier Continuous S/W Force
Register Set
0x01F0 001E
0x01F0 201E
0x01F0 401E
DBCTL
1
No
Dead-Band Generator Control Register
0x01F0 0020
0x01F0 2020
0x01F0 4020
DBRED
1
No
Dead-Band Generator Rising Edge
Delay Count Register
0x01F0 0022
0x01F0 2022
0x01F0 4022
DBFED
1
No
Dead-Band Generator Falling Edge
Delay Count Register
PWM-Chopper Submodule Registers
0x01F0 003C
0x01F0 203C
0x01F0 403C
PCCTL
1
No
PWM-Chopper Control Register
Trip-Zone Submodule Registers
0x01F0 0024
0x01F0 2024
0x01F0 4024
TZSEL
1
No
Trip-Zone Select Register
0x01F0 0028
0x01F0 2028
0x01F0 4028
TZCTL
1
No
Trip-Zone Control Register
0x01F0 002A
0x01F0 202A
0x01F0 402A
TZEINT
1
No
Trip-Zone Enable Interrupt Register
0x01F0 002C
0x01F0 202C
0x01F0 402C
TZFLG
1
No
Trip-Zone Flag Register
0x01F0 002E
0x01F0 202E
0x01F0 402E
TZCLR
1
No
Trip-Zone Clear Register
0x01F0 0030
0x01F0 2030
0x01F0 4030
TZFRC
1
No
Trip-Zone Force Register
Event-Trigger Submodule Registers
0x01F0 0032
0x01F0 2032
0x01F0 4032
ETSEL
1
No
Event-Trigger Selection Register
0x01F0 0034
0x01F0 2034
0x01F0 4034
ETPS
1
No
Event-Trigger Pre-Scale Register
0x01F0 0036
0x01F0 2036
0x01F0 4036
ETFLG
1
No
Event-Trigger Flag Register
0x01F0 0038
0x01F0 2038
0x01F0 4038
ETCLR
1
No
Event-Trigger Clear Register
0x01F0 003A
0x01F0 203A
0x01F0 403A
ETFRC
1
No
Event-Trigger Force Register
0x01F0 1020
0x01F0 3020
0x01F0 5020
High-Resolution PWM (HRPWM) Submodule Registers
HRCNFG
1
No
HRPWM Configuration Register
(1)
6.19.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
PWM refers to PWM outputs on eHRPWM1-6. Table 6-71 shows the PWM timing requirements and
Table 6-72, switching characteristics.
Table 6-71. eHRPWM Timing Requirements
PARAMETER
tw(SYNCIN)
Sync input pulse width
TEST CONDITIONS
MIN
MAX
UNIT
Asynchronous
2tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
With input qualifier
Table 6-72. eHRPWM Switching Characteristics
PARAMETER
tw(PWM)
Pulse duration, PWMx output high/low
tw(SYNCOUT)
Sync output pulse width
td(PWM)TZA
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
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TEST CONDITIONS
MIN
MAX
UNIT
20
ns
8tc(SCO)
no pin load
cycles
25
Peripheral Information and Electrical Specifications
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149
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Table 6-72. eHRPWM Switching Characteristics (continued)
PARAMETER
td(TZ-PWM)HZ
TEST CONDITIONS
MIN
MAX
Delay time, trip input active to PWM Hi-Z
20
UNIT
ns
6.19.2 Trip-Zone Input Timing
tw(TZ)
TZ
td(TZ-PWM)HZ
ADVANCE INFORMATION
PWM(A)
A.
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-47. PWM Hi-Z Characteristics
Table 6-73. Trip-Zone input Timing Requirements
PARAMETER
tw(TZ)
MIN
Pulse duration, TZx input low
MAX
UNIT
Asynchronous
1tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
With input qualifier
Table 6-74 shows the high-resolution PWM switching characteristics.
Table 6-74. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
PARAMETER
Micro Edge Positioning (MEP) step size (1)
(1)
150
MIN
TYP
MAX
UNIT
150
310
ps
Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
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6.20 LCD Controller
Table 6-75 lists the LCD Controller registers
Address Offset
Acronym
Register Description
0x01E1 3000
REVID
LCD Revision Identification Register
0x01E1 3004
LCD_CTRL
LCD Control Register
0x01E1 3008
LCD_STAT
LCD Status Register
0x01E1 300C
LIDD_CTRL
LCD LIDD Control Register
0x01E1 3010
LIDD_CS0_CONF
LCD LIDD CS0 Configuration Register
0x01E1 3014
LIDD_CS0_ADDR
LCD LIDD CS0 Address Read/Write Register
0x01E1 3018
LIDD_CS0_DATA
LCD LIDD CS0 Data Read/Write Register
0x01E1 301C
LIDD_CS1_CONF
LCD LIDD CS1 Configuration Register
0x01E1 3020
LIDD_CS1_ADDR
LCD LIDD CS1 Address Read/Write Register
0x01E1 3024
LIDD_CS1_DATA
LCD LIDD CS1 Data Read/Write Register
0x01E1 3028
RASTER_CTRL
LCD Raster Control Register
0x01E1 302C
RASTER_TIMING_0
LCD Raster Timing 0 Register
0x01E1 3030
RASTER_TIMING_1
LCD Raster Timing 1 Register
0x01E1 3034
RASTER_TIMING_2
LCD Raster Timing 2 Register
0x01E1 3038
RASTER_SUBPANEL
LCD Raster Subpanel Display Register
0x01E1 3040
LCDDMA_CTRL
LCD DMA Control Register
0x01E1 3044
LCDDMA_FB0_BASE
LCD DMA Frame Buffer 0 Base Address Register
0x01E1 3048
LCDDMA_FB0_CEILING
LCD DMA Frame Buffer 0 Ceiling Address Register
0x01E1 304C
LCDDMA_FB1_BASE
LCD DMA Frame Buffer 1 Base Address Register
0x01E1 3050
LCDDMA_FB1_CEILING
LCD DMA Frame Buffer 1 Ceiling Address Register
ADVANCE INFORMATION
Table 6-75. LCD Controller (LCDC) Registers
6.20.1 LCD Interface Display Driver (LIDD Mode)
Table 6-76. LCD LIDD Mode Timing Requirements
NO
PARAMETER
16
tsu(LCD_D)
Setup time, LCD_D[15:0] valid
before LCD_CLK (SYSCLK2) ↑
17
th(LCD_D)
Hold time, LCD_D[15:0] valid after
LCD_CLK (SYSCLK2) ↑
MIN
MAX
UNIT
7
ns
0
ns
Table 6-77. LCD LIDD Mode Timing Characteristics
NO
PARAMETER
MIN
MAX
UNIT
0
7
ns
4
td(LCD_D_V)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_D[15:0] valid (write)
5
td(LCD_D_I)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_D[15:0] invalid (write)
0
7
ns
6
td(LCD_E_A)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_AC_ENB_CS↓
0
7
ns
7
td(LCD_E_I)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_AC_ENB_CS↑
0
7
ns
8
td(LCD_A_A)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_VSYNC↓
0
7
ns
9
td(LCD_A_I)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_VSYNC↑
0
7
ns
10
td(LCD_W_A)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_HSYNC↓
0
7
ns
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Table 6-77. LCD LIDD Mode Timing Characteristics (continued)
NO
PARAMETER
MIN
MAX
UNIT
0
7
ns
ADVANCE INFORMATION
11
td(LCD_W_I)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_HSYNC↑
12
td(LCD_STRB_A)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_PCLK↑
0
7
ns
13
td(LCD_STRB_I)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_PCLK↓
0
7
ns
14
td(LCD_D_Z)
Delay time, LCD_CLK (SYSCLK2) ↑
to LCD_D[15:0] in 3-state
0
7
ns
15
td(Z_LCD_D)
Delay time, LCD_CLK (SYSCLK2) ↑
to 15 td(Z_LCD_D) 3-state)
LCD_D[15:0] (valid from 3-state)
0
7
ns
1
W_SU
(0 to 31)
2
3
LCD_CLK
(SYSCLK2)
CS_DELAY
(0 to 3)
W_STROBE
(1 to 63)
R_SU
(0 to 31)
4
R_HOLD
(1 to 15)
R_STROBE
(1 to 63)
W_HOLD
(1 to 15)
5
14
17
16
LCD_D[15:0]
CS_DELAY
(0 to 3)
15
Write Data
Data[7:0]
Read Status
LCD_PCLK
Not Used
8
9
LCD_VSYNC
RS
10
11
LCD_HSYNC
R/W
12
12
13
13
E0
E1
LCD_AC_ENB_CS
Figure 6-48. Character Display HD44780 Write
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W_HOLD
(1–15)
R_SU
(0–31)
1
2
R_STROBE
R_HOLD
CS_DELAY
(1–63)
(1–5)
(0−3)
(0–31)
W_SU
17
15
4
W_STROBE
CS_DELAY
(1–63)
(0 − 3)
3
Not
Used
LCD_CLK
(SYSCLK2)
16
LCD_D[7:0]
5
Data[7:0]
Write Instruction
ADVANCE INFORMATION
14
Read
Data
LCD_PCLK
Not
Used
8
9
RS
LCD_VSYNC
10
11
LCD_HSYNC
R/W
12
12
13
13
LCD_AC_ENB_CS
E0
E1
Figure 6-49. Character Display HD44780 Read
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W_HOLD
(1−15)
W_HOLD
(1−15)
1
2
W_SU
W_STROBE
CS_DELAY
W_SU
W_STROBE
(0−31)
(1−63)
(0−3)
(0−31)
(1−63)
CS_DELAY
(0−3)
3
Clock
LCD_CLK
(SYSCLK2)
4
LCD_D[15:0]
5
5
4
Write Address
Write Data
ADVANCE INFORMATION
7
6
Data[15:0]
6
7
LCD_AC_ENB_CS
(async mode)
CS0
CS1
9
8
A0
LCD_VSYNC
10
11
11
10
R/W
LCD_HSYNC
12
13
12
13
E
LCD_PCLK
Figure 6-50. Micro-Interface Graphic Display 6800 Write
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W_HOLD
(1−15)
1
2
W_SU
W_STROBE
(0−31)
(1−63)
R_SU
(0−31)
CS_DELAY
R_STROBE
R_HOLD
CS_DELAY
(1−15)
(0−3)
(1−63
(0−3)
3
Clock
LCD_CLK
(SYSCLK2)
4
14
16
17
15
Write Address
Data[15:0]
6
7
Read
Data
6
LCD_AC_ENB_CS
(async mode)
ADVANCE INFORMATION
LCD_D[15:0]
5
7
CS0
CS1
9
8
LCD_VSYNC
A0
11
10
LCD_HSYNC
R/W
12
13
12
13
LCD_PCLK
E
Figure 6-51. Micro-Interface Graphic Display 6800 Read
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R_SU
(0−31)
R_SU
(0−31)
R_STROBE R_HOLD CS_DELAY
R_STROBE R_HOLD CS_DELAY
1
2
(1−63)
3
(1−15)
(0−3)
(1−63)
(1−15)
(0−3)
Clock
LCD_CLK
(SYSCLK2)
14
16
17
15
14
17
16
15
LCD_D[15:0]
Data[15:0]
ADVANCE INFORMATION
Read
Data
6
LCD_AC_ENB_CS
(async mode)
7
Read
Status
6
7
CS0
CS1
8
9
LCD_VSYNC
A0
LCD_HSYNC
R/W
12
13
12
13
E
LCD_PCLK
Figure 6-52. Micro-Interface Graphic Display 6800 Status
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W_HOLD
(1−15)
W_HOLD
(1−15)
1
2
W_SU
W_STROBE
CS_DELAY
W_SU
W_STROBE
CS_DELAY
(0−31)
3
(1−63)
(0−3)
(0−31)
(1−63)
(0 − 3)
Clock
LCD_CLK
(SYSCLK2)
LCD_D[15:0]
LCD_AC_ENB_CS
(async mode)
5
4
Write Address
5
DATA[15:0]
Write Data
7
6
6
7
CS0
CS1
8
9
LCD_VSYNC
A0
10
11
10
11
LCD_HSYNC
WR
RD
LCD_PCLK
Figure 6-53. Micro-Interface Graphic Display 8080 Write
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W_HOLD
(1−15)
W_SU
W_STROBE
R_SU
(0−31)
CS_DELAY
R_STROBE
R_HOLD
CS_DELAY
1
2
3
(0−31)
(1−63)
(0−3)
(1−63)
(1−15)
16
17
(0−3)
Clock
LCD_CLK
(SYSCLK2)
4
LCD_D[15:0]
5
14
15
Data[15:0]
Write Address
ADVANCE INFORMATION
6
7
LCD_AC_ENB_CS
(async mode)
6
Read
Data
7
CS0
CS1
9
8
LCD_VSYNC
A0
10
11
WR
LCD_HSYNC
12
13
RD
LCD_PCLK
Figure 6-54. Micro-Interface Graphic Display 8080 Read
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R_SU
(0−31)
R_SU
(0−31)
R_STROBE
1
2
(1−63)
R_HOLD
CS_DELAY
(1−15)
(0−3)
R_STROBE R_HOLD
(1−63)
CS_DELAY
(1−15)
(0−3)
3
Clock
LCD_CLK
(SYSCLK2)
14
16
17
15
14
16
17
15
Data[15:0]
LCD_D[15:0]
Read Data
6
ADVANCE INFORMATION
Read Status
7
6
7
LCD_AC_ENB_CS
CS0
CS1
8
9
A0
LCD_VSYNC
WR
LCD_HSYNC
12
13
12
13
RD
LCD_PCLK
Figure 6-55. Micro-Interface Graphic Display 8080 Status
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6.20.2 LCD Raster Mode
Table 6-78. LCD Raster Mode Timing
See Figure 6-56 through Figure 6-59
NO.
ADVANCE INFORMATION
(1)
PARAMETER
fclock(PIXEL_CLK)
Clock frequency, pixel clock
1
tc(PIXEL_CLK)
Cycle time, pixel clock
2
tw(PIXEL_CLK_H)
3
4
MIN
MAX
F/2
UNIT
(1)
MHz
23.81
ns
Pulse duration, pixel clock high
10
ns
tw(PIXEL_CLK_L)
Pulse duration, pixel clock low
10
td(LCD_D_V)
Delay time, LCD_PCLK↑ to LCD_D[15:0] valid (write)
0
12
ns
5
td(LCD_D_IV)
Delay time, LCD_PCLK↑ to LCD_D[15:0] invalid (write)
0
12
ns
6
td(LCD_AC_ENB_CS_A)
Delay time, LCD_PCLK↓ to LCD_AC_ENB_CS↑
0
12
ns
7
td(LCD_AC_ENB_CS_I)
Delay time, LCD_PCLK↓ to LCD_AC_ENB_CS↓
0
12
ns
8
td(LCD_VSYNC_A)
Delay time, LCD_PCLK↓ to LCD_VSYNC↑
0
12
ns
9
td(LCD_VSYNC_I)
Delay time, LCD_PCLK↓ to LCD_VSYNC↓
0
12
ns
10
td(LCD_HSYNC_A)
Delay time, LCD_PCLK↑ to LCD_HSYNC↑
0
12
ns
11
td(LCD_HSYNC_I)
Delay time, LCD_PCLK↑ to LCD_HSYNC↓
0
12
ns
ns
F = frequency of LCD_PCLK in ns
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
• Vertical front porch (VFP)
• Vertical sync pulse width (VSW)
• Vertical back porch (VBP)
• Lines per panel (LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
• Horizontal front porch (HFP)
• Horizontal sync pulse width (HSW)
• Horizontal back porch (HBP)
• Pixels per panel (PPL)
LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
• AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 6-56. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
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Data Pixels (From 1 to P)
1, 1
2, 1
1, 2
2, 2
P−2,
1
3, 1
P−1,
1
P, 1
P−1,
2
P, 2
ADVANCE INFORMATION
P, 3
Data Lines (From 1 to L)
1, 3
LCD
P,
L−2
1,
L−2
1,
L−1
2,
L−1
1, L
2, L
P−1,
L−1
P−2,
L
3, L
P−1,
L
P,
L−1
P, L
Figure 6-56. LCD Raster-Mode Display Format
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Frame Time ~ 70Hz
Active TFT
VBP
(0 to 255)
VSW
(1 to 64)
Line
Time
LPP
VFP
(1 to 1024)
(0 to 255)
VSW
(1 to 64)
Hsync
LCD_HSYNC
LCD_VSYNC
Vsync
ADVANCE INFORMATION
Data
LCD_D[15:0]
1, 1
P, 1
1, L−1
P, L−1
1, 2
P, 2
1, L
P, L
Enable
LCD_AC_ENB_CS
ACB
ACB
(0 to 255)
(0 to 255)
10
11
Hsync
LCD_HSYNC
CLK
LCD_PCLK
Data
LCD_D[15:0]
1, 1
2, 1
1, 2
P, 1
PLL
HFP
16 y (1 to 1024)
(1 to 256)
2, 2
HSW
HBP
PLL
(1 to 64)
(1 to 256)
16 y (1 to 1024)
Line 1
P, 2
Line 2
Figure 6-57. LCD Raster-Mode Active
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Frame Time ~ 70Hz
VBP = 0
VFP = 0
Passive STN VSW = 1
(1 to 64)
VBP = 0
VFP = 0
VSW = 1
(1 to 64)
LPP
(1 to 1024)
Line
LCD_HSYNC
LP
LCD_VSYNC
FP
ADVANCE INFORMATION
Time
1, L
Data
LCD_D[7:0]
1, 1:
P, 1
1, L:
P, L
1, 2:
P, 2
1, 3:
P, 3
1, 4:
P, 4
1, 5:
P, 5
1, L
P, L
1, 6:
P, 6
1, L−1
P, L−1
1, L−4
P, L−4
1, 1
P, 1
1, 2
P, 2
1, L−3 1, L−2 1, L−1
P, L−3 P, L−2 P, L−1
M
LCD_AC_ENB_CS
ACB
ACB
(0 to 255)
(0 to 255)
11
10
LCD_HSYNC
LP
LCD_PCLK
CP
Data
LCD_D[7:0]
1, 5
2, 5
1, 6
P, 5
PPL
16 y (1 to 1024)
2, 6
HFP
HSW
HBP
PPL
(1 to 256)
(1 to 64)
(1 to 256)
16 y (1 to 2024)
P, 6
Line 6
Line 5
Figure 6-58. LCD Raster-Mode Passive
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6
LCD_AC_ENB_CS
8
LCD_VSYNC
10
11
LCD_HSYNC
ADVANCE INFORMATION
1
2
3
LCD_PCLK
(passive mode)
5
4
LCD_D[7:0]
(passive mode)
1, L
2, L
P, L
1, 1
2, 1
P, 1
1
2
3
LCD_PCLK
(active mode)
4
LCD_D[15:0]
(active mode)
VBP = 0
VFP = 0
VSW = 1
1, L
2, L
PPL
16 y (1 to 1024)
5
P, L
HFP
(1 to 256
Line L
HSW
(1 to 64)
HBP
(1 to 256)
PPL
16 y (1 to 256)
Line 1 (Passive Only)
Figure 6-59. LCD Raster-Mode Control Signal Activation
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6
LCD_AC_ENB_CS
8
LCD_VSYNC
11
10
ADVANCE INFORMATION
LCD_HSYNC
1
2
3
LCD_PCLK
(passive mode)
5
4
LCD_D[7:0]
(passive mode)
1, L
2, L
P, L
1, 1
2, 1
P, 1
1
2
3
LCD_PCLK
(active mode)
4
LCD_D[15:0]
(active mode)
1, L
VBP = 0
VFP = 0
VSW = 1
2, L
PPL
16 y (1 to 1024)
Line L
5
P, L
HFP
(1 to 256
HSW
(1 to 64)
HBP
(1 to 256)
PPL
16 y (1 to 256)
Line 1 (Passive Only)
Figure 6-60. LCD Raster-Mode Control Signal Deactivation
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6.21 Timers
The timers support the following features:
• Configurable as single 64-bit timer or two 32-bit timers
• Period timeouts generate interrupts, DMA events or external pin events
• 8 32-bit compare registers
• Compare matches generate interrupt events
• Capture capability
• 64-bit Watchdog capability (Timer64P1 only)
Table 6-79 lists the timer registers.
ADVANCE INFORMATION
Table 6-79. Timer Registers
Timer64P 0
Timer64P 1
Acronym
0x01C2 0000
0x01C2 1000
REV
0x01C2 0004
0x01C2 1004
EMUMGT
Register Description
Revision Register
Emulation Management Register
0x01C2 0008
0x01C2 1008
GPINTGPEN
0x01C2 000C
0x01C2 100C
GPDATGPDIR
GPIO Interrupt and GPIO Enable Register
0x01C2 0010
0x01C2 1010
TIM12
Timer Counter Register 12
0x01C2 0014
0x01C2 1014
TIM34
Timer Counter Register 34
0x01C2 0018
0x01C2 1018
PRD12
Timer Period Register 12
0x01C2 001C
0x01C2 101C
PRD34
Timer Period Register 34
0x01C2 0020
0x01C2 1020
TCR
0x01C2 0024
0x01C2 1024
TGCR
0x01C2 0028
0x01C2 1028
WDTCR
0x01C2 0034
0x01C2 1034
REL12
Timer Reload Register 12
GPIO Data and GPIO Direction Register
Timer Control Register
Timer Global Control Register
Watchdog Timer Control Register
0x01C2 0038
0x01C2 1038
REL34
Timer Reload Register 34
0x01C2 003C
0x01C2 103C
CAP12
Timer Capture Register 12
0x01C2 0040
0x01C2 1040
CAP34
Timer Capture Register 34
0x01C2 0044
0x01C2 1044
INTCTLSTAT
0x01C2 0060
0x01C2 1060
CMP0
Compare Register 0
0x01C2 0064
0x01C2 1064
CMP1
Compare Register 1
Timer Interrupt Control and Status Register
0x01C2 0068
0x01C2 1068
CMP2
Compare Register 2
0x01C2 006C
0x01C2 106C
CMP3
Compare Register 3
0x01C2 0070
0x01C2 1070
CMP4
Compare Register 4
0x01C2 0074
0x01C2 1074
CMP5
Compare Register 5
0x01C2 0078
0x01C2 1078
CMP6
Compare Register 6
0x01C2 007C
0x01C2 107C
CMP7
Compare Register 7
6.21.1
Timer Electrical Data/Timing
Table 6-80. Timing Requirements for Timer Input (1) (2) (see Figure 6-61)
NO.
MIN
MAX
1
tc(TM64Px_IN12) Cycle time, TM64Px_IN12
2
tw(TINPH)
Pulse duration, TM64Px_IN12 high
0.45C
0.55C
ns
3
tw(TINPL)
Pulse duration, TM64Px_IN12 low
0.45C
0.55C
ns
4
tt(TM64Px_IN12)
Transition time, TM64Px_IN12
0.05C
ns
(1)
(2)
166
4P
UNIT
ns
P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
C = TM64P0_IN12 cycle time in ns. For example, when TM64Px_IN12 frequency is 27 MHz, use C = 37.037 ns
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1
2
3
4
4
TM64P0_IN12
Figure 6-61. Timer Timing
NO.
(1)
MIN
MAX
(1)
UNIT
5
tw(TOUTH)
Pulse duration, TM64P0_OUT12 high
4P
ns
6
tw(TOUTL)
Pulse duration, TM64P0_OUT12 low
4P
ns
P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
5
6
TM64P0_OUT12
Figure 6-62. Timer Timing
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Table 6-81. Switching Characteristics Over Recommended Operating Conditions for Timer Output
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6.22 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
6.22.1 I2C Device-Specific Information
Having two I2C modules on the C6745/6747 simplifies system architecture, since one module may be
used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to
communicate with other controllers in a system or to implement a user interface. Figure 6-63 is block
diagram of the C6745/6747 I2C Module.
ADVANCE INFORMATION
Each I2C port supports:
• Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
• Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
• Noise Filter to Remove Noise 50 ns or less
• Seven- and Ten-Bit Device Addressing Modes
• Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
• Events: DMA, Interrupt, or Polling
• General-Purpose I/O Capability if not used as I2C
Clock Prescaler
I2CPSCx
Control
Prescaler
Register
I2CCOARx
Own Address
Register
I2CSARx
Slave Address
Register
Bit Clock Generator
I2Cx_SCL
Noise
Filter
I2CCLKHx
Clock Divide
High Register
I2CCMDRx
Mode Register
I2CCLKLx
Clock Divide
Low Register
I2CEMDRx
Extended Mode
Register
I2CCNTx
Data Count
Register
I2CPID1
Peripheral ID
Register 1
I2CPID2
Peripheral ID
Register 2
Transmit
I2Cx_SDA
Noise
Filter
I2CXSRx
Transmit Shift
Register
I2CDXRx
Transmit Buffer
Interrupt/DMA
Receive
I2CIERx
I2CDRRx
Receive Buffer
I2CSTRx
I2CRSRx
Receive Shift
Register
I2CSRCx
I2CPFUNC
Pin Function
Register
I2CPDOUT
Interrupt Enable
Register
Interrupt Status
Register
Interrupt Source
Register
Peripheral
Configuration
Bus
Interrupt DMA
Requests
Control
I2CPDIR
I2CPDIN
Pin Direction
Register
Pin Data In
Register
I2CPDSET
I2CPDCLR
Pin Data Out
Register
Pin Data Set
Register
Pin Data Clear
Register
Figure 6-63. I2C Module Block Diagram
6.22.2 I2C Peripheral Registers Description(s)
Table 6-82 is the list of the I2C registers.
168
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I2C0
BYTE ADDRESS
I2C1
BYTE ADDRESS
Acronym
Register Description
0x01C2 2000
0x01C2 2004
0x01E2 8000
ICOAR
I2C Own Address Register
0x01E2 8004
ICIMR
I2C Interrupt Mask Register
0x01C2 2008
0x01E2 8008
ICSTR
I2C Interrupt Status Register
0x01C2 200C
0x01E2 800C
ICCLKL
I2C Clock Low-Time Divider Register
0x01C2 2010
0x01E2 8010
ICCLKH
I2C Clock High-Time Divider Register
0x01C2 2014
0x01E2 8014
ICCNT
I2C Data Count Register
0x01C2 2018
0x01E2 8018
ICDRR
I2C Data Receive Register
0x01C2 201C
0x01E2 801C
ICSAR
I2C Slave Address Register
0x01C2 2020
0x01E2 8020
ICDXR
I2C Data Transmit Register
0x01C2 2024
0x01E2 8024
ICMDR
I2C Mode Register
0x01C2 2028
0x01E2 8028
ICIVR
I2C Interrupt Vector Register
0x01C2 202C
0x01E2 802C
ICEMDR
I2C Extended Mode Register
0x01C2 2030
0x01E2 8030
ICPSC
I2C Prescaler Register
0x01C2 2034
0x01E2 8034
REVID1
I2C Revision Identification Register 1
0x01C2 2038
0x01E2 8038
REVID2
I2C Revision Identification Register 2
0x01C2 2048
0x01E2 8048
ICPFUNC
I2C Pin Function Register
0x01C2 204C
0x01E2 804C
ICPDIR
I2C Pin Direction Register
0x01C2 2050
0x01E2 8050
ICPDIN
I2C Pin Data In Register
0x01C2 2054
0x01E2 8054
ICPDOUT
I2C Pin Data Out Register
0x01C2 2058
0x01E2 8058
ICPDSET
I2C Pin Data Set Register
0x01C2 205C
0x01E2 805C
ICPDCLR
I2C Pin Data Clear Register
ADVANCE INFORMATION
Table 6-82. Inter-Integrated Circuit (I2C) Registers
6.22.3 I2C Electrical Data/Timing
6.22.3.1 Inter-Integrated Circuit (I2C) Timing
Table 6-83 and Table 6-84 assume testing over recommended operating conditions (see Figure 6-64 and
Figure 6-65).
Table 6-83. I2C Input Timing Requirements
NO.
MIN
1
tc(SCL)
Cycle time, I2Cx_SCL
2
tsu(SCLH-SDAL)
Setup time, I2Cx_SCL high before I2Cx_SDA
low
3
th(SCLL-SDAL)
Hold time, I2Cx_SCL low after I2Cx_SDA low
4
tw(SCLL)
Pulse duration, I2Cx_SCL low
5
tw(SCLH)
Pulse duration, I2Cx_SCL high
6
tsu(SDA-SCLH)
Setup time, I2Cx_SDA before I2Cx_SCL high
7
th(SDA-SCLL)
Hold time, I2Cx_SDA after I2Cx_SCL low
8
tw(SDAH)
Pulse duration, I2Cx_SDA high
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Standard Mode
10
Fast Mode
2.5
Standard Mode
4.7
Fast Mode
0.6
Standard Mode
0.6
Standard Mode
4.7
Fast Mode
1.3
µs
µs
µs
4
Fast Mode
0.6
Standard Mode
250
Fast Mode
100
Standard Mode
0
Fast Mode
0
Standard Mode
4.7
Fast Mode
1.3
UNIT
µs
4
Fast Mode
Standard Mode
MAX
µs
ns
0.9
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µs
µs
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Table 6-83. I2C Input Timing Requirements (continued)
NO.
MIN
ADVANCE INFORMATION
9
tr(SDA)
Rise time, I2Cx_SDA
10
tr(SCL)
Rise time, I2Cx_SCL
11
tf(SDA)
Fall time, I2Cx_SDA
12
tf(SCL)
Fall time, I2Cx_SCL
13
tsu(SCLH-SDAH)
Setup time, I2Cx_SCL high before I2Cx_SDA
high
14
tw(SP)
Pulse duration, spike (must be suppressed)
15
Cb
Capacitive load for each bus line
Standard Mode
Fast Mode
1000
20 + 0.1Cb
Standard Mode
Fast Mode
Standard Mode
20 + 0.1Cb
300
300
20 + 0.1Cb
300
4
Fast Mode
0.6
Standard Mode
N/A
Fast Mode
300
300
Standard Mode
Fast Mode
300
1000
20 + 0.1Cb
Standard Mode
Fast Mode
MAX
0
UNIT
ns
ns
ns
ns
µs
50
Standard Mode
400
Fast Mode
400
ns
pF
Table 6-84. I2C Switching Characteristics (1)
NO.
PARAMETER
16
tc(SCL)
Cycle time, I2Cx_SCL
17
tsu(SCLH-SDAL)
Setup time, I2Cx_SCL high before I2Cx_SDA
low
18
th(SDAL-SCLL)
Hold time, I2Cx_SCL low after I2Cx_SDA low
19
tw(SCLL)
Pulse duration, I2Cx_SCL low
20
tw(SCLH)
Pulse duration, I2Cx_SCL high
21
tsu(SDAV-SCLH)
Setup time, I2Cx_SDA valid before I2Cx_SCL
high
22
th(SCLL-SDAV)
Hold time, I2Cx_SDA valid after I2Cx_SCL low
23
tw(SDAH)
Pulse duration, I2Cx_SDA high
28
tsu(SCLH-SDAH)
Setup time, I2Cx_SCL high before I2Cx_SDA
high
(1)
170
MIN
Standard Mode
10
Fast Mode
2.5
Standard Mode
4.7
Fast Mode
0.6
Standard Mode
0.6
Standard Mode
4.7
Fast Mode
1.3
0.6
Standard Mode
250
Fast Mode
100
Standard Mode
0
Fast Mode
0
Standard Mode
4.7
Fast Mode
1.3
Standard Mode
Fast Mode
µs
µs
µs
4
Fast Mode
4
0.6
UNIT
µs
4
Fast Mode
Standard Mode
MAX
µs
ns
0.9
µs
µs
µs
I2C must be configured correctly to meet the timings in Table 6-84.
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11
9
I2Cx_SDA
6
8
14
4
13
5
10
I2Cx_SCL
12
3
2
7
3
Stop
Start
Repeated
Start
ADVANCE INFORMATION
1
Stop
Figure 6-64. I2C Receive Timings
26
24
I2Cx_SDA
21
23
19
28
20
25
I2Cx_SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 6-65. I2C Transmit Timings
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6.23
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Universal Asynchronous Receiver/Transmitter (UART)
ADVANCE INFORMATION
C6745/6747 has 3 UART peripherals. Each UART has the following features:
• 16-byte storage space for both the transmitter and receiver FIFOs
• 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
• DMA signaling capability for both received and transmitted data
• Programmable auto-rts and auto-cts for autoflow control
• Programmable Baud Rate up to 3MBaud
• Programmable Oversampling Options of x13 and x16
• Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
• Prioritized interrupts
• Programmable serial data formats
– 5, 6, 7, or 8-bit characters
– Even, odd, or no parity bit generation and detection
– 1, 1.5, or 2 stop bit generation
• False start bit detection
• Line break generation and detection
• Internal diagnostic capabilities
– Loopback controls for communications link fault isolation
– Break, parity, overrun, and framing error simulation
• Modem control functions (CTS, RTS) on UART0 only.
The UART registers are listed in Section 6.23.1
6.23.1 UART Peripheral Registers Description(s)
Table 6-85 is the list of UART registers.
Table 6-85. UART Registers
UART0
BYTE ADDRESS
UART1
BYTE ADDRESS
UART2
BYTE ADDRESS
0x01C4 2000
0x01D0 C000
0x01C4 2000
0x01D0 C000
0x01C4 2004
172
REGISTER NAME
Register Description
0x01D0 D000
RBR
Receiver Buffer Register (read only)
0x01D0 D000
THR
Transmitter Holding Register (write only)
0x01D0 C004
0x01D0 D004
IER
Interrupt Enable Register
0x01C4 2008
0x01D0 C008
0x01D0 D008
IIR
Interrupt Identification Register (read only)
0x01C4 2008
0x01D0 C008
0x01D0 D008
FCR
FIFO Control Register (write only)
0x01C4 200C
0x01D0 C00C
0x01D0 D00C
LCR
Line Control Register
0x01C4 2010
0x01D0 C010
0x01D0 D010
MCR
Modem Control Register
0x01C4 2014
0x01D0 C014
0x01D0 D014
LSR
Line Status Register
0x01C4 2018
0x01D0 C018
0x01D0 D018
MSR
Modem Status Register
0x01C4 201C
0x01D0 C01C
0x01D0 D01C
SCR
Scratchpad Register
0x01C4 2020
0x01D0 C020
0x01D0 D020
DLL
Divisor LSB Latch
0x01C4 2024
0x01D0 C024
0x01D0 D024
DLH
Divisor MSB Latch
0x01C4 2028
0x01D0 C028
0x01D0 D028
REVID1
Revision Identification Register 1
0x01C4 2030
0x01D0 C030
0x01D0 D030
PWREMU_MGMT
Power and Emulation Management Register
0x01C4 2034
0x01D0 C034
0x01D0 D034
MDR
Mode Definition Register
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6.23.2 UART Electrical Data/Timing
Table 6-86. Timing Requirements for UARTx Receive (1) (see Figure 6-66)
NO.
(1)
MIN
MAX
UNIT
4
tw(URXDB)
Pulse duration, receive data bit (RXDn)
0.96U
1.05U
ns
5
tw(URXSB)
Pulse duration, receive start bit
0.96U
1.05U
ns
U = UART baud time = 1/programmed baud rate.
NO.
(1)
PARAMETER
MIN
UNIT
MAX
1
f(baud)
Maximum programmable baud rate
2
tw(UTXDB)
Pulse duration, transmit data bit (TXDn)
U-2
U+2
3 MBaud
ns
3
tw(UTXSB)
Pulse duration, transmit start bit
U-2
U+2
ns
U = UART baud time = 1/programmed baud rate.
3
2
UART_TXDn
Start
Bit
Data Bits
5
4
UART_RXDn
Start
Bit
Data Bits
Figure 6-66. UART Transmit/Receive Timing
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ADVANCE INFORMATION
Table 6-87. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (1)
(see Figure 6-66)
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6.24 USB1 Host Controller Registers (USB1.1 OHCI)
All C6745/6747 USB interfaces are compliant with Universal Serial Bus Specifications, Revision 1.1.
Table 6-88 is the list of USB Host Controller registers.
Table 6-88. USB Host Controller Registers
USB
BYTE ADDRESS
ADVANCE INFORMATION
REGISTER NAME
Register Description
0x01E2 5000
HCREVISION
OHCI Revision Number Register
0x01E2 5004
HCCONTROL
HC Operating Mode Register
0x01E2 5008
HCCOMMANDSTATUS
HC Command and Status Register
0x01E2 500C
HCINTERRUPTSTATUS
HC Interrupt and Status Register
0x01E2 5010
HCINTERRUPTENABLE
HC Interrupt Enable Register
0x01E2 5014
HCINTERRUPTDISABLE
HC Interrupt Disable Register
0x01E2 5018
HCHCCA
HC HCAA Address Register
0x01E2 501C
HCPERIODCURRENTED
HC Current Periodic Register
0x01E2 5020
HCCONTROLHEADED
HC Head Control Register
0x01E2 5024
HCCONTROLCURRENTED
HC Current Control Register
0x01E2 5028
HCBULKHEADED
HC Head Bulk Register
0x01E2 502C
HCBULKCURRENTED
HC Current Bulk Register
0x01E2 5030
HCDONEHEAD
HC Head Done Register
0x01E2 5034
HCFMINTERVAL
HC Frame Interval Register
0x01E2 5038
HCFMREMAINING
HC Frame Remaining Register
0x01E2 503C
HCFMNUMBER
HC Frame Number Register
0x01E2 5040
HCPERIODICSTART
HC Periodic Start Register
0x01E2 5044
HCLSTHRESHOLD
HC Low-Speed Threshold Register
0x01E2 5048
HCRHDESCRIPTORA
HC Root Hub A Register
0x01E2 504C
HCRHDESCRIPTORB
HC Root Hub B Register
0x01E2 5050
HCRHSTATUS
HC Root Hub Status Register
0x01E2 5054
HCRHPORTSTATUS1
HC Port 1 Status and Control Register
0x01E2 5058
HCRHPORTSTATUS2
HC Port 2 Status and Control Register
Table 6-89. Switching Characteristics Over Recommended Operating Conditions for USB
NO.
PARAMETER
LOW SPEED
FULL SPEED
UNIT
MIN
MAX
MAX
MAX
4
20
ns
U1
tr
Rise time, USB.DP and USB.DM signals
75
300
U2
tf
Fall time, USB.DP and USB.DM signals
75
300
4
20
ns
U3
tRFM
Rise/Fall time matching
80
120
90
110
%
U4
VCRS
Output signal cross-over voltage
1.3
2
1.3
2
V
U5
tj
Differential propagation jitter
-25
25
-2
U6
fop
Operating frequency
174
Peripheral Information and Electrical Specifications
1.5
2
ns
12
MHz
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6.25 USB0 OTG (USB2.0 OTG)
ADVANCE INFORMATION
The C6745/6747 USB2.0 peripheral supports the following features:
• USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s - C6747 only) and full speed (FS: 12 Mb/s)
• USB 2.0 host at speeds HS (C6747 only), FS, and low speed (LS: 1.5 Mb/s)
• All transfer modes (control, bulk, interrupt, and isochronous)
• 4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
• FIFO RAM
– 4K endpoint
– Programmable size
• Integrated USB 2.0 High Speed PHY
• Connects to a standard Charge Pump for VBUS 5 V generation
• RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
Table 6-90 is the list of USB OTG registers.
Table 6-90. Universal Serial Bus OTG (USB0) Registers
BYTE ADDRESS
Acronym
Register Description
0x01E0 0000
REVID
Revision Register
0x01E0 0004
CTRLR
Control Register
0x01E0 0008
STATR
Status Register
0x01E0 000C
EMUR
Emulation Register
0x01E0 0010
MODE
Mode Register
0x01E0 0014
AUTOREQ
Autorequest Register
SRP Fix Time Register
0x01E0 0018
SRPFIXTIME
0x01E0 001C
TEARDOWN
Teardown Register
0x01E0 0020
INTSRCR
USB Interrupt Source Register
0x01E0 0024
INTSETR
USB Interrupt Source Set Register
USB Interrupt Source Clear Register
0x01E0 0028
INTCLRR
0x01E0 002C
INTMSKR
USB Interrupt Mask Register
0x01E0 0030
INTMSKSETR
USB Interrupt Mask Set Register
0x01E0 0034
INTMSKCLRR
USB Interrupt Mask Clear Register
0x01E0 0038
INTMASKEDR
USB Interrupt Source Masked Register
0x01E0 003C
EOIR
USB End of Interrupt Register
0x01E0 0040
INTVECTR
USB Interrupt Vector Register
0x01E0 0050
GENRNDISSZ1
Generic RNDIS Size EP1
0x01E0 0054
GENRNDISSZ2
Generic RNDIS Size EP2
0x01E0 0058
GENRNDISSZ3
Generic RNDIS Size EP3
0x01E0 005C
GENRNDISSZ4
Generic RNDIS Size EP4
0x01E0 0400
FADDR
Function Address Register
0x01E0 0401
POWER
Power Management Register
0x01E0 0402
INTRTX
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
0x01E0 0404
INTRRX
Interrupt Register for Receive Endpoints 1 to 4
0x01E0 0406
INTRTXE
Interrupt enable register for INTRTX
0x01E0 0408
INTRRXE
Interrupt Enable Register for INTRRX
0x01E0 040A
INTRUSB
Interrupt Register for Common USB Interrupts
0x01E0 040B
INTRUSBE
Interrupt Enable Register for INTRUSB
0x01E0 040C
FRAME
Frame Number Register
0x01E0 040E
INDEX
Index Register for Selecting the Endpoint Status and Control Registers
0x01E0 040F
TESTMODE
Register to Enable the USB 2.0 Test Modes
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Table 6-90. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
Register Description
Indexed Registers
These registers operate on the endpoint selected by the INDEX register
ADVANCE INFORMATION
0x01E0 0410
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint (Index
register set to select Endpoints 1-4 only)
0x01E0 0412
PERI_CSR0
Control Status Register for Endpoint 0 in Peripheral Mode. (Index
register set to select Endpoint 0)
HOST_CSR0
Control Status Register for Endpoint 0 in Host Mode.
(Index register set to select Endpoint 0)
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint. (Index
register set to select Endpoints 1-4)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0414
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint (Index
register set to select Endpoints 1-4 only)
0x01E0 0416
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint. (Index register
set to select Endpoints 1-4)
HOST_RXCSR
Control Status Register for Host Receive Endpoint.
(Index register set to select Endpoints 1-4)
COUNT0
Number of Received Bytes in Endpoint 0 FIFO.
(Index register set to select Endpoint 0)
RXCOUNT
Number of Bytes in Host Receive Endpoint FIFO.
(Index register set to select Endpoints 1- 4)
0x01E0 0418
0x01E0 041A
HOST_TYPE0
Defines the speed of Endpoint 0
HOST_TXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint. (Index register set to select
Endpoints 1-4 only)
HOST_NAKLIMIT0
Sets the NAK response timeout on Endpoint 0.
(Index register set to select Endpoint 0)
HOST_TXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
(Index register set to select Endpoints 1-4 only)
0x01E0 041C
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint. (Index register set to select
Endpoints 1-4 only)
0x01E0 041D
HOST_RXINTERVAL
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
(Index register set to select Endpoints 1-4 only)
0x01E0 041F
CONFIGDATA
Returns details of core configuration. (Index register set to select
Endpoint 0)
0x01E0 0420
FIFO0
Transmit and Receive FIFO Register for Endpoint 0
0x01E0 0424
FIFO1
Transmit and Receive FIFO Register for Endpoint 1
0x01E0 041B
FIFO
0x01E0 0428
FIFO2
Transmit and Receive FIFO Register for Endpoint 2
0x01E0 042C
FIFO3
Transmit and Receive FIFO Register for Endpoint 3
0x01E0 0430
FIFO4
Transmit and Receive FIFO Register for Endpoint 4
0x01E0 0460
DEVCTL
OTG Device Control
Device Control Register
Dynamic FIFO Control
176
0x01E0 0462
TXFIFOSZ
Transmit Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
0x01E0 0463
RXFIFOSZ
Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
0x01E0 0464
TXFIFOADDR
Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
0x01E0 0464
HWVERS
Hardware Version Register
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Table 6-90. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
Register Description
0x01E0 0466
RXFIFOADDR
Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
0x01E0 0482
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0483
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0484
RXFUNCADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
0x01E0 0486
RXHUBADDR
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0487
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
Target Endpoint 1 Control Registers, Valid Only in Host Mode
0x01E0 0488
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
0x01E0 048A
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048B
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048C
RXFUNCADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
0x01E0 048E
RXHUBADDR
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048F
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
Target Endpoint 2 Control Registers, Valid Only in Host Mode
0x01E0 0490
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
0x01E0 0492
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0493
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0494
RXFUNCADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
0x01E0 0496
RXHUBADDR
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0497
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
Target Endpoint 3 Control Registers, Valid Only in Host Mode
0x01E0 0498
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TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
Peripheral Information and Electrical Specifications
177
ADVANCE INFORMATION
Target Endpoint 0 Control Registers, Valid Only in Host Mode
0x01E0 0480
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Table 6-90. Universal Serial Bus OTG (USB0) Registers (continued)
ADVANCE INFORMATION
BYTE ADDRESS
Acronym
Register Description
0x01E0 049A
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049B
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049C
RXFUNCADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
0x01E0 049E
RXHUBADDR
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049F
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
Target Endpoint 4 Control Registers, Valid Only in Host Mode
0x01E0 04A0
TXFUNCADDR
Address of the target function that has to be accessed through the
associated Transmit Endpoint.
0x01E0 04A2
TXHUBADDR
Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A3
TXHUBPORT
Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A4
RXFUNCADDR
Address of the target function that has to be accessed through the
associated Receive Endpoint.
0x01E0 04A6
RXHUBADDR
Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A7
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
Control and Status Register for Endpoint 0
0x01E0 0502
0x01E0 0508
PERI_CSR0
Control Status Register for Endpoint 0 in Peripheral Mode
HOST_CSR0
Control Status Register for Endpoint 0 in Host Mode
COUNT0
Number of Received Bytes in Endpoint 0 FIFO
0x01E0 050A
HOST_TYPE0
Defines the Speed of Endpoint 0
0x01E0 050B
HOST_NAKLIMIT0
Sets the NAK Response Timeout on Endpoint 0
0x01E0 050F
CONFIGDATA
Returns details of core configuration.
0x01E0 0510
TXMAXP
0x01E0 0512
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral
mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
Control and Status Register for Endpoint 1
178
Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0514
RXMAXP
0x01E0 0516
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral
mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0518
RXCOUNT
0x01E0 051A
HOST_TXTYPE
0x01E0 051B
HOST_TXINTERVAL
Peripheral Information and Electrical Specifications
Maximum Packet Size for Peripheral/Host Receive Endpoint
Number of Bytes in Host Receive endpoint FIFO
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
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Table 6-90. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
0x01E0 051C
HOST_RXTYPE
Register Description
0x01E0 051D
HOST_RXINTERVAL
0x01E0 0520
TXMAXP
0x01E0 0522
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral
mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 2
0x01E0 0524
RXMAXP
0x01E0 0526
PERI_RXCSR
Maximum Packet Size for Peripheral/Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral
mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0528
RXCOUNT
Number of Bytes in Host Receive endpoint FIFO
0x01E0 052A
HOST_TXTYPE
0x01E0 052B
HOST_TXINTERVAL
0x01E0 052C
HOST_RXTYPE
0x01E0 052D
HOST_RXINTERVAL
0x01E0 0530
TXMAXP
0x01E0 0532
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral
mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 3
Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0534
RXMAXP
0x01E0 0536
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral
mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0538
RXCOUNT
0x01E0 053A
HOST_TXTYPE
0x01E0 053B
HOST_TXINTERVAL
0x01E0 053C
HOST_RXTYPE
0x01E0 053D
HOST_RXINTERVAL
Maximum Packet Size for Peripheral/Host Receive Endpoint
Number of Bytes in Host Receive endpoint FIFO
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
Control and Status Register for Endpoint 4
0x01E0 0540
TXMAXP
0x01E0 0542
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral
mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0544
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RXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Maximum Packet Size for Peripheral/Host Receive Endpoint
Peripheral Information and Electrical Specifications
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ADVANCE INFORMATION
Maximum Packet Size for Peripheral/Host Transmit Endpoint
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Table 6-90. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
0x01E0 0546
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral
mode)
Register Description
HOST_RXCSR
Control Status Register for Host Receive Endpoint
(host mode)
ADVANCE INFORMATION
0x01E0 0548
RXCOUNT
0x01E0 054A
HOST_TXTYPE
Number of Bytes in Host Receive endpoint FIFO
0x01E0 054B
HOST_TXINTERVAL
0x01E0 054C
HOST_RXTYPE
0x01E0 054D
HOST_RXINTERVAL
0x01E0 1000
DMAREVID
0x01E0 1004
TDFDQ
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
DMA Registers
DMA Revision Register
DMA Teardown Free Descriptor Queue Control Register
0x01E0 1008
DMAEMU
DMA Emulation Control Register
0x01E0 1800
TXGCR[0]
Transmit Channel 0 Global Configuration Register
0x01E0 1808
RXGCR[0]
Receive Channel 0 Global Configuration Register
0x01E0 180C
RXHPCRA[0]
Receive Channel 0 Host Packet Configuration Register A
0x01E0 1810
RXHPCRB[0]
Receive Channel 0 Host Packet Configuration Register B
0x01E0 1820
TXGCR[1]
Transmit Channel 1 Global Configuration Register
0x01E0 1828
RXGCR[1]
Receive Channel 1 Global Configuration Register
0x01E0 182C
RXHPCRA[1]
Receive Channel 1 Host Packet Configuration Register A
0x01E0 1830
RXHPCRB[1]
Receive Channel 1 Host Packet Configuration Register B
0x01E0 1840
TXGCR[2]
Transmit Channel 2 Global Configuration Register
Receive Channel 2 Global Configuration Register
0x01E0 1848
RXGCR[2]
0x01E0 184C
RXHPCRA[2]
Receive Channel 2 Host Packet Configuration Register A
0x01E0 1850
RXHPCRB[2]
Receive Channel 2 Host Packet Configuration Register B
0x01E0 1860
TXGCR[3]
Transmit Channel 3 Global Configuration Register
Receive Channel 3 Global Configuration Register
0x01E0 1868
RXGCR[3]
0x01E0 186C
RXHPCRA[3]
Receive Channel 3 Host Packet Configuration Register A
0x01E0 1870
RXHPCRB[3]
Receive Channel 3 Host Packet Configuration Register B
0x01E0 2C00
DMA_SCHED_CTRL
0x01E0 2D00
ENTRY[0]
DMA Scheduler Table Word 0
0x01E0 2D04
ENTRY[1]
DMA Scheduler Table Word 1
...
...
0x01E0 2DFC
ENTRY[63]
DMA Scheduler Control Register
...
DMA Scheduler Table Word 63
Queue Manager Registers
180
0x01E0 4000
QMGRREVID
Queue Manager Revision Register
0x01E0 4008
DIVERSION
0x01E0 4020
FDBSC0
Free Descriptor/Buffer Starvation Count Register 0
0x01E0 4024
FDBSC1
Free Descriptor/Buffer Starvation Count Register 1
Queue Diversion Register
0x01E0 4028
FDBSC2
Free Descriptor/Buffer Starvation Count Register 2
0x01E0 402C
FDBSC3
Free Descriptor/Buffer Starvation Count Register 3
0x01E0 4080
LRAM0BASE
Linking RAM Region 0 Base Address Register
0x01E0 4084
LRAM0SIZE
Linking RAM Region 0 Size Register
0x01E0 4088
LRAM1BASE
Linking RAM Region 1 Base Address Register
0x01E0 4090
PEND0
Peripheral Information and Electrical Specifications
Queue Pending Register 0
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
Table 6-90. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
Acronym
0x01E0 4094
PEND1
Register Description
0x01E0 5000
QMEMRBASE[0]
Memory Region 0 Base Address Register
0x01E0 5004
QMEMRCTRL[0]
Memory Region 0 Control Register
0x01E0 5010
QMEMRBASE[1]
Memory Region 1 Base Address Register
0x01E0 5014
QMEMRCTRL[1]
Memory Region 1 Control Register
Queue Pending Register 1
...
QMEMRBASE[7]
...
Memory Region 7 Base Address Register
0x01E0 5074
QMEMRCTRL[7]
Memory Region 7 Control Register
0x01E0 600C
CTRLD[0]
Queue Manager Queue 0 Control Register D
0x01E0 601C
CTRLD[1]
Queue Manager Queue 1 Control Register D
...
...
0x01E0 63FC
CTRLD[63]
Queue Manager Queue 63 Status Register D
0x01E0 6800
QSTATA[0]
Queue Manager Queue 0 Status Register A
0x01E0 6804
QSTATB[0]
Queue Manager Queue 0 Status Register B
0x01E0 6808
QSTATC[0]
Queue Manager Queue 0 Status Register C
0x01E0 6810
QSTATA[1]
Queue Manager Queue 1 Status Register A
0x01E0 6814
QSTATB[1]
Queue Manager Queue 1 Status Register B
0x01E0 6818
QSTATC[1]
Queue Manager Queue 1 Status Register C
...
...
0x01E0 6BF0
QSTATA[63]
Queue Manager Queue 63 Status Register A
0x01E0 6BF4
QSTATB[63]
Queue Manager Queue 63 Status Register B
0x01E0 6BF8
QSTATC[63]
Queue Manager Queue 63 Status Register C
ADVANCE INFORMATION
...
0x01E0 5070
...
...
6.25.1 USB2.0 Electrical Data/Timing
Table 6-91. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see
Figure 6-67)
NO.
PARAMETER
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
1
tr(D)
Rise time, USB_DP and USB_DM signals (1)
75
300
4
20
0.5
2
tf(D)
Fall time, USB_DP and USB_DM signals (1)
75
300
4
20
0.5
3
trfM
Rise/Fall time, matching (2)
80
120
90
111
–
–
4
VCRS
Output signal cross-over voltage (1)
1.3
2
1.3
2
–
–
5
6
tjr(source)NT
Source (Host) Driver jitter, next transition
tjr(FUNC)NT
Function Driver jitter, next transition
tjr(source)PT
Source (Host) Driver jitter, paired transition (4)
tjr(FUNC)PT
Function Driver jitter, paired transition
7
tw(EOPT)
Pulse duration, EOP transmitter
8
tw(EOPR)
Pulse duration, EOP receiver
9
t(DRATE)
Data Rate
10
ZDRV
Driver Output Resistance
11
ZINP
Receiver Input Impedance
(1)
(2)
(3)
(4)
LOW SPEED
1.5 Mbps
V
(3)
2
2
(3)
ns
1
1
(3)
ns
1
(3)
ns
–
ns
1500
160
175
82
1.5
100k
%
2
670
–
ns
25
10
1250
ns
–
ns
–
–
12
40.5
49.5
100k
ns
480 Mb/s
40.5
49.5
Ω
-
-
Ω
Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
tjr = tpx(1) - tpx(0)
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USB_DM
VCRS
USB_DP
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tper − tjr
90% VOH
10% VOL
tr
tf
Figure 6-67. USB2.0 Integrated Transceiver Interface Timing
ADVANCE INFORMATION
182
Peripheral Information and Electrical Specifications
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SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
6.26 Host-Port Interface (UHPI)
6.26.1 HPI Device-Specific Information
The device includes a user-configurable 16-bit Host-port interface (HPI16). See the TMS320C6745/C6747
DSP Peripherals Overview Reference Guide. – Literature Number SPRUFK9 for more details.
6.26.2 HPI Peripheral Register Description(s)
Table 6-92. HPI Control Registers
(1)
ACRONYM
0x01E1 0000
PID
0x01E1 0004
PWREMU_MGMT
REGISTER NAME
COMMENTS
Peripheral Identification Register
HPI power and emulation management register
0x01E1 0008
-
0x01E1 000C
GPIO_EN
0x01E1 0010
GPIO_DIR1
General Purpose IO Direction Register 1
0x01E1 0014
GPIO_DAT1
General Purpose IO Data Register 1
The CPU has read/write
access to the
PWREMU_MGMT register.
Reserved
General Purpose IO Enable Register
0x01E1 0018
GPIO_DIR2
General Purpose IO Direction Register 2
0x01E1 001C
GPIO_DAT2
General Purpose IO Data Register 2
0x01E1 0020
GPIO_DIR3
General Purpose IO Direction Register 3
0x01E1 0024
GPIO_DAT3
General Purpose IO Data Register 3
01E1 0028
-
Reserved
01E1 002C
-
Reserved
01E1 0030
HPIC
HPI control register
01E1 0034
HPIA
(HPIAW) (1)
HPI address register
(Write)
01E1 0038
HPIA
(HPIAR) (1)
HPI address register
(Read)
01E1 000C - 01E1 07FF
-
The Host and the CPU both
have read/write access to the
HPIC register.
The Host has read/write
access to the HPIA registers.
The CPU has only read
access to the HPIA registers.
Reserved
There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The CPU can access HPIAW and HPIAR independently.
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6.26.3 HPI Electrical Data/Timing
Table 6-93. Timing Requirements for Host-Port Interface Cycles (1) (2)
NO.
MIN
(3)
1
tsu(SELV-HSTBL)
Setup time, select signals
2
th(HSTBL-SELV)
Hold time, select signals (3) valid after UHPI_HSTROBE low
valid before UHPI_HSTROBE low
3
tw(HSTBL)
4
MAX
UNIT
5
ns
2
ns
Pulse duration, UHPI_HSTROBE active low
15
ns
tw(HSTBH)
Pulse duration, UHPI_HSTROBE inactive high between consecutive
accesses
2M
ns
ADVANCE INFORMATION
9
tsu(SELV-HASL)
Setup time, selects signals valid before UHPI_HAS low
5
10
th(HASL-SELV)
Hold time, select signals valid after UHPI_HAS low
2
11
tsu(HDV-HSTBH)
Setup time, host data valid before UHPI_HSTROBE high
5
ns
12
th(HSTBH-HDV)
Hold time, host data valid after UHPI_HSTROBE high
2
ns
13
th(HRDYL-HSTBH)
Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE
should not be inactivated until UHPI_HRDY is active (low); otherwise, HPI
writes will not complete properly.
2
ns
16
tsu(HASL-HSTBL)
Setup time, UHPI_HAS low before UHPI_HSTROBE low
2
17
th(HSTBL-HASH)
Hold time, UHPI_HAS low after UHPI_HSTROBE low
2
(1)
(2)
(3)
184
UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
M=SYSCLK2 period (CPU clock frequency)/2 in ns. For example, when running parts at 300 MHz, use M=6.67 ns.
Select signals include: HCNTL[1:0], HR/W and HHWIL.
Peripheral Information and Electrical Specifications
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Table 6-94. Switching Characteristics for Host-Port Interface Cycles (1) (2) (3)
NO.
PARAMETER
MIN
UNIT
MAX
5
td(HSTBL-HRDYV)
Delay time, HSTROBE low to
HRDY valid
5a
td(HASL-HRDYV)
Delay time, HAS low to HRDY valid
6
ten(HSTBL-HDLZ)
Enable time, HD driven from HSTROBE low
7
td(HRDYL-HDV)
Delay time, HRDY low to HD valid
8
toh(HSTBH-HDV)
Output hold time, HD valid after HSTROBE high
14
tdis(HSTBH-HDHZ)
Disable time, HD high-impedance from HSTROBE high
15
18
(1)
(2)
(3)
For HPI Read, HRDY can go high (not
ready) for these HPI Read conditions:
Case 1: HPID read (with
auto-increment) and data not in Read
FIFO (can only happen to first
half-word of HPID access)
Case 2: First half-word access of HPID
Read without auto-increment
For HPI Read, HRDY stays low (ready)
for these HPI Read conditions:
Case 1: HPID read with auto-increment
and data is already in Read FIFO
(applies to either half-word of HPID
access)
Case 2: HPID read without
auto-increment and data is already in
Read FIFO (always applies to second
half-word of HPID access)
Case 3: HPIC or HPIA read (applies to
either half-word access)
td(HSTBL-HDV)
td(HSTBH-HRDYV)
10
ADVANCE INFORMATION
For HPI Write, HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can
be either first or second half-word)
Case 2: HPIA write following a
PREFETCH command (can be either
first or second half-word)
Case 3: HPID write when FIFO is full
or flushing (can be either first or
second half-word)
Case 4: HPIA write and Write FIFO not
empty
ns
10
2
ns
0
1.5
ns
ns
10
ns
Delay time, HSTROBE low to
HD valid
For HPI Read. Applies to conditions
where data is already residing in
HPID/FIFO:
Case 1: HPIC or HPIA read
Case 2: First half-word of HPID read
with auto-increment and data is
already in Read FIFO
Case 3: Second half-word of HPID
read with or without auto-increment
15
ns
Delay time, HSTROBE high to
HRDY valid
For HPI Write, HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, HRDY stays low (ready):
Case 1: HPID write when Write FIFO is
full (can happen to either half-word)
Case 2: HPIA write (can happen to
either half-word)
Case 3: HPID write without
auto-increment (only happens to
second half-word)
12
ns
M=SYSCLK2 period (CPU clock frequency)/2 in ns. For example, when running parts at 300 MHz, use M=6.67 ns.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).
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UHPI_HCS
UHPI_HAS(D)
2
2
1
1
UHPI_HCNTL[1:0]
2
1
2
1
UHPI_HR/W
2
2
1
1
ADVANCE INFORMATION
UHPI_HHWIL
4
3
3
UHPI_HSTROBE(A)(C)
15
15
14
14
6
8
8
6
UHPI_HD[15:0]
(output)
5
13
7
1st Half-Word
2nd Half-Word
UHPI_HRDY(B)
A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1
XOR HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or
UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE.
D The diagram above assumes UHPI_HAS has been pulled high.
Figure 6-68. UHPI Read Timing (HAS Not Used, Tied High)
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UHPI_HAS(A)
17
10
17
9
10
9
UHPI_HCNTL[1:0]
10
10
9
9
UHPI_HR/W
10
10
9
9
UHPI_HHWIL
4
3
16
16
UHPI_HCS
14
UHPI_HD[15:0]
6
(output)
5a
ADVANCE INFORMATION
UHPI_HSTROBE(B)
8
1st half-word
14
15
7
8
2nd half-word
UHPI_HRDY
A.
For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
B.
UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
Figure 6-69. UHPI Read Timing (HAS Used)
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UHPI_HCS
UHPI_HAS(D)
1
1
2
2
UHPI_HCNTL[1:0]
1
1
2
2
UHPI_HR/W
ADVANCE INFORMATION
1
1
2
2
UHPI_HHWIL
3
3
4
UHPI_HSTROBE(A)(C)
11
UHPI_HD[15:0]
(input)
11
12
12
1st Half-Word
5
13
2nd Half-Word
18
13
18
5
UHPI_HRDY(B)
A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR
UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the
state of the FIFO, transitions on UHPI_HRDY may or may not occur.
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2. UHPI_HCS
timing requirements are reflected by parameters for UHPI_HSTROBE.
D The diagram above assumes UHPI_HAS has been pulled high.
Figure 6-70. UHPI Write Timing (HAS Not Used, Tied High)
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17
UHPI_HAS(A)
17
10
10
9
9
UHPI_HCNTL[1:0]
10
10
9
9
UHPI_HR/W
10
10
9
9
UHPI_HHWIL
3
ADVANCE INFORMATION
4
UHPI_HSTROBE(B)
16
16
UHPI_HCS
11
12
UHPI_HD[15:0]
(input)
1st half-word
11
12
2nd half-word
5a
13
UHPI_HRDY
Figure 6-71. UHPI Write Timing (HAS Used)
17
UHPI_HAS†
17
10
10
9
9
UHPI_HCNTL[1:0]
10
10
9
9
UHPI_HR/W
10
10
9
9
UHPI_HHWIL
3
4
UHPI_HSTROBE‡
16
16
UHPI_HCS
11
12
UHPI_HD[15:0]
(input)
1st half-word
5a
11
12
2nd half-word
13
UHPI_HRDY
A.
For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
B.
UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
Figure 6-72.
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6.27 Power and Sleep Controller (PSC)
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control.
ADVANCE INFORMATION
The PSC includes the following features:
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Supports IcePick emulation features: power, clock and reset
Table 6-95. Power and Sleep Controller (PSC) Registers
PSC0
PSC1
Register
Description
0x01C1 0000
0x01C1 0018
0x01E2 7000
REVID
Peripheral Revision and Class Information Register
0x01E2 7018
INTEVAL
Interrupt Evaluation Register
0x01C1 0040
0x01E2 7040
MERRPR0
Module Error Pending Register 0 (module 0-15) (PSC0)
0x01C1 0050
0x01E2 7050
MERRCR0
0x01C1 0060
0x01E2 7060
PERRPR
Power Error Pending Register
0x01C1 0068
0x01E2 7068
PERRCR
Power Error Clear Register
0x01C1 0120
0x01E2 7120
PTCMD
Power Domain Transition Command Register
0x01C1 0128
0x01E2 7128
PTSTAT
Power Domain Transition Status Register
0x01C1 0200
0x01E2 7200
PDSTAT0
Power Domain 0 Status Register
0x01C1 0204
0x01E2 7204
PDSTAT1
Power Domain 1 Status Register
0x01C1 0300
0x01E2 7300
PDCTL0
Power Domain 0 Control Register
0x01C1 0304
0x01E2 7304
PDCTL1
Power Domain 1 Control Register
0x01C1 0400
0x01E2 7400
PDCFG0
Power Domain 0 Configuration Register
0x01C1 0404
0x01E2 7404
PDCFG1
Power Domain 1 Configuration Register
0x01C1 0800 - 0x01C1
083C
0x01E2 7800 0x01E2 787C
MDSTAT0MDSTAT15
Module Status n Register (modules 0-15) (PSC0)
MDSTAT0MDSTAT31
Module Status n Register (modules 0-31) (PSC1)
MDCTL0MDCTL15
Module Control n Register (modules 0-15) (PSC0)
MDSTAT0MDSTAT31
Module Status n Register (modules 0-31) (PSC1)
Module Error Pending Register 0 (module 0-31) (PSC1)
Module Error Clear Register 0 (module 0-15) (PSC0)
Module Error Clear Register 0 (module 0-31) (PSC1)
0x01C1 0A00 - 0x01C1
0A3C
0x01E2 7A00 0x01E2 7A7C
6.27.1 Power Domain and Module Topology
The device includes two PSC modules.
Each PSC module controls clock states for several of the on chip modules, controllers and interconnect
components. Table 6-96 and Table 6-97 lists the set of peripherals/modules that are controlled by the
PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 6.27.1.2.
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LPSC Number
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
0
EDMA3 Channel Controller
AlwaysON (PD0)
SwRstDisable
—
1
EDMA3 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
2
EDMA3 Transfer Controller 1
AlwaysON (PD0)
SwRstDisable
—
3
EMIFA (BR7)
AlwaysON (PD0)
SwRstDisable
—
4
SPI 0
AlwaysON (PD0)
SwRstDisable
—
5
MMC/SD 0
AlwaysON (PD0)
SwRstDisable
—
8
-
-
-
-
9
UART 0
AlwaysON (PD0)
SwRstDisable
—
10
SCR0
(Br 0, Br 1, Br 2, Br 8)
AlwaysON (PD0)
Enable
Yes
11
SCR1
(Br 4)
AlwaysON (PD0)
Enable
Yes
12
SCR2
(Br 3, Br 5, Br 6)
AlwaysON (PD0)
Enable
Yes
13
-
-
-
-
15
DSP
PD_DSP (PD1)
Enable
—
Table 6-97. PSC1 Default Module Configuration
LPSC Number
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
0
Not Used
—
—
—
1
USB0 (USB2.0)
AlwaysON (PD0)
SwRstDisable
—
2
USB1 (USB1.1)
AlwaysON (PD0)
SwRstDisable
—
3
GPIO
AlwaysON (PD0)
SwRstDisable
—
4
UHPI
AlwaysON (PD0)
SwRstDisable
—
5
EMAC
AlwaysON (PD0)
SwRstDisable
—
6
EMIFB (Br 20)
AlwaysON (PD0)
SwRstDisable
—
7
McASP0 ( + McASP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
8
McASP1 ( + McASP1 FIFO)
AlwaysON (PD0)
SwRstDisable
—
9
McASP2( + McASP2 FIFO)
AlwaysON (PD0)
SwRstDisable
—
10
SPI 1
AlwaysON (PD0)
SwRstDisable
—
11
I2C 1
AlwaysON (PD0)
SwRstDisable
—
12
UART 1
AlwaysON (PD0)
SwRstDisable
—
13
UART 2
AlwaysON (PD0)
SwRstDisable
—
14-15
Not Used
—
—
—
16
LCDC
AlwaysON (PD0)
SwRstDisable
—
17
eHRPWM0/1/2
AlwaysON (PD0)
SwRstDisable
—
18-19
Not Used
—
—
—
20
ECAP0/1/2
AlwaysON (PD0)
SwRstDisable
—
21
EQEP0/1
AlwaysON (PD0)
SwRstDisable
—
22-23
Not Used
—
—
—
24
SCR8
(Br 15)
AlwaysON (PD0)
Enable
Yes
25
SCR7
(Br 12)
AlwaysON (PD0)
Enable
Yes
26
SCR12
(Br 18)
AlwaysON (PD0)
Enable
Yes
27-30
Not Used
—
—
—
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Table 6-96. PSC0 Default Module Configuration
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Table 6-97. PSC1 Default Module Configuration (continued)
LPSC Number
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
31
Shared RAM
(Br 13)
PD_SHRAM
Enable
Yes
6.27.1.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
• ON: power to the domain is on
• OFF: power to the domain is off
ADVANCE INFORMATION
In the device , for both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state.
• On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
• On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128K Shared RAM
6.27.1.2 Module States
The PSC defines several possible states for a module. This states are essentially a combination of the
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are
defined in Table 6-98.
Table 6-98. Module States
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has its
clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has its
module clock off. This state is typically used for disabling a module clock to
save power. The device is designed in full static CMOS, so when you stop a
module clock, it retains the module’s state. When the clock is restarted, the
module resumes operating from the stopping point.
SyncReset
Asserted
On
A module state in the SyncReset state has its module reset asserted and it has
its clock on. Generally, software is not expected to initiate this state
SwRstDisable
Asserted
Off
A module in the SwResetDisable state has its module reset asserted and it has
its clock disabled. After initial power-on, several modules come up in the
SwRstDisable state. Generally, software is not expected to initiate this state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it can
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re de-asserted
and module clock disabled), without any software intervention. The transition
from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are
fully operational and moving data.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from then
on (with module reset re de-asserted and module clock on), without any
software intervention. The transition from sleep to enabled state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data.
6.28 Emulation Logic
The debug capabilities and features for DSP are as shown below.
DSP:
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•
•
•
•
•
•
Basic Debug
– Execution Control
– System Visibility
Real-Time Debug
– Interrupts serviced while halted
– Low/non-intrusive system visibility while running
Advanced Debug
– Global Start
– Global Stop
– Specify targeted memory level(s) during memory accesses
– HSRTDX (High Speed Real Time Data eXchange)
Advanced System Control
– Subsystem reset via debug
– Peripheral notification of debug events
– Cache-coherent debug accesses
Analysis Actions
– Stop program execution
– Generate debug interrupt
– Benchmarking with counters
– External trigger generation
– Debug state machine state transition
– Combinational and Sequential event generation
Analysis Events
– Program event detection
– Data event detection
– External trigger Detection
– System event detection (i.e. cache miss)
– Debug state machine state detection
Analysis Configuration
– Application access
– Debugger access
ADVANCE INFORMATION
•
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Table 6-99. DSP Debug Features
Category
Hardware Feature
Software breakpoint
Availability
Unlimited
Up to 10 HWBPs, including:
Basic Debug
Hardware breakpoint
4 precise (1) HWBPs inside DSP core and one of them is
associated with a counter.
2 imprecise (1) HWBPs from AET.
4 imprecise (1) HWBPs from AET which are shared for
watch point.
(1)
Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
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Table 6-99. DSP Debug Features (continued)
Category
Hardware Feature
Availability
Watch point
Up to 4 watch points, which are shared with HWBPs,
and can also be used as 2 watch points with data (32
bits)
Watch point with Data
Up to 2, Which can also be used as 4 watch points.
Counters/timers
1x64-bits (cycle only) + 2x32-bits (water marke counters)
External Event Trigger In
1
External Event Trigger Out
1
Analysis
6.28.1 JTAG Port Description
ADVANCE INFORMATION
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO).
TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its
default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device
functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be
driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed
while the TRST pin is pulled low.
Table 6-100. JTAG Port Description
PIN
TYPE
NAME
DESCRIPTION
TRST
I
Test Logic Reset
When asserted (active low) causes all test and debug logic in the device
to be reset along with the IEEE 1149.1 interface
TCK
I
Test Clock
This is the test clock used to drive an IEEE 1149.1 TAP state machine
and logic.
TMS
I
Test Mode Select
Directs the next state of the IEEE 1149.1 test access port state machine
TDI
I
Test Data Input
Scan data input to the device
TDO
O
Test Data Output
Scan data output of the device
EMU0
I/O
Emulation 0
Channel 0 trigger + HSRTDX
6.28.2 Scan Chain Configuration Parameters
Table 6-101 shows the TAP configuration details required to configure the router/emulator for this device.
Table 6-101. JTAG Port Description
Router Port ID
Default TAP
TAP Name
Tap IR Length
17
No
C674x
38
The router is revision C and has a 6-bit IR length.
6.29 Real Time Clock (RTC)
The RTC provides a time reference to an application running on the device. The current date and time is
tracked in a set of counter registers that update once per second. The time can be represented in 12-hour
or 24-hour mode. The calendar and time registers are buffered during reads and writes so that updates do
not interfere with the accuracy of the time and date.
Alarms are available to interrupt the CPU at a particular time, or at periodic time intervals, such as once
per minute or once per day. In addition, the RTC can interrupt the CPU every time the calendar and time
registers are updated, or at programmable periodic intervals.
The real-time clock (RTC) provides the following features:
• 100-year calendar (xx00 to xx99)
• Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation
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Binary-coded-decimal (BCD) representation of time, calendar, and alarm
12-hour clock mode (with AM and PM) or 24-hour clock mode
Alarm interrupt
Periodic interrupt
Single interrupt to the CPU
Supports external 32.768-kHz crystal or external clock source of the same frequency
Separate isolated power supply
RTC_XI
Counter
32 kHz
Oscillator
Compensation
Seconds
Minutes
Week
Days
XTAL
RTC_XO
Hours
Days
Months
Years
Oscillator
Alarm
Alarm
Interrupts
Timer
Periodic
Interrupts
Figure 6-73. Real-Time Clock Block Diagram
6.29.1 Clock Source
The clock reference for the RTC is an external 32.768-kHz crystal or an external clock source of the same
frequency. The RTC also has a separate power supply that is isolated from the rest of the system. When
the CPU and other peripherals are without power, the RTC can remain powered to preserve the current
time and calendar information.
The source for the RTC reference clock may be provided by a crystal or by an external clock source. The
RTC has an internal oscillator buffer to support direct operation with a crystal. The crystal is connected
between pins RTC_XI and RTC_XO. RTC_XI is the input to the on-chip oscillator and RTC_XO is the
output from the oscillator back to the crystal.
An external 32.768-kHz clock source may be used instead of a crystal. In such a case, the clock source is
connected to RTC_XI, and RTC_XO is left unconnected.
If the RTC is not used, the RTC_XI pin should be held low and RTC_XO should be left unconnected.
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ADVANCE INFORMATION
Figure 6-73 shows a block diagram of the RTC.
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Switch for Device
Core Power
+1.2V
CVDD
Real Time Clock
C2
RTC_CVDD
RTC_X1
XTAL
32.768
kHz
RTC_X0
ADVANCE INFORMATION
32K
OSC
C1
Real
Time
Clock
(RTC)
Module
RTC_VSS
Isolated RTC
Power Domain
Figure 6-74. Clock Source
6.29.2 Registers
Table 6-102 lists the memory-mapped registers for the RTC. See the device-specific data manual for the
memory address of these registers.
Table 6-102. Real-Time Clock (RTC) Registers
196
BYTE ADDRESS
Acronym
Register Description
0x01C2 3000
SECOND
Seconds Register
0x01C2 3004
MINUTE
Minutes Register
0x01C2 3008
HOUR
Hours Register
0x01C2 300C
DAY
Day of the Month Register
0x01C2 3010
MONTH
Month Register
0x01C2 3014
YEAR
Year Register
0x01C2 3018
DOTW
Day of the Week Register
0x01C2 3020
ALARMSECOND
Alarm Seconds Register
0x01C2 3024
ALARMMINUTE
Alarm Minutes Register
0x01C2 3028
ALARMHOUR
Alarm Hours Register
0x01C2 302C
ALARMDAY
Alarm Days Register
0x01C2 3030
ALARMMONTH
Alarm Months Register
0x01C2 3034
ALARMYEAR
Alarm Years Register
0x01C2 3040
CTRL
Control Register
0x01C2 3044
STATUS
Status Register
0x01C2 3048
INTERRUPT
Interrupt Enable Register
0x01C2 304C
COMPLSB
Compensation (LSB) Register
0x01C2 3050
COMPMSB
Compensation (MSB) Register
0x01C2 3054
OSC
Oscillator Register
0x01C2 3060
SCRATCH0
Scratch 0 (General-Purpose) Register
0x01C2 3064
SCRATCH1
Scratch 1 (General-Purpose) Register
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Table 6-102. Real-Time Clock (RTC) Registers (continued)
Acronym
Register Description
0x01C2 3068
SCRATCH2
Scratch 2 (General-Purpose) Register
0x01C2 306C
KICK0
Kick 0 (Write Protect) Register
0x01C2 3070
KICK1
Kick 1 (Write Protect) Register
ADVANCE INFORMATION
BYTE ADDRESS
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7 Mechanical Packaging and Orderable Information
This section describes the C6745/6747 orderable part numbers, packaging options, materials, thermal and
mechanical parameters.
7.1 Thermal Data for ZKB
The following table(s) show the thermal resistance characteristics for the PBGA–ZKB mechanical
package.
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZKB]
NO.
ADVANCE INFORMATION
°C/W (1)
°C/W (2)
AIR FLOW
(m/s) (3)
1
RΘJC
Junction-to-case
12.8
13.5
N/A
2
RΘJB
Junction-to-board
15.1
19.7
N/A
3
RΘJA
Junction-to-free air
24.5
33.8
0.00
4
21.9
30
0.50
5
21.1
28.7
1.00
RΘJMA
6
Junction-to-moving air
20.4
27.4
2.00
7
19.6
26
4.00
8
0.6
0.8
0.00
9
0.8
1
0.50
10
0.9
1.2
1.00
11
1.1
1.4
2.00
12
1.3
1.8
4.00
13
14.9
19.1
0.00
14
14.4
18.2
0.50
14.4
18
1.00
16
14.3
17.7
2.00
17
14.1
17.4
4.00
15
(1)
(2)
(3)
198
PsiJT
PsiJB
Junction-to-package top
Junction-to-board
These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages. Power dissipation of 1W and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and
1.5oz (50um) inner copper thickness
Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness.
Power dissipation of 1W and ambient temp of 70C assumed.
m/s = meters per second
Mechanical Packaging and Orderable Information
Submit Documentation Feedback
TMS320C6745/6747 Floating-point Digital Signal Processor
www.ti.com
SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008
7.2 Thermal Data for PTP
The following table(s) show the thermal resistance characteristics for the HTQFP–PTP mechanical
package.
NO.
°C/W (1)
°C/W (2)
°C/W (3)
°C/W (4)
AIR FLOW
(m/s) (5)
N/A
1
RΘJC
Junction-to-case
7.8
9.4
8.6
10.1
2
RΘJB
Junction-to-board
6.2
9.9
7.1
10.6
N/A
3
RΘJA
Junction-to-free air
21.3
27.9
23.2
30.6
0.00
4
14.3
20.2
22.6
0.50
5
13.1
18.6
21.0
1.00
12.1
17.4
19.6
2.00
7
11.2
16.2
18.2
4.00
8
0.5
0.7
0.8
0.00
9
0.6
0.9
1.0
0.50
6
10
RΘJMA
PsiJT
Junction-to-moving air
0.7
1.0
1.1
1.00
11
Junction-to-package top
0.8
1.1
1.3
2.00
12
1.0
1.3
1.5
4.00
13
6.3
9.5
10.8
0.00
5.9
8.8
9.9
0.50
5.9
8.7
9.8
1.00
5.8
8.6
9.7
2.00
5.8
8.5
9.6
4.00
14
15
PsiJB
Junction-to-board
16
17
(1)
(2)
(3)
(4)
(5)
Simulation data, using a model of a JEDEC defined 2S2P system with a 12mmx12mm copper pad on the top and bottom copper layers
connected with an 8x8 thermal via array and soldered to the package thermal pad. Power dissipation of 1W assumed, 70C Ambient
temp assumed. Signal layer copper coverage 20%, inner layer copper coverage 90%. Actual performance will change based on
environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal
Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for
Leaded Surface Mount Packages.
Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness.
Power dissipation of 1W and ambient temp of 70C assumed.
Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper
thickness 2oz (70um) top and bottom.
Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper
thickness 1oz (35um) top and bottom.
m/s = meters per second
7.3 Mechanical Drawings
This section contains mechanical drawings for the ZKB Ball Grid Array package and the PTP Thin Quad
Flat Pack package. Additionally, for the PTP package a detailed drawing of the actual thermal pad
dimensions as well as a recommended PCB footprint are provided.
Submit Documentation Feedback
Mechanical Packaging and Orderable Information
199
ADVANCE INFORMATION
Table 7-2. Thermal Resistance Characteristics (HTQFP Package) [PTP]
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TMS320C6745PTP2
PREVIEW
HLQFP
PTP
176
TBD
Call TI
Call TI
TMS320C6745PTP3
PREVIEW
HLQFP
PTP
176
TBD
Call TI
Call TI
TMS320C6745PTPT2
PREVIEW
HLQFP
PTP
176
TBD
Call TI
Call TI
TMS320C6745PTPT3
PREVIEW
HLQFP
PTP
176
TBD
Call TI
Call TI
TMS320C6747ZKB2
PREVIEW
BGA
ZKB
256
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
TMS320C6747ZKB3
PREVIEW
BGA
ZKB
256
TBD
Call TI
Call TI
TMS320C6747ZKBT2
PREVIEW
BGA
ZKB
256
TBD
Call TI
Call TI
TMS320C6747ZKBT3
PREVIEW
BGA
ZKB
256
TBD
Call TI
Call TI
TMX320C6745PTP2
ACTIVE
HLQFP
PTP
176
40
TBD
Call TI
Call TI
TMX320C6745PTP3
ACTIVE
HLQFP
PTP
176
40
TBD
Call TI
Call TI
TMX320C6747ZKB2
ACTIVE
BGA
ZKB
256
90
TBD
Call TI
Call TI
TMX320C6747ZKB3
ACTIVE
BGA
ZKB
256
90
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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