TI TMS320F28044PZS

TMS320F28044
Digital Signal Processor
Data Manual
Literature Number: SPRS357B
August 2006 – Revised May 2007
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TMS320F28044
Digital Signal Processor
www.ti.com
SPRS357B – AUGUST 2006 – REVISED MAY 2007
Contents
1
F28044 Digital Signal Processor ............................................................................................ 9
1.1
1.2
2
Introduction ....................................................................................................................... 11
2.1
2.2
3
3.3
3.4
3.5
3.6
3.7
4.6
4.7
4.8
4.9
21
23
23
23
24
24
24
24
24
25
26
27
27
27
27
27
27
28
28
28
28
29
29
30
31
33
34
36
38
40
32-Bit CPU-Timers 0/1/2 ..................................................................................................
Enhanced PWM Modules (ePWM1-16) .................................................................................
Hi-Resolution PWM (HRPWM) ...........................................................................................
Enhanced Analog-to-Digital Converter (ADC) Module ................................................................
4.5
ADC Connections if the ADC Is Not Used ...................................................................
Serial Communications Interface (SCI) Module (SCI-A) ..............................................................
Serial Peripheral Interface (SPI) Module (SPI-A) ......................................................................
Inter-Integrated Circuit (I2C)...............................................................................................
GPIO MUX ..................................................................................................................
41
43
48
49
52
54
57
60
62
Device Support .................................................................................................................. 66
5.1
5.2
2
Memory Map ................................................................................................................
Brief Descriptions...........................................................................................................
3.2.1
C28x CPU .......................................................................................................
3.2.2
Memory Bus (Harvard Bus Architecture) ....................................................................
3.2.3
Peripheral Bus ..................................................................................................
3.2.4
Real-Time JTAG and Analysis ................................................................................
3.2.5
Flash ..............................................................................................................
3.2.6
M0, M1 SARAMs ...............................................................................................
3.2.7
L0, L1 SARAMs .................................................................................................
3.2.8
Boot ROM ........................................................................................................
3.2.9
Security ..........................................................................................................
3.2.10 Peripheral Interrupt Expansion (PIE) Block ..................................................................
3.2.11 External Interrupts (XINT1, XINT2, XNMI) ...................................................................
3.2.12 Oscillator and PLL ..............................................................................................
3.2.13 Watchdog ........................................................................................................
3.2.14 Peripheral Clocking .............................................................................................
3.2.15 Low-Power Modes ..............................................................................................
3.2.16 Peripheral Frames 0, 1, 2 (PFn) ..............................................................................
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer .........................................................
3.2.18 32-Bit CPU-Timers (0, 1, 2) ...................................................................................
3.2.19 Control Peripherals .............................................................................................
3.2.20 Serial Port Peripherals .........................................................................................
Register Map ................................................................................................................
Device Emulation Registers...............................................................................................
Interrupts ....................................................................................................................
3.5.1
External Interrupts ..............................................................................................
System Control .............................................................................................................
3.6.1
OSC and PLL Block ............................................................................................
3.6.2
Watchdog Block .................................................................................................
Low-Power Modes Block ..................................................................................................
Peripherals ........................................................................................................................ 41
4.1
4.2
4.3
4.4
5
Pin Assignments............................................................................................................ 11
Signal Descriptions ......................................................................................................... 14
Functional Overview ........................................................................................................... 20
3.1
3.2
4
Features ....................................................................................................................... 9
Getting Started.............................................................................................................. 10
Device and Development Support Tool Nomenclature................................................................ 66
Documentation Support ................................................................................................... 68
Contents
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SPRS357B – AUGUST 2006 – REVISED MAY 2007
6
Electrical Specifications ...................................................................................................... 71
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
Absolute Maximum Ratings ............................................................................................... 71
Recommended Operating Conditions ................................................................................... 72
Electrical Characteristics ................................................................................................. 72
Current Consumption ..................................................................................................... 73
6.4.1
Reducing Current Consumption .............................................................................. 74
Emulator Connection Without Signal Buffering for the DSP .......................................................... 75
Timing Parameter Symbology ............................................................................................ 76
6.6.1
General Notes on Timing Parameters ........................................................................ 76
6.6.2
Test Load Circuit ................................................................................................ 77
6.6.3
Device Clock Table ............................................................................................. 77
Clock Requirements and Characteristics ............................................................................... 78
Power Sequencing ......................................................................................................... 79
6.8.1
Power Management and Supervisory Circuit Solutions .................................................... 79
General-Purpose Input/Output (GPIO) .................................................................................. 82
6.9.1
GPIO - Output Timing ........................................................................................... 82
6.9.2
GPIO - Input Timing ............................................................................................. 83
Enhanced Control Peripherals ............................................................................................ 88
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ......................................................... 88
6.10.2 Trip-Zone Input Timing.......................................................................................... 88
6.10.3 External Interrupt Timing ....................................................................................... 89
6.10.4 I2C Electrical Specification and Timing ....................................................................... 90
6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing ..................................................... 90
6.10.6 SPI Slave Mode Timing......................................................................................... 94
On-Chip Analog-to-Digital Converter .................................................................................... 97
6.11.1 ADC Power-Up Control Bit Timing ............................................................................ 98
6.11.2 Definitions ........................................................................................................ 99
6.11.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................. 100
6.11.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) ........................................... 101
Detailed Descriptions .................................................................................................... 102
Flash Timing ............................................................................................................... 103
Mechanical Data ............................................................................................................... 105
Contents
3
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Digital Signal Processor
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SPRS357B – AUGUST 2006 – REVISED MAY 2007
List of Figures
2-1
100-Pin PZ LQFP (Top View) ................................................................................................... 12
2-2
100-Ball GGM and ZGM MicroStar BGA™ (Bottom View) .................................................................. 13
3-1
Functional Block Diagram ........................................................................................................ 20
3-2
F28044 Memory Map ............................................................................................................. 21
3-3
External and PIE Interrupt Sources ............................................................................................. 31
3-4
Multiplexing of Interrupts Using the PIE Block ................................................................................ 32
3-5
Clock and Reset Domains ....................................................................................................... 34
3-6
...................................................................................................
Using a 3.3-V External Oscillator ...............................................................................................
Using a 1.8-V External Oscillator ...............................................................................................
Using the Internal Oscillator .....................................................................................................
Watchdog Module .................................................................................................................
CPU-Timers ........................................................................................................................
CPU-Timer Interrupt Signals and Output Signal ..............................................................................
Multiple PWM Modules ...........................................................................................................
ePWM Sub-Modules Showing Critical Internal Signal Interconnections ...................................................
Block Diagram of the ADC Module .............................................................................................
ADC Pin Connections With Internal Reference ...............................................................................
ADC Pin Connections With External Reference ..............................................................................
Serial Communications Interface (SCI) Module Block Diagram ............................................................
SPI Module Block Diagram (Slave Mode) .....................................................................................
I2C Peripheral Module Interfaces ...............................................................................................
GPIO MUX Block Diagram .......................................................................................................
Qualification Using Sampling Window..........................................................................................
Example of TMS320x280x Device Nomenclature ............................................................................
Emulator Connection Without Signal Buffering for the DSP.................................................................
3.3-V Test Load Circuit ...........................................................................................................
Clock Timing .......................................................................................................................
Power-on Reset ...................................................................................................................
Warm Reset........................................................................................................................
Example of Effect of Writing Into PLLCR Register ...........................................................................
General-Purpose Output Timing ................................................................................................
Sampling Mode ....................................................................................................................
General-Purpose Input Timing ..................................................................................................
IDLE Entry and Exit Timing ......................................................................................................
STANDBY Entry and Exit Timing Diagram ....................................................................................
HALT Wake-Up Using GPIOn ...................................................................................................
PWM Hi-Z Characteristics .......................................................................................................
ADCSOCAO or ADCSOCBO Timing ...........................................................................................
3-7
3-8
3-9
3-10
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
4
OSC and PLL Block Diagram
List of Figures
36
36
36
36
39
41
42
43
48
50
51
52
56
59
61
62
65
67
75
77
79
80
81
82
82
83
84
85
86
87
88
89
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SPRS357B – AUGUST 2006 – REVISED MAY 2007
6-15
External Interrupt Timing ......................................................................................................... 89
6-16
SPI Master Mode External Timing (Clock Phase = 0)........................................................................ 92
6-17
SPI Master External Timing (Clock Phase = 1) ............................................................................... 94
6-18
SPI Slave Mode External Timing (Clock Phase = 0) ......................................................................... 95
6-19
SPI Slave Mode External Timing (Clock Phase = 1) ......................................................................... 96
6-20
ADC Power-Up Control Bit Timing .............................................................................................. 98
6-21
ADC Analog Input Impedance Model........................................................................................... 99
6-22
Sequential Sampling Mode (Single-Channel) Timing ....................................................................... 100
6-23
Simultaneous Sampling Mode Timing ........................................................................................ 101
List of Figures
5
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Digital Signal Processor
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SPRS357B – AUGUST 2006 – REVISED MAY 2007
List of Tables
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6
...............................................................................................................
Signal Descriptions ...............................................................................................................
Addresses of Flash Sectors .....................................................................................................
Wait-states .........................................................................................................................
Boot Mode Selection..............................................................................................................
Peripheral Frame 0 Registers ...................................................................................................
Peripheral Frame 1 Registers ...................................................................................................
Peripheral Frame 2 Registers ...................................................................................................
Device Emulation Registers .....................................................................................................
PIE Peripheral Interrupts .........................................................................................................
PIE Configuration and Control Registers ......................................................................................
External Interrupt Registers ......................................................................................................
PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................
PLLCR Register Bit Definitions ..................................................................................................
Possible PLL Configuration Modes .............................................................................................
Low-Power Modes ................................................................................................................
CPU-Timers 0, 1, 2 Configuration and Control Registers ...................................................................
ePWM1-4 Control and Status Registers .......................................................................................
ePWM5-8 Control and Status Registers .......................................................................................
ePWM9-12 Control and Status Registers ......................................................................................
ePWM13-16 Control and Status Registers ....................................................................................
ADC Registers .....................................................................................................................
SCI-A Registers ...................................................................................................................
SPI-A Registers ...................................................................................................................
I2C-A Registers ....................................................................................................................
GPIO Registers ...................................................................................................................
F28044 GPIO MUX Table........................................................................................................
TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT .............................
Typical Current Consumption by Various Peripherals (at 100 MHz) .......................................................
TMS320x280x Clock Table and Nomenclature ...............................................................................
Input Clock Frequency ...........................................................................................................
XCLKIN Timing Requirements - PLL Enabled ................................................................................
XCLKIN Timing Requirements - PLL Disabled ................................................................................
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) .........................................................
Power Management and Supervisory Circuit Solutions ......................................................................
Reset (XRS) Timing Requirements ............................................................................................
General-Purpose Output Switching Characteristics ..........................................................................
General-Purpose Input Timing Requirements .................................................................................
IDLE Mode Timing Requirements...............................................................................................
Hardware Features
List of Tables
11
14
22
23
25
29
30
30
30
32
33
33
35
37
38
40
42
44
45
46
47
53
55
58
61
63
64
73
74
77
78
78
78
78
79
81
82
83
85
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SPRS357B – AUGUST 2006 – REVISED MAY 2007
6-13
IDLE Mode Switching Characteristics .......................................................................................... 85
6-14
STANDBY Mode Timing Requirements ........................................................................................ 85
6-15
.................................................................................. 86
HALT Mode Timing Requirements .............................................................................................. 86
HALT Mode Switching Characteristics ........................................................................................ 87
ePWM Timing Requirements .................................................................................................... 88
ePWM Switching Characteristics................................................................................................ 88
Trip-Zone input Timing Requirements .......................................................................................... 88
High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz) ................................................ 89
External ADC Start-of-Conversion Switching Characteristics ............................................................... 89
External Interrupt Timing Requirements ....................................................................................... 89
External Interrupt Switching Characteristics ................................................................................... 89
I2C Timing ......................................................................................................................... 90
SPI Master Mode External Timing (Clock Phase = 0)........................................................................ 91
SPI Master Mode External Timing (Clock Phase = 1)........................................................................ 93
SPI Slave Mode External Timing (Clock Phase = 0) ......................................................................... 94
SPI Slave Mode External Timing (Clock Phase = 1) ......................................................................... 95
ADC Electrical Characteristics (over recommended operating conditions)................................................ 97
ADC Power-Up Delays ........................................................................................................... 98
Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) .......................................... 98
Sequential Sampling Mode Timing ............................................................................................ 100
Simultaneous Sampling Mode Timing ........................................................................................ 101
Flash Endurance ................................................................................................................. 103
Flash Parameters at 100-MHz SYSCLKOUT ................................................................................ 103
Flash/OTP Access Timing ...................................................................................................... 103
Minimum Required Flash/OTP Wait-States at Different Frequencies .................................................... 104
F28044 Thermal Model 100-pin GGM Results .............................................................................. 105
F28044 Thermal Model 100-pin PZ Results ................................................................................. 105
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
7-1
7-2
STANDBY Mode Switching Characteristics
List of Tables
7
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Digital Signal Processor
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SPRS357B – AUGUST 2006 – REVISED MAY 2007
This data manual was revised from SPRS357A to SPRS357B.
Changes in This Revision
8
LOCATION
ADDITIONS, MODIFICATIONS, DELETIONS
Global
Document changed from Advance Information to Production Data to reflect device change from TMX to
TMS.
Section 1.1
Features list revised
Section 1.2
Added Getting Started Section
Section 4.5
Added subsection on pin connections when ADC is not used
Section 5.2
Updated the documents list in Documentation Support
Section 6.4.1
Added a note to the section on reducing current consumption
Table 6-28
Modified values on last two rows of table
Table 6-29
Modified values on last two rows of table
List of Tables
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Digital Signal Processor
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SPRS357B – AUGUST 2006 – REVISED MAY 2007
1
F28044 Digital Signal Processor
1.1
Features
•
•
•
•
•
•
•
•
High-Performance 100-MHz (10-ns Cycle Time)
Processor
TMS320C28x™ 32-Bit CPU
– Single-cycle 16 × 16 and 32 × 32
Multiply-accumulate (MAC) Operations
– Dual 16 × 16 MAC
– Fast Interrupt Response
– Unified Memory Programming Model
On-Chip Memory
– 64K × 16 Flash
– 10K × 16 SARAM
– 1K × 16 OTP
– 4K × 16 Boot ROM
– Code Security Module Protects Against
Unauthorized Memory Access
Clocking
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Clock-Fail-Detect Mode
Interrupts
– Support for up to Three External Core
Interrupts
– Peripheral Interrupt Expansion (PIE) Block
That Supports All Peripheral Interrupts
High-speed, 12-Bit ADC
– 80 ns (12.5 MSPS) Conversion Rate
– 16 Channels
– Two Sample-and-Hold
– Single/Simultaneous Conversions
– Internal or External Reference
High-Resolution PWM
– 16 Outputs with 150 ps Resolution
– 14.8 Bits at 200-KHz Switching
– 13.4 Bits at 500-KHz Switching
– 12.4 Bits at 1-MHz Switching
Communications Port Peripherals
•
•
•
•
•
•
•
•
•
(1)
– Serial Peripheral Interface (SPI) Module
– Serial Communications Interface (SCI)
– Inter-Integrated Circuit (I2C) Bus
Timers
– Three 32-bit CPU Timers
– Up to 16 16-bit Timers
– Watchdog Timer Module
Up to 35 General-Purpose Input/Output (GPIO)
Pins With Input Filtering
On-chip JTAG Emulation With Real-time
Debug via Hardware
JTAG Boundary Scan Support
Low-power IDLE, STANDBY, and HALT Modes
Development Tools
– F28044 eZdsp Starter Kit
– Code Composer Studio™ IDE With Flash
Programming Plug-in
– C28x-optimized ANSI C/C++
Compiler/Assembler/Linker
– DSP/BIOS™ Real-time Operating System
– USB-based JTAG Emulators (1)
Available Software
– C2000™ Digital Power Supply Software
Library
– C28x™ IQ Math Library
– C28x Header Files With Example Programs
for all Peripherals
– C28x DSP Library
– C28x Digital Motor Control Software Library
Package Options
– 100-pin Thin Quad Flatpack (PZ)
– 100-pin MicroStar BGA™ (GGM, ZGM)
– RoHS-compliant, Green Packaging
Temperature Range:
-40°C to 85°C (PZ, GGM, ZGM)
IEEE Standard 1149.1-1990 Standard Test Access Port and
Boundary Scan Architecture
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
TMS320C28x, Code Composer Studio, DSP/BIOS, C2000, C28x, MicroStar BGA, TMS320 are trademarks of Texas Instruments.
eZdsp, XDS510USB are trademarks of Spectrum Digital.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
TMS320F28044
Digital Signal Processor
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SPRS357B – AUGUST 2006 – REVISED MAY 2007
1.2
Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more
detail on each of these steps, see the following:
• Getting Started With TMS320C28x™ Digital Signal Controllers (literature number SPRAAM0).
• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)
Step 1. Acquire the appropriate development tools
The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initial
development, which, in one package, includes:
• On-board JTAG emulation via USB or parallel port
• Appropriate emulation driver
• Code Composer Studio™ IDE for eZdsp
Once you have become familiar with the device and begin developing on your own
hardware, purchase Code Composer Studio™ IDE separately for software development and
a JTAG emulation tool to get started on your project.
Step 2. Download starter software
To simplify programming for C28x devices, it is recommended that users download and use
the C/C++ Header Files and Example(s) to begin developing software for the C28x devices
and their various peripherals.
After downloading the appropriate header file package for your device, refer to the following
resources for step-by-step instructions on how to run the peripheral examples and use the
header file structure for your own software
• The Quick Start Readme in the /doc directory to run your first application.
• Programming TMS320x28xx and 28xxx Peripherals in C/C++ Application Report
(literature number SPRAA85)
Step 3. Download flash programming software
Many C28x devices include on-chip flash memory and tools that allow you to program the
flash with your software IP.
• Flash Tools: C28x Flash Tools
• TMS320F281x Flash Programming Solutions (literature number SPRB169)
• Running an Application from Internal Flash Memory on the TMS320F28xx DSP (literature
number SPRA958)
Step 4. Move on to more advanced topics
For more application software and other advanced topics, visit the TI website at
http://www.ti.com or http://www.ti.com/c2000getstarted.
10
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2
Introduction
The TMS320F28044 device, member of the TMS320C28x™ DSP generation, is a highly integrated,
high-performance solution for demanding control applications.
Throughout this document, TMS320F28044 is abbreviated as F28044. Table 2-1 provides a summary of
the device's features.
Table 2-1. Hardware Features
FEATURE
F28044
Instruction cycle (at 100 MHz)
10 ns
10K
(L0, L1, M0, M1)
Single-access RAM (SARAM) (16-bit word)
3.3-V on-chip flash (16-bit word)
64K
On-chip ROM (16-bit word)
–
Code security for on-chip flash/SARAM/OTP blocks
Yes
Boot ROM (4K X16)
Yes
One-time programmable (OTP) ROM
(16-bit word)
1K
PWM outputs (one 16-bit timer/module)
ePWM1-16
HRPWM channels
ePWM1-16
Watchdog timer
Yes
No. of channels
12-Bit ADC
16
MSPS
12.5
Conversion time
80 ns
32-Bit CPU timers
3
Serial Peripheral Interface (SPI)
SPI-A
Serial Communications Interface (SCI)
SCI-A
Inter-Integrated Circuit (I2C)
I2C-A
Digital I/O pins (shared)
35
External interrupts
3
Supply voltage
1.8-V Core, 3.3-V I/O
Yes
Packaging
100-Pin PZ
Yes
100-ball GGM, ZGM
Yes
Temperature options
A: -40°C to 85°C
Product status (1)
(1)
2.1
(PZ, GGM, ZGM)
TMS
See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.
Pin Assignments
The TMS320F28044 100-pin PZ low-profile quad flatpack (LQFP) pin assignments are shown in
Figure 2-1. The 100-ball GGM and ZGM ball grid array (BGA) terminal assignments are shown in
Figure 2-2. Table 2-2 describes the function(s) of each pin.
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GPIO5/EPWM6A
GPIO17/SPISOMIA/TZ6
GPIO4/EPWM5A
51
52
54
53
GPIO6/EPWM7A/EPWMSYNCI/EPWMSYNCO
VSS
GPIO18/SPICLKA/TZ1
55
57
56
VDD
GPIO7/EPWM8A
GPIO19/SPISTEA/TZ2
59
58
GPIO9/EPWM10A
GPIO8/EPWM9A/ADCSOCAO
61
60
63
62
VDDIO
GPIO10/EPWM11A/ADCSOCBO
GPIO20
VSS
65
64
GPIO21
XCLKOUT
67
66
69
68
71
70
TDI
GPIO23
GPIO22
GPIO11/EPWM12A
VSS
VDD
73
72
TCK
TMS
75
74
SPRS357B – AUGUST 2006 – REVISED MAY 2007
TDO
VSS
76
50
GPIO16/SPISIMOA/TZ5
77
49
VSS
XRS
GPIO27
78
48
79
47
EMU0
80
46
GPIO3/EPWM4A
GPIO0/EPWM1A
VDDIO
EMU1
VDDIO
81
45
82
44
GPIO24
83
43
TRST
84
42
GPIO34
VDD
VDD
X2
85
41
VSS
86
40
VSS
X1
87
39
VDD2A18
VSS2AGND
88
38
ADCRESEXT
VSS
89
37
XCLKIN
90
36
ADCREFP
ADCREFM
GPIO2/EPWM3A
GPIO1/EPWM2A
ADCINB0
VDDAIO
24
ADCINA0
ADCLO
VSSAIO
25
22
23
ADCINA3
ADCINA2
ADCINA1
ADCINA6
ADCINA5
ADCINA4
16
11
12
9
GPIO15/TZ4/EPWM16A
VDD
VSS
VDD1A18
GPIO31/TZ4
GPIO14/TZ3/EPWM15A
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO30/TZ3
VDDIO
GPIO29/SCITXDA/TZ6
VSS
GPIO12/TZ1/EPWM13A
21
26
19
100
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
20
ADCINB1
27
17
28
99
18
98
15
TEST2
GPIO26
VDDA2
ADCINA7
ADCINB3
ADCINB2
13
29
14
97
VSSA2
30
TEST1
VSS1AGND
31
96
10
95
7
GPIO13/TZ2/EPWM14A
VDD3VFL
8
32
5
33
94
6
93
VSS
3
34
4
35
92
1
91
2
GPIO25
GPIO28/SCIRXDA/TZ5
VDD
ADCREFIN
ADCINB7
ADCINB6
ADCINB5
ADCINB4
Figure 2-1. 100-Pin PZ LQFP (Top View)
12
Introduction
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K
VSSAIO
ADCINB0
ADCINB3
ADCINB5
ADCINB7
VSS2AGND
GPIO1
GPIO0
VSS
GPIO16
J
ADCLO
VDDAIO
ADCINB1
ADCINB4
ADCREFIN
VDD2A18
GPIO2
GPIO3
GPIO4
GPIO17
ADCINA1
ADCINA0
ADCINB2
ADCINB6
ADCREFM
VSS
VDDIO
GPIO18
GPIO5
VSS
ADCINA4
ADCINA3
ADCINA2
ADCINA5
ADCREFP
VDD
GPIO34
GPIO7
GPIO6
GPIO19
VSSA2
VDDA2
ADCINA7
ADCINA6
ADCRESEXT
GPIO20
VSS
GPIO9
GPIO8
VDD
GPIO15
VDD
VSS
VDD1A18
VSS1AGND
X1
GPIO21
XCLKOUT
VDDIO
GPIO10
GPIO31
GPIO30
GPIO14
VDD
GPIO28
VSS
VDD
GPIO22
GPIO11
VSS
GPIO33
VDDIO
GPIO29
VDD3VFL
GPIO25
X2
GPIO24
GPIO27
TDI
GPIO23
VSS
GPIO12
TEST2
GPIO13
XCLKIN
VDD
EMU1
XRS
TDO
TMS
GPIO32
GPIO26
TEST1
VSS
VSS
TRST
VDDIO
EMU0
VSS
TCK
1
2
3
4
5
6
7
8
9
10
H
G
F
E
D
C
B
A
Bottom View
Figure 2-2. 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)
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Digital Signal Processor
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2.2
Signal Descriptions
Table 2-2 describes the signals on the F28044 device. All digital inputs are TTL-compatible. All outputs
are 3.3 V with CMOS levels. Inputs are not 5-V tolerant.
Table 2-2. Signal Descriptions
PIN NO.
NAME
PZ
PIN #
GGM/
ZGM
BALL #
DESCRIPTION
(1)
JTAG
TRST
84
A6
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
high test pin and must be maintained low at all times during normal device operation. In a low-noise
environment, TRST may be left floating. In other instances, an external pulldown resistor is highly
recommended. The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board be validated for proper operation of
the debugger and the application. (I, ↓)
TCK
75
A10
JTAG test clock with internal pullup (I, ↑)
TMS
74
B10
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)
TDI
73
C9
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)
TDO
76
B9
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
A8
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
(I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
B7
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
(I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
EMU0
80
EMU1
81
FLASH
VDD3VFL
96
C4
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM
parts (C280x), this pin should be connected to VDDIO.
TEST1
97
A3
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2
98
B3
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
XCLKOUT
66
E8
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0
(XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal
can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not
placed in high-impedance state during a reset. (O/Z, 8 mA drive).
XCLKIN
90
B5
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is
used to feed clock to X1 pin), this pin must be tied to GND. (I)
(1)
14
I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
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Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME
PZ
PIN #
GGM/
ZGM
BALL #
DESCRIPTION
(1)
X1
88
E6
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital
power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must
be tied to GND. (I)
X2
86
C6
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
X2. If X2 is not used it must be left unconnected. (O)
RESET
XRS
78
B8
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
The output buffer of this pin is an open-drain with an internal pullup (100 µA, typical). It is
recommended that this pin be driven by an open-drain device.
ADCINA7
16
F3
ADC Group A, Channel 7 input (I)
ADCINA6
17
F4
ADC Group A, Channel 6 input (I)
ADCINA5
18
G4
ADC Group A, Channel 5 input (I)
ADCINA4
19
G1
ADC Group A, Channel 4 input (I)
ADCINA3
20
G2
ADC Group A, Channel 3 input (I)
ADCINA2
21
G3
ADC Group A, Channel 2 input (I)
ADCINA1
22
H1
ADC Group A, Channel 1 input (I)
ADCINA0
23
H2
ADC Group A, Channel 0 input (I)
ADCINB7
34
K5
ADC Group B, Channel 7 input (I)
ADCINB6
33
H4
ADC Group B, Channel 6 input (I)
ADCINB5
32
K4
ADC Group B, Channel 5 input (I)
ADCINB4
31
J4
ADC Group B, Channel 4 input (I)
ADCINB3
30
K3
ADC Group B, Channel 3 input (I)
ADCINB2
29
H3
ADC Group B, Channel 2 input (I)
ADCINB1
28
J3
ADC Group B, Channel 1 input (I)
ADCINB0
27
K2
ADC Group B, Channel 0 input (I)
ADCLO
24
J1
Low Reference (connect to analog ground) (I)
ADCRESEXT
38
F5
ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
ADCREFIN
35
J5
External reference input (I)
ADCREFP
37
G5
Internal Reference Positive Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitor
of 2.2 µF to analog ground. (O)
ADCREFM
36
H5
Internal Reference Medium Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitor
of 2.2 µF to analog ground. (O)
VDDA2
15
F2
ADC Analog Power Pin (3.3 V)
VSSA2
14
F1
ADC Analog Ground Pin
VDDAIO
26
J2
ADC Analog I/O Power Pin (3.3 V)
VSSAIO
25
K1
ADC Analog I/O Ground Pin
VDD1A18
12
E4
ADC Analog Power Pin (1.8 V)
VSS1AGND
13
E5
ADC Analog Ground Pin
VDD2A18
40
J6
ADC Analog Power Pin (1.8 V)
VSS2AGND
39
K6
ADC Analog Ground Pin
ADC SIGNALS
CPU AND I/O POWER PINS
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Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME
PZ
PIN #
GGM/
ZGM
BALL #
VDD
10
E2
VDD
42
G6
VDD
59
F10
VDD
68
D7
VDD
85
B6
VDD
93
D4
VDDIO
3
C2
VDDIO
46
H7
VDDIO
65
E9
VDDIO
82
A7
VSS
2
B1
VSS
11
E3
VSS
41
H6
VSS
49
K9
VSS
55
H10
VSS
62
F7
VSS
69
D10
VSS
77
A9
VSS
87
D6
VSS
89
A5
VSS
94
A4
DESCRIPTION
(1)
CPU and Logic Digital Power Pins (1.8 V)
Digital I/O Power Pin (3.3 V)
Digital Ground Pins
GPIOA AND PERIPHERAL SIGNALS (2)
GPIO0
EPWM1A
GPIO1
EPWM2A
GPIO2
EPWM3A
GPIO3
EPWM4A
GPIO4
EPWM5A
GPIO5
EPWM6A
-
(2)
(3)
16
47
44
45
48
51
53
K8
General purpose input/output 0 (I/O/Z) (3)
Enhanced PWM1 Output and HRPWM channel (O)
-
K7
General purpose input/output 1 (I/O/Z) (3)
Enhanced PWM2 Output A and HRPWM channel (O)
-
J7
General purpose input/output 2 (I/O/Z) (3)
Enhanced PWM3 Output A and HRPWM channel (O)
-
J8
General purpose input/output 3 (I/O/Z) (3)
Enhanced PWM4 Output A and HRPWM channel (O)
-
J9
General purpose input/output 4 (I/O/Z) (3)
Enhanced PWM5 output A and HRPWM channel (O)
-
H9
General purpose input/output 5 (I/O/Z) (3)
Enhanced PWM6 Output A and HRPWM channel (O)
-
All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.
The pullups on GPIO0-GPIO15 pins are not enabled at reset.
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Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME
PZ
PIN #
GGM/
ZGM
BALL #
DESCRIPTION
GPIO6
EPWM7A
EPWMSYNCI
EPWMSYNCO
56
G9
General purpose input/output 6 (I/O/Z) (3)
Enhanced PWM7 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
EPWM8A
-
58
G8
General purpose input/output 7 (I/O/Z) (3)
Enhanced PWM8 Output A and HRPWM channel (O)
-
GPIO8
EPWM9A
ADCSOCAO
60
F9
General purpose input/output 8 (I/O/Z) (3)
Enhanced PWM9 output A(O)
ADC start-of-conversion A (O)
GPIO9
EPWM10A
-
61
F8
General purpose input/output 9 (I/O/Z) (3)
Enhanced PWM10 Output A and HRPWM channel (O)
-
GPIO10
EPWM11A
ADCSOCBO
64
E10
General purpose input/output 10 (I/O/Z) (3)
Enhanced PWM11 Output A and HRPWM channel (O)
ADC start-of-conversion B (O)
GPIO11
EPWM12A
-
70
D9
General purpose input/output 11 (I/O/Z) (3)
Enhanced PWM12 Output A and HRPWM channel (O)
-
B2
General purpose input/output 12 (I/O/Z) (4)
Trip Zone input 1 (I)
Enhanced PWM13 Output A and HRPWM channel (O)
-
B4
General purpose input/output 13 (I/O/Z) (4)
Trip zone input 2 (I)
Enhanced PWM14 Output A and HRPWM channel (O)
-
D3
General purpose input/output 14 (I/O/Z) (4)
Trip zone input 3 (I)
Enhanced PWM15 Output A and HRPWM channel (O)
-
E1
General purpose input/output 15 (I/O/Z) (4)
Trip zone input 4 (I)
Enhanced PWM16 Output A and HRPWM channel (O)
-
K10
General purpose input/output 16 (I/O/Z) (4)
SPI-A slave in, master out (I/O)
Trip zone input 5 (I)
J10
General purpose input/output 17 (I/O/Z) (4)
SPI-A slave out, master in (I/O)
Trip zone input 6(I)
H8
General purpose input/output 18 (I/O/Z) (4)
SPI-A clock input/output (I/O)
Trip zone input 1 (I)
GPIO12
TZ1
EPWM13A
GPIO13
TZ2
EPWM14A
GPIO14
TZ3
EPWM15A
GPIO15
TZ4
EPWM16A
GPIO16
SPISIMOA
TZ5
GPIO17
SPISOMIA
TZ6
GPIO18
SPICLKA
TZ1
GPIO19
SPISTEA
TZ2
GPIO20
(4)
1
95
8
9
50
52
54
57
G10
63
F6
(1)
General purpose input/output 19 (I/O/Z) (4)
SPI-A slave transmit enable input/output (I/O)
Trip zone input 2 (I)
General purpose input/output 20 (I/O/Z) (4)
-
The pullups on GPIO16-GPIO34 are enabled upon reset.
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Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
SCIRXDA
TZ5
GPIO29
SCITXDA
TZ6
GPIO30
TZ3
GPIO31
TZ4
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
18
Introduction
PZ
PIN #
67
71
72
83
91
99
79
92
4
6
7
100
GGM/
ZGM
BALL #
DESCRIPTION
(1)
E7
General purpose input/output 21 (I/O/Z) (4)
-
D8
General purpose input/output 22 (I/O/Z) (4)
-
C10
General purpose input/output 23 (I/O/Z) (4)
-
C7
General purpose input/output 24 (I/O/Z) (4)
-
C5
General purpose input/output 25 (I/O/Z) (4)
-
A2
General purpose input/output 26 (I/O/Z) (4)
-
C8
General purpose input/output 27 (I/O/Z) (4)
-
D5
General purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z) (4)
SCI receive data (I)
Trip zone 5 (I)
C3
General purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z) (4)
SCI transmit data (O)
Trip zone 6 (I)
D2
General purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z) (4)
Trip zone input 3 (I)
D1
General purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z) (4)
Trip zone input 4 (I)
A1
General purpose input/output 32 (I/O/Z) (4)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion (O)
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Table 2-2. Signal Descriptions (continued)
PIN NO.
NAME
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
GPIO34
(1)
PZ
PIN #
5
43
GGM/
ZGM
BALL #
DESCRIPTION
C1
General-Purpose Input/Output 33 (I/O/Z) (1)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion (O)
G7
General-Purpose Input/Output 34 (I/O/Z) (1)
-
(1)
The pullups on GPIO16-GPIO34 are enabled upon reset.
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3
Functional Overview
Memory Bus
TINT0
32-bit CPU TIMER 0
TINT1
7
32-bit CPU TIMER 1
TINT2
Real-Time JTAG
(TDI, TDO, TRST, TCK,
TMS, EMU0, EMU1)
32-bit CPU TIMER 2
INT14
PIE
(96 Interrupts)(A)
INT[12:1]
M0 SARAM
1 K 16
NMI, INT13
External Interrupt
Control
32
4
SCI-A
FIFO
16
2
FIFO
I2C-A
FIFO
L0 SARAM
4 K 16
(0-wait)
L1 SARAM(B)
4 K 16
(0-wait)
GPIO MUX
GPIOs
(35)
SPI-A
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
M1 SARAM
1 K 16
ePWM1−16
(16 PWM outputs,
6 trip zones,
6 timers 16-bit)
16
C28x CPU
(100 MHz)
FLASH
64K x 16
32
SYSCLKOUT
System Control
XCLKOUT
RS
XRS
(Oscillator, PLL,
Peripheral Clocking,
Low Power Modes,
WatchDog)
XCLKIN
X1
X2
CLKIN
OTP(D)
1K 16
ADCSOCA/B
ÍÍÍ
ÍÍÍ
ÍÍÍ
ÍÍÍ
SOCA/B
Boot ROM
4 K 16
(1-wait state)
12-Bit ADC
16 Channels
Protected by the code-security module.
Peripheral Bus
A.
43 of the possible 96 interrupts are used on the devices.
B.
The 1K x 16 OTP has been replaced with 1K x 16 ROM for the F28044 device.
Figure 3-1. Functional Block Diagram
20
Functional Overview
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3.1
Memory Map
Block Start
Address
Data Space
Prog Space
0x00 0000
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
M0 SARAM (1K y 16)
0x00 0400
M1 SARAM (1K y 16)
Low 64K [0000−FFFF]
(24x/240x equivalent data space)
0x00 0800
Peripheral Frame 0
0x00 0D00
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
0x00 0E00
0x00 6000
Peripheral Frame 1
(protected)
0x00 7000
Peripheral Frame 2
(protected)
0x00 8000
0x00 9000
0x00 A000
0x3D 7800
L0 SARAM (0-wait)
(4k y 16, Secure Zone, Dual Mapped)
L1 SARAM (0-wait)
(4k y 16, Secure Zone, Dual Mapped)
OTP
(1 K y 16, Secure Zone)
0x3D 7C00
High 64K [3F0000 −3FFFF]
(24x/240x equivalent program space)
0x3E 8000
0x3F 7FF8
FLASH
64 K y 16, Secure Zone)
128-bit Password
0x3F 8000
L0 SARAM (0-wait) (4k y 16,
Secure Zone, Dual Mapped)
0x3F 9000
L1 SARAM (0-wait) (4k y 16,
Secure Zone, Dual Mapped)
0x3F A000
0x3F F000
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
0x3F FFC0
Boot ROM (4 K y 16)
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
Reserved
A.
Memory blocks are not to scale.
B.
Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
C.
“ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
D.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 3-2. F28044 Memory Map
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Table 3-1. Addresses of Flash Sectors
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3E 8000 - 0x3E BFFF
Sector D (16K x 16)
0x3E C000 - 0x3E FFFF
Sector C (16K x 16)
0x3F 0000 - 0x3F 3FFF
Sector B (16K x 16)
0x3F 4000 - 0x3F 7F7F
Sector A (16K x 16)
0x3F 7F80 - 0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6 - 0x3F 7FF7
Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8 - 0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be
write/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different
memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems
in certain peripheral applications where the user expected the write to occur first (as written). The C28x
CPU supports a block protection mode where a region of memory can be protected so as to make sure
that operations occur as written (the penalty is extra cycles are added to align the operations). This mode
is programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 3-2.
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Table 3-2. Wait-states
AREA
WAIT-STATES
M0 and M1 SARAMs
0-wait
Fixed
Peripheral Frame 0
0-wait
Fixed
Peripheral Frame 1
0-wait (writes)
2-wait (reads)
Fixed.
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
Fixed
L0 & L1 SARAMs
0-wait
OTP
Programmed via the Flash registers. 1-wait-state operation
Programmable,
is possible at a reduced CPU frequency. See Section
1-wait minimum
Section 3.2.5 for more information.
Flash
Programmed via the Flash registers. 0-wait-state operation
Programmable, is possible at reduced CPU frequency. The CSM password
0-wait minimum locations are hardwired for 16 wait-states. See Section
Section 3.2.5 for more information.
Boot-ROM
3.2
3.2.1
COMMENTS
1-wait
Fixed
Brief Descriptions
C28x CPU
The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is a
very efficient C/C++ engine, hence enabling users to develop not only their system control software in a
high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as
efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller
devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC
capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher
numerical resolution problems that would otherwise demand a more expensive floating-point processor
solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in
a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to
execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead
hardware minimizes the latency for conditional discontinuities. Special store conditional operations further
improve performance.
3.2.2
Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed "Harvard Bus", enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes
(Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Lowest:
Program Reads
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Fetches
(Simultaneous program reads and fetches cannot occur on the memory bus.)
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3.2.3
Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the
F28044 device adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16
address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus
are supported on the F28044. One version only supports 16-bit accesses (called peripheral frame 2). The
other version supports both 16- and 32-bit accesses (called peripheral frame 1).
3.2.4
Real-Time JTAG and Analysis
The F28044 device implements the standard IEEE 1149.1 JTAG interface. Additionally, the device
supports real-time mode of operation whereby the contents of memory, peripheral and register locations
can be modified while the processor is running and executing code and servicing interrupts. The user can
also single step through non-time critical code while enabling time-critical interrupts to be serviced without
interference. The F28044 implements the real-time mode in hardware within the CPU. This is a unique
feature to the F28044, no software monitor is required. Additionally, special analysis hardware is provided
which allows the user to set hardware breakpoint or data/address watch-points and generate various
user-selectable break events when a match occurs.
3.2.5
Flash
The F28044 contains 64K x 16 of embedded flash memory, segregated into four 16K X 16 sectors. Both
devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The
user can individually erase, program, and validate a flash sector while leaving other sectors untouched.
However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that
erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve
higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used
to execute code or store data information. Note that addresses 0x3F7FF0 – 0x3F7FF5 are reserved for
data variables and should not contain program code.
NOTE
The F28044 Flash and OTP wait-states can be configured by the application. This allows
applications running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the TMS320x280x, 2801x, 2804x System Control and Interrupts Reference Guide
(literature number SPRU712).
3.2.6
M0, M1 SARAMs
The F28044 device contains these two blocks (M0/M1) of single access memory, each 1K x 16 in size.
The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other
memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use
M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x
device presents a unified memory map to the programmer. This makes for easier programming in
high-level languages.
3.2.7
L0, L1 SARAMs
The F28044 device contains an additional 8K x 16 of single-access RAM, divided into 2 blocks (L0-4K,
L1-4K). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is
mapped to both program and data space.
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3.2.8
Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math related algorithms.
Table 3-3. Boot Mode Selection
MODE
DESCRIPTION
GPIO18
SPICLKA
GPIO29
SCITXDA
GPIO34
Boot to Flash/ROM
Jump to Flash/ROM address 0x3F 7FF6
You must have programmed a branch instruction here prior
to reset to redirect code execution as desired.
1
1
1
SCI-A Boot
Load a data stream from SCI-A
1
1
0
SPI-A Boot
Load from an external serial SPI EEPROM on SPI-A
1
0
1
I2C
Load data from an external EEPROM at address 0x50 on
the I2C bus
1
0
0
eCAN-A Boot
Reserved. This mode should not be used.
0
1
1
Boot to M0 SARAM
Jump to M0 SARAM address 0x00 0000.
0
1
0
Boot to OTP
Jump to OTP address 0x3D 7800
0
0
1
Parallel I/O Boot
Load data from GPIO0 - GPIO15
0
0
0
Boot
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3.2.9
Security
The device supports high levels of security to protect the user firmware from being reverse engineered.
The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the
flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks.
The security feature prevents unauthorized users from examining the memory contents via the JTAG port,
executing code from external memory or trying to boot-load some undesirable software that would export
the secure memory contents. To enable access to the secure blocks, the user must write the correct
128-bit "KEY" value, which matches the value stored in the password locations within the Flash.
NOTE
For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be
used as program code or data, but must be programmed to 0x0000 when the Code
Security Password is programmed. If security is not a concern, addresses 0x3F7F80
through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are
reserved for data variables and should not contain program code.
The 128-bit password (at 0x3F 7FF8 - 0x3F 7FFF) must not be programmed to zeros.
Doing so would permanently lock the device.
NOTE
Code Security Module Disclaimer
THE CODE SECURITY MODULE ("CSM") INCLUDED ON THIS DEVICE WAS
DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED
MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS
INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND
CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE
WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER,
EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN
ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
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3.2.10
Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F28044 device, 43 of the possible 96
interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed
into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector
stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched
by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical
CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is
controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE
block.
3.2.11
External Interrupts (XINT1, XINT2, XNMI)
The F28044 device supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be
connected to the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative,
positive, or both negative and positive edge triggering and can also be enabled/disabled (including the
XNMI). The masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a
valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike
the 281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can
be configured to trigger any external interrupt.
3.2.12
Oscillator and PLL
The F28044 device can be clocked by an external oscillator or by a crystal attached to the on-chip
oscillator circuit. A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be
changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power
operation is desired. Refer to the Electrical Specification section for timing details. The PLL block can be
set in bypass mode.
3.2.13
Watchdog
The F28044 device contains a watchdog timer. The user software must regularly reset the watchdog
counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The
watchdog can be disabled if necessary.
3.2.14
Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) and the ADC
blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled
from increasing CPU clock speeds.
3.2.15
Low-Power Modes
The F28044 device is full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral or the watchdog timer will wake the processor from IDLE mode.
STANDBY:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event
HALT:
Turns off the internal oscillator. This mode basically shuts down the device and places it in
the lowest possible power consumption mode. A reset or external signal can wake the
device from this mode.
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3.2.16
Peripheral Frames 0, 1, 2 (PFn)
The F28044 device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0:
PF1:
PF2:
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash:
Flash Control, Programming, Erase, Verify Registers
Timers:
CPU-Timers 0, 1, 2 Registers
CSM:
Code Security Module KEY Registers
ADC:
ADC Result Registers (dual-mapped)
GPIO:
GPIO MUX Configuration and Control Registers
ePWM:
Enhanced Pulse Width Modulator Module and Registers
SYS:
System Control Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
SPI:
Serial Port Interface (SPI) Control and RX/TX Registers
ADC:
ADC Status, Control, and Result Register
2
I C:
3.2.17
Inter-Integrated Circuit Module and Registers
General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
3.2.18
32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for Real-Time OS (RTOS)/BIOS applications. CPU-Timer 1 is also reserved for TI system
functions. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be connected to INT13 of
the CPU. CPU-Timer 0 is for general use and is connected to the PIE block.
3.2.19
Control Peripherals
The F28044 device supports the following peripherals which are used for embedded control and
communication:
28
ePWM:
The enhanced PWM peripheral supports independent/complementary PWM generation,
adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip
mechanism. Some of the PWM pins support HRPWM features.
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
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3.2.20
Serial Port Peripherals
The F28044 device supports the following serial communication peripherals:
3.3
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multi-device communications are supported by the master/slave
operation of the SPI. On the F28044 device, the SPI contains a 16-level receive and
transmit FIFO for reducing interrupt servicing overhead.
SCI:
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F28044 device, the SCI contains a 16-level receive and transmit
FIFO for reducing interrupt servicing overhead.
I2C:
The inter-integrated circuit (I2C) module provides an interface between a DSP and other
devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version
2.1 and connected by way of an I2C-bus. External components attached to this 2-wire
serial bus can transmit/receive up to 8-bit data to/from the DSP through the I2C module.
On the F28044 device, the I2C contains a 16-level receive and transmit FIFO for reducing
interrupt servicing overhead.
Register Map
The F28044 device contains three peripheral register spaces. The spaces are categorized as follows:
Peripheral
Frame 0:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-4
Peripheral
Frame 1
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 3-5
Peripheral
Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 3-6
Table 3-4. Peripheral Frame 0 Registers (1) (2)
NAME
ACCESS TYPE (3)
ADDRESS RANGE
SIZE (x16)
Device Emulation Registers
0x0880 - 0x09FF
384
EALLOW protected
Registers (4)
0x0A80 - 0x0ADF
96
EALLOW protected
CSM Protected
0x0AE0 - 0x0AEF
16
EALLOW protected
FLASH
Code Security Module Registers
ADC Result Registers (dual-mapped)
0xB00 - 0xB0F
16
CPU-TIMER0/1/2 Registers
0x0C00 - 0x0C3F
64
PIE Registers
0x0CE0 - 0x0CFF
32
PIE Vector Table
0x0D00 - 0x0DFF
256
(1)
(2)
(3)
(4)
Not EALLOW protected
EALLOW protected
Registers in Frame 0 support 16-bit and 32-bit accesses.
Missing segments of memory space are reserved and should not be used in applications.
If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).
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Table 3-5. Peripheral Frame 1 Registers (1) (2)
NAME
ADDRESS RANGE
SIZE (x16)
0x6800 - 0x683F
64
ePWM2 + HRPWM Registers
0x6840 - 0x687F
64
ePWM3 + HRPWM Registers
0x6880 - 0x68BF
64
ePWM4 + HRPWM Registers
0x68C0 - 0x68FF
64
ePWM5 + HRPWM Registers
0x6900 - 0x693F
64
ePWM6 + HRPWM Registers
0x6940 - 0x697F
64
ePWM7 + HRPWM Registers
0x6980 - 0x69BF
64
ePWM8 + HRPWM Registers
0x69C0 - 0x69FF
64
ePWM9 + HRPWM Registers
0x6600 - 0x663F
64
ePWM10 + HRPWM Registers
0x6640 - 0x667F
64
ePWM11 + HRPWM Registers
0x6680 - 0x66BF
64
ePWM12 + HRPWM Registers
0x66C0 - 0x66FF
64
ePWM13 + HRPWM Registers
0x6700 - 0x673F
64
ePWM14 + HRPWM Registers
0x6740 - 0x677F
64
ePWM15 + HRPWM Registers
0x6780 - 0x67BF
64
ePWM16 + HRPWM Registers
0x67C0 - 0x67FF
64
GPIO Control Registers
0x6F80 - 0x6FBF
128
EALLOW protected
GPIO Data Registers
0x6FC0 - 0x6FDF
32
Not EALLOW protected
GPIO Interrupt and LPM Select Registers
0x6FE0 - 0x6FFF
32
EALLOW protected
ePWM1 + HRPWM Registers
(1)
(2)
ACCESS TYPE
Some ePWM registers are EALLOW
protected.
See Table 4-2
All 32-bit accesses are aligned to even address boundaries.
Missing segments of memory space are reserved and should not be used in applications.
Table 3-6. Peripheral Frame 2 Registers (1) (2)
ADDRESS RANGE
SIZE (x16)
System Control Registers
NAME
0x7010 - 0x702F
32
SPI-A Registers
0x7040 - 0x704F
16
SCI-A Registers
0x7050 - 0x705F
16
External Interrupt Registers
0x7070 - 0x707F
16
ADC Registers
0x7100 - 0x711F
32
I2C Registers
0x7900 - 0x792F
48
(1)
(2)
ACCESS TYPE
EALLOW Protected
Not EALLOW Protected
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
Missing segments of memory space are reserved and should not be used in applications.
3.4
Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 3-7.
Table 3-7. Device Emulation Registers
NAME
ADDRESS RANGE
SIZE (x16)
DEVICECNF
0x0880
0x0881
2
Device Configuration Register
PARTID
0x0882
1
Part ID Register
0x00FC - F28044
REVID
0x0883
1
Revision ID Register
0x0000 - Silicon Rev. 0 - TMX or TMS
PROTSTART
0x0884
1
Block Protection Start Address Register
PROTRANGE
0x0885
1
Block Protection Range Address Register
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3.5
Interrupts
Figure 3-3 shows how the various interrupt sources are multiplexed within the F28044 device.
Peripherals
(SPI, SCI, I2C, ePWM, ADC)
WDINT
WAKEINT
XINT1
XINT1
Interrupt Control
Low Power Modes
MUX
LPMINT
Watchdog
96 Interrupts
XINT1CTR(15:0)
GPIOXINT1SEL(4:0)
XINT2SOC
ADC
XINT2
C28
MUX
INT1 to
INT12
PIE
XINT1CR(15:0)
XINT2
Interrupt Control
XINT2CR(15:0)
CPU
XINT2CTR(15:0)
GPIOXINT2SEL(4:0)
TINT0
CPU TIMER 0
TINT2
INT14
CPU TIMER 2 (for TI/RTOS)
TINT1
INT13
MUX
CPU TIMER 1 (for TI)
int13_select
nmi_select
GPIO0.int
MUX
NMI
GPIO
MUX
XNMI_XINT13
Interrupt Control
XNMICR(15:0)
MUX
GPIO31.int
1
XNMICTR(15:0)
GPIOXNMISEL(4:0)
Figure 3-3. External and PIE Interrupt Sources
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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the F28044 device, 43 of these are used by
peripherals as shown in Table 3-8.
IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
(Flag)
INTx
Global
Enable
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
MUX
PIEACKx
(Enable/Flag)
(Enable)
(Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
From
Peripherals or
External
Interrupts
Figure 3-4. Multiplexing of Interrupts Using the PIE Block
Table 3-8. PIE Peripheral Interrupts (1)
CPU
INTERRUPTS
(1)
32
PIE INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INT1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
XINT2
INT2
EPWM8_TZINT
(ePWM8)
EPWM7_TZINT
(ePWM7)
EPWM6_TZINT
(ePWM6)
INT3
EPWM8_INT
(ePWM8)
EPWM7_INT
(ePWM7)
INT4
Reserved
INT5
Reserved
INT6
INT7
INTx.4
INTx.3
INTx.2
INTx.1
XINT1
Reserved
SEQ2INT
(ADC)
SEQ1INT
(ADC)
EPWM5_TZINT
(ePWM5)
EPWM4_TZINT
(ePWM4)
EPWM3_TZINT
(ePWM3)
EPWM2_TZINT
(ePWM2)
EPWM1_TZINT
(ePWM1)
EPWM6T_INTn
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2CINT1A
(I2C-A)
INT8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2CINT2A
(I2C-A)
INT9
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT10
EPWM16_TZINT
(ePWM16)
EPWM15_TZINT
(ePWM15)
EPWM14_TZINT
(ePWM14)
EPWM13_TZINT
(ePWM13)
EPWM12_TZINT
(ePWM12)
EPWM11_TZINT
(ePWM11)
EPWM10_TZINT
(ePWM10)
EPWM9_TZINT
(ePWM9)
INT11
EPWM16_INT
(ePWM16)
EPWM15_INT
(ePWM15)
EPWM14_INT
(ePWM14)
EPWM13_INT
(ePWM13)
EPWM12_INT
(ePWM12)
EPWM11_INT
(ePWM11)
EPWM10_INT
(ePWM10)
EPWM9_INT
(ePWM9)
INT12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1. No peripheral within the group is asserting interrupts.
2. No peripheral interrupts are assigned to the group (example PIE group 12).
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Table 3-9. PIE Configuration and Control Registers
NAME
SIZE (X16)
PIECTRL
0x0CE0
1
PIE, Control Register
PIEACK
0x0CE1
1
PIE, Acknowledge Register
PIEIER1
0x0CE2
1
PIE, INT1 Group Enable Register
PIEIFR1
0x0CE3
1
PIE, INT1 Group Flag Register
PIEIER2
0x0CE4
1
PIE, INT2 Group Enable Register
PIEIFR2
0x0CE5
1
PIE, INT2 Group Flag Register
PIEIER3
0x0CE6
1
PIE, INT3 Group Enable Register
PIEIFR3
0x0CE7
1
PIE, INT3 Group Flag Register
PIEIER4
0x0CE8
1
PIE, INT4 Group Enable Register
PIEIFR4
0x0CE9
1
PIE, INT4 Group Flag Register
PIEIER5
0x0CEA
1
PIE, INT5 Group Enable Register
PIEIFR5
0x0CEB
1
PIE, INT5 Group Flag Register
PIEIER6
0x0CEC
1
PIE, INT6 Group Enable Register
PIEIFR6
0x0CED
1
PIE, INT6 Group Flag Register
PIEIER7
0x0CEE
1
PIE, INT7 Group Enable Register
PIEIFR7
0x0CEF
1
PIE, INT7 Group Flag Register
PIEIER8
0x0CF0
1
PIE, INT8 Group Enable Register
PIEIFR8
0x0CF1
1
PIE, INT8 Group Flag Register
PIEIER9
0x0CF2
1
PIE, INT9 Group Enable Register
PIEIFR9
0x0CF3
1
PIE, INT9 Group Flag Register
PIEIER10
0x0CF4
1
PIE, INT10 Group Enable Register
PIEIFR10
0x0CF5
1
PIE, INT10 Group Flag Register
PIEIER11
0x0CF6
1
PIE, INT11 Group Enable Register
PIEIFR11
0x0CF7
1
PIE, INT11 Group Flag Register
PIEIER12
0x0CF8
1
PIE, INT12 Group Enable Register
PIEIFR12
0x0CF9
1
PIE, INT12 Group Flag Register
Reserved
0x0CFA
0x0CFF
6
Reserved
(1)
3.5.1
DESCRIPTION (1)
ADDRESS
The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.
External Interrupts
Table 3-10. External Interrupt Registers
ADDRESS
SIZE (x16)
XINT1CR
NAME
0x7070
1
XINT1 control register
XINT2CR
0x7071
1
XINT2 control register
reserved
0x7072
0x7076
5
XNMICR
0x7077
1
XNMI control register
XINT1CTR
0x7078
1
XINT1 counter register
XINT2CTR
0x7079
1
XINT2 counter register
reserved
0x707A
0x707E
5
XNMICTR
0x707F
1
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XNMI counter register
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Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x280x, 2801x, 2804x System Control and Interrupts
Reference Guide (literature number SPRU712).
3.6
System Control
This section describes the F28044 device oscillator, PLL and clocking mechanisms, the watchdog function
and the low power modes. Figure 3-5 shows the various clock and reset domains in the F28044 device
that will be discussed.
Reset
XRS
Watchdog
Block
SYSCLKOUT(A)
Peripheral Reset
X1
CLKIN(A)
28x
CPU
PLL
Peripheral
Registers
Peripheral Bus
System
Control
Registers
X2
Power
Modes
Control
CPU
Timers
XCLKIN
Clock Enables
Peripheral
Registers
ePWM 1−16
I/O
Peripheral
Registers
I2C-A
I/O
GPIO
MUX
Low-Speed Prescaler
Peripheral
Registers
OSC
GPIOs
LSPCLK
Low-Speed Peripherals
SCI-A, SPI-A
I/O
High-Speed Prescaler
HSPCLK
ADC
Registers
A.
12-Bit ADC
16 ADC inputs
CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 3-5. Clock and Reset Domains
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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-11.
Table 3-11. PLL, Clocking, Watchdog, and Low-Power Mode Registers (1)
ADDRESS
SIZE (x16)
XCLK
NAME
0x7010
1
XCLKOUT Pin Control, X1 and XCLKIN Status Register
PLLSTS
0x7011
1
PLL Status Register
reserved
0x7012
0x7018
7
PCLKCR2
0x7019
1
Peripheral Clock Control Register 2
HISPCP
0x701A
1
High-Speed Peripheral Clock Prescaler Register (for HSPCLK)
LOSPCP
0x701B
1
Low-Speed Peripheral Clock Prescaler Register (for LSPCLK)
PCLKCR0
0x701C
1
Peripheral Clock Control Register 0
PCLKCR1
0x701D
1
Peripheral Clock Control Register 1
LPMCR0
0x701E
1
Low Power Mode Control Register 0
reserved
0x701F
0x7020
1
PLLCR
0x7021
1
PLL Control Register
SCSR
0x7022
1
System Control and Status Register
WDCNTR
0x7023
1
Watchdog Counter Register
reserved
0x7024
1
WDKEY
0x7025
1
reserved
0x7026
0x7028
3
WDCR
0x7029
1
reserved
0x702A
0x702F
6
(1)
DESCRIPTION
Watchdog Reset Key Register
Watchdog Control Register
All of the registers in this table are EALLOW protected.
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3.6.1
OSC and PLL Block
Figure 3-6 shows the OSC and PLL block on the F28044.
XCLKIN
(3.3-V clock input)
OSCCLK
OSCCLK
0
xor
PLLSTS[OSCOFF]
PLL
OSCCLK or
VCOCLK
CLKIN
VCOCLK
n
n≠0
/2
PLLSTS[PLLOFF]
PLLSTS[CLKINDIV]
X1
On chip
oscillator
4-bit PLL Select (PLLCR)
X2
Figure 3-6. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the F28044 device using the X1
and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the
following configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO.
2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left
unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed VDD.
The three possible input-clock configurations are shown in Figure 3-7 through Figure 3-9
XCLKIN
X1
X2
NC
External Clock Signal
(Toggling 0 −VDDIO)
Figure 3-7. Using a 3.3-V External Oscillator
X2
X1
XCLKIN
External Clock Signal
(Toggling 0 −VDD)
NC
Figure 3-8. Using a 1.8-V External Oscillator
XCLKIN
X1
X2
CL2
CL1
Crystal
Figure 3-9. Using the Internal Oscillator
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3.6.1.1
External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:
• Fundamental mode, parallel resonant
• CL (load capacitance) = 12 pF
• CL1 = CL2 = 24 pF
• Cshunt = 6 pF
• ESR range = 30 to 60 Ω
TI recommends that customers have the resonator/crystal vendor characterize the operation of their
device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank
circuit. The vendor can also advise the customer regarding the proper tank component values that will
produce proper start up and stability over the entire operating range.
3.6.1.2 PLL-Based Clock Module
The F28044 device has an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before
writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which
takes 131072 OSCCLK cycles.
Table 3-12. PLLCR Register Bit Definitions
(1)
(2)
SYSCLKOUT
(CLKIN) (2)
PLLCR[DIV] (1)
PLLSTS[CLKINDIV]
0000 (PLL bypass)
0
OSCCLK/2
0000 (PLL bypass)
1
OSCCLK
0001
0
(OSCCLK*1)/2
0010
0
(OSCCLK*2)/2
0011
0
(OSCCLK*3)/2
0100
0
(OSCCLK*4)/2
0101
0
(OSCCLK*5)/2
0110
0
(OSCCLK*6)/2
0111
0
(OSCCLK*7)/2
1000
0
(OSCCLK*8)/2
1001
0
(OSCCLK*9)/2
1010
0
(OSCCLK*10)/2
1011-1111
0
reserved
This register is EALLOW protected.
CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same as
CLKIN.
NOTE
PLLSTS[CLKINDIV] can be set to 1 only if PLLCR is 0x0000. PLLCR should not be
changed once PLLSTS[CLKINDIV] is set.
The PLL-based clock module provides two modes of operation:
• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
• External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
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Table 3-13. Possible PLL Configuration Modes
REMARKS
PLLSTS[CLKINDIV]
SYSCLKOUT
(CLKIN)
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0
OSCCLK/2
1
OSCCLK
0
OSCCLK/2
1
OSCCLK
0
OSCCLK*n/2
PLL MODE
PLL Off
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
PLL Bypass
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
PLL Enable
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
3.6.1.3 Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a "limp-mode" clock. The limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have
been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog
reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops
decrementing (i.e., the watchdog counter does not change with the limp-mode clock). In addition to this,
the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could
be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the DSP will be held in reset, should the input clocks
ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP,
should the capacitor ever get fully charged. An I/O pin may be used to discharge the
capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would
also help in detecting failure of the flash memory and the VDD3VFL rail.
3.6.2
Watchdog Block
The watchdog block on the F28044 is similar to the one used on the 240x and 281x devices. The
watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the
software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset
the watchdog counter. Figure 3-10 shows the various functional blocks within the watchdog module.
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WDCR (WDPS(2:0))
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
Watchdog
Prescaler
/512
WDCLK
8-Bit
Watchdog
Counter
CLR
Clear Counter
Internal
Pullup
WDKEY(7:0)
Watchdog
55 + AA
Key Detector
WDRST
Generate
Output Pulse
WDINT
(512 OSCCLKs)
Good Key
XRS
Core-reset
WDCR (WDCHK(2:0))
WDRST(A)
A.
1
0
Bad
WDCHK
Key
SCSR (WDENINT)
1
The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-10. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the
LPM block so that it can wake the device from STANDBY (if enabled). See Section Section 3.7,
Low-Power Modes Block, for details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so
is the WATCHDOG.
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3.7
Low-Power Modes Block
The low-power modes on the F28044 device are similar to the 240x devices. Table 3-14 summarizes the
various modes.
Table 3-14. Low-Power Modes
EXIT (1)
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
IDLE
00
On
On
On (2)
XRS, Watchdog interrupt, any enabled
interrupt, XNMI
STANDBY
01
On
(watchdog still running)
Off
Off
XRS, Watchdog interrupt, GPIO Port A
signal, debugger (3), XNMI
HALT
1X
Off
(oscillator and PLL turned off,
watchdog not functional)
Off
Off
XRS, GPIO Port A signal, XNMI,
debugger (3)
(1)
(2)
(3)
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will
exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized by
the processor. The LPM block performs no tasks during this mode as long as the
LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK
before waking the device. The number of OSCCLKs is specified in the LPMCR0
register.
HALT Mode:
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device
from HALT mode. The user selects the signal in the GPIOLPMSEL register.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included).
They will be in whatever state the code left them in when the IDLE instruction was
executed. See the TMS320x280x System Control and Interrupts Reference Guide
(literature number SPRU712) for details.
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4
Peripherals
The integrated peripherals of the F28044 device are described in the following subsections:
• Three 32-bit CPU-Timers
• Up to 16 enhanced PWM modules (ePWM1-16)
• Enhanced analog-to-digital converter (ADC) module
• Serial communications interface module (SCI-A)
• Serial peripheral interface (SPI) module (SPI-A)
• Inter-integrated circuit module (I2C)
• Digital I/O and shared pin functions
4.1
32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the F28044 device (CPU-TIMER0/1/2).
CPU-Timer 1 is reserved for TI system functions and Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0
can be used in user applications. These timers are different from the timers that are present in the ePWM
modules.
NOTE
NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
TDDRH:TDDR
SYSCLKOUT
TCR.4
(Timer Start Status)
32-Bit Timer Period
PRDH:PRD
16-Bit Prescale Counter
PSCH:PSC
Borrow
32-Bit Counter
TIMH:TIM
Borrow
TINT
Figure 4-1. CPU-Timers
In the F28044 device, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
Figure 4-2.
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INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
C28x
CPU-TIMER 1
(Reserved for TI
system functions)
TINT1
INT13
XINT13
CPU-TIMER 2
(Reserved for
DSP/BIOS)
TINT2
INT14
A.
The timer registers are connected to the memory bus of the C28x processor.
B.
The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
C.
While TIMER1 is reserved, INT13 is not reserved and the user can use XINT13 connected to INT13.
Figure 4-2. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the
value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x280x,
2801x, 2804x System Control and Interrupts Reference Guide (literature number SPRU712).
Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers
ADDRESS
SIZE (x16)
TIMER0TIM
NAME
0x0C00
1
CPU-Timer 0, Counter Register
TIMER0TIMH
0x0C01
1
CPU-Timer 0, Counter Register High
TIMER0PRD
0x0C02
1
CPU-Timer 0, Period Register
TIMER0PRDH
0x0C03
1
CPU-Timer 0, Period Register High
TIMER0TCR
0x0C04
1
CPU-Timer 0, Control Register
reserved
0x0C05
1
TIMER0TPR
0x0C06
1
CPU-Timer 0, Prescale Register
TIMER0TPRH
0x0C07
1
CPU-Timer 0, Prescale Register High
TIMER1TIM
0x0C08
1
CPU-Timer 1, Counter Register
TIMER1TIMH
0x0C09
1
CPU-Timer 1, Counter Register High
TIMER1PRD
0x0C0A
1
CPU-Timer 1, Period Register
TIMER1PRDH
0x0C0B
1
CPU-Timer 1, Period Register High
TIMER1TCR
0x0C0C
1
CPU-Timer 1, Control Register
reserved
0x0C0D
1
TIMER1TPR
0x0C0E
1
CPU-Timer 1, Prescale Register
TIMER1TPRH
0x0C0F
1
CPU-Timer 1, Prescale Register High
TIMER2TIM
0x0C10
1
CPU-Timer 2, Counter Register
TIMER2TIMH
0x0C11
1
CPU-Timer 2, Counter Register High
TIMER2PRD
0x0C12
1
CPU-Timer 2, Period Register
TIMER2PRDH
0x0C13
1
CPU-Timer 2, Period Register High
TIMER2TCR
0x0C14
1
CPU-Timer 2, Control Register
reserved
0x0C15
1
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Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers (continued)
ADDRESS
SIZE (x16)
TIMER2TPR
NAME
0x0C16
1
CPU-Timer 2, Prescale Register
TIMER2TPRH
0x0C17
1
CPU-Timer 2, Prescale Register High
reserved
0x0C18
0x0C3F
40
4.2
DESCRIPTION
Enhanced PWM Modules (ePWM1-16)
The F28044 device contains up to 16 enhanced PWM Modules (ePWM). Figure 4-3 shows a block
diagram of multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM. See
the TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature
number SPRU791) for details.
EPWM1SYNCI
EPWM1INT
EPWM1SYNCI
EPWM1A
EPWM1SOC
ePWM1 module
EPWM1B
TZ1 to TZ6
to eCAP1
module
(sync in)
EPWM1SYNCO
EPWM1SYNCO
.
EPWM2SYNCI
EPWM2INT
EPWM2SOC
PIE
EPWM2A
ePWM2 module
EPWM2B
GPIO
MUX
TZ1 to TZ6
EPWM2SYNCO
EPWMxSYNCI
EPWMxINT
EPWMxSOC
EPWMxA
ePWMx module
EPWMxB
EPWMxSYNCO
TZ1 to TZ6
ADCSOCx0
ADC
Peripheral Bus
Figure 4-3. Multiple PWM Modules
The F28044 device contains 16 enhanced PWM modules (EPWM) and 16 high resolution PWM modules
(HRPWM). The EPWM modules synchronize input/output and the ADC start of conversion (SOCA/B)
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signals are regrouped in the F28044. At reset, EPWMMODE bits in the GPAMCFG register configure the
sync signals to be compatible to the TMS320F2808 device. In F28044 mode, the ePWMMODE bits are
set to 11 to select the EPWMA signals on all 16 GPIOs (GPIO0-GPIO15). This mode selection also
reconfigures the EPWM1 SYNCOUT to be connected to four groups of EPWM modules and as
EPWMSYNCO signals on the pin:
• Group 1: EPWM2, EPWM3, EPWM4
• Group 2: EPWM5, EPWM6, EPWM7, EPWM8
• Group 3: EPWM9, EPWM10, EPWM11, EPWM12
• Group 4: EPWM13, EPWM14, EPWM15, EPWM16
See the TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) User's Guide (SPRU791) for
additional details.
Table 4-2 through Table 4-5 show the complete ePWM register set per module.
Table 4-2. ePWM1-4 Control and Status Registers
EPWM1
EPWM2
EPWM3
EPWM4
SIZE (x16) /
#SHADOW
TBCTL
0x6800
0x6840
0x6880
0x68C0
1/0
Time Base Control Register
TBSTS
0x6801
0x6841
0x6881
0x68C1
1/0
Time Base Status Register
TBPHSHR
0x6802
0x6842
0x6882
0x68C2
1/0
Time Base Phase HRPWM Register
TBPHS
0x6803
0x6843
0x6883
0x68C3
1/0
Time Base Phase Register
TBCTR
0x6804
0x6844
0x6884
0x68C4
1/0
Time Base Counter Register
TBPRD
0x6805
0x6845
0x6885
0x68C5
1/1
Time Base Period Register Set
CMPCTL
0x6807
0x6847
0x6887
0x68C7
1/0
Counter Compare Control Register
CMPAHR
0x6808
0x6848
0x6888
0x68C8
1/1
Time Base Compare A HRPWM Register
CMPA
0x6809
0x6849
0x6889
0x68C9
1/1
Counter Compare A Register Set
CMPB
0x680A
0x684A
0x688A
0x68CA
1/1
Counter Compare B Register Set
AQCTLA
0x680B
0x684B
0x688B
0x68CB
1/0
Action Qualifier Control Register For Output A
AQCTLB
0x680C
0x684C
0x688C
0x68CC
1/0
Action Qualifier Control Register For Output B
AQSFRC
0x680D
0x684D
0x688D
0x68CD
1/0
Action Qualifier Software Force Register
AQCSFRC
0x680E
0x684E
0x688E
0x68CE
1/1
Action Qualifier Continuous S/W Force Register Set
DBCTL
0x680F
0x684F
0x688F
0x68CF
1/1
Dead-Band Generator Control Register
DBRED
0x6810
0x6850
0x6890
0x68D0
1/0
Dead-Band Generator Rising Edge Delay Count Register
DBFED
0x6811
0x6851
0x6891
0x68D1
1/0
Dead-Band Generator Falling Edge Delay Count Register
TZSEL
0x6812
0x6852
0x6892
0x68D2
1/0
Trip Zone Select Register (1)
TZCTL
0x6814
0x6854
0x6894
0x68D4
1/0
Trip Zone Control Register (1)
TZEINT
0x6815
0x6855
0x6895
0x68D5
1/0
Trip Zone Enable Interrupt Register (1)
TZFLG
0x6816
0x6856
0x6896
0x68D6
1/0
Trip Zone Flag Register
TZCLR
0x6817
0x6857
0x6897
0x68D7
1/0
Trip Zone Clear Register (1)
TZFRC
0x6818
0x6858
0x6898
0x68D8
1/0
Trip Zone Force Register (1)
ETSEL
0x6819
0x6859
0x6899
0x68D9
1/0
Event Trigger Selection Register
ETPS
0x681A
0x685A
0x689A
0x68DA
1/0
Event Trigger Prescale Register
ETFLG
0x681B
0x685B
0x689B
0x68DB
1/0
Event Trigger Flag Register
ETCLR
0x681C
0x685C
0x689C
0x68DC
1/0
Event Trigger Clear Register
ETFRC
0x681D
0x685D
0x689D
0x68DD
1/0
Event Trigger Force Register
PCCTL
0x681E
0x685E
0x689E
0x68DE
1/0
PWM Chopper Control Register
HRCNFG
0x6820
0x6860
0x68A0
0x68E0
1/0
HRPWM Configuration Register (1)
NAME
(1)
44
DESCRIPTION
Registers that are EALLOW protected.
Peripherals
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Table 4-3. ePWM5-8 Control and Status Registers
EPWM5
EPWM6
EPWM7
EPWM8
SIZE (x16) /
#SHADOW
TBCTL
0x6900
0x6940
0x6980
0x69C0
1/0
Time Base Control Register
TBSTS
0x6901
0x6941
0x6981
0x69C1
1/0
Time Base Status Register
TBPHSHR
0x6902
0x6942
0x6982
0x69C2
1/0
Time Base Phase HRPWM Register
TBPHS
0x6903
0x6943
0x6983
0x69C3
1/0
Time Base Phase Register
TBCTR
0x6904
0x6944
0x6984
0x69C4
1/0
Time Base Counter Register
TBPRD
0x6905
0x6945
0x6985
0x69C5
1/1
Time Base Period Register Set
CMPCTL
0x6907
0x6947
0x6987
0x69C7
1/0
Counter Compare Control Register
CMPAHR
0x6908
0x6948
0x6988
0x69C8
1/1
Time Base Compare A HRPWM Register
CMPA
0x6909
0x6949
0x6989
0x69C9
1/1
Counter Compare A Register Set
CMPB
0x690A
0x694A
0x698A
0x69CA
1/1
Counter Compare B Register Set
AQCTLA
0x690B
0x694B
0x698B
0x69CB
1/0
Action Qualifier Control Register For Output A
AQCTLB
0x690C
0x694C
0x698C
0x69CC
1/0
Action Qualifier Control Register For Output B
AQSFRC
0x690D
0x694D
0x698D
0x69CD
1/0
Action Qualifier Software Force Register
AQCSFRC
0x690E
0x694E
0x698E
0x69CE
1/1
Action Qualifier Continuous S/W Force Register Set
DBCTL
0x690F
0x694F
0x698F
0x69CF
1/1
Dead-Band Generator Control Register
DBRED
0x6910
0x6950
0x6990
0x69D0
1/0
Dead-Band Generator Rising Edge Delay Count Register
DBFED
0x6911
0x6951
0x6991
0x69D1
1/0
Dead-Band Generator Falling Edge Delay Count Register
TZSEL
0x6912
0x6952
0x6992
0x69D2
1/0
Trip Zone Select Register (1)
TZCTL
0x6914
0x6954
0x6994
0x69D4
1/0
Trip Zone Control Register (1)
TZEINT
0x6915
0x6955
0x6995
0x69D5
1/0
Trip Zone Enable Interrupt Register (1)
TZFLG
0x6916
0x6956
0x6996
0x69D6
1/0
Trip Zone Flag Register
TZCLR
0x6917
0x6957
0x6997
0x69D7
1/0
Trip Zone Clear Register (1)
TZFRC
0x6918
0x6958
0x6998
0x69D8
1/0
Trip Zone Force Register (1)
ETSEL
0x6919
0x6959
0x6999
0x69D9
1/0
Event Trigger Selection Register
ETPS
0x691A
0x695A
0x699A
0x69DA
1/0
Event Trigger Prescale Register
ETFLG
0x691B
0x695B
0x699B
0x69DB
1/0
Event Trigger Flag Register
ETCLR
0x691C
0x695C
0x699C
0x69DC
1/0
Event Trigger Clear Register
ETFRC
0x691D
0x695D
0x699D
0x69DD
1/0
Event Trigger Force Register
PCCTL
0x691E
0x695E
0x699E
0x69DE
1/0
PWM Chopper Control Register
HRCNFG
0x6920
0x6960
0x69A0
0x69E0
1/0
HRPWM Configuration Register (1)
NAME
(1)
DESCRIPTION
Registers that are EALLOW protected.
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Table 4-4. ePWM9-12 Control and Status Registers
EPWM9
EPWM10
EPWM11
EPWM12
SIZE (x16) /
#SHADOW
TBCTL
0x6600
0x6640
0x6680
0x66C0
1/0
Time Base Control Register
TBSTS
0x6601
0x6641
0x6681
0x66C1
1/0
Time Base Status Register
TBPHSHR
0x6602
0x6642
0x6682
0x66C2
1/0
Time Base Phase HRPWM Register
TBPHS
0x6603
0x6643
0x6683
0x66C3
1/0
Time Base Phase Register
TBCTR
0x6604
0x6644
0x6684
0x66C4
1/0
Time Base Counter Register
TBPRD
0x6605
0x6645
0x6685
0x66C5
1/1
Time Base Period Register Set
CMPCTL
0x6607
0x6647
0x6687
0x66C7
1/0
Counter Compare Control Register
CMPAHR
0x6608
0x6648
0x6688
0x66C8
1/1
Time Base Compare A HRPWM Register
CMPA
0x6609
0x6649
0x6689
0x66C9
1/1
Counter Compare A Register Set
CMPB
0x660A
0x664A
0x668A
0x66CA
1/1
Counter Compare B Register Set
AQCTLA
0x660B
0x664B
0x668B
0x66CB
1/0
Action Qualifier Control Register For Output A
AQCTLB
0x660C
0x664C
0x668C
0x66CC
1/0
Action Qualifier Control Register For Output B
AQSFRC
0x660D
0x664D
0x668D
0x66CD
1/0
Action Qualifier Software Force Register
AQCSFRC
0x660E
0x664E
0x668E
0x66CE
1/1
Action Qualifier Continuous S/W Force Register Set
DBCTL
0x660F
0x664F
0x668F
0x66CF
1/1
Dead-Band Generator Control Register
DBRED
0x6610
0x6650
0x6690
0x66D0
1/0
Dead-Band Generator Rising Edge Delay Count Register
DBFED
0x6611
0x6651
0x6691
0x66D1
1/0
Dead-Band Generator Falling Edge Delay Count Register
TZSEL
0x6612
0x6652
0x6692
0x66D2
1/0
Trip Zone Select Register (1)
TZCTL
0x6614
0x6654
0x6694
0x66D4
1/0
Trip Zone Control Register (1)
TZEINT
0x6615
0x6655
0x6695
0x66D5
1/0
Trip Zone Enable Interrupt Register (1)
TZFLG
0x6616
0x6656
0x6696
0x66D6
1/0
Trip Zone Flag Register
TZCLR
0x6617
0x6657
0x6697
0x66D7
1/0
Trip Zone Clear Register (1)
TZFRC
0x6618
0x6658
0x6698
0x66D8
1/0
Trip Zone Force Register (1)
ETSEL
0x6619
0x6659
0x6699
0x66D9
1/0
Event Trigger Selection Register
ETPS
0x661A
0x665A
0x669A
0x66DA
1/0
Event Trigger Prescale Register
ETFLG
0x661B
0x665B
0x669B
0x66DB
1/0
Event Trigger Flag Register
ETCLR
0x661C
0x665C
0x669C
0x66DC
1/0
Event Trigger Clear Register
ETFRC
0x661D
0x665D
0x669D
0x66DD
1/0
Event Trigger Force Register
PCCTL
0x661E
0x665E
0x669E
0x66DE
1/0
PWM Chopper Control Register
HRCNFG
0x6620
0x6660
0x66A0
0x66E0
1/0
HRPWM Configuration Register (1)
NAME
(1)
46
DESCRIPTION
Registers that are EALLOW protected.
Peripherals
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Table 4-5. ePWM13-16 Control and Status Registers
EPWM13
EPWM14
EPWM15
EPWM16
SIZE (x16) /
#SHADOW
TBCTL
0x6700
0x6740
0x6780
0x67C0
1/0
Time Base Control Register
TBSTS
0x6701
0x6741
0x6781
0x67C1
1/0
Time Base Status Register
TBPHSHR
0x6702
0x6742
0x6782
0x67C2
1/0
Time Base Phase HRPWM Register
TBPHS
0x6703
0x6743
0x6783
0x67C3
1/0
Time Base Phase Register
TBCTR
0x6704
0x6744
0x6784
0x67C4
1/0
Time Base Counter Register
TBPRD
0x6705
0x6745
0x6785
0x67C5
1/1
Time Base Period Register Set
CMPCTL
0x6707
0x6747
0x6787
0x67C7
1/0
Counter Compare Control Register
CMPAHR
0x6708
0x6748
0x6788
0x67C8
1/1
Time Base Compare A HRPWM Register
CMPA
0x6709
0x6749
0x6789
0x67C9
1/1
Counter Compare A Register Set
CMPB
0x670A
0x674A
0x678A
0x67CA
1/1
Counter Compare B Register Set
AQCTLA
0x670B
0x674B
0x678B
0x67CB
1/0
Action Qualifier Control Register For Output A
AQCTLB
0x670C
0x674C
0x678C
0x67CC
1/0
Action Qualifier Control Register For Output B
AQSFRC
0x670D
0x674D
0x678D
0x67CD
1/0
Action Qualifier Software Force Register
AQCSFRC
0x670E
0x674E
0x678E
0x67CE
1/1
Action Qualifier Continuous S/W Force Register Set
DBCTL
0x670F
0x674F
0x678F
0x67CF
1/1
Dead-Band Generator Control Register
DBRED
0x6710
0x6750
0x6790
0x67D0
1/0
Dead-Band Generator Rising Edge Delay Count Register
DBFED
0x6711
0x6751
0x6791
0x67D1
1/0
Dead-Band Generator Falling Edge Delay Count Register
TZSEL
0x6712
0x6752
0x6792
0x67D2
1/0
Trip Zone Select Register (1)
TZCTL
0x6714
0x6754
0x6794
0x67D4
1/0
Trip Zone Control Register (1)
TZEINT
0x6715
0x6755
0x6795
0x67D5
1/0
Trip Zone Enable Interrupt Register (1)
TZFLG
0x6716
0x6756
0x6796
0x67D6
1/0
Trip Zone Flag Register
TZCLR
0x6717
0x6757
0x6797
0x67D7
1/0
Trip Zone Clear Register (1)
TZFRC
0x6718
0x6758
0x6798
0x67D8
1/0
Trip Zone Force Register (1)
ETSEL
0x6719
0x6759
0x6799
0x67D9
1/0
Event Trigger Selection Register
ETPS
0x671A
0x675A
0x679A
0x67DA
1/0
Event Trigger Prescale Register
ETFLG
0x671B
0x675B
0x679B
0x67DB
1/0
Event Trigger Flag Register
ETCLR
0x671C
0x675C
0x679C
0x67DC
1/0
Event Trigger Clear Register
ETFRC
0x671D
0x675D
0x679D
0x67DD
1/0
Event Trigger Force Register
PCCTL
0x671E
0x675E
0x679E
0x67DE
1/0
PWM Chopper Control Register
HRCNFG
0x6720
0x6760
0x67A0
0x67E0
1/0
HRPWM Configuration Register (1)
NAME
(1)
DESCRIPTION
Registers that are EALLOW protected.
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Time−base (TB)
Sync
in/out
select
Mux
CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
CTR=PRD
EPWMxSYNCO
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMxSYNCI
Counter
up/down
(16 bit)
CTR=ZERO
TBCNT
active (16)
CTR_Dir
TBPHSHR (8)
16
8
TBPHS active (24)
Phase
control
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
16
TBCTL[SWFSYNC]
(software forced sync)
Action
qualifier
(AQ)
CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPB
CTR_Dir
8
Event
trigger
and
interrupt
(ET)
EPWMxINT
EPWMxSOCA
EPWMxSOCB
HiRes PWM (HRPWM)
CMPA active (24)
EPWMxAO
EPWMA
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
16
PWM
chopper
(PC)
EPWMB
EPWMxBO
CMPB active (16)
CMPB shadow (16)
Trip
zone
(TZ)
EPWMxTZINT
CTR = ZERO
TZ1 to TZ6
Figure 4-4. ePWM Sub-Modules Showing Critical Internal Signal Interconnections
4.3
Hi-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can
be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module
are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies
greater than ~200 KHz when using a CPU/System clock of 100 MHz.
• This capability can be utilized in both duty cycle and phase-shift control methods.
• Finer time granularity control or edge positioning is controlled via extensions to the Compare A and
Phase registers of the ePWM module.
• HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA
output). EPWMxB output has conventional PWM capabilities.
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4.4
Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 4-5. The ADC module
consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module
include:
• 12-bit ADC core with built-in S/H
• Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
• Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS
• 16-channel, MUXed inputs
• Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion
can be programmed to select any 1 of 16 input channels
• Sequencer can be operated as two independent 8-state sequencers or as one large 16-state
sequencer (i.e., two cascaded 8-state sequencers)
• Sixteen result registers (individually addressable) to store conversion values
– The digital value of the input analog voltage is derived by:
when input ≤ 0 V
Digital Value + 0,
Digital Value + 4096
Digital Value + 4095,
A.
•
•
•
•
•
Input Analog Voltage * ADCLO
3
when 0 V < input < 3 V
when input ≥ 3 V
All fractional values are truncated.
Multiple triggers as sources for the start-of-conversion (SOC) sequence
– S/W - software immediate start
– ePWM start of conversion
– XINT2 ADC start of conversion
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.
Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to
synchronize conversions.
SOCA and SOCB triggers can operate independently in dual-sequencer mode.
Sample-and-hold (S/H) acquisition time window has separate prescale control.
The ADC module in the F28044 device has been enhanced to provide flexible interface to ePWM
peripherals. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80
ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel
modules. The two independent 8-channel modules can be cascaded to form a 16-channel module.
Although there are multiple input channels and two sequencers, there is only one converter in the ADC
module. Figure 4-5 shows the block diagram of the ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module
has the choice of selecting any one of the respective eight channels available through an analog MUX. In
the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer,
once the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to
perform oversampling algorithms. This gives increased resolution over traditional single-sampled
conversion results.
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System
Control Block
ADCENCLK
SYSCLKOUT
High-Speed
Prescaler
HALT
DSP
HSPCLK
Analog
MUX
Result Registers
Result Reg 0
ADCINA0
70A8h
Result Reg 1
S/H
ADCINA7
12-Bit
ADC
Module
Result Reg 7
70AFh
Result Reg 8
70B0h
Result Reg 15
70B7h
ADCINB0
S/H
ADCINB7
ADC Control Registers
S/W
EPWMSOCA
GPIO/XINT2
_ADCSOC
SOC
Sequencer 2
Sequencer 1
SOC
S/W
EPWMSOCB
Figure 4-5. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( VDD1A18,
VDD2A18 , VDDA2, VDDAIO ) from the digital supply.Figure 4-6 shows the ADC pin connections for the F28044
device.
NOTE
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the
ADC module is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT
signals is as follows:
–
–
50
Peripherals
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the
clock to the register will still function. This is necessary to make sure all registers
and modes go into their default reset state. The analog module, however, will be
in a low-power inactive state. As soon as reset goes high, then the clock to the
registers will be disabled. When the user sets the ADCENCLK signal high, then
the clocks to the registers will be enabled and the analog module will be enabled.
There will be a certain time delay (ms range) before the ADC is stable and can be
used.
HALT: This mode only affects the analog module. It does not affect the registers.
In this mode, the ADC module goes into low-power mode. This mode also will stop
the clock to the CPU, which will stop the HSPCLK; therefore, the ADC register
logic will be turned off indirectly.
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Figure 4-6 shows the ADC pin-biasing for internal reference and Figure 4-7 shows the ADC pin-biasing for
external reference.
ADC 16-Channel Analog Inputs
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN
Analog input 0−3 V with respect to ADCLO
Connect to analog ground
Float or ground if internal reference is used
22 kW
ADC External Current Bias Resistor
ADCRESEXT
ADC Reference Positive Output
ADCREFP
ADC Reference Medium Output
ADCREFM
ADC Power
2.2 mF (A)
2.2 mF (A)
VDD1A18
VDD2A18
ADCREFP and ADCREFM should not
be loaded by external circuitry
VSS1AGND
VSS2AGND
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Analog Ground Pin
VDDA2
VSSA2
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
VDDAIO
VSSAIO
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
ADC Analog and Reference I/O Power
A.
TAIYO YUDEN LMK212BJ225MG-T or equivalent
B.
External decoupling capacitors are recommended on all power pins.
C.
Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 4-6. ADC Pin Connections With Internal Reference
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ADC 16-Channel Analog Inputs
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADCREFIN
Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
Connect to 1.500, 1.024, or 2.048-V precision source (D)
22 kW
ADC External Current Bias Resistor
ADCRESEXT
ADC Reference Positive Output
ADCREFP
ADC Reference Medium Output
ADCREFM
ADC Analog Power
VDD1A18
VDD2A18
VSS1AGND
VSS2AGND
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Analog Ground Pin
VDDA2
VSSA2
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
VDDAIO
VSSAIO
ADC Analog Power Pin (3.3 V)
ADC Analog and Reference I/O Power
2.2 mF (A)
2.2 mF (A)
ADCREFP and ADCREFM should not
be loaded by external circuitry
ADC Analog I/O Ground Pin
A.
TAIYO YUDEN LMK212BJ225MG-T or equivalent
B.
External decoupling capacitors are recommended on all power pins.
C.
Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
D.
External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on
the voltage used on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain
accuracy will be determined by accuracy of this voltage source.
Figure 4-7. ADC Pin Connections With External Reference
NOTE
The temperature rating of any recommended component must match the rating of the end
product.
4.5
ADC Connections if the ADC Is Not Used
It is recommended that the connections for the analog power pins be kept even if the ADC is not used.
Following is a summary of how the ADC pins should be connected, if the ADC is not used in an
application:
• VDD1A18/VDD2A18 – Connect to VDD
• VDDA2, VDDAIO – Connect to VDDIO
• VSS1AGND/VSS2AGND, VSSA2, VSSAIO – Connect to VSS
• ADCLO – Connect to VSS
• ADCREFIN – Connect to VSS
• ADCREFP/ADCREFM – Connect a 100 nF cap to VSS
• ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to VSS.
• ADCINAn, ADCINBn - Connect to VSS
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power
savings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (VSS1AGND/VSS2AGND)
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-6.
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Table 4-6. ADC Registers (1)
NAME
ADDRESS (1)
ADDRESS (2)
ADCTRL1
0x7100
1
ADC Control Register 1
SIZE (x16)
DESCRIPTION
ADCTRL2
0x7101
1
ADC Control Register 2
ADCMAXCONV
0x7102
1
ADC Maximum Conversion Channels Register
ADCCHSELSEQ1
0x7103
1
ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2
0x7104
1
ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3
0x7105
1
ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4
0x7106
1
ADC Channel Select Sequencing Control Register 4
ADCASEQSR
0x7107
1
ADC Auto-Sequence Status Register
ADCRESULT0
0x7108
0x0B00
1
ADC Conversion Result Buffer Register 0
ADCRESULT1
0x7109
0x0B01
1
ADC Conversion Result Buffer Register 1
ADCRESULT2
0x710A
0x0B02
1
ADC Conversion Result Buffer Register 2
ADCRESULT3
0x710B
0x0B03
1
ADC Conversion Result Buffer Register 3
ADCRESULT4
0x710C
0x0B04
1
ADC Conversion Result Buffer Register 4
ADCRESULT5
0x710D
0x0B05
1
ADC Conversion Result Buffer Register 5
ADCRESULT6
0x710E
0x0B06
1
ADC Conversion Result Buffer Register 6
ADCRESULT7
0x710F
0x0B07
1
ADC Conversion Result Buffer Register 7
ADCRESULT8
0x7110
0x0B08
1
ADC Conversion Result Buffer Register 8
ADCRESULT9
0x7111
0x0B09
1
ADC Conversion Result Buffer Register 9
ADCRESULT10
0x7112
0x0B0A
1
ADC Conversion Result Buffer Register 10
ADCRESULT11
0x7113
0x0B0B
1
ADC Conversion Result Buffer Register 11
ADCRESULT12
0x7114
0x0B0C
1
ADC Conversion Result Buffer Register 12
ADCRESULT13
0x7115
0x0B0D
1
ADC Conversion Result Buffer Register 13
ADCRESULT14
0x7116
0x0B0E
1
ADC Conversion Result Buffer Register 14
ADCRESULT15
0x7117
0x0B0F
1
ADC Conversion Result Buffer Register 15
ADCTRL3
0x7118
1
ADC Control Register 3
ADCST
0x7119
1
ADC Status Register
Reserved
0x711A
0x711B
2
(1)
(2)
ADCREFSEL
0x711C
1
ADC Reference Select Register
ADCOFFTRIM
0x711D
1
ADC Offset Trim Register
Reserved
0x711E
0x711F
2
ADC Status Register
The registers in this column are Peripheral Frame 2 Registers.
The ADC result registers are dual mapped in the F28044 DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and
left justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high speed/continuous
conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory.
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4.6
Serial Communications Interface (SCI) Module (SCI-A)
The F28044 device includes a serial communications interface (SCI) module. The SCI module supports
digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its
own separate enable and interrupt bits. Both can be operated independently or simultaneously in the
full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,
overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit
baud-select register.
Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
•
•
•
•
•
•
•
•
•
•
Baud rate =
LSPCLK
(BRR ) 1) * 8
when BRR ≠ 0
Baud rate =
LSPCLK
16
when BRR = 0
Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
Max bit rate + 100 MHz + 6.25 106 bńs
16
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 4-7.
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Table 4-7. SCI-A Registers (1)
(1)
(2)
NAME
ADDRESS
SIZE (x16)
SCICCRA
0x7050
1
SCI-A Communications Control Register
DESCRIPTION
SCICTL1A
0x7051
1
SCI-A Control Register 1
SCIHBAUDA
0x7052
1
SCI-A Baud Register, High Bits
SCILBAUDA
0x7053
1
SCI-A Baud Register, Low Bits
SCICTL2A
0x7054
1
SCI-A Control Register 2
SCIRXSTA
0x7055
1
SCI-A Receive Status Register
SCIRXEMUA
0x7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x7057
1
SCI-A Receive Data Buffer Register
SCITXBUFA
0x7059
1
SCI-A Transmit Data Buffer Register
SCIFFTXA (2)
0x705A
1
SCI-A FIFO Transmit Register
SCIFFRXA (2)
0x705B
1
SCI-A FIFO Receive Register
SCIFFCTA (2)
0x705C
1
SCI-A FIFO Control Register
SCIPRIA
0x705F
1
SCI-A Priority Control Register
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
These registers are new registers for the FIFO mode.
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Figure 4-8 shows the SCI module block diagram.
SCICTL1.1
SCITXD
Frame Format and Mode
Parity
Even/Odd Enable
TXSHF
Register
TXENA
8
SCICCR.6 SCICCR.5
TX EMPTY
SCICTL2.6
TXRDY
TXWAKE
SCICTL1.3
1
Transmitter-Data
Buffer Register
8
TX INT ENA
SCICTL2.7
SCICTL2.0
TX FIFO
Interrupts
TX FIFO _0
TX FIFO _1
SCITXD
TXINT
TX Interrupt
Logic
-----
To CPU
TX FIFO _15
WUT
SCI TX Interrupt select logic
SCITXBUF.7-0
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCIRXD
RXSHF
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
Baud Rate
LSbyte
Register
RXENA
8
SCICTL1.0
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7-0
RXRDY
8
BRKDT
RX FIFO _15
----RX FIFO_1
RX FIFO _0
SCIRXBUF.7-0
RX/BK INT ENA
SCIRXST.6
SCIRXST.5
RX FIFO
Interrupts
RX Interrupt
Logic
To CPU
RX FIFO registers
SCIRXST.7
SCIRXST.4 - 2
RX Error
FE OE PE
RXINT
RXFFOVF
SCIFFRX.15
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 4-8. Serial Communications Interface (SCI) Module Block Diagram
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4.7
Serial Peripheral Interface (SPI) Module (SPI-A)
The F28044 device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be
shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSP controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
• Two operational modes: master and slave
Baud rate: 125 different programmable rates.
•
•
•
•
•
Baud rate =
LSPCLK
(SPIBRR ) 1)
Baud rate =
LSPCLK
4
when SPIBRR = 3 to 127
when SPIBRR = 0,1, 2
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
• 16-level transmit/receive FIFO
• Delayed transmit control
The SPI port operation is configured and controlled by the registers listed in Table 4-8.
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Table 4-8. SPI-A Registers
(1)
58
DESCRIPTION (1)
NAME
ADDRESS
SIZE (X16)
SPICCR
0x7040
1
SPI-A Configuration Control Register
SPICTL
0x7041
1
SPI-A Operation Control Register
SPISTS
0x7042
1
SPI-A Status Register
SPIBRR
0x7044
1
SPI-A Baud Rate Register
SPIRXEMU
0x7046
1
SPI-A Receive Emulation Buffer Register
SPIRXBUF
0x7047
1
SPI-A Serial Input Buffer Register
SPITXBUF
0x7048
1
SPI-A Serial Output Buffer Register
SPIDAT
0x7049
1
SPI-A Serial Data Register
SPIFFTX
0x704A
1
SPI-A FIFO Transmit Register
SPIFFRX
0x704B
1
SPI-A FIFO Receive Register
SPIFFCT
0x704C
1
SPI-A FIFO Control Register
SPIPRI
0x704F
1
SPI-A Priority Control Register
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Figure 4-9 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPISTS.7
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
−−−−−
SPIINT/SPIRXINT
RX FIFO Interrupt
RX Interrupt
Logic
RX FIFO _15
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
−−−−−
TX Interrupt
Logic
TX FIFO Interrupt
TX FIFO _1
TX FIFO _0
SPITXINT
16
SPI INT FLAG
SPITXBUF
Buffer Register
16
SPI INT
ENA
SPISTS.6
SPICTL.0
16
M
M
SPIDAT
Data Register
S
S
SW1
SPISIMO
M
M
SPIDAT.15 − 0
S
S
SW2
SPISOMI
Talk
SPICTL.1
SPISTE(A)
State Control
Master/Slave
SPI Char
SPICCR.3 − 0
3
2
1
SW3
M
SPI Bit Rate
LSPCLK
S
SPIBRR.6 − 0
6
A.
SPICTL.2
S
0
5
4
3
2
1
0
Clock
Polarity
Clock
Phase
SPICCR.6
SPICTL.3
SPICLK
M
SPISTE is driven low by the master for a slave device.
Figure 4-9. SPI Module Block Diagram (Slave Mode)
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4.8
Inter-Integrated Circuit (I2C)
The F28044 device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module
interfaces within the F28044 device.
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)
• One 16-bit receive FIFO and one 16-bit transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode
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System Control
Block
C28X CPU
I2CAENCLK
SYSRS
Control
Data[16]
SDAA
Peripheral Bus
SYSCLKOUT
Data[16]
GPIO
MUX
I2C−A
Addr[16]
SCLA
I2CINT1A
PIE
Block
I2CINT2A
A.
The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
B.
The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 4-10. I2C Peripheral Module Interfaces
The registers in Table 4-9 configure and control the I2C port operation.
Table 4-9. I2C-A Registers
NAME
ADDRESS
I2COAR
0x7900
I2C own address register
DESCRIPTION
I2CIER
0x7901
I2C interrupt enable register
I2CSTR
0x7902
I2C status register
I2CCLKL
0x7903
I2C clock low-time divider register
I2CCLKH
0x7904
I2C clock high-time divider register
I2CCNT
0x7905
I2C data count register
I2CDRR
0x7906
I2C data receive register
I2CSAR
0x7907
I2C slave address register
I2CDXR
0x7908
I2C data transmit register
I2CMDR
0x7909
I2C mode register
I2CISRC
0x790A
I2C interrupt source register
I2CPSC
0x790C
I2C prescaler register
I2CFFTX
0x7920
I2C FIFO transmit register
I2CFFRX
0x7921
I2C FIFO receive register
I2CRSR
-
I2C receive shift register (not accessible to the CPU)
I2CXSR
-
I2C transmit shift register (not accessible to the CPU)
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4.9
GPIO MUX
On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in Figure 4-11. Because of the open drain capabilities of the I2C pins, the GPIO MUX block
diagram for these pins differ. See the TMS320x280x, 2801x, 2804x System Control and Interrupts
Reference Guide (literature number SPRU712) for details.
GPIOXINT1SEL
GPIOLMPSEL
GPIOXINT2SEL
LPMCR0
GPIOXNMISEL
External Interrupt
MUX
Low Power
Modes Block
Asynchronous
path
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD
00
Input
Qualification
Internal
Pullup
PIE
N/C
01
Peripheral 1 Input
10
Peripheral 2 Input
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
GPxDAT (latch)
01
Peripheral 1 Output
10
Peripheral 2 Output
11
Peripheral 3 Output
00
GPxDIR (latch)
High Impedance
Output Control
0 = Input, 1 = Output
XRS
= Default at Reset
01
Peripheral 1 Output Enable
10
Peripheral 2 Output Enable
11
Peripheral 3 Output Enable
GPxMUX1/2
A.
x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B.
GPxDAT latch/read are accessed at the same memory location.
Figure 4-11. GPIO MUX Block Diagram
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The F28044 supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral
Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-10 shows the
GPIO register mapping.
Table 4-10. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL
0x6F80
2
GPIO A Control Register (GPIO0 to 31)
GPAQSEL1
0x6F82
2
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2
0x6F84
2
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1
0x6F86
2
GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2
0x6F88
2
GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR
0x6F8A
2
GPIO A Direction Register (GPIO0 to 31)
GPAPUD
0x6F8C
2
GPIO A Pull Up Disable Register (GPIO0 to 31)
GPAMCFG
0x6F8E
2
GPIO A Miscellaneous Configuration Register (GPIO0 to 31)
GPBCTRL
0x6F90
2
GPIO B Control Register (GPIO32 to 35)
GPBQSEL1
0x6F92
2
GPIO B Qualifier Select 1 Register (GPIO32 to 35)
GPBQSEL2
0x6F94
2
reserved
GPBMUX1
0x6F96
2
GPIO B MUX 1 Register (GPIO32 to 35)
GPBMUX2
0x6F98
2
reserved
GPBDIR
0x6F9A
2
GPIO B Direction Register (GPIO32 to 35)
GPBPUD
0x6F9C
2
GPIO B Pull Up Disable Register (GPIO32 to 35)
reserved
0x6F9E
0x6F9F
2
reserved
reserved
0x6FA0
0x6FBF
32
GPADAT
0x6FC0
2
GPIO Data Register (GPIO0 to 31)
GPASET
0x6FC2
2
GPIO Data Set Register (GPIO0 to 31)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPACLEAR
0x6FC4
2
GPIO Data Clear Register (GPIO0 to 31)
GPATOGGLE
0x6FC6
2
GPIO Data Toggle Register (GPIO0 to 31)
GPBDAT
0x6FC8
2
GPIO Data Register (GPIO32 to 35)
GPBSET
0x6FCA
2
GPIO Data Set Register (GPIO32 to 35)
GPBCLEAR
0x6FCC
2
GPIO Data Clear Register (GPIO32 to 35)
GPBTOGGLE
0x6FCE
2
GPIO Data Toggle Register (GPIO32 to 35)
reserved
0x6FD0
0x6FDF
16
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
0x6FE0
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL
0x6FE1
1
XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXNMISEL
0x6FE2
1
XNMI GPIO Input Select Register (GPIO0 to 31)
reserved
0x6FE3
0x6FE7
5
GPIOLPMSEL
0x6FE8
2
reserved
0x6FEA
0x6FFF
22
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LPM GPIO Select Register (GPIO0 to 31)
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Table 4-11. F28044 GPIO MUX Table
GPxMUX1/2
(1)
REGISTER
BITS
DEFAULT AT
RESET
PRIMARY I/O
FUNCTION
(GPxMUX1/2
BITS = 0,0)
PERIPHERAL
SELECTION 1 (2)
(GPxMUX1 BITS = 0,1)
PERIPHERAL
SELECTION 2 (2)
(GPxMUX1/2 BITS = 1,0)
PERIPHERAL
SELECTION 3 (2)
(GPxMUX1/2 BITS =
1,1)
GPAMCFG(EPWMMODE) (3)
0,0 (4)
1,1
GPAMUX1
1-0
GPIO0
EPWM1A (O)
EPWM1A (O)
Reserved
Reserved
3-2
GPIO1
EPWM1B (O)
EPWM2A (O)
Reserved
Reserved
5-4
GPIO2
EPWM2A (O)
EPWM3A (O)
Reserved
Reserved
7-6
GPIO3
EPWM2B (O)
EPWM4A (O)
Reserved
Reserved
Reserved
9-8
GPIO4
EPWM3A (O)
EPWM5A (O)
Reserved
11-10
GPIO5
EPWM3B (O)
EPWM6A (O)
Reserved
Reserved
13-12
GPIO6
EPWM4A (O)
EPWM7A (O)
EPWMSYNCI (I)
EPWMSYNCO (O)
15-14
GPIO7
EPWM4B (O)
EPWM8A (O)
Reserved
Reserved
17-16
GPIO8
EPWM5A (O)
EPWM9A (O)
Reserved
ADCSOCAO (O)
19-18
GPIO9
EPWM5B (O)
EPWM10A (O)
Reserved
Reserved
21-20
GPIO10
EPWM6A (O)
EPWM11A (O)
Reserved
ADCSOCBO (O)
23-22
GPIO11
EPWM6B (O)
EPWM12A (O)
Reserved
Reserved
25-24
GPIO12
TZ1 (I)
EPWM13A (O)
Reserved
Reserved
27-26
GPIO13
TZ2 (I)
EPWM14A (O)
Reserved
Reserved
29-28
GPIO14
TZ3 (I)
EPWM15A (O)
Reserved
Reserved
31-30
GPIO15
TZ4 (I)
EPWM16A (O)
Reserved
Reserved
GPAMUX2
1-0
GPIO16
SPISIMOA (I/O)
Reserved
TZ5 (I)
3-2
GPIO17
SPISOMIA (I/O)
Reserved
TZ6 (I)
5-4
GPIO18
SPICLKA (I/O)
Reserved
TZ1 (I)
7-6
GPIO19
SPISTEA (I/O)
Reserved
TZ2 (I)
9-8
GPIO20
Reserved
Reserved
Reserved
11-10
GPIO21
Reserved
Reserved
Reserved
13-12
GPIO22
Reserved
Reserved
Reserved
15-14
GPIO23
Reserved
Reserved
Reserved
17-16
GPIO24
Reserved
Reserved
Reserved
19-18
GPIO25
Reserved
Reserved
Reserved
21-20
GPIO26
Reserved
Reserved
Reserved
23-22
GPIO27
Reserved
Reserved
Reserved
25-24
GPIO28
SCIRXDA (I)
Reserved
TZ5 (I)
27-26
GPIO29
SCITXDA (O)
Reserved
TZ6 (I)
29-28
GPIO30
Reserved
Reserved
TZ3 (I)
31-30
GPIO31
Reserved
Reserved
TZ4 (I)
GPBMUX1
(1)
(2)
(3)
(4)
64
1-0
GPIO32
SDAA (I/OC)
EPWMSYNCI (I)
ADCSOCAO (O)
3-2
GPIO33
SCLA (I/OC)
EPWMSYNCO (O)
ADCSOCBO (O)
5-4
GPIO34
Reserved
Reserved
Reserved
GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.
The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
The options GPAMCFG(EPWMMODE) = 0, 1 and 1, 0 are reserved.
This is the default configuration upon reset.
Peripherals
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The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
• Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0,0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2=0,1 and 1,0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before
the input is allowed to change.
Time between samples
GPyCTRL Reg
GPIOx
SYNC
Qualification
Input Signal
Qualified By 3
or 6 Samples
GPxQSEL
SYSCLKOUT
Number of Samples
Figure 4-12. Qualification Using Sampling Window
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multi-level multiplexing that is required on the F28044 device, there may be cases where a
peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not
selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.
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5
Device Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of 280x-based applications:
Software Development Tools
• Code Composer Studio™ Integrated Development Environment (IDE)
– C/C++ Compiler
– Code generation tools
– Assembler/Linker
– Cycle Accurate Simulator
• Application algorithms
• Sample applications code
Hardware Development Tools
• 2808 eZdsp™
• JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510USB™
• Universal 5-V dc power supply
• Documentation and cables
5.1
Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one of
three prefixes: TMX, TMP, or TMS (e.g., TMS320F2808). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/TMDX) through fully qualified
production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PBK) and temperature range (for example, A). Figure 5-1 provides a legend
for reading the complete device name for any family member.
TMS
320
F
28044
PZ
A
PREFIX
TMX = Experimental Device
TMP = Prototype Device
TMS = Qualified Device
DEVICE FAMILY
320 = TMS320E DSP Family
TECHNOLOGY
F = Flash EEPROM
(1.8-V Core/3.3-V I/O)
TEMPERATURE RANGE
A
= –405C to 855C
S
= –405C to 1255C
Q = –405C to 1255C — Q100 Fault Grading
PACKAGE TYPE
PZ
= 100-Pin Low-Profile Quad
Flatpack (LQFP)
GGM = 100-Ball Ball Grid Array (BGA)
ZGM = 100-Ball Lead-Free BGA
DEVICE
28044
Figure 5-1. Example of TMS320x280x Device Nomenclature
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5.2
Documentation Support
Extensive documentation supports all of the TMS320™ DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets and data manuals, with design specifications; and hardware and software applications.
TMS320F28044 device reference guides are applicable to the UCD9501 device as well. Useful reference
documentation includes:
CPU User's Guides
SPRU430
TMS320C28x DSP CPU and Instruction Set Reference Guide describes the central
processing unit (CPU) and the assembly language instructions of the TMS320C28x
fixed-point digital signal processors (DSPs). It also describes emulation features available on
these DSPs.
SPRU712
TMS320x28xx, 28xxx System Control and Interrupts Reference Guide describes the various
interrupts and system control features of the 280x digital signal processors (DSPs).
Peripheral Guides
SPRU566
TMS320x28xx, 28xxx Peripheral Reference Guide describes the peripheral reference guides
of the 28x digital signal processors (DSPs).
68
SPRU716
TMS320x280x, 2801x, 2804x Analog-to-Digital Converter (ADC) Reference Guide describes
how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.
SPRU791
TMS320x28xx, 28xxx Enhanced Pulse Width Modulator (ePWM) Module Reference Guide
describes the main areas of the enhanced pulse width modulator that include digital motor
control, switch mode power supply control, UPS (uninterruptible power supplies), and other
forms of power conversion
SPRU924
TMS320x28xx, 28xxx High-Resolution Pulse Width Modulator (HRPWM) describes the
operation of the high-resolution extension to the pulse width modulator (HRPWM)
SPRU807
TMS320x28xx, 28xxx Enhanced Capture (eCAP) Module Reference Guide describes the
enhanced capture module. It includes the module description and registers.
SPRU790
TMS320x28xx, 28xxx Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide
describes the eQEP module, which is used for interfacing with a linear or rotary incremental
encoder to get position, direction, and speed information from a rotating machine in high
performance motion and position control systems. It includes the module description and
registers
SPRU074
TMS320x28xx, 28xxx Enhanced Controller Area Network (eCAN) Reference Guide
describes the eCAN that uses established protocol to communicate serially with other
controllers in electrically noisy environments.
SPRU051
TMS320x28xx, 28xxx Serial Communication Interface (SCI) Reference Guide describes the
SCI, which is a two-wire asynchronous serial port, commonly known as a UART. The SCI
modules support digital communications between the CPU and other asynchronous
peripherals that use the standard non-return-to-zero (NRZ) format.
SPRU059
TMS320x28xx, 28xxx Serial Peripheral Interface (SPI) Reference Guide describes the SPI a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmed bit-transfer rate.
SPRU721
TMS320x28xx, 28xxx Inter-Integrated Circuit (I2C) Reference Guide describes the features
and operation of the inter-integrated circuit (I2C) module that is available on the
TMS320x280x digital signal processor (DSP).
SPRU722
TMS320x280x, 2801x, 2804x Boot ROM Reference Guide describes the purpose and
features of the bootloader (factory-programmed boot-loading software). It also describes
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other contents of the device on-chip boot ROM and identifies where all of the information is
located within that memory.
Tools Guides
SPRU513
TMS320C28x Assembly Language Tools User's Guide describes the assembly language
tools (assembler and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the
TMS320C28x device.
SPRU514
TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x™ C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320
DSP assembly language source code for the TMS320C28x device.
SPRU608
The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,
available within the Code Composer Studio for TMS320C2000 IDE, that simulates the
instruction set of the C28x™ core.
SPRU625
TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide
describes development using DSP/BIOS.
Application Reports and Software
Key Links Include:
1. C2000 Get Started - www.ti.com/c2000getstarted
2. C2000 Digital Motor Control Software Library - www.ti.com/c2000appsw
3. C2000 Digital Power Supply Software Library - www.ti.com/dpslib
4. DSP Power Management Reference Designs - www.ti.com/dsppower
SPRAAM0
Getting Started With TMS320C28x™ Digital Signal Controllers is organized by development
flow and functional areas to make your design effort as seamless as possible. Tips on
getting started with C28x™ DSP software and hardware development are provided to aid in
your initial design and debug efforts. Each section includes pointers to valuable information
including technical documentation, software, and tools for use in each phase of design.
SPRA958
Running an Application from Internal Flash Memory on the TMS320F28xx DSP covers the
requirements needed to properly configure application software for execution from on-chip
flash memory. Requirements for both DSP/BIOS™ and non-DSP/BIOS projects are
presented. Example code projects are included.
SPRAA85
Programming TMS320x28xx and 28xxx Peripherals in C/C++ explores a hardware
abstraction layer implementation to make C/C++ coding easier on 28x DSPs. This method is
compared to traditional #define macros and topics of code efficiency and special case
registers are also addressed.
SPRAA88
Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x presents a method
for utilizing the on-chip pulse width modulated (PWM) signal generators on the
TMS320F280x family of digital signal controllers as a digital-to-analog converter (DAC).
SPRAA91
TMS320F280x DSC USB Connectivity Using TUSB3410 USB-to-UART Bridge Chip presents
hardware connections as well as software preparation and operation of the development
system using a simple communication echo program.
SPRAAH1
Using the Enhanced Quadrature Encoder Pulse (eQEP) Module provides a guide for the use
of the eQEP module as a dedicated capture unit and is applicable to the TMS320x280x,
28xxx family of processors.
SPRAA58
TMS320x281x to TMS320x280x Migration Overview describes differences between the
Texas Instruments TMS320x281x and TMS320x280x DSPs to assist in application migration
from the 281x to the 280x. While the main focus of this document is migration from 281x to
280x, users considering migrating in the reverse direction (280x to 281x) will also find this
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document useful.
SPRAAI1
Using Enhanced Pulse Width Modulator (ePWM) Module for 0-100% Duty Cycle Control
provides a guide for the use of the ePWM module to provide 0% to 100% duty cycle control
and is applicable to the TMS320x280x family of processors.
SPRAAD5
Power Line Communication for Lighting Apps using BPSK w/ a Single DSP Controller
presents a complete implementation of a power line modem following CEA-709 protocol
using a single DSP.
SPRAAD8
TMS320280x and TMS320F2801x ADC Calibration describes a method for improving the
absolute accuracy of the 12-bit ADC found on the TMS320280x and TMS3202801x devices.
Inherent gain and offset errors affect the absolute accuracy of the ADC. The methods
described in this report can improve the absolute accuracy of the ADC to levels better than
0.5%. This application report has an option to download an example program that executes
from RAM on the F2808 EzDSP.
SPRA820
Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for
online stack overflow detection on the TMS320C28x™ DSP. C-source code is provided that
contains functions for implementing the overflow detection on both DSP/BIOS™ and
non-DSP/BIOS applications.
SPRA806
An Easy Way of Creating a C-callable Assembly Function for the TMS320C28x DSP
provides instructions and suggestions to configure the C compiler to assist with
understanding of parameter-passing conventions and environments expected by the C
compiler.
Software
SPRC191
Download: C280x, C2801x C/C++ Header Files and Peripheral Examples
SPRM246
F28044 GGM/ZGM BSDL Model
SPRM247
F28044 PZ BSDL Model
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this data manual (literature number SPRS230), use the
[email protected] email address, which is a repository for feedback. For questions and support,
contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
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6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320F28044 DSP.
6.1
Absolute Maximum Ratings (1) (2)
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.
Supply voltage range, VDDIO, VDD3VFL
with respect to VSS
- 0.3 V to 4.6 V
Supply voltage range, VDDA2, VDDAIO
with respect to VSSA
- 0.3 V to 4.6 V
Supply voltage range, VDD
with respect to VSS
- 0.3 V to 2.5 V
Supply voltage range, VDD1A18, VDD2A18
with respect to VSSA
- 0.3 V to 2.5 V
Supply voltage range, VSSA2, VSSAIO, VSS1AGND, VSS2AGND
with respect to VSS
- 0.3 V to 0.3 V
Input voltage range, VIN
- 0.3 V to 4.6 V
Output voltage range, VO
- 0.3 V to 4.6 V
± 20 mA
Input clamp current, IIK (VIN < 0 or VIN > VDDIO) (3)
± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDDIO)
Operating ambient temperature range,
Junction temperature range, Tj (4)
Storage temperature range, Tstg
(1)
(2)
(3)
(4)
(4)
TA: A version (GGM, PZ) (4)
- 40°C to 85°C
- 40°C to 150°C
- 65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
Continuous clamp current per pin is ± 2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the
voltage to a diode drop above VDDA2 or below VSSA2.
Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963)
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6.2
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Device supply voltage, I/O, VDDIO
3.14
3.3
3.47
V
Device supply voltage CPU, VDD
1.71
1.8
1.89
V
Supply ground, VSS, VSSIO
0
V
ADC supply voltage (3.3 V), VDDA2, VDDAIO
3.14
3.3
3.47
V
ADC supply voltage (1.8 V), VDD1A18, VDD2A18
1.71
1.8
1.89
V
Flash supply voltage, VDD3VFL
3.14
3.3
3.47
V
MHz
Device clock frequency (system clock), fSYSCLKOUT
2
100
High-level input voltage, VIH
2
VDDIO
Low-level input voltage, VIL
High-level output source current, VOH = 2.4 V, IOH
Low-level output sink current, VOL = VOL MAX, IOL
Ambient temperature, TA
(1)
6.3
V
0.8
All I/Os except Group 2
-4
Group 2 (1)
-8
All I/Os except Group 2
4
Group 2 (1)
8
A version
-40
mA
mA
°C
85
Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1
Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
IIL
IIH
Input current
(low level)
Input current
(high level)
MIN
TYP
MAX
2.4
IOH = 50 µA
IOL = IOLMAX
0.4
VDDIO = 3.3 V, VIN = 0 V
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = 0 V
±2
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = VDDIO
±2
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = VDDIO (F280x)
28
50
80
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = VDDIO (C280x)
80
140
190
Output current, pullup or
pulldown disabled
CI
Input capacitance
Electrical Specifications
All I/Os (including XRS)
-80
UNIT
V
VDDIO - 0.2
Pin with pullup
enabled
IOZ
72
TEST CONDITIONS
IOH = IOHMAX
-140
V
-190
µA
±2
VO = VDDIO or 0 V
2
µA
µA
pF
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6.4
Current Consumption
Table 6-1. TMS320F28044 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
MODE
TEST CONDITIONS
IDDIO (1)
IDD
IDDA18 (2)
IDD3VFL
IDDA33 (3)
TYP (4)
MAX
TYP (4)
MAX
TYP
MAX
TYP (4)
MAX
TYP (4)
MAX
205 mA
230 mA
10 mA
15 mA
35 mA
40 mA
30 mA
38 mA
1.5 mA
2 mA
75 mA
90 mA
500 µA
2 mA
2 µA
10 µA
5 µA
50 µA
15 µA
30 µA
12 mA
100 µA
500 µA
2 µA
10 µA
5 µA
50 µA
15 µA
30 µA
60 µA
120 µA
2 µA
10 µA
5 µA
50 µA
15 µA
30 µA
The following peripheral
clocks are enabled:
•
ePWM1-16
•
SCI-A
•
SPI-A
•
ADC
Operational
(Flash)
IDLE
•
I2C
All PWM pins are toggled
at 100 kHz.
All I/O pins are left
unconnected.
Data is continuously
transmitted out of the
SCI-A port. The
hardware multiplier is
exercised.
Code is running out of
flash with 3 wait-states.
XCLKOUT is turned off.
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
•
SCI-A
•
SPI-A
•
I2C
STANDBY
Flash is powered down.
Peripheral clocks are off.
6 mA
HALT
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
70 µA
(1)
(2)
(3)
(4)
IDDIO current is dependent on the electrical loading on the I/O pins.
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
IDDA33 includes current into VDDA2 and VDDAIO pins.
The TYP numbers are applicable over room temperature and nominal voltage.
NOTE
The peripheral - I/O multiplexing implemented in the F28044 device prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done,
the current drawn by the device will be more than the numbers specified in the current
consumption tables.
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6.4.1
Reducing Current Consumption
Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption
can be achieved by turning off the clock to any peripheral module that is not used in a given application.
Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current
consumption even further. Table 6-2 indicates the typical reduction in current consumption achieved by
turning off the clocks.
Table 6-2. Typical Current Consumption by Various
Peripherals (at 100 MHz) (1)
(1)
(2)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION (mA)
ADC
8 (2)
I2C
5
ePWM
5
SCI
4
SPI
5
All peripheral clocks are disabled upon reset. Writing to/reading
from peripheral registers is possible only after the peripheral clocks
are turned on.
This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the
ADC (IDDA18) as well.
NOTE
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
NOTE
The baseline IDD current (current when the core is executing a dummy loop with no
peripherals enabled) is 110 mA, typical. To arrive at the IDD current for a given application,
the current-drawn by the peripherals (enabled by that application) must be added to the
baseline IDD current.
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6.5
Emulator Connection Without Signal Buffering for the DSP
Figure 6-1 shows the connection between the DSP and JTAG header for a single-processor configuration.
If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals
must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-1 shows
the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.
For details on buffering JTAG signals and multiple processor connections, see TMS320F/C24x DSP
Controllers CPU and Instruction Set Reference Guide (literature number SPRU160).
6 inches or less
VDDIO
VDDIO
5
13
EMU0
EMU0
PD
14
EMU1
EMU1
4
2
TRST
TRST
GND
TMS
GND
TDI
GND
TDO
GND
TCK
GND
6
1
TMS
8
3
TDI
10
7
TDO
12
11
TCK
9
TCK_RET
DSP
JTAG Header
Figure 6-1. Emulator Connection Without Signal Buffering for the DSP
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6.6
Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
6.6.1
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
f
fall time
X
Unknown, changing, or don't
care level
h
hold time
Z
High impedance
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
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6.6.2
Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
42 Ω
Data Sheet Timing Reference Point
3.5 nH
Transmission Line
Z0 = 50 Ω(Α)
Output
Under
Test
Device Pin(B)
4.0 pF
1.85 pF
A.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 6-2. 3.3-V Test Load Circuit
6.6.3
Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the F28044 DSP. Table 6-3 lists the cycle times of various clocks.
Table 6-3. TMS320x280x Clock Table and Nomenclature
MIN
On-chip oscillator
clock
XCLKIN (1)
SYSCLKOUT
XCLKOUT
HSPCLK (2)
LSPCLK (2)
ADC clock
(1)
(2)
(3)
tc(OSC), Cycle time
NOM
28.6
MAX
UNIT
50
ns
MHz
Frequency
20
35
tc(CI), Cycle time
10
250
ns
4
100
MHz
10
500
ns
MHz
Frequency
tc(SCO), Cycle time
Frequency
2
100
tc(XCO), Cycle time
10
2000
ns
Frequency
0.5
100
MHz
tc(HCO), Cycle time
10
100
MHz
50 (3)
Frequency
tc(LCO), Cycle time
10
Frequency
ns
40 (3)
25 (3)
Frequency
tc(ADCCLK), Cycle time
20 (3)
ns
100
MHz
12.5
MHz
80
ns
This also applies to the X1 pin if a 1.8-V oscillator is used.
Lower LSPCLK and HSPCLK will reduce device power consumption.
This is the default reset value if SYSCLKOUT = 100 MHz.
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6.7
Clock Requirements and Characteristics
Table 6-4. Input Clock Frequency
PARAMETER
fx
Input clock frequency
MIN
MAX
20
Crystal (X1/X2)
20
35
4
100
External oscillator/clock source (XCLKIN or X1 pin)
fl
TYP
Resonator (X1/X2)
Limp mode SYSCLKOUT frequency range (with /2 enabled)
UNIT
35
1-5
MHz
MHz
Table 6-5. XCLKIN (1) Timing Requirements - PLL Enabled
NO.
MIN
MAX
UNIT
33.3
200
ns
Fall time, XCLKIN
6
ns
tr(CI)
Rise time, XCLKIN
6
ns
C11
tw(CIL)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
45
55
%
C12
tw(CIH)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45
55
%
MIN
MAX
UNIT
10
250
ns
Up to 20 MHz
6
ns
20 MHz to 100 MHz
2
ns
Up to 20 MHz
6
ns
C8
tc(CI)
Cycle time, XCLKIN
C9
tf(CI)
C10
(1)
This applies to the X1 pin also.
Table 6-6. XCLKIN (1) Timing Requirements - PLL Disabled
NO.
C8
tc(CI)
Cycle time, XCLKIN
C9
tf(CI)
Fall time, XCLKIN
C10
tr(CI)
Rise time, XCLKIN
2
ns
C11
tw(CIL)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
45
55
%
C12
tw(CIH)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45
55
%
20 MHz to 100 MHz
(1)
This applies to the X1 pin also.
The possible configuration modes are shown in Table 3-13.
Table 6-7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
NO.
(1)
(2)
(3)
78
PARAMETER
MIN
TYP
MAX
UNIT
C1
tc(XCO)
Cycle time, XCLKOUT
10
C3
tf(XCO)
Fall time, XCLKOUT
2
ns
ns
C4
tr(XCO)
Rise time, XCLKOUT
2
ns
C5
tw(XCOL)
Pulse duration, XCLKOUT low
H-2
H+2
ns
C6
tw(XCOH)
Pulse duration, XCLKOUT high
H-2
H+2
ns
tp
PLL lock time
131072tc(OSCCLK) (3) cycles
A load of 40 pF is assumed for these parameters.
H = 0.5tc(XCO)
OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
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C10
C9
C8
XCLKIN(A)
C6
C3
C1
C4
C5
XCLKOUT(B)
A.
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B.
XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-3. Clock Timing
6.8
Power Sequencing
No requirements are placed on the power up/down sequence of the various power pins to ensure the
correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers
of the I/O pins are powered prior to the 1.8-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or
simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins
reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (see
Table 6-9). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 µs prior to VDD reaching 1.5 V. This is to
enhance flash reliability.
Additionally it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any
pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n
junctions in unintended ways and produce unpredictable results.
6.8.1
Power Management and Supervisory Circuit Solutions
Table 6-8 lists the power management and supervisory circuit solutions for F28044 DSP. LDO selection
depends on the total power consumed in the end application. Go to www.power.ti.com for a complete list
of TI power ICs or select TI DSP Power Solutions for links to the DSP Power Selection Guide
(slub006a.pdf) and links to specific power reference designs.
Table 6-8. Power Management and Supervisory Circuit Solutions
TYPE
PART
Texas Instruments
SUPPLIER
LDO
TPS767D301
Texas Instruments
LDO
TPS70202
Dual 500/250-mA LDO with SVS
Texas Instruments
LDO
TPS766xx
250-mA LDO with PG
Texas Instruments
SVS
TPS3808
Open Drain SVS with programmable delay
Texas Instruments
SVS
TPS3803
Low-cost Open-drain SVS with 5 µS delay
Texas Instruments
LDO
TPS799xx
200-mA LDO in WCSP package
Texas Instruments
LDO
TPS736xx
400-mA LDO with 40 mV of VDO
Texas Instruments
DC/DC
TPS62110
High Vin 1.2-A dc/dc converter in 4x4 QFN package
Texas Instruments
DC/DC
TPS6230x
500-mA converter in WCSP package
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DESCRIPTION
Dual 1-A low-dropout regulator (LDO) with supply voltage supervisor (SVS)
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VDDIO, VDD3VFL
VDDA2, VDDAIO
(3.3 V)
VDD, VDD1A18,
VDD2A18
(1.8 V)
XCLKIN
X1/X2
OSCCLK/8(A)
XCLKOUT
tOSCST
User-Code Dependent
tw(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
(Internal)
td(EX)
th(boot-mode)(B)
Boot-Mode
Pins
User-Code Execution Phase
User-Code Dependent
GPIO Pins as Input
Peripheral/GPIO Function
Based on Boot Code
Boot-ROM Execution Starts
I/O Pins(C)
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A.
Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =
OSCCLK/8 during this phase.
B.
After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
C.
See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up.
Figure 6-4. Power-on Reset
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Table 6-9. Reset (XRS) Timing Requirements
MIN
tw(RSL1)
(1)
Pulse duration, stable XCLKIN to XRS high
tw(RSL2)
Pulse duration, XRS low
tw(WDRS)
Pulse duration, reset pulse generated by
watchdog
td(EX)
Delay time, address/data valid after XRS high
tOSCST (2)
Oscillator start-up time
th(boot-mode)
Hold time for boot-mode pins
(1)
(2)
Warm reset
NOM
MAX
UNIT
8tc(OSCCLK)
cycles
8tc(OSCCLK)
cycles
512tc(OSCCLK)
cycles
32tc(OSCCLK)
cycles
1
10
200tc(OSCCLK)
ms
cycles
In addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
User-Code Dependent
OSCCLK * 5
tw(RSL2)
XRS
Address/Data/
Control
(Internal)
td(EX)
User-Code Execution
(Don’t Care)
Boot-ROM Execution Starts
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Execution Phase
GPIO Pins as Input
th(boot-mode)(A)
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A.
After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-5. Warm Reset
Figure 6-6 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.
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OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, tp) is
131072 OSCCLK Cycles Long.)
(Changed CPU Frequency)
Figure 6-6. Example of Effect of Writing Into PLLCR Register
6.9
6.9.1
General-Purpose Input/Output (GPIO)
GPIO - Output Timing
Table 6-10. General-Purpose Output Switching Characteristics
PARAMETER
MIN
MAX
UNIT
tr(GPO)
Rise time, GPIO switching low to high
All GPIOs
8
tf(GPO)
Fall time, GPIO switching high to low
All GPIOs
8
ns
ns
tfGPO
Toggling frequency, GPO pins
25
MHz
GPIO
tf(GPO)
tr(GPO)
Figure 6-7. General-Purpose Output Timing
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6.9.2
GPIO - Input Timing
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
tw(SP)
0
0
1
1
1
1
1
1
1
1
1
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C))
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A.
This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled).
B.
The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
Figure 6-8. Sampling Mode
Table 6-11. General-Purpose Input Timing Requirements
MIN
tw(SP)
Sampling period
tw(IQSW)
Input qualifier sampling window
tw(GPI) (2)
(1)
(2)
Pulse duration, GPIO low/high
MAX
UNIT
QUALPRD = 0
1tc(SCO)
cycles
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
cycles
tw(SP) * (n (1) - 1)
cycles
2tc(SCO)
cycles
tw(IQSW) + tw(SP) + 1tc(SCO)
cycles
Synchronous mode
With input qualifier
"n" represents the number of qualification samples as defined by GPxQSELn register.
For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
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6.9.3
Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
XCLKOUT
GPIOxn
tw(GPI)
Figure 6-9. General-Purpose Input Timing
The pulse-width requirement
XINT2_ADCSOC signal as well.
84
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NOTE
general-purpose
input
is
applicable
for
the
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6.9.4
Low-Power Mode Wakeup Timing
Table 6-12 shows the timing requirements, Table 6-13 shows the switching characteristics, and
Figure 6-10 shows the timing diagram for IDLE mode.
Table 6-12. IDLE Mode Timing Requirements (1)
MIN
tw(WAKE-INT)
(1)
Pulse duration, external wake-up signal
Without input qualifier
NOM
MAX
2tc(SCO)
With input qualifier
UNIT
cycles
5tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Table 6-11.
Table 6-13. IDLE Mode Switching Characteristics (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
20tc(SCO)
cycles
Delay time, external wake signal to
program execution resume (2)
•
td(WAKE-IDLE)
•
•
Wake-up from Flash
– Flash module in active state
Without input qualifier
Wake-up from Flash
– Flash module in sleep state
Without input qualifier
Wake-up from SARAM
Without input qualifier
With input qualifier
20tc(SCO) + tw(IQSW)
1050tc(SCO)
With input qualifier
20tc(SCO)
With input qualifier
(1)
(2)
cycles
1050tc(SCO) + tw(IQSW)
cycles
20tc(SCO) + tw(IQSW)
For an explanation of the input qualifier parameters, see Table 6-11.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
td(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE−INT)
WAKE INT(A)
A.
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-10. IDLE Entry and Exit Timing
Table 6-14. STANDBY Mode Timing Requirements
tw(WAKE-INT)
(1)
Pulse duration, external
wake-up signal
TEST CONDITIONS
MIN
Without input qualification
3tc(OSCCLK)
With input qualification (1)
(2 + QUALSTDBY) * tc(OSCCLK)
NOM
MAX
UNIT
cycles
QUALSTDBY is a 6-bit field in the LPMCR0 register.
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Table 6-15. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
Delay time, IDLE instruction
executed to XCLKOUT low
td(IDLE-XCOL)
MIN
TYP
32tc(SCO)
MAX
UNIT
45tc(SCO)
cycles
Delay time, external wake signal
to program execution resume (1)
•
td(WAKE-STBY)
•
Wake up from flash
– Flash module in active
state
Without input qualifier
Wake up from flash
– Flash module in sleep
state
Without input qualifier
100tc(SCO)
With input qualifier
100tc(SCO) + tw(WAKE-INT)
With input qualifier
Wake up from SARAM
cycles
1125tc(SCO)
1125tc(SCO) + tw(WAKE-INT)
Without input qualifier
•
(1)
cycles
100tc(SCO)
With input qualifier
100tc(SCO) + tw(WAKE-INT)
cycles
cycles
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
(A)
(C)
(B)
Device
Status
STANDBY
(E)
(D)
(F)
STANDBY
Normal Execution
Flushing Pipeline
Wake−up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
td(IDLE−XCOL)
A.
IDLE instruction is executed to put the device into STANDBY mode.
B.
The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being
turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C.
Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
D.
The external wake-up signal is driven active.
E.
After a latency period, the STANDBY mode is exited.
F.
Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-11. STANDBY Entry and Exit Timing Diagram
Table 6-16. HALT Mode Timing Requirements
MIN
tw(WAKE-GPIO)
Pulse duration, GPIO wake-up signal
tw(WAKE-XRS)
Pulse duration, XRS wakeup signal
(1)
86
NOM
MAX
UNIT
toscst + 2tc(OSCCLK) (1)
cycles
toscst + 8tc(OSCCLK)
cycles
See Table 6-9 for an explanation of toscst.
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Table 6-17. HALT Mode Switching Characteristics
PARAMETER
MIN
td(IDLE-XCOL)
Delay time, IDLE instruction executed to XCLKOUT low
tp
PLL lock-up time
td(WAKE-HALT)
Delay time, PLL lock to program execution resume
• Wake up from flash
– Flash module in sleep state
•
TYP
32tc(SCO)
(C)
45tc(SCO)
cycles
cycles
1125tc(SCO)
cycles
35tc(SCO)
cycles
(D)
HALT
Flushing Pipeline
(G)
(E)
(B)
Device
Status
UNIT
131072tc(OSCCLK)
Wake up from SARAM
(A)
MAX
(F)
HALT
PLL Lock-up Time
Wake-up Latency
Normal
Execution
GPIOn
td(WAKE−HALT)
tw(WAKE-GPIO)
tp
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
td(IDLE−XCOL)
A.
IDLE instruction is executed to put the device into HALT mode.
B.
The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles before the oscillator is
turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush properly.
C.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
D.
When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The
GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock
signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup
procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.
E.
When GPIOn is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles.
F.
When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
G.
Normal operation resumes.
Figure 6-12. HALT Wake-Up Using GPIOn
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6.10 Enhanced Control Peripherals
6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing
Table 6-18 shows the PWM output timing requirements and Table 6-19, switching characteristics.
Table 6-18. ePWM Timing Requirements (1)
TEST CONDITIONS
tw(SYCIN)
Sync input pulse width
MIN
Asynchronous
(1)
UNIT
cycles
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
Synchronous
With input qualifier
MAX
2tc(SCO)
For an explanation of the input qualifier parameters, see Table 6-11.
Table 6-19. ePWM Switching Characteristics
PARAMETER
tw(PWM)
Pulse duration, PWMx output high/low
tw(SYNCOUT)
Sync output pulse width
td(PWM)tza
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
TEST CONDITIONS
MIN
MAX
20
UNIT
ns
8tc(SCO)
cycles
no pin load
25
ns
20
ns
6.10.2 Trip-Zone Input Timing
XCLKOUT(A)
tw(TZ)
TZ
td(TZ-PWM)HZ
PWM(B)
A.
TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B.
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-13. PWM Hi-Z Characteristics
Table 6-20. Trip-Zone input Timing Requirements (1)
MIN
tw(TZ)
Pulse duration, TZx input low
Asynchronous
Synchronous
With input qualifier
(1)
MAX
UNIT
1tc(SCO)
cycles
2tc(SCO)
cycles
1tc(SCO) + tw(IQSW)
cycles
For an explanation of the input qualifier parameters, see Table 6-11.
Table 6-21 shows the high-resolution PWM switching characteristics.
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Table 6-21. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
MIN
Micro Edge Positioning (MEP) step size (1)
(1)
TYP
MAX
UNIT
150
310
ps
Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
Table 6-22. External ADC Start-of-Conversion Switching Characteristics
PARAMETER
tw(ADCSOCAL)
MIN
Pulse duration, ADCSOCAO low
MAX
32tc(HCO)
UNIT
cycles
tw(ADCSOCAL)
ADCSOCAO
or
ADCSOCBO
Figure 6-14. ADCSOCAO or ADCSOCBO Timing
6.10.3 External Interrupt Timing
tw(INT)
XNMI, XINT1, XINT2
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 6-15. External Interrupt Timing
Table 6-23. External Interrupt Timing Requirements (1)
TEST CONDITIONS
tw(INT) (2)
(1)
(2)
Pulse duration, INT input low/high
MIN
MAX
UNIT
Synchronous
1tc(SCO)
cycles
With qualifier
1tc(SCO) + tw(IQSW)
cycles
For an explanation of the input qualifier parameters, see Table 6-11.
This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 6-24. External Interrupt Switching Characteristics (1)
PARAMETER
td(INT)
(1)
Delay time, INT low/high to interrupt-vector fetch
MIN
MAX
UNIT
tw(IQSW) + 12tc(SCO)
cycles
For an explanation of the input qualifier parameters, see Table 6-11.
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6.10.4 I2C Electrical Specification and Timing
Table 6-25. I2C Timing
TEST CONDITIONS
MIN
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
MAX
UNIT
400
kHz
fSCL
SCL clock frequency
vil
Low level input voltage
Vih
High level input voltage
Vhys
Input hysteresis
Vol
Low level output voltage
3 mA sink current
tLOW
Low period of SCL clock
I2C
clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3
µs
tHIGH
High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
µs
lI
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX
0.3 VDDIO
0.7 VDDIO
V
0.05 VDDIO
0
-10
V
V
0.4
10
V
µA
6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing
Table 6-26 lists the master mode timing (clock phase = 0) and Table 6-27 lists the timing (clock
phase = 1). Figure 6-16 and Figure 6-17 show the timing waveforms.
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Table 6-26. SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
MIN
MIN
MAX
tc(SPC)M
Cycle time, SPICLK
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
ns
2
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M - 0.5tc(LCO)
ns
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M - 0.5tc(LCO)
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO)-10
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO)- 10
0.5tc(SPC)M + 0.5tc(LCO)
td(SPCH-SIMO)M
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
10
10
td(SPCL-SIMO)M
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
10
10
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M + 0.5tc(LCO) -10
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M + 0.5tc(LCO) -10
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
35
35
ns
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
35
35
ns
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25tc(SPC)M -10
0.5tc(SPC)M- 0.5tc(LCO)- 10
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
0.25tc(SPC)M - 10
0.5tc(SPC)M- 0.5tc(LCO)- 10
4
5
8
9
(5)
MAX
UNIT
1
3
(1)
(2)
(3)
(4)
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
ns
ns
ns
The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
tc(LCO) = LSPCLK cycle time
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
SPISOMI
Master In Data
Must Be Valid
SPISTE(A)
A.
In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-16. SPI Master Mode External Timing (Clock Phase = 0)
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Table 6-27. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
MIN
MAX
tc(SPC)M
Cycle time, SPICLK
4tc(LCO)
128tc(LCO)
5tc(LCO)
127tc(LCO)
ns
2
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc (LCO)-10
0.5tc(SPC)M - 0.5tc(LCO)
ns
tw(SPCL))M
Pulse duration, SPICLK low (clock
polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc (LCO)-10
0.5tc(SPC)M - 0.5tc(LCO
ns
tw(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) - 10
0.5tc(SPC)M + 0.5tc(LCO)
ns
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO) -10
0.5tc(SPC)M + 0.5tc(LCO)
ns
tsu(SIMO-SPCH)M
Setup time, SPISIMO data valid
before SPICLK high (clock polarity
= 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 10
ns
tsu(SIMO-SPCL)M
Setup time, SPISIMO data valid
before SPICLK low (clock polarity =
1)
0.5tc(SPC)M -10
0.5tc(SPC)M - 10
ns
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 10
ns
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
ns
tsu(SOMI-SPCH)M
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
35
35
ns
tsu(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
35
35
ns
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
0.25tc(SPC)M -10
0.5tc(SPC)M -10
ns
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
0.25tc(SPC)M -10
0.5tc(SPC)M -10
ns
6
7
10
11
(4)
(5)
MIN
UNIT
1
3
(1)
(2)
(3)
MAX
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
Data Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE(A)
A.
In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-17. SPI Master External Timing (Clock Phase = 1)
6.10.6 SPI Slave Mode Timing
Table 6-28 lists the slave mode external timing (clock phase = 0) and Table 6-29 (clock phase = 1).
Figure 6-18 and Figure 6-19 show the timing waveforms.
Table 6-28. SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
NO.
MIN
MAX
tc(SPC)S
Cycle time, SPICLK Cycle time, SPICLK
13
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
td(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
35
ns
td(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
35
ns
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)
0.75tc(SPC)S
ns
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)
0.75tc(SPC)S
ns
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
35
ns
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
35
ns
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)
0.5tc(SPC)S-10
ns
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)
0.5tc(SPC)S-10
ns
14
15
16
19
20
(1)
(2)
(3)
(4)
(5)
94
4tc(LCO)
UNIT
12
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
tc(LCO) = LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO
SPISIMO Data
Must Be Valid
SPISTE(A)
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-18. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-29. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4)
NO.
tc(SPC)S
Cycle time, SPICLK
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
tsu(SOMI-SPCH)S
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
0.125tc(SPC)S
ns
tsu(SOMI-SPCL)S
Setup time, SPISOMI before SPICLK low (clock polarity = 1
0.125tc(SPC)S
ns
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK low (clock polarity
= 0)
0.75tc(SPC)S
ns
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
0.75tc(SPC)S
ns
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
35
ns
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
35
ns
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S-10
ns
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low (clock polarity
= 1)
0.5tc(SPC)S-10
ns
18
21
22
8tc(LCO)
UNIT
13
17
(4)
MAX
12
14
(1)
(2)
(3)
MIN
ns
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
SPISOMI Data Is Valid
Data Valid
21
22
SPISIMO
SPISIMO Data
Must Be Valid
SPISTE(A)
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-19. SPI Slave Mode External Timing (Clock Phase = 1)
96
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6.11 On-Chip Analog-to-Digital Converter
Table 6-30. ADC Electrical Characteristics (over recommended operating conditions) (1) (2)
PARAMETER
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS
Resolution
12
Bits
ADC clock
1
kHz
25
MHz
ACCURACY
INL (Integral nonlinearity)
1 - 25-MHz ADC clock (12.5 MSPS)
±2.0
LSB
DNL (Differential nonlinearity) (3)
1 - 25-MHz ADC clock (12.5 MSPS)
±1
LSB
60
LSB
Offset error
(4)
-60
±4
Offset error with hardware trimming
Overall gain error with internal reference
(5)
Overall gain error with external reference
LSB
-60
60
LSB
-60
60
LSB
Channel-to-channel offset variation
±4
LSB
Channel-to-channel gain variation
±4
LSB
ANALOG INPUT
Analog input voltage (ADCINx to ADCLO)
(6)
0
ADCLO
-5
Input capacitance
0
V
5
mV
10
pF
±5
Input leakage current
INTERNAL VOltAGE REFERENCE
3
µA
(5)
VADCREFP - ADCREFP output voltage at the pin based on
internal reference
1.275
V
VADCREFM - ADCREFM output voltage at the pin based on
internal reference
0.525
V
0.75
V
Voltage difference, ADCREFP - ADCREFM
Temperature coefficient
50
PPM/°C
EXTERNAL VOltAGE REFERENCE (5) (7)
VADCREFIN - External reference voltage input on ADCREFIN
pin 0.2% or better accurate reference recommended
ADCREFSEL[15:14] = 11b
1.024
V
ADCREFSEL[15:14] = 10b
1.500
V
ADCREFSEL[15:14] = 01b
2.048
V
67.5
dB
68
dB
AC SPECIFICATIONS
SINAD (100 kHz) Signal-to-noise ratio + distortion
SNR (100 kHz) Signal-to-noise ratio
THD (100 kHz) Total harmonic distortion
-79
dB
ENOB (100 kHz) Effective number of bits
10.9
Bits
83
dB
SFDR (100 kHz) Spurious free dynamic range
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Tested at 25-MHz ADCCLK.
All voltages listed in this table are with respect to VSSA2.
TI specifies that the ADC will have no missing codes.
1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal reference
is inclusive of the movement of the internal bandgap over temperature. Gain error over temperature for the external reference option will
depend on the temperature profile of the source used.
Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
TI recommends using high precision external reference TI part REF3020/3120 or equivalent for 2.048-V reference.
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6.11.1 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
td(BGR)
PWDNADC
td(PWD)
Request for
ADC
Conversion
Figure 6-20. ADC Power-Up Control Bit Timing
Table 6-31. ADC Power-Up Delays
PARAMETER (1)
td(BGR)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
td(PWD)
Delay time for power-down control to be stable. Bit delay time for band-gap
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
register (PWDNADC)must be set to 1 before any ADC conversions are initiated.
(1)
MIN
20
TYP
MAX
UNIT
5
ms
µs
50
1
ms
Timings maintain compatibility to the 281x ADC module. The F28044 ADC also supports driving all 3 bits at the same time and waiting
td(BGR) ms before first conversion.
Table 6-32. Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) (1) (2)
VDDA18
VDDA3.3
UNIT
Mode A (Operational Mode):
ADC OPERATING MODE
•
•
BG and REF enabled
PWD disabled
30
2
mA
Mode B:
•
•
•
ADC clock enabled
BG and REF enabled
PWD enabled
9
0.5
mA
Mode C:
•
•
•
ADC clock enabled
BG and REF disabled
PWD enabled
5
20
µA
Mode D:
•
•
•
ADC clock disabled
BG and REF disabled
PWD enabled
5
15
µA
(1)
(2)
98
CONDITIONS
Test Conditions:
SYSCLKOUT = 100 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO.
Electrical Specifications
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Rs
Source
Signal
ADCIN0
Ron
1 kΩ
Switch
Cp
10 pF
ac
Ch
1.64 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron):
Sampling Capacitor (Ch):
Parasitic Capacitance (Cp):
Source Resistance (Rs):
1 kΩ
1.64 pF
10 pF
50 Ω
Figure 6-21. ADC Analog Input Impedance Model
6.11.2 Definitions
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at
a time. These inputs are software-selectable.
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with
low power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:
• Sequential sampling mode (SMODE = 0)
• Simultaneous sampling mode (SMODE = 1)
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6.11.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an
external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on
every Sample/Hold pulse. The conversion time and latency of the Result register update are explained
below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The
selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Channel Ax or Bx
Sample n
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschx_n+1
tdschx_n
ADC Event Trigger from
ePWM or Other Sources
tSH
Figure 6-22. Sequential Sampling Mode (Single-Channel) Timing
Table 6-33. Sequential Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 25-MHz
ADC CLOCK,
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event trigger to
sampling
2.5tc(ADCCLK)
tSH
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
40 ns with Acqps = 0
td(schx_n)
Delay time for first result to appear
in Result register
4tc(ADCCLK)
160 ns
td(schx_n+1)
Delay time for successive results to
appear in Result register
100
Electrical Specifications
(2 + Acqps) *
tc(ADCCLK)
REMARKS
Acqps value = 0-15
ADCTRL1[8:11]
80 ns
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6.11.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or
from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register
update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold
pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC
clocks wide (maximum).
NOTE
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, etc.).
Sample n
Sample n+2
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschA0_n+1
tSH
ADC Event Trigger from
ePWM or Other Sources
tdschA0_n
tdschB0_n+1
tdschB0_n
Figure 6-23. Simultaneous Sampling Mode Timing
Table 6-34. Simultaneous Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 25-MHz
ADC CLOCK,
tc(ADCCLK) = 40 ns
td(SH)
Delay time from event trigger to
sampling
2.5tc(ADCCLK)
tSH
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
40 ns with Acqps = 0
td(schA0_n)
Delay time for first result to
appear in Result register
4tc(ADCCLK)
160 ns
td(schB0_n)
Delay time for first result to
appear in Result register
5tc(ADCCLK)
200 ns
td(schA0_n+1)
Delay time for successive results
to appear in Result register
(3 + Acqps) * tc(ADCCLK)
120 ns
td(schB0_n+1)
Delay time for successive results
to appear in Result register
(3 + Acqps) * tc(ADCCLK)
120 ns
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REMARKS
Acqps value = 0-15
ADCTRL1[8:11]
Electrical Specifications
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6.12 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is
defined as level one-half LSB beyond the last code transition. The deviation is measured from the center
of each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following
(SINAD * 1.76)
N+
6.02
formula,
it is possible to get a measure of performance expressed as N, the effective
number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency
can be calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
102
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6.13 Flash Timing
Table 6-35. Flash Endurance
Nf
Flash endurance for the array (write/erase cycles)
NOTP OTP endurance for the array (write cycles)
0°C to 85°C (ambient)
MIN
TYP
100
1000
0°C to 85°C (ambient)
MAX
UNIT
cycles
1
write
MAX
UNIT
Table 6-36. Flash Parameters at 100-MHz SYSCLKOUT
PARAMETER (1)
TEST CONDITIONS
MIN
TYP
Program
Time
16-Bit Word
50
µs
16K Sector
500
ms
Erase Time
16K Sector
10
S
IDD3VFLP
VDD3VFL current consumption during the
Erase/Program cycle
75
mA
IDDP
VDD current consumption during Erase/Program
cycle
IDDIOP
VDDIO current consumption during Erase/Program
cycle
(1)
Erase
Program
35
mA
140
mA
20
mA
Typical parameters as seen at room temperature using flash API version 3.00 including function call overhead.
Table 6-37. Flash/OTP Access Timing
PARAMETER
MIN
TYP
MAX
UNIT
ta(fp)
Paged flash access time
36
ns
ta(fr)
Random flash access time
36
ns
ta(OTP)
OTP access time
60
ns
Equations to compute the Flash page wait-state and random wait-state in Table 6-38 are as follows:
Flash Page Wait-State +
ƪǒ
Flash Random Wait-State +
ta(fp)
t c(SCO)
ƪǒ
Ǔ ƫ
* 1 (round up to the next highest integer) or 0, whichever is larger
ta(fr)
t c(SCO)
Ǔ ƫ
*1
(round up to the next highest integer) or 1, whichever is larger
Equation to compute the OTP wait-state in Table 6-38 is as follows:
OTP Wait-State +
ƪǒ
ta(OTP)
t c(SCO)
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Ǔ ƫ
* 1 (round up to the next highest integer) or 1, whichever is larger
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Table 6-38. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT
(MHz)
(1)
104
SYSCLKOUT (ns)
FLASH PAGE
WAIT-STATE
FLASH RANDOM
WAIT-STATE (1)
OTP
WAIT-STATE
100
10
3
3
5
75
13.33
2
2
4
50
20
1
1
2
30
33.33
1
1
1
25
40
0
1
1
15
66.67
0
1
1
4
250
0
1
1
Random wait-state must be greater than or equal to 1.
Electrical Specifications
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7
Mechanical Data
Table 7-1 and Table 7-2 show the thermal data.
The mechanical package diagram(s) that follow the tables reflect the most current released mechanical
data available for the designated device(s).
Table 7-1. F28044 Thermal Model 100-pin GGM Results
AIR FLOW
PARAMETER
0 lfm
150 lfm
250 lfm
500 lfm
θJA[°C/W] High k PCB
28.15
26.89
25.68
24.22
ΨJT[°C/W]
0.38
0.35
0.33
0.44
θJC
10.36
θJB
13.3
Table 7-2. F28044 Thermal Model 100-pin PZ Results
AIR FLOW
PARAMETER
0 lfm
150 lfm
250 lfm
500 lfm
θJA[°C/W] High k PCB
44.02
28.34
36.28
33.68
ΨJT[°C/W]
0.2
0.56
0.7
0.95
θJC
7.06
θJB
28.76
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Mechanical Data
105
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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