TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC WRN RDN BBUSN GND VDD GND VDD GND GND CSN GND MODE NC DCAS RESETN LADCS GND VDD GND ATNN GND DIO8N RENN GND DIO7N SRQN DIO5N IFCN GND DIO6N Generic Pin Configuration 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DATA5 DATA4 GND DATA3 DATA2 DATA1 GND VDD DATA0 RDY1 GND VDD GND INTR DACKN DRQ BURST_RDN TRIG VDD GND PAGED GND REM SWAPN FIFO_RDY TNT4882 Generic Pin Configuration BBUS_OEN KEYCLKN KEYDQ KEYRSTN DATA7 DATA6 GND ADDR3 ADDR4 ABUS_OEN TADCS CPUACC VDD XTAL0 XTAL1 GND 50 49 48 DATA11 GND DATA10 DATA9 DATA8 VDD GND ABUSN ADDR0 ADDR1 ADDR2 DIO3N GND DIO2N DIO1N GND 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DATA15 DATA14 GND DATA13 DATA12 NDACN NRFDN GND DAVN EOIN GND VDD DIO4N Figure 3. TNT4882 Generic Pin Configuration Generic Pin Description All pins with names that end in ‘N’ are active low; all others are active high. All input (I) and bidirectional (I/O) pins have an internal pull-up resistor between 50 kΩ and 150 kΩ. Note: You can also see the “Hardware Considerations” chapter of the “TNT Programmer Reference Manual” (P/N 320724-01) for more information. Pin No.(s) 1 2,3,5,6,7,9,10,11 Name(s) BBUS_OEN DATA15-8 Type O I/O 14 19-15 20 21 22 23 26 28 29 30 31 ABUSN ADDR4-0 ABUS_OEN TADCS CPUACC TRIG PAGED REM SWAPN FIFO_RDY BURST_RDN I I O O O O I O I O I 32 33 34 38 DRQ DACKN INTR RDY1 O I O O 50,49,47,46, 44,43,42,39 DATA7-0 I/O Description Asserts when DATA7-0 (B bus) is enabled for output Upper 8 bits of bidirectional three-state data bus for transfer of commands, data, and status between TNT4882 and CPU – also known as the A bus Enables register accesses through the A bus (DATA15-8) – DATA15 is the most significant bit Determines which register to access during a read or write operation Asserts when DATA15-8 (A bus) is enabled for output Asserts when the TNT4882 is an active or addressed IEEE 488 Talker (TADS, TACS, or SPAS) Asserts in two-chip mode during a NAT4882 register I/O access Asserts when in DTAS or when the auxiliary trigger software command is issued Asserting this pin pages in the page-in registers in the 7210 mode Asserts when the TNT4882 is in a remote state (REMS or RWLS) Rearranges the order of the registers when asserted and in 9914 mode Asserts when the FIFO is ready for burst access When asserted, places the TNT4882 in a burst read mode, in which the first word in the FIFO is always driven on the TNT4882 data bus – words are removed from the FIFOs at each rising edge of RDN – see reference manual for details Asserts to request a DMA transfer cycle Enables FIFO accesses during a DMA transfer cycle Asserts when one or more of the unmasked interrupt conditions becomes true Asserts during an I/O access to indicate that the read data is available or that the write data has been latched – asserts immediately on an access to Turbo488 registers or in one-chip mode Lower eight bits of bidirectional three-state data bus for transfer of commands, data, and status between TNT4882 and CPU – also known as the B bus – DATA7 is the most significant bit Table continued on page 4 National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com 3 TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC Table continued from page 3 Pin No.(s) 51 52 53 Name(s) DCAS NC MODE Type O O I 55 62 63 CSN BBUSN RDN I I I 64 WRN I 66 67 71,74,77,80,88, 89,91,92 70,73,76,79, 81,82,84,85 LADCS RESETN DIO8-1N O I I/O Description Asserts when the device clear state machine is in DCAS Leave this pin unconnected Determines whether the TNT4882 powers up in 7210 or 9914 emulation mode – High = 7210 mode, Low = 9914 mode Chip Select enables I/O transfers between the CPU and the TNT4882 Enables register accesses through the B bus (DATA7-0) Enables the contents of the registers selected by ADDR 4:0 and CSN or the FIFOs to appear on the data bus selected by ABUSN and BBUSN Latches data on the bus selected by ABUSN and BBUSN into an internal TNT4882 register on the trailing (rising) edge of WRN Asserts when the TNT4882 is addressed as a Listener Holds the TNT4882 in its idle state 8-bit bidirectional IEEE 488 data bus RENN, ATNN, SRQN, IFCN, NDACN, NRFDN, DAVN, EOIN XTAL0 XTAL1 KEYCLKN KEYDQ KEYRSTN GND I/O IEEE 488 control signals O I O I/O O _ Output of crystal circuit – use only for driving a quartz crystal Crystal oscillator input – drive with a 40 MHz CMOS input level clock signal Strobes data to or from a DS1204 electronic key Transmits serial data between the TNT4882 and a DS1204 key Resets a DS1204 key Ground pins – 0 V VDD _ Power pins – +5 V (±5%) RESET IOCS16N GND VDD GND RENN ATNN GND DIO8N GND DIO7N SRQN IFCN GND DIO6N DIO5N ISA Pin Configuration IOWN IORN SENSE_8_16N GND VDD VDD VDD GND VDD SW5 NC MODE SW9 SW8 95 96 98 99 100 4,8,13,25,27,35,37 41,45,48,54,56,57, 59,61,65,68,72,75, 78,83,86,90,93,97 12,24,36,40,58, 60,69,87,94 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ADDR6 ADDR7 ADDR8 VDD GND ADDR5 GND SW7 ADDR3 ADDR4 D15_8_OEN NC SW6 ADDR0 ADDR1 ADDR2 D7_0_OEN GND KEYCLKN KEYDQ KEYRSTN TNT4882 ISA Pin Configuration BHEN_N XTAL0 XTAL1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DATA11 GND DATA10 DATA9 DATA8 VDD GND GND VDD 50 49 GND DATA13 DATA12 DIO4N DIO3N GND DIO2N DIO1N 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DATA15 DATA14 NDACN NRFDN GND DAVN EOIN GND VDD Figure 4. TNT4882 ISA Pin Configuration 4 National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com DATA7 DATA6 GND DATA5 DATA4 GND DATA3 DATA2 DATA1 GND VDD DATA0 IOCHRDY AEN_N VDD GND INTR DACKN DRQ ADDR9 TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC ISA Pin Description All input (I) and bidirectional (I/O) pins have an internal pull-up resistor between 50 kΩ and 150 kΩ. Pins with names that end in “N” are active low signals – all others are active high. Open-collector outputs are type “OC.” Note: You can also see the “Hardware Considerations” chapter of the “TNT Programmer Reference Manual” (P/N 320724-01) for more information. Pin No.(s) 1 2,3,5,6,7,9,10,11 Name(s) D7_0_OEN DATA15-8 14 19-15 31,30,29,28,26 BHEN_N ADDR4-0 ADDR9-5 20 21,54 52,51,23,22,55 32 33 34 37 38 D15_8_OEN NC SW9-5 DRQ DACKN INTR AEN_N IOCHRDY O O I O I O I OC 50,49,47,46,44, 43,42,39 DATA7-0 I/O 53 MODE I 62 SENSE_8_16N I 63 IORN I 64 IOWN I 66 67 71,74,77,80,88, 89,91,92 70,73,76,79,81, 82,84,85 IOCS16N RESET DIO8-1N RENN, ATNN, SRQN, IFCN, NDACN, NRFDN, DAVN, EOIN XTAL0 XTAL1 KEYCLKN KEYDQ KEYRSTN GND 95 96 98 99 100 4,8,13,25,27,35,41, 45,48,57,61,65,68,72, 75,78,83,86,90,93,97 12,24,36,40,56,58, 59,60,69,87,94 VDD Type O I/O Description Asserts when DATA7-0 bus is enabled for output – may be left unconnected Upper eight bits of bidirectional three-state data bus for transfer of commands, data, and status between TNT4882 and CPU – can connect directly to the AT bus – DATA15 is the most significant bit I I I OC I I/O Enables access to upper eight bits of data bus when asserted Determines which register will be accessed during an I/O access Determines if an I/O address is within the range occupied by the TNT4882 – the chip is selected and an I/O access occurs when ADDR9-5 match SW9-5 and AEN_N is asserted Asserts when DATA15:8 bus is enabled for output – may be left unconnected Leave unconnected Determines the base address of the TNT4882 Asserts to request a DMA transfer cycle Enables FIFO accesses during a DMA transfer cycle Asserts when one or more of the unmasked interrupt conditions becomes true Enables I/O accesses to the TNT4882 When the TNT4882 is not accessed, this open-collector signal is not driven, and a pull-up resistor on the system board keeps it pulled high – at the start of some TNT4882 accesses, the TNT4882 may drive it low, then pull it high again during the cycle to indicate that the TNT4882 is ready for the CPU to end that cycle Lower eight bits of bidirectional three-state data bus for transfer of commands, data, and status between TNT4882 and CPU – can connect directly to the AT bus – DATA7 is the most significant bit Forces the TNT4882 to 7210 (high) or 9914 (low) emulation mode on a hardware reset – may be left unconnected Pull this pin low to tell the TNT4882 that it is connected to a 16-bit bus – leave it unconnected if the TNT4882 is connected to an 8-bit bus Drives the contents of the register selected by ADDR4-0 on the data bus when the TNT4882 is selected The value on the data bus is latched into the register selected by ADDR4-0 on the rising edge of IOWN when you select the TNT4882 Driven low during an access to the upper data bus Causes a hardware reset and holds the TNT4882 in its idle state while asserted 8-bit bidirectional IEEE 488 data bus I/O IEEE 488 control signals O I O I/O O – Output of crystal circuit – use only for driving a quartz crystal Crystal oscillator input – drive with a 40 MHz CMOS input level clock signal Strobes data to or from the DS1204 electronic key Transmits serial data between the TNT4882 and a DS1204 key Resets a DS1204 key Ground pins – 0 V – Power pins – +5 V (±5%) National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com 5 TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC TNT4882 Register Map NAT4882 Registers 7210 Mode Read Register Write Register DIR CDOR 9914 Mode Read Register Write Register ISR0 IMR0 9914 Mode Swapped Read Register Write Register DIR CDOR ADDR4-0 00000 Hex Offset 0 00010 00100 “ “ “ 2 4 “ “ “ ISR1 ISR2 IMR1 IMR2 ISR1 ADSR IMR1 IMR2 EOSR BCR ACCR CPTR SPSR PPR SPMR 00110 01000 “ “ “ 6 8 “ “ “ SPSR ADSR SPMR ADMR BSR ISR2 AUXCR ADR ISR2 ADSR ADR IMR2 EOSR BCR ACCR 01010 01100 01110 10001 10011 A C E 11 13 CPTR ADR0 ADR1 DSR – AUXMR ADR EOSR SH_CNT HIER SPSR CPTR DIR – – SPMR PPR CDOR – – BSR ISR0 ISR1 – – AUXCR IMR0 IMR1 – – 10101 15 – MISC – – – – 10111 11011 11101 11111 17 1B 1D 1F CSR SASR ISR0 BSR KEYREG DCR IMR0 BCR – – – – – – – – – – – – – – – – ADDR4-0 01001 Hex Offset 9 Read Register CNT2 Write Register CNT2 01011 01101 B D CNT3 – CNT3 HSSEL 10000 10010 10100 10 12 14 STS1 IMR3 CNT0 CFG IMR3 CNT0 10110 11000 16 18 CNT1 FIFOB CNT1 FIFOB 11001 11010 11100 19 1A 1C FIFOA ISR3 STS2 FIFOA CCR CMDR 11110 1E TIMER TIMER Turbo488 Registers (Same in All Modes) Special Registers Only Accessible in ISA Pin Configuration ADDR4-0 00101 Hex Offset 5 Read Register – Write Register ACCWR 00111 7 – INTR Notes on Register Map 1. For complete register descriptions, see the “TNT4882 Programmer Reference Manual” (320724-01) 2. Some of the 7210 mode registers, such as the ISR1, have the same names as some of the 9914 mode registers. The 7210 mode registers are NOT the same as their 9914 mode counterparts. Be sure to refer to the appropriate bit map for the chip emulation mode you are using when programming these registers. 3. The shaded registers are “paged-in registers.” Paged-in registers only exist in 9914 mode. Writing to the address of the 9914 mode ADSR normally does not access any registers. Writing one of four page-in commands to the AUXCR changes all subsequent writes to that address to that of the 6 corresponding paged-in register. The two readable paged-in registers, the 9914 mode SPSR and ISR2, are both paged in whenever any one of the four writable paged-in registers is paged in. When you write the clear page-in command to the AUXCR, all paged-in registers are paged out again and are no longer accessible. 4. There are several unused bytes in the address space of the TNT4882. These addresses are reserved for adding new features to the chip. You should not map any external hardware into these addresses or access them at any time, as this may cause compatibility problems with future versions of the TNT4882. National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC Hardware Interfacing – ISA Mode TNT4882 GPIB AT(ISA) Bus Connector NC NC NC BALE SA19-16 LA23-17 NC NC NC NC SMEMR* SMEMW* MEMR* MEMW* NC NC NC MEMCS16* NOWS* REFRESH* NC MASTER16* NC IOCHK* NC NC BCLK OSC NC TC TNT4882 SD15-0 DATA15-0 SA9-0 ADDR9-0 SBHE* AEN IOCHRDY RESET IOW* IOR* IOCS16* BHEN_N AEN_N IOCHRDY RESET IOWN IORN IOCS16N DACK*7-5 DRQ7-5 IRQ (3-7,9,10-12,14,15) NC NC NC D15_8_OEN D7_0_OEN MODE NC NC NC KEYRSTN KEYDQ KEYCLKN BALE SA19-16 LA23-17 NC NC NC NC SMEMR* SMEMW* MEMR* MEMW* NC REFRESH* NC IOCHK* NC NC BCLK OSC NC TC XTAL0 XTAL1 NC SW9 SW8 SW7 SW6 SW5 NC NC NC 40 MHz CMOS OSCILLATOR } The TNT4882 is selected when the binary value on these pins matches that on ADDR9-5. Connecting them to ground causes the corresponding address lines to be compared to zero; leaving them unconnected causes those address lines to be compared to one. (Base I/O address 2C0 hex shown.) GPIB PC/XT Bus Connector NC NC NC RENN IFCN NDACN NRFDN DAVN EOIN ATNN SRQN DACKN DRQ INTR SENSE_8_16N Connect DACKN, DRQ, and INTR to one of the available lines on the AT bus. DIO8N DIO7N DIO6N DIO5N DIO4N DIO3N DIO2N DIO1N TNT4882 SD7-0 DATA7-0 SA9-0 ADDR9-0 AEN IOCHRDY RESET IOW* IOR* AEN_N IOCHRDY RESET IOWN IORN DACK*3-1 DRQ3-1 IRQ7-2 NC DACKN DRQ INTR SENSE_8_16N NC NC NC NC DATA15-8 D15_8_OEN D7_0_OEN MODE NC NC NC KEYRSTN KEYDQ KEYCLKN Connect DACKN, DRQ, and INTR to one of the available lines on the PC bus. DIO8N DIO7N DIO6N DIO5N DIO4N DIO3N DIO2N DIO1N RENN IFCN NDACN NRFDN DAVN EOIN ATNN SRQN XTAL0 XTAL1 NC SW9 SW8 SW7 SW6 SW5 NC NC NC 40 MHz CMOS OSCILLATOR } The TNT4882 is selected when the binary value on these pins matches that on ADDR9-5. Connecting them to ground causes the corresponding address lines to be compared to zero; leaving them unconnected causes those address lines to be compared to one. (Base I/O address 2C0 hex shown.) Figure 5. PC/XT and AT (ISA) Bus to ISA Mode TNT4882 National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com 7 TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC ISA Pin Configuration Byte Lane Table This table shows which byte lane accesses the TNT4882 internal registers during an I/O access when you use the ISA pin configuration. All combinations of ADDR4-1, SENSE_8_16N, and BHEN_N not shown in this table are illegal. You should not apply these combinations to the TNT4882 while the chip is selected. The accessed register is determined only by ADDR4-0, not SENSE_8_16N or BHEN_N. 8 SENSE_8_16N BHEN_N ADDR4-0 IORN IOWN 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 11000 11000 XXXX1 XXXX1 XXXX0 XXXX0 XXXX0 XXXX0 XXXX1 XXXX1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 DATA15-8 DATA7-0 FIFOA FIFOA Read Written Not Driven Ignored Not Driven Ignored Not Driven Ignored FIFOB FIFOB Not Driven Ignored Read Written Read Written Read Written National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC Hardware Interfacing – Generic Mode TNT4882 GPIB TNT4882-AQ (GENERIC) CPU (80186) DRQ0 DRQ ARDY RD RDY1 WR WRN INTR RRN INT0 RESET RESETN ABUSN BHE AD0 BBUSN DACKN Decode AD15-0 CSN DIO8N DIO7N DIO6N DIO5N DIO4N DIO3N DIO2N DIO1N RENN IFCN NDACN NRFDN DAVN EOIN ATNN SRQN 74573 ALE ADDR4-0 DATA15-8 74245 DEN DT/R DATA7-0 73245 NC CPUACC NC NC NC NC PAGED SWAPN BURST_RDN FIFO_RDY MODE XTAL0 XTAL1 NC KEYRSTN KEYDQ KEYCLKN NC NC NC TADCS LADCS NC NC REM TRIG DCAS NC NC NC ABUS_OEN BBUS_OEN NC NC 40 MHz CMOS OSCILLATOR Figure 6. Intel CPU to Generic Mode TNT4882 Generic Pin Configuration Byte Lane Table This table shows which byte lanes will access TNT4882 registers during I/O accesses. ABUSN BBUSN ADDR4-0 D15-8 D7-0 0 1 0 0 1 1 0 0 1 0 11000 11000 11000 XXXXX* XXXXX* FIFOB unused FIFOA used unused unused FIFOB FIFOB unused used *Any address except 11000 National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com 9 TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC Generic Mode DC Characteristics Parameter Supply voltage Voltage input low Voltage input high Voltage output low Voltage output high Supply current Output current low DATA15-0, LADCS, DRQ, INTR, RDY1 Output current low BBUS_OEN, ABUS_OEN, TADCS, CPUACC, REM, TRIG, DCAS, CIC FIFO_RDY Output current low KEYDQ, KEYRSTN, KEYCLKN DIO8-1N, IFCN, SRQN, EOIN, ATNN, RENN, DAVN, NRFDN, NDACN Output current high DATA15-0, LADCS, DRQ, INTR, RDY1 Output current high BBUS_OEN, ABUS_OEN, TADCS, CPUACC, REM, TRIG, DCAS FIFO_RDY Symbol VDD VIL VIH VOL VOH IDD IOL Output current high KEYDQ, KEYRSTN, KEYCLKN DIO8-1N, IFCN, SRQN, EOIN, ATNN, RENN, DAVN, NRFDN, NDACN Input leakage current – all pins Output leakage current – all pins IOH Min 4.75 -0.5 2.0 0.0 2.4 Max 5.25 0.8 VCC 0.4 VDD 90 24 Unit V V V V V mA mA Notes 50 mA, typical VOL = 0.4 V IOL 8 mA VOL = 0.4 V IOL IOL 4 2 mA mA VOL = 0.4 V VOL = 0.4 V IOL 48 mA VOL = 0.4 V IOH -12 -24 -4 mA mA mA VOH = VDD-0.5 V VOH = 2.4 V VOH = VDD-0.5 V mA mA IOH -8 -2 -4 -1 -2 16 mA mA mA VOH = 2.4 V VOH = VDD-0.5 V VOH = 2.4 V VOH = VDD-0.5 V VOH = 2.4 V VOH = 2.4 V IIH IOZ ±10 ±10 µA µA VDD = 5.5 V VDD = 5.5 V IOH IOH Generic Mode Capacitance Parameter Pin capacitance DIO8-1N, RENN, ATNN, IFCN, SRQN, DAVN, EOIN, NDACN, NRFDN Pin capacitance all other pins Symbol C Min Typ C Max 50 3.6 Unit pF Notes pF Generic Mode AC Characteristics Parameter Address setup to RDN = 0, WRN = 0 Data delay from RDN = 0, CSN = 0 (one-chip mode access) Data float from RDN = 1 RDN pulsewidth (I/0 access) RDN recovery width Address hold from RDN = 1, WRN = 1 DRQ unassertion Data delay from RDN = 0, DACKN = 0 Data setup to WRN = 1 Data hold from WRN = 1 CSN setup to RDN or WRN CSN hold from RDN or WRN DACKN setup to RDN or WRN DACKN hold from RDN or WRN RDN or WRN to CPUACC (two-chip mode NAT4882 access only) RDN or WRN to RDY1 assert Two-chip mode NAT4882 access Other accesses RDN or WRN to RDY1 unassert WRN pulse width (DMA access) RDN pulse width (DMA access) 10 Symbol t AS t RD t DF t RW t RR t AH t DU t DR t WS t WH t CS t CH t DS t DH t CPU t ARDY t URDY t WP t RP Min 24 Commercial Max Industrial Min 27 71 40 71 40 0 78 44 78 44 0 78 40 14 0 0 0 0 0 40 40 National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com Max 86 44 16 0 0 0 0 0 26 29 10 25 22 10 28 25 44 44 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns clock periods ns ns ns ns TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC Generic Mode AC Characteristics Waveforms ABUSN, BBUSN, ADDR4-0 t t AS AH CSN t t CS CH tRW RDN t t DF RD DATA t t ARDY URDY t tCPU RDY1 CPU CPUACC†† †† CPUACC asserts during two-chip mode NAT4882 accesses only Figure 7. CPU Read DRQ t DU DACKN t t t RP DS RDN DH t DF t DR DATA15-0 t RDYQ t RDY1 URDY Figure 8. DMA Read ABUSN, BBUSN, ADDR4-0 CSN tAS tAH tCS tCH tWP WRN tWS tWH DATA tARDY tURDY RDY1 tCPU tCPU CPUACC†† †† CPUACC asserts during two-chip mode NAT4882 accesses only Figure 9. CPU Write Waveforms continued on page 12 National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com 11 TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC Waveforms continued from page 11 DRQ tDU DACKN tDS tDH WRN tWH DATA15-0 tWS Figure 10. DMA Write ISA Mode DC Characteristics Parameter Supply voltage Voltage input low Voltage input high Voltage output low Voltage output high Supply current Output current low DATA15-0 DRQ, INTR, IOCS16, IOCHRDY Output current low D7_0_OEN Output current low D15_8_OEN, TP_INTWTN Output current low KEYDQ, KEYRSTN, KEYCLKN Output current low DIO8-1N, RENN, ATNN, IFCN, SRQN, DAVN, EOIN, NDACN, NRFDN Output current high DATA15-0 DRQ, INTR Output current high D7_0_OEN Output current high D15_8_OEN, TP_INTWTN Output current high KEYDQ, KEYRSTN, KEYCLKN Output current high DIO8-1N, RENN, ATNN, IFCN, SRQN, DAVN, EOIN, NDACN, NRFDN Input leakage current – all pins Output leakage current – all pins 12 Symbol Unit Notes 90 24 V V V V V mA mA 50 mA, typical VOL = 0.4 V IOL 16 mA VOL = 0.4 V IOL 8 mA VOL = 0.4 V IOL 2 mA VOL = 0.4 V IOL 48 mA VOL = 0.4 V IOH -12 mA VOH = VDD-0.5 V IOH -24 -8 mA mA VOH = 2.4 V VOH = VDD-0.5 V IOH -16 -4 mA mA VOH = 2.4 V VOH = VDD-0.5 V IOH -8 -1 mA mA VOH = 2.4 V VOH = VDD-0.5 V -2 mA VOH = 2.4 V IOH -16 mA VOH = 2.4 V IIH IOZ ±10 ±10 mA mA VDD = 5.5 V VDD = 5.5 V VDD VIL VIH VOL VOH IDD IOL Min 4.75 -0.5 2.0 0.0 2.4 Max 5.25 0.8 VCC 0.4 VDD National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC ISA Mode Capacitance Parameter Symbol Pin capacitance DATA15-0, DRQ, INTR, IOCS16N, IOCHRDY, ADDR6 Pin capacitance D7_0_OEN, D15_8_OEN, TP_INTWTN, KEYDQ, KEYRSTN, KEYCLKN, ADDR4, ADDR8, ADDR9 Pin capacitance BHEN_N, ADDR3-0, ADDR5, ADDR7, DACKN, AEN_N, MODE, TESTMODE, PWBSEL2-0, SW9, SENSE_8_16N, IORN, IOWN, RESET Pin capacitance DIO8-1N, RENN, ATNN, IFCN, SRQN, DAVN, EOIN, NDACN, NRFDN Min Typ Max Unit C 3.6 pF C 3.0 pF C 3.5 pF C 50 Notes pF ISA Mode AC Characteristics Parameter ADDR9-0 setup to IORN, IOWN Symbol tAS Min 30 Max Unit ns ADDR9-0 hold from IORN, IOWN tAH 0 DACKN setup to IORN, IOWN tDS 0 ns DACKN hold from IORN, IOWN tDH 20 ns Data setup time to IOWN rising tSU 22 ns Data hold time from IOWN rising tWH 0 ns IORN low pulse width tRPWL 100 ns Notes ns IORN high pulse width tRPWH 42 ns IOWN low pulse width tWPWL 100 ns IOWN high pulse width tWPWH 100 ns IORN or IOWN held from IOCHRDY tTD 20 ns DRQ unassertion time tDU 73 ns Due to FIFO full/empty DRQ unassertion time tDU 48 ns Due to byte count reached Data access time from IORN falling, DMA tDACC 80 ns Data access time from IORN falling, I/O tACC 80 ns Data hold time from IORN rising tRH Data float time from IORN rising tDF 30 ns IOCS16N assertion after valid address tDEC 30 ns IOCS16N negation after invalid address tDECN 20 ns IOCHRDY negation from IORN or IOWN tRDYN 40 ns IOCHRDY release after IORN or IOWN tRDY 350 ns 0 ns ISA Mode AC Characteristics Waveforms ADDR9-0, AEN_N tAS IORN tAH tRPWL tRPWH DATA15-0 tACC IOCS16N IOCHRDY tRH tDEC tDF tRDY tTD tRDYN Figure 11. I/O Read Access tDECN Waveforms continued on page 14 National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com 13 TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC Waveforms continued from page 13 ADDR9-0, AEN_N tAS IOWN tAH tWPWL tWPWH DATA15-0 tSU IOCS16N tWH tDEC tRDY tTD tDECN IOCHRDY tRDYN Figure 12. I/O Write Access DRQ t DU DACKN t t t DS IORN DH RPWL t RPWH DATA15-0 t t RH DACC t DF Figure 13. DMA Read Access DRQ t DACKN DU t IOWN DS t t DH WPWL t WPWH DATA15-0 t SU t Figure 14. DMA Write Access 14 National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com WH TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC Absolute Maximum Ratings Property Range Supply voltage, VDD Input voltage, VIN Output voltage, VOUT Units - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 - 55 to 150 Storage temperature, TSTG V V V ˚C 23.90 ±0.25 3.40 (MAX.) 20.00 ±0.10 18.85 PIN 80 2.80 ±0.25 PIN 51 PIN 81 0.23 ±0.13 PIN 50 0.65 14.00 ±0.10 12.35 17.90 ±0.25 PIN 1 INDEX +0.08 0.15 –0.02 0.22 (MIN) 0.38 (MAX) 0° –7° PIN 31 PIN 100 PIN 1 PIN 30 DETAIL A SEE DETAIL A FRONT VIEW 0.80 ±0.15 SIDE VIEW NOTES: 1. All dimensions are shown in millimeters. 2. Unless otherwise specified, all dimensions are nominal. 3. When converting from millimeters to inches, four significant digits to the right of the decimal point are necessary. Figure 16. Mechanical Data LAND PATTERN .075 1.90 PIN 1 .980 24.9 .0256 0.65 Note: 20 x 30 Lead Pattern .013 .330 .745 18.9 Figure 17. Recommended Land Pattern (not to scale) National Instruments Phone: (512) 794-0100 • Fax: (512) 683-9300 • [email protected] • www.natinst.com 15 TNT4882 Single-Chip IEEE 488.2 Talker/Listener ASIC Technical Support Seminars/Training National Instruments strives to provide you with quality technical assistance worldwide. We currently offer electronic technical support along with our technical support centers staffed by Applications Engineers. Access information from our Web site at www.natinst.com Our FTP site is dedicated to 24-hour support, with a collection of files and documents to answer your questions. Log on to our Internet host at ftp.natinst.com You can fax questions to our Applications Engineers anytime at (800) 328-2203 or (512) 683-5678. Or, you can call from 8:00 a.m. to 6:00 p.m. (central time) at (512) 795-8248. Internationally, contact your local office. National Instruments sponsors a wide variety of group activities, such as user group meetings at trade shows and at large industrial sites. Our users also receive our quarterly Instrumentation Newsletter with the latest information on new products, product updates, application tips, and current events. In addition, sign up for NI News, our electronic news service at www.natinst.com/news Free and fee-paid seminars are presented several times a year in cities around the world. Comprehensive, fee-paid training courses are available at National Instruments offices or at customer sites. Call for training schedules. Warranty Part Number Legend ™ All National Instruments data acquisition, computer-based instrument, VXIbus, and MXIbus products are covered by a oneyear warranty. GPIB hardware products are covered by a two-year warranty from the date of shipment. The warranty covers board failures, components, cables, connectors, and switches, but does not cover faults caused by misuse. The owner may return a failed assembly to National Instruments for repair during the warranty period. Extended warranties are available at an additional charge. Information furnished by National Instruments is believed to be accurate and reliable. National Instruments reserves the right to change product specifications without notice. For More Information Contact National Instruments for Application Notes such as: ”Using the TNT4882 in a MC68340 System“ ”Factors to Consider When Clocking the TNT4882 at Frequencies Less than 40 MHz“ ”Porting a 9914 GPIB Design to Use the TNT4882“ Ordering Information TNT4882-BQ TNT4882 Developer Kit..........................................776866-01 Includes 2 TNT4882 ASICs, PC AT evaluation board, ESP-488TL source code software, and documentation. TNT4882 Programmer Reference Manual..............320724-01 a TNT b 4882 c d B e Q a. Family name TNT = Single-chip, high-speed, GPIB Talker/Listener interface b. Device-number 4882 = IEEE 488.2 compatible c. Reserved d. Revision e. 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