TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com 2.5-V to 18-V High-Efficiency Adjustable Power-Limiting Hot-Swap Controller With Current Monitor and Overvoltage Protection Check for Samples: TPS24720 FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • 1 2.5-V to 18-V Operation Accurate Current Limiting for Startup Programmable FET SOA Protection Adjustable Current Sense Threshold Programmable Fault Timer Power-Good Output Fast Breaker for Short-Circuit Protection Analog Load-Current Monitor Output Programmable UV and OV Low-current Standby Mode FET Fault Detection Flag 3-mm × 3-mm, 16-Pin QFN package Server Backplanes Storage Area Networks (SAN) Telecommunications Mezzanine Cards Medical Systems Plug-In Modules Base Stations DESCRIPTION The TPS24720 is an easy-to-use, full-featured protection device for 2.5-V to 18-V power rails. This hot-swap controller drives an external N-channel MOSFET, while protecting source, load and external MOSFET against multiple potentially damaging events. During startup, load current and MOSFET power dissipation are limited to user-selected values. After startup, currents above the user-selected limit will be allowed to flow until programmed timeout – except in extreme overload events when load is immediately disconnected from source. Programmable power limiting ensures the external MOSFET operates inside its safe operating area (SOA) at all times. This allows use of smaller FETs while improving system reliability. Power good, Fault, FET Fault, and current monitor outputs are provided for system status monitoring and downstream load control. TYPICAL APPLICATION (12 V at 10 A) R4 3.01 kΩ OUT VCC FLTb EN PGb LATCH GND RPROG 53.6 kΩ PROG 2 TIMER 3 GND 4 ENSD PGb LATCH FLTb 15 14 13 Thermal Pad TIMER CT 56 nF RIMON 1.43 kΩ VUVLO = 10.83 V VOV = 14.02 V ILMT = 12 A tFAULT = 7.56 ms 8 IMON PROG 1 12 VCC 11 SENSE 10 GATE 9 FFLTb FFLTb OV ENSD EN OUT TPS24720 R6 3.01 kΩ 7 R2 2.94 kΩ R5 3.01 kΩ SET GATE 6 SENSE IMON SET 3V RGATE 10 Ω 16 RSET 51.1 Ω R7 R3 10 kΩ RGT Package (Top View) VOUT COUT 470 μF C1 0.1 μF R1 90.9 kΩ M1 CSD16403Q5 5 VIN PINOUT OV RSENSE 2 mΩ 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION (1) TA PACKAGE PART NUMBER (1) FUNCTION MARKING –40ºC to 85ºC QFN-16 TPS24720 Latched or retry 24720 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range, all voltages referred to GND (unless otherwise noted) VALUE EN, FFLTb Input voltage range Sink current Source current ESD rating Temperature (1) (1) (1) (1) (1) –0.3 to 30 , FLTb , GATE, OUT, PGb , SENSE, SET , VCC ENSD, OV –0.3 to 20 PROG (1) –0.3 to 0.3 [SET, SENSE] to VCC –0.3 to 0.3 IMON, LATCH, TIMER –0.3 to 5 FFLTb, FLTb, PGb 5 PROG UNIT V mA Internally limited IMON 5 Human-body model All pins except PGb mA 2 PGb 0.5 Charged-device model 0.5 Maximum junction, TJ Internally limited kV °C Do not apply voltage directly to these pins. THERMAL INFORMATION THERMAL METRIC (1) TPS24720 QFN (16) PINS UNIT θJA Junction-to-ambient thermal resistance 47.3 °C/W θJCtop Junction-to-case (top) thermal resistance 63.8 °C/W θJB Junction-to-board thermal resistance 20.9 °C/W ψJT Junction-to-top characterization parameter 1.6 °C/W ψJB Junction-to-board characterization parameter 21 °C/W θJCbot Junction-to-case (bottom) thermal resistance 5.1 °C/W (1) 2 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN ENSD, OV NOM MAX UNIT 0 16 2.5 18 EN, FFLTb, FLTb, PGb, OUT 0 18 Sink current FFLTb, FLTb, PGb 0 2 mA Source current IMON 0 1 mA Resistance PROG 4.99 500 kΩ TIMER 1 Input voltage range External capacitance SENSE, SET (1), VCC GATE (1) (2) nF (2) –40 Operating junction temperature range, TJ V 1 µF 125 °C Do not apply voltage directly to these pins. External capacitance tied to GATE should be in series with a resistor no less than 1 kΩ. ELECTRICAL CHARACTERISTICS –40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, VENSD = 3 V, RSET = 190 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages referenced to GND, unless otherwise noted. PARAMETER CONDITIONS MIN NOM MAX UNIT UVLO threshold, rising 2.2 2.32 2.45 V UVLO threshold, falling 2.1 2.22 2.35 V VCC UVLO hysteresis (1) 0.1 Enabled ― IOUT + IVCC + ISENSE Supply current 1 Disabled ― EN = 0 V, IOUT + IVCC + ISENSE V 1.4 0.45 Shutdown ― ENSD = 0 V, IOUT + IVCC + ISENSE mA mA 1.7 10 1.3 1.4 µA EN Threshold voltage, falling 1.2 Hysteresis (1) 50 V mV Input leakage current 0 V ≤ VEN ≤ 30 V –1 0 1 µA Turnoff time EN ↓ to VGATE < 1 V, CGATE = 33 nF 20 60 150 µs Deglitch time EN ↑ 8 14 18 µs Disable delay EN ↓ to GATE ↓, CGATE = 0, tpff50–90, See Figure 1 0.1 0.4 1 µs Threshold voltage Rising or falling edge 0.3 0.7 1.4 V Pullup current VENSD = 5 V 0.5 1.2 2 µA Disable delay ENSD to GATE, tpff50–90, See Figure 2 0.75 1 µs 1.35 1.45 ENSD OV Threshold voltage, rising 1.25 Hysteresis (1) 60 V mV Input leakage current 0 V ≤ VOV ≤ 30 V –1 0 1 µA Deglitch time OV rising 0.5 1.2 1.5 µs FLTb Output low voltage Sinking 2 mA Input leakage current VFLTb = 0 V, 30 V 0.11 0.25 V –1 0 1 µA 140 240 340 mV PGb Threshold Hysteresis (1) V(SENSE – OUT) rising, PGb going high (1) Measured V(SENSE – OUT) falling, PGb going low 70 mV These parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 3 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, VENSD = 3 V, RSET = 190 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages referenced to GND, unless otherwise noted. PARAMETER CONDITIONS Output low voltage Sinking 2 mA Input leakage current VPGb = 0 V, 30 V Delay (deglitch) time Rising or falling edge MIN NOM MAX UNIT 0.11 0.25 V –1 0 1 µA 2 3.4 6 ms mV FFLTb VIMON threshold Measured VIMON to GND Output low voltage Sinking 2 mA Input leakage current FFLTb = 0 V, 30 V Delay FFLTb falling 90 103 115 0.11 0.25 V –1 0 1 µA 60 115 140 ms PROG Bias voltage Sourcing 10 µA 0.65 0.678 0.7 V Input leakage current VPROG = 1.5 V –0.2 0 0.2 µA VTIMER = 0 V 8 10 12 µA VTIMER = 2 V 8 10 12 µA mA TIMER Sourcing current Sinking current 2 4.5 7 Upper threshold voltage VEN = 0 V, VTIMER = 2 V 1.3 1.35 1.4 V Lower threshold voltage 0.33 0.35 0.37 V Timer activation voltage Raise GATE until ITIMER sinking, measure V(GATE – VCC), VVCC = 12 V 5 5.9 7 V Bleed-down resistance VENSD = 0 V, VTIMER = 2 V 70 104 130 kΩ Current limit in regulation 660 675 690 mV 16 30 µA IMON Summing threshold OUT Input bias current VOUT = 12 V SET Measure SET to SENSE –1.5 0 1.5 mV Output voltage VOUT = 12 V 23.5 25.8 28 V Clamp voltage Inject 10 µA into GATE, measure V(GATE – VCC) 12 13.9 15.5 V Sourcing current VGATE = 12 V 20 30 40 µA Fast turnoff, VGATE = 14 V 0.5 1 1.4 A Input referred offset GATE Sinking current Sustained, VGATE = 4 V to 23 V 6 11 20 mA In inrush current limit, VGATE = 4 V to 23 V 20 30 40 µA Pulldown resistance Thermal shutdown or VENSD = 0 V 14 20 26 kΩ Turn on delay VVCC rising to GATE sourcing, tprr50-50, See Figure 3 100 250 µs SENSE 30 40 µA 22.5 25 27.5 mV VOUT = 7 V, RPROG = 50 kΩ 10 12.5 15 VOUT = 2 V, RPROG = 25 kΩ 10 12.5 15 52 60 68 mV 8 13.5 18 µs Input bias current VSENSE = 12 V, sinking current Current limit threshold VOUT = 12 V Power limit threshold Fast-trip threshold Fast-turnoff duration Fast-turnoff delay V(VCC – SENSE) = 80 mV, CGATE = 0 pF, tprf50–50, See Figure 4 200 mV ns LATCH Threshold, rising Pullup current 4 VLATCH = 0 V Submit Documentation Feedback 0.3 0.9 1.4 V 7 10 13 µA Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, VENSD = 3 V, RSET = 190 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages referenced to GND, unless otherwise noted. PARAMETER CONDITIONS MIN NOM MAX UNIT 130 140 °C 10 °C OTSD Threshold, rising Hysteresis (2) (2) These parameters are provided for reference only and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty. VGATE VGATE 90% 90% VENSD VEN 50% 50% 0 Time 0 Time t(pff50-90) t(pff50-90) T0493-01 T0492-01 Figure 1. tpff50–90 Timing Definition IGATE Figure 2. tpff50–90 Timing Definition VGATE 50% 50% VVCC VVCC – VSENSE 50% 50% 0 0 Time t(prr50-50) Time t(prf50-50) T0494-01 Figure 3. tprr50–50 Timing Definition T0495-01 Figure 4. tprf50–50 Timing Definition Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 5 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM M1 VIN RSENSE RSET SET SENSE 11 7 RGATE GATE OUT 10 8 60 mV Charge Pump – + DC VCC – Servo Amplifier Fast Comparator – IMON RIMON Gate Comparator S Q R Q + VCC 6V 11 mA 1-shot 6 Inrush Latch + 30 µA + 12 – 0~60 µA + A – 9 ö , 675 mV ÷ è B ø Main Opamp in Inrush FFLTb æ KpA Min ç + PROG RPROG OUT DC UVLO + 2.32 V 2.22 V OV 20 kΩ Becomes Comparator After Inrush Limit Complete – 2 EN B – 240 mV 170 mV – 15 PGb 2 ms + PG Comparator + 1 1.35 V 1.3 V – 1.35 V 1.29 V + 14 µs 5 10 µA 13 FLTb Fault Logic 1.2 μs + + TSD – 1.5 V 1.35 V 0.35 V POR 10 µA + ENSD 16 0.7 V Turn Off Main Circuit 4 + 10 μA GND 0.9 V 3 14 TIMER LATCH CT B0438-01 Figure 5. Block Diagram of the TPS24720 PIN FUNCTIONS NAME PIN I/O EN 1 I Active-high enable input. Logic input. Connects to resistor divider. ENSD 16 I Pull low to put device into low-current standby mode. Logic input. FFLTb 9 O Active-low, open-drain FET fault indicator. Indicates shorted MOSFET when output is off. FLTb 13 O Active-low, open-drain output indicates overload fault timer has turned MOSFET off. GATE 10 O Gate driver output for external MOSFET GND 4 – Ground IMON 6 O Analog load current limit program point. Connect RIMON to ground. 6 DESCRIPTION Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com PIN FUNCTIONS (continued) NAME PIN I/O DESCRIPTION LATCH 14 I Latch or retry mode select input. Latch when floating or connected to a logic-level voltage; retry when connected to GND. OUT 8 I Output voltage sensor for monitoring MOSFET power. OV 5 I Overvoltage comparator input. Connects to resistor divider. GATE is pulled low when OV exceeds the threshold. PGb 15 O Active-low, open-drain power-good indicator. Status is determined by the voltage across the MOSFET. PROG 2 I Power-limiting programming pin. A resistor from this pin to GND sets the maximum power dissipation for the FET. SENSE 11 I Current-sensing input for resistor shunt from VCC to SENSE. SET 7 I Current-limit programming set pin. A resistor is connected from this pin to VCC. TIMER 3 I/O VCC 12 I Thermal pad — — A capacitor connected from this pin to GND provides a fault timing function. Input-voltage sense and power supply Tied to GND DETAILED PIN DESCRIPTIONS The following description relies on the typical application diagram shown on the front page of this data sheet, as well as the functional block diagram in Figure 5. EN: Applying a voltage of 1.35 V or more to this pin enables the gate driver. The addition of an external resistor divider allows the EN pin to serve as an undervoltage monitor. Cycling EN low and then back high resets the TPS24720 that has latched off due to a fault condition. This pin should not be left floating. ENSD: When this pin is pulled low, it shuts off all internal circuitry and thus places the device in a low-current standby mode. While in standby, the PGb, FLTb, and FFLTb outputs assume high-impedance states. A 20-kΩ resistor pulls GATE to GND in standby. This is a much weaker pulldown than the 11 mA drawn while the part is disabled (e.g., by EN, UVLO, OV, or overload fault current). Applications requiring rapid turnoff should disable the device using the EN pin before pulling ENSD low. This pin is preferably pulled up to a positive voltage from 2 V to 18 V, if not otherwise connected. FFLTb: This active-low open-drain output pulls low if VVCC is higher than the UVLO rising threshold and the voltage on the IMON pin exceeds 103 mV when EN is disabled. The presence of this voltage indicates that current continues to flow through the external circuitry even though the external MOSFET has been turned off. This presumably indicates a shorted MOSFET. FFLTb assumes a high impedance if one of the following conditions occurs: • ENSD is pulled low. • Temperature on the die exceeds the OTSD shutdown threshold. • VVCC drops below the UVLO falling threshold. FFLTb also asserts if VVCC is higher than the UVLO rising threshold, GATE is disabled by OV, and the voltage on the IMON pin exceeds 103 mV. This pin can be left floating when not used. FLTb: This active-low open-drain output pulls low when the TPS24720 has remained in current limit long enough for the fault timer to expire. The behavior of the FLTb pin depends on the status of the LATCH pin. If the LATCH pin is held high or left floating, the TPS24720 operates in latch mode. If the LATCH pin is held low, the TPS24720 operates in retry mode. In latch mode, a fault timeout disables the external MOSFET and holds FLTb low. The latched mode of operation is reset by cycling EN, VCC, or ENSD. In retry mode, a fault timeout first disables the external MOSFET, next waits sixteen cycles of TIMER charging and discharging, and finally attempts a restart. This process repeats as long as the fault persists. In retry mode, the FLTb pin is pulled low whenever the external MOSFET is disabled by the fault timer. In a sustained fault, the FLTb waveform becomes a train of pulses. The FLTb pin does not assert if the external MOSFET is disabled by EN, ENSD, OV, overtemperature shutdown, or UVLO. This pin can be left floating when not used. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 7 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com GATE: This pin provides gate drive to the external MOSFET. A charge pump sources 30 µA to enhance the external MOSFET. A 13.9-V clamp between GATE and VCC limits the gate-to-source voltage, because VVCC is very close to VOUT in normal operation. During start-up, a transconductance amplifier regulates the gate voltage of M1 to provide inrush current limiting. The TIMER pin charges timer capacitor CT during the inrush. Inrush current limiting continues until the V(GATE – VCC) exceeds the Timer Activation Voltage (6 V for VVCC = 12 V). Then the TPS24720 enters into circuit-breaker mode. The Timer Activation Voltage is defined as a threshold voltage. When V(GATE-VCC) exceeds this threshold voltage, the inrush operation is finished and the TIMER stops sourcing current and begins sinking current. In the circuit-breaker mode, the current flowing in RSENSE is compared with the current-limit threshold derived from the MOSFET power-limit scheme (see PROG). If the current flowing in RSENSE exceeds the current limit threshold, then MOSFET M1 is turned off. The GATE pin is disabled by the following three mechanisms: 1. GATE is pulled down by an 11-mA current source when – The fault timer expires during an overload current fault (VIMON > 675 mV) – VEN is below its falling threshold – VVCC drops below the UVLO threshold – VOV is above its rising threshold 2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V(VCC – SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the external MOSFET remains off. 3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold or ENSD is pulled low. GATE remains low in latch mode and attempts a restart periodically in retry mode. If used, any capacitor connecting GATE and GND should not exceed 1 μF and it should be connected in series with a resistor of no less than 1 kΩ. No external resistor should be directly connected from GATE to GND or from GATE to OUT. GND: This pin is connected to system ground. IMON: A resistor connected from this pin to GND scales the current-limit and power-limit settings, as illustrated in Figure 5. The voltage present at this pin is proportional to the current flowing through sense resistor RSENSE. This voltage can be used as a means of monitoring current flow through the system. The value of RIMON can be calculated from Equation 3. This pin should not have a bypass capacitor or any other load except for RIMON. LATCH: This pin determines whether the TPS24720 operates in latch mode or retry mode. Applying a voltage of 2 V to 5 V to this pin or allowing it to float selects latch mode. Tying the pin to ground selects retry mode. In latch mode, an overload current fault disables the TPS24720 until EN, ENSD, or VCC is cycled. In retry mode, the TPS24720 automatically attempts a restart after every sixteen cycles of TIMER charging and discharging. In a sustained fault in retry mode, the external MOSFET conducts 3.93% of the time; i.e., the duty ratio is 0.0393. If the LATCH pin is allowed to float, then its open-circuit voltage is approximately 2.28 V. OUT: This pin allows the controller to measure the drain-to-source voltage across the external MOSFET M1. The power-good indicator (PGb) relies on this information, as does the power-limiting engine. The OUT pin should be protected from negative voltage transients by a clamping diode or sufficient capacitors. A Schottky diode of 3 A / 40 V in a SMC package is recommended as a clamping diode for high-power applications. The OUT pin should be bypassed to GND with a low-impedance ceramic capacitor in the range of 10 nF to 1 µF. OV: This pin is used to program the device overvoltage level. A voltage of more than 1.35 V on this pin turns off the external MOSFET. A resistor divider connected from VCC to this pin provides overvoltage protection for the downstream load. This pin should be tied to GND when not used. PGb: This active-low, open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PGb pulls low after the drain-to-source voltage of the FET has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. It goes open-drain when VDS exceeds 240 mV. PGb assumes high-impedance status after a 3.4-ms deglitch delay once VDS of M1 rises up, resulting from GATE being pulled to GND at any of the following conditions : • An overload current fault occurs (VIMON > 675 mV). • A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, i.e., the fast-trip shutdown threshold has been exceeded. • VEN is below its falling threshold. 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com • • • • VENSD is below its threshold. VVCC drops below the UVLO threshold. VOV is above its rising threshold. Die temperature exceeds the OTSD threshold. This pin can be left floating when not used. PROG: A resistor from this pin to GND sets the maximum power permitted in the external MOSFET M1 during inrush. Do not apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of 4.99 kΩ. To set the maximum power, use Equation 1, 3125 PLIM = RPROG ´ RSENSE (1) where PLIM is the allowed power limit of MOSFET M1. RSENSE is the load-current-monitoring resistor connected between the VCC pin and the SENSE pin. RPROG is the resistor connected from the PROG pin to GND. Both RPROG and RSENSE are in ohms and PLIM is in watts. PLIM is determined by the maximum allowed thermal stress of MOSFET M1, given by Equation 2, TJ(MAX) - TC(MAX) PLIM < RθJC(MAX) (2) where TJ(MAX) is the maximum desired transient junction temperature and TC(MAX) is the maximum case temperature prior to a start or restart. RӨJC(MAX) is the junction-to-case thermal impedance of the pass MOSFET M1 in units of °C/W. Both TJ(MAX) and TC(MAX) are in °C. SENSE: This pin connects to the negative terminal of RSENSE. It provides a means of sensing the voltage across this resistor, as well as a way to monitor the drain-to-source voltage across the external FET. The current limit ILIM is set by Equation 3. 0.675 V ´ RSET ILIM = RIMON ´ RSENSE (3) A fast-trip shutdown occurs when V(VCC – VSENSE) exceeds 60 mV. SET: A resistor RSET is connected from this pin to the positive terminal of RSENSE. This resistor scales the current limit and power limit settings. It coordinates with RIMON and RSENSE to determine the current limit value. The value of RSET can be calculated from Equation 3 (see SENSE). TIMER: A capacitor CT connected from the TIMER pin to GND determines the overload fault timing. TIMER sources 10 µA when an overload is present, and discharges CT at 10 µA otherwise. M1 is turned off when VTIMER reaches 1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period before the external MOSFET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure proper operation of the fault timer. The value of CT can be calculated from the desired fault time tFLT, using Equation 4. 10 μA CT = ´ tFLT 1.35 V (4) As is explained in the description of the LATCH pin, either latch mode or retry mode occurs if the load current exceeds the current limit threshold or the fast-trip shutdown threshold, depending on the status of the LATCH pin. While in latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically. In retry mode, the external MOSFET is disabled for sixteen cycles of TIMER charging and discharging. The TIMER pin is pulled to GND by a 2-mA current source at the end of the 16th cycle of charging and discharging. The external MOSFET is then re-enabled. The TIMER pin capacitor, CT, can also be discharged to GND during latch mode or retry mode in the following two ways: 1. A 2-mA current sinks TIMER whenever any of the following occurs: – VEN is below its falling threshold. – VVCC drops below the UVLO threshold. – VOV is above its rising threshold. 2. A 100-kΩ resistor is connected to TIMER and discharges CT at the moment when VENSD drops below its threshold. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 9 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com TIMER is not affected when the die temperature exceeds the OTSD threshold. VCC: This pin performs three functions. First, it provides biasing power to the integrated circuit. Second, it serves as an input to the power-on reset (POR) and undervoltage lockout (UVLO) functions. The VCC trace from the integrated circuit should connect directly to the positive terminal of RSENSE to minimize the voltage sensing error. Bypass capacitor C1, shown in the typical application diagram on the front page, should be connected to the positive terminal of RSENSE. A capacitance of at least 10 nF is recommended. 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS 1200 5 1000 T = 25°C Supply Current (µA) Supply Current (µA) T = 125°C 4 T = 125°C 800 T = –40°C T = 25°C 3 2 T = –40°C 600 1 400 0 4 2 6 8 10 12 14 Input Voltage, VVCC (V) 16 18 0 20 Figure 6. Supply Current vs Input Voltage at Normal Operation (EN = High) 0 4 2 6 8 10 12 14 Input Voltage, VVCC (V) 16 18 20 Figure 7. Supply Current vs Input Voltage at Shutdown (EN = 0 V) 32 26.5 28 Voltage ,V(VCC – SENSE) (mV) VVCC = 2.5 V 25.5 25 24.5 VVCC = 18 V 24 T = 125°C T = 25°C 20 16 T = –40°C 12 8 23.5 –50 –20 10 40 70 Temperature (°C) 100 4 130 Figure 8. Voltage Across RSENSE in Inrush Current Limiting vs Temperature 0 2 4 6 8 10 Voltage, V(SENSE – OUT) (V) 12 0.25 1.8 Gate Current at Current Limiting VVCC Voltage = 12 V 32 16 1.2 Gate Current (A) 1.4 8 0 T = 125°C –8 VVCC = 12 V 1.6 24 T = 25°C 14 Figure 9. Voltage Across RSENSE in Inrush Power Limiting vs VDS of Pass MOSFET 40 MOSFET Gate Current (µA) 24 0.2 T = –40°C T = 25°C 0.15 0.1 0.05 1 0.8 0 V(VCC – SENSE) T = 125°C 0.6 –0.05 0.4 –0.1 0.2 –0.15 –16 T = –40°C –24 0 –32 –0.2 –0.2 –10 –40 0 5 10 15 20 25 30 35 40 Voltage, V(VCC – SENSE) (mV) 45 50 0 10 20 30 40 –0.25 Time (µs) 55 Figure 10. MOSFET Gate Current vs Voltage Across RSENSE During Inrush Power Limiting Voltage, V(VCC – SENSE) (V) Voltage, V(VCC – SENSE) (V) VCC Voltage = 12 V VVCC = 12 V 26 Figure 11. Gate Current During Fast Trip, VVCC = VGATE = 12 V Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 11 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com 0.7 0.2 T = –40°C Gate Current (A) 0.6 0.15 T = 25°C 0.5 0.1 0.4 0.05 0.3 0 V(VCC – SENSE) T = 125°C 0.2 –0.05 0.1 –0.1 0 –0.15 –0.1 –0.2 VVCC = 3.3 V –0.2 –10 0 10 20 40 30 –0.25 Gate Voltage Referenced to GND, VGATE (V) 0.25 Voltage, V(VCC – SENSE) (V) TYPICAL CHARACTERISTICS (continued) 0.9 Time (µs) Figure 12. Gate Current During Fast Trip, VVCC = VGATE = 3.3 V T = –40°C 16 12 8 4 0 8 12 Input Voltage, VVCC (V) 16 20 VVCC = 12 V CT = 10 nF Fault-Timer Period (ms) TIMER Activation Voltage Threshold (V) 20 T = 25°C 6 T = –40°C 5 4 1.6 1.2 CT = 4.7 nF 0.8 CT = 1 nF 0.4 4 0 8 12 Input Voltage, VVCC (V) 16 0 –50 20 –20 10 40 70 Temperature (°C) 100 130 Figure 15. Fault-Timer vs Temperature With Various TIMER Capacitors 2 2.36 VVCC = 12 V VVCC = 12 V EN Upper Threshold 1.6 UVLO Threshold Voltage (V) EN and ENSD Threshold Voltage (V) T = 125°C 24 2 T = 125°C Figure 14. TIMER Activation Voltage Threshold vs Input Voltage at Various Temperatures 1.2 ENSD Threshold 0.8 0.4 0 –50 –20 –10 10 30 50 70 Temperature (°C) 90 110 130 Figure 16. EN and ENSD Threshold Voltage vs Temperature 12 T = 25°C 28 Figure 13. Gate Voltage With Zero Gate Current vs Input Voltage 7 3 32 UVLO Upper Threshold 2.32 2.28 UVLO Lower Threshold 2.24 2.20 –50 –20 10 40 70 Temperature (°C) 100 130 Figure 17. UVLO Threshold Voltage vs Temperature Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 64 PGb Rising Fast-Trip Threshold Voltage (mV) V(SENSE – OUT) Threshold Voltage (mV) 240 220 200 180 PGb Falling 160 140 –50 –20 10 40 70 Temperature (°C) 100 120 VVCC = 18 V VVCC = 2.5 V 100 80 VVCC = 12 V 60 –50 –20 10 40 70 Temperature (°C) 100 130 Figure 20. PGb Open-Drain Output Voltage in Low State 62 61.5 61 VVCC = 18 V 60.5 10 –20 40 70 Temperature (°C) 100 130 160 140 120 VVCC = 2.5 V VVCC = 18 V 100 80 VVCC = 12 V 60 –50 10 –20 40 70 Temperature (°C) 100 130 Figure 21. FLTb Open-Drain Output Voltage in Low State 160 0.7 VEN = 0 V 140 T = 125°C 0.6 Supply Current (µA) Low-State Open-Drain Output Voltage (mV) VVCC = 2.5 V 62.5 Figure 19. Fast-Trip Threshold Voltage vs Temperature Low-State Open-Drain Output Voltage (mV) Low-State Open-Drain Output Voltage (mV) Figure 18. Threshold Voltage of VDS vs Temperature, PGb Rising and Falling 140 VVCC = 12 V 63 60 –50 130 160 63.5 120 VVCC = 18 V VVCC = 2.5 V 100 80 T = 25°C 0.5 0.4 T = –40°C 0.3 VVCC = 12 V 60 –50 –20 10 40 70 Temperature (°C) 100 130 Figure 22. FFLTb Open-Drain Output Voltage in Low State 0.2 0 4 8 12 Input Voltage, VVCC (V) 16 20 Figure 23. Supply Current vs Input Voltage at Various Temperatures When EN Pulled Low Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 13 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 0.365 Timer Lower Threshold Voltage (V) Timer Upper Threshold Voltage (V) 1.344 1.342 VVCC = 18 V VVCC = 12 V 1.34 1.338 VVCC = 2.5 V 1.336 1.334 –50 –20 10 40 70 Temperature (°C) 100 Figure 24. Timer Upper Threshold Voltage vs Temperature at Various Input Voltages –20 10 40 70 Temperature (°C) 10.3 VVCC = 18 V Timer Sinking Current (µA) Timer Sourcing Current (µA) VVCC = 2.5 V 100 130 10.4 10.1 VVCC = 12 V 9.9 9.8 9.7 VVCC = 2.5 V 9.6 9.5 –50 0.36 Figure 25. Timer Lower Threshold Voltage vs Temperature at Various Input Voltages 10.2 10 VVCC = 12 V 0.357 –50 130 VVCC = 18 V 0.362 VVCC = 18 V VVCC = 12 V 10.2 10.1 10 VVCC = 2.5 V 9.9 9.8 –20 10 40 70 Temperature (°C) 100 130 9.7 –50 Figure 26. Timer Sourcing Current vs Temperature at Various Input Voltages –20 10 40 70 Temperature (°C) 100 130 Figure 27. Timer Sinking Current vs Temperature at Various Input Voltages OV, LATCH Threshold Voltage (V) 1.6 OV Upper Threshold 1.4 1.2 Latch Threshold 1 0.8 –50 –20 10 40 70 Temperature (°C) 100 130 Figure 28. OV and LATCH Threshold Voltage vs Temperature 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com SYSTEM OPERATION INTRODUCTION The TPS24720 provides all the features needed for a positive hot-swap controller. These features include: • Undervoltage lockout • Adjustable (system-level) enable • Turn-on inrush limiting • High-side gate drive for an external N-channel MOSFET • MOSFET protection by power limiting • Adjustable overload timeout, also called an electronic circuit breaker • Charge-complete indicator for downstream converter coordination • A choice of latch or automatic restart mode • A low-power disable mode accessed by holding ENSD low • MOSFET short detection • Load overvoltage protection The typical application diagram, shown on the front page of this datasheet, and oscilloscope plots, shown in Figure 29 through Figure 31 and Figure 33 through Figure 36, demonstrate many of the functions described previously. BOARD PLUG-IN Figure 29 and Figure 30 illustrate the inrush current that flows when a hot swap board under the control of the TPS24720 is plugged into a system bus. Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in. The TPS24720 is held inactive for a short period while internal voltages stabilize. In this short period, GATE, PROG, and TIMER are held low and PGb, FLTb, and FFLTb are held open-drain. When the voltage on the internal VCC rail exceeds approximately 1.5 V, the power-on reset (POR) circuit initializes the TPS24720 and a start-up cycle is ready to take place. GATE, PROG, TIMER, PGb, FLTb and FFTb are released after the internal voltages have stabilized and the external EN (enable) thresholds have been exceeded. The part begins sourcing current from the GATE pin to turn on MOSFET M1. The TPS24720 monitors both the drain-to-source voltage across MOSFET M1 and the drain current passing through it. Based on these measurements, the TPS24720 limits the drain current by controlling the gate voltage so that the power dissipation within the MOSFET does not exceed the power limit programmed by the user. The current increases as the voltage across the MOSFET decreases until finally the current reaches the current limit ILIM. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 15 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com Figure 29. Inrush Mode at Hot-Swap Circuit Insertion INRUSH OPERATION When the TPS24720 activates the MOSFET M1, a current flows into the downstream bulk storage capacitors. When this current exceeds the limit set by the power-limit engine, the gate of the MOSFET is regulated by a feedback loop to make the MOSFET current rise in a controlled manner. This not only limits the capacitor-charging inrush current but it also limits the power dissipation of the MOSFET to safe levels. A more complete explanation of the power-limiting scheme is given in the section entitled Action of the Constant Power Engine. At the instant when the current in RSENSE reaches the programmed limit, the TIMER pin begins to charge the timing capacitor CT with a current of approximately 10 µA. The TIMER pin continues to charge CT until V(GATE – VCC) reaches the timer activation voltage (6 V for VVCC = 12 V). The TIMER then begins to discharge CT with a current of approximately 10 µA. This indicates that the inrush mode is finished. If the TIMER exceeds its upper threshold of 1.35 V before V(GATE – VCC) reaches the timer activation voltage, the GATE pin is pulled to GND and the hot-swap circuit enters either latch mode or auto-retry mode, depending upon the status of the LATCH pin (see LATCH in Detailed Pin Descriptions). The power limit feature is disabled once the inrush operation is finished and the hotswap circuit becomes a circuit breaker. The TPS24720 will turn off the MOSFET M1 after a fault timer period once the load exceeds the current limit threshold. ACTION OF THE CONSTANT-POWER ENGINE Figure 30 illustrates the operation of the constant-power engine during start-up. The circuit used to generate the waveforms of Figure 30 was programmed to a power limit of 29.3 W by means of the resistor connected between PROG and GND. At the moment current begins to flow through the MOSFET, a voltage of 12 V appears across it (input voltage VVCC = 12 V), and the constant-power engine therefore allows a current of 2.44 A (equal to 29.3 W divided by 12 V) to flow. This current increases in inverse ratio as the drain-to-source voltage diminishes, so as to maintain a constant dissipation of 29.3 W. The constant-power engine adjusts the current by altering the reference signal fed to the current limit amplifier. The lower part of Figure 31 shows the measured power 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com dissipated within the MOSFET, labeled FET PWR, remaining substantially constant during this period of operation, which ends when the current through the MOSFET reaches the current limit ILIM. This behavior can be considered a form of foldback limiting, but unlike the standard linear form of foldback limiting, it allows the power device to operate near its maximum capability, thus reducing the start-up time and minimizing the size of the required MOSFET. I_IN: Input Current, 2 A/div GAT: Voltage on GATE Pin, 5 V/div V_DS: Drain-to-Source Voltage of M1, 5 V/div TIMER: Voltage on TIMER Pin, 500 mV/div FET_PWR: Power on M1 (product of V_DS and I_IN), 19 W/div Time: 10 ms/div C002 Figure 30. Computation of M1 Power Stress During Startup CIRCUIT BREAKER AND FAST TRIP The TPS24720 monitors load current by sensing the voltage across RSENSE. The TPS24720 incorporates two distinct thresholds: a current-limit threshold and a fast-trip threshold. The functions of circuit breaker and fast-trip turn off are shown in Figure 31 through Figure 34. Figure 31 shows the behavior of the TPS24720 when a fault in the output load causes the current passing through RSENSE to increase to a value above the current limit but less than the fast-trip threshold. When the current exceeds the current-limit threshold, a current of approximately 10 μA begins to charge timing capacitor CT. If the voltage on CT reaches 1.35 V, then the external MOSFET is turned off. The TPS24720 either latches off or commences a restart cycle, depending upon the state of the LATCH pin. In either event, fault pin FLTb pulls low to signal a fault condition. Overload between the current limit and the fast-trip threshold is permitted for this period. This shutdown scheme is sometimes called an electronic circuit breaker. The fast-trip threshold protects the system against a severe overload or a dead short circuit. When the voltage across the sense resistor RSENSE exceeds the 60-mV fast-trip threshold, the GATE pin immediately pulls the external MOSFET gate to ground with approximately 1 A of current. This extremely rapid shutdown may generate disruptive transients in the system, in which case a low-value resistor inserted between the GATE pin and the MOSFET gate can be used to moderate the turn off current. The fast-trip circuit holds the MOSFET off for only a few microseconds, after which the TPS24720 turns back on slowly, allowing the current-limit feedback loop to take over the gate control of M1. Then the hot-swap circuit goes into latch mode or auto-retry mode, depending on pre-determined conditions. Figure 33 and Figure 34 illustrate the behavior of the system when the current exceeds the fast-trip threshold. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 17 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com Figure 31. Circuit-Breaker Mode During Overload Condition ILIMIT M1 RSENSE RGATE RSET SET VCC 7 12 SENSE GATE 11 10 OUT 8 + 60 mV – Server Amplifier + – Fast Trip Comparator A1 60 μA + 675 mV IMON RIMON 6 PROG VCP – Current Limit Amp 2 RPROG A2 30 μA + B0439-01 Figure 32. Partial Diagram of the TPS24720 With Selected External Components 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com Figure 33. Current Limit During Output-Load Short-Circuit Condition (Overview) Figure 34. Current Limit During Output-Load Short-Circuit Condition (Onset) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 19 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com AUTOMATIC RESTART If LATCH is connected to GND, then the TPS24720 automatically initiates a restart after a fault has caused it to turn off the external MOSFET M1. Internal control circuits use CT to count 16 cycles before re-enabling M1 as shown in Figure 35. This sequence repeats if the fault persists. The timer has a 1 : 1 charge-to-discharge current ratio. For the very first cycle, the TIMER pin starts from 0 V and rises to the upper threshold of 1.35 V and subsequently falls to 0.35 V before restarting. For the following 16 cycles, 0.35 V is used as the lower threshold. This small duty cycle often reduces the average short-circuit power dissipation to levels associated with normal operation and eliminates special thermal considerations for surviving a prolonged output short. Figure 35. Auto-Restart Cycle Timing 20 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com Figure 36. Latch After Overload Fault Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 21 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com PGb, FLTb, AND TIMER OPERATIONS The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across M1. PGb is useful for preventing a downstream dc/dc converter from starting while its input capacitor COUT is still charging. PGb goes active-low about 3.4 ms after COUT is charged. This delay allows M1 to fully turn on and any transients in the power circuits to end before the converter starts up. This type of sequencing prevents the downstream converter from demanding full current before the power-limiting engine allows the MOSFET to conduct the full current set by the current limit ILIM. Failure to observe this precaution may prevent the system from starting. The pullup resistor shown on the PGb pin in the typical application diagram on the front page is illustrative only; the actual connection to the converter depends on the application. The PGb pin may indicate that inrush has ended before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its full operating voltage. Care should be taken to ensure that the MOSFET on-resistance is sufficiently small to ensure that the voltage drop across this transistor is less than the minimum power-good threshold of 140 mV. After the hot-swap circuit successfully starts up, the PGb pin can return to a high-impedance status whenever the drain-to-source voltage of MOSFET M1 exceeds its upper threshold of 340 mV, which presents the downstream converters a warning flag. This flag may occur as a result of overload fault, output short fault, input overvoltage, higher die temperature, or the GATE shutdown by UVLO, EN or ENSD. FLTb is an indicator that the allowed fault-timer period during which the load current can exceed the programmed current limit (but not the fast-trip threshold) expires. The fault timer starts when a current of approximately 10 μA begins to flow into the external capacitor, CT, and ends when the voltage of CT reaches TIMER upper threshold, i.e., 1.35 V. FLTb pulls low at the end of the fault timer. Otherwise, FLTb assumes a high-impedance state. The fault-timer state requires an external capacitor CT connected between the TIMER pin and GND pin. The duration of the fault timer is the charging time of CT from 0 V to its upper threshold of 1.35 V. The fault timer begins to count under any of the following three conditions: 1. In the inrush mode, TIMER begins to source current to the timer capacitor, CT, when MOSFET M1 is enabled. TIMER begins to sink current from the timer capacitor, CT when V(GATE – VCC) exceeds the timer activation voltage (see the Inrush Operation section). If V(GATE – VCC) does not reach the timer activation voltage before TIMER reaches 1.35 V, then the TPS24720 disables the external MOSFET M1. After the MOSFET turns off, the timer goes into either latch mode or retry mode, depending on the LATCH pin status. 2. In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode or retry mode, depending on the LATCH pin status. 3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, CT, when the load current exceeds the programmed current limits following a fast-trip shutdown of M1. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode or retry mode, depending on the LATCH pin status. If the fault current drops below the programmed current limit within the fault timer period, VTIMER decreases and the pass MOSFET remains enabled. The behaviors of TIMER are different in the latch mode and retry mode. If the timer capacitor reaches the upper threshold of 1.35 V, then: • In latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically until TPS24720 is disabled by UVLO, EN, ENSD, or OV, as shown in Figure 36. • In retry mode, TIMER charges and discharges CT between the lower threshold of 0.35 V and the upper threshold of 1.35 V for sixteen cycles before the TPS24720 attempts to re-start. The TIMER pin is pulled to GND at the end of the 16th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is removed or the TPS24720 is disabled by UVLO, EN, ENSD, or OV. OVERTEMPERATURE SHUTDOWN The TPS24720 includes a built-in overtemperature shutdown circuit designed to disable the gate driver if the die temperature exceeds approximately 140°C. An overtemperature condition also causes the FLTb, FFLTb and PGb pins to go to high-impedance states. Normal operation resumes once the die temperature has fallen approximately 10°C. 22 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com START-UP OF HOT-SWAP CIRCUIT BY VCC OR EN The connection and disconnection between a load and the input power bus are controlled by turning on and turning off the MOSFET, M1. The TPS24720 has two ways to turn on MOSFET M1: • Increasing VVCC above UVLO upper threshold while EN is already higher than its upper threshold sources current to the GATE pin. After an inrush period, the TPS24720 fully turns on MOSFET M1. • Increasing EN above its upper threshold while VVCC is already higher than the UVLO upper threshold sources current to the GATE pin. After an inrush period, the TPS24720 fully turns on MOSFET M1. The EN pin can be used to start up the TPS24720 at a selected input voltage VVCC. To isolate the load from the input power bus, the GATE pin sinks current and pulls the gate of MOSFET M1 low. The MOSFET can be disabled by any of the following conditions: UVLO, EN, ENSD, load current above the current-limit threshold, hard short at load, OV, or OTSD. Three separate mechanisms pull down the GATE pin: 1. GATE is pulled down by an 11-mA current source when any of the following occurs. – The fault timer expires during an overload current fault (VIMON > 675 mV). – VEN is below its falling threshold. – VVCC drops below the UVLO threshold. – VOV is above its rising threshold. 2. GATE is pulled down by a 1-A current source for 13.5 μs when a hard output short circuit occurs and V(VCC – SENSE) is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the external MOSFET remains off. 3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold or ENSD is pulled low. MINIMIZATION OF POWER DISSIPATION AT STANDY BY ENSD The ENSD pin enables the use of TPS24720 in applications requiring a low-power standby mode. When this pin is pulled below its threshold voltage, all the internal circuitry is switched off and the GATE pin is discharged to GND through a 20-kΩ resistor. Thus, the MOSFET is disabled and power consumption is kept to a minimum. The correct procedure to go into standby mode is first to shut down the TPS24720 by using the EN pin and then to pull the ENSD pin low. FAULT DETECTION OF MOSFET SHORT WITH FFLTb One of the salient features of the TPS24720 is the detection of short-circuited MOSFETs by the FFLTb pin. The FFLTb is pulled low to indicate a FET short if all the following conditions occur. • EN is below its threshold voltage. • VVCC is above the UVLO threshold. • VIMON > 103 mV. The fact that GATE is turned off but current is still flowing through RSENSE indicates a drain-to-source short. DESIGN EXAMPLE: POWER-LIMITED START-UP This design example assumes a 12-V system voltage with an operating tolerance of ±2 V. The rated load current is 10 A, corresponding to a dc load of 1.2 Ω. If the current exceeds 12 A, then the controller should shut down and then attempt to restart. Ambient temperatures may range from 20°C to 50°C. The load has a minimum input capacitance of 470 μF. Figure 37 shows a simplified system block diagram of the proposed application. This design procedure seeks to control the junction temperature of MOSFET M1 under both static and transient conditions by proper selection of package, cooling, rDS(on), current limit, fault timeout, and power limit. The design procedure further assumes that a unit running at full load and maximum ambient temperature experiences a brief input power interruption sufficient to discharge COUT, but short enough to keep M1 from cooling. A full COUT recharge then takes place. Adjust this procedure to fit the application and design criteria. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 23 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com PROTECTION RSENSE 0.1 μF LOAD M1 0.1 μF RSET RGATE Specifications (at Output): Peak Current Limit = 12 A Nominal Current = 10 A COUT 470 μF OUT GATE SENSE SET VCC 12-V Main Bus Supply RLOAD 1.2 W IMON GND TPS24720 RIMON TIMER CT B0440-01 Figure 37. Simplified Block Diagram of the System Constructed in the Design Example STEP 1. Choose RSENSE, RSET, and RIMON The recommended range of the current-limit threshold voltage, V(VCC – SENSE), extends from 10 mV to 42 mV. Values near the low threshold of 10 mV may be affected by system noise. Values near the upper threshold of 42 mV may be too close to the minimum fast-trip threshold voltage of 52 mV. Values near the middle of this range help minimize both concerns. To achieve high efficiency, the power dissipation in RSENSE must be kept to a minimum. A RSENSE of 2 mΩ develops a voltage of 24 mV at the specified peak current limit of 12 A, while dissipating only 200 mW at the rated 10-A current. This represents a 0.17% power loss. For best performance, a current of approximately 0.5 mA (referring to the RECOMMENDED OPERATING CONDITIONS table) should flow into the SET pin and out of the IMON pin when the TPS24720 is in current limit. The voltage across RSET nominally equals the voltage across RSENSE, or 24 mV. Dividing 24 mV by 0.5 mA gives a recommended value of RSET of 48 Ω. A 51.1-Ω, 1% resistor was chosen. Using Equation 3, the value of RIMON must equal 1437 Ω, or as near as practically possible. A 1.43-kΩ, 1% resistor was chosen. 0.675 V ´ RSET RIMON = , ILIM ´ RSENSE therefore, RIMON = 0.675 V ´ 51.1 W = 1437 W 12 A ´ 2 mW (5) STEP 2. Choose MOSFET M1 The next design step is to select M1. The TPS24720 is designed to use an N-channel MOSFET with a gate-to-source voltage rating of 20 V. Devices with lower gate-to-source voltage ratings can be used if a Zener diode is connected so as to limit the maximum gate-to-source voltage the transistor sees. The next factor to consider is the drain-to-source voltage rating, VDS(MAX), of the MOSFET. Although the MOSFET only sees 12 V dc, it may experience much higher transient voltages during extreme conditions, such as the abrupt shutoff that occurs during a fast trip. A TVS may be required to limit inductive transients under such conditions. A transistor with a VDS(MAX) rating of at least twice the nominal input power-supply voltage is recommended regardless of whether a TVS is used or not. 24 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com Next select the on-resistance of the transistor, rDS(on). The maximum on-resistance must not generate a voltage greater then the minimum power-good threshold voltage of 140 mV. Assuming a current limit of 12 A, a maximum rDS(on) of 11.67 mΩ is required. Also consider the effect of rDS(on) on the maximum operating temperature TJ(MAX) of the MOSFET. Equation 6 computes the value of rDS(on)(MAX) at a junction temperature of TJ(MAX). Most manufacturers list rDS(on)(MAX) at 25°C and provide a derating curve from which values at other temperatures can be derived. Compute the maximum allowable on-resistance, rDS(on)(MAX), using Equation 6. TJ(MAX) - TA(MAX) rDS(on)(MAX) = , IMAX2 ´ RqJA therefore, rDS(on)(MAX) = 150°C - 50°C (12 A )2 ´ 51°C / W = 13.6 mW (6) Taking these factors into consideration, the TI CSD16403Q5 was selected for this example. This transistor has a VGS(MAX) rating of 16 V, a VDS(MAX) rating of 25 V, and a maximum rDS(on) of 2.8 mΩ at room temperature. During normal circuit operation, the MOSFET can have up to 10 A flowing through it. The power dissipation of the MOSFET equates to 0.24 W and an 9.6°C rise in junction temperature. This is well within the data sheet limits for the MOSFET. The power dissipated during a fault (e.g., output short) is far larger than the steady-state power. The power handling capability of the MOSFET must be checked during fault conditions. STEP 3. Choose Power-Limit Value, PLIM, and RPROG MOSFET M1 dissipates large amounts of power during inrush. The power limit PLIM of the TPS24720 should be set to prevent the die temperature from exceeding a short-term maximum temperature, TJ(MAX)2. The short-term TJ(MAX)2 could be set as high as 150°C while still leaving ample margin to the usual manufacturer’s rating of 175°C. Equation 7 is an expression for calculating PLIM, ( PLIM TJ(MAX)2 - é IMAX2 ´ r DS(on) ´ RqCA ë £ 0.8 ´ RqJC ) +T ù A(MAX) û , therefore, PLIM 130°C - é êë £ 0.8 ´ ((12 A ) ´ 0.002 W ´ (51°C / W - 1.8°C / W )) + 50°Cúûù = 29.3 W 2 1.8°C / W (7) where RθJC is the junction-to-case thermal resistance of the MOSFET, rDS(on) is the its resistance at the maximum operating temperature, and the factor of 0.8 represents the tolerance of the constant-power engine. For an ambient temperature of 50°C, the calculated maximum PLIM is 29.3 W. From Equation 1, a 53.6-kΩ, 1% resistor is selected for RPROG (see Equation 8). 3125 RPROG = , PLIM ´ R SENSE therefore, RPROG = 3125 = 53.15 kW 29.3 W ´ 0.002 W (8) STEP 4. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT The maximum output voltage rise time, tON, set by timer capacitor CT must suffice to fully charge the load capacitance COUT without triggering the fault circuitry. Equation 9 defines tON for two possible inrush cases. Assuming that only the load capacitance draws current during startup, Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 25 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 COUT ´ PLIM 2 ´ ILIM2 t ON = + www.ti.com COUT ´ VVCC(MAX)2 2 ´ PLIM COUT ´ VVCC(MAX) ILIM if - COUT ´ VVCC(MAX) ILIM if PLIM < ILIM ´ VVCC(MAX) PLIM > ILIM ´ VVCC(MAX) therefore, t ON = 470 μF ´ 29.3 W 2 ´ (12 A ) 2 470 μF ´ (12 V ) 2 + 2 ´ 29.3 W - 470 μF ´ 12 V = 0.614 ms 12 A (9) The next step is to determine the minimum fault-timer period. In Equation 9, the output rise time is tON. This is the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer uses the difference between the input voltage and the gate voltage to determine if the TPS24720 is still in inrush limit. The fault timer continues to run until VGS rises 6 V (for VVCC = 12 V) above the input voltage. Some additional time must be added to the charge time to account for this additional gate voltage rise. The minimum fault time can be calculated using Equation 10, 6 V ´ CISS tFLT = t ON + , IGATE therefore, tFLT = 0.614 ms + 6 V ´ 2040 pF = 1.23 ms 20 μA (10) where CISS is the MOSFET input capacitance and IGATE is the minimum gate sourcing current of TPS24720, or 20 μA. Using the example parameters and the CSD16403Q5 data sheet in Equation 10 leads to a minimum fault time of 1.23 ms. This time is derived considering the tolerances of COUT, CISS, ILIM, PLIM, IGATE, and VVCC(MAX). The fault timer must be set to a value higher than 1.23 ms to avoid turning off during start-up, but lower than any maximum fault time limit determined by the device SOA curve. There is a maximum time limit set by the SOA curve of the MOSFET. Referring to Figure 38, which shows the CSD16403Q5 SOA curve at TJ = 25°C, the MOSFET can tolerate 12 A with 12 V across it for approximately 20 ms. If the junction temperature TJ is other than 25°C, then the pulse time should be scaled by a factor of (150°C – TJ) / (150°C – 25°C). Therefore, the fault timer should be set between 1.23 ms and 20 ms. For this example, we will select 7 ms to allow for variation of system parameters such as temperature, load, component tolerance, and input voltage. The timing capacitor is calculated in Equation 11 as 52 nF. Selecting the next-highest standard value, 56 nF, yields a 7.56-ms fault time. 10 μA CT = ´ tFLT , 1.35 V therefore, CT = 26 10 μA ´ 7 ms = 52 nF 1.35 V (11) Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com IDS – Drain-to-Source Current – A 1k 100 1ms 10 10ms 100ms Area Limited by RDS(on) 1 1s 0.1 Single Pulse RθJA = 94ºC/W (min Cu) 0.01 0.01 0.1 DC 1 10 VDS – Drain-to-Source Voltage – V 100 G009 Figure 38. CSD16403Q5 SOA Curve STEP 5. Calculate the Retry-Mode Duty Ratio In retry mode, the TPS24720 is on for one charging cycle and off for 16 charge/discharge cycles, as can be seen in Figure 35. The first CT charging cycle is from 0 V to 1.35 V, which gives 7.56 ms. The first CT discharging cycle is from 1.35 V to 0.35 V, which gives 5.6 ms. Therefore, the total time is 7.56 ms + 33 x 5.6 ms = 192.36 ms. As a result, the retry mode duty ratio is 7.56 ms/192.36 ms = 3.93%. STEP 6. Select R1, R2, and R3 for UV and OV Next, select the values of the OV and UV resistors, R1, R2, and R3, as shown in the typical application diagram on the front page. From the TPS24720 electrical specifications, VOVTHRESH = 1.35 V and VENTHRESH = 1.35 V. VOV is the overvoltage trip voltage, which in this case is 14 V. VUV is the undervoltage trip voltage, which for this example equals 10.8 V. R3 VENTHRESH = ´ VOV R1 + R2 + R3 (12) VUVTHRESH = R 2 + R3 ´ VUV R1 + R2 + R3 (13) Assume R3 is 1 kΩ and use Equation 12 to solve for (R2 + R3). Use Equation 13 and the (R2 + R3) from Equation 12 to solve for R2 and finally for R3. From Equation 12, (R2 + R3) = 9370.4 Ω. From Equation 13, R2 = 296 Ω and R1 = 9.074 kΩ. Scaling all three resistors by a factor of ten to use less supply current for these voltage references and using standard 1% resistor values gives R1 = 90.9 kΩ, R2 = 2.94 kΩ, and R3 = 10 kΩ. STEP 7. Choose RGATE, R4, R5, R6, and C1 In the typical application diagram on the front page, the gate resistor, RGATE, is intended to suppress high-frequency oscillations. A resistor of 10 Ω serves for most applications, but if M1 has a CISS below 200 pF, then 33 Ω is recommended. Applications with larger MOSFETs and very short wiring may not require RGATE. R4, R5, and R6 are required only if PGb, FLTb, and FFLTb are used; these resistors serve as pullups for the open-drain output drivers. The current sunk by each of these pins should not exceed 2 mA ( referring to the RECOMMENDATION OPERATING CONDITIONS table). C1 is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise while in the disabled state. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended. ALTERNATIVE DESIGN EXAMPLE: GATE CAPACITOR (dV/dt) CONTROL IN INRUSH MODE The TPS24720 can be used in applications that expect a constant inrush current. This current is controlled by a capacitor connected from the GATE terminal to GND. A resistor of 1 kΩ placed in series with this capacitor prevents it from slowing a fast-turnoff event. In this mode of operation, M1 operates as a source follower, and the slew rate of the output voltage approximately equals the slew rate of the gate voltage (see Figure 39). To implement a constant-inrush-current circuit, choose the time to charge, ∆t, using Equation 14, C ´ VVCC Dt = OUT ICHG Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 (14) 27 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com where COUT is the output capacitance, VVCC is the input voltage, and ICHG is the desired charge current. Set PLIM to a value greater than VVCC × ICHG to prevent power limiting from affecting the desired current. To select the gate capacitance use Equation 15. æ Dt ö CGATE = ç IGATE ´ ÷ - CISS VVCC ø è (15) M1 To Load From Source RGATE Part of TPS24720 CGATE GATE IGATE 30 μA 1 kΩ GND S0509-01 Figure 39. Gate Capacitor (dV/dt) Control Inrush Mode. ADDITIONAL DESIGN CONSIDERATIONS Use of PGb Use the PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time delay is needed to allow COUT to fully charge before the converter starts. An undesirable latch-up condition can be created between the TPS24720 output characteristic and the dc/dc converter input characteristic if the converter starts while COUT is still charging; using the PGb pin is one way to avoid this. Output Clamp Diode Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a current-limit event. The OUT pin ratings can be satisfied by connecting a diode from OUT to GND. The diode should be selected to control the negative voltage at the full short-circuit current. Schottky diodes are generally recommended for this application. Gate Clamp Diode The TPS24720 has a relatively well-regulated gate voltage of 12 V–15.5 V with a supply voltage VVCC higher than 4 V. A small clamp Zener from gate to source of M1 is recommended if VGS of M1 is rated below 12 V. A series resistance of several hundred ohms or a series silicon diode is recommended to prevent the output capacitance from discharging through the gate driver to ground. High-Gate-Capacitance Applications Gate voltage overstress and abnormally large fault-current spikes can be caused by large gate capacitance. An external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1 exceeds about 4000 pF. When gate capacitor dV/dt control is used, a 1-kΩ resistor in series with CGATE is recommended (see Figure 39). If the series R-C combination is used for MOSFETs with CISS less than 3000 pF, then a Zener is not necessary . 28 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com Bypass Capacitors It is a good practice to provide low-impedance ceramic capacitor bypassing of the VCC and OUT pins. Values in the range of 10 nF to 1 µF are recommended. Some system topologies are insensitive to the values of these capacitors; however, some are not and require minimization of the value of the bypass capacitor. Input capacitance on a plug-in board may cause a large inrush current as the capacitor charges through the low-impedance power bus when inserted. This stresses the connector contacts and causes a short voltage sag on the input bus. Small amounts of capacitance (e.g., 10 nF to 0.1 µF) are often tolerable in these systems. Output Short-Circuit Measurements Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads, circuit layout and component selection, output shorting method, relative location of the short, and instrumentation all contribute to variation in results. The actual short itself exhibits a certain degree of randomness as it microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do not expect to see waveforms exactly like those in the data sheet; every setup differs. Layout Considerations TPS24720 applications require careful attention to layout to ensure proper performance and to minimize susceptibility to transients and noise. In general, all traces should be as short as possible, but the following list deserves first consideration: • Decoupling capacitors on VCC pin should have minimal trace lengths to the pin and to GND. • Traces to SET and SENSE must be short and run side-by-side to maximize common-mode rejection. Kelvin connections should be used at the points of contact with RSENSE (see Figure 40). • SET runs must be short on both sides of RSET. • Power path connections should be as short as possible and sized to carry at least twice the full-load current, more if possible. • Connections to GND and IMON pins should be minimized after the previously described connections have been placed. • The device dissipates low power, so soldering the thermal pad to the board is not a requirement. However, doing so improves thermal performance and reduces susceptibility to noise. • Protection devices such as snubbers, TVS, capacitors, or diodes should be placed physically close to the device they are intended to protect, and routed with short traces to reduce inductance. For example, the protection Schottky diode shown in the typical application diagram on the front page of the data sheet should be physically close to the OUT pin. LOAD CURRENT PATH LOAD CURRENT PATH RSENSE SET RSET VCC SET SENSE RSET TPS24720 TPS24720 Method 1 Method 2 M0217-01 Figure 40. Recommended RSENSE Layout Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 29 TPS24720 SLVSAL1B – MARCH 2011 – REVISED MAY 2011 www.ti.com REVISION HISTORY Changes from Revision A (April 2011) to Revision B Page • Changed voltages in PGb pin description from 140 mV and 340 mV to 170 mV and 240 mV. ........................................... 8 • Changed RIMON equation ..................................................................................................................................................... 24 Changes from Revision Original (March 2011) to Revision A • 30 Page Corrected voltages shown in the block diagram ................................................................................................................... 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS24720 PACKAGE OPTION ADDENDUM www.ti.com 14-May-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) TBD Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) TPS24720RGT PREVIEW QFN RGT 16 Call TI TPS24720RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS24720RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS24720RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS24720RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS24720RGTR QFN RGT 16 3000 346.0 346.0 29.0 TPS24720RGTT QFN RGT 16 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps RF/IF and ZigBee® Solutions www.ti.com/lprf TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated