TPS2421-1 TPS2421-2 www.ti.com .................................................................................................................................................. SLUS907A – JANUARY 2009 – REVISED MARCH 2009 3-V to 20-V Integrated FET Hot Swap FEATURES 1 • • • • 2 • • • • • DESCRIPTION Integrated Pass MOSFET 3.3-V to 20-V Bus Operation Programmable Fault Current Current Limit Proportionally Larger than Fault Current Programmable Fault Timer Internal MOSFET Power Limiting Latch-Off on Fault (-1) and Retry (-2) Versions SO-8 PowerPad™ Package –40°C to 125°C Junction Temperature Range The TPS2421 provides highly integrated hot swap power management and superior protection in applications where the load is powered by voltages between 3.0 V and 20 V. These devices are very effective in systems where a voltage bus must be protected to prevent shorts from interrupting or damaging the unit. The TPS2421 is an easy to use devices in an 8-pin PowerPad™ SO-8 package. The TPS2421 has multiple programmable protection features. Load protection is accomplished by a non-current limiting fault threshold, a hard current limit, and a fault timer. The current dual thresholds allow the system to draw short high current pulses, while the fault timer is running, without causing a voltage droop at the load. An example of this is a disk drive startup. This technique is ideal for loads that experience brief high demand, but benefit from protection levels in-line with their average current draw. APPLICATIONS • • • • RAID Arrays Telecommunications Plug-In Circuit Boards Disk Drive Hotswap MOSFET protection is provided by power limit circuitry which protects the internal MOSFET against SOA related failures. The TPS2421 is available in latch-off on fault (-1) and retry on fault (-2). 3 V to 20 V IN VIN 2 EN FLT 1 (A) ISET CT PG 4 5 6 8 (A) COUT CCT (A) GND RSET CVIN OUT VOUT 7 Optional: To System Monitor 3 Figure 1. Typical Application NOTE: (A) Required only in systems with lead and/or load inductance. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPS2421-1 TPS2421-2 SLUS907A – JANUARY 2009 – REVISED MARCH 2009 .................................................................................................................................................. www.ti.com ORDERING INFORMATION (1) DEVICE JUNCTION TEMPERATURE TPS2421-1 –40°C to 125°C TPS2421-2 (1) PACKAGE ORDERING CODE MARKING DDA (SO8 PowerPad™) TPS2421-1DDA TPS2421-1 DDA (SO8 PowerPad™) TPS2421-2DDA TPS2421-2 VALUE UNIT Add an R suffix to the device type for tape and reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) VIN, VOUT Input voltage range –0.3 to 25 FLT, PG Voltage range –0.3 to 20 ISET, CT Voltage IMAX Maximum continuous output current 9 A FLT, PG Output sink current 10 mA EN Input voltage range –0.3 to 6 CT, (3) ISET (3) Voltage range ESD rating, CDM TJ Operating junction temperature range Tstg Storage temperature range (2) (3) V -0.3 to 3 ESD rating, HBM (1) V 1.75 2.5 kV 400 V Internally Limited °C –65 to 150 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. Do not apply voltage to these pins. DISSIPATION RATINGS (1) (1) (2) (3) (4) PACKAGE θJA LOW K, °C/W θJA HIGH K, °C/W θJA BEST (2), °C/W DDA 190 (3) 45 (4) 45 Tested per JEDEC JESD51, natural convection. The definitions of high-k and low-k are per JESD 51-7 and JESD 51-3. The best case thermal resistance is obtained using the recommendations per SLMA002A (2 signal – 2 plane with the pad connected to the plane). Low-k (2 signal – no plane, 3 in. by 3 in. board, 0.062 in. thick, 1 oz. copper) test board with the pad soldered, and an additional 0.12 in.2 of top-side copper added to the pad. High-k is a (2 signal – 2 plane) test board with the pad soldered. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VIN, VOUT Input voltage range 3 EN Voltage range 0 5 FLT, PG Voltage range 0 20 IOUT Continuous output current 0 6 A FLT, PG Output sink current 0 1 mA 100 10 pF/µF –40 125 °C CCT Junction temperature 2 Submit Documentation Feedback 20 V Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 TPS2421-1 TPS2421-2 www.ti.com .................................................................................................................................................. SLUS907A – JANUARY 2009 – REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS Unless otherwise noted: 3 V ≤ VIN ≤ 18 V, EN = 0 V, PG = FLT = open, ROUT = open, CLOAD = 0, RSET = 49.9 kΩ, –40°C ≤ TJ ≤ 125°C PARAMETER TEST CONDITIONS MIN TYP MAX 2.6 2.85 2.9 UNIT VIN UVLO VIN rising Hysteresis 150 V mV EN = 2.4V 25 100 µA EN = 0V 3.9 5 mA RON RVIN-VOUT, IVOUT < IRMAX or IVOUT < (ISET × 1.25), 1 A ≤ IVOUT ≤ 4.5 A 33 50 mΩ Power limit TPS242x VIN: 12 V, COUT = 1000 µF EN: 3 V → 0 V 5 7.5 Reverse diode voltage VOUT > VIN , EN = 5 V, IIN = –1 A 0.77 1.0 Bias current VIN, VOUT 3 V ISET IVOUT ↑, ICT: sinking → sourcing, pulsed test 0°C ≤ TJ ≤ 85°C ISET Fault current threshold -40°C ≤ TJ ≤ 125°C ILIM / IFLT ILIM Ratio ILIM / IFLT Current limit RRSET = 200 kΩ 0.80 1.2 RRSET = 100 kΩ 1.80 2.2 RRSET = 49.9 kΩ 3.60 4.40 RRSET = 200 kΩ 0.75 1.25 RRSET = 100 kΩ 1.75 2.25 RRSET = 49.9 kΩ 3.60 4.40 RRSET = 200 kΩ 1.1 1.8 2.6 RRSET = 100 kΩ 1.1 1.5 2.1 RRSET = 49.9 kΩ 1.1 1.4 1.6 RRSET = 200 kΩ 1.1 1.8 2.4 RRSET = 100 kΩ 2.3 3.0 3.7 RRSET = 49.9 kΩ 4.6 5.5 6.3 IVOUT rising, VVIN-VOUT = 0.3 V, pulsed test A – CT Charge/discharge current Threshold voltage ON/OFF fault duty cycle ICT sourcing, VCT = 1 V, In current limit 29 35 41 ICT sinking, VCT = 1 V, drive CT to 1 V, measure current 1.0 1.4 1.8 VCT rising 1.3 1.4 1.5 VCT falling, drive CT to 1 V, measure current 0.1 0.16 0.3 2.8% 3.7% 4.6% VVOUT = 0 V Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 µA V 3 TPS2421-1 TPS2421-2 SLUS907A – JANUARY 2009 – REVISED MARCH 2009 .................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted: 3 V ≤ VIN ≤ 18 V, EN = 0 V, PG = FLT = open, ROUT = open, CLOAD = 0, RSET = 49.9 kΩ, –40°C ≤ TJ ≤ 125°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN Threshold voltage Input bias current VEN falling 0.8 1.0 1.5 V Hysteresis 20 150 250 mV VEN = 2.4 V –2.0 0 0.5 VEN = 0.2 V –3.0 1 0.5 µA Turn on propagation delay VIN = 3.3 V, ILOAD = 1 A, VEN : 2.4 V → 0.2 V, VOUT: rising 90% × VIN 350 500 Turn off propagation delay VIN = 3.3 V, ILOAD = 1 A, VEN : 0.2 V → 2.4 V, VOUT: ↓ 10% × VIN 30 50 Low level output voltage VCT = 1.8 V, IFLT = 1 mA 0.2 0.4 V Leakage current VFLT = 18 V 1 µA µs FLT VOL PG PG threshold VOL V(VIN-VOUT) falling 0.4 0.5 0.75 Hysteresis 0.1 0.25 0.4 0.2 0.4 Low level output voltage IPG = 1 mA Leakage current VPG = 18 V 1 V µA Thermal Shutdown TSD Thermal shutdown Junction temperature rising Hysteresis 4 160 10 Submit Documentation Feedback °C Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 TPS2421-1 TPS2421-2 www.ti.com .................................................................................................................................................. SLUS907A – JANUARY 2009 – REVISED MARCH 2009 BLOCK DIAGRAM IOUT 7 VOUT VIN 3 V(DS) Detector + GND S 10 mA Q Pump Constant Power Engine 4 I(D) Detector 0.8R Fast Trip + + LCA 1.6 x ILIM R 1.0V + 0.2R + IOUT ______ 200 kW ISET 5 + PWRG FLT THERMAL SHUTDOWN CT Charge 1 34 mA 1.35 V CT 6 S Q R Q + FLT 1.25 mA 33 mA + LATCH -1 FACTORY SET 200 mV RETRY -2 1.5V EN PG + 2 VIN 8 VOUT PWRG + Internal Rail + VIN -500mV 2.7 / 2.6 PINOUT DIAGRAM TPS2421-x 1 FLT PG 8 2 EN VOUT 7 CT 6 ISET 5 3 VIN 4 GND Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 5 TPS2421-1 TPS2421-2 SLUS907A – JANUARY 2009 – REVISED MARCH 2009 .................................................................................................................................................. www.ti.com Table 1. TERMINAL FUNCTIONS FUNCTION PIN NO. DESCRIPTION FLT 1 Fault low indicated the fault time has expired and the FET is switched off EN 2 Device is enabled when this pin is pulled low VIN 3 Power In and control supply voltage GND 4 GND ISET 5 A resistor to ground sets the fault current, the current limit is 125% of the fault current. TPS2421 only CT 6 A capacitor to ground sets the fault time VOUT 7 Output to the load PG 8 Power Good low represents the output voltage is within 300 mV of the input voltage PIN DESCRIPTION CT: Connect a capacitor form CT to GND to set the fault time. The fault timer starts when the fault current threshold is exceeded, charging the capacitor with 36 µA from GND towards an upper threshold of 1.4 V. If the capacitor reaches the upper threshold, the internal pass MOSFET is turned off. The MOSFET will stay off until EN is cycled if a latching version is used. If an auto-retry version is used, the capacitor will discharge at 5 µA to 0.2 V and then re-enable the pass MOSFET. When the device is disabled, CT is pulled to GND through a 100-kΩ resistor. The timer period must be chosen long enough to allow the external load capacitance to charge. The fault timer period is selected using Equation 1 where TFAULT is the minimum timer period in seconds and CCT is in Farads. CCT = TFAULT 38.9 × 103 (1) This equation does not account for component tolerances. In autoretry versions, the second and subsequent retry timer periods will be approximately 85% as long as the first retry period. In autoretry versions, the fault timer discharges the capacitor for a nominal TSD in seconds with CCT in Farads per Equation 2. TSD = 1 . 0 ´ 10 6 ´ C CT (2) The nominal ratio of on to off times represents about a 3% duty cycle when a hard fault is present on the output of an autoretry version part. FLT: Open-drain output that pulls low on any condition that causes the output to open. These conditions are either an overload with a fault time-out, or a thermal shutdown. FLT becomes operational before UV, when VIN is greater than 1 V. GND: This is the most negative voltage in the circuit and is used as reference for all voltage measurements unless otherwise specified. ISET: A resistor from this pin to GND sets both the fault current (IFAULT) and current limit (IMAX) levels. The current limit is internally set at 125% of the fault current. The fault timer function on CT starts charging CT if IVIN exceeds the programmed fault current. If this current continues long enough for VCT to reach its upper trip threshold, the output is turned off. If IVIN falls below the fault current threshold before CT reaches its upper threshold, CT is discharged and normal operation continues. The internal MOSFET actively limits current if IVIN reaches the current limit set point. The fault timer operation is the same in this mode as described previously. The fault current value is programmed as follows; R IFLT = 6 200 k W I FAULT (3) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 TPS2421-1 TPS2421-2 www.ti.com .................................................................................................................................................. SLUS907A – JANUARY 2009 – REVISED MARCH 2009 EN: When this pin is pulled low, the device is enabled. The input threshold is hysteretic, allowing the user to program a startup delay with an external RC circuit. EN is pulled to VIN by a 10-MΩ resistor, pulled to GND by 16.8 MΩ and is clamped to ground by a 7-V Zener diode. Because high impedance pullup/down resistors are used to reduce current draw, any external FET controlling this pin should be low leakage. If EN is tied to GND at startup and VIN does not ramp quickly the TPS2421 may momentarily turn off then on during startup. This can happen if a capacitive load momentarily pulls down the input voltage below the UV threshold. If necessary, this can be avoided by delaying EN assertion until VIN is fully up. VIN: Input voltage to the TPS2421. The recommended operating voltage range is 3 V to 20 V. All VIN pins should be connected together and to the power source. VOUT: Output connection for the TPS2421. When switched on the output voltage will be approximately: VOUT = VIN - 0.04 ´ IOUT (4) All VOUT pins should be connected together and to the load. PG: Active low, Open Drain output, Power Good indicates that there is no fault condition and the output voltage is within 0.5 V of the input voltage. PG becomes operational before UV, whenever VIN is greater than 1 V. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 7 TPS2421-1 TPS2421-2 SLUS907A – JANUARY 2009 – REVISED MARCH 2009 .................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS FAULT TIMER THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FAULT CURRENT vs JUNCTION TEMPERATURE 1.50 RFLT = 100 kW 2.15 IFAULT – Fault Current – A VTHRESH – Fault Timer Threshold Voltage -– V 2.20 2.10 2.50 2.00 1.95 1.90 1.85 1.80 –50 0 TJ 50 – Junction 100 1.40 1.35 1.30 –50 150 Temperature – °C 0 TJ 50 – Junction 100 150 Temperature – °C Figure 2. Figure 3. POWER LIMIT vs JUNCTION TEMPERATURE SUPPLY CURRENT vs JUNCTION TEMPERATURE 8.0 7.5 1.45 24 ILOAD = 1 A Sleep Mode 7.0 ISUPPLY – Supply Current – mA PLIMIT – Power Limit Level – W 22 6.5 6.0 5.5 5.0 4.5 4.0 20 18 16 14 12 3.5 3.0 –50 0 TJ 50 – Junction 100 Temperature – °C 150 10 –50 0 TJ Figure 4. 8 50 – Junction 100 150 Temperature – °C Figure 5. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 TPS2421-1 TPS2421-2 www.ti.com .................................................................................................................................................. SLUS907A – JANUARY 2009 – REVISED MARCH 2009 TYPICAL CHARACTERISTICS (continued) PG PG EN VCT 12 V Startup into 15 W, 700 mF Load RSET = 49.9 kW ILOAD Temp capacitive overload, power limit tripped 12-V load at 1.5 A, then 140 mF added to load ILOAD RSET = 49.9 kW VOUT VOUT Figure 6. 12-V Startup Into 15 Ω, 700 µF Load Figure 7. 12-V, 140 µF Added to 8 Ω Load PG VIN 12-V failed startup in 4 W, 0 mF load VCT EN ILOAD FLT Soft overload, power limit not tripped, 12-V load stepped from 3 A to 4.2 A, CLOAD = 700 mF, R SET = 49.9 kW VOUT VOUT Figure 8. 12-V Faulted Startup Into 4 Ω Load Figure 9. 12-V Soft Overload, 3 A to 4.2 A, Power Limit Not Tripped Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 9 TPS2421-1 TPS2421-2 SLUS907A – JANUARY 2009 – REVISED MARCH 2009 .................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) PG PG VCT VCT ILOAD ILOAD Overload, power limit tripped, 12-V load stepped from 3 A to 5.4 A, CLOAD = 700 mF, R SET = 49.9 kW 12-V load at 3.6 A, then short applied to output, RSET = 49.9 kW VOUT VOUT Figure 10. 12-V Firm Overload, 3 A to 5.4 A, Power Limit Tripped Figure 11. 12-V Hard Overload, 3.6-A LoaD Then Short 12-V PLIM during startup into 60 W, 800 mF RSET = 49.9 kW 12-V PLIM during startup into overload, CT = 0.1 mF RFLT =ILOAD 100 k RSET = 49.9 kW P dissipation internal FET VOUT CT VOUT P dissipation internal FET ILOAD Figure 12. Power Dissipation During 12-V Startup into 60 Ω, 800 µF 10 Figure 13. Power Dissipation During 12-V Startup into 15 Ω, 140 µF Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 TPS2421-1 TPS2421-2 www.ti.com .................................................................................................................................................. SLUS907A – JANUARY 2009 – REVISED MARCH 2009 TYPICAL CHARACTERISTICS (continued) PG PG VCT EN 3 V startup into 3.2 A load RSET = 49.9 kW ILOAD 3.3 V overload step from 3.8 A to 5.5 A, RSET = 49.9 kW ILOAD VOUT VOUT Figure 14. 3-V Startup into 1-Ω Load PG Figure 15. 3-V Firm Overload, Load Stepped From 3.8 A to 5.5 A FLT VCT VCT ILOAD ILOAD 3.3 V overload shorted while under 3.5 A load, RSET = 49.9 kW 3.3 V overload step from 3.8 A to 7.1 A, RSET = 49.9 kW VOUT VOUT Figure 16. 3-V Hard Overload, Load Stepped From 3.8 A to 7.1 A Figure 17. 3-V Output Shorted While Under 3.5-A Load Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 11 TPS2421-1 TPS2421-2 SLUS907A – JANUARY 2009 – REVISED MARCH 2009 .................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) PG 3.3 V attempting startup into 1 W, 2200 mF load, retry mode - CT = 0.1 mF EN RSET = 49.9 kW VCT VCT ILOAD ILOAD 3.3 V, 1600 mF added while under 3.5 A load, RSET = 49.9 kW VOUT VOUT Figure 18. 3 V, 1600 µF Added To 3.5-A Load Figure 19. 3-V Retry Startup into 1 Ω, 2200-µF Load Figure 20. Startup Into a Short Circuit Output 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 TPS2421-1 TPS2421-2 www.ti.com .................................................................................................................................................. SLUS907A – JANUARY 2009 – REVISED MARCH 2009 APPLICATION INFORMATION Maximum Load at Startup The power limiting function of the TPS2421 provides very effective protection for the internal FET. Expectedly, there is a supply voltage dependent maximum load which the device will be able to power up. Loads above this level may cause the device to shut off current before startup is complete. Neglecting any load capacitance, the maximum load ( minimum load resistance ) is calculated using the equation; V 2 RMIN = IN 12 (5) Adding load capacitance may reduce the maximum load which can be present at start up. If EN is tied to GND at startup and VIN does not ramp quickly the TPS2421 may momentarily turn off then on during startup. This can happen if a capacitive load momentarily pulls down the input voltage below the UV threshold. If necessary, this can be avoided by delaying EN assertion until VIN is fully up. Transient Protection The need for transient protection in conjunction with hot-swap controllers should always be considered. When the TPS2421 interrupts current flow, input inductance generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the output. Such transients can easily exceed twice the supply voltage if steps are not taken to address the issue. Typical methods for addressing transients include; • Minimizing lead length/inductance into and out of the device • Voltage Suppressors (TVS) on the input to absorb inductive spikes • Shottky diode across the output to absorb negative spikes • A combination of ceramic and electrolytic capacitors on the input and output to absorb energy • Use PCB GND planes The following equation estimates the magnitude of these voltage spikes: VSPIKE(absolute ) = VNOM + ILOAD ´ L C (6) where • • • • VNOM is the nominal supply voltage ILOAD is the load current C is the capacitance present at the input or output of the TPS2421 L equals the effective inductance seen looking into the source or the load Calculating the inductance due to a straight length of wire is shown in Equation 7. æ 4´L ö - 0.75 ÷ (nH) Lstraightwire » 0.2 ´ L ´ ln ç è D ø (7) where • • L is the length of the wire D is diameter of the wire Some applications may require the addition of a TVS to prevent transients from exceeding the absolute ratings if sufficient capacitance cannot be included. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 13 TPS2421-1 TPS2421-2 SLUS907A – JANUARY 2009 – REVISED MARCH 2009 .................................................................................................................................................. www.ti.com Operation When load current exceeds the user programmed fault limit (ISET) during normal operation the fault timer starts. If load current drops below the ISET threshold before the fault timer expires, normal operation continues. If load current stays above the ISET threshold the fault timer expires and a fault is declared. When a fault is declared a device operating in latch mode turns off and can be restarted by cycling power or toggling the EN signal. A device operating in retry mode attempts to turn on at a 3% duty cycle until the fault is cleared. When the IMAX limit is reached during a fault the device goes into current limit and the fault timer keeps running. IMAX is automatically set to 1.25 times ISET. Startup When power is first applied to a load with discharged capacitors there is a large inrush current. The inrush is controlled by the TPS2421 by initially entering the power limit mode and turning on the fault timer. See Figure 13. As the charge builds on the capacitor, the current increases to IMAX. When the capacitor is fully charged, current output is set by the dc load value, The fault timer is turned off. The FET is then fully enhanced and the power good signal is true. In order to start properly, the fault timer must be set to exceed the capacitor charge time. When the load has a resistive component as well as capacitive, the fault time needs to be increased because current to the resistive load is unavailable to charge the capacitor. The startup time for some selected loading is given in Table 2. Table 2 data was taken with ISET equal to 4 A. Lower current settings of TPS2421 do not have a great influence on the start up timer because of operation at power limit. Load capacitance and dc resistance was selected for a measured start time. The start time is measured from the assertion of the EN pin to the assertion of the PG pin. Table 2. Start Time for Input Voltage and Output Loading (1) INPUT VOLTAGE (V) LOAD CAPACITANCE (µF) 220 5 1000 220 12 1000 (1) DC LOAD RESISTANCE (Ω) START TIME (ms) OPEN 2.5 5 2.7 12 2.6 OPEN 4 5 4 12 4 OPEN 4.4 5 No start 12 7 OPEN 14 5 No start 12 23 ISET = 4 A Some combinations of loading and current limit settings exceed the 5-W power limit of the internal MOSFET. The output voltage will not turn on regardless of the fault time setting. One way to work with the physical limits that create this problem is to allow the power manager to charge only the capacitive component of the load and use the PG signal to turn on the resistive component. This is common usage in dc-to-dc converters and other electrical equipment with power good inputs. 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 TPS2421-1 TPS2421-2 www.ti.com .................................................................................................................................................. SLUS907A – JANUARY 2009 – REVISED MARCH 2009 Start Up Into a Short The controller attempts to power on into a short for the duration of the timer. Figure 20 shows a small current resulting from power limiting the internal MOSFET. This happens only once for the latch off part, TPS2421-1. For the retry part, TPS2421-2, Figure 19 shows this cycle repeating at an interval based on the CT time. Shutdown Modes Hard Overload - Fast Trip When a hard overload causes the load current to exceed ~1.6 × ISET the TPS2421 immediately shuts off current to the load without waiting for the fault timer to expire. After such a shutoff the TPS2421 enters into startup mode and attempts to apply power to the load. If the hard overload is caused by a current transient, then a normal startup can be expected with a low probability of disruption to the load, assuming there is sufficient load capacitance to hold up the load during the fractions of a millisecond that make up the fast trip/restart cycle. If the hard overload is caused by a real, continuous failure then the TPS2421 goes into current limit during the attempt at restart. The timer starts and eventually runs out, shutting off current to the load. See the fast trip Figure 17. When the hard overload occurs the current is turned off, the PG pin becomes false, and the FLT pin stays false. The FLT pin becomes true only when the fault timer times out. Overcurrent Shutdown Overcurrent shutdown occurs when the output current exceeds ISET for the duration of the fault timer. Figure 9 shows a step rise in output current which exceeds the IFLT threshold but not the IMAX threshold. The increased current is on for the duration of the timer. At conclusion of the timer, the output is turned off. Layout Support Components Locate all TPS2421 support components, RSET, CT, etc. or any input or output voltage clamps, close to their connection pin. Connect the other end of the component to the inner layer GND without trace length. PowerPad™ When properly mounted the PowerPad package provides significantly greater cooling ability than an ordinary package. To operate at rated power the Power Pad must be soldered directly to the PC board GND plane directly under the device. The PowerPad is at GND potential and can be connected using multiple vias to inner layer GND. Other planes, such as the bottom side of the circuit board can be used to increase heat sinking in higher current applications. Refer to Technical Briefs: PowerPAD™ Thermally Enhanced Package (TI Literature Number SLMA002) and PowerPAD™ Made Easy (TI Literature Number SLMA004) for more information on using this PowerPadTM package.These documents are available at www.ti.com (Search by Keyword). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 15 TPS2421-1 TPS2421-2 SLUS907A – JANUARY 2009 – REVISED MARCH 2009 .................................................................................................................................................. www.ti.com Design Example This TPS2421 Design supports 12 V to operate a hot plugged disk drive. The 12 V specification for a disk drive is approximately 1-A operating current and 2-A typical spin-up. Selecting a 2.5 A setting for ISET would allow some margin for the operating current and satisfy the start current requirements. Calculate RIFLT using equation Equation 8 or select it using Table 3. RIFLT = 200kW 200,000 ´ = 80 (kW ) IFAULT 2.5 (8) Because ISET satisfies the spin up current, the timer can be set for the additional loading of charging the capacitor. Estimate approximately 20 ms. Use either Equation 9 or Table 3 to estimate the capacitance. C CT = tFAULT 38.9 ´ 10 3 = 20 ´ 10 - 3 38.9 ´ 10 3 = 0.514 ´ 10 - 6 (9) To alter parameters IIAX, IFAULT, IIMON or CCT use the formulas in the Pin Description section or use Table 3 . R2 10 kW R1 10 kW TPS2421 PG 8 EN VOUT 7 3 VIN CT 6 4 GND ISET 5 1 FLT 2 12VOUT 12VIN 15 V D1 SMAJ15A D2 MBR130LSFT1 C1 0.1 mF PwPd 9 CT 560 nF RISET 80.6 kW GND GND 1 Figure 21. 12-V, 2.5-A Steady State Current, 3.125-A Max Currrent NOTE: D1, D2, and C1 are required only in systems with significant feed and/or load inductance. Table 3. Pin Parameters 16 ISET (A) RISET (kΩ) CCT (µF) tFAULT (ms) tSD (ms) 1 200 0.022 0.86 0.22 ILOAD(max) (A) 1 1.5 133 0.047 1.83 0.47 1.5 2 100 0.1 3.89 1 2 2.5 80.6 0.22 8.56 2.2 2.5 3 65.5 0.47 18.28 4.7 3 3.5 56.2 0.68 26.45 6.8 3.5 4 49.9 1 38.9 10 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TPS2421-1 TPS2421-2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2421-1DDAR SO Power PAD DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2421-2DDAR SO Power PAD DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2421-1DDAR SO PowerPAD DDA 8 2500 358.0 335.0 35.0 TPS2421-2DDAR SO PowerPAD DDA 8 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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