TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 4.5-V TO 18-V INPUT 10-PIN SYNCHRONOUS BUCK CONTROLLER WITH POWER GOOD FEATURES CONTENTS 1 • • • • • • • • • • • • Input Operating Voltage Range: 4.5 V to 18 V Up to 20-A Output Currents Supports Pre-Biased Outputs 0.5% 0.591-V Reference 600 kHz (TPS40192) and 300 kHz (TPS40193) Switching Frequencies Three Selectable Thermally Compensated Short Circuit Protection Levels Hiccup Restart from Faults Internal 5-V Regulator High and Low side FET RDSON Current Sensing 10-Pin 3 mm × 3 mm SON Package Internal 4-ms Soft-Start Time Thermal Shutdown Protection at 145°C 3 Electrical Characteristics 4 Typical Characteristics 6 Terminal Information 9 Application Information 11 Design Example 17 Additional References 27 DESCRIPTION TPS40192 and TPS40193 are cost-optimized synchronous buck controllers that operate from 4.5 V to 18 V input. These controllers implement a voltage-mode control architecture with the switching frequency fixed at either 600 kHz (TPS40192) or 300 kHz (TPS40193). The higher switching frequency facilitates the use of smaller inductor and output capacitors, thereby providing a compact power-supply solution. An adaptive anti-cross conduction scheme is used to prevent shoot through current in the power FETs. APPLICATIONS • • • • Device Ratings Cable Modem CPE Digital Set Top Box Graphics/Audio Cards Entry Level and Mid-Range Servers SIMPLIFIED APPLICATION DIAGRAM VIN VOUT TPS40192/3 ON/OFF External Logic Supply 5V or Less, or BP5 1 ENABLE 2 FB 3 HDRV 10 SW 9 COMP BOOT 8 4 VDD LDRV 7 5 PGD BP5 6 VOUT GND 11 UDG−06063 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 DESCRIPTION (continued) Short circuit detection is done by sensing the voltage drop across the low-side MOSFET when it is on and comparing it with a user selected threshold of 100 mV, 200 mV or 280 mV. The threshold is set with a single external resistor connected from COMP to GND. This resistor is sensed at startup and the selected threshold is latched. Pulse by pulse limiting (to prevent current runaway) is provided by sensing the voltage across the high-side MOSFET when it is on and terminating the cycle when the voltage drop rises above a fixed threshold of 550 mV. When the controller senses an output short circuit, both MOSFETs are turned off and a timeout period is observed before attempting to restart. This provides limited power dissipation in the event of a sustained fault. ORDERING INFORMATION TJ PACKAGE FREQUENCY (kHz) TAPE AND REEL QUANTITY PART NUMBER 250 TPS40193DRCT 3000 TPS40193DRCR 300 -40°C to 85°C Plastic 10-Pin SON (DRC) 600 2 Submit Documentation Feedback 250 TPS40192DRCT 3000 TPS40192DRCR Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 DEVICE RATINGS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPS40192/TPS40193 VDD, ENABLE SW Input voltage range –5 to 25 BOOT, HDRV –0.3 to 30 BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW) -0.3 to 6 COMP, FB, BP5, LDRV, PGD –0.3 to 6 TJ Operating junction temperature range –40 to 150 Tstg Storage temperature –55 to 150 (1) UNIT –0.3 to 20 V °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VVDD Input voltage 4.5 18 V TJ Operating Junction temperature -40 125 °C PACKAGE DISSIPATION RATINGS PACKAGE DRC (1) AIRFLOW (LFM) RθJA High-K Board (1) (°C/W) Power Rating (W) TA = 25°C Power Rating (W) TA = 85°C 0 (Natural Convection) 47.9 2.08 0.835 200 40.5 2.46 0.987 400 38.2 2.61 1.04 Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI Technical Brief SZZA017. ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN TYP Human Body Model (HBM) 2500 Charged Device Model (CDM) 1500 MAX Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 UNIT V 3 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS TJ = –40°C to 85°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0°C ≤ TJ ≤ 85°C 588 591 594 -40°C ≤ TJ ≤ 85°C 585 591 594 UNIT REFERENCE VFB Feedback voltage range mV INPUT SUPPLY VVDD Input voltage range IVDD Operating current 4.5 18.0 V VENABLE = 3 V 2.5 4.0 mA VENABLE = 0.6 V 45 70 μA ON BOARD REGULATOR V5VBP Output voltage VVDD > 6 V, I5VBP ≤ 10 mA VDO Regulator dropout voltage VVDD - VBP5 , VVDD = 5 V, IBP5 ≤ 25 mA ISC Regulator current limit threshold IBP5 Average current 5.1 5.3 5.5 V 350 550 mV 50 50 mA OSCILLATOR fSW Switching frequency VRMP Ramp amplitude (1) TPS40193 240 300 360 TPS40192 500 600 700 1 kHz V PWM DMAX tON(min) tDEAD Maximum duty cycle (1) Minimum controlled pulse 85% (1) 110 Output driver dead time HDRV off to LDRV on 50 LDRV off to HDRV on 25 ns SOFT-START tSS Soft-start time tSSDLY Soft-start delay time 3 4 2 tREG Time to regulation 6 6 ms ERROR AMPLIFIER GBWP Gain bandwidth product (1) AOL DC gain (1) IIB Input bias current (current out of FB pin) IEAOP Output source current VFB = 0 V 1 IEAOM Output sink current VFB = 2 V 1 7 10 MHz 60 dB 100 nA mA SHORT CIRCUIT PROTECTION tPSS(min) Minimum pulse during short circuit (1) tBLNK Blanking time (1) tOFF Off-time between restart attempts 250 60 VILIMH (1) 4 Short circuit comparator threshold voltage Short circuit threshold voltage on high-side MOSFET 120 30 50 160 200 240 RCOMP(GND) = 4 kΩ, TJ = 25°C 80 100 120 RCOMP(GND) = 12 kΩ, TJ = 25°C 228 280 342 TJ = 25°C 400 550 650 RCOMP(GND) = OPEN, TJ = 25°C VILIM 90 ns ms mV Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 85°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT DRIVERS RHDHI High-side driver pull-up resistance VBOOT - VSW = 4.5 V, IHDRV = -100 mA 3 6 RHDLO High-side driver pull-down resistance VBOOT - VSW = 4.5 V, IHDRV = 100 mA 1.5 3.0 RLDHI Low-side driver pull-up resistance ILDRV = -100 mA 2.5 5.0 RLDLO Low-side driver pull-down resistance ILDRV = 100 mA 0.8 1.5 tHRISE High-side driver rise time (2) 15 35 10 25 15 35 10 25 (2) tHFALL High-side driver fall time tLRISE Low-side driver rise time (2) tLFALL Low-side driver fall time (2) CLOAD = 1 nF Ω ns UVLO VUVLO Turn-on voltage 3.9 4.2 4.4 V UVLOHYST Hysteresis 700 800 900 mV 1.9 3.0 SHUTDOWN VIH High-level input voltage, ENABLE VIL Low-level input votlage, ENABLE 0.6 V POWER GOOD VOV Feedback voltage limit for powergood 650 VUV Feedback voltage limit for powergood 525 VPG_HYST Powergood hysteresis voltage at FB pin RPGD Pulldown resistance of PGD pin VFB = 0 V 7 50 Ω IPDGLK Leakage current VFB = 0 V 7 12 μA 0.8 1.2 V mV 30 BOOT DIODE VDFWD Bootstrap diode forward voltage IBOOT = 5 mA 0.5 THERMAL SHUTDOWN TJSD Junction shutdown temperature (2) TJSDH Hysteresis (2) (2) 145 20 °C Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 5 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS RELATIVE REFERENCE FEEDBACK VOLTAGE vs JUNCTION TEMPERATURE RELATIVE OSCILLATOR FREQUENCY CHANGE vs JUNCTION TEMPERATURE 0.5 fSW − Relative Oscillator Frequency Change − % VFB− Relative Reverefnce Voltage Change − % 0.50 0.00 −0.05 −0.10 −0.15 −0.20 −0.25 −0.30 −0.35 −0.40 −0.45 0.0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 −3.5 −4.0 −4.5 −40 −25 −10 −0.50 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C Figure 1. Figure 2. SHUTDOWN INPUT CURRENT vs JUNCTION TEMPERATURE ENABLE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2.5 60 VENABLE − Enable Threshold Voltage − V VENABLE< 0.6 V IVDD − Shutdown Current − µA 50 40 30 20 10 0 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C 2.0 Turn On 1.5 1.0 Turn Off 0.5 0 −40 −25 −10 Figure 3. 6 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C Figure 4. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) SOFT START TIME vs JUNCTION TEMPERATURE LOW-SIDE MOSFET CURRENT LIMIT THRESHOLD vs JUNCTION TEMPERATURE 4.05 400 350 VILIM − Current Limit Threshold − mV tSS − Soft start Time − ms 4.00 3.95 3.90 3.85 3.80 3.75 −40 −25 −10 5 20 35 50 65 80 300 RCOMP = 12 kΩ 250 200 100 RCOMP = 4 kΩ 50 0 −40 −25 −10 5 95 110 125 TJ − Junction Temperature − °C 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C Figure 5. Figure 6. HIGH-SIDE MOSFET CURRENT LIMIT THRESHOLD vs JUNCTION TEMPERATURE TOTAL TIME TO REGULATION vs JUNCTION TEMPERATURE 800 6.3 6.1 700 5.9 600 tREG − Regulation Time − ms VILIMH − Current Limit Threshold − mV RCOMP = OPEN 150 500 400 300 200 100 5.7 5.5 5.5 5.3 5.1 4.9 4.7 0 −40 −25 −10 5 20 35 50 65 80 TJ − Junction Temperature − °C 95 110 125 4.4 −40 −25 −10 5 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 7 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS (continued) POWERGOOD THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE SHUTDOWN CURRENT vs INPUT VOLTAGE 100 VENABLE < 0.6 V Overvoltage 90 660 80 640 IVDD − Supply Current − µA VOV, VUV − Powergood Threshold Voltage − mV 680 620 600 580 560 540 Undervoltage 70 60 50 40 30 20 520 10 500 −40 −25 −10 0 5 20 35 50 65 80 4 95 110 125 6 8 10 12 14 16 18 VVDD − Input Voltage − V TJ − Junction Temperature − °C Figure 9. Figure 10. RELATIVE OVERCURRENT TRIP POINT vs FREEWHEEL TIME IOC - Relative Overcurrent Trip Point - A 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0.4 0.6 0.8 1.0 1.2 1-D - Freewheel Time - ms 1.4 1.6 Figure 11. 8 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 DEVICE INFORMATION Table 1. TERMINAL FUNCTIONS TERMINAL NAME NO. BOOT 8 I/O DESCRIPTION I Gate drive voltage for the high-side N-channel MOSFET. A capacitor 100 nF typical must be connected between this pin and SW. BP5 6 O Output bypass for the internal regulator. Connect at least 1μF capacitor from this pin to GND. Larger capacitors, up to 4.7μF will improve noise performance when using a low side FET with a gate charge of 25nC or greater. Low power, low noise loads may be connected here if desired. The sum of the external load and the gate drive requirements must not exceed 50 mA. This regulator is turned off when ENABLE is pulled low. COMP 3 O Output of the error amplifier. ENABLE 1 I Logic level input which starts or stops the controller from an external user command. A high-level turns the controller on. A weak internal pull-up holds this pin high so that the pin may be left floating if this function is not used. FB 2 I Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference voltage (591 mV typical) GND (11) - Thermal pad ground connection. Common reference for the device. Connect to the system GND. HDRV 10 O Bootstrapped output for driving the gate of the high side N channel FET. LDRV 7 O Output to the rectifier MOSFET gate PGD 5 O Open drain power good output SW 9 I Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high side MOSFET driver VDD 4 I Power input to the controller DRC PACKAGE (TOP VIEW) PGD 5 VDD COMP 4 3 FB ENABLE 2 1 9 10 SW HDRV TPS40192 TPS40193 6 BP5 7 8 LDRV BOOT Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 9 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 VDD SC + OCL FAULT Fault Controller CLK ENABLE SD 1 + OCH SD UVLO Soft Start Ramp Generator VDD - 0.5 V VDD BP5 5V Regulator 4 6 4.2 V + 5V UVLO CLK COMP Oscillator 3 FAULT UVLO 591 mV FB 2 SS + + Error Amplifier GND PP 8 SD 5V PWM Logic and Anti-Cross Conduction 10 HDRV 5V UVLO FAULT + 9 SW 7 LDRV SC Threshold Latch FB Short Circuit Threshold Selector SD SS Powergood Control ENABLE 5 PGD 750 kW SC: -110 mV, -200 mV, or -280 mV UDG-06064 10 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 APPLICATION INFORMATION Introduction The TPS40192 and TPS40193 are cost optimized controllers providing all the necessary features to construct a high performance DC/DC converter while keeping costs to a minimum. Support for pre-biased outputs eliminates concerns about damaging sensitive loads during startup. Strong gate drivers for the high side and rectifier N-channel MOSFETs decrease switching losses for increased efficiency. Adaptive gate drive timing prevents shoot through and minimizes body diode conduction in the rectifier MOSFET, also increasing efficiency. Selectable short circuit protection thresholds and hiccup recovery from a short circuit increase design flexibility and minimize power dissipation in the event of a prolonged output fault. A dedicated enable pin (ENABLE) allows the converter to be placed in a very low quiescent current shutdown mode. Internally fixed switching frequency and soft-start time reduce external component count, simplifying design and layout, as well as reducing footprint and cost. The 3 mm × 3 mm package size also contributes to a reduced overall converter footprint. Voltage Reference The band gap cell is designed with a trimmed 591 mV output. The 0.5% tolerance on the reference voltage allows the user to design a very accurate power-supply. Oscillator The TPS40192 has a fixed internal switching frequency of 600 kHz while the TPS40193 operates at 300 kHz. UVLO When the input voltage is below the UVLO threshold, the device holds all gate drive outputs in the low (OFF) state. When the input rises above the UVLO threshold, and the ENABLE pin is above the turn ON threshold, the oscillator begins to operate and the start-up sequence is allowed to begin. The UVLO level is internally fixed at 4.2 V. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 11 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Enable Functionality The TPS40192 and TPS40193 have a dedicated ENABLE pin. This simplifies user level interface design since no multiplexed functions exist. Another benefit is a true low power shutdown mode of operation. When the ENABLE pin is pulled to GND, all unnecessary functions, including the BP5 regulator, are turned off, reducing the device IDD current to 45-uA. A functionally equivalent circuit of the enable circuitry shown in Figure 12. VDD 4 200 kΩ 1.5 MΩ 1 kΩ ENABLE 1 To Enable Chip 200 Ω 1 kΩ 300 kΩ GND 5 UDG−05061 Figure 12. TPS40192 ENABLE Pin Internal Circuitry If the ENABLE pin is left floating, the chip starts automatically. The pin must be pulled to less than 600 mV to guarantee that the TPS40192/3 is in shutdown mode. Note that the ENABLE pin is relatively high impedance. In some situations, there could be enough noise nearby to cause the ENABLE pin to swing below the 600 mV threshold and give erroneous shutdown commands to the rest of the device. There are two solutions to this problem should it arise. 1. Place a capacitor from ENABLE to GND. A side effect of this is to delay the start of the converter while the capacitor charges past the enable threshold 2. Place a resistor from VDD to ENABLE. This causes more current to flow in the shutdown mode, but does not delay converter startup. If a resistor is used, the total current into the ENABLE pin should be limited to no more than 500 μA. 12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Startup Sequence and Timing The TPS40192/3 startup sequence is as follows. After input power is applied, the 5-V onboard regulator comes up. Once this regulator comes up, the device goes through a period where it samples the impedance at the COMP pin and determines the short circuit protection threshold voltage, by placing 400 mV on the COMP pin for approximately 1 ms. During this time, the current is measured and compared against internal thresholds to select the short circuit protection threshold. After this, the COMP pin is brought low for 1 ms. This ensures that the feedback loop is preconditioned at startup and no sudden output rise occurs at the output of the converter when the converter is allowed to start switching. After these initial two milliseconds, the internal soft-start circuitry is engaged and the converter is allowed to start. See Figure 13. ENABLE COMP VOUT Soft Start Time (4 ms) SC Threshold Configured (1 ms) Compensation Network Zeroed (1 ms) UDG−06062 Figure 13. Startup Sequence Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 13 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Selecting the Short Circuit Current A short circuit in the TPS40192/3 is detected by sensing the voltage drop across the low-side FET when it is on, and across the high-side FET when it is on. If the voltage drop across either FET exceeds the short circuit threshold in any given switching cycle, a counter increments one count. If the voltage across the high-side FET was higher that the short circuit threshold, that FET is turned off early. If the voltage drop across either FET does not exceed the short circuit threshold during a cycle, the counter is decremented for that cycle. If the counter fills up (a count of 7) a fault condition is declared and the drivers turn off both MOSFETs. After a timeout of approximately 50 ms, the controller attempts to restart. If a short circuit is still present at the output, the current quickly ramps up to the short circuit threshold and another fault condition is declared and the process of waiting for the 50 ms an attempting to restart repeats. The low side threshold will increase as the low side on time decreases due to blanking time and comparator response time. See Figure 11 for changes in the threshold as the low side FET conduction time decreases. The TPS40192/3 provides three selectable short circuit protection thresholds for the low side FET: 100 mV, 200 mV and 280 mV. The particular threshold is selected by connecting a resistor from COMP to GND. Table 2 shows the short circuit thresholds for corresponding resistors from COMP to GND. When designing the compensation for the feedback loop, remember that a low impedance compensation network combined with a long network time constant can cause the short circuit threshold setting to not be as expected. The time constant and impedance of the network connected from COMP to FB should be as in Equation 1 to guarantee no interaction with the short circuit threshold setting. 0.4 V e ǒR1*tC1Ǔ t 10 mA R1 (1) where • • t is 1 ms, the sampling time of the short circuit threshold setting circuit R1 and C1 are the values of the components in Figure 14 C2 VOUT RCOMP C1 R1 2 3 FB COMP TPS40192/3 UDG−06061 Figure 14. Short Circuit Threshold Feedback Network 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Table 2. Short Circuit Threshold Voltage Selection COMPARATOR RESISTANCE RCOMP (kΩ) CURRENT LIMIT THRESHOLD VOLTAGE (mV) VILIM(V) 12 ±10% 280 Open 200 4 ±10% 100 The range of short circuit current thresholds that can be expected is shown in Equation 2 and Equation 3. V ILIM(max) I SCP(max) + RDS(on)min I SCP(min) + (2) V ILIM(min) RDS(on)max (3) where • • • ISCP is the short circuit current VILIM is the short circuit threshold for the low-side MOSFET RDS(on) is the channel resistance of the low-side MOSFET Note that due to blanking time considerations, overcurrent threshold accuracy may fall off for duty cycle greater than 75% with the TPS40192, or 88% with the TPS40193. The reason for this is that the over current comparator will have only a very short time to sample the SW pin voltage under these conditions and may not have time to respond to voltages very near the threshold. The short circuit protection threshold for the high-side MOSFET is fixed at 550 mV typical, 400 mV minimum. This threshold is in place to provide a maximum current output using pulse by pulse current limit in the case of a fault. The pulse will be terminated when the voltage drop acros the high side FET exceeds the short circuit threshold. The maximum amount of current that can be guaranteed to be sourced from a converter can be found by Equation 4. V ILIM(min) I OUT(max) + RDS(on)max (4) where • • • IOUT(max) is the maximum current that the converter is guaranteed to source VILIMH(min) is the short circuit threshold for the high-side MOSFET (400 mV) RDS(on)max is the maximum resistance of the high-side MOSFET If the required current from the converter is greater than the calculated IOUT(max) , a lower resistance high-side MOSFET must be chosen. Both the high side and low side thresholds use temperature compensation to approximate the change in resistance for a typical power MOSFET. This will help couneract shifts in overcurrent thresholds as temperature increases. For this to be effective, the MOSFETs and the IC must be well coupled thermally. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 15 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 5-V Regulator These devices have an on board 5-V regulator that allows the parts to operate from a single voltage feed. No separate 5-V feed to the part is required. This regulator needs to have a minimum of 1-μF of capacitance on the BP5 pin to guarantee stability. A ceramic capacitor is suggested for this purpose. This regulator can also be used to supply power to nearby circuitry, eliminating the need for a separate LDO in some cases. If this pin is used for external loads, be aware that this is the power supply for the internals of the TPS40192/3. While efforts have been made to reduce sensitivity, any noise induced on this line has an adverse effect on the overall performance of the internal circuitry and shows up as increased pulse jitter, or skewed reference voltage. Also, when the device is disabled by pulling the EN pin low, this regulator is turned off and will not be available to supply power. The amount of power available from this pin varies with the size of the power MOSFETs that the drivers must operate. Larger MOSFETs require more gate drive current and reduce the amount of power available on this pin for other tasks. The total current that can be drwan from this pin by both the gate drive and external loads cannot exceed 50mA. The IC itself will use up to 4mA from the regulator and the total gate drive current can be found from Equation 5. For regulator stability, a 1-μF capacitor is required to be connected from BP5 to GND. In some applications using higher gate charge MOSFETs, a larger capacitor is required for noise suppression. For a total gate charge of both the high and low side MOSFETs greater than 20 nC, a 2.2-μF or larger capacitor is recommended. I G + f SW ǒQG (high) ) QG (low)Ǔ (5) where • • • • 16 IG is the required gate drive current fSW is the switching frequency (600 kHz for TPS40192, and 300 kHz for TPS40193) QG(high) is the gate charge requirement for the high-side FET when VGS=5 V QG(low) is the gate charge requirement for the low-side FET when VGS=5 V Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Pre-Bias Startup The TPS40192/3 contains a unique circuit to prevent current from being pulled from the output during startup in the condition the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft-start becomes greater than feedback voltage [VFB]), the controller slowly activates synchronous rectification by starting the first LDRV pulses with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensures that the out voltage (VOUT) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased startup to normal mode operation with minimal disturbance to the output voltage. The amount of time from the start of switching until the low-side MOSFET is turned on for the full (1-D) interval is defined by 32 clock cycles. Drivers The drivers for the external HDRV and LDRV MOSFETs are capable of driving a gate-to-source voltage of 5 V. The LDRV driver switches between VDD and GND, while HDRV driver is referenced to SW and switches between BOOT and SW. The drivers have non-overlapping timing that is governed by an adaptive delay circuit to minimize body diode conduction in the synchronous rectifier. The drivers are capable of driving MOSFETS that are appropriate for a 15-A (TPS40192) or 20A (TPS40193) converter. Power Good The TPS40192/3 provides an indication that output power is good for the converter. This is an open drain signal and pulls low when any condition exists that would indicate that the output of the supply might be out of regulation. These conditions include: • VFB is more than ±10% from nominal • soft-start is active • an undervoltage condition exists for the device • a short circuit condition has been detected • die temperature is over (145°C) NOTE: When there is no power to the device, PGOOD is not able to pull close to GND if an auxiliary supply is used for the power good indication. In this case, a built in resistor connected from drain to gate on the PGOOD pull down device makes the PGOOD pin look approximately like a diode to GND. Thermal Shutdown If the junction temperature of the device reaches the thermal shutdown limit of 145°C, the PWM and the oscillator are turned off and HDRV and LDRV are driven low, turning off both FETs. When the junction cools to the required level (125°C nominal), the PWM inititates soft start as during a normal power up cycle. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 17 TPS40192, TPS40193 SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 www.ti.com Layout Recommendations and Sample Layout Layout Recommendations: • PowerPad™ is the device’s(U1) only GND connection. PowerPad™ must be connected to ground. • PowerPad™ should be directly connected to SYNC FET (Q3) source with short, wide trace. • Locate 3-5 vias in PowerPad™ land to remove heat from the device. • Connect input capacitors (C7 & C9) and output capacitors (C8 & C10) grounds directly to SYNC FET (Q3) source with wide copper trace or solid power ground island. • Locate input capacitors (C7 & C9), MOSFETs (Q2 & Q3), inductor (L1) and output capacitor (C8 & C10) over power ground island. • Use short, wide traces for LDRV and HDRV MOSFET connections. • Route SW trace near HDRV trace. • Route GND trace near LDRV trace. • Use separate analog ground island under feedback components (C1, C2, C3, R5, R6, R7, R8 & R10). • Connect ground islands at PowerPad™ with 10-mil wide trace opposite SYNC FET (Q2) source connection. Sample Layout: Figure 15. TPS40192/3 Sample Layout - Component Placement and Top Side Copper Figure 16. TPS40192/3 Sample Layout - Bottom Side Copper (X-Ray view from Top) 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 DESIGN EXAMPLE Introduction This example illustrates the design process and component selection for a 12 V to 1.8 V point-of-load synchronous buck regulator using the TPS40192. A definition of symbols used can be found in Table 8 of this datasheet. Table 3. Design Example Electrical Characteristics PARAMETER TEST CONDITION MIN NOM 8 MAX VIN Input voltage VIN(ripple Input ripple IOUT = 10 A Output voltage 0 A ≤ IOUT ≤ 10 A Line regulation 8.0 V ≤ VIN ≤ 14 V 0.5% Load regulation 0 A ≤ IOUT ≤ 10 A 0.5% VRIPPLE Output ripple IOUT = 10 A VOVER Output overshoot 3 A ≤ IOUT ≤ 7 A VUNDER Output undershoot IOUT Output current ISCP Short circuit current trip point η Efficiency fSW Switching frequency ) VOUT 0.6 1.764 UNIT 14 1.800 V 1.836 36 50 mV 50 0 10 VIN =12 V, IOUT = 5 A A 90% 600 kHz Size The list of materials for this application is shown Table 7. The efficiency, line and load regulation from boards built using this design are shown in Figure 17 and Table 3. Gerber Files and additional application information are available from the factory. Figure 17. TPS40192 Sample Schematic Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 19 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Design Procedure Selecting the Switching Frequency For this design the TPS40192, with fSW = 600 kHz, is selected to reduce inductor and capacitor sizes. Inductor Selection The inductor is typically sized for approximately 30% peak-to-peak ripple current (IRIPPLE). Given this target ripple current, the required inductor size can be calculated by Equation 6. V IN(max) * V OUT VOUT 1 L[ 0.3 I OUT V IN(max) f SW (6) Solving this for • • • • VIN(max) = 14 V VOUT = 1.8 V IOUT = 10A fSW = 600 kHz an inductor value of 0.87 μH is obtained. A standard value of 1.0 μH is selected. Solving for IRIPPLE with 1.0 μH results in 2.6-A peak-to-peak ripple. The RMS current through the inductor is approximated by Equation 7. I L(rms) + Ǹǒ 2 2 I L(avg)Ǔ ) 1 ǒI RIPPLEǓ + 12 Ǹǒ 2 I OUTǓ ) 1 ǒI RIPPLEǓ 12 2 (7) Using Equation 7, the maximum RMS current in the inductor is approximately 10.03 A 20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Output Capacitor Selection (C8) The selection of the output capacitor is typically driven by the output transient response. The Equation 8 and Equation 9 overestimate the voltage deviation to account for delays in the loop bandwidth and can be used to determine the required output capacitance. 2 I V OVER t TRAN COUT V UNDER t ǒITRANǓ L I TRAN L + VOUT V OUT C OUT I DT + TRAN COUT I TRAN COUT DT + I TRAN COUT I TRAN L + V IN * V OUT ǒV (8) ǒITRANǓ IN * 2 L VOUTǓ COUT (9) If • • VIN(min) > 2 × VOUT, use overshoot to calculate minimum output capacitance. VIN(min) < 2 × VOUT, use undershoot to calculate minimum output capacitance. C OUT(min) + ǒITRAN(max)Ǔ V OUT 2 L V OVER (10) Based on a 4-A load transient with a maximum 50 mV overshoot at 8.0 V input, calculate a minimum 178-μF output capacitance. With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is approximated by Equation 11. ESR MAX t VRIPPLE(tot) * VRIPPLE(cap) C OUT V RIPPLE(tot) * + ǒ Ǔ I RIPPLE C OUT f SW I RIPPLE (11) Based on 178 μF of capacitance, 2.6-A ripple current, 600-kHz switching frequency and 36-mV ripple voltage, calculate a capacitive ripple of 24.3 mV and a maximum ESR of 4.4 mΩ. Two 1206 100-μF, 6.3-V X5R ceramic capacitors are selected to provide more than 178-μF of minimum capacitance and less than 4.4 mΩ of ESR (2.5 mΩ each). Peak Current Rating of the Inductor With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum saturation current rating for the inductor. The start-up charging current is approximated by Equation 12. V COUT I CHARGE + OUT T SS (12) Using the TPS40192's minimum soft-start time of 3.0 ms, COUT = 240 μF and VOUT = 1.8 V, ICHARGE = 144 mA. I L(peak) + I OUT(max) ) 1 I RIPPLE ) I CHARGE 2 (13) Table 4. Inductor Requirements PARAMETER Inductance SYMBOL VALUE UNITS μH L 1.0 RMS current (thermal rating) IL(rms) 10.03 Peak current (saturation rating) IL(peak) 11.3 A A PG0083.102 1.0-μH is selected for its small size, low DCR (6.6 mΩ) and high current handling capability (12 A thermal, 17 A saturation) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 21 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Input Capacitor Selection (C7) The input voltage ripple is divided between capacitance and ESR. For this design VRIPPLE(cap) = 400 mV and VRIPPLE(ESR) = 200 mV. The minimum capacitance and maximum ESR are estimated by Equation 14. I LOAD VOUT C IN(min) + VRIPPLE(cap) VIN f SW (14) ESR MAX + VRIPPLE(esr) I LOAD ) 1 I RIPPLE 2 (15) For this design CIN > 9.375 μF and ESR < 17.7 mΩ . The RMS current in the input capacitors is estimated by Equation 16. ǒ Ǔ ǸVVOUT * VOUTV I RMS(Cin) + I IN(rms) * I IN(avg) + I OUT ) 1 I RIPPLE 12 IN I OUT IN (16) For this design VIN = 14 V, VOUT = 1.8 V, IOUT=10 A and IRIPPLE = 2.6 A calculate an RMS of 2.37 A, so the total of our input capacitors must support 2.37 A of RMS ripple current. Two 1210 10-μF 25V X5R ceramic capacitors with about 2 mΩ ESR and a 2-ARMS current rating are selected. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to ensure the capacitors have sufficient capacitance at the working voltage. 22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 MOSFET Switch Selection (Q1, Q2) The switching losses for the high-side FET are estimated by Equation 17. Q GD1 P G1_SW + 1 VIN I OUT T SW f SW + 1 VIN I OUT 2 2 VDD*V TH RDRV f SW (17) For this design switching losses will be highest at high-line Designing for 1 W of total losses in each MOSFETS and 60% of the total high-side FET losses in switching losses, we can estimate our maximum gate-drain charge for the design by using Equation 18. PG1SW VDD * V T 1 Q GD1 t VIN I OUT RDRV f SW (18) For a 2-V gate threshold MOSFET, the TPS40192's 5-V gate drive, and the TPS40192's 2.5-Ω drive resistance, we estimate a maximum gate-to-drain charge of 8.5 nC. The switching losses of the synchronous rectifier are lower than the switching losses of the main FET because the voltage across the FET at the point of switching is reduced to the forward voltage drop across the body diode of the SR FET and are estimated by using Equation 19. The conduction losses in the main FET are estimated by the RMS current through the FET times its RDS(on). 2 VOUT 1 I P G1COM + I OUT R DS(on) D + I L(rms) RDS(on)Q1 RIPPLE 12 V IN (19) ǒ Ǔ Estimating about 40% of total MOSFET losses to be high-side conduction losses, the maximum RDS(on) of the high-side FET can be estimated by using Equation 20. P Q1C(on) R DS(on)Q1 + 2 V OUT I L(rms) VIN (20) ǒ Ǔ For this design with IL_RMS = 11.22 ARMS and 8 V to 1.8 V design, calculate RDS(on)Q1 < 17.3 mΩ for our main switching FET. Estimating 80% of total low-side MOSFET losses in conduction losses, repeat the calculation for the synchronous rectifier, whose losses are dominated by the conduction losses. Calculate the maximum RDS(on) of the synchronous rectifier by Equation 21. PQ2C(on) R DS(on)Q2 + 2 V I L(rms) 1 * OUT V IN ǒ Ǔ ǒ Ǔ (21) For this design IL(RMS) = 10.22 A at VIN = 14 V to 1.8 V RDS(on)Q2(max) = 8.8 mΩ. Table 5. Inductor Requirements VIN = 4.5 V PARAMETER SYMBOL VALUE UNITS High-side MOSFET on-resistance RDS(on) 17.3 mΩ High-side MOSFET gate-to-drain charge QGD1 8.5 nC Low-side MOSFET on-resistance RDS(on)Q2 8.8 mΩ The IRF7466 has an RDS(on)MAX of 17 mΩ at 4.5-V gate drive and only 8.0-nC VGD "Miller" charge with a 4.5-V gate drive, and is chosen as a high-side FET. The IRF7834 has an RDS(on)MAX of 5.5 mΩ at 4.5-V gate drive and 44 nC of total gate charge. These two FETs have maximum total gate charges of 23 nC and 44 nC respectively, which draws 40.2-mA from the 5-V regulator, less than its 50-mA minimum rating. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 23 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Boot Strap Capacitor To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than 50 mV. C BOOST + 20 Q G1 (22) Based on the IRF7466 MOSFET with a gate charge of 23 nC, we calculate minimum of 460 nF of capacitance. The next higher standard value of 470 nF is selected for the bootstrap capacitor. Input Bypass Capacitor (C6) As suggested the TPS40192/93 datasheet, select a 1.0-μF ceramic bypass capacitor for VDD. BP5 Bypass Capacitor (C5) The TPS40192 recommends a minimum 1.0-μF ceramic capacitance to stabilize the 5-V regulator. To limit regulator noise to less than 10 mV, the bypass capacitor is sized by using Equation 23. C BP5 + 100 MAXǒQ G1, Q G2Ǔ (23) Since Q2 is larger than Q1 and Q2's total gate charge is 44 nC, a BP5 capacitor of 4.4-μF is calculated, and the next larger standard value of 4.7 μF is selected to limit noise on the BP5 regulator. Input Voltage Filter Resistor (R11) VIN(min) > 6.0 V so a 0 Ω resistor is placed in the VDD resistor location. If VIN(min) was < 6.0 V, an optional 1Ω to 2 Ω series VDD resistor could be used to filter switching noise from the device. Limit the voltage drop across this resistor to less than 50 mV. VRVDD(max) 50 mV R VDD t + I DD 3 mA ) ǒQ G1, Q G2Ǔ f SW (24) Driving the two FETs with 23 nC and 44 nC respectively, we calculate a maximum IVDD current of 43 mA and would select a 1-Ωresistor. Short Circuit Protection (R9) The TPS40192/93 use the negative drop across the low-side FET during the OFF time to measure the inductor current. The voltage drop across the low-side FET is given by Equation 25. V CS + I L(peak) RDS(on) (25) When 8 V ≤ VIN ≤14 V, IL(peak) = 11.5 A Using the IRF7834 MOSFET, we calculate a peak voltage drop of 63.3 mV. The TPS40192's internal temperature coefficient helps compensate for the MOSFET's RDS(on) temperature coefficient. For this design select the short circuit protection voltage threshold of 110 mV by selecting R9 = 3.9 kΩ. 24 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Feedback Compensation Modeling the Power Stage The DC gain of the modulator is given by Equation 26. dV OUT dt 1 A MOD + + dD V IN + dVCOMP V COMP dV RAMP T SW V IN (26) Since the peak-to-peak ramp voltage given in the Electrical Characteristics Table is projected from the ramp slope over a full switching period, the modulator gain can be calculated as Equation 27. V IN A MOD + VRAMP(p*p) (27) This design finds a maximum modulator gain of 14 (23.0 dB). The L-C filter applies a double pole at the resonance frequency described in Equation 28. 1 f RES + Ǹ 2p L C (28) For this design with a 1.0-μH inductor and 2 100-μF capacitors, the resonance frequency is approximately 11.3 kHz. At any lower frequency, the power stage has a DC gain of 23 dB and at any higher frequency the power stage gain drops off at -40 dB per decade. The ESR zero is approximated in Equation 29. 1 f ESR + 2p C OUT R ESR (29) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 25 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 For COUT = 2, 100-μF and RESR = 2.5 mΩ each, fESR = 636 kHz, greater than 1/5th the switching frequency and outside the scope of the error amplifier design. The gain of the power stage would change to -20 dB per decade above fESR. The straight line approximation the power stage gain is described in Figure 18. fRES −40 dB/decade AMOD 0 dB −20 dB/decade fESR Frequency (Log Scale) Figure 18. Approximation of Power Stage Gain The following compensation design procedure assumes fESR > fRES. For designs using large high-ESR bulk capacitors on the output where fESR < fRES. Type-II compensation can be used but is not addressed in this document. C3 3 R6 C1 R8 VOUT 2 C2 + To PWM R10 + VFB R7 11 Power Pad UDG−06068 Figure 19. Type-III Compensator Used with TPS40040/41 26 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 Feedback Divider (R7, R8) Select R8 to be between 10 kΩ and 100 kΩ. For this design, select 20 kΩ. R7 is then selected to produce the desired output voltage when VFB = 0.591 V using Equation 30. V FB R8 R7 + V OUT * V FB (30) VFB = 0.591 V and R8 = 20 kΩ for VOUT = 1.8 V, R7 = 9.78 kΩ, so the value of 9.76 kΩ is selected as the closest standard value. A slightly lower nominal value increases the nominal output voltage slightly to compensate for some trace impedance at load. Error Amplifier Compensation (R6, R10, C1, C2, C3) Place two zeros at 50% and 100% of the resonance frequency to boost the phase margin before resonance frequency generates -180° of phase shift. For fRES = 11.7 kHz, FZ1 = 5.8 kHz and FZ2 = 11 kHz. Selecting the crossover frequency (fCO) of the control loop between 3 times the LC filter resonance and 1/5th the switching frequency. For most applications 1/10th the switching frequency provides a good balance between ease of design and fast transient response. • If fESR < fCO FP1 = fESR and FP2 = 4 × fCO. • If fESR > 2 × fCO; FP1 = fCO and FP2 = 8 × fCO. For this design • fSW = 600 kHz, • fRES = 11.7 kHz • fESR = 636 kHz • fCO = 60 kHz and since • fESR > 2 × fCO, FP1 = fCO = 60 kHz and FP2 = 4 × fCO = 500 kHz. Since fCO < fESR the power stage gain at the desired crossover can be approximated in Equation 31. A PS(fco) + AMOD(dc) * 40 LOG ǒ Ǔ f CO f RES (31) 5.4 dB/20 APS(FCC) = -5.4 dB, and the error amplifier gain between the poles should be should be 10 = 1.86. Table 6. Error Amplifier Design Parameters PARAMETER SYMBOL VALUE FZ1 5.8 Second zero frequency FZ2 11.0 First pole frequency FP1 60 First zero frequency Second pole frequency Midband gain FP2 500 AMID(band) 1.86 UNITS kHz V/V Approximate C2 with the formula described in Equation 32. 1 C2 + 2p R8 f Z2 (32) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 27 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 C2 = 1000 pf (A standard capacitor value to calculated 723 pF) and approximate R6 with the formula described in Equation 33. 1 R10 + 2p C2 f P1 (33) R10 = 2.61 kΩ (Closest standard resistor value to calculated 2.65 kΩ ) Calculate R3 with Equation 34. A MID(band) (R10 R8) R6 + R10 ) R8 (34) With AMID(band) = 1.86, R10 = 2.61 kΩ and R8 = 20 kΩ , R6 = 4.22 kΩ (Closest standard resistor value to calculated 4.29 kΩ ). Calculate C1 and C3 using Equation 35 and Equation 36. 1 C3 + 2p R6 f Z1 C1 + 2p 1 R6 (35) f P1 (36) For R6 = 4.22kΩ , C1 = 100 pF (a standard value close to 75 pF) C3 = 1000 pF (the closest standard value to 7.5 nF) error amplifier straight line approximation transfer function is described in Figure 20. fP1 fP2 0 dB AMID(band) fZ1 fZ2 Frequency (Log Scale) Figure 20. Error Amplifier Transfer Function Approximation 28 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 List of Materials Table 7. List of Materials QTY RefDe s Value Description Size Part Number MFR 1 C1 100 pF Capacitor, Ceramic, 10V, C0G, 10% 0603 STD STD 1 C2 1000 pF Capacitor, Ceramic, 10V, C0G, 10% 0603 STD STD 1 C3 10 nF Capacitor, Ceramic, 10V, C0G, 10% 0603 STD STD 1 C4 1.0 μF Capacitor, Ceramic, 25V, X5R, 20% 0805 STD STD 1 C5 4.7 μF Capacitor, Ceramic, 10V, X5R, 20% 0805 STD STD 1 C6 470 nF Capacitor, Ceramic, 10V, X5R, 20% 0603 Std Std 2 C7 10 μF Capacitor, Ceramic, 25V, X5R, 20% 1210 C3225X7R1E106M TDK 2 C8 100 μF Capacitor, Ceramic, 6.3V, X5R, 20% 1210 C3225X5R0J107M TDK 1 C11 1.0 μF Capacitor, Ceramic, 6.3V, X5R, 20% 0603 STD STD 1 L1 1.0 μH Inductor, SMT, 1.0-μF, 6.6 mΩ, 12 A / 17 A 0.268 x 0.268 inch PG0083.102 Pulse 1 Q1 2N7002W Mosfet, N-Ch, VDS 60 V, RDS(on) 2 Ω, IDD 115 mA SOT-323 (SC-70) 2N7002W-7 Diodes Inc 1 Q2 IRF7466 Transistor, MOSFET, N-channel, 30 V, RDS(on) 17 mΩ, 9 A SO8 IRF7466 IR 1 Q3 IRF7834 Transistor, MOSFET, N-channel, 30 V, RDS(on) 5.5 mΩ, 9 A SO8 IRF7834 IR 1 R1 5.1 kΩ Resistor, Chip, 1/16W, 5% 0603 Std Std 1 R2 2 kΩ Resistor, Chip, 1/16W, 5% 0603 Std Std 1 R4 100 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R6 4.22 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R7 9.76 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R8 20 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std 1 R9 3.9 kΩ Resistor, Chip, 1/16W, 5% 0603 Std Std 1 R10 2.61 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std 2 R11, R13 0 Resistor, Chip, 1/16W, 5% 0603 Std Std 1 R12 100 kΩ Resistor, Chip, 1/16W, 5% 0603 Std Std 1 U1 TPS40192DRC Cost Optimized Midrange Input Votlage High-Frequancy Synchronous Buck Controller DRC10 TPS40192DRC TI Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 29 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 DEFINITION OF SYMBOLS Table 8. Definition of Symbols SYMBOL DESCRIPTION VIN(max) Maximum Operating Input Voltage VIN(min) Minimum Operating Input Voltage VIN(ripple) Peak to Peak AC ripple voltage on VIN VOUT Target Output Voltage VOUT(ripple) Peak to Peak AC ripple voltage on VOUT IOUT(max) Maximum Operating Load Current IRIPPLE Peak-to-Peak ripple current through Inductor IL(peak) Peak Current through Inductor IL(rms) Root Mean Squared Current through Inductor IRMS(Cin) Root Mean Squared Current through Input Capacitor fSW Switching Frequency fCO Desired Control Loop Crossover frequency AMOD Low Frequency Gain of the PWM Modulator ( VOUT / VCONTROL) VCONTROL PWM Control Voltage (Error Amplifier Output Voltage VCOMP) fRES L-C Filter Resonant Frequency fESR Output Capacitors' ESR zero Frequency FP1 First Pole Frequency in Error Amplifier Compensation FP2 Second Pole Frequency in Error Amplifier Compensation FZ1 First Zero Frequency in Error Amplifier Compensation FZ2 Second Pole Frequency in Error Amplifier Compensation QG1 Total Gate Charge of Main MOSFET QG2 Total Gate Charge of SR MOSFET RDS(on)Q1 "ON" Drain to Source Resistance of Main MOSFET RDS(on)Q2 "ON" Drain to Source Resistance of SR MOSEFT PQ1C(on) Conduction Losses in Main Switching MOSFET PQ1SW Switching Losses in Main Switching MOSFET PQ2C(on) Conduction Losses in Synchronous Rectifier MOSFET QGD Gate to Drain Charge of Synchronous Rectifier MOSFET QGS Gate to Source Charge of Synchronous Rectifier MOSFET 30 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 TPS40192, TPS40193 www.ti.com SLUS719B – MARCH 2007 – REVISED SEPTEMBER 2007 ADDITIONAL REFERENCES Related Parts The following parts have characteristics similar to the TPS40192/3 and may be of interest. Related Parts DEVICE DESCRIPTION TPS40100 Midrange Input Synchronous Controller with Advanced Sequencing and Output Margining TPS40075 Wide Input Synchronous Controller with Voltage Feed Forward TPS40190 Low Pin Count Synchronous Buck Controller References These references may be found on the web at www.power.ti.com under Technical Documents. Many design tools and links to additional references, including design software, may also be found at www.power.ti.com 1. Under The Hood Of Low Voltage DC/DC Converters, SEM1500 Topdevice 5, 2002 Seminar Series 2. Understanding Buck Power Stages in Switchmode Power Supplies, SLVA057, March 1999 3. Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar Series 4. Designing Stable Control Loops, SEM 1400, 2001 Seminar Series 5. Additional PowerPADTM information may be found in Applications Briefs SLMA002 and SLMA004 6. QFN/SON PCB Attachment, Texas Instruments Literature Number SLUA271, June 2002 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40192 TPS40193 31 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS40192DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40192DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40192DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40192DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40193DRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40193DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40193DRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40193DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40192DRCR DRC 10 SITE 41 330 12 3.3 3.3 1.1 8 12 Q2 TPS40192DRCT DRC 10 SITE 41 180 12 3.3 3.3 1.1 8 12 Q2 TPS40193DRCR DRC 10 SITE 41 330 12 3.3 3.3 1.1 8 12 Q2 TPS40193DRCT DRC 10 SITE 41 180 12 3.3 3.3 1.1 8 12 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2007 Device Package Pins Site Length (mm) Width (mm) TPS40192DRCR DRC 10 SITE 41 346.0 346.0 29.0 TPS40192DRCT DRC 10 SITE 41 190.0 212.7 31.75 TPS40193DRCR DRC 10 SITE 41 346.0 346.0 29.0 TPS40193DRCT DRC 10 SITE 41 190.0 212.7 31.75 Pack Materials-Page 2 Height (mm) IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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