TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 1.5-A/2.5-A Dual, Fully-Synchronous Buck Converter With Integrated MOSFET Check for Samples :TPS54290 TPS54291 TPS54292 FEATURES APPLICATIONS • • • • • • • • 1 2 • • • • • • • • • • • 4.5 V to 18 V Input Range Output Voltage Range 0.8 V to DMAX × VIN Fully Integrated Dual Buck, 1.5 A/2.5 A Three Fixed Switching Frequency Versions: – TPS54290 – 300 kHz – TPS54291 – 600 kHz – TPS54292 – 1.2 MHz Integrated UVLO 0.8 VREF With 1% Accuracy (0°C to 85°C) Internal Soft-Start – TPS54290 – 5.2 ms – TPS54291 – 2.6 ms – TPS54292 – 1.3 ms Dual PWM Outputs 180° Out-of-Phase Dedicated Enable for Each Channel Current Mode Control for Simplified Compensation External Compensation Pulse-by-Pulse Overcurrent Protection, 2.2 A/3.8 A Overcurrent Limit Integrated Bootstrap Switch Thermal Shutdown Protection at 145°C 16-Pin PowerPAD™ HTSSOP Package Set Top Box Digital TV Power for DSP Consumer Electronics DESCRIPTION TPS54290/1/2 is a dual output fully synchronous buck converter capable of supporting applications with a minimal number of external components. It operates from a 4.5 V to 18 V input supply voltage, and supports output voltages as low as 0.8 V and as high as 90% of the input voltage. Both high-side and low-side MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. Channel1 can provide up to 1.5 A of continuous current, meanwhile, Channel2 supports up to 2.5 A. Current mode control simplifies the compensation. The external compensation adds flexibility for the user to choose different type of output capacitors. 180° out-of-phase operation reduces the ripple current through the input capacitor, providing the benefit of reducing input capacitance, alleviating EMI and increasing capacitor life. VIN TPS54290 1 PVDD1 PVDD2 16 2 BOOT1 BOOT2 15 3 SW1 4 PGND1 5 EN1 BP 12 6 EN2 GND 11 7 FB1 FB2 10 8 COMP1 COMP2 GND VOUT2 VOUT1 SW2 14 PGND2 13 9 UDG-09130 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION ORDERABLE DEVICE NUMBER TJ OPERATING FREQUENCY (kHz) TPS54290PWP 300 TPS54290PWPR –40°C to 145°C PACKING MEDIA PACKAGE TPS54291PWP 600 TPS54291PWPR TPS54292PWP 16-Pin HTTSOP 1200 TPS54292PWPR PACKING QUANTITY Tube 90 Tape and Reel 2500 Tube 90 Tape and Reel 2500 Tube 90 Tape and Reel 2500 ABSOLUTE MAXIMUM RATINGS (operating in a typical application circuit) over operating free-air temperature range, all voltages are with respect to GND (unless otherwise noted) VALUE PVDD1, PVDD2, EN1, EN2 UNIT –0.3 to 20 SW1, SW2 –1 to 20 BOOT1, BOOT2 –0.3 to SW+7 SW1, SW2 transient (< 50 ns) V –3 to 20 BP 7 FB1, FB2 –0.3 to 3 Operating junction temperature –40 to 145 Storage junction temperature –55 to 155 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds PACKAGE DISSIPATION RATINGS (1) °C 260 (2) (3) PACKAGE THERMAL IMPEDANCE JUNCTION TO THERMAL PAD TA = 25°C POWER RATING TA = 85°C POWER RATING 16 Pin HTSSOP (PWP) 2.07°/W 1.6 W 1.0 W (1) (2) (3) For more information on the PWP package, refer to TI technical brief (SLMA002A) TI device packages are modeled and tested for thermal performance using PWB designs outlined in JEDEC standards JESD 51-3 and JESD 51-7. For Application information see Power Derating section RECOMMENDED OPERATING CONDITIONS MIN MAX VDD Input voltage 4.5 18 UNIT V TJ Junction temperature –40 125 °C MIN UNIT ELECTROSTATIC DISCHARGE (ESD) PROTECTION PARAMETER Human Body Model CDM 2 Submit Documentation Feedback 2k V 1.5k V Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, PVDD1 and 2 = 12V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY PVDD1, PVDD2 Input voltage range 18 V IDDSDN Shutdown current EN1=EN2 = PVDD2 (4.5-18V) 80 160 µA IDDQ Quiescent, non-switching FB1 = FB2 = 1 V, Outputs Off 1.65 3.00 mA IDDSW Quiescent, while switching FB1 = FB2 = 0.75V, measured at BP UVLO Minimum turn-on voltage PVDD2 only UVLOHYS Hysteresis (1) (2) tstart 4.5 Time from startup to soft start begin 10 3.8 CBP=10µF, EN1 and EN2 go low simultaneously mA 4.1 4.4 V 460 600 mV 1.5 ms ENABLE (ACTIVE LOW) Enable threshold voltage V ENx 0.9 Hysteresis I ENx Enable pull-up current BP Regulator voltage 8 V ≤ VPVDD2 ≤ 18 V BPLDO Dropout voltage VPVDD2 = 4.5 V IBPS Regulator short current 4.5 V ≤ VPVDD2 ≤ 18 V V mV 10 Other enable pin = GND (1) 1.5 70 Time from enable to soft-start begin t ENx 1.2 10 µA µs BP REGULATOR 5.0 5.2 5.6 V 400 mV 25 mA OSCILLATOR fSW Oscillator frequency tDEAD (1) TPS54290 260 300 360 TPS54291 520 600 720 TPS54292 1040 1200 1440 Clock dead time 140 kHz kHz ns gMTRANSCONDUCTANCE AMPLIFIER AND VOLTAGE REFERENCE (Applies to both channels) 0°C < TJ < 85°C 792 800 808 mV –40ºC < TJ < 125°C 786 800 812 mV 5 50 nA 200 325 450 µS 15 30 40 µA 15 30 40 µA TPS54290 0 V ≤ VFB ≤ 0.8 V 4.0 5.2 6.0 TPS54291 2.0 2.6 3.0 TPS54292 1.0 1.3 1.6 1.8 2.2 2.6 3.2 3.8 4.6 VFB Feedback input voltage IFB Feedback Input bias current gM (1) VFB=0.8 V Transconductance ISOURCE Error amplifier source current capability VFB1=VFB2=0.7 V, VCOMP=0 V ISINK Error amplifier sink current capability VFB1=VFB2=0.9 V, VCOMP=2 V SOFT-START (Applies to both channels) tSS Soft-start time ms OVERCURRENT PROTECTION ICL1 Current limit CH1 ICL2 Current limit CH2 THICCUP (1) Hiccup timeout TPS54290 30 TPS54291 16 TPS54292 tONOC (1) (2) (1) Minimum overcurrent pulse A A ms 8 150 200 ns Specified by design. Not tested in production. When both outputs are started simultaneously, a 20-mA current source charges the BP capacitor. Faster times are possible with a lower BP capacitor value. See Input UVLO and Startup. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 3 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, PVDD1 and 2 = 12V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BOOTSTRAP (Applied to both channels) RBOOT Bootstrap switch resistance R(BP to BOOT), I external = 10 mA Ω 33 PGOOD VUV VPG-HYST (3) Feedback voltage limit for PGOOD 660 PGOOD hysteresis voltage on FB 40 730 mV mV OUTPUT STAGE (Applied to both channels) RDS(on1)(HS) (3) On resistance of high-side FET and bondwire on CH1 170 265 mΩ RDS(on2)(HS) (3) On resistance of high-side FET and bondwire on CH2 120 190 mΩ RDS(on1)(LS) (3) On resistance of low-side FET and bondwire on CH1 120 190 RDS(on2)(LS) (3) On resistance of low-side FET and bondwire on CH2 90 150 tON_MIN (3) Miimum controllable pulse width Minimum duty cycle tDEAD (3) VFB = 0.9 V Output driver dead time DMAX 150 Maximum duty cycle mΩ mΩ ns 0% HDRV off to LDRV on 20 ns LDRV off to HDRV on 20 ns TPS54290 90% 96% TPS54291 85% 91% TPS54292 78% 82% THERMAL SHUTDOWN TSD (3) Shutdown temperature TSD_HYS (3) 4 (3) Hysteresis 145 °C 20 °C Specified by design. Not tested in production. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 TYPICAL PERFORMANCE CHARACTERISTICS QUIESCENT CURRENT vs TEMPERATURE SHUTDOWN CURRENT vs TEMPERATURE 1.75 140 Non-Switching 120 ISD – Shutdown Current – mA IDDQ – Quiescent Current – mA 1.70 1.65 1.60 VIN = 18 V 100 80 VIN = 12 V 60 40 1.55 VIN = 4.5 V 20 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 1. Figure 2. UVLO TURN-ON AND TURN-OFF THRESHOLDS vs TEMPERATURE ENx TURN ON AND OFF THRESHOLD vs TEMPERATURE 4.2 1.26 4.1 1.24 VEN – Enable Voltage Threshold – V VUVLO – Undervoltage Lockout Threshold Voltage – V 1.50 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C UVLO ON 1.22 4.0 1.20 3.9 Enable OFF 1.18 3.8 Enable ON 1.16 UVLO OFF 3.7 1.14 3.6 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C 1.12 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 3. Figure 4. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 5 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) SOFT START TIME vs TEMPERATURE OSCILLATOR FREQUENCY vs TEMPERATURE 1.4 6 tSS – Soft-Start Time – ms 4 fSW = 300 kHz fSW = 600 kHz 3 2 fSW – Switching Frequency – MHz 1.2 5 1 fSW = 1.2 MHz fSW = 600 kHz 0.8 0.6 0.4 0.2 fSW = 300 kHz 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C fSW = 1.2 MHz 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 5. Figure 6. FEEDBACK VOLTAGE vs TEMPERATURE CURRENT LIMIT vs TEMPERATURE 808 4.50 806 4.25 804 4.00 IILIMx – Current Limit – A VFB – Feedback Voltage – mV 1.0 Channel2 3.75 802 3.50 800 3.25 798 3.00 796 2.75 794 Channel1 792 2.50 790 2.25 788 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C 2.00 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 7. 6 Figure 8. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 TYPICAL PERFORMANCE CHARACTERISTICS (continued) BP VOLTAGE vs TEMPERARURE SW NODE LEAKAGE CURRENT vs TEMPERATURE 5.20 9 VBP – BP Regulation Voltage – V ISW(off) – Switch-Node Current – mA 8 5.15 5.10 5.05 VVDD = 12 V 5.00 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C 7 6 5 4 3 2 1 0 -1 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 9. Figure 10. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 7 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com DEVICE INFORMATION HTSSOP (PWP) (Top View) PVDD1 1 16 PVDD2 BOOT1 2 15 BOOT2 SW1 3 14 SW2 PGND1 4 13 PGND2 EN1 5 12 BP EN2 6 11 GND FB1 7 COMP1 8 10 FB2 Thermal Pad (bottom side) 9 COMP2 PIN FUNCTIONS PIN NAME NO. BOOT1 2 I/O DESCRIPTION I Input supply to the high-side gate driver for Output1. Connect a 22 nF to 68 nF capacitor from this pin to SW1. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the off time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ω to 5 Ω) may be placed in series with the bootstrap capacitor. BOOT2 15 I Input supply to the high-side gate driver for Output2. Connect a 22 nF to 68 nF capacitor from this pin to SW2. This capacitor is charged from the BP pin voltage through an internal switch. The switch is turned ON during the off time of the converter. To slow down the turn ON of the internal FET, a small resistor (2 Ω to 5 Ω) may be placed in series with the bootstrap capacitor. BP 12 – Regulated voltage to charge the bootstrap capacitors. Bypass this pin to GND with a low-ESR 4.7-µF (10-µF preferred) ceramic capacitor. EN1 5 I Active-low enable input for Output1. If the voltage on this pin is greater than 1.5 V, Output1 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output1 and allow soft start of Output1 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass the enable function. EN2 6 I Active-low enable input for Output2. If the voltage on this pin is greater than 1.5 V, Output2 is disabled (high-side switch is OFF). A voltage of less than 0.9 V enables Output2 and allow soft-start of Output2 to begin. An internal current source drives this pin to PVDD2 if left floating. Connect this pin to GND to bypass the enable function. FB1 7 I FB2 10 I COMP1 8 O COMP2 9 O PGND1 4 – PGND2 13 – Power ground for Outputx. It is separated from GND to prevent the switching noise coupled to the internal logic circuits. GND 11 – Analog ground pin for the device. PVDD1 1 I Power input to the Output1 high-side MOSFET only. This pin should be locally bypassed to PGND1 with a low ESR ceramic capacitor of 10 µF or greater. PVDD1 and PVDD2 could be tied externally together. PVDD2 16 I The PVDD2 pin provides power to the device control circuitry, provides the pull-up for the EN1 and EN2 pins and provides power to the Output2 high-side MOSFET. This pin should be locally bypassed to PGND2 with a low ESR ceramic capacitor of 10 µF or greater. The UVLO function monitors PVDD2 and enables the device when PVDD2 is greater than 4.2 V. SW1 3 O Source (switching) output for Output1 PWM. SW2 14 O Source (switching) output for Output2 PWM. – This pad must be tied externally to a ground plane. Thermal Pad 8 Voltage feedback pin for Outputx. The internal transconductance error amplifier adjusts the PWM for Outputx to regulate the voltage at this pin to the internal 0.8 V reference. A series resistor divider from Outputx to ground, with the center connection tied to this pin, determines the value of the regulated output voltage. Output of the transconductance (gM) amplifier. A R-C compensation network is connected from COMPx to GND. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 BLOCK DIAGRAM BP f(IDRAIN1) + DC(ofst) Current Comparator FET Switch CLK1 + COMP1 8 f(IDRAIN1) FB1 + R R Q 1 PVDD1 IDRAIN1 3 SW1 4 PGND1 BP Overcurrent Comp f(ISLOPE1) Soft Start 1 Q BOOT1 + 7 0.8 VREF S 2 f(IMAX1) CLK1 Anti-Cross Conduction SD1 TSD 10 mA (max) EN1 EN2 10 mA (max) 5 SD1 Internal Control 6 f(ISLOPE1) Ramp Gen 1 SD2 UVLO FB1 FB2 2.4 MHz Oscilator CLK1 Divide by 2/4/8 f(ISLOPE2) Ramp Gen 2 Output Undervoltage Detect CLK2 PVDD2 BP 12 5.25-V Regulator References GND 11 BP 15 BOOT2 f(IDRAIN2) + DC(ofst) Current Comparator 16 PVDD2 FET Switch CLK2 + COMP2 9 f(IDRAIN2) FB2 10 0.8 VREF + Q R R Q IDRAIN2 14 SW2 + BP Overcurrent Comp f(ISLOPE2) Soft Start 2 S f(IMAX2) SD2 CLK2 Anti-Cross Conduction 13 PGND2 FET Switch UDG-09124 Figure 11. Block Diagram Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 9 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com APPLICATION INFORMATION FUNCTIONAL DESCRIPTION The TPS54290/1/2 is a dual output fully synchronous buck converter. Each PWM channel contains an error amplifier, current mode pulse width modulator (PWM), switching and rectifying MOSFETs, enable, and fault protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference, and clock oscillator. VOLTAGE REFERENCE The band gap cell common to both outputs, trimmed to 800 mV. The reference voltage is 1% accurate in the temperature range from 0°C to 85°C. OSCILLATOR The oscillator frequency is internally fixed at 2.4 MHz which is divided by 8/4/2 to generate the ramps for TPS54290/1/2 respectively. The two outputs are internally configured to operate on alternating switch cycles (i.e., 180° out-of-phase). INPUT UVLO AND STARTUP When the voltage at the PVDD2 pin is less than 4.4 V, a portion of the internal bias circuitry is operational, and all other functions are held OFF. All of the internal MOSFETs are also held OFF. When the PVDD2 voltage rises above the UVLO turn on threshold, the state of the enable pins determines the remainder of the internal startup sequence. If either output is enabled (ENx pulled low), the BP regulator turns on, charging the BP capacitor with a 20 mA current. When the BP pin is greater than 4 V, PWM is enabled and soft-start commences. Note that the internal regulator and control circuitry are powered from PVDD2. The voltage on PVDD1 may be higher or lower than PVDD2. ENABLE AND TIMED TURN ON OF THE OUTPUTS Each output has a dedicated (active low) enable pin. If left floating, an internal current source pulls the pin to PVDD2. By grounding, or by pulling the ENx pin to below approximately 1.25 V with an external circuit, the associated output is enabled and soft-start is initiated. If both enable pins are left in the “high” state, the device operates in a shutdown mode, where the BP regulator is shut down and minimal house keeping functions are active. The total standby current from both PVDD pins is 80 µA at 12 V input supply. An R-C connect to an ENx pin may be used to delay the turn on of the associated output after power is applied to PVDDx (see Figure 12). After power is applied to PVDD2, the voltage on the ENx pin slowly decays towards ground. Once the voltage decays to approximately 1.25 V, then the output is enabled and the startup sequence begins. If it is desired to enable the outputs of the device immediately upon the application of power to the PVDD2 pin, then omit these two components and tie the ENx pin to GND directly. If an R-C circuit is used to delay the turn on of the output, the resistor value must be an order of magnitude less than 1.25 V/10 µA or 120 kΩ. A suggested value is 51 kΩ. This allows the ENx voltage to decay below the 1.25 V threshold while the 10-µA bias current flows. The time to start (after the application of PVDD2) is æ VTH - I ´R ö ENx ÷ (s ) tSTART = -R ´ C ´ ln ç ç VIN - 2 ´ Iuuuuur ´ R ÷ ENx è ø ( ) (1) where • • • R and C are the timing components VTH is the 1.25 V enable threshold voltage IEN is the 10-µA maximum enable pin biasing current Figure 12 and Figure 13 illustrate startup delay with an R-C filter on the enable pin(s). 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 X TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 PVDD2 10 mA (max) ENx C + PVDDx R PVDDx 1.25 V 1.25-V Threshold TPS5429x UDG-09125 ENxB VOUTx Time 0 Figure 12. Startup Delay Schematic tDELAY tDELAY + tSS Figure 13. Startup Delay Timing Diagram NOTE If delayed output voltage startup is not necessary, simply connect EN1 and EN2 to GND. This allows the outputs to “start” immediately on the valid application of PVDD2. If ENx is allowed to go “high” after the outputx has been in regulation, the upper and lower MOSFETs shut off, and the output decays at a rate determined by the output capacitor and the load. SOFT START Each output has a dedicated soft start circuit. The soft start voltage is an internal digital reference ramp to one of the two non-inverting inputs of the error amplifier. The other input is the internal precise 0.8-V reference. The total ramp time for the FB voltage to charge from 0 V to 0.8 V is about 5.2 ms, 2.6 ms and 1.3 ms for TPS54190/1/2 respectively. During a soft start interval, the TPS5429x output slowly increases the voltage to the non-inverting input of the error amplifier. In this way, the output voltage slowly ramps up until the voltage on the non-inverting input to the error amplifier reaches the internal 0.8V reference voltage. At that time, the voltage at the non-inverting input to the error amplifier remains at the reference voltage. During the soft-start interval, pulse-by-pulse current limiting is in effect. If an over-current pulse is detected, six PWM pulses is skipped to allow the inductor current to decay before another PWM pulse is applied (See Output Overload Protection). There is no pulse skipping if a current limit pulse is not detected. If the rate of rise of the input voltage (PVDDx) is such that the input voltage is too low to support the desired regulation voltage by the time soft-start has completed, then the output UV circuit may trip and cause a hiccup in the output voltage. In this case, use a timed delay startup from the ENx pin to delay the startup of the output until the PVDDx voltage has the capability of supporting the desired regulation voltage. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 11 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com OUTPUT VOLTAGE REGULATION The regulation output voltage is determined by a resistor divider connecting the output node, the FBx pin, and GND (Figure 14). The value of the output voltage is shown in Equation 2. R1 ö æ VOUT = VREF ´ ç 1 + ÷ (V ) è R2 ø (2) where • VREF is the internal 0.8-V reference voltage TPS54290 1 PVDD1 PVDD2 16 2 BOOT1 BOOT2 15 3 SW1 4 PGND1 5 EN1 BP 12 6 EN2 GND 11 7 FB1 FB2 10 8 COMP1 VOUT1 R1 R2 SW2 14 PGND2 13 COMP2 9 UDG-09131 Figure 14. Feedback Network for Channel1 INDUCTOR SELECTION Equation 3 calculates the inductance value so that the output ripple current falls from 20% to 40% of the full load current. V - V OUT L = IN DIOUT (3) 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 MAXIMUM OUTPUT CAPACITANCE With internal pulse-by-pulse current limiting and a fixed soft-start time, there is a maximum output capacitance which may be used before startup problems begin to occur. If the output capacitance is large enough so that the device enters a current-limit protection mode during startup, then there is a possibility that the output never reaches regulation. Instead, the TPS5429x simply shuts down and attempts a restart as if the output were short-circuited to ground. The maximum output capacitance (including bypass capacitance distributed at the load) is given by C OUT(max) = æ t SS æI öö ´ ç ILIM - ILOAD - ç RIPPLE ÷ ÷ VOUT è 2 è øø (4) where • • tSS is the soft start time ILIM is the current limit level FEEDBACK LOOP COMPENSATION In the feedback signal path, the output voltage setting divider is followed by an internal gM-type error amplifier with a typical transconductance of 325 µS. An external series connected R-C circuit from the gM amplifier output (COMPx pin) to ground serves as the compensation network for the converter. The signal from the error amplifier output is then buffered and combined with a slope compensation signal before it is mirrored to be referenced to the SW node. Here, it is compared with the current feedback signal to create a pulse-width-modulated (PWM) signal-fed to drive the upper MOSFET switch. A simplified equivalent circuit of the signal control path is depicted in Figure 15. NOTE Noise coupling from the SWx node to internal circuitry of BOOTx may impact narrow pulse width operation, especially at load currents less than 1 A. BP ICOMP – ISLOPE Error Amplifier FB 0.8 VREF + PWM to Switch x2 ISLOPE + ICOMP Offset f(IDRAIN) COMP GND 11.5 kW RCOMP CCOMP UDG-09128 Figure 15. Feedback Loop Equivalent Circuit A more conventional small-signal equivalent block diagram is shown in Figure 16. Here, the full closed-loop signal path is shown. Because the TPS5429x contains internal slope compensation, the external L-C filter must be selected appropriately so that the resulting control loop meets criteria for stability. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 13 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com V IN VREF VC + VOUT + Modulator _ _ Filter Current Feedback Network Compensation Network Figure 16. Small Signal Equivalent Block Diagram To determine the components necessary for compensating the feedback loop, the controller frequency response characteristics must be understood and the desired crossover frequency selected. The best results are obtained if 10% of the switching frequency is used as this closed loop crossover frequency. In some cases, up to 20% of the switching frequency is also possible. With the output filter components selected, the next step is to calculate the DC gain of the modulator. For TPS5429x: fSW FM TPS5429x = æ æ (V - VOUT ) ö ö K ´t ç 19.7 ´ e( ON ) + 95 ´ 10 -6 ´ ç IN ÷÷ ÷ ç ç ÷ L è øø è (5) where • • • K = 5.6 ×105 for TPS54290 K = 1.5 × 106 for TPS54291 K = 3.6 × 106 for TPS54292 The overall DC gain of the converter control-to-output transfer function is approximated Equation 6. fC = VIN ´ FM ´ 2 ´ 10 -4 ( æ æ V ´ FM ´ 95 ´ 10 -6 ç ç IN ç1 + ç 2 ´ RLOAD ç ç è è )ö÷ ö÷ ÷÷ ÷÷ øø (6) The next step is to find the desired gain of the error amplifier at the desired crossover frequency. Assuming a single-pole roll-off, us Equation 6 to evaluate the following expression at the desired crossover frequency. æ ö fC ÷ KEA = -20 ´ log ç ç 1 + 2 ´ p ´ fCO ´ (2 ´ RLOAD )´ COUT ÷ è ø (7) ( ) where • 14 ƒCO is the desired crossover frequency Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 TPS54290 VOUT1 ZUPPER C1 (Optional) C2 (Optional) R1 R2 1 PVDD1 PVDD2 16 2 BOOT1 BOOT2 15 3 SW1 4 PGND1 5 EN1 BP 12 6 EN2 GND 11 7 FB1 FB2 10 8 COMP1 SW2 14 PGND2 13 COMP2 9 RCOMP CCOMP ZLOWER UDG-09129 Figure 17. Loop Compensation Network If operating at wide duty cycles (over 50%), a capacitor may be necessary across the upper resistor of the voltage setting divider. If duty cycles are less than 50%, this capacitor may be omitted. L ´ COUT C1 = R1 (8) If a high ESR capacitor is used in the output filter, a zero appears in the loop response that could lead to instability. To compensate, a small capacitor is placed in parallel with the lower voltage setting divider resistor. The value of the capacitor is determined such that a pole is placed at the same frequency as the ESR zero. If low ESR capacitors are used, this capacitor may be omitted. ESR ´ (R1 + R2 ) C2 = COUT ´ (R1´ R2 ) (9) Next, calculate the value of the error amplifier gain setting resistor and capacitor using Equation 10. RCOMP = CCOMP = 10 KEA 20 ´ (ZLOWER + ZUPPER ) gM ´ ZLOWER (10) 1 2 ´ p ´ fPOLE ´ RCOMP (11) where fPOLE = • 1 2 ´ p ´ (2 ´ RLOAD )´ COUT NOTE Once the filter and compensation component values have been established, laboratory measurements of the physical design should be performed to confirm converter stability. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 15 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com BOOTSTRAP FOR N-CHANNEL MOSFET A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to maximum, i.e., 90% for TPS54291, allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and BOOTx) during every cycle. When the PWM switch is commanded to turn ON, the energy used to drive the MOSFET gate is derived from the voltage on this capacitor. Because this is a charge transfer circuit, care must be taken in selecting the value of the bootstrap capacitor. It must be sized such that the energy stored in the capacitor on a per cycle basis is greater than the gate charge requirement of the MOSFET being used. Typically a ceramic capacitor with a value between 22nF and 68nF is selected for the bootstrap capacitor. OUTPUT OVERLOAD PROTECTION In the event of an overcurrent on either output after the output reaches regulation, pulse-by-pulse current limit is in effect for that output. In addition, an output under-voltage (UV) comparator monitors the FBx voltage (which follows the output voltage) to declare a fault if the output drops below 85% of regulation. During this fault condition, both PWM outputs are disabled. This ensures that both outputs discharge to GND, in the event that over-current is on one output while the other is not loaded. The converter enters a hiccup mode timeout before attempting to restart. If an over-current condition exists during soft start, pulse-by-pulse current limiting reduces the pulse width of the affected output’s PWM. In addition, if an overcurrent pulse is detected, six clock cycles are skipped before a next PWM pulse is enabled, effectively dividing the PWM frequency by six and preventing excessive current build up in the indictor. At the end of the soft start time, a UV fault is declared and the operation is the same as described above. The overcurrent threshold for Output1 and Output2 are set nominally 2.2 A and 3.8 A respectively. DESIGN HINT: The OCP Threshold refers to the peak current in the internal switch. Be sure to add the 1/2 of the peak inductor ripple current to the DC load current in determining how close the actual operating point is to the OCP Threshold. OPERATING NEAR MAXIMUM DUTY CYCLE If the TPS5429x is operated at maximum duty cycle, and if the input voltage is insufficient to support the output voltage (at full load or during a load current transient) then there is a possibility that the output voltage falls from regulation and trip the output UV comparator. If this should occur, the TPS5429x protection circuitry declares a fault and enter hiccup mode. DESIGN HINT: Ensure that under ALL conditions of line and load regulation that there is sufficient duty cycle to maintain output voltage regulation. DUAL SUPPLY OPERATION It is possible to operate a TPS5429x from two supply voltages. If this application is desired, then the sequencing of the supplies must be such that PVDD2 is above the UVLO voltage before PVDD1 begins to rise. This is to ensure the internal regulator and the control circuitry is in operation before PVDD1 supplies energy to the output. In addition, Output1 must be held in the disabled state (EN1 high) until there is sufficient voltage on PVDD1 to support Output1 in regulation. (See Operating near Maximum Duty Cycle) The preferred sequence of events follows: 1. PVDD2 rises above the input UVLO voltage 2. PVDD1 rises with Output1 disabled until PVDD1 rises above level to support Output1 regulation With the two conditions above satisfied, there is no restriction on PVDD2 to be greater than, or less than PVDD1. DESIGN HINT: An R-C delay on EN1 may be used to delay the startup of Output1 for a long enough period of time to ensure PVDD1 can support Output1 load. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 OVER-TEMPERATURE PROTECTION AND JUNCTION TEMPERATURE RISE The over temperature thermal protection limits the maximum power to be dissipated at a given operating ambient temperature. In other words, at a given device power dissipation, the maximum ambient operating temperature is limited by the maximum allowable junction operating temperature. The device junction temperature is a function of power dissipation, and the thermal impedance from the junction to the ambient. If the internal die temperature should reach the thermal shutdown level, the TPS5429x shuts off both PWMs and remain in this state until the die temperature drops below 125°C, at which time the device restarts. The first step in determining the device junction temperature is to calculate the power dissipation. The power dissipation is dominated by the two switching MOSFETs and the BP internal regulator. The power dissipated by each MOSFET is composed of conduction losses and switching losses. The total conduction loss in the high side and low side MOSFETs for each channel is given by Equation 12. æ DI 2 ö PD(cond) = RDS(on )HS ´ D + RDS(on)LS ´ (1 - D ) ´ ç IO2 + O ÷ ç 12 ÷ø è ) ( (12) where • • IO is the DC output current, ΔIO is the peak-to-peak ripple current in the inductor Notice the impact of operating duty cycle on the result. The switching loss for each channal is approximated by Equation 13. PD(SW ) = VIN2 ´ C OSS (HS ) + C OSS (LS ) ´ fS 2 ( ) (13) where • • • COSS(HS) is the output capacitance of the high-side MOSFET COSS(LS) is the output capacitance of the low-side MOSFET ƒS is the switching frequency The total power dissipation is found by summing the power loss for both MOSFETs plus the loss in the internal regulator. PD = PD(cond)output1 + PD(SW )output1 + PD(cond)output2 + PD(SW )output2 + VIN ´ Iq (14) The temperature rise of the device junction is dependent on the thermal impedance from junction to the mounting pad (See Package Dissipation Ratings), plus the thermal impedance from the thermal pad to ambient. The thermal impedance from the thermal pad to ambient is dependent on the PCB layout (PowerPAD interface to the PCB, the exposed pad area) and airflow (if any). See PCB Layout Guidelines, Additional References. The operating junction temperature is shown in Equation 15. ( TJ = TA + PD ´ qTH(pkg) + qTH(pad-amb) ) (15) where • θth is the thermal impedance BYPASSING AND FILTERING As with any integrated circuit, supply bypassing is important for jitter free operation. To improve the noise immunity of the converter, ceramic bypass capacitors must be placed as close to the package as possible. • PVDD1 to GND – Use a 10 µF ceramic capacitor • PVDD2 to GND – Use a 10 µF ceramic capacitor • BP to GND – Use a 4.7 µF Ceramic capacitor Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 17 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com POWER DERATING The TPS5429x delivers full current at wide duty cycles at ambient temperatures up to 85°C if the thermal impedance from the thermal pad is sufficient to maintain the junction temperature below the thermal shut down level. At higher ambient temperatures, the device power dissipation must be reduced to maintain the junction temperature at or below the thermal shutdown level. Figure 18 illustrates the power derating for elevated ambient temperature under various air flow conditions. Note that these curves assume the PowerPAD is soldered to the recommended thermal pad. See References for further information. 1.8 LFM = 250 1.6 LFM = 500 PD – Power Dissipation – W 1.4 LFM = 0 1.2 LFM = 150 1.0 0.8 0.6 LFM 0 150 250 500 0.4 0.2 0 0 20 40 60 80 100 120 TA – Ambient Temperature – °C 140 Figure 18. Power Derating Curves PowerPAD PACKAGE The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD package. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. (See Additional References) 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 LAYOUT RECOMMENDATIONS • • • • • • • • • • The PowerPad must be connected to the low-current ground with available surface copper to dissipate heat. Extending ground land beyond the device package area between PVDD1 (pin 1) and PVDD2 (pin 16) and between COMP1 (pin 8) and COMP2( pin 9) is recommended.. Connect PGND1 and PGND2 to the PowerPad through a 10-mil wide trace. Place the ceramic input capacitors near PVDD1 and PVDD2 and bypass to PGND1 and PGND2 respectively. Locate the inductor near the SW1 or SW2 pin. Connect the output capacitor grounds to PGND1 or PGND2 with wide, tight loops. Use a wide ground connection from input capacitor PGND1 or PGND2 as close to power path as possible. It is recommend they be placed directly underneath. Locate the bootstrap capacitor near the BOOT pin to minimize gate drive loop. Locate the feedback and compensation components far from switch node and input capacitor ground connection. Locate the snubber components from SW1 or SW2 to PGND1 or PGND2 close to the device, minimizing the loop area. Locate the BP bypass capacitor very close to device and bypass to PowerPad. Locate output ceramic capacitor close to inductor output terminal and between inductor and electrolytic capacitors if used. Figure 19. Top Layer Figure 20. Bottom Layer Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 19 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com DESIGN EXAMPLES Design Example 1 The following example illustrates the design process and component selection for a 12-V to 5-V and 3.3-V dual non-synchronous buck regulator using the TPS54291 converter. A definition of symbols used can be found in Table 1 of the appendix Table 1. Design Example Electrical Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 8 12 14 V 12 20 mA 4.2 4.4 V INPUT CHARACTERSTICS VIN Input voltage IIN Input current VIN = Nom, IOUT = Max No load input current VIN = Nom, IOUT = 0 A Input UVLO IOUT = Min to Max VIN(UVLO) A 4 OUTPUT CHARACTERSTICS VOUT1 Output voltage 1 VIN = Nom, IOUT = Nom 3.2 3.3 3.4 V VOUT2 Output voltage 2 VIN = Nom, IOUT = Nom 1.15 1.20 1.25 V Line regulation VIN = Min to Max 1% Load regulation IOUT = Min to Max 1% VOUT1(ripple) Output1 voltage Ripple VIN = Nom, IOUT1 = Max VOUT2(ripple) Output2 voltage Ripple VIN = Nom, IOUT2 = Max IOUT1 Output current 1 VIN = Min to Max 0 IOUT2 Output current 2 VIN = Min to Max 0 2.5 A IOCP1 Output overcurrent Channel 1 VIN = Nom, VOUT = (VOUT1 – 5%) 1.8 2.2 2.6 A IOCP2 Output overcurrent Channel 2 VIN = Nom, VOUT = (VOUT2 – 5%) 3.2 3.8 4.6 A 50 mVPP 24 mVPP 1.5 A TRANSIENT RESPONSE ΔVOUT Change from load transient ΔIOUT = 1 A @ 3 µA/s Settling time to 1% of VOUT 200 mV 1 ms SYSTEMS CHARACTERSTICS f SW Switching frequency ηPEAK Peak efficiency VIN = Nom η Full load efficiency VIN = Nom, IOUT = Max TOP Operating temperature range VIN = Min to Max, IOUT = Min to Max 20 500 Submit Documentation Feedback 600 700 kHz 60 °C 90% 80% 0 25 Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 The list of materials for this application is shown below in Table 2. The efficiency, line regulation and load regulation from printed circuit boards built using this design are shown in Figure 23 and Figure 24. Figure 21. TPS54291 Design Example 1 Schematic Step by Step Design Procedure Duty Cycle Estimation The duty cycle of the main switching FET is estimated by Equation 16 and Equation 17. DMAX1 » VOUT VOUT 3.3 1.2 = = 0.413 ¾¾® DMAX2 » = = 0.15 VIN(min ) 8.0 VIN(min ) 8.0 (16) VOUT VOUT 3.3 1.2 DMIN1 » = = 0.236 ¾¾® DMIN2 » = = 0.086 VIN(max ) 14 VIN(max ) 14 (17) Inductor Selection The peak to peak ripple should be limited to between 20% and 30% of the maximum output current. ILrip1(max ) = 0.30 ´ IOUT(max ) = 0.3 ´ 1.5 A = 0.450 A ILrip2(max ) = 0.30 ´ IOUT(max ) = 0.3 ´ 2.5 A = 0.750 A (19) The minimum inductor size can be estimated by Equation 20 and Equation 21. VIN(max ) - VOUT 1 14 - 3.3 1 ´ DMIN ´ = ´ 0.236 ´ = 9.35 mH LMIN1 » ILRIP(max ) 0.45 A 600kHz fSW L MIN2 » VIN(max ) - VOUT ILRIP (max ) ´ DMIN ´ (18) 1 14 - 1.2 1 = ´ 0.086 ´ = 2.45 mH 0.75 A 600 kHz fSW (20) (21) The standard inductor values of 8.2 µH and 3.3 µH are selected for Channel 1 and Channel 2 respectively. The actual ripple currents are estimated by Equation 22 and Equation 23. Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 21 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 IRIPPLE1 » IRIPPLE2 » www.ti.com VIN(max ) - VOUT L1 VIN(max ) - VOUT L2 ´ DMIN ´ ´ DMIN ´ 1 fSW 1 fSW = = 14 - 3.3 1 ´ 0.236 ´ = 0.513 A 8.2 mH 600kHz (22) 14 - 1.2 1 ´ 0.086 ´ = 0.556A 3.3 mH 600kHz (23) The RMS current through the inductor is approximated by Equation 24 and Equation 25. IL(rms ) = IL(avg)2 + 2 1 I 12 RIPPLE » IOUT(max )2 + 2 1 I 12 RIPPLE = (1.5 )2 + 112 (0.513 )2 A = 1.51A IL(rms ) = IL(avg)2 + 2 1 I 12 RIPPLE » IOUT(max )2 + 2 1 I 12 RIPPLE = (2.5 )2 + 112 (0.556 )2 A = 2.51A (24) (25) A DC current with 30% peak-to-peak ripple has an RMS current approximately 0.4% above the average current. The peak inductor current is estimated by Equation 26 and Equation 27. IL(peak ) » IOUT(max ) + 12 IRIPPLE = 1.5 A + 12 0.513A = 1.76 A 1 (26) 1 IL(peak ) » IOUT(max ) + 2 IRIPPLE = 2.5 A + 2 0.556A = 2.78 A (27) A 8.2-µH inductor with a minimum RMS current rating of 1.51 A and minimum saturation current rating of 3.7 A must be selected. A Coilcraft MSS1048-822ML 8.2-µH, 4.38-A inductor is chosen for Channel 1 and a Coilcraft MSS1048-332 3.3-µH inductor is chosen for Channel 2. Output Capacitor Selection Output capacitors are selected to support load transients and output ripple current. The minimum output capacitance to meet the transient specification is given by Equation 28 and Equation 29. COUT1(min ) = ITRAN(max )2 ´ L (VOUT )´ VOVER = 2 C OUT2(min ) = ITRAN(max ) ´ L (VOUT )´ VOVER = 1A 2 ´ 8.2 mH = 12.4 mF 3.3 V ´ 0.2 V (28) 1A 2 ´ 3.3 mH = 13.7 mF 1.2 V ´ 0.2 V (29) The maximum ESR to meet the ripple specification is given by Equation 30 and Equation 31. æ ö IRIPPLE æ ö 0.513 A VRIPPLE(total) - ç ÷ 0.050 V - ç ÷ f ´ ´ 8 C OUT SW ø è è 8 ´ 12.4 mF ´ 600kHz ø = 0.081W = ESRMAX = IRIPPLE 0.513 A (30) æ ö IRIPPLE æ ö 0.556 A VRIPPLE(total) - ç ÷ 0.024 V - ç ÷ è 8 ´ COUT ´ fSW ø = è 8 ´ 13.7 mF ´ 600kHz ø = 0.028 W ESRMAX = IRIPPLE 0.556 A (31) A single 22-µF ceramic capacitor with approximately 2.5 mΩ of ESR is selected to provide sufficient margin for capacitance loss due to DC voltage bias. Input Capacitor Selection A minimum 10-µF ceramic input capacitor on each PVDD pin is recommended. The ceramic capacitor must handle the RMS ripple current in the input capacitor. The RMS current in the input capacitors is estimated by Equation 32 and Equation 33. 22 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 IRMS(CIN1) = IOUT1 ´ D1 ´ (1 - D1 ) = 1.5 A ´ 0.413 ´ (1 - 0.413 ) = 0.74 A (32) IRMS(CIN2 ) = IOUT1 ´ D2 ´ (1 - D2 ) = 2.5 A ´ 0.15 ´ (1 - 0.15 ) = 0.89 A (33) One 1210 10-µF, 25-V, X5R, ceramic capacitor with 2-mΩ ESR and a 2-A RMS current rating are selected for each PVDD input. Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to ensure the capacitors will have sufficient capacitance at the working voltage. Feedback The primary feedback divider resistor (RFB) from VOUT to FB should be selected between 10-kΩ and 100-kΩ to maintain a balance between power dissipation and noise sensitivity. For a 3.3-V and 5-V output, 20.5 kΩ is selected and the lower resistor is given by Equation 34. V ´ RFB RBIAS = FB VOUT - VFB (34) For RFB = 20.5kΩ and VFB = 0.80 V, RBIAS = 6.56 kΩ and 41.0 kΩ (6.49 kΩ and 40.2 kΩ selected) for 3.3 V and 1.2 V respectively. It is common to select the next lower available resistor value for the bias resistor. This biases the nominal output voltage slightly higher, allowing additional tolerance for load regulation. Compensation Components The TPS54291 controller uses a transconductance error amplifier, which is compensated with a series capacitor and resistor to ground plus a high-frequency capacitor to reduce the gain at high frequency. To select the component, the following equations define the control loop and power stage gain and transfer function: FMTPS5429x = fSW é (K´tON ) + 95 ´ 10-6 ´ æ VIN - VOUT ö ù ê19.7 ´ e ç ÷ú L è øû ë = 600kHz = 3762 6 é 1.5 10 393ns ´ ´ ( ) -6 æ 14 - 3.3 ö ù + 95 ´ 10 ´ ç ê19.7 ´ e ÷ú è 8.2 mH ø ûú ëê (35) where • • • K = 5.6 × 105 for TPS54290 K = 1.5 × 106 for TPS54291 K = 3.6 × 106 for TPS54292 The overall DC gain of the converter control-to-output transfer function is approximated by Equation 36. fC = VIN ´ FM ´ 2 ´ 10-4 é æ V ´ FM ´ 95 ´ 10-6 ê1 + ç IN ç 2 ´ RLOAD ëê è öù ÷ú ÷ú øû = 14 V ´ 3762 ´ 2 ´ 10-4 é æ 14 V ´ 3762 ´ 95 ´ 10-6 ê1 + ç 4.4 W êë çè öù ÷ú ÷ú øû = 4.293 (36) With the power stage DC gain, it is possible to estimate the required mid-band gain to program a desired cross-over frequency. æ ö fC æ ö 3.22 KEA = -20 ´ log ç ÷ = -20 ´ log ç ÷ = 11.83 dB ç 1 + 2 ´ p ´ fCO ´ (2 ´ RLOAD )´ COUT ÷ 1 2 30kHz 4.4 22 F + ´ p ´ ´ W ´ m è ø è ø (37) Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 23 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com Compensation Gain Setting Resistor RCOMP programs the mid-band error amplifier gain to set the desired cross-over frequency in Equation 38. RCOMP = 10 KEA 20 ´ (ZLOWER + ZUPPER ) 10 = gM ´ ZLOWER 11.83dB 20 ´ (6.49kW + 20.5kW) = 50.42kW » 53.6kW 325 mS ´ 6.49kW (38) Compensation Integrator Capacitor An integrator capacitor provides maximum DC gain for the best possible DC regulation while programming the compensation zero to match the natural pole of the output filter. CCOMP is selected by Equation 40. 1 1 fPOLE = = = 1.644kHz 2 ´ p ´ RLOAD ´ COUT 2 ´ p ´ 4.4 W ´ 22 mF (39) CCOMP = 1 = 2 ´ p ´ fPOLE ´ RCOMP 1 = 1.80nF 2 ´ p ´ 1.644kHz ´ 53.6kW (40) Bootstap Capacitor To ensure proper charging of the high-side FET gate and limit the ripple voltage on the boost capacitor, a 47-nF boot strap capacitor is recommended. Power Dissipation The power dissipation in the TPS54291 is made from FET conduction losses, switching losses and regulator losses. Conduction losses are estimated by Equation 41 and Equation 42. ) ( 2 ö = 150mW ´ 0.413 + 100mW ´ 0.587 ´ 1.51 2 = 0.275 W PCON1 = RDS(on )HS ´ D1 + RDS(on )LS ´ (1 - D1 ) ´ æç I ( ) ( ) ÷ è SW 1(RMS ) ø (41) ) ( 2 ö = 105mW ´ 0.15 + 75mW ´ 0.85 ´ 2.51 2 = 0.501W PCON2 = RDS(on )HS ´ D1 + RDS(on )LS ´ (1 - D1 ) ´ æç I ( ) ( ) ÷ SW 1 RMS ( ) è ø (42) The switching losses are estimated by Equation 43 and Equation 44. PSW1 » VIN(max )2 ´ (COSS(HS) + COSS(LS) ) ´ fSW 2 = 2 PSW 2 » VIN(max ) ´ (COSS(HS ) + COSS(LS ) ) ´ fSW 2 = 142 ´ (140pF + 200pF) ´ 600kHz = 20mW 2 (43) 142 ´ (200pF + 280pF) ´ 600kHz = 28mW 2 (44) The regulator losses are estimated by Equation 45. ( ) PREG » IDD ´ VIN(max ) + IBP ´ VIN(max ) - VBP = 10mA ´ 14 V = 140mW (45) Total power dissipation in the device is the sum of conduction losses and switching losses for both channels plus regulator losses, which is estimated to be 1.01 W. 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 Design Example Test Results Figure 22. TPS54291 Design Example Switching Waveforms 90 100 VIN = 8 V 85 VIN = 8 V 95 90 80 h – Efficiency – % h – Efficiency – % 85 VIN = 12 V 75 70 VIN = 14 V 65 VIN = 14 V 80 75 VIN = 12 V 70 65 60 60 55 VOUT = 1.2 V 50 55 VOUT = 3.3 V 50 0 0.5 1.0 1.5 2.0 ILOAD – Load Current – A Figure 23. Design Efficiency for 1.2-V Output 2.5 0 0.3 0.6 0.9 1.2 ILOAD – Load Current – A 1.5 Figure 24. Design Efficiency for 3.3-V Output Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 25 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com Table 2. Design Example List of Materials REFERENCE DESIGNATOR QTY VALUE DESCRIPTION SIZE PART NUMBER MFR C12 1 4.7 µF Capacitor, Ceramic, 10 V, X5R, 20% 0805 Std C2, C14 2 22 µF Capacitor, Ceramic, 6.3 V, X5R, 20% 1206 C3216X5R0J226M TDK Std C3, C13 2 470 pF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std C4, C11 2 0.047 µF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std TDK C5, C10 2 10 µF Capacitor, Ceramic, 25 V, X5R, 20% 1210 C3225X5R1E106 M C6 2 1.8 nF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std C7 1 15 pF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std C8 1 47 pF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std C9 1 1.2 nF Capacitor, Ceramic, 25 V, X7R, 20% 0603 Std Std L1 1 8.2 µH Inductor, SMT, 4.38 A, 20 mΩ 0.402 x 0.394 inch MSS1048-822L Coilcraft L2 1 3.3 µH Inductor, SMT, 5.04 A, 10 mΩ 0.402 x 0.394 inch MSS1048-332L Coilcraft R10 1 40.2 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std R2, R11 2 10 Ω Resistor, Chip, 1/16W, 5% 0603 Std Std R3, R12 2 20.5 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std R4 1 6.49 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std R6 1 7.87 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std R7 1 4.64 kΩ Resistor, Chip, 1/16W, 1% 0603 Std Std 1 2.5 A/1.5 A, Dual Output Fully Synchronous Buck 600 Hz Converter w/Integrated FET CSP TPS54291PWP TI U1 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 TPS54290, TPS54291, TPS54292 www.ti.com SLUS973 – OCTOBER 2009 Design Example 2 (Cascading Operation) TPS5429x can be configured as cascaded operation as shown in Figure 25. The 12-V input supply is applied to PVDD2 and the the channel 2 output is tied to PVDD1. The channel 2 output is 3.3 V and capable of supporting 1.5 A to the load while generating power for the 1.2-V input for channel 1. + + [email protected] [email protected] + + Figure 25. Cascading Operation Design Example 2 Test Results For Figure 26, Ch1: 12-V supply; Ch2: VOUT1 (1.2 V); Ch3: VOUT2(3.3 V). For Figure 27, Ch1: Channel 1 SW node; Ch2: Channel 1 output ripple Ch3: Channel 2 output ripple; Ch2: Channel 2 SW node. Figure 26. Start-Up Waveforms Figure 27. Output Ripple and SW Nodes Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 Submit Documentation Feedback 27 TPS54290, TPS54291, TPS54292 SLUS973 – OCTOBER 2009 www.ti.com ADDITIONAL REFERENCES RELATED DEVICES The following devices have characteristics similar to the TPS54290/1/2 and may be of interest. DEVICE DESCRIPTION TPS40222 5-V input, 1.5-A, Non-Synchronous Buck Converter TPS54283/TPS54286 2-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE FET TPS55383/TPS55386 3-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE FET REFERENCES These references, design tools and links to additional references, including design software, may be found at www.power.ti.com. 1. Additional PowerPAD™ information may be found in Applications Briefs (SLMA002A) and (SLMA004). 2. Under The Hood Of Low Voltage DC/DC Converters – SEM1500 Topic 5 – 2002 Seminar Series 3. Understanding Buck Power Stages in Switchmode Power Supplies, (SLVA057), March 1999 4. Designing Stable Control Loops – SEM 1400 – 2001 Seminar Series Package Outline and Recommended PCB Footprint The following pages outline the mechanical dimensions of the 16-pin PWP package and provide recommendations for PCB layout. 28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :TPS54290 TPS54291 TPS54292 PACKAGE OPTION ADDENDUM www.ti.com 20-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS54290PWP ACTIVE HTSSOP PWP 16 TPS54290PWPR ACTIVE HTSSOP PWP 16 TPS54291PWP ACTIVE HTSSOP PWP 16 TPS54291PWPR ACTIVE HTSSOP PWP 16 TPS54292PWP ACTIVE HTSSOP PWP 16 TPS54292PWPR ACTIVE HTSSOP PWP 16 90 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 90 90 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS54290PWPR HTSSOP PWP 16 2000 330.0 12.4 TPS54292PWPR HTSSOP PWP 16 2000 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54290PWPR HTSSOP PWP 16 2000 346.0 346.0 29.0 TPS54292PWPR HTSSOP PWP 16 2000 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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