BB TSC2004IYZKT

 TS
C20
04
TSC2004
®
SBAS408A – JUNE 2007 – REVISED AUGUST 2007
1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire
TOUCH SCREEN CONTROLLER with I2C™ Interface
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4-Wire Touch Screen Interface
Ratiometric Conversion
Single 1.2V to 3.6V Supply
Preprocessing to Reduce Bus Activity
High-Speed I2C-Compatible Interface
Internal Detection of Screen Touch
Register-Based Programmable:
– 10-Bit or 12-Bit Resolution
– Sampling Rates
– System Timing
On-Chip Temperature Measurement
Touch Pressure Measurement
Auto Power-Down Control
Low Power:
– 760μW at 1.8V, 50SSPS
– 580μW at 1.6V, 50SSPS
– 285μW at 1.2V, 50SSPS
– 74μW at 1.6V, 8.2kSPS Eq. Rate
– 47μW at 1.2V, 8.2kSPS Eq. Rate
Enhanced ESD Protection:
– ±6kV HBM
– ±1kV CDM
– Target ±18kV Air Gap Discharge
– Target ±12kV Contact Discharge
2.5 x 2.5 WCSP-18 and 4 x 4 QFN-20 Packages
U.S. Patent NO. 6246394; other patents pending.
Cellular Phones
Portable Instruments
MP3 Players, Pagers
Multiscreen Touch Control
DESCRIPTION
The TSC2004 is a very low-power touch screen
controller designed to work with power-sensitive,
handheld applications that are based on an
advanced low-voltage processor. It works with a
supply voltage as low as 1.2V, which can be
supplied by a single-cell battery. It contains a
complete, ultra-low power, 12-bit, analog-to-digital
(A/D) resistive touch screen converter, including
drivers and the control logic to measure touch
pressure.
In addition to these standard features, the TSC2004
offers preprocessing of the touch screen
measurements to reduce bus loading, thus reducing
the consumption of host processor resources that
can then be redirected to more critical functions.
The TSC2004 supports an I2C serial bus and data
transmission protocol in all three defined modes:
standard,
fast,
and
high-speed.
It
offers
programmable resolution of 10 or 12 bits to
accommodate
different
screen
sizes
and
performance needs.
The TSC2004 is available in a miniature, 18-lead,
5 x 5 array, (2.554 ±0.54)mm x (2.554 ±0.54)mm
wafer chip-scale package (WCSP), and a 20-pin, 4 x
4 QFN package. Both packages are characterized
for the –40°C to +85°C industrial temperature range.
PENIRQ
VREF
Touch
Screen
Drivers
Interface
Mux
SAR
ADC
TEMP
AUX
Internal
Clock
Pre-Processing
X+
XY+
Y-
DAV
PINTDAV
SCL
I2C
Serial
Interface
and
Control
SDA
AD0
AD1
RESET
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TSC2004
www.ti.com
SBAS408A – JUNE 2007 – REVISED AUGUST 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
PRODUCT
TSC2004
(1)
TYPICAL
INTEGRAL
LINEARITY
(LSB)
–0.8 to +1.4
TYPICAL
GAIN
ERROR
(LSB)
NO MISSING
CODES
RESOLUTION
(BITS)
+0.1
PACKAGE
TYPE
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
20-Pin,
0.8 x 4 x 4
Thin QFN
RTJ
–40°C to +85°C
TSC2004I
18-Pin,
5 x 5 Matrix,
2.5 x 2.5
WCSP
YZK
ORDERING
NUMBER
TSC2004IRTJT
Small Tape
and Reel, 250
TSC2004IRTJR
Tape and
Reel, 2500
TSC2004IYZKT
Small Tape
and Reel, 250
TSC2004IYZKR
Tape and
Reel, 2500
11
–40°C to +85°C
TRANSPORT
MEDIA,
QUANTITY
TSC2004I
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see
the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted)
TSC2004
UNIT
Analog input X+, Y+, AUX to SNSGND
–0.4 to SNSVDD + 0.1
V
Analog input X–, Y– to SNSGND
–0.4 to SNSVDD + 0.1
V
SNSVDD to SNSGND
–0.3 to 5
V
SNSVDD to AGND
–0.3 to 5
V
I/OVDD to DGND
–0.3 to 5
V
–2.40 to +0.3
V
Digital input voltage to DGND
–0.3 to I/OVDD + 0.3
V
Digital output voltage to DGND
–0.3 to I/OVDD + 0.3
V
Voltage range
SNSVDD to I/OVDD
Power dissipation
(TJ Max - TA)/θJA
WCSP package
Low-K
°C/W
62
°C/W
39.97
°C/W
Operating free-air temperature range, TA
–40 to +85
°C
Storage temperature range, TSTG
–65 to +150
°C
+150
°C
Vapor phase (60 sec)
+215
°C
Infrared (15 sec)
+220
°C
X+, X–, Y+, Y–
±12
kV
X+, X–, Y+, Y–
±25
kV
Thermal impedance, θJA
High-K
QFN package
Junction temperature, TJ Max
Lead temperature
IEC contact discharge
IEC air discharge (2)
(1)
(2)
2
113
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum rated conditions for extended periods may affect device reliability.
Test method based on IEC standard 61000-4-2. Contact Texas Instruments for test details.
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SBAS408A – JUNE 2007 – REVISED AUGUST 2007
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, SNSVDD = VREF = +1.2V to +3.6V, I/OVDD (1) = +1.2V to +3.6V, unless otherwise noted.
TSC2004
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUXILIARY ANALOG INPUT
Input voltage range
0
Input capacitance
VREF
12
Input leakage current
–1
V
pF
+1
μA
12
Bits
A/D CONVERTER
Resolution
Programmable: 10 or 12 bits
No missing codes
12-bit resolution
11
Integral linearity
Differential linearity
Offset error
Gain error
SNSVDD = 1.6V, VREF = 1.6V,
High-Speed mode, filter off
TSC2004IRTJ
SNSVDD = 1.6V, VREF = 1.6V,
High-Speed mode, filter off
TSC2004IRTJ
Bits
–4
–0.8 to +1.4
+4
LSB (2)
–2
–0.6 to +0.7
+4
LSB
0
2.2
5
LSB
TSC2004IYZK
2.2
–3
TSC2004IYZK
0.1
LSB
+3
0.1
LSB
REFERENCE INPUT
VREF range
1.2
VREF input current drain
Non-cont. AUX mode, SNSVDD = VREF = 1.6V,
TA = +25°C, fADC = 2MHz, High-Speed mode
Input impedance
A/D converter not converting
SNSVDD
V
1.2
μA
1
GΩ
TA = +25°C, SNSVDD = VREF = 1.6V
47
kΩ
Y+, X+
TA = +25°C, SNSVDD = VREF = 1.6V
6
Ω
Y–, X–
TA = +25°C, SNSVDD = VREF = 1.6V
5
Ω
TOUCH SENSORS
PENIRQ Pull-Up Resistor,
RIRQ
Switch
OnResistance
Switch drivers drive current
(3)
100ms duration
50
mA
INTERNAL TEMPERATURE SENSOR
Temperature range
–40
Differential method (4)
Resolution
TEMP1 (5)
Differential method (4)
Accuracy
TEMP1 (5)
+85
°C
SNSVDD = 1.6V
0.3
°C/LSB
SNSVDD = 3V
1.6
°C/LSB
SNSVDD = 1.6V
0.3
°C/LSB
SNSVDD = 3V
1.6
°C/LSB
SNSVDD = 1.6V
±3
°C/LSB
SNSVDD = 3V
±2
°C/LSB
SNSVDD = 1.6V
±3
°C/LSB
SNSVDD = 3V
±2
°C/LSB
INTERNAL OSCILLATOR
SNSVDD = 1.2V, TA = +25°C
Clock frequency, fOSC
SNSVDD = 1.6V
3.3
3.6
SNSVDD = 3.0V, TA = +25°C
Frequency drift
(1)
(2)
(3)
(4)
(5)
3.9
MHz
4.3
MHz
4.1
MHz
SNSVDD = 1.2V
0.118
%/°C
SNSVDD = 1.6V
–0.018
%/°C
SNSVDD = 3.0V
–0.032
%/°C
I/OVDD must be ≤ SNSVDD.
LSB means Least Significant Bit. With VREF = +2.5V, one LSB is 610μV.
Assured by design, but not tested. Exceeding 50mA source current may result in device degradation.
Difference between TEMP1 and TEMP2 measurement; no calibration necessary.
Temperature drift is –2.1mV/°C.
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TSC2004
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SBAS408A – JUNE 2007 – REVISED AUGUST 2007
ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +85°C, SNSVDD = VREF = +1.2V to +3.6V, I/OVDD = +1.2V to +3.6V, unless otherwise noted.
TSC2004
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
Logic family
CMOS
VIH
VIL
Logic level
1.2V ≤ I/OVDD < 1.6V
0.7 × I/OVDD
I/OVDD + 0.3
V
1.6V ≤ I/OVDD ≤ 3.6V
0.7 × I/OVDD
I/OVDD + 0.3
V
1.2V ≤ I/OVDD < 1.6V
–0.3
0.2 × I/OVDD
V
1.6V ≤ I/OVDD ≤ 3.6V
–0.3
0.3 × I/OVDD
V
–1
1
μA
IIL
SCL and SDA pins
CIN
SCL and SDA pins
10
pF
VOH
IOH = 2 TTL loads
I/OVDD – 0.2
I/OVDD
V
VOL
IOL = 2 TTL loads
0
0.2
V
ILEAK
Floating output
–1
1
μA
COUT
Floating output
10
pF
1.2
3.6
V
1.2
SNSVDD
V
Data format
Straight Binary
POWER-SUPPLY REQUIREMENTS
Power-supply voltage
SNSVDD
Specified performance
I/OVDD (6)
TA = +25°C, filter on, M = 15,
W = 7, PSM = 1, C[3:0] =
(0,0,0,0), RM = 1, CL[1:0] =
(0,1), BTD[2:0] = (1,0,1),
50SSPS, MAVEX = MAVEY =
MAVEZ = 1, fADC = 2MHz,
High-Speed mode, sensor
drivers supply included
SNSVDD = I/OVDD = VREF = 1.2V
237
μA
364
μA
797
μA
237
μA
342
μA
757
μA
SNSVDD = I/OVDD = VREF = 1.2V
176
μA
SNSVDD = I/OVDD = VREF = 1.6V
268
μA
SNSVDD = I/OVDD = VREF = 3.0V
526
μA
SNSVDD = I/OVDD = VREF = 1.2V,
~10.3kSPS effective rate
347
μA
SNSVDD = I/OVDD = VREF = 1.6V,
~11.8kSPS effective rate
468
μA
SNSVDD = I/OVDD = VREF = 3.0V,
~12.3kSPS effective rate
897
μA
SNSVDD = I/OVDD = VREF = 1.2V,
~1.17kSPS effective rate
39.4
μA
SNSVDD = I/OVDD = VREF = 1.6V,
~1.17kSPS effective rate
46.4
μA
SNSVDD = I/OVDD = VREF = 3.0V,
~1.17kSPS effective rate
85.3
μA
x
SNSVDD = I/OVDD = VREF = 1.6V
x
SNSVDD = I/OVDD = VREF = 3.0V
TA = +25°C, filter off, M = W = SNSVDD = I/OVDD = VREF = 1.2V
1, PSM = 1, C[3:0] = (0,0,0,0), x
RM = 1, CL[1:0] = (0,1),
SNSVDD = I/OVDD = VREF = 1.6V
BTD[2:0] = (1,0,1), 50SSPS,
x
MAVEX = MAVEY = MAVEZ =
1, fADC = 2MHz, High-Speed
mode, sensor drivers supply
SNSVDD = I/OVDD = VREF = 3.0V
included
Quiescent supply current (7) (8)
TA = +25°C, filter off, M = W =
1, C[3:0] = (0,1,0,1), RM = 1,
CL[1:0] = (0,1), non-cont AUX
mode, fADC = 2MHz,
High-Speed mode
TA = +25°C, filter on, M = 7, W
= 3, C[3:0] = (0,1,0,1), RM = 1,
CL[1:0] = (0,1), MAVEAUX =
1, non-cont AUX mode, fADC =
2MHz, High-Speed mode, full
speed
TA = +25°C, filter on, M = 7, W
= 3, C[3:0] = (0,1,0,1), RM = 1,
CL[1:0] = (0,1), MAVEAUX =
1, non-cont AUX mode, fADC =
2MHz, High-Speed mode,
reduced speed (8.2kSPS
equivalent rate)
Power down supply current
(6)
(7)
(8)
4
Not addressed, SCL =SDA = 1
I/OVDD must be ≤ SNSVDD.
Supply current from SNSVDD.
For detailed information on test condition parameter and bit settings, see the Digital Interface section.
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0
0.8
μA
TSC2004
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SBAS408A – JUNE 2007 – REVISED AUGUST 2007
PIN CONFIGURATION
RTJ PACKAGE(1)
QFN-20
(TOP VIEW)
SUBGND
Y+
X+
SNSVDD
VREF
YZK PACKAGE
WCSP-18
(TOP VIEW, SOLDER BUMPS ON BOTTOM SIDE)
15
14
13
12
11
AGND
VREF
AUX
NC
I/OVDD
NC
DGND
AD1
SNSVDD
X+
Y+
SUBGND
X-
NC
NC
Y-
NC
NC
SNSGND
SCL
SDA
AD0
C
D
E
5
4
16
10
AGND
Y-
17
9
AUX
SNSGND
18
8
NC
NC
19
7
I/OVDD
AD0
20
6
DGND
TSC2004
Thermal Pad
Rows
X-
3
2
PINTDAV RESET
1
(1)
5
A
RESET
4
PINTDAV
3
AD1
2
SCL
SDA
1
B
Columns
(FRONT VIEW)
The thermal pad is internally connected to
SUBGND. The thermal pad can be
connected to the analog ground or left
floating. Keep the thermal pad separate
from the digital ground, if possible.
PIN ASSIGNMENTS
PIN NO.
QFN
WCSP
PIN
NAME
I/O
A/D
DESCRIPTION
1
D1
SDA
I/O
D
Serial data I/O
2
C1
SCL
I
D
Serial clock.
3
B2
AD1
I
D
Address input bit 1
4
A1
PINTDAV
O
D
Interrupt output. Data available or PENIRQ, depending on setting. Pin polarity with active low.
5
B1
RESET
I
D
System reset. All register values reset to default values.
6
A2
DGND
Digital ground
7
A3
I/OVDD
Digital I/O interface voltage
8, 19
B3, B4,
C2, C3,
D2, D3
NC
9
A4
AUX
10
A5
AGND
11
B5
VREF
12
C5
SNSVDD
13
D5
14
No internal connection, but solder bumps are populated. These pins may be connected to analog ground
for mechanical stability.
I
A
Auxiliary channel input
I
A
X+
I
A
X+ channel input
E5
Y+
I
A
Y+ channel input
15
D4
SUBGND
16
E4
X–
I
A
X– channel input
17
E3
Y–
I
A
Y– channel input
18
E2
SNSGND
20
E1
AD0
I
D
—
C4
NC
Analog ground
External reference input
Power supply for sensor drivers and other analog blocks.
Substrate ground (for ESD current). Connection to AGND (on the PCB) is recommended.
Sensor driver return
Address input bit 0
No solder bump for this location. Sensitive area. Avoid trtace beneath.
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SBAS408A – JUNE 2007 – REVISED AUGUST 2007
TIMING INFORMATION
SDA
tSU, STA
tSU, DAT
tBUF
tHD, STA
tHD, DAT
tLOW
SCL
tSU, STO
tHIGH
tHD, STA
tR
tF
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 1. Detailed I/O Timing
TIMING REQUIREMENTS: I2C Standard Mode (fSCL = 100kHz) (1)
All specifications typical at –40°C to +85°C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.
2-WIRE STANDARD MODE PARAMETERS
MIN
10
1.2V ≤ SNSVDD < 1.6V
13
MAX
UNIT
μs
Reset low time (2)
tWL(RESET)
SCL clock frequency
fSCL
Bus free time between a STOP and START
condition
tBUF
4.7
μs
Hold time (repeated) START condition
tHD, STA
4.0
μs
Low period of SCL clock
tLOW
4.7
μs
High period of the SCL clock
tHIGH
4.0
μs
Setup time for a repeated START condition
tSU,
STA
4.7
Data hold time
tHD, DAT
0
Data setup time
tSU,
Rise time for both SDA and SCL clock signals
(receiving)
tR
Cb = total bus capacitance
1000
ns
Fall time for both SDA and SCL clock signals
(receiving)
tF
Cb = total bus capacitance
300
ns
Fall time for both SDA and SCL clock signals
(transmitting)
tOF
Cb = total bus capacitance
250
ns
Setup time for STOP condition
tSU,
Capacitive load for each bus line
Cb
400
pF
Pulse width of spike suppressed
tSP
N/A
ns
(1)
(2)
6
TEST CONDITIONS
SNSVDD ≥ 1.6V
μs
100
μs
3.45
250
DAT
Cb = total capacitance of one bus line in pF
N/A
All input signals are specified with tR = tF = 5ns (10% to 90% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2.
Refer to Figure 36.
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μs
ns
μs
4.0
STO
kHz
TSC2004
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SBAS408A – JUNE 2007 – REVISED AUGUST 2007
2
TIMING REQUIREMENTS: I C Fast Mode (fSCL = 400kHz)
(1)
All specifications typical at –40°C to +85°C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.
2-WIRE FAST MODE PARAMETERS
Reset low time
(2)
TEST CONDITIONS
tWL(RESET)
MIN
SNSVDD ≥ 1.6V
10
1.2V ≤ SNSVDD < 1.6V
13
MAX
UNIT
μs
μs
SCL clock frequency
fSCL
Bus free time between a STOP and START
condition
tBUF
1.3
μs
Hold time (repeated) START condition
tHD, STA
0.6
μs
Low period of SCL clock
tLOW
1.3
μs
High period of the SCL clock
tHIGH
0.6
μs
Setup time for a repeated START condition
tSU,
STA
0.6
Data hold time
tHD, DAT
0
Data setup time
tSU,
Rise time for both SDA and SCL clock signals
(receiving)
tR
Cb = total bus capacitance
20 + 0.1 × Cb
300
ns
Fall time for both SDA and SCL clock signals
(receiving)
tF
Cb = total bus capacitance
20 + 0.1 × Cb
300
ns
Fall time for both SDA and SCL clock signals
(transmitting)
tOF
Cb = total bus capacitance
20 + 0.1 × Cb
250
ns
Setup time for STOP condition
tSU,
Capacitive load for each bus line
Cb
400
pF
Pulse width of spike suppressed
tSP
50
ns
(1)
(2)
400
μs
0.9
100
DAT
Cb = total capacitance of one bus line in pF
0
μs
ns
μs
0.6
STO
kHz
All input signals are specified with tR = tF = 5ns (10% to 90% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2.
Refer to Figure 36.
TIMING REQUIREMENTS: I2C High-Speed Mode (fSCL = 1.7MHz) (1)
All specifications typical at –40°C to +85°C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS
TEST CONDITIONS
MIN
SNSVDD ≥ 1.6V
10
1.2V ≤ SNSVDD < 1.6V
13
MAX
UNIT
μs
Reset low time (2)
tWL(RESET)
SCL clock frequency
fSCL
Hold time (repeated) START condition
tHD, STA
160
ns
Low period of SCL clock
tLOW
320
ns
High period of the SCL clock
tHIGH
120
ns
Setup time for a repeated START condition
tSU,
STA
160
Data hold time
tHD, DAT
0
Data setup time
tSU,
Rise time for SCL clock signal (receiving)
tR
Cb = total bus capacitance
20
80
ns
Rise time for SDA clock signal (receiving)
tR
Cb = total bus capacitance
20
160
ns
Fall time for SCL clock signal (receiving)
tF
Cb = total bus capacitance
20
80
ns
Fall time for SDA clock signal (receiving)
tF
Cb = total bus capacitance
20
160
ns
Fall time for both SDA and SCL clock signals
(transmitting)
tOF
Cb = total bus capacitance
10
80
ns
Setup time for STOP condition
tSU,
Capacitive load for each bus line
Cb
400
pF
Pulse width of spike suppressed
tSP
10
ns
(1)
(2)
μs
1.7
ns
150
10
DAT
Cb = total capacitance of one bus line in pF
0
ns
ns
160
STO
MHz
ns
All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Refer to Figure 36.
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SBAS408A – JUNE 2007 – REVISED AUGUST 2007
TIMING REQUIREMENTS: I2C High-Speed Mode (fSCL = 3.4MHz) (1)
All specifications typical at –40°C to +85°C, SNSVDD = I/OVDD = +1.2V (2) to +3.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS
MIN
10
1.2V ≤ SNSVDD < 1.6V
13
MAX
UNIT
μs
Reset low time (3)
tWL(RESET)
SCL clock frequency
fSCL
Hold time (repeated) START condition
tHD, STA
160
ns
Low period of SCL clock
tLOW
160
ns
High period of the SCL clock
tHIGH
60
ns
Setup time for a repeated START condition
tSU,
STA
160
Data hold time
tHD, DAT
0
Data setup time
tSU,
Rise time for SCL clock signal (receiving)
tR
Cb = total bus capacitance
10
40
ns
Rise time for SDA clock signal (receiving)
tR
Cb = total bus capacitance
10
80
ns
Fall time for SCL clock signal (receiving)
tF
Cb = total bus capacitance
10
40
ns
Fall time for SDA clock signal (receiving)
tF
Cb = total bus capacitance
10
80
ns
Fall time for both SDA and SCL clock signals
(transmitting)
tOF
Cb = total bus capacitance
10
80
ns
Setup time for STOP condition
tSU,
Capacitive load for each bus line
Cb
100
pF
Pulse width of spike suppressed
tSP
10
ns
(1)
(2)
(3)
8
TEST CONDITIONS
SNSVDD ≥ 1.6V
μs
3.4
ns
70
10
DAT
Cb = total capacitance of one bus line in pF
0
ns
ns
160
STO
MHz
ns
All input signals are specified with tR = tF = 5ns (10% to 90% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2.
Due to the low supply voltage of 1.2V and the wide temperature range of –40°C to +85°C, the I2C system devices may not reach the
maximum specification of I2C High-Speed mode, and fSCL may not reach 3.4Mhz.
Refer to Figure 36.
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TYPICAL CHARACTERISTICS
At TA = –40°C to +85°C, SNSVDD = VREF = +1.6V to +3.6V, I/OVDD = +1.2V to +3.6V, fADC = fOSC/2, High-Speed mode (fSCL
= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
CHANGE IN OFFSET
vs TEMPERATURE
CHANGE IN GAIN
vs TEMPERATURE
1.5
1.5
SNSVDD = IOVDD = VREF
SNSVDD = I/OVDD = VREF
1.0
Delta from +25°C (LSB)
Delta from +25°C (LSB)
1.0
0.5
SNSVDD = 1.6V
0
SNSVDD = 3.0V
-0.5
SNSVDD = 1.2V
-1.0
0
-20
20
40
60
80
SNSVDD = 1.6V
100
-40
-20
0
20
40
60
80
Temperature (°C)
Temperature (°C)
Figure 2.
Figure 3.
SNSVDD SUPPLY CURRENT
vs TEMPERATURE
SNSVDD SUPPLY CURRENT
vs SNSVDD SUPPLY VOLTAGE
650
100
1.00
I/OVDD = SNSVDD = VREF
SNSVDD = 3.0V
SNSVDD Supply Current (mA)
SNSVDD Supply Current (mA)
-0.5
-1.5
-40
550
450
350
SNSVDD = 1.6V
250
150
SNSVDD = 1.2V
50
I/OVDD = SNSVDD = VREF
TA = +25°C
0.75
fADC = 1MHz
0.50
fADC = 2MHz
0.25
0
-40
0
-20
20
40
Temperature (°C)
60
80
100
1.2
1.6
2.0
2.4
2.8
3.2
3.6
SNSVDD (V)
Figure 4.
Figure 5.
SNSVDD SUPPLY CURRENT
vs SNSVDD SUPPLY VOLTAGE
POWER-DOWN SUPPLY CURRENT
vs TEMPERATURE
100
I/OVDD = SNSVDD = VREF
TA = +25°C
tPVS, tPRE, tSNS = default values
TSC-Initiated Mode Scan X, Y, Z at 50SSPS
0.8
M = 15, W = 7(1)
0.6
M = 1, W = 1(1)
0.4
Touch Sensor Modeled By:
2kW for Y-Plane
2kW for Y-Plane
1kW for Z (Touch Resistance)(2)
0.2
0
Power-Down Supply Current (nA)
1.2
SNSVDD Supply Current (mA)
SNSVDD = 1.2V
0
-1.0
-1.5
1.0
SNSVDD = 3.0V
0.5
80
SNSVDD = 3.0V
SNSVDD = 3.6V
60
40
SNSVDD = 1.6V
20
I/OVDD = SNSVDD
VREF = 1.6V
0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
-40
SNSVDD (V)
(1)
See Table 1
(2)
See Figure 24
-20
0
20
40
60
80
100
Temperature (°C)
Figure 7.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
At TA = –40°C to +85°C, SNSVDD = VREF = +1.6V to +3.6V, I/OVDD = +1.2V to +3.6V, fADC = fOSC/2, High-Speed mode (fSCL
= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
I/OVDD SUPPLY CURRENT
vs TEMPERATURE
I/OVDD SUPPLY CURRENT
vs I/OVDD SUPPLY VOLTAGE
25
80
I/OVDD Supply Current (mA)
I/OVDD Supply Current (mA)
I/OVDD = SNSVDD = VREF
20
I/OVDD = 1.6V
15
10
I/OVDD = 1.2V
5
I/OVDD = SNSVDD = VREF
TA = +25°C
70
60
50
fADC = 2MHz
40
fADC = 1MHz
30
20
10
0
0
-40
-20
0
20
40
Temperature (°C)
60
80
100
1.2
REFERENCE INPUT CURRENT
vs TEMPERATURE
REFERENCE INPUT CURRENT
vs SNSVDD SUPPLY VOLTAGE
3.6
SNSVDD = I/OVDD = VREF
Reference Input Current (mA)
Reference Input Current (mA)
3.2
4.0
1.5
SNSVDD = 1.6V
1.0
SNSVDD = 1.2V
0.5
3.0
2.0
1.0
0
-40
-20
0
20
40
60
80
100
1.2
1.6
2.0
2.4
2.8
Temperature (°C)
SNSVDD (V)
Figure 10.
Figure 11.
SWITCH ON-RESISTANCE
vs TEMPERATURE
SWITCH ON-RESISTANCE
vs TEMPERATURE
7
3.2
3.6
9
X+
Y+
6
Y+
8
X+
7
5
X-
4
X-
Y-
RON (W)
RON (W)
2.8
Figure 9.
0
3
6
Y5
4
3
X+, Y+: SNSVDD = 3V to Pin
X-, Y-: Pin to GND
-40
-20
0
20
40
Temperature (°C)
2
60
80
100
X+, Y+: SNSVDD = 1.8V to Pin
X-, Y-: Pin to GND
-40
Figure 12.
10
2.4
Figure 8.
SNSVDD = I/OVDD = VREF
1
2.0
I/OVDD (V)
2.0
2
1.6
-20
0
20
40
Temperature (°C)
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
At TA = –40°C to +85°C, SNSVDD = VREF = +1.6V to +3.6V, I/OVDD = +1.2V to +3.6V, fADC = fOSC/2, High-Speed mode (fSCL
= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
SWITCH ON-RESISTANCE
vs SNSVDD SUPPLY VOLTAGE
TEMP DIODE VOLTAGE
vs TEMPERATURE
11
850
10
800
TEMP Diode Voltage (mV)
Y+
X+
8
7
X-
6
Y5
X+, Y+: SNSVDD to Pin
X-, Y-: Pin to GND
TA = +25°C
4
3
1.2
TEMP1 Diode Voltage (mV)
590
588
95.3mV
TEMP2
700
650
600
TEMP1
550
138.2mV
500
I/OVDD = SNSVDD = 3V
VREF = 2.5V
400
SNSVDD (V)
20
40
Temperature (°C)
Figure 14.
Figure 15.
TEMP1 DIODE VOLTAGE
vs SNSVDD SUPPLY VOLTAGE
TEMP2 DIODE VOLTAGE
vs SNSVDD SUPPLY VOLTAGE
1.6
2.0
2.4
2.8
SNSVDD = IOVDD = VREF
TA = +25°C
3.2
-40
3.6
Measurement Includes
A/D Converter Offset
and Gain Errors
586
584
582
580
706
578
704
-20
0
SNSVDD = IOVDD = VREF
TA = +25°C
60
80
100
Measurement Includes
A/D Converter Offset
and Gain Errors
702
700
698
696
694
1.2
1.6
2.0
2.4
2.8
3.2
3.6
1.2
1.6
2.0
2.4
2.8
3.2
3.6
SNSVDD (V)
SNSVDD (V)
Figure 16.
Figure 17.
INTERNAL OSCILLATOR CLOCK FREQUENCY
vs TEMPERATURE
INTERNAL OSCILLATOR CLOCK FREQUENCY
vs TEMPERATURE
4.20
3.90
SNSVDD = I/OVDD = VREF = 3.0V
Internal Clock Frequency (MHz)
Internal Clock Frequency (MHz)
750
450
TEMP2 Diode Voltage (mV)
RON (W)
9
Measurement Includes
A/D Converter Offset
and Gain Errors
4.15
4.10
4.05
4.00
SNSVDD = I/OVDD = VREF = 1.6V
3.85
3.80
3.75
3.70
3.95
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
Temperature (°C)
Temperature (°C)
Figure 18.
Figure 19.
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80
100
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TYPICAL CHARACTERISTICS (continued)
At TA = –40°C to +85°C, SNSVDD = VREF = +1.6V to +3.6V, I/OVDD = +1.2V to +3.6V, fADC = fOSC/2, High-Speed mode (fSCL
= 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.
INTERNAL OSCILLATOR CLOCK FREQUENCY
vs TEMPERATURE
INTERNAL OSCILLATOR CLOCK FREQUENCY
vs SNSVDD SUPPLY VOLTAGE
4.20
SNSVDD = I/OVDD = VREF = 1.2V
Internal Clock Frequency (MHz)
Internal Clock Frequency (MHz)
3.50
3.40
3.30
3.20
3.10
3.00
2.90
SNSVDD = I/OVDD = VREF
TA = +25°C
4.00
3.90
3.80
3.70
3.60
3.50
3.40
3.30
3.20
-40
12
4.10
-20
0
20
40
60
80
100
1.2
1.6
2.0
2.4
Temperature (°C)
SNSVDD (V)
Figure 20.
Figure 21.
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3.2
3.6
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OVERVIEW
The TSC2004 is an analog interface circuit for a human interface touch screen device. A register-based
architecture eases integration with microprocessor-based systems through a standard I2C bus. All peripheral
functions are controlled through the registers and onboard state machines. The TSC2004 features include:
• Very low-power touch screen controller
• Very small onboard footprint
• Relieves host from tedious routine tasks by flexible preprocessing, saving resources for more critical tasks
• Ability to work on very low supply voltage
• Minimal connection interface allows easiest isolation and reduces the number of dedicated I/O pins required
• Miniature, yet complete; requires no external supporting component. (NOTE: Although the TSC2004 can use
an external reference, it is also possible to use SNSVDD as the reference.)
• Enhanced ESD
The TSC2004 consists of the following blocks (refer to the block diagram on the front page):
• Touch Screen Interface
• Auxiliary Input (AUX)
• Temperature Sensor
• Acquisition Activity Preprocessing
• Internal Conversion Clock
• I2C Interface
Communication with the TSC2004 is done via an I2C serial interface. The TSC2004 is an I2C slave device;
therefore, data is shifted into or out of the TSC2004 under control of the host microprocessor, which also
provides the serial data clock.
Control of the TSC2004 and its functions is accomplished by writing to different registers in the TSC2004. A
simple command protocol compatible with I2C is used to address these registers. This protocol can be an I2C
write-addressing followed by multiple control bytes, or multiple combinations of control/data bytes to be written
into different registers (two bytes each). Reading from registers is performed by writing an I2C read-addressing
to the TSC, followed by one or multiple sequential reads from the registers.
The address of the register to be read can be written in TSC Control Byte 0 with the register address and
read-bit (as described in the previous paragraph), and serves as a pointer to the register map where the first
read will start. This designated register address is static; there is no need to write a register address again
unless it is overwritten by a new register address, or if the TSC is reset (by a software reset or by the
RESETpin).
The measurement result is placed in the TSC2004 registers and may be read by the host at any time. This
preprocessing frees up the host so that resources can be redirected for more critical tasks. Two optional signals
are also available from the TSC2004 to indicate that data is available for the host to read. PINTDAV is a
programmable interrupt/status output pin. When PINTDAV is programmed as a DAV output, it indicates that an
A/D conversion has completed and that data are available. When this pin is programmed as a PENIRQ output, it
indicates that a touch has been detected on the touch screen. The status register of the TSC2004 provides an
extended status reading including the state of DAV and PENIRQ without the cost of any dedicated pin.
Figure 22 shows a typical application of the TSC2004.
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OVERVIEW (continued)
1.6VDC
1 mF
1 mF
1m F
0.1mF
0.1mF
AGND
0.1mF
1.6VDC
VREF
1.2kW
I/OVDD
X+
SNSVDD
DGND
SNSGND
1.2kW
PINTDAV
GPIO
RESET
GPIO
Y+
SDA
TSC2004
X-
SDA
Auxilary Input
AD0
AD1
DGND
SUBGND
AUX
AGND
Y-
SNSGND
SCL
Touch
Screen
Host
Processor
SCL
(PINTDAV is optional;
software implementation
polling of the Status
register is possible)
AGND
Figure 22. Typical Circuit Configuration
TOUCH SCREEN OPERATION
A resistive touch screen operates by applying a voltage across a resistor network and measuring the change in
resistance at a given point on the matrix where the screen is touched by an input (stylus, pen, or finger). The
change in the resistance ratio marks the location on the touch screen.
The TSC2004 supports the resistive 4-wire configurations, as shown in Figure 23. The circuit determines
location in two coordinate pair dimensions, although a third dimension can be added for measuring pressure.
4-WIRE TOUCH SCREEN COORDINATE PAIR MEASUREMENT
A 4-wire touch screen is typically constructed as shown in Figure 23. It consists of two transparent resistive
layers separated by insulating spacers.
Conductive Bar
Transparent Conductor (ITO)
Bottom Side
Y+
X+
Silver
Ink
Transparent
Conductor (ITO)
Top Side
XY-
ITO = Indium Tin Oxide
Insulating Material (Glass)
Figure 23. 4-Wire Touch Screen Construction
The 4-wire touch screen panel works by applying a voltage across the vertical or horizontal resistive network.
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OVERVIEW (continued)
The A/D converter converts the voltage measured at the point where the panel is touched. A measurement of
the Y position of the pointing device is made by connecting the X+ input to a data converter chip, turning on the
Y+ and Y– drivers, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the
voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+
lead does not affect the conversion because of the high input impedance of the A/D converter.
Voltage is then applied to the other axis, and the A/D converter converts the voltage representing the X position
on the screen. This process provides the X and Y coordinates to the associated processor.
Measuring touch pressure (Z) can also be done with the TSC2004. To determine pen or finger touch, the
pressure of the touch must be determined. Generally, it is not necessary to have very high performance for this
test; therefore, 10-bit resolution mode is recommended (however, data sheet calculations will be shown with the
12-bit resolution mode). There are several different ways of performing this measurement. The TSC2004
supports two methods. The first method requires knowing the X-plate resistance, the measurement of the
X-Position, and two additional cross panel measurements (Z2 and Z1) of the touch screen (see Figure 24).
Equation 1 calculates the touch resistance:
R TOUCH + RX−plate @
ǒ
Ǔ
XPostition Z 2
*1
4096 Z 1
(1)
The second method requires knowing both the X-plate and Y-plate resistance, measurement of X-Position and
Y-Position, and Z1. Equation 2 also calculates the touch resistance:
RX−plate @ XPostition 4096
Y
R TOUCH +
*1 *R Y−plate @ 1* Position
4096
4096
Z1
ǒ
Ǔ
ǒ
Ǔ
(2)
Measure X-Position
X+
Y+
Touch
X-Position
Y-
X-
Measure Z1-Position
Y+
X+
Touch
Z1-Position
Y-
X-
Y+
X+
Touch
Z2-Position
X-
YMeasure Z2-Position
Figure 24. Pressure Measurement
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OVERVIEW (continued)
When the touch panel is pressed or touched and the drivers to the panel are turned on, the voltage across the
touch panel will often overshoot and then slowly settle down (decay) to a stable DC value. This effect is a result
of mechanical bouncing caused by vibration of the top layer sheet of the touch panel when the panel is pressed.
This settling time must be accounted for, or else the converted value will be in error. Therefore, a delay must be
introduced between the time the driver for a particular measurement is turned on, and the time a measurement
is made.
In some applications, external capacitors may be required across the touch screen for filtering noise picked up
by the touch screen (for example, noise generated by the LCD panel or back-light circuitry). The value of these
capacitors provides a low-pass filter to reduce the noise, but will cause an additional settling time requirement
when the panel is touched.
The TSC2004 offers several solutions to this problem. A programmable delay time is available that sets the
delay between turning the drivers on and making a conversion. This delay is referred to as the panel voltage
stabilization time, and is used in some of the TSC2004 modes. In other modes, the TSC2004 can be
commanded to turn on the drivers only without performing a conversion. Time can then be allowed before the
command is issued to perform a conversion.
The TSC2004 touch screen interface can measure position (X,Y) and pressure (Z). Determination of these
coordinates is possible under three different modes of the A/D converter:
• TSMode1 — conversion controlled by the TSC2004 initiated by the TSC;
• TSMode2 — conversion controlled by the TSC2004 initiated by the host responding to the PENIRQ signal; or
• TSMode3 — conversion completely controlled by the host processor.
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OVERVIEW (continued)
INTERNAL TEMPERATURE SENSOR
In some applications, such as battery recharging, an ambient temperature measurement is required. The
temperature measurement technique used in the TSC2004 relies on the characteristics of a semiconductor
junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic
versus temperature. The ambient temperature can be predicted in applications by knowing the +25°C value of
the VBE voltage and then monitoring the delta of that voltage as the temperature changes.
The TSC2004 offers two modes of temperature measurement. The first mode requires calibration at a known
temperature, but only requires a single reading to predict the ambient temperature. The TEMP1 diode, shown in
Figure 25, is used during this measurement cycle. This voltage is typically 580mV at +25°C with a 10μA current.
The absolute value of this diode voltage can vary by a few millivolts; the temperature coefficient (TC) of this
voltage is very consistent at –2.1mV/°C. During the final test of the end product, the diode voltage would be
stored at a known room temperature, in system memory, for calibration purposes by the user. The result is an
equivalent temperature measurement resolution of 0.3°C/LSB (1LSB = 610μV with VREF = 2.5V).
SNSVDD
TEMP2
TEMP1
+IN
Converter
-IN
AGND
Figure 25. Functional Block Diagram of Temperature Measurement Mode
The second mode does not require a test temperature calibration, but uses a two-measurement (differential)
method to eliminate the need for absolute temperature calibration and for achieving 2°C/LSB accuracy. This
mode requires a second conversion of the voltage across the TEMP2 diode with a resistance 80 times larger
than the TEMP1 diode. The voltage difference between the first (TEMP1) and second (TEMP2) conversion is
represented by:
DV + kT
q @ ln(N)
(3)
Where:
N = the resistance ratio = 80.
k = Boltzmann's constant = 1.3807 × 10-23 J/K (joules/kelvins).
q = the electron charge = 1.6022 × 10-19 C (coulombs).
T = the temperature in kelvins (K).
This method can provide much improved absolute temperature measurement, but a lower resolution of
1.6°C/LSB. The resulting equation to solve for T is:
q @ DV
T+
k @ ln(N)
(4)
Where:
ΔV = VBE (TEMP2) – VBE(TEMP1) (in mV)
∴ T = 2.648 ⋅ ΔV (in K)
or T = 2.648 ⋅ ΔV – 273 (in °C)
Temperature 1 and/or temperature 2 measurements have the same timing as Figure 44.
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OVERVIEW (continued)
ANALOG-TO-DIGITAL CONVERTER
Figure 26 shows the analog inputs of the TSC2004. The analog inputs (X, Y, and Z touch panel coordinates,
chip temperature and auxiliary inputs) are provided via a multiplexer to the Successive Approximation Register
(SAR) Analog-to-Digital (A/D) converter. The A/D architecture is based on capacitive redistribution architecture,
which inherently includes a sample-and-hold function.
SNSVDD
VREF
PINTDAV
SNSVDD
Level Shift
RIRQ
51kW
Data
Available
Pen Touch
Control
Logic
Preprocessing
Zone
Detect
X+
TEMP2
TEMP1
MAV
C3-C0
AGND
XSNSVDD
Y+
+IN
Y-
+REF
Converter
-IN
-REF
SNSGND
AUX
AGND
Figure 26. Simplified Diagram of the Analog Input Section
A unique configuration of low on-resistance switches allows an unselected A/D converter input channel to
provide power and an accompanying pin to provide ground for driving the touch panel. By maintaining a
differential input to the converter and a differential reference input architecture, it is possible to negate errors
caused by the driver switch on-resistances.
The A/D converter is controlled by two A/D Converter Control registers. Several modes of operation are
possible, depending on the bits set in the control registers. Channel selection, scan operation, preprocessing,
resolution, and conversion rate may all be programmed through these registers. These modes are outlined in
the sections that follow for each type of analog input. The conversion results are stored in the appropriate result
register.
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OVERVIEW (continued)
Data Format
The TSC2004 output data is in Straight Binary format as shown in Figure 27. This figure shows the ideal output
code for the given input voltage and does not include the effects of offset, gain, or noise.
FS = Full-Scale Voltage = VREF(1)
1LSB = VREF(1)/4096
1LSB
11...111
Output Code
11...110
11...101
00...010
00...001
00...000
0V
Input Voltage
(2)
FS - 1LSB
(V)
(1)
Reference voltage at converter: +REF – (–REF). See Figure 26.
(2)
Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 26.
Figure 27. Ideal Input Voltages and Output Codes
Reference
The TSC2004 uses an external voltage reference that applied to the VREF pin. It is possible to use VDD as the
reference voltage because the upper reference voltage range is the same as the supply voltage range.
Variable Resolution
The TSC2004 provides either 10-bit or 12-bit resolution for the A/D converter. Lower resolution is often practical
for measuring slow changing signals such as touch pressure. Performing the conversions at lower resolution
reduces the amount of time it takes for the A/D converter to complete its conversion process, which also lowers
power consumption.
Conversion Clock and Conversion Time
The TSC2004 contains an internal clock (oscillator) that drives the internal state machines that perform the
many functions of the part. This clock is divided down to provide a conversion clock for the A/D converter. The
division ratio for this clock is set in the A/D Converter Control register (see Table 15). The ability to change the
conversion clock rate allows the user to choose the optimal values for resolution, speed, and power dissipation.
If the 4MHz (oscillator) clock is used directly as the A/D converter clock (when CL[1:0] = (0,0)), the A/D
converter resolution is limited to 10 bits. Using higher resolutions at this speed does not result in more accurate
conversions. 12-bit resolution requires that CL[1:0] is set to (0,1) or (1,0).
Regardless of the conversion clock speed, the internal clock runs nominally at 3.8MHz at a 3V supply
(SNSVDD) and slows down to 3.6MHz at a 1.6V supply. The conversion time of the TSC2004 depends on
several functions. While the conversion clock speed plays an important role in the time it takes for a conversion
to complete, a certain number of internal clock cycles are needed for proper sampling of the signal. Moreover,
additional times (such as the panel voltage stabilization time), can add significantly to the time it takes to perform
a conversion. Conversion time can vary depending on the mode in which the TSC2004 is used. Throughout this
data sheet, internal and conversion clock cycles are used to describe the amount of time that many functions
take. These times must be taken into account when considering the total system design.
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OVERVIEW (continued)
Touch Detect
PINTDAV can be programmed to generate an interrupt to the host. Figure 28 details an example for the
Y-position measurement. While in the power-down mode, the Y– driver is on and connected to GND. The
internal pen-touch signal depends on whether or not the X+ input is driven low. When the panel is touched, the
X+ input is pulled to ground through the touch screen and the internal pen-touch output is set to low because of
the detection on the current path through the panel to GND, which initiates an interrupt to the processor. During
the measurement cycles for X- and Y-Position, the X+ input is disconnected, which eliminates any leakage
current from the pull-up resistor to flow through the touch screen, thus causing no errors.
Analog VDD
Plane
SNSVDD
PINTDAV
SNSVDD
Level
Shifter
Y+
Pen Touch
Control
Logic
Data Available
TEMP1
High when
the X+ or Y+
driver is on.
X+
TEMP2
RIRQ
51kW
Sense
DGND
Y-
ON
SNSGND
High when the X+ or Y+
driver is on, or when any
sensor connection/short
circuit tests are activated.
Vias go to system analog ground plane.
AGND
Figure 28. Example of a Pen-Touch Induced Interrupt via the PINTDAV Pin
In modes where the TSC2004 must detect whether or not the screen is still being touched (for example, when
doing a pen-touch initiated X, Y, and Z conversion), the TSC2004 must reset the drivers so that the RIRQ resistor
is connected again. Because of the high value of this pull-up resistor, any capacitance on the touch screen
inputs will cause a long delay time, and may prevent the detection from occurring correctly. To prevent this
possible delay, the TSC2004 has a circuit that allows any screen capacitance to be precharged, so that the
pull-up resistor does not have to be the only source for the charging current. The time allowed for this
precharge, as well as the time needed to sense if the screen is still touched, can be set in the configuration
register.
This configuration underscores the need to use the minimum possible capacitor values on the touch screen
inputs. These capacitors may be needed to reduce noise, but too large a value will increase the needed
precharge and sense times, as well as the panel voltage stabilization time.
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OVERVIEW (continued)
Preprocessing
The TSC2004 offers an array of powerful preprocessing operations that reduce unnecessary traffic on the bus
and reduce the host processor loading. This reduction is especially critical for the serial interface, where limited
bandwidth is a tradeoff, keeping the connection lines to a minimum.
All data acquisition tasks are looking for specific data that meet certain criteria. Many of these tasks fall into a
predefined range, while other tasks may be looking for a value in a noisy environment. If these data are all to be
retrieved by host processor for processing, the limited bus bandwidth will be quickly saturated, along with the
host processor processing capability. In any case, the host processor must always be reserved for more critical
tasks, not for routine work.
The preprocessing unit consists of two main functions: the combined MAV filter (median value filter and
averaging filter), followed by the zone detection.
Preprocessing - Median Value Filter and Averaging Value Filter
The first preprocessing function, a combined MAV filter, can be operated independently as a median value filter
(MVF), an averaging value filter (AVF) and a combined filter (MAVF).
If the acquired signal source is noisy because of the digital switching circuit, it may be necessary to evaluate the
data without noise. In this case, the median value filter (MVF) operation helps to discard the noise. The array of
N converted results is first sorted. The return value is either the middle (median value) of an array of M
converted results, or the average value of a window size of W of converted results:
• N = the total number of converted results used by the MAV filter
• M = the median value filter size programmed
• W = the averaging window size programmed
If M = 1, then N = W. A special case is W = 1, which means the MAVF is bypassed. Otherwise, if W > 1, only
averaging is performed on these converted results. In either case, the return value is the averaged value of
window size W of converted results. If M > 1 and W = 1, then N = M, meaning only the median value filter is
operating. The return value is the middle position converted result from the array of M converted results. If M > 1
and W > 1, then N = M. In this case, W < M. The return value is the averaged value of middle portion W of
converted results out of the array of M converted results. Since the value of W is an odd number in this case,
the averaging value is calculated with the middle position converted result counted twice (so a total of W + 1
converted results are averaged).
Table 1. Median Value Filter Size Selection
M1
M0
MEDIAN VALUE FILTER
M=
POSSIBLE AVERAGING WINDOW SIZE
W=
0
0
1
1, 4, 8, 16
0
1
3
1
1
0
7
1, 3
1
1
15
1, 3, 7
Table 2. Averaging Value Filter Size Selection
AVERAGING VALUE FILTER SIZE SELECTION
W=
W1
W0
M = 1 (Averaging Only)
M>1
0
0
1
1
0
1
4
3
1
0
8
7
1
1
16
Reserved
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NOTE: The default setting for MAVF is MVF (median value filter with averaging bypassed) for any invalid
configuration. For example, if (M1, M0, W1, W0) = (1,0,1,0), the MAVF performs as it was configured for
(1,0,0,0), median filter only with filter size = 7 and no averaging. The only exception is M > 1 and (W1, W0) =
(1,1). This setting is reserved and should not be used.
Table 3. Combined MAV Filter Setting
M
W
INTERPRETATION
N=
=1
=1
Bypass both MAF and AVF
W
The converted result
=1
>1
Bypass MVF only
W
Average of W converted results
>1
=1
Bypass AVF only
M
Median of M converted results
M
Average of middle W of M converted results with the median
counted twice
>1
>1
M>W
OUTPUT
The MAV filter is available for all analog inputs including the touch screen inputs, temperature measurements
TEMP1 and TEMP2, and the AUX measurement.
N measurements input
into temporary array
N
N Acquired
Data
M=1
N
W
Averaging output
from window W
M > 1 and W = 1
N
M
Median value
from array M
M > 1 and W > 1
N
M
Averaging output
from window W
Sort by
descending order
W
Figure 29. MAV Filter Operation (patent pending)
Zone Detection
The Zone Detection unit is capable of screening all processed data from the MAVF and retaining only the data
of interest (data that fit the prerequisite). This unit can be programmed to send an alert if a predefined condition
set by two threshold value registers is met. Three different zones may be set:
1. Above the upper limit (X ≥ Threshold High)
2. Between the two thresholds (Threshold Low < X < Threshold High)
3. Below the lower limit (X ≤ Threshold Low)
The AUX and temperatures TEMP1 and TEMP2 have separate threshold value registers that can be enabled or
disabled. This function is not available to the touch screen inputs. Once the preset condition is met, the DAV
output to the PINTDAV pin is pulled low and the corresponding DAV bit is set.
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2
I C INTERFACE
The TSC2004 supports the I2C serial bus and data transmission protocol in all three defined modes: standard,
fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving
data as a receiver. The device that controls the message is called a master. The devices that are controlled by
the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL),
controls the bus access, and generates the START and STOP conditions. The TSC2004 operates as a slave on
the I2C bus. Connections to the bus are made via the open-drain I/O lines, SDA and SCL.
The following bus protocol has been defined (see Figure 30):
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy
Both data and clock lines remain HIGH.
Start Data Transfer
A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop Data Transfer
A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data Valid
The state of the data line represents valid data, when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock signal. There is one clock pulse per bit of
data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is
determined by the master device. The information is transferred byte-wise and each receiver
acknowledges with a ninth-bit.
Within the I2C bus specifications, a standard mode (100kHz clock rate), a fast mode (400kHz clock
rate), and a high-speed mode (3.4MHz clock rate) are each defined. The TSC2004 works in all
three modes.
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception
of each byte. The master device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during the HIGH period of the acknowledge clock
pulse. Of course, setup and hold times must be taken into account. A master must signal an end of
data to the slave by not generating an acknowledge bit on the last byte that has been clocked out
of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate
the STOP condition.
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Figure 30 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit,
two types of data transfer are possible:
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the
slave address and each received byte.
2. Data transfer from a slave transmitter to a master receiver. The first byte, the slave address, is
transmitted by the master. The slave then returns an acknowledge bit. Next, a number of data bytes are
transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received byte, a not-acknowledge is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer ends
with a STOP condition or a repeated START condition. Because a repeated START condition is also the
beginning of the next serial transfer, the bus will not be released.
The TSC2004 may operate in the following two modes:
1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception of
the slave address and direction bit.
2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave
receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the TSC2004 while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning and end of a serial transfer.
I2C Fast or Standard Mode (F/S Mode)
In I2C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Timing Information
section.
In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a
START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has
finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high, as shown in Figure 30. The bus is free for another transmission after a stop condition
has occurred. Figure 30 shows the complete F/S mode transfer on the I2C, 2-wire serial interface. The address
byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA state is
only allowed to change while SCL is low, except for the START and STOP conditions. Data are transmitted in
8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word plus
acknowledge bit).
SDA
MSB
Slave Address
R/W
Direction Bit
Acknowledgement
Signal from Receiver
Acknowledgement
Signal from Receiver
1
SCL
2
6
7
8
9
1
2
3-8
8
ACK
START
Condition
Repeated If More Bytes Are Transferred
Figure 30. Complete Fast- or Standard-Mode Transfer
24
9
ACK
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2
I C High-Speed Mode (Hs Mode)
Serial data transfer format in High-Speed (Hs) mode meets the Fast or Standard (F/S) mode I2C bus
specification. Hs mode can only commence after the following conditions (all of which are in F/S mode) exist:
1. START condition (S)
2. 8-bit master code (00001xxx)
3. not-acknowledge bit (N)
Figure 31 shows this sequence in more detail. Hs-mode master codes are reserved 8-bit codes used only for
triggering Hs mode, and are not to be used for slave addressing or any other purpose. The master code
indicates to other devices that an Hs-mode transfer is about to begin and the connected devices must meet the
Hs mode specification. Because no device is allowed to acknowledge the master code, the master code is
followed by a not-acknowledge bit (N).
After the not-acknowledge bit (N) and SCL have been pulled-up to a HIGH level, the master switches to
Hs-mode and enables (at time tH; shown in Figure 31) the current-source pull-up circuit for SCL. Because other
devices can delay the serial transfer before tH by stretching the LOW period of SCL, the master will enable its
current-source pull-up circuit when all devices have released SCL, and SCL has reached a HIGH level, thus
speeding up the last part of the rise time of the SCL.
The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit
address, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) condition
and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pull-up
circuit. This disabling enables other devices to delay the serial transfer by stretching the LOW period of SCL.
The master re-enables its current-source pull-up circuit again when all devices have released, and SCL reaches
a HIGH level, which speeds up the last part of the SCL signal rise time.
Data transfer continues in Hs mode after the next repeated START (Sr), and only switches back to F/S mode
after a STOP condition (P). To reduce the overhead of the master code, it is possible that a master links a
number of Hs mode transfers, separated by repeated START conditions (Sr).
8-Bit Master Code 00001xxx
S
N
tH
SDA
SCL
1
2 to 5
6
7
8
9
Fast or Standard Mode
R/W
7-Bit Slave Address
Sr
A
n x (8-Bit DATA
+
A/N)
Sr P
SDA
SCL
1
2 to 5
6
7
8
9
1
2 to 5
6
7
8
9
If P then
Fast or Standard Mode
High-Speed Mode
tH
= Current Source Pull-Up
= Resistor Pull-Up
A = Acknowledge (SDA LOW)
N = Not Acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = Repeated START Condition
If Sr (dotted lines)
then High-Speed Mode
tFS
Figure 31. Complete High-Speed Mode Transfer
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DIGITAL INTERFACE
ADDRESS BYTE
The TSC2004 has a 7-bit slave address word. The first five bits (MSBs) of the slave address are factory-preset
to comply with the I2C standard for A/D converters and are always set at '10010'. The logic state of the address
input pins (AD1-AD0) determine the two LSBs of the device address to activate communication. Therefore, a
maximum of four devices with the same preset code can be connected on the same bus at one time.
The AD1-AD0 address inputs are only read during a power-up of the device, and should be connected to a
digital supply (I/OVDD), or digital ground (DGND). The slave address is latched into the TSC2004 on the falling
edge of SCL after the read/write bit has been received by the slave.
The last bit of the address byte (R/W) defines the operation to be performed. When set to a '1', a read operation
is selected; when set to a ‘0’, a write operation is selected. Following the START condition, the TSC2004
monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the '10010' code,
the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA
line.
Table 4. I2C Slave Address Byte
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
1
0
0
1
0
AD1
AD0
R/W
Bit D0: R/W
1: I2C master read from TSC (I2C read addressing).
0: I2C master write to TSC (I2C write addressing).
I2C Write-Addressing Byte
S/Sr
1
0
0
1
0
AD1 AD0
0
START or
Repeated START
A
From Master to Slave
A = Acknowledge (SDA LOW)
S = START Condition
ACK
From Slave to Master
Sr = Repeated START Condition
I2C Read-Addressing Byte
S/Sr
1
0
0
1
0
AD1 AD0
START or
Repeated START
1
A
ACK
Figure 32. I2C Bus Addressing (Slave Address Byte Format)
CONTROL BYTE
Table 5. Control Byte Format:
Start a Conversion and Mode Setting
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
1
(Control Byte 1)
C3
C2
C1
C0
RM
SWRST
STS
0
(Control Byte 0)
A3
A2
A1
A0
Reserved
(Write '0')
PND0
R/W
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Table 6. Control Byte 1 Bit Register Description (D7 = 1)
BIT
NAME
D7
Control Byte ID
D6-D3
C3:C0
D2
RM
D1
SWRST
D0
STS
DESCRIPTION
1
Converter Function Select as detailed in Table 7
0: 10 Bit
1: 12 Bit
Software Reset. This bit is self-clearing.
1: Reset all register values to default
Stop bit for all converter functions. This bit is self-clearing.
Bit D7: Control Byte ID
1: Control Byte 1 (start conversion and channel select and conversion-related configuration).
0: Control Byte 0 (read/write data registers and non-conversion-related controls).
Bits D6-D3: C3-C0
Converter function select bits. These bits select the input to be converted, and the converter function to be
executed. Table 7 lists the possible converter functions.
Table 7. Converter Function Select
C3
C2
C1
C0
FUNCTION
0
0
0
0
Touch screen scan function: X, Y, Z1, and Z2 coordinates converted and the results returned
to X, Y, Z1, and Z2 data registers. Scan continues until either the pen is lifted or a stop bit is
sent.
0
0
0
1
Touch screen scan function: X and Y coordinates converted and the results returned to X and
Y data registers. Scan continues until either the pen is lifted or a stop bit is sent.
0
0
1
0
Touch screen scan function: X coordinate converted and the results returned to X data
register.
0
0
1
1
Touch screen scan function: Y coordinate converted and the results returned to Y data
register.
0
1
0
0
Touch screen scan function: Z1 and Z2 coordinates converted and the results returned to Z1
and Z2 data registers.
0
1
0
1
Auxiliary input converted and the results returned to the AUX data register.
0
1
1
0
A temperature measurement is made and the results returned to the Temperature
Measurement 1 data register.
0
1
1
1
A differential temperature measurement is made and the results returned to the Temperature
Measurement 2 data register.
1
0
0
0
Auxiliary input is converted continuously and the results returned to the AUX data register.
1
0
0
1
Touch screen panel connection to X-axis drivers is tested. The test result is output to
PINTDAV and shown in STATUS register.
1
0
1
0
Touch screen panel connection to Y-axis drivers is tested. The test result is output to
PINTDAV and shown in STATUS register.
1
0
1
1
RESERVED (Note: any condition caused by this command can be cleared by setting the STS
bit to 1).
1
1
0
0
Touch screen panel short-circuit (between X and Y plates) is tested through Y-axis. The test
result is output to PINTDAV and shown in the STATUS register.
1
1
0
1
X+, X– drivers status
1
1
1
0
Y+, Y– drivers status
1
1
1
1
Y+, X– drivers status
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Touch Screen Scan Function for XYZ or XY
C3-C0 = 0000 or 0001: These scan functions can collaborate with the PSM bit that defines the control mode of
converter functions. If the PSM bit is set to '1', these scan function select commands are recommended to be
issued before a pen touch is detected in order to allow the TSC2004 to initiate and control the scan processes
immediately after the screen is touched. If these functions are not issued before a pen touch is detected, the
TSC2004 will wait for the host to write these functions before starting a scan process. If PSM stays as '1' after a
TSC-initiated scan function is complete, the host is not required to write these function select bits again for each
of the following pen touches after the detected touch. In the host-controlled converter function mode (PSM = 0),
the host must send these functions select bits repeatedly for each scan function after a detected pen touch.
Note that the data registers may be updated while a host reading is in progress. Using the sequential read cycle
(see Figure 34) prevents the TSC from updating registers while a host reading is in progress. To ensure that the
XYZ or XY coordinates are correctly read, use the sequential read cycle to read the coordinates after the scan.
Touch Screen Sensor Connection Tests for X-Axis and Y-Axis
Range of resistances of different touch screen panels can be selected by setting the TBM bits in CFR1; see
Table 20. Once the resistance of the sensor panel is selected, two continuity tests are run separately for the
X-axis and Y-axis. The unit under test must pass both connection tests to ensure that a proper connection is
secured.
C3-C0 = 1001: PINTDAV = 0 during this connection test. A '1' shown at end of the test indicates the X-axis
drivers are well-connected to the sensor; otherwise, X-axis drivers are poorly connected. If drivers fail to
connect, then PINTDAV stays low until a stop bit (STS set to '1') is issued.
C3-C0 = 1010: PINTDAV = 0 during this connection test. A '1' shown at end of the test indicates the Y-axis
drivers are well-connected to the sensor; otherwise, Y-axis drivers are poorly connected. If the drivers are fail to
connect, then PINTDAV stays low until a stop bit (STS set to '1') is issued.
Touch Sensor Short-Circuit Test
If the TBM bits of CFR1 detailed in Table 20 are all set to '1', a short-circuit in the touch sensor can be detected.
C3-C0 = 1011: Reserved.
C3-C0 = 1100: PINTDAV = 0 during this short-circuit test. A '1' shown at end of the test indicates there is no
short-circuit detected (through Y-axis) between the flex and stable layers. If there is a short-circuit detected,
PINTDAV stays low until a stop bit (STS set to '1') is issued.
RM—Resolution select. If RM = 1, the conversion result resolution is 12-bit; otherwise, the resolution is 10-bit.
This bit is the same RM bit shown in CFR0.
SWRST—Software reset input. All register values are set to default value if a '1' is written to this bit. This bit is
automatically set to '0' in order to cancel the software reset and resume normal operation.
STS—Stop bit for all converter functions. When writing a '1' to this register, this bit aborts the converter function
currently running in the TSC2004. A '0' is automatically written to this register in order to end the stop bit. This
bit can only stop converter functions; it does not reset any data, status, or configuration registers. This bit is the
same STS bit shown in CFR0, but can only be read through the CFR0 register with different interpretations.
Table 8. STS Bit Operation
28
OPERATION
VALUE
Write
0
DESCRIPTION
Normal operation
Write
1
Stop converter functions and power down
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Table 9. Control Byte 0 Bit Register Description (D7 = 0)
BIT
NAME
DESCRIPTION
D7
Control Byte ID
D6-D3
A3-A0
D2
RESERVED
1: Control Byte 1—start conversion, channel select, and converison-related
configuration
0: Control Byte 0—read/write data registers and non-conversion-related
controls
Register Address Bits as detailed in Table 10
A '0' must be set in this bit for normal operation
Power Not Down Control
D1
1: A/D converter biasing circuitry is always on between conversions but is
shut down after the converter function stops
PND0
0: A/D converter biasing circuitry is shut down either between conversions
or after the converter function stops
TSC Internal Register Data Flow Control
D0
R/W
1: Read from TSC internal registers
0: Write to TSC internal registers
Table 10. Internal Register Map
REGISTER ADDRESS
A3
A2
A1
A0
REGISTER CONTENT
READ/WRITE
0
0
0
0
X measurement result
R
0
0
0
1
Y measurement result
R
0
0
1
0
Z1 measurement result
R
0
0
1
1
Z2 measurement result
R
0
1
0
0
AUX measurement result
R
0
1
0
1
Temp1 measurement result
R
0
1
1
0
Temp2 measurement result
R
0
1
1
1
Status
R
1
0
0
0
AUX high threshold
R/W
1
0
0
1
AUX low threshold
R/W
1
0
1
0
Temp high threshold (apply to both TEMP1 and TEMP2)
R/W
1
0
1
1
Temp low threshold (apply to both TEMP1 and TEMP2)
R/W
1
1
0
0
CFR0
R/W
1
1
0
1
CFR1
R/W
1
1
1
0
CFR2
R/W
1
1
1
1
Converter function select status
R
R/W—Register read and write control. A '1' indicates the internal register addressed by A3-A0. The value of
A3-A0 is stored as the starting point for a register read (see Figure 33). The content of the addressed register is
sent to SDA by using I2C read addressing (see Figure 34 and Figure 35). A '0' indicates the data following
Control Byte 0 on SDA are written into registers addressed by A3-A0 (see Figure 33).
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START A WRITE CYCLE
A write cycle begins when the master issues the slave address to the TSC2004. The slave address consists of
seven address bits and a write bit (R/W = 0; see Table 5). When the eighth bit has been received and the
address matches the AD1-AD0 address input pin setting, the TSC2004 issues an acknowledge bit by pulling
SDA low for one additional clock cycle (ACK = 0); see Figure 32.
When the master receives the acknowledge bit from the TSC2004, the master writes the input control byte to the
slave; see Table 5. After the control byte is received by the slave, the slave issues another acknowledge bit by
pulling SDA low for one clock cycle (ACK = 0). The master then ends the write cycle by issuing a STOP or
repeated START condition; see Figure 33.
Write Cycle
START
I C Slave Address
2
I C WriteAddressing Byte
0 A
8
Control Byte 1
ACK 1 C3 C2 C1 C0 RM
A P
STS
S
1
SWRST
7
2
STOP(1)
Converter Function Select
START
I C Slave Address
I2C WriteAddressing Byte
0 A
8
8
Control Byte 0
ACK 0 A3 A2 A1 A0
Rsvd
S
1
Data Byte 1/2
(HIGH Byte)
A
PND0
7
2
8
A
Data Byte 2/2
(LOW Byte)
A P
STOP(1)
0
TSC Internal Register Address for Write Data
START
I2C Slave Address
2
I C WriteAddressing Byte
0 A
8
Control Byte 0
ACK 0 A3 A2 A1 A0
Rsvd
S
1
A P
PND0
7
STOP(1)
1
TSC Internal Register Starting Address mh(2)
(M + N x 3) x 8
7
S
START
I2C Slave Address
1
0 A
I2C WriteAddressing Byte
From Master to Slave
From Slave to Master
A
A
A P
Mixed M (Control Byte 1 or Control Byte 0 with Read Bit)
Plus N (Control Byte 0 with Data Bytes), Separated by TSC ACKs
A = Acknowledge (SDA LOW)
N = Not Acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = Repeated START Condition
NOTES: (1) In order to start the next sequence, a STOP condition must be followed by a START condition. If no STOP is
used, then a Repeated START must be used. Also note that is a STOP condition is issued in High-Speed
mode, the mode will revert to the previous mode: Fast or Standard.
(2) mh is a hexadecimal number.
Figure 33. Write Cycle
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REGISTER ACCESS
Data access begins with the master issuing a START (or repeated START) condition followed by the 7-bit
address and a read bit (R/W = 1; see Table 5). When the eighth bit has been received and the address
matches, the slave issues an acknowledge by pulling SDA low for one clock cycle (ACK = 0). The first byte of
serial data will follow. After the first byte has been sent by the slave, it releases the SDA line for the master to
issue an acknowledge (ACK = 0). The slave issues the second byte of serial data upon receiving the
acknowledgement from the master (D7-D0), followed by a not-acknowledge bit (ACK = 1) from the master to
indicate that the last data byte has been received. The master then issues a STOP condition (P) or repeated
START (Sr), which ends the read cycle, as shown in Figure 34 and Figure 35. If the master issues a
not-acknowledge (ACK = 1) after receipt of the first data byte, the master must then issue a stop condition (P) to
reset the registers. If the master is not ready to receive the second data byte, it should issue the acknowledge
(ACK = 0), or the master should stretch the clock. Upon restart of the clock, the second byte of data can be
received by the master.
Read Cycle: Sequential, from Register Address mh(2) to (m + n)h(3)
7
S
START
I2C Slave Address
1
8
8
1
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
A
2
A
A
Register (Address = mh) Content
I C Read-Addressing Byte
8
8
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
A
A
Register (Address = (m + 1)h) Content
8
8
NACK
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
N
A
Register (Address = (m + n)h) Content
From Master to Slave
From Slave to Master
P
STOP(1)
A = Acknowledge (SDA LOW)
N = Not Acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = Repeated START Condition
NOTES: (1) In order to start the next sequence, a STOP condition must be followed by a START condition. If no STOP is
used, then a Repeated START must be used. Also note that is a STOP condition is issued in High-Speed
mode, the mode will revert to the previous mode: Fast or Standard.
(2) mh is a hexadecimal number.
(3) If (m+n)h is greater than Fh, then (m + n)h is modulo 16.
Figure 34. Sequential Read Cycle
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Read Cycle: Repeated, Register Address mh(2)
7
S
START
I2C Slave Address
START
8
8
NACK
1
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
N
A
2
I C Read-Addressing Byte
7
S
1
I2C Slave Address
1
8
8
NACK
1
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
N
A
START
I C Slave Address
1
A
A
P
STOP(1)
Register (Address = mh) Content
7
S
P
STOP(1)
Register (Address = mh) Content
I2C Read-Addressing Byte
2
A
8
8
NACK
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
N
I2C Read-Addressing Byte
A
P
STOP(1)
Register (Address = mh) Content
Or...
7
Sr
2
I C Slave Address
1
8
8
NACK
1
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
N
A
Repeated I2C Read-Addressing Byte
START
7
Sr
2
I C Slave Address
Register (Address = mh) Content
1
8
8
NACK
1
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
N
A
Repeated I2C Read-Addressing Byte
START
I2C Slave Address
2
1
Repeated I C Read-Addressing Byte
START
From Master to Slave
From Slave to Master
A
Register (Address = mh) Content
7
Sr
A
A
8
8
NACK
Data Byte 1/2
(HIGH Byte)
Data Byte 2/2
(LOW Byte)
N
A
Register (Address = mh) Content
P
STOP(1)
A = Acknowledge (SDA LOW)
N = Not Acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = Repeated START Condition
NOTES: (1) In order to start the next sequence, a STOP condition must be followed by a START condition. If no STOP is
used, then a Repeated START must be used. Also note that is a STOP condition is issued in High-Speed
mode, the mode will revert to the previous mode: Fast or Standard.
(2) mh is a hexadecimal number.
Figure 35. Repeated Read Cycle
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COMMUNICATION PROTOCOL
The TSC2004 is controlled entirely by registers. Reading and writing to these registers are accomplished by the
use of Control Byte 0, which includes a 4-bit address plus one read/write TSC register control bit. The data
registers defined in Table 10 are all 16-bit, right-adjusted. NOTE: Except for some configuration registers and
the Status register that are full 16-bit registers, the rest of the value registers are 12-bit (or 10-bit) data preceded
by four (or six) zeros.
Configuration Register 0
Table 11. Configuration Register 0 (Reset Value = 4000h for Read; 0000h for Write)
MSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
D0
PSM
STS
RM
CL1
CL0
PV2
PV1
PV0
PR2
PR1
PR0
SN2
SN1
SN0
DTW
LSM
PSM—Pen status/control mode. Reading this bit allows the host to determine if the screen is touched. Writing to
this bit selects the mode used to control the flow of converter functions that are either initiated and/or controlled
by host or under control of the TSC2004 responding to a pen touch. When reading, the PSM bit indicates if the
pen is down or not. When writing to this register, this bit determines if the TSC2004 controls the converter
functions, or if the converter functions are host-controlled. The default state is the host-controlled converter
function mode (0). The other state (1) is the TSC-initiated scan function mode that must only collaborate with
C3-C0 = 0000 or 0001 in order to allow the TSC2004 to initiate and control the scan function for XYZ or XY
when a pen touch is detected.
Table 12. PSM Bit Operation
OPERATION
VALUE
DESCRIPTION
Read
0
No screen touch detected
Read
1
Screen touch detected
Write
0
Converter functions initiated and/or controlled by host
Write
1
Converter functions initiated and controlled by the TSC2004
STS—A/D converter status. When reading, this bit indicates if the converter is busy or not busy. Continuous
scans or conversions can be stopped by writing a '1' to this bit, immediately aborting the running converter
function (even if the pen is still down) and causing the A/D converter to power down. The default state for write
is 0 (normal operation), and the default state for read is 1 (converter is not busy). NOTE: The same bit can be
written through Control Byte 1. This bit is self-clearing.
Table 13. STS Bit Operation
OPERATION
VALUE
Read
0
DESCRIPTION
Converter is busy
Read
1
Converter is not busy
Write
0
Normal operation
Write
1
Stop converter function and power down
RM—Resolution control. The A/D converter resolution is specified with this bit. See Table 14 for a description of
these bits. This bit is the same whether reading or writing, and defaults to 0. Note that the same bit can be
written through Control Byte 1.
Table 14. A/D Converter Resolution Control
RM
FUNCTION
0
10-bit resolution. Power-up and reset default.
1
12-bit resolution
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CL1, CL0—Conversion clock control. These two bits specify the clock rate that the A/D converter uses to
perform conversion, as shown in Table 15.
Table 15. A/D Converter Conversion Clock Control
(1)
CL1
CL0
0
0
FUNCTION
fADC = fOSC/1. This is referred to as the 4MHz A/D converter clock rate, 10-bit resolution only (1).
0
1
fADC = fOSC/2. This is referred to as the 2MHz A/D converter clock rate.
1
0
fADC = fOSC/4. This is referred to as the 1MHz A/D converter clock rate.
1
1
fADC = fOSC/4. This is referred to as the 1MHz A/D converter clock rate.
For SNSVDD = 1.2V at –40°C, a lower A/D converter clock rate should be used to allow enough time for conversion settling.
PV2-PV0—Panel voltage stabilization time control. These bits specify a delay time from the moment the touch
screen drivers are enabled to the time the voltage is sampled and a conversion is started. These bits allow the
user to adjust the appropriate settling time for the touch panel and external capacitances. See Table 16 for
settings of these bits. The default state is 000, indicating a 0μs stabilization time. These bits are the same
whether reading or writing.
Table 16. Panel Voltage Stabilization Time Control
PV2
PV1
PV0
0
0
0
STABILIZATION TIME (tPVS)
0μs
0
0
1
100μs
0
1
0
500μs
0
1
1
1ms
1
0
0
5ms
1
0
1
10ms
1
1
0
50ms
1
1
1
100ms
PR2-PR0—Precharge time selection. These bits set the amount of time allowed for precharging any pin
capacitance on the touch screen prior to sensing if a pen touch is happening.
Table 17. Precharge Time Selection
PR2
PR1
PR0
PRECHARGE TIME(tPRE)
0
0
0
20μs
0
0
1
84μs
0
1
0
276μs
0
1
1
340μs
1
0
0
1.044ms
1
0
1
1.108ms
1
1
0
1.300ms
1
1
1
1.364ms
SNS2-SNS0—Sense time selection. These bits set the amount of time the TSC2004 waits to sense whether the
screen is touched after converting a coordinate.
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Table 18. Sense Time Selection
SNS2
SNS1
SNS0
SENSE TIME (tSNS)
0
0
0
32μs
0
0
1
96μs
0
1
0
544μs
0
1
1
608μs
1
0
0
2.080ms
1
0
1
2.144ms
1
1
0
2.592ms
1
1
1
2.656ms
DTW—Detection of pen touch in wait (patent pending). Writing a '1' to this bit enables the pen touch detection in
background while waiting for the host to issue the converter function in host-initiated/controlled modes. This
detection in background allows the TSC2004 to pull high at PINTDAV to indicate no pen touch detected while
waiting for the host to issue the converter function. If the host polls a high state at PINTDAV before the convert
function is sent, the host can abort the issuance of the convert function and stay in the polling PINTDAV mode
until the next pen touch is detected.
LSM—Longer sampling mode. When this bit is set to '1', the extra 500ns of sampling time is added to the
normal sampling cycles of each conversion. This additional time is represented as approximately two internal
oscillator clock cycles. For SNSVDD = 1.2V at –40°C, the LSM bit should be set to '1' so that the sampled signal
has enough time to settle.
Configuration Register 1
Configuration register 1 (CFR1) defines the connection test-bit modes configuration and batch delay selection.
Table 19. Configuration Register 1 (Reset Value = 0000h)
MSB
D15
D14
D13
D12
Resrvd Resrvd Resrvd Resrvd
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
D0
TBM3
TBM2
TBM1
TBM0
Resrvd
Resrvd
Resrvd
Resrvd
Resrvd
BTD2
BTD1
BTD0
TBM3-TBM0—Connection test-bit modes (patent pending). These bits specify the mode of test bits used for the
predefined range of the combined X-axis and Y-axis touch screen panel resistance (RTS).
Table 20. Touch Screen Resistance Range and Test-Bit Modes
TEST-BIT MODES
RTS
(kΩ)
TBM3
TBM2
TBM1
TBM0
0
0
0
0
0.17
0
0
0
1
0.17 < RTS ≤ 0.52
0
0
1
0
0.52 < RTS ≤ 0.86
0
0
1
1
0.86 < RTS ≤ 1.6
0
1
0
0
1.6 < RTS ≤ 2.2
0
1
0
1
2.2 < RTS ≤ 3.6
0
1
1
0
3.6 < RTS ≤ 5.0
0
1
1
1
5.0 < RTS ≤ 7.8
1
0
0
0
7.8 < RTS ≤ 10.5
1
0
0
1
10.5 < RTS ≤ 16.0
1
0
1
0
16.0 < RTS ≤ 21.6
1
0
1
1
21.6 < RTS ≤ 32.6
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Only for short-circuit panel test
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BTD2-BTD0—Batch Time Delay mode. These are the selection bits that specify the delay before a
sample/conversion scan cycle is triggered. When it is set, Batch Time Delay mode uses a set of timers to
automatically trigger a sequence of sample-and-conversion events. The mode works for both TSC-initiated
scans (XYZ or XY) and host-initiated scans (XYZ or XY).
A TSC-initiated scan (XYZ or XY) can be configured by setting the PSM bit in CFR0 to '1' and C[3:0] in Control
Byte 1 to '0000' or '0001'. In the case of a TSC-initiated scan (XYZ or XY), the sequence begins with the TSC
responding to a pen touch. After the first processed sample set completes during the batch delay, the scan
enters a wait mode until the end of the batch delay is reached. If a pen touch is still detected at that moment, the
scan continues to process the next sample set, and the batch delay is resumed. The throughput of the
processed sample sets (shown in Table 21 as sample sets per second, or SSPS) is regulated by the selected
batch delay during the time of the detected pen touch. A TSC-initiated scan (XYZ or XY) can be configured by
setting the PSM bit in CFR0 to '1' and C[3:0] in Control Byte 1 to '0000' or '0001'. Note that the throughput of the
processed sample set also depends on the settings of stabilization, precharge, and sense times, and the total
number of samples to be processed per coordinates. If the accrual time of these factors exceeds the batch delay
time, the accrual time dominates. Batch delay time starts when the pen touch initiates the scan function that
converts coordinates.
A host-initiated scan (XYZ or XY) can be configured by setting the PSM bit in CFR0 to '0' and C[3:0] in Control
Byte 1 to '0000' or '0001'. For the host-initiated scan (XYZ or XY), the host must set TSC internal register C[3:0]
in Control Byte 1 to '0000' or '0001' initially after a pen touch is detected; see Conversion Controlled by
TSC2004 Initiated by Host (TSMode 2), in the Theory of Operation section. After the scan (XYZ or XY) is
engaged, the throughput of the processed sample sets is regulated by the selected batch delay timer, as long as
the initial detected touch is not interrupted.
Table 21. Touch Screen Throughput and Batch Selection Bits
BATCH DELAY SELECTION
THROUGHPUT FOR TSC-INITIATED
OR HOST-INITIATED SCAN, XYZ OR XY
(SSPS)
BTD2
BTD1
BTD0
DELAY TIME
(ms)
0
0
0
0
Normal operation throughput depends on settings.
0
0
1
1
1000
0
1
0
2
500
0
1
1
4
250
1
0
0
10
100
1
0
1
20
50
1
1
0
40
25
1
1
1
100
10
For example, if stabilization time, precharge time, and sense time are selected as 100μs, 84μs, and 96μs,
respectively, and the batch delay time is 2ms, then the scan function enters wait mode after the first processed
sample set until the 2ms of batch delay time is reached. When the scan function starts to process the second
sample set (if the screen is still touched), the batch delay restarts at 2ms (in this example). This procedure
remains regulated by 2ms until the pen touch is not detected or the scan function is stopped by a stop bit or any
reset form.
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Configuration Register 2
Configuration register 2 (CFR2) defines the preprocessor configuration.
Table 22. Configuration Register 2 (Reset Value = 0000h)
MSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
D0
PINTS1
PINTS0
M1
M0
W1
W0
TZ1
TZ0
AZ1
AZ0
Resrvd
MAVE
X
MAVE
Y
MAVE
Z
MAVE
AUX
MAVE
TEMP
PINTS1 (default 0)—This bit controls the output format of the PINTDAV pin. When this bit is set to '0', the output
format is shown as the AND-form of internal signals of PENIRQ and DAV). When this bit is set to '1', PINTDAV
outputs PENIRQ only.
PINTS0 (default 0)—This bit selects what is output on the PINTDAV pin. If this bit set to '0', the output format of
PINTDAV depends on the selection made on the PINTS1 bit. If this bit set to '1', the internal signal of DAV is
output on PINTDAV.
Table 23. PINTSx Selection
PINTS1
PINTS0
0
0
PINTDAV PIN OUTPUT =
AND combination of PENIRQ (active low) and DAV (active high).
0
1
Data available, DAV (active low).
1
0
Interrupt, PENIRQ (active low) generated by pen-touch.
1
1
Data available, DAV (active low).
M1, M0, W1, W0 (default 0000)—Preprocessing MAV filter control. Note that when the MAV filter is processing
data, the STS bit and the corresponding DAV bits in the status register will indicate that the converter is busy
until all conversions necessary for the preprocessing are complete. The default state for these bits is 0000,
which bypasses the preprocessor. These bits are the same whether reading or writing.
TZ1 and TZ0, or AZ1 and AZ0 (default 00)—Zone detection bit definition (for TEMP or AUX measurements).
TZ1 and TZ0 are for the TEMP measurement. AZ1 and AZ0 are for the AUX measurement. The action taken in
zone detection is to store the processed data in the corresponding data registers and to update the
corresponding DAV bits in status register. If the processed data do not meet the selected criteria, these data are
ignored and the corresponding DAV bits are not updated. When zone detection is disabled, the processed data
are simply stored in the corresponding data registers and the corresponding DAV bits are updated without any
comparison of criteria. Note that the converted samples are always processed according to the setting of the
MAVE bits for AUX/TEMP before zone detection takes effect. SeeTable 30 for thresholds.
Table 24. Zone Detection Bit Definition
TZ1/AZ1
TZ0/AZ0
0
0
FUNCTION
Zone detection is disabled.
0
1
When the processed data is below low threshold
1
0
When the processed data is between low and high thresholds
1
1
When the processed data is above high threshold
MAVE (default is 00000)—MAV filter function enable bit. When the corresponding bit is set to 1, the MAV filter
setup is applied to the corresponding measurement.
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Converter Function Select Register
The Converter Function Select (CFN) register reflects the converter function select status.
Table 25. Converter Function Select Status Register (Reset Value = 0000h)
MSB
D15
D14
D13
D12
D11
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
D0
CFN9
CFN8
CFN7
CFN6
CFN5
CFN4
CFN3
CFN2
CFN1
CFN0
D10
CFN15 CFN14 CFN13 CFN12 CFN11 CFN10
CFN15-CFN13—Touch screen drivers status. These bits represent the current status of the touch screen drivers
that are turned on. CFN13 is set to '1' if both X+ and X- drivers are turned on. CFN14 is set to '1' if both Y+ and
Y- drivers are turned on. CFN15 is set to '1' if Y+ and X- drivers are turned on. Otherwise, these bits are set to
'0'. These bits are reset to 0h whenever the converter function is either complete, stopped by the STS bit, or
reset (by a hardware reset from the RESET pin or a software reset from SWRST bit in Control Byte 1).
CFN12-CFN0—Converter function select status. These bits represent the converter function currently running,
which is set in bits C3-C0 of Control Byte 1. When the CFNx bit shows '1', where x is the decimal value of
converter function select bits C3-C0, it indicates that the converter function that is set in bits C3-C0 is running.
For example, when CFN2 shows '1', it indicates the converter function set in bits C3-C0 ('0010') is running. The
CFNx bits are reset to 0000h whenever the converter function is complete, stopped by STS bit, or reset (by the
hardware reset from the RESET pin or the software reset from SWRST bit in Control Byte 1). However, if the
TSC-initiated scan function mode is issued (by setting the PSM bit in the CFR0 register to '1'), the CFN0 or
CFN1 bit will not be reset when the corresponding converter function is complete due to no pen touch. This
event allows the TSC2004 to immediately initiate the scan process (corresponding to CFN0 or CFN1 set to '1')
when the next pen touch is detected.
Table 26. STATUS Register (Reset Value = 0004h)
MSB
D15
D14
D13
D12
D11
D10
D9
DAV
Due
X
DAV
Due
Y
DAV
Due
Z1
DAV
Due
Z2
DAV
Due
AUX
DAV
Due
TEMP1
DAV
Due
TEMP2
D8
D7
RESRVD RESET
(read '0')
Flag
D6
D5
D4
D3
D2
D1
LSB
D0
X
CON
Y
CON
RESRVD
(read '0')
Y
SHR
PDST
ID1
ID0
DAV Bits—Data available bits. These seven bits mirror the operation of the internal signals of DAV. When any
processed data are stored in data registers, the corresponding DAV bit is set to '1'. It stays at '1' until the
register(s) updated to the processed data have been read out by the host.
Table 27. DAV Function
DAV
DESCRIPTION
0
No new processed data are available.
1
Processed data are available. This will stay at 1 until the host has read out all updated registers.
RESET Flag—See Table 28 for the interpretation of the RESET flag bits.
Table 28. RESET Flag Bits
RESET Flag
DESCRIPTION
0
Device was reset since last status poll (hardware or software reset).
1
Device has not been reset since last status poll.
X CON—This bit is '1' if the X axis of the touch screen panel is properly connected to the X drivers. This bit is
the connection test result.
Y CON—This bit is '1' if the Y axis of the touch screen panel is properly connected to the Y drivers. This bit is
the connection test result.
Y SHR—This bit is '1' if there is no short-circuit tested at the Y axis of the touch screen panel. This bit is the
short-circuit test result.
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PDST—Power down status. This bit reflects the setting of the PND0 bit in Control Byte 0. When this bit shows
'0', it indicates ADC bias circuitry is still powered on after each conversion and before the next sampling;
otherwise, it indicates ADC bias circuitry is powered down after each conversion and before the next sampling.
However, it is powered down between conversion sets. Because this status bit is synchronized with the internal
clock, it does not reflect the setting of the PND0 bit until a pen touch is detected or a converter function is
running.
ID[1:0] Device ID bits: These bits represent the version ID of TSC2004. This version defaults to '00'.
DATA REGISTERS
The data registers of the TSC2004 hold data results from conversions. All of these registers default to 0000h
upon reset.
X, Y, Z1, Z2, AUX, TEMP1 and TEMP2 REGISTERS
The results of all A/D conversions are placed in the appropriate data registers, as described in Table 10. The
data format of the result word (R) of these registers is right-justified, as shown in Table 29:
Table 29. Internal Register Format
MSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
D0
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Register Map
The TSC2004 has several 16-bit registers that allow control of the device, as well as providing a location to store
results from the TSC2004 until read out by the host microprocessor. Table 30 shows the memory map.
Table 30. Register Content and Reset Values (1)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESET
VALUE
(HEX)
0
X
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0000
1
Y
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0000
2
Z1
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0000
3
Z2
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0000
4
AUX
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0000
5
Temp1
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0000
6
Temp2
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0000
(2)
S3
S2
S1
S0
0004
0FFF
A3-A0
(HEX)
(1)
(2)
REGISTER
NAME
7
Status
8
9
Rsvd
S15
S14
S13
S12
S11
S10
S9
0
S7
S6
S5
AUX High
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
AUX Low
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0000
A
Temp High
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0FFF
B
Temp Low
C
CFR0
0
0
0
0
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0000
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
4000
D
CFR1
0
0
E
CFR2
R15
R14
0
0
R11
R10
R9
R8
0
0
0
0
0
R2
R1
R0
0000
R13
R12
R11
R10
R9
R8
R7
R6
0
R4
R3
R2
R1
R0
F
Converter
Function
Select Status
0000
R15
R14
R13
R12
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
0000
Rsvd
(2)
For all combination bits, the pattern marked as reserved must not be used. The default pattern is read back after reset.
This bit is reserved.
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REGISTER RESET
There are three way to reset the TSC2004. First, at power-on, a power good signal will generate a prolonged
reset pulse internally to all registers.
Second, an external pin, RESET, is available to perform a system reset or allow other peripherals (such as a
display) to reset the device if the pulse meets the timing requirement (at least 10μs wide). Any RESET pulse
less than 5μs will be rejected. To accommodate the timing drift between devices because of process variation, a
RESET pulse width between 5μs to 10μs falls into the gray area that will not be recognized and the result is
undetermined; this situation should be avoided. Refer to Figure 36 for details. A good reset pulse must be low
for at least 10μs. There is an internal spike filter to reject spikes up to 20ns wide.
tWL(RESET) < 5ms
tR
tR
tWL(RESET) ³ 10ms
RESET
State
Normal Operation
Resetting
Initial Condition
Figure 36. External Reset Timing
Finally, a software reset can be activated by writing a '1' to CB1.1 (bit 1 of control byte 1). It should be noted this
reset is not self-cleared, so the user must write a '0' to remove the software reset.
A reset clears all registers and loads default values. A power-on reset and external (hardware) reset take
precedence over a software reset. If a software reset not cleared by the user, it will be cleared by either a
power-on reset or an external (hardware) reset.
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THEORY OF OPERATION
TOUCH SCREEN MEASUREMENTS
As noted previously in the discussion of the A/D converter, several operating modes can be used that allow
great flexibility for the host processor. This section examines these different modes.
Conversion Controlled by TSC2004 Initiated by TSC2004 (TSMode 1)
In TSMode 1, before a pen touch can be detected, the TSC2004 must be programmed with PSM = 1 and one of
two scan modes:
1. X-Y-Z Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0000); or
2. X-Y Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0001).
See Table 7 for more information on the converter function select bits.
When the touch panel is touched, which causes the internal pen-touch signal to activate, the PINTDAV output is
lowered if it is programmed as PENIRQ. The TSC2004 then executes the preprogrammed scan function without
a host intervention.
At the same time, the TSC2004 starts up its internal clock. It then turns on the Y-drivers, and after a
programmed panel voltage stabilization time, powers up the A/D converter and converts the Y coordinate. If
preprocessing is selected, several conversions may take place. When data preprocessing is complete, the Y
coordinate result is stored in a temporary register.
If the screen is still touched at this time, the X-drivers are enabled, and the process repeats, but measuring the
X coordinate instead, and storing the result in a temporary register.
If only X and Y coordinates are to be measured, then the conversion process is complete. A set of X and Y
coordinates are stored in the X and Y registers. Figure 37 shows a flowchart for this process. The time it takes
to go through this process depends upon the selected resolution, internal conversion clock rate, panel voltage
stabilization time, precharge and sense times, and whether preprocessing is selected. The time needed to get a
complete X and Y coordinate (sample set) reading can be calculated by:
ǒ
Ǔ
ǒ ǒ
Ǔ ǒ Ǔ ǒ ǓǓ
f
L
OH DLY1
t COORDINATE + OH1 )2 @ t PVS)t PRE)t SNS)
)2 @ N @ (B)2) @ OSC )OHCONV @ 1 ) PPRO
f OSC
f OSC
f ADC
f OSC
f OSC
(5)
Where:
tCOORDINATE = time to complete X/Y coordinate reading.
tPVS = panel voltage stabilization time, as given in Table 16.
tPRE = precharge time, as given in Table 17.
tSNS = sense time, as given in Table 18.
N = number of measurements for MAV filter input, as given in Table 3 as N.
(For no MAV: M1-0[1:0] = '00', W1-0[1:0] = '00', N = 1.)
B = number of bits of resolution.
fOSC = TSC onboard OSC clock frequency. See Electrical Characteristics for supply frequency (SNSVDD).
fADC = A/D converter clock frequency, as given in Table 15.
OH1 = overhead time #1 = 2.5 internal clock cycles.
OHDLY1 = total overhead time for tPVS, tPRE, and tSNS = 10 internal clock cycles.
OHCONV = total overhead time for A/D conversion = 3 internal clock cycles.
LPPRO = pre-processor preocessing time as given in Table 31.
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THEORY OF OPERATION (continued)
Table 31. Preprocessing Delay
LPPRO =
M=
W=
FOR B = 12 BIT
1
1, 4, 8, 16
2
FOR B = 10 BIT
2
3, 7
1
28
24
7
3
31
27
15
1
31
29
15
3
34
32
15
7
38
36
Programmed for
Self-Control
(PSM = 1)
X-Y Scan Mode
(Control Byte1
D[6:3] = 0001)
TSC
Not Addressed
Reading
X-Data
Register
Reading
Y-Data
Register
tCOORDINATE
Detecting Touch
PINTDAV Programmed:
Sample, Conversion, and
Preprocessing for
Y Coordinate
Touch is Detected
Detecting
Touch
Sample, Conversion, and
Preprocessing for
X Coordinate
Detecting
Touch
Sample, Conversion, and
Preprocessing for
Y Coordinate
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
Touch is Detected
As PENIRQ and DAV,
CFR2, D[15:14] = 00
Figure 37. Example of an X and Y Coordinate Touch Screen Scan using TSMode 1
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If the pressure of the touch is also to be measured, the process continues in the same way, but measuring the
Z1 and Z2 values instead, and storing the results in temporary registers. Once the complete sample set of data
(X, Y, Z1, and Z2) are available, they are loaded in the X, Y, Z1, and Z2 registers. This process is illustrated in
Figure 38. As before, this process time depends upon the settings described above. The time for a complete X,
Y, Z1, and Z2 coordinate reading is given by:
ǒ
ǒ ǒ
Ǔ
Ǔ ǒ Ǔ ǒ ǓǓ
f
L
OH DLY1
t COORDINATE + OH2 )3 @ t PVS)t PRE)t SNS)
)4 @ N @ (B)2) @ OSC )OHCONV @ 1 ) PPRO
f OSC
f OSC
f ADC
f OSC
f OSC
(6)
Where:
OH2 = overhead time #2 = 3.5 internal clock cycles.
Programmed for
Self-Control
(PSM = 1)
X-Y-Z1-Z2 Scan Mode
(Control Byte1
D[6:3] = 0000)
TSC
Not Addressed
Reading
X-Data
Register
Reading Reading
Y-Data Z1-Data
Register Register
Reading
Z2-Data
Register
tCOORDINATE
Detecting
Touch
Sample, Conversion,
Sample, Conversion,
Detecting
Detecting
and Preprocessing for
and Preprocessing for
Touch
Touch
X Coordinate
Y Coordinate
PINTDAV Programmed:
Touch is Detected
Touch is Detected
Sample, Conversion,
Sample, Conversion,
Detecting
and Preprocessing for
and Preprocessing for
Touch
Y Coordinate
Z1 Coordinate and Z2 Coordinate
Detecting
Touch
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
Touch is Detected
As PENIRQ and DAV,
CFR2, D[15:14] = 00
Figure 38. Example of an X, Y, and Z Coordinate Touch Screen Scan using TSMode 1
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Conversion Controlled by TSC2004 Initiated by Host (TSMode 2)
In TSMode 2, the TSC2004 detects when the touch panel is touched and causes the internal Pen-Touch signal
to activate, which lowers the PINTDAV output if it is programmed as PENIRQ. The host recognizes the interrupt
request, and then writes to the A/D Converter Control register to select one of the two touch screen scan
functions:
1. X-Y-Z Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0000); or
2. X-Y Scan (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0001).
See Table 7 for more information on the converter function select bits.
The conversion process then proceeds as shown in Figure 39; see the previous sections for more deatils.
The main difference between this mode and the previous mode is that the host, not the TSC2004, decides when
the touch screen scan begins.
The time needed to convert both X and Y coordinates under host control (not including the time needed to send
the command over the I2C bus) is given by:
ǒ
Ǔ
ǒ ǒ
Ǔ ǒ Ǔ ǒ ǓǓ
f
L
OH DLY1
t COORDINATE + OH1 )2 @ t PVS)t PRE)t SNS)
)2 @ N @ (B)2) @ OSC )OHCONV @ 1 ) PPRO
f OSC
f OSC
f ADC
f OSC
f OSC
Programmed
for
HostControlled
Mode
(PSM = 0)
TSC
Not
Programmed
Addressed
for
TSC
Not Addressed
X-Y
Scan Mode
Reading
X-Data
Register
Reading
Y-Data
Register
TSC
Not Addressed
tCOORDINATE
Detecting
Touch
PINTDAV Programmed:
As PENIRQ,
CFR2, D[15:14] = 10
Waiting for Host to
Write Into
Control Byte 1 D[6:3]
Sample, Conversion,
and Preprocessing for
Y Coordinate
Detecting Sample, Conversion, Detecting Sample, Conversion, Detecting
and Preprocessing for
and Preprocessing for
Touch
Touch
Touch
X Coordinate
Y Coordinate
Touch is Detected
Touch is Detected
As DAV,
CFR2, D[15:14] = 11 or 01
Touch is Still Here
As PENIRQ and DAV,
CFR2, D[15:14] = 00
Figure 39. Example of an X and Y Coordinate Touch Screen Scan using TSMode 2
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Conversion Controlled by Host (TSMode 3)
In TSMode 3, the TSC2004 detects when the touch panel is touched and causes the internal Pen-Touch signal
to be active, which lowers the PINTDAV output if it is programmed as PENIRQ. The host recognizes the
interrupt request. Instead of starting a sequence in the TSC2004, which then reads each coordinate in turn, the
host must now control all aspects of the conversion. Generally, upon receiving the interrupt request, the host
turns on the X drivers. (NOTE: If drivers are not turned on, the device detects this condition and turns them on
before the scan starts. This situation is why the event of turn on drivers is shown as optional in Figure 40 and
Figure 41.) After waiting for the settling time, the host then addresses the TSC2004 again, this time requesting
an X coordinate conversion.
The process is then repeated for the Y and Z coordinates. The processes are outlined in Figure 40 and
Figure 41. Figure 40 shows two consecutive scans on X and Y. Figure 41 shows a single Z scan.
The time needed to convert any single coordinate X or Y under host control (not including the time needed to
send the command over the I2C bus) is given by:
ǒ
Ǔ ǒ
Ǔ ǒ Ǔ ǒ Ǔ
f
L
OHDLY2
t COORDINATE + OH1 ) t PRE)t SNS)
) N @ (B)2) @ OSC )OH CONV @ 1 ) PPRO
f OSC
f OSC
f OSC
f ADC
f OSC
(8)
Where:
OHDLY2 = total overhead time for tPRE and tSNS = 6 internal clock cycles.
Programmed
for HostControlled
Mode
(PSM = 0)
TSC
Not
Addressed
Programmed for:
Turn On
X+ and
XDrivers
(1)
X
Scan
Mode
Programmed for:
TSC
Not
Addressed
Reading
X-Data
Register
Turn On
Y+ and
YDrivers
(1)
Y
Scan
Mode
tCOORDINATE
Detecting
Touch
PINTDAV Programmed:
Waiting for Host to Write Into
Control Byte 1 D[6:3]
Touch is Detected
Sample, Conversion,
and Preprocessing
for X Coordinate
TSC
Not
Addressed
TSC
Not
Reading Addressed
Y-Data
Register
tCOORDINATE
Detecting Waiting for Host to Write Into
Control Byte 1 D[6:3]
Touch
Sample, Conversion,
and Preprocessing
for Y Coordinate
Detecting
Touch
Touch is Detected
Waiting for Host to
Write Into Control
Byte 1 D[6:3]
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
As PENIRQ and DAV,
CFR2, D[15:14] = 00
NOTE: (1) Optional. If not turned on, it will be turned on by the Scan mode, once detected.
Figure 40. Example of X and Y Coordinate Touch Screen Scan using TSMode 3
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The time needed to convert any Z1 and Z2 coordinate under host control (not including the time needed to send
the command over the I2C bus) is given by:
ǒ
Ǔ ǒ
Ǔ ǒ Ǔ ǒ Ǔ
f
L
OHDLY2
t COORDINATE + OH2 ) t PRE)t SNS)
) N @ (B)2) @ OSC )OH CONV @ 1 ) PPRO
f OSC
f OSC
f OSC
f ADC
f OSC
(9)
Programmed for:
TSC
Not
Addressed
Programmed
for
Host-Controlled
Mode
(PSM = 0)
Turn On
Y+
and
XDrivers(1)
TSC
Not Addressed
Z
Scan
Mode
Reading
Z1-Data
Register
TSC
Not Addressed
Reading
Z2-Data
Register
tCOORDINATE
Detecting
Touch
Waiting for Host to Write
Into Control Byte 1 D[6:3]
PINTDAV Programmed:
Sample, Conversion, Sample, Conversion,
and Preprocessing
and Preprocessing
for Z1 Coordinate
for Z2 Coordinate
Detecting
Touch
Touch is Detected
Waiting for Host to Write
Into Control Byte 1 D[6:3]
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
As PENIRQ and DAV,
CFR2D[15:14] = 00
NOTE: (1) Optional. If not turned on, it will be turned on by the Scan mode, once detected.
Figure 41. Example of Z1 and Z2 Coordinate Touch Screen Scan
(without Panel Stabilization Time) using TSMode 3
If the drivers are not turned on before the touch screen scan mode is programmed, the panel stabilization time
should be included. In this case, the time needed to convert any single X or Y under host control (not including
the time needed to send the command over the I2C bus) is given by:
ǒ
Ǔ ǒ
Ǔ ǒ Ǔ ǒ Ǔ
f
L
OH DLY1
t COORDINATE + OH2 ) t PVS)t PRE)t SNS)
) N @ (B)2) @ OSC )OHCONV @ 1 ) PPRO
f OSC
f OSC
f OSC
f ADC
f OSC
Programmed for
Host-Controlled
Mode
(PSM = 0)
TSC
Programmed
Not Addressed
for
TSC
Not Addressed
Z1-Z2
Scan Mode
Reading
Z1-Data
Register
Reading
Z2-Data
Register
TSC
Not Addressed
tCOORDINATE
Detecting
Touch
Waiting for Host to Write
Into Control Byte 1 D[6:3]
PINTDAV Programmed:
Sample, Conversion, and
Preprocessing for Z1, Z2 Coordinates
Detecting
Touch
Waiting for Host to Write
Into Control Byte 1 D[6:3]
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
Touch is Still Here
As PENIRQ and DAV,
CFR2D[15:14] = 00
Figure 42. Example of a Z1 and Z2 Coordinate Touch Screen Scan
(with Panel Stabilization Time) using TSMode 3
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The time needed to convert any single coordinate (either X or Y) under host control (not including the time
needed to send the command over the I2C bus) is given by:
ǒ
Ǔ ǒ
Ǔ ǒ Ǔ ǒ Ǔ
f
L
OH DLY1
t COORDINATE + OH1 ) t PVS)t PRE)t SNS)
) N @ (B)2) @ OSC )OHCONV @ 1 ) PPRO
f OSC
f OSC
f OSC
f ADC
f OSC
TSC
Programmed
Not Addressed
for
Programmed for
Host-Controlled
Mode
(PSM = 0)
TSC
Not Addressed
X
Scan Mode
Reading
X-Data
Register
(11)
TSC
Not Addressed
tCOORDINATE
Detecting
Touch
Waiting for Host to Write
Into Control Byte 1 D[6:3]
Sample, Conversion, and
Preprocessing for X Coordinate
Detecting
Touch
Waiting for Host to Write
Into Control Byte 1 D[6:3]
PINTDAV Programmed:
Touch is Detected
As PENIRQ,
CFR2, D[15:14] = 10
As DAV,
CFR2, D[15:14] = 11 or 01
Touch is Still Here
As PENIRQ and DAV,
CFR2, D[15:14] = 00
Figure 43. Example of a Single X Coordinate Touch Screen Scan
(with Panel Stabilization Time) using TSMode 3
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AUXILIARY AND TEMPERATURE MEASUREMENT
The TSC2004 can measure the voltage from the auxiliary input (AUX) and from the internal temperature sensor.
Applications for the AUX can include external temperature sensing, ambient light monitoring for controlling
backlighting, or sensing the current drawn from batteries. There are two converter functions that can be used for
the measurement of the AUX:
1. Non-continuous AUX measurement shown in Figure 44 (converter function select bits C[3:0] = Control
Byte 1 D[6:3] = 0101); or
2. Continuous AUX Measurement shown in Figure 45 (converter function select bits C[3:0] = Control Byte 1
D[6:3] = 1000).
See Table 7 for more information on the converter function select bits.
There are also two converter functions for the measurement of the internal temperature sensor:
1. TEMP1 measurement (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0110); or
2. TEMP2 measurement (converter function select bits C[3:0] = Control Byte 1 D[6:3] = 0111).
See Table 7 for more information on the converter function select bits.
For the detailed calculation of the internal temperature sensor, please see the SubSec1 9.3 section. These two
converter functions have the same timing as the non-continuous AUX measurement operation as shown in
Figure 44; therefore, Equation 12 can also be used for internal temperature sensor measurement. The time
needed to make a non-continuous auxiliary measurement or an internal temperature sensor measurement is
given by:
ǒ
Ǔ ǒ Ǔ ǒ Ǔ
f
L
t COORDINATE + OH3 ) N @ (B)2) @ OSC )OH CONV @ 1 ) PPRO
f OSC
f OSC
f ADC
f OSC
(12)
Where:
OH3 = overhead time #3 = 3.5 internal clock cycles.
TSC
Not Addressed
Programmed for
Non-Continuous
AUX Measurement
TSC
Not Addressed
TSC
Not Addressed
Reading
AUX-Data
Register
tCOORDINATE
No Touch
Detected
Host Write to
Control Byte 1 D[6:3]
Sample, Conversion, and
Averaging for AUX Measurement
No Touch
Detected
Waiting for Host to
Read AUX Data
As DAV
Figure 44. Non-Touch Screen, Non-Continuous AUX Measurement
The time needed to make continuous auxiliary measurement is given by:
ǒ
Ǔ ǒ Ǔ ǒ Ǔ
f
L
t COORDINATE + OH3 ) N @ (B)2) @ OSC )OH CONV @ 1 ) PPRO
f OSC
f OSC
f ADC
f OSC
TSC
Not Addressed
No Touch
Detected
Programmed for
Continuous
AUX Measurement
Host to Write to
Control Byte 1 D[6:3]
(13)
TSC
TSC
Not
Reading Not Addressed Reading Addressed
AUX-Data
AUX-Data
Register
Register
TSC
Not Addressed
tCOORDINATE
tCOORDINATE
tCOORDINATE
Sample, Conversion,
and Averaging for
AUX Measurement
Sample, Conversion,
and Averaging for
AUX Measurement
Sample, Conversion,
and Averaging for
AUX Measurement
As DAV
Figure 45. Non-Touch Screen, Continuous AUX Measurement
48
Submit Documentation Feedback
TSC2004
www.ti.com
SBAS408A – JUNE 2007 – REVISED AUGUST 2007
LAYOUT
The following layout suggestions should obtain optimum performance from the TSC2004. However, many
portable applications have conflicting requirements for power, cost, size, and weight. In general, most portable
devices have fairly clean power and grounds because most of the internal components are very low power. This
situation would mean less bypassing for the converter power and less concern regarding grounding. Still, each
situation is unique and the following suggestions should be reviewed carefully.
For optimum performance, care should be taken with the physical layout of the TSC2004 circuitry. The basic
SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore,
during any single conversion for an n-bit SAR converter, there are n windows in which large external transient
voltages can easily affect the conversion result. Such glitches might originate from switching power supplies,
nearby digital logic, and high power devices. The degree of error in the digital output depends on the reference
voltage, layout, and the exact timing of the external event. The error can change if the external event changes in
time with respect to the SCL input.
With this in mind, power to the TSC2004 should be clean and well-bypassed. A 0.1μF ceramic bypass capacitor
should be added between (SNSVDD to AGND and SNSGND) or (I/OVDD to DGND). A 0.1μF decoupling
capacitor between VREF to AGND is also needed unless the SNSVDD is used as a reference input and is
connected to VREF. These capacitors need to be placed as close to the device as possible. A 1μF to 10μF
capacitor may also be needed if the impedance of the connection between SNSVDD and the power supply is
high. The I/OVDD needs to be shorted to the same supply plane as the SNSVDD. Short both SNSVDD and
I/OVDD to the analog VDD plane.
The TSC2004 architecture offers no inherent rejection of noise or voltage variation in regards to using an
external reference input, which is of particular concern when the reference input is tied to the power supply. Any
noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be
filtered out, voltage variation due to line frequency (50Hz or 60Hz) can be difficult to remove. Some package
options have pins labeled as VOID. Avoid any active trace going under those pins marked as VOID unless they
are shielded by a ground or power plane.
All GND (AGND, DGND, SUBGND and SNSGND) pins should be connected to a clean ground point. In many
cases, this point will be the analog ground. Avoid connections that are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the
power-supply entry or battery connection point. The ideal layout includes an analog ground plane dedicated to
the converter and associated analog circuitry.
In the specific case of use with a resistive touch screen, care should be taken with the connection between the
converter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnection
should be as short and robust as possible. Loose connections can be a source of error when the contact
resistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of error in touch-screen applications (for example,
applications that require a back-lit LCD panel). This electromagnetic interfence (EMI) noise can be coupled
through the LCD panel to the touch screen and cause flickering of the converted ADC data. Several things can
be done to reduce this error, such as using a touch screen with a bottom-side metal layer connected to ground,
which will couple the majority of noise to ground. Additionally, filtering capacitors, from Y+, Y–, X+, and X– to
ground, can also help. Note, however, that the use of these capacitors increases screen settling time and
requires longer panel voltage stabilization times, and also increases precharge and sense times for the
PINTADV circuitry of the TSC2004. The resistor value varies depending on the touch screen sensor used. The
internal 51kΩ resistor (RIRQ) may be adequate for most of sensors.
Submit Documentation Feedback
49
PACKAGE OPTION ADDENDUM
www.ti.com
7-Aug-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TSC2004IRTJR
PREVIEW
QFN
RTJ
20
3000
TBD
Call TI
Call TI
TSC2004IRTJT
PREVIEW
QFN
RTJ
20
250
TBD
Call TI
Call TI
TSC2004IYZKR
PREVIEW
DSBGA
YZK
24
3000
TBD
Call TI
Call TI
TSC2004IYZKT
PREVIEW
DSBGA
YZK
24
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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designed into the PCB. This design optimizes the heat transfer from the integrated circuit (IC).
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