[AK4186] AK4186 Low Power Touch Screen Controller with I2C Interface GENERAL DESCRIPTION The AK4186 is a 4-wire/ 5-wire resistive touch screen controller that incorporates 12bit SAR A/D converter. The AK4186 can detect the pressed screen location with two A/D conversions and it can also measure touch pressure. The AK4186 has both an automatic continuous measurement and a measurement data calculation function. The functions that normally require external processing, such as calculating the average screen input value, are processed by the AK4186. In addition, a new sequential mode achieves short coordinate measurement time while greatly reducing the microprocessor overhead. The AK4186 operates off of supply voltage down to 1.6V in order to connect a low voltage microprocessor. The AK4186 is the best fit for cellular phone, DSC, DVC, smart phone and other portable devices. ! ! ! ! ! ! ! ! ! ! ! ! ! FEATURES 4-wire or 5-wire Touch Screen Interface I2C Serial Interface 12bit SAR A/D Converter with S/H circuit Sampling Rate: 22.2kHz Pen Pressure Measurement (4-wire) Continuous Read Function Integrated Internal Osc (Sequence Mode) Integrated Median Averaging Filter Low Voltage Operation: VDD = 1.6V ~ 3.6V PENIRQN Buffer Output Low Power Consumption: 60µA at 1.8V Auto Power Down Package: 12pin CSP (1.7mm x 1.3mm, pitch 0.4mm) 16pin QFN (3mm x 3mm, pitch 0.5mm) VDD TEST XP/BR YP/TR XN/TL 4/5wire Touch Screen Drivers Interface I2 C VREF+ MUX AIN+ SAR ADC AIN- YN/BL Serial I/F & Control Logic CAD0 SCL SDA VREF- IN/ WIPER PENIRQN Internal Osc VSS Figure 1. Block Diagram MS1068-E-04 I2C-bus is a trademark of NXP B.V. 2011/03 -1- [AK4186] ■ Ordering Guide AK4186ECB AK4186EN AKD4186 AKD4186EN −40 ∼ +85°C 12pin CSP (1.66mm x 1.26mm, 0.4mm pitch) −40 ∼ +85°C 16pin QFN (3mm x 3mm, 0.5mm pitch) AK4186ECB Evaluation Board AK4186EN Evaluation Board Black Type ■ Pin Layout AK4186ECB 3 AK4186ECB 2 Top View 1 A B C D 3 XP/BR YP/TR XN/TL YN/BL 2 VDD CAD0 TEST VSS 1 IN/WIPER PENIRQN SDA SCL A B C D TOP View YN/BL XN/TL YP/TR XP/BR 11 10 9 6 IN/WIPER 5 NC 4 16 Top View CAD0 NC VDD 3 15 7 PENIRQ TEST AK4186EN 2 14 NC SDA VSS 8 1 13 SCL NC 12 AK4186EN MS1068-E-04 2011/03 -2- [AK4186] PIN/FUNCTION Pin No. ECB EN D1 1 C1 2 B1 3 Pin Name Function I/O I2C Serial Clock Input I2C Serial Data Input/ Output Pen Interrupt Output (CMOS output) The PENIRQN pin is “L” when touch-screen press is detected. This pin is always “L” irrespective of touch-screen press when pen interrupt is not enabled. B2 4 CAD0 I I2C Slave Address bit 0 5 NC No Connection. No internal bonding. This pin must be connected to VSS. A1 6 IN I Auxiliary Analog Input (4-wire, PANEL bit = “0”) WIPER I Top Touch Panel Input (5-wire, PANEL bit = “1”) A2 7 VDD Power Supply and External Reference Input: 1.6V ~ 3.6V 8 NC No Connection. No internal bonding. This pin must be connected to VSS. A3 9 XP I/O Touch Panel X+ Input (4-wire, PANEL bit = “0”) BR I/O Touch Panel Bottom Right Input (5-wire, PANEL bit = “1”) B3 10 YP I/O Touch Panel Y+ Input (4-wire, PANEL bit = “0”) TR I/O Touch Panel Top Right Input (5-wire, PANEL bit = “1”) C3 11 XN I/O Touch Panel X- Input (4-wire, PANEL bit = “0”) TL I/O Touch Panel Top Left Input (5-wire, PANEL bit = “1”) D3 12 YN I/O Touch Panel Y- Input (4-wire, PANEL bit = “0”) BL I/O Touch Panel Bottom Left Input (5-wire, PANEL bit = “1”) 13 NC No Connection. No internal bonding. This pin must be connected to VSS. D2 14 VSS Ground C2 15 TEST I TEST pin This pin must be connected to VSS. 16 NC No Connection. No internal bonding. This pin must be connected to VSS. Note 1. All digital input pins (CAD0, SCL, SDA) must not be left floating. SCL SDA PENIRQN I I/O O MS1068-E-04 2011/03 -3- [AK4186] ■ Handling of Unused Pin The unused I/O pin must be processed appropriately as below. Classification Analog Pin Name IN/WIPER Setting This pin must be open. ABSOLUTE MAXIMUM RATINGS (VSS = 0V (Note 2)) Parameter Symbol min max Units Power Supply VDD -0.3 4.6 V Input Current, Any Pins except for supply IIN mA ±10 Touch Panel Drive Current IOUTDRV 50 mA Input Voltage (Note 3) VIN VDD+0.3 or 4.6 V −0.3 Ambient Temperature (power applied) Ta -40 85 °C Storage Temperature Tstg -65 150 °C Note 2. All voltages with respect to ground. Note 3. XP/BR, XN/TL, YP/TR, YN/TL, IN/WIPER, CAD0, SCL and SDA pins. Max is smaller value between (VDD+0.3)V and 4.6V. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMEND OPERATING CONDITIONS (VSS = 0V (Note 2)) Parameter Symbol min typ Power Supply VDD 1.6 1.8 Note 2. All voltages with respect to ground. max 3.6 Units V WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1068-E-04 2011/03 -4- [AK4186] ANALOG CHARACTERISTICS (Ta = -40°C to 85°C, VDD = 1.8V, I C bus SCL=400kHz) Parameter min typ max Units A/D Converter Resolution 12 Bits No Missing Codes 11 12 Bits Integral Nonlinearity (INL) Error ±2 LSB Differential Nonlinearity (DNL) Error -2 ±1 +3 LSB Offset Error AK4186ECB ±6 LSB AK4186EN -4 +8 LSB Gain Error AK4186ECB ±4 LSB AK4186EN -4.5 +3.5 LSB Throughput Rate 22.2 kHz Touch Panel Drivers Switch On-Resistance XP, YP 6 Ω XN, YN 6 Ω PENIRQ Pull Up Resistor RIRQ 50 kΩ Auxiliary IN Input Input Voltage Range 0 VDD V Power Supply Current Normal Mode (Single mode, PD0 bit = “0”) VDD=1.8V 60 μA (Note 4) 220 VDD=3.6V μA Normal Mode (Sequence mode, 10kHz equal rate) (Note 5) 25 μA Full Power Down (SDA = SCL = “H”) 0 3 μA Note 4. Continuous ADC data read (fs = 22.2kHz). Expect for Power Consumption of Touch Panel driver. Note 5. COUNT bit = “1”, INTERVAL2-0 bits = 000. Write command cycle = 1kHz. Expect for Power Consumption of Touch Panel driver. 2 DC CHARACTERISTTICS (Logic I/O) (Ta=-40°C to 85°C, VDD =1.6V to 3.6V) Parameter Symbol min typ “H” level input voltage VIH 0.8xVDD “L” level input voltage VIL Input Leakage Current IILK -10 VOH VDD-0.3 “H” level output voltage (PENIRQN pin @ Iout = -250μA) “L” level output voltage (PENIRQN pin @ Iout = 250μA) VOL (SDA pin @ Iout = 3mA) Tri-state Leakage Current (Note 6) IOLK All pins expect for XP, YP, XN, YN pins -10 XP, YP, XN, YN pins -10 Note 6. Expect for TEST pin. TEST pin has internal pull-down device, nominally 100kΩ. MS1068-E-04 max 0.2xVDD 10 - Units V V μA V 0.3 V 10 10 μA μA 2011/03 -5- [AK4186] SWITCHING CHARACTERISTICS (Ta=-40°C to 85°C, VDD=1.6V to 3.6V) Parameter Symbol min Internal OSCILATOR Clock Frequency fOSC 2.5 Touch Panel (A/D Converter) SCL clock frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time (prior to first Clock pulse) tHD:STA 0.6 Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 7) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Pulse Width of Spike Noise Suppressed By Input Filter tSP 0 Capacitive load on bus Cb Note 7: Data must be held for sufficient time to bridge the 300ns transition time of SCL. typ max Units 3.6 5.1 MHz - 400 0.3 0.3 50 400 kHz μs μs μs μs μs μs μs μs μs μs ns pF VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start Figure 2. Timing Diagram MS1068-E-04 2011/03 -6- [AK4186] OPERATION OVERVIEW ■ Function Overview The AK4186 consists of the following blocks: ● 1.6V Successive Approximation Resister (SAR) A/D converter ● 4-wire or 5-wire resistive touch screen controller interface ● Single or Continuous A/D conversion ● Internal Clock for SAR A/D Converter ● I2CTM I/F ■ A/D Converter for Touch Screen The AK4186 integrates a 12bit successive approximation resistor (SAR) A/D converter for position measurement, temperature, and auxiliary input. The architecture is based on capacitive redistribution algorithm, and an internal capacitor array functions as the sample/hold (S/H) circuit. The SAR A/D converter output is a straight binary format as shown below: Input Voltage Output Code FFFH (ΔVREF-1.5LSB)~ ΔVREF FFEH (ΔVREF-2.5LSB) ~ (ΔVREF-1.5LSB) ----------------0.5LSB ~ 1.5LSB 001H 0 ~ 0.5LSB 000H ΔVREF: (VREF+) – (VREF-) Table 1. Output Code The fOSC clock of an internal oscillator is used for A/D conversion. The full scale (ΔVREF) of the A/D converter depends on the input mode. Position and pen pressure are measured in differential mode, and then IN is measured in single-ended mode. The AK4186 is controlled by 8bit serial command. A/D conversion result is 12bit data output on the SDA pin. ■ Analog Inputs The analog input channel is automatically selected in sequential measurement mode. When position detection (X-axis and Y-axis) and pen pressure are selected as analog inputs in differential mode, the full scale (ΔVREF) is the voltage difference between the non-inverting terminal and the inverting terminal of the measured axis (e.g. X-axis measurement: (XP) – (XN)). Analog input to A/D converters (ΔAIN) is the voltage difference between the noninverting terminal of the non-measured axis and the inverting terminal of the measured axis. At single-ended mode, the full scale of A/D converter (ΔVREF) is the voltage difference between the VDD and the VSS. The analog input of A/D converter (ΔAIN) is the voltage difference between the selected channel (IN) and the VSS. If the source of analog input is high impedance, longer tracking time is required. Then A/D conversion should be started. Channel Selection AIN Measure X-axis Measure Y-axis Measure Z1 Measure (Pressure) Z2 Measure (Pressure) Status of Driver Switch X-Driver Y-Driver OFF OFF ON OFF OFF ON XN-ON YP-ON XN-ON YP-ON ADC input (ΔAIN) AIN+ AININ GND YP XN XP YN XP XN YN XN Reference Voltage (ΔVREF) VREF+ VREFVREF GND XP XN YP YN YP XN YP XN Ref. Mode SER DFR DFR DFR DFR Table 2. Measurement Mode (4-wire) MS1068-E-04 2011/03 -7- [AK4186] Status of Driver Switch TL-Driver BR-Driver ON OFF OFF ON Channel Selection X-axis Measure Y-axis Measure ADC input (ΔAIN) AIN+ AINWIPER TL WIPER BR Reference Voltage (ΔVREF) VREF+ VREFBR TL TL BR Ref. Mode DFR DFR Table 3. Measurement Mode (5-wire) ■ Position Detection of Touch Screen 1. The Position Detection for 4-wire Touch Screen The position on the touch screen is detected by taking the voltage of one axis when the voltage is supplied between the two terminals of another axis. At least two A/D conversions are needed to get the two-dimensions (X/Y-axis) position. VDD VDD X-Plate XP-Driver SW ON XP VREF+ AIN+ YP ADC VREF X-Plate YP-Driver SW ON XP Y-Plate VREF+ AIN+ VREF- AIN- ADC AINXN Y-Plate YP XN XN-Driver SW ON YN a) YN-Driver SW ON X-Position Measurement Differential Mode b) YN Touch Screen Y-Position Measurement Differential Mode The X-plate and Y-plate are connected on the dotted line when the panel is touched. X+ X-Plate (Top side) X- Y-Plate (Bottom side) Y- Y+ c) 4-wire Touch Screen Construction Figure 3. Axis Measurements for 4-wire Touch Screen MS1068-E-04 2011/03 -8- [AK4186] 2. The Position Detection for 5-wire Touch Screen A 5-wire touch panel consists of one transparent resistive layer and a top metal contact area separated by insulating spacers. The top layer acts only as a voltage measuring probe, the position detection uses the bottom resistive layer that had metal contacts at the 4 corners. When the top layer is pressed by a pen or stylus, the top layer contacts with the bottom layer. Then the X and Y coordinates is detected. The 5-wire touch screen works properly even with damages or scratches on the top layer, therefore the 5-wire touch panel has higher durability than the 4-wire touch panel. Connect the metal contact of the top layer to the WIPER pin to measure the Y-axis of current position at AIN+. The top right and top left contacts at the 4 corners are connected to VDD and the bottom right and bottom left contacts connected to VSS. Then the AK4186 initiates A/D conversion of AIN+ input voltage, and Y-axis position is determined. Terminal X-axis Y-axis SW TL TR BL BR VSS VDD VSS VDD VDD VDD VSS VSS Switch VDD VSS Switch VDD/VSS ON/OFF ON/OFF VDD/VSS Table 4. Driver SW configuration VDD VDD VDD TR SW ON VDD BR SW ON VREF+ TL SW ON BR TR TR SW ON WIPER AIN+ VREF+ ADC AIN+ WIPER ADC TL AIN- VREF TL TR VREF- AIN- TL SW ON BL BR BL SW ON BL BL SW ON BR SW ON a) X-Position Measurement Differential Mode b) Y-Position Measurement Differential Mode The Top layer and Bottom layer are connected on the dotted line when the panel is touched. Detection side (Top layer) ADC WIPER TL BL TR Drive side (Bottom Layer) BR 5-wire Touch Screen Construction Figure 4. Axis Measurements for 5-wire Touch Screen MS1068-E-04 2011/03 -9- [AK4186] ■ Pen Pressure Measurement (Only 4-wire Touch Screen) The touch screen pen pressure can be derived from the measurement of the contact resistor between two plates. The contact resistance depends on the size of the depressed area and the pressure. The area of the spot is proportional to the contact resistance. This resistance (Rtouch) can be calculated using two different methods. The first method is that when the total resistance of the X-plate sheet is already known. The resistance, Rtouch, is calculated from the results of three conversions, X-position, Z1-position, and Z2-position, and then using following formula: R TOUCH = R X -plate ⋅ X Position 4096 ⎛ Z2 ⎞ ⎜⎜ − 1⎟⎟ ⎝ Z1 ⎠ The second method is that when both the resistances of the X-plate and Y-plate are known. The resistance, Rtouch, is calculated from the results of three conversions, X-position, Y-position, and Z1-position, and then using the following formula: R X -plate ⋅ X Position ⎛ 4096 ⎞ ⎛ Y ⎞ ⎜⎜ − 1⎟⎟ − R Y-plate ⋅ ⎜1 - Position ⎟ 4096 ⎝ 4096 ⎠ ⎠ ⎝ Z1 R TOUCH = VDD VDD ON ON YP YP XP VREF+ AIN+ VREF- AIN- touch ADC XP VREF+ AIN+ VREF- AIN- touch ADC XN XN ON ON YN a) YN b) Z1-Position Measurement Differential Mode Z2-Position Measurement Differential Mode Figure 5. Pen Pressure Measurements MS1068-E-04 2011/03 - 10 - [AK4186] ■ Digital I/F The AK4186 is controlled by a microprocessor via I2C bus and supports standard mode (100kHz) and fast mode (400kHz). Note that the AK4186 operates in those two modes and does not support a High speed mode I2C-bus system (3.4MHz). The AK4186 can operate as a slave device on the I2C bus network. The AK4186 operates off of supply voltage down to 1.6V in order to connect a low voltage microprocessor. VDD=1.6V ~ 3.6V Rp CAD0 AK4186 “L” or “H” SCL SDA 4/5-wire touch panel Rp MicroProcessor 2 I C bus Controller PENIRQN Figure 6. Digital I/F 1. WRITE Operations Figure 7 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 11). After the START condition, a slave address is sent. This address is 6 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave address are fixed as “100100”. The next bit is CAD0 (device address bit). This bit identify the specific device on the bus. The hard-wired input pin (CAD0 pin) set this device address bit (Figure 8). If the slave address matches that of the AK4186, the AK4186 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 12). R/W bit value of “1” indicates that the read operation is to be executed. “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4186. The format is MSB first, and those most significant two bits are fixed to zeros (Figure 9). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 10). The AK4186 generates an acknowledge after each byte is received. A data transfer is always terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 11). The AK4186 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4186 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1FH prior to generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 13) except for the START and STOP conditions. MS1068-E-04 2011/03 - 11 - [AK4186] S T A R T Data (n+x) P AK4186 ACK AK4186 ACK Data (n+1) AK4186 ACK AK4186 ACK Data (n) AK4186 ACK Sub Address(n) Slave Address S AK4186 ACK SDA S T O P R/W = “0” Figure 7. Data Transfer Sequence at the I2C-Bus Mode 1 0 0 1 0 0 CAD0 R/W A2 A1 A0 D2 D1 D0 (This CAD0 should match with CAD0 pin.) Figure 8. The First Byte 0 0 A5 A4 A3 Figure 9. The Second Byte D7 D6 D5 D4 D3 Figure 10. Byte Structure after the second byte SDA SCL S P start condition stop condition Figure 11. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START CONDITION Figure 12. Acknowledge on the I2C-Bus MS1068-E-04 2011/03 - 12 - [AK4186] SDA SCL data line stable; data valid change of data allowed Figure 13. Bit Transfer on the I2C-Bus 2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4186. (1) Register READ Operation After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1FH prior to generating stop condition, the address counter will “roll over” to 00H and the data of 00H will be read out. The register read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit “1”. The AK4186 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge but generates stop condition instead, the AK4186 ceases transmission. A/D conversion data in sequence mode can be read when the data is available. Data (n+x) P MASTR NACK Data (n+1) Data (n) MASTR ACK Slave Address MASTR ACK S S T O P R/W= “1” MASTR ACK Sub Address(n) Slave Address S T A R T AK4186 ACK S AK4186 ACK SDA R/W= “0” AK4186 ACK S T A R T Figure 14. Register Address Read (2) A/D Measurement Operation When the master send a READ command after sending a control register address for a measurement channel by a WRITE operation, the AK4186 starts A/D conversion in single mode. The master issues the slave address with the R/W bit “1”. The AK4186 then generates an acknowledge, and outputs ADC data. The ADC data is 2 bytes format (MSB first), and upper 12-bit are valid and lower 4-bit are filled with “0”. (Figure 17, Figure 18) The master receives the first byte, and generates an acknowledge. Then the master receives the second byte and does not generate an acknowledge, the AK4186 ceases transmission. (Figure 15) If the master generates an acknowledge, the AK4186 newly repeats A/D conversion to set the channel every read cycle, and the master can receive update ADC data on each read operation. The AK4186 repeats A/D conversion and continuously outputs ADC data until the master does not generate an acknowledge but generates a stop condition instead. (Figure 16) This continuous read mode enables the higher sampling rate and lower processor load than a single ADC data read. MS1068-E-04 2011/03 - 13 - [AK4186] Slave Address S ADC Data (High Byte) ADC Data (Low Byte) P MASTER NACK Sub Address(n) MASTER ACK Slave Address S T O P R/W= “1” AK4186 ACK S AK4186 ACK SDA S T A R T R/W= “0” AK4186 ACK S T A R T Figure 15. Single ADC Data Read MASTER ACK ADC Data (Low Byte) MASTER ACK ADC Data (Low Byte) P MASTER NACK ADC Data (High Byte) S T O P MASTER ACK ADC Data (Low Byte) MASTER ACK ADC Data (High Byte) ADC Data (High Byte) Slave Address MASTER ACK S MASTER ACK Sub Address(n) Slave Address R/W= “1” AK4186 ACK S AK4186 ACK SDA S T A R T R/W= “0” AK4186 ACK S T A R T Figure 16. Continuous ADC Data Read D11 D10 D9 D8 D7 D6 D5 D4 0 0 Figure 17. ADC Data (High Byte) D3 D2 D1 D0 0 0 Figure 18. ADC Data (Low Byte) MS1068-E-04 2011/03 - 14 - [AK4186] ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 SRST PANEL 0 SLEEP1 SLEEP0 0 0 0 PD0 Sequence Command 0 SEQM2 SEQM1 SEQM0 COUNT Reserved 0 0 0 0 0 0 0 0 Status CHST3 CHST2 CHST1 CHST0 SEQST3 SEQST2 SEQST1 SEQST0 11H Sequence Data 1H D1T11 D1T10 D1T9 D1T8 D1T7 D1T6 D1T5 D1T4 12H Sequence Data 1L D1T3 D1T2 D1T1 D1T0 0 0 0 0 13H Sequence Data 2H D2T11 D2T10 D2T9 D2T8 D2T7 D2T6 D2T5 D2T4 00H System Reset 01H Setup Command 02H 03H -0FH 10H INTERVAL2 INTERVAL1 INTERVAL0 14H Sequence Data 2L D2T3 D2T2 D2T1 D2T0 0 0 0 0 15H Sequence Data 3H D3T11 D3T10 D3T9 D3T8 D3T7 D3T6 D3T5 D3T4 16H Sequence Data 3L D3T3 D3T2 D3T1 D3T0 0 0 0 0 17H Sequence Data 4H D4T11 D4T10 D4T9 D4T8 D4T7 D4T6 D4T5 D4T4 18H 19H -1FH 20H Sequence Data 4L D4T3 D4T2 D4T1 D4T0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 Single XH XS11 XS10 XS9 XS8 XS7 XS6 XS5 XS4 21H Single XL XS3 XS2 XS1 XS0 0 0 0 0 22H Single YH YS11 YS10 YS9 YS8 YS7 YS6 YS5 YS4 23H Single YL YS3 YS2 YS1 YS0 0 0 0 0 24H Single Z1H Z1S11 Z1S10 Z1S9 Z1S8 Z1S7 Z1S6 Z1S5 Z1S4 25H Single Z1L Z1S3 Z1S2 Z1S1 Z1S0 0 0 0 0 26H Single Z2H Z2S11 Z2S10 Z2S9 Z2S8 Z2S7 Z2S6 Z2S5 Z2S4 27H Single Z2L Z2S3 Z2S2 Z2S1 Z2S0 0 0 0 0 28H Single INH INS11 INS10 INS9 INS8 INS7 INS6 INS5 INS4 29H Single INL INS3 INS2 INS1 INS0 0 0 0 0 Table 5. AK4186 Register Map MS1068-E-04 2011/03 - 15 - [AK4186] ■ System Reset Upon power-up, the AK4186 must be reset by writing the reset command. (Refer to the “■ Power-up Sequence” for details) This ensures that all internal register reset to their initial values (00H) and set the channel to X-axis (auto driver = OFF). The System reset can also stop a sequential measurement forcibly, but all data will be cleared. S T A R T Sub Address Reset Command P AK4186 ACK Slave Address AK4186 ACK S AK4186 ACK SDA S T O P R/W= “0” Figure 19. Data Transfer Sequence at the System Reset 1 0 0 1 0 0 CAD0 R/W (Those CAD1/0 should match with CAD1/0 pins.) Figure 20. The First Byte 0 0 0 0 0 0 0 0 0 0 1 Figure 21. The Second Byte 0 0 0 0 0 Figure 22. Byte Structure at Reset Command ■ Setup Function of Touch Panel 1. Setup Command Configuration Addr 01H Register Name Setup Command D7 D6 D5 D4 D3 D2 D1 D0 PANEL 0 SLEEP1 SLEEP0 0 0 0 PD0 Table 6. Setup Command Register Format MS1068-E-04 2011/03 - 16 - [AK4186] Bits D7 Name PANEL D6 D5-D4 Reserved SLEEP1-0 D3 D2 D1 D0 Reserved Reserved Reserved PD0 Description Panel type Selection 0: 4-wire (default) 1: 5-wire Must write “0” Sleep Command bits (refer to “■ Sleep Mode”) 00: Normal Mode (default) 01: Sleep Mode 1 (PENIRQN disabled and output “H”. Touch Panel is open.) 10: Sleep Mode 2 (PENIRQN disabled and open. Touch Panel is open.) 11: Reserved Must write “0” Must write “0” Must write “0” Power-down Mode (refer to “■ Power-down Control”) 0: Auto Power-down Mode (default) 1: Driver ON Mode Table 7. Setup Command description SLEEP1-0, PD0 bits can be written during a sequential measurement but PANEL bit will not be changed. 2. Sequence Command Configuration Addr 02H Register Name Sequence Command D7 D6 D5 D4 D3 D2 D1 D0 0 SEQM2 SEQM1 SEQM0 COUNT INTERVAL2 INTERAVAL1 INTERVAL0 Table 8. Sequence Command Register Format The AK4186 starts A/D conversion in sequence mode by setting the COUNT, SEQM2-0, INTERVAL2-0 bits of the register address to 02H. The AK4186 makes six or ten measurements by setting the COUNT bit. The results are used to calculate the average value, discarding the minimum and maximum values, and the result sets the data register of sequence mode. If the address 02H is set again during a sequential measurement, this setting is ignored and the AK4186 continues the measurement. The master executes the register read operation to read the measurement data of sequence mode after confirming the PENIRQN pin turns to “H” (Data Available). Bits D7 D6-D4 Name Reserved SEQM2-0 D3 COUNT D2-D0 INTERVAL2-0 Description Must write “0” Sequence Mode 000: X → Y → Z1 → Z2 Scan (only 4-wire Touch Screen) (default) 001: X → Y Scan 010: X Scan 011: Y Scan 100: Z1 → Z2 Scan (only 4-wire Touch Screen) 101: Reserved 110: A-IN (only 4-wire Touch Screen) 111: Reserved A/D Conversion count 0: 6 times A/D Conversion (default) 1: 10 times A/D Conversion Sampling interval times. 000: 0μs (default) 001: 5μs 010: 10μs 011: 20μs 100: 50μs 101: 100μs 110: 200μs 111: 500μs Table 9. Sequence Command description MS1068-E-04 2011/03 - 17 - [AK4186] ■ Data Register 1. Sequence Mode Data Register The AK4186 starts A/D conversion in sequence mode by setting the COUNT, SEQM2-0, INTERVAL2-0 bits of the register address 02H. The AK4186 makes six or ten measurements by setting the COUNT bit. The results are used to calculate the average value, discarding the minimum and maximum values, and the result sets the data register of sequence mode. The AK4186 registers data from address 11H in order of setting the SEQM2-0 bits. The master can read the ADC data by the register read operation after confirming the PENIRQN pin turns to “H” or a register status SEQST3-0 = 02H (Data Available). The data register is Read Clear so that data will be deleted once it is read. Do not read data during a sequential measurement. Addr 10H 11H 12H 13H 14H 15H 16H 17H 18H Register Name Status Sequence Data 1H Sequence Data 1L Sequence Data 2H Sequence Data 2L Sequence Data 3H Sequence Data 3L Sequence Data 4H Sequence Data 4L D7 D6 D5 D4 D3 D2 D1 D0 CHST3 D1T11 D1T3 D2T11 D2T3 D3T11 D3T3 D4T11 D4T3 CHST2 D1T10 D1T2 D2T10 D2T2 D3T10 D3T2 D4T10 D4T2 CHST1 D1T9 D1T1 D2T9 D2T1 D3T9 D3T1 D4T9 D4T1 CHST0 D1T8 D1T0 D2T8 D2T0 D3T8 D3T0 D4T8 D4T0 SEQST3 D1T7 0 D2T7 0 D3T7 0 D4T7 0 SEQST2 D1T6 0 D2T6 0 D3T6 0 D4T6 0 SEQST1 D1T5 0 D2T5 0 D3T5 0 D4T5 0 SEQST0 D1T4 0 D2T4 0 D3T4 0 D4T4 0 Table 10. Data Register for Sequence Mode (Read Only) BIT D7-D4 Name CHST3-0 D3-D0 SEQST3-0 Description Last Measurement Channel for Single Mode 0011: AIN 0100: X-axis 0101: Y-axis 0110: Z1 0111: Z2 others: Reserved Status Bits for Sequence Mode 0000: Not Busy 0001: Sequence Busy 0010: Data Available others: Reserved Table 11. Status Register description (Read Only) MS1068-E-04 2011/03 - 18 - [AK4186] 2. Single Mode Data Register The AK4186 starts A/D conversion in single mode by receiving a single measurement command, and then outputs MSB first 12bit A/D data. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 XS4 20H Single XH XS11 XS10 XS9 XS8 XS7 XS6 XS5 21H Single XL XS3 XS2 XS1 XS0 0 0 0 0 22H Single YH YS11 YS10 YS9 YS8 YS7 YS6 YS5 YS4 23H Single YL YS3 YS2 YS1 YS0 0 0 0 0 24H Single Z1H Z1S11 Z1S10 Z1S9 Z1S8 Z1S7 Z1S6 Z1S5 Z1S4 25H Single Z1L Z1S3 Z1S2 Z1S1 Z1S0 0 0 0 0 26H Single Z2H Z2S11 Z2S10 Z2S9 Z2S8 Z2S7 Z2S6 Z2S5 Z2S4 27H Single Z2L Z2S3 Z2S2 Z2S1 Z2S0 0 0 0 0 28H Single INH INS11 INS10 INS9 INS8 INS7 INS6 INS5 INS4 29H Single INL INS3 INS2 INS1 INS0 0 0 0 0 Table 12. Data Register for Single Mode (Read Only) ■ Power-down Control Power-down and pen interrupt function are controlled by PD0 bit. In order to achieve minimum current, it is recommended to set PD0 bit = “0” for automatic power down of the touch screen driver after A/D conversion. It is possible to reduce the variation in data by setting PD0 bit = “1” during measurements. A/D converter keeps power up state after every measurement completed. When the register data of address 01H is written, PD0 bit is updated at the rising edge of the 27th SCL. The last PD0 bit is valid until this timing. The A/D converter and internal oscillator are automatically powered up at the start of the conversion, and automatically powered down at the end of the conversion, regardless of the PD0 bit setting. PD0 0 PENIRQN Enable 1 Disable Function Auto Power-down Mode In power-down state, the touch screen driver switches are powered down. (Only YN or BL driver switch is turned ON and forced to VSS.) PEN interrupt function is enabled except when in the sampling time and converting time. Driver ON Mode If X-axis or Y-axis is selected as analog input, touch screen driver switches are always powered up. This is effective when more settling time is required to suppress the electrical bouncing of touch plate. PEN interrupt function is disabled and PENIRQN is forced to “L” state. Table 13. Power-down Control MS1068-E-04 2011/03 - 19 - [AK4186] ■ Sleep Mode The AK4186 supports sleep mode that puts touch panel to open state and disables pen interrupt function, effective for reducing power consumption caused by unnecessary pen touch. Sleep mode is controlled by SLEEP1-0 bits. The AK4186 changes to sleep mode on the rising edge of 27th SCL after the micro-controller writes “01” or “10” to SLEEP1-0 bits of AK4186’s register. All touch screen driver switches and A/D converter are powered down in this sleep mode, and it reduces power consumption to the minimum value. The PENIRQN output is shown below. (Table 14) The AK4186 returns to normal operation out of sleep mode when the micro-controller writes “00” to SLEEP1-0 bits. The timing of going back to normal operation mode is the rising edge of the 27th SCL. The initial state after system reset is in normal operation mode. SLEEP1-0 00 01 10 11 PENIRQN Touch Panel Normal Operation Normal Operation Disable (PENIRQN=H) Open Disable (PENIRQN=Hi-z) Open N/A N/A Table 14. Sleep Mode A/D conversion is available during sleep mode by issuing an ADC executing command (sequential). The AK4186 returns to sleep mode after completing an A/D conversion. MS1068-E-04 2011/03 - 20 - [AK4186] CONTROL SEQUENCE ■ Power-up Sequence To fix the I2C interface statement, send a dummy command when first power up. After the dummy command, send a reset command to initialize internal registers. 1 0 0 1 0 0 CAD0 R/W Figure 23. Slave Address Construction (CAD0 is set by a pin) 1 1 1 1 1 1 1 1 1 1 Figure 24. Dummy Address Construction 1 1 1 1 1 1 Figure 25. Dummy Command Construction P S AK4186 ACK or NACK Dummy Command S T A R T S T O P R/W= “0” Slave Address Sub Address Dummy Command Reset Command P AK4186 ACK Dummy Address S T O P AK4186 ACK Slave Address AK4186 ACK or NACK S AK4186 ACK or NACK SDA R/W= “0” AK4186 ACK S T A R T Reset Command Figure 26. Power-up Sequence MS1068-E-04 2011/03 - 21 - [AK4186] ■ Touch Screen Controller Control Sequence (Single Mode) (1) Setup Sequence In case of the single measurement mode, this touch panel configuration register sets the measurement mode of the AK4186. Touch screen driver switches are turned ON at Driver ON mode (PD0 bit = “1”) on the rising edge of the 27th SCL. It is possible to have longer tracking time even if the source of analog input impedance is high, because the actual sampling is executed at the read operation. If a current measurement is made by the same setting of PD0 bit as the last time, the setup sequence is unnecessary. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 20 19 18 21 22 23 24 25 26 27 SCL Data Byte Sub Address Byte Slave Address Byte R/ W SDA 1 0 0 1 0 0 0 CAD0 0 Register Addr = 01H 0 AK4186 ACK START PANEL SLEEP SLEEP 1 0 0 0 0 0 PD0 AK4186 ACK Touch Screen Driver SW PD0=1 PD0=0 0 AK4186 ACK STOP “Off” Figure 27. Setup operation and Driver SW timing (2) Single Measurement Sequence When the master send a READ command after sending a control register address for a measurement channel by a WRITE operation, the AK4186 starts A/D conversion in single mode. This A/D conversion is synchronized with the internal clock. The internal oscillator of the AK4186 is automatically powered up on the falling edge of 25th SCL after writing the register address, and the AK4186 samples the analog input and completes A/D conversion after the rising edge of 26th SCL. The master receives the first byte of serial data (D11-D4, MSB first), and generates an acknowledge. Then the master receives the second byte of serial data (D3-D0, followed by four 0 bits). When the master continuously reads ADC data, the master repeats read operation after generating an acknowledge. If the master does not generate an acknowledge but generates stop condition instead, the AK4186 ceases continuous operation. 0 1 2 3 4 5 6 1 0 0 1 0 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 0 0 1 0 0 25 26 27 28 29 30 31 32 33 34 35 0 D11 D10 D9 D8 D7 D5 D4 36 37 38 39 0 D2 D1 40 41 42 43 44 0 0 0 45 46 SCL R/ W SDA CAD 0 0 R/ W 0 Register Addr = 20H~28H AK4186 ACK START Slave Address Byte CAD 1 0 Slave Address Byte D3 D0 Master ACK AK4186 ACK AK4186 START ACK Sub Address Byte D6 Data Byte (MSB) 0 1 Master ACK STOP Data Byte (LSB) OSCLK Sampling PD0=“1” Sampling AD conv. AD conv. “H” Touch Screen Driver SW PD0=“0” PENIRQN PD0=“0” ENABLE “L” ENABLE Figure 28. Single Measurement operation and Driver SW timing MS1068-E-04 2011/03 - 22 - [AK4186] ■ Touch Screen Controller Control Sequence (Sequence Mode) The AK4186 starts A/D conversion in sequence mode by setting the COUNT, SEQM2-0, INTERVAL2-0 bits of the register address 02H. PENIRQN is forced to “L” state, and internal oscillator is automatically powered up. The AK4186 makes six or ten measurements by setting the COUNT bit. The results are used to calculate the average value, discarding the minimum and maximum values, and the result sets the data register of sequence mode. When the sequence is finished, the AK4186 sets the PENIRQN pin to “H” and notifies that sequence is ended. After 20μs (typ.) is passed from the rising edge of the PENIRQN pin, the internal oscillator is powered down and PEN interrupt function is enabled. The master executes the register read operation to read the measurement data of sequence mode after confirming Data availability. The master can confirm Data availability by PENIRQN↑ or SEQST3-0 = 03H. This sequence data can be read in register read operation one by one (Address 11H). Prior to issuing the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit “1”. The AK4186 then generates an acknowledge, 1 byte of ADC data, and increments the internal address counter by 1. If the master does not generate an acknowledge but generates stop condition instead, the AK4186 ceases transmission. The A/D data is cleared after reading all the A/D data. Pen Touch Sequence Start Set PENIRQN Low Start Clock Driver Set Wait Timer ADC No Count End? Yes Sequence End? No Yes Set PENIRQN High Stop Clock & PenTouch Enable Done Figure 29. Internal Clock Mode Control Flowchart MS1068-E-04 2011/03 - 23 - [AK4186] PENIRQN SCL SDA S Slave Address W Sub Address (02H ) Data (10H) P W=0 OSCLK Internal Sequence (SEQM2-0 bits=“001”, X-Y Scan) PEN Touch Tracking, Conversion (X-axis 1st) Tracking, Conversion (X-axis nth) 20 / fosc 20 / fosc Wait Tracking, Conversion (Y-axis 1st) Tracking, Conversion (Y-axis nth) 20 / fosc 20 / fosc Wait PENIRQN Enable DAV Figure 30. Sequence Mode Control Sequence (X-Y Scan: SEQM bits = “001”) (Sequence Mode Start → Internal Sequence Processing → Data Available) PENIRQN SCL SDA S Slave Address W Sub Address (11H) S Slave Address W=0 DAV AK4186 ACK AK4186 ACK R ADC Data (11H) R=1 AK4186 ACK ADC Data (12H) MASTER ACK ADC Data (13H) ADC Data (14H) MASTER ACK MASTER ACK P MASTER NACK Figure 31. Sequence Mode Control Sequence (X-Y Scan: SEQM bits = “001”) (Data Available → A/D Data Read) D11 (MSB) D10 D9 D8 D7 D6 D5 D4 0 0 Figure 32. ADC Data (High Byte) D3 D2 D1 D0 (LSB) 0 0 Figure 33. ADC Data (Low Byte) MS1068-E-04 2011/03 - 24 - [AK4186] ■ Pen Interrupt The AK4186 has pen interrupt function to detect pen touches. Pen interrupt function is enabled at power-down state and PD0 bit = “0” (Figure 34). The YN pin (4-wire) or BL pin (5-wire) is connected to VSS at the PEN interrupt enabled state. The XP pin (4-wire) or WIPER pin (5-wire) is pulled up via an internal resistor (RIRQ: typ.50kΩ). PENIRQN is connected to the XP pin (4-wire) or WIPER pin (5-wire) inside. If touch plate is pressed by a pen, the current flows via <VDD> - <Ri> - <X+> - <Y-> (4-wire). If 5-wire, via <VDD> - <Ri> - <WIPER> - <BL>. The resistance of the plate is generally 1kΩ or less, PENIRQN is forced to “L” level. If the pen is released, PENIRQN returns “H” level because two plates are disconnected, and the current does not flow via two plates. During an A/D conversion or Sequence measurement or when PD0 bit is set to “1”, the PENIRQN is “L” for all the time in this period regardless of the touched/non-touched state. While in single measurement mode, the pen interrupt function is disabled from the rising edge of 26th SCL to the end of the measurement. (Figure 28) It is recommended that the micro controller mask the pseudo-interrupts while the control command is issued or A/D data is output. PENIRQN VDD VDD RIRQ = 50kΩ VDD EN2 Driver OFF XP/WIPER EN1 YN/BL Driver ON Figure 34. PENIRQN Functional Block Diagram (WIPER does not have a driver.) MS1068-E-04 2011/03 - 25 - [AK4186] SYSTEM DESIGN Figure 35, Figure 36, Figure 37, Figure 38 shows the system connection diagram for the AK4186. The evaluation board [AKD4186] demonstrates the optimum layout, power supply arrangements and measurement results. AK4186ECB <4-wire Touch Screen Input> 4-wire Analog Ground Touch Screen Digital Ground 0.001µ * 0.001µ * 0.001µ * 0.001µ * XP Analog Supply 1.6∼3.6V YP XN YN Top View 10µ + 0.1µ VDD CAD0 TEST VSS IN PENIRQN SDA SCL Auxiliary Analog Input Rp Rp “L” or “H” µP Figure 35. Typical Connection Diagram (4-wire, AK4186ECB) Notes: - VSS of the AK4186 should be distributed separately from the ground of external controllers. - All digital input pins (SCL, SDA, CAD0 pins) must not be left floating. MS1068-E-04 2011/03 - 26 - [AK4186] AK4186EN <4-wire Touch Screen Input> 4-wire Touch Screen Digital Ground Analog Ground 0.001µ * 0.001µ * 0.001µ * Rp 10 YP NC 14 VSS 15 T EST 16 NC 9 11 XN 13 10µ XP 12 YN 0.001µ * NC 8 VDD 7 IN 6 NC 5 AK4186EN Top View SC L SDA PENIRQN CAD0 1 2 3 4 0.1µ + Analog Supply 1.6∼3.6V Auxiliary Analog Input Rp “L” or “H” µP Figure 36. Typical Connection Diagram (4-wire, AK4186EN) Notes: - VSS of the AK4186 should be distributed separately from the ground of external controllers. - All digital input pins (SCL, SDA, CAD0 pins) must not be left floating. MS1068-E-04 2011/03 - 27 - [AK4186] AK4186ECB <5-wire Touch Screen Input> 5-wire Analog Ground Touch Screen Digital Ground 0.001µ * 0.001µ * 0.001µ * 0.001µ * BR Analog Supply 1.6∼3.6V TR TL BL Top View 10µ + 0.1µ VDD CAD0 TEST VSS WIPER PENIRQN SDA SCL 0.001µ* Rp Rp “L” or “H” µP Figure 37. Typical Connection Diagram (5-wire, AK4186ECB) Notes: - VSS of the AK4186 should be distributed separately from the ground of external controllers. - All digital input pins (SCL, SDA, CAD0 pins) must not be left floating. MS1068-E-04 2011/03 - 28 - [AK4186] AK4186EN <5-wire Touch Screen Input> 5-wire Touch Screen Digital Ground Analog Ground 13 NC 14 VSS BP + NC 8 Analog Supply 1.6∼3.6V VDD 7 WIPER 6 5 10µ AK4186EN Top View Rp * * * * 9 10 TR 11 TL BL 12 0.001µ 0.001µ 0.001µ 0.001µ SDA PENIRQN CAD0 3 4 NC 2 16 0.1µ SC L T EST 1 15 NC 0.001µ * Rp “L” or “H” µP Figure 38. Typical Connection Diagram (5-wire, AK4186EN) Notes: - VSS of the AK4186 should be distributed separately from the ground of external controllers. - All digital input pins (SCL, SDA, CAD0 pins) must not be left floating. 1. Grounding and Power Supply Decoupling The AK4186 requires careful attention to power supply and grounding arrangements. VDD is usually supplied from the system’s analog supply. VSS of the AK4186 must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4186 as possible, with the small value ceramic capacitor being the nearest. 2. Analog Inputs When an EMI source is close to the touch panel analog signal line, EMI noise affects analog characteristics performance. Connect noise canceling capacitors (*) as close as possible to each pin (XP, XN, YP, YN pins) of the AK4186 to avoid this noise. (Figure 35, Figure 36, Figure 37, Figure 38) MS1068-E-04 2011/03 - 29 - [AK4186] PACKAGE (AK4186ECB) 12pin CSP (Unit: mm) Top View Bottom View A 0.40 1.66 ± 0.05 (0.23) 0.40 3 XXXX 2 0.65 ± 0.05 0.19 ± 0.05 (0.23) 1.26 ± 0.05 B 1 D C B A φ 0.27 ± 0.05 φ 0.05 M S AB S 0.08 S ■ Material & Lead finish Package molding compound: Epoxy resin, Halogen (bromine and chlorine) free Solder ball material: SnAgCu MS1068-E-04 2011/03 - 30 - [AK4186] PACKAGE (AK4186EN) 16pin QFN (Unit: mm) Bottom View Top View 1.80 9 12 3.00±0.07 8 13 1.50 0.30±0.07 1.80 A Exposed Pad 16 1 4 B 1.50 0.05 M S 0.22±0.05 C0.30 A B 0.12~0.18 0.00~0.05 0.70 0.75 max 3.00±0.07 0.05max S 0.17~0.27 Part A 0.50 [Part A Detail] 0.05 S Note: The thermal die pad must be open or connected to the ground. ■ Package & Lead frame material Package molding compound: Epoxy Resin, Halogen (bromine and chlorine) free Lead frame material: Cu Alloy Lead frame surface treatment: Palladium Plate MS1068-E-04 2011/03 - 31 - [AK4186] MARKING (AK4186ECB) XXXX A1 Date Code: XXXX(4 digits) Pin #A1 indication MARKING (AK4186EN) 4186 XXXXX Date Code: XXXXX (5 digits) Pin #1 indication MS1068-E-04 2011/03 - 32 - [AK4186] REVISION HISTORY Date (YY/MM/DD) 09/03/30 09/10/22 Revision 00 01 Reason First Edition Error Correction 10/07/02 02 10/12/15 03 Product Addition Spec Change 11/03/30 04 Error Correction Page/Line Contents 18 /2 /6 22 Sequence Mode Data Register “register address 03H” →“register address 02H” SEQST7-0 = 03H → SEQST3-0 = 02H Setup Sequence Figure 27 was changed. AK4186EN was added. 5 ANALOG CHARACTERISTICS Gain Error (AK4186EN): -6 → -4.5 (min) +2 → +3.5 (max) PIN/FUNCTION Pin No. D3, 12: BL “Touch Panel Bottom Right Input” → “Touch Panel Bottom Left Input” 3 IMPORTANT NOTICE " These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. " Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. " Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. " AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. " It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1068-E-04 2011/03 - 33 -