Carradio IC FM Car Radio IC with PLL TUA 4401 Specification 1 B6CA Features • Double balanced RF mixer with low noise figure, high IP3 and wide dynamic range • Strictly symmetrical RF circuitry • IF amplifier with adjustable gain • 7 stage limiter amplifier with dB linear fieldstrength output • Low distortion coincidence demodulator • Multipath detector with analog output • CMOS PLL-Synthesizer • Resolution between 100 kHz and 6.25kHz • Search tuning stop with IF counter and Fieldstrength/Multipath evaluation • ADC’s for fieldstr. and Multipath detector • SOCCAR Bus I2C Bus and 3 Wire Bus operation possible 2 Package Ordering Information Type Ordering Code TUA 4401 3 MQFP 64 Package MQFP-64 General Description The TUA 4401 is the first Infineon Carradio IC using BICMOS technology. The combination of an analog FM receiver circuit and a digital PLL synthesizer on the same chip reduces the over all pin count in comparision to two separate IC’s and in addition the number of necessary external components. This gives the flexibility both for high performance and low cost applications. The recommended applications for this device are FM only carradios and background receivers, capable for all world standards. TUA 4401 features: Frontend - High level, high impedance mixer input with improved dynamic range - High input / output 3rd order intercept point - Integrated prestage AGC generation and control for PIN diodes and MOS tetrode - Bus controlled AGC threshold - 2 pin 1st local oscillator with improved low phase noise, internally coupled to PLL - Strictly symmetrical RF parts - PLL with fast acquisition mode - Resolution 100 kHz, 50 kHz, 25 kHz, 12,5 kHz, 10 kHz and 6.25 kHz - High running (61.5 MHz) crystal oscillator to avoid interference with bus controlled adjustment Semiconductor Group 2 1.6.99 Specification TUA 4401 IF amplification, demodulation and STS - Low noise IF amplifier - Gain adjust with DC control voltage or serial bus possible - 7 stage IF limiter with extended fieldstrength range suitable for the IF frequency range of 10.7 MHz ... 21.4 MHz - Fieldstrength DC output and ADC output available - Low distortion coincidence demodulator (using short loop AFC principle) with MPX output - Soft mute for weak signal conditions with adjustable bus controlled mute depth - Multipath detector with high pass filter, analog output and ADC output - IF counter for search tuning stop with selectable IF center frequency and window width - STS informations -in window-,-below-,-beyond- available SOCCAR Bus (Siemens One Chip CAr Radio Bus) - I2C bus (2 wire, fast mode device with 400 kbit/s) and 3 Wire bus (3 or 4 wire) operation possible - Bus interface with low threshold voltage Schmitt-Trigger inputs for interfacing 3V or 5V microprocessors 4 Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 17 64 1 Semiconductor Group 2 3 4 5 6 7 9 10 11 12 13 14 15 16 8 3 1.6.99 Specification 5 Pin No. TUA 4401 Pin Definitions and Functions Symbol Function +5V 64 1 MP_ADC 1: ADC input multipath detector +5V 5 pF 64 FS_ADC 64: ADC input fieldstrength 1 GNDD +5V 2: IF counter output IF center 2 2 IF_CENT GNDD +5V 3: IF counter detect output (below beyond window) 3 3 IF_WINDOW GNDD + 5V 4 4 330 BUS_MODE +5V 4: SOCCAR bus select input (I2C or 3 Wire mode) GNDD Semiconductor Group 4 1.6.99 Specification TUA 4401 + 5V 5 5 5: SOCCAR bus clock input 330 SCL +5V GNDD + 5V 6 6 6: SOCCAR bus data in/output (I2C mode), data input (3 Wire mode) 330 SDA GNDD 7 NC 7: not connected + 5V 8 8 330 BUS_ENA +5V 8: SOCCAR bus enable input GNDD 9 NC 9: not connected 10 VREFD5V 10: Reference voltage digital section (5V) 11 VREFD3V 11: Reference voltage digital section (3V) 12 NC 12: not connected V+ 3V 13 XTAL_DIV6 13 2k 13: Crystal oscillator auxiliary output (10.25 MHz) 200fF GNDD 14 NC Semiconductor Group 14: not connected 5 1.6.99 Specification TUA 4401 +5V 15 330 15 15: Switch port output 2(open drain) PORT_2 GNDD +V 16 16: Reference oscillator input / Crystal QUARTZ1 2,5 k 16 17 5k QUARTZ2 5k 17 17: Reference oscillator input / Crystal 18 VCCD 18: Positive power supply voltage for serial bus und synthesizer 19 GNDD 19: Ground for serial bus und synthesizer 20 NC 20: Not connected 21 NC 21: Not connected +5V 22 330 22 PORT_1 22: Switch port output 1 (open drain) GNDD Semiconductor Group 6 1.6.99 Specification TUA 4401 VCCD IPDA +5 V 23: PLL phasedetector output analog (Tuningvoltage) 23 PDA PD 12 3k 23 GNDD +5 V 24 PD PD_0 25 PD_1 26 GNDRF 24 +5 V 25: PLL chargepump output 1 (Phase detector tristate chargepump output) 25 +5 V 26: Ground for RF part +V +V 27 27 24: PLL chargepump output 0 (Phase detector tristate chargepump output) 28 OSC1 27: 1st local oscillator circuit 28: 1st local oscillator circuit 28 OSC2 2,2V 29 29: Positive power supply voltage for RF part VCCRF Semiconductor Group 7 1.6.99 Specification TUA 4401 +V 30 30 30: Prestage AGC time constant capacitor; output for MOS tetrode gate 2 PRE_CAP 6,4V 37 38 +V 31 FM1 31: FM 1st mixer symmetrical input 31 32 2,0k FM2 2,0k 32 32: FM 1st mixer symmetrical input 2,6 V 33 NC 34 AGCOUNT_ N 33: not connected 34 35 +V 34: Prestage AGC current output for PIN diode inverse polarity 35 AGCOUNT_ P 35: Prestage AGC current output for PIN diode normal polarity 36 NC not connected Semiconductor Group 8 1.6.99 Specification 37 TUA 4401 38 +V 37 37: 1st mixer output (open collector) IF2 31 38 38: 1st mixer output (open collector) IF1 2,0k 2,0k 32 2,6 V 39 VREFRF 39: Reference voltage RF section (4.8V) 40 GNDIF1 40: Ground for IF amplifier +V 42 IFINFM 41: 10.7 MHz IF amplifier input 330 41 IFIN 17k 42 17k 41 42: 10.7 MHz IF amplifier operation point 3,8V 43 43: Reference voltage IF section (4.8V) VREFIF Semiconductor Group 9 1.6.99 Specification TUA 4401 +5V 44 44 IFAMPG 44: 10.7 MHz IF amplifier DC gain control adjust, overwrite of DAC from DAC 2,5 V 330 330 +V 45 45 45: 10.7 MHz IF amplifier output IFOUTFM +V 46: 10.7 MHz IF amplifier DC gain control adjust blocking capacitor 46 IFAMPC 47 VCCIF 47: Positive power supply voltage for IF amplifier 48 NC 48: not connected 10k 46 Semiconductor Group 10 1.6.99 Specification TUA 4401 +V 50 49: FM limiter input FMIFIN 330 49 FMIFBIAS2 33k 50 33k 49 50: FM limiter input bias decoupling cpacitor 5,5 V 51 GNDIF2 51: Ground for limiter amplifier 52 NC 52: not connected +V MUTE 55 FSOUT 53 +V 53: Dynamic soft mute control blocking capacitor 55: Fieldstrength output 34k 66k 53 55 +V 54 54 54: FM MPX signal output MPXOUT Semiconductor Group 11 1.6.99 Specification TUA 4401 100k +V 56 56 56: Multipath detector highpass filter input MPA_IN +V 86k 57 MPA_AIN 58 57 58 57: Multipath detector auxiliary input +V 58: Multipath detector rectifier capacitor MPACAP +V 59 59 MPA_OUT 59: Multipath detector output +V 60 DEMAFC 60 76k 60: Demodulator AFC blocking capacitor 3,5V Semiconductor Group 12 1.6.99 Specification TUA 4401 +V 15p 61 PH02 61: Demodulator circuit 15k 62 61/62 PH01 62: Demodulator circuit 4,8V 63 6 OPA Test pin Applications • FM only car radio receiver, background receiver Semiconductor Group 13 1.6.99 Specification NC AGCOUNT_N AGCONT_P NC IF2 IF1 VREFRF GNDIF1 IFINFM IFIN VREFIF IFAMPG IFOUTFM IFAMPC VCCIF Block Diagram NC 7 TUA 4401 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 FM2 31 FM1 30 PRE_CAP 52 29 VCCRF 53 28 OSC2 FMINFIN 49 FMIFBIAS 50 GNDIF2 51 NC MUTE IF AMP Vref FM Lim / Dem / FS / MP-Det Mixer 1st LO Preset AGC MPXOUT 54 27 OSC1 FSOUT 55 26 GNDRF MPA_IN 56 25 PD_1 MPA_AIN 57 24 PD_0 23 PDA 22 PORT_1 MPACAP 58 MPA_OUT 59 DEMAFC 60 21 NC PH02 61 20 NC PH01 62 19 GNDD OPA 63 64 18 Cryst OSC17 9 10 11 12 13 14 15 16 VCCD FS_ADC Semiconductor Group IF_CENT IF_WINDOW BUS_MODE SCL SDA NC BUS_ENA 14 PORT_2 8 QUARTZ2 QUARTZ1 7 NC 6 NC 5 XTAL_DIV6 4 VREFD3V 3 VREFD5V 2 NC 1 MPA_ADC PLL Synth. Serial Bus IF counter ADC/DAC 1.6.99 Specification 8 TUA 4401 Circuit Description The TUA 4401 is a one chip FM car radio system consisting of RF frontend, gain adjustable IF amplifier, FM-IF limiter amplifier, demodulator, PLL synthesizer, IF counter for STS and ADC’s for fieldstrength and multipath detector.The serial bus is switchable between I2C and 3 Wire bus mode. 8.1 FM frontend The frontend consists of a two pin varactor tuned oscillator, a double balanced mixer and a prestage AGC control circuit. The mixer has an improved intermodulation behaviour and convertes the RF signal to the 10,7 MHz IF range. Two inputs allow both symmetrical and unsymmetrical operation. The integrated AGC stage for prestage control drives MOSFETS as well as PIN diodes with current drivers for normal and inverse polarity. The AGC threshold can be set with aserial bus controlled 2 Bit DAC. 8.2 FM IF amplifier After the mixer an IF amplifier is present for IF post amplification. Input and output impedance are both 330 Ohms for matching with ceramic filters. For adjusting the over all gain the IF amplifier gain can be adjusted with a serial bus controlled 4 Bit DAC. The DAC output is available at a pin and can be overwritten by an external control voltage for a not bus controlled gain adjust. 8.3 FM limiter and demodulator The FM IF amplifier includes a seven stage capacitive coupled limiter amplifier and a fieldstrength generator with high linearity and increased dynamic range. The coincidence demodulator has an additional AFC short loop circuit with integrated varactor diode in parallel to the external tank circuit to improve the distortion bahaviour in case of detuning. For decreasing noise a soft mute circuit is available. Noise can be continueasly decreased controlled by the fieldstrength value. Mute depth is adjustable with a serial bus controlled 7 bit DAC. The adjustment range includes a full mute feature. 8.4 Multipath detector A multipath detector with analog output is available. Its input signal is fed through a 200 kHz 2nd order highpass filter and a 80 kHz 1st order highpass filter. 8.5 A/D converter for fieldstrength and multipath detector The 7 bit A/D converter has two input channels and works as successive approximation converter. The conversion time for both input signals is t = 32 µs. The 7-bit digital-words from both channels (14 bit) are read out together via bus into two bytes with the read subadress 82H. The input voltage range for both channels is 0...VREFD5V. 8.6 IF counter and multipath/fieldstrength evaluation for STS FM center frequencies ar available in two ranges set by bit D7 in subaddress 05H. For D7=1 the range of centerfrequency is 20.800 MHz...22.3875 MHz in 128 steps (12.5 kHz per step). For D7=0 the range of centerfrequency is 10.400 MHz...11.1937 MHz in 128 steps (6.25 kHz per step). The gate time is adjustable in 8 steps from 320us...40.96ms and the tolerance of the accepted count value, the window is adjustable in 5 steps from +/- (6.25kHz...100kHz) for D7=0 in subaddress 05H and +/- (12.5 kHz...200 kHz) for D7=1 in subaddress 05H. The results IF_CENT and IF_WINDOW are read out via bus (read-subadress 82H) or pin IF_CENT. If the IF frequency is into the preselected window, IF_CENT goes from high to low level. If the IF frequency is outside the preselected window, IF_CENT is high. The bit IF_WINDOW is a hint IF-frequency that is to low (IF_WINDOW=high) or is to high (IF_WINDOW=low). In addition to the frequency measurement, thresholds for multipath and fieldstrength voltages can be programmed via bus (subaddress 0BH). IF_CENT will only go to low level in case of fieldstrength and multipath voltages are beyond the thresholds and the frequency is inside the window. When setting the thresholds to zero multipath and fieldstrength evaluation is disabled. Semiconductor Group 15 1.6.99 Specification TUA 4401 8.7 Crystal oscillator A master crystal oscillator provides all necessary clock frequencies for the whole IC. A 61.5 MHz crystal is used in 3rd harmonic mode. The oscillator frequency can fine tuned with a serial bus controlled 4 bit D/A converter. The crystal frequency is used as reference frequency for the PLL oscillator and IF counter. It is also used as clock for the ADC’s. Finally the crystal frequency divided by 6 (10.25 MHz) is available at a pin as low pass filtered voltage, it can be disabled with the serial bus. 8.8 Output ports PORT_1 / 2 are NMOS Open drain outputs. 8.9 SOCCAR Bus The TUA4401 supports the I2C bus protocol (2 wire) or 3 Wire bus protocol (3 or 4 wire) operation selectable by pin 4: BUS_MODE (I2C=low, 3W=high). All bus pins ( BUS_MODE, SCL, SDA, BUS_ENA) are Schmitt-triggered input buffer for 3V or 5V µC. The bit stream begins with the most significant bit (MSB), is shifted in (write mode) on the low to high transition of CLK and is shifted out (read mode) on the high to low transition of CLK. I2C bus mode In this mode pin4 (BUS_MODE) = low and pin8 (BUS_ENA)=low. In this mode SDA is a bidirectional input / output pin. Data Transition: Data transition on the pin SDA must only occur when the clock SCL is low. SDA transitions while SCL is high will be interpreted as start or stop condition. Start Condition (STA): A start condition is defined by a high to low transition of the SDA line while SCL is at a stable high level.This start condition must precede any command and initiate a data transfer onto the bus. Stop Condition (STO): A stop condition is defined by a low to high transition of the SDA while the SCL line is at a stable high level. This condition terminate the communication between the devices and forces the bus interface into the initial conditions. Acknowlage (ACK): Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data. During the 9th clock cycle the receiver will pull the SDA line to low level to indicate it has receive the 8 bits of data correctly. Data Transfer Write Mode: To start the communication, the bus master must initiate a start condition, followed by the 8bit chip address (write). The chip address for the TUA 4401 is fixed as ”1100110” (MSB at first). The last bit (LSB=A0) of the chip address byte defines the typ of operation to be performed: A0=1, a read operation is selected and A0=0, a write operation is selected. After this comparision the TUA 4401 will generate an ACK. After this device addressing the desired sub address byte and data bytes must be followed. The subaddresses determines which one of the 9 data bytes (00H...07H,0BH) is transmitted first. At the end of data transition the master must be generate the stop condition. Data Transfer Read Mode: To start the communication in the read mode, the bus master must initiate a start condition, followed by the 8bit chip address (write: A0=0), followed by the sub address read (82H or 83H), followed by the chip address (read: A0=1). After that procedure the 16bit data register 82H or the 8bit data register 83H is read out. After the first 8 bit read out, the uP mandatory send LOW during the ACK-clock. After the second 8 bit read out the uP mandatory send HIGH during the ACK-clock. At the end of data transition the master must be generate the stop condition. Semiconductor Group 16 1.6.99 Specification TUA 4401 3W bus mode In this mode pin4 (BUS_MODE) =high. Pin6 (SDA) is in this mode a bidirectional input / output. Pin8 (BUS_ENA) is used to activate the bus interface to allow the transfer of data (SDA) to / from the device. When BUS_ENA is in an inactive high state, shifting is inhibited. Data Transition: Data transition on the pin SDA must only occur when the clock SCL is low. To transfer data to / from the device, BUS_ENA (which must start inactive high) is taken low, a serial transfer is made via SDA, DOUT and CLK and BUS_ENA is taken back high. The bit stream needs neither the chip address. Data Transfer Write Mode: To start the communication, the BUS_ENA is taken low. The desired sub address byte and data bytes must be followed. The subaddresses determines which one of the 9 data bytes (00H...07H,0BH) is transmitted first. At the end of data transition the BUS_ENA must be high. Data Transfer Read Mode: To start the communication in the read mode, the BUS_ENA is taken low, followed by the sub address read (82H). After that the device is ready to read out the 16bit data register 82H. At the end of data transition the BUS_ENA must be high. 8.10 PLL Synthesizer R / N Counter The TUA 4401 has 2 identical 16bit counter for R and N path. Input frequency for the R-counter is the buffered XTAL-frequency (61.5MHz). Tuning steps can be selected by the 16bit R-counter from fR= 6.25kHz...100kHz. Input frequency for the N-counter is the buffered LO-frequency (in FM mode 98.2MHz...118.7MHz). Three State Phase Comparator The phase comparator generates a phase error signal according to phase difference between f R (R counter output) and fN (N counter output).This phase error signal drives the charge pump current generator. Polarity is fixed positiv for this application note. Charge Pump The charge pump generates signed pulses of current. 4 current values and 2 outputs are available. Loop Amp The integrated rail to rail loop amplifier allows an active loop filter design with external components. Two modes are avialiable with status bit D11: high speed and normal mode. Semiconductor Group 17 1.6.99 MOS tetrode Pin Diode 2 Pin Diode 1 VCC RF FM prest AGC FM 18 SOCCAR Bus N counter D W D ' V X % Charge pump PD Port R counter 4 bit DAC IF gain VREF RF OSC or Amp 10.7 MHz CER Filter 1. LO 2 bit DAC Prest. AGC thresh. 10.7 MHz CER Filter adj crystal IF amp gain adj. OSC Buffer External VRef IF div/6 10.7 MHz CER Filter SCL Mode ENA VCC IF SDA Clock counter Gate time counter Field strength FM IF limiter IF counter AfC loop Dem MP det in 7 Bit ADC 80 kHz HP 7 Bit DAC Mute depth MP det. 100 kHz HP Soft Mute P1 P2 MPX out VCCD Semiconductor Group Center Window Gate2 Fieldstrength MP det out Specification TUA 4401 8.11 Functional Block Diagram 1.6.99 Specification TUA 4401 8.12 Phase detector outputs fR fn PD_0/1 Polarity pos. P-Channel Tri-State. N-Channel Frequency fV < fR or fV lagging Semiconductor Group Frequency fV > fR or fV leading 19 Frequency fV = fR 1.6.99 Specification TUA 4401 8.13 Bus Interface Pin Function Pin name BUS_MODE BUS_ENA SCL SDA Function Bus mode select Enable Serial clock Serial data I2C-mode Low 3Wire mode High High=Inactiv Low=Activ Clock input Data in / out Data in 8.13.1 Bus Data Format I2C Bus Write Mode STA MSB CHIP ADDRESS (WRITE) 1 1 0 0 1 LSB 1 0 0 ACK MSB SUB ADDRESS (WRITE) 00H...07H, 0BH S7 S6 MSB SUB ADDRESS (READ) 82H, 83H LSB 1 0 0 S5 S4 S3 S2 LSB S1 S0 ACK MSB DATA IN X...0 (X=7 or 15) DX ... D5 D4 D3 D2 LSB D1 D0 ACK STO I2C Bus Read Mode MSB CHIP ADDRESS (WRITE) STA 1 1 MSB DATA OUT FROM SUB ADD 82H LSB R15 R14 R8 0 R13 R12 0 R11 1 LSB 1 R10 0 R9 0 ACK ACK1) 0 0 0 0 1 MSB DATA OUT FROM SUB ADD 82H, 83H LSB R7 R6 R0 R5 R4 R3 R2 R1 ACK ACK2) STA MSB CHIP ADDRESS (READ) 1 1 0 0 1 1 LSB 0 1 ACK STO 1): mandatory LOW send by uP, 2): mandatory HiGH send by uP 3W Bus Write Mode MSB SUB ADDRESS (WRITE) 00H...07H, 0BH S7 S6 S5 S4 S3 S2 S1 LSB MSB DATA IN X...0 (X=7 or 15) S0 DX ... D5 D4 D3 LSB D2 D1 D0 3W Bus Read Mode MSB SUB ADDRESS (READ) 82H, 83H LSB MSB DATA OUT FROM SUB ADD 82H (MSB) LSB MSB DATA OUT FROM SUB ADD 82H (LSB) / 83H (LSB) LSB 1 0 0 R15 R14 R8 R7 R6 R0 0 0 0 0 1 R13 R12 R11 R10 R9 R5 R4 R3 R2 R1 Chipaddress Organisation Chip Address (only I2C mode) MSB LSB Function 1 1 0 0 1 1 0 0 Chip Address Write 1 1 0 0 1 1 0 1 Chip Address Read LSB Hex Subaddress Organisation Sub Addresses of Data Registers Write MSB Bin Function 0 0 0 0 0 0 0 0 00H Status 0 0 0 0 0 0 0 1 01H R_Counter 0 0 0 0 0 0 1 0 02H N_Counter 0 0 0 0 0 0 1 1 03H Mute_DAC7 0 0 0 0 0 1 0 0 04H IF_COUNT_P1 0 0 0 0 0 1 0 1 05H IF_COUNT_P2 0 0 0 0 0 1 1 0 06H Specials 0 0 0 0 0 1 1 1 07H Gain_DAC4 0 0 0 0 1 0 1 1 0BH COMP_PRESET Sub Address of Data Register Read MSB Bin 1 0 0 0 0 0 1 0 0 0 0 0 Semiconductor Group LSB Hex Function 1 0 82H Result Multipath, Fieldstrength, IF_Window and IF_Center 1 1 83H Result-MISC 20 1.6.99 Specification TUA 4401 Data Byte Specification Status Subaddress 00H Bit R_Counter Subaddress 01H Results Fieldstrength, Multipath and IF counter Subaddress 82H (read address) N_Counter Subaddress 02H Function Bit Function Bit Function Bit Function MSB D15 not used (must be=0) MSB D15 215 MSB D15 215 MSB D15 IF_window D14 Port_2 (0=low, 1=high) D14 214 D14 214 D14 Multipath_26 D13 213 D13 213 D13 Multipath_25 D13 Port_1 (0=low, 1=high) D12 not used (must be=0) D12 212 D12 212 D12 Multipath_24 D11 Loopamp current D11 211 D11 211 D11 Multipath_23 D10 210 D10 210 D10 Multipath_22 D9 29 D9 29 D9 Multipath_21 8 D8 2 8 D8 Multipath_20 D7 27 D7 IF_center D10 D9 not used (must be=0) not used (must be=0) D8 not used (must be=0) D8 2 D7 ADC_Single D7 27 D6 2 6 D6 26 D6 Fieldstrength_26 5 D5 2 5 D5 Fieldstrength_25 D6 ADC_Mode D5 ADC_ON D5 2 D4 IF_DAC4 D4 24 D4 24 D4 Fieldstrength_24 D3 PD_select D3 23 D3 23 D3 Fieldstrength_23 D2 2 2 D2 2 2 D2 Fieldstrength_22 D1 21 D1 Fieldstrength_21 D0 LSB 20 D0 LSB Fieldstrength_20 D2 CP_Current 2 D1 CP_Current 1 D1 21 D0 LSB CP_Mode D0 LSB 20 Mute_DAC7 Subaddress 03H IF_Count_P1 Subaddress 04H IF_Count_P2 Subaddress 05H Specials Subaddress 06H IF_DAC4 Subaddress 07H COMP_PRESET Subaddress 0BH Bit Function Bit Function Bit Function Bit Function Bit Function Bit Function MSB D7 Enable MSB D7 Enable MSB D7 CF_Mod e MSB D7 XTAL_DIV6 MSB D7 not used MSB D15 not used D6 MDAC_6 D6 not used D6 CF_6 D6 VCO_2 D6 not used D14 Fieldstrength_26 D5 MDAC_5 D5 Win_2 D5 CF_5 D5 AGC_1 D5 not used D13 Fieldstrength_25 D4 MDAC_4 D4 Win_1 D4 CF_4 D4 AGC_0 D4 not used D12 Fieldstrength_24 D3 MDAC_3 D3 Win_0 D3 CF_3 D3 XTAL_3 D3 GDAC_3 D11 Fieldstrength_23 D2 MDAC_2 D2 Gate_2 D2 CF_2 D2 XTAL_2 D2 GDAC_2 D10 Fieldstrength_22 D1 MDAC_1 D1 Gate_1 D1 CF_1 D1 XTAL_1 D1 GDAC_1 D9 Fieldstrength_21 D0 LSB MDAC_0 D0 LSB Gate_0 D0 LSB CF_0 D0 LSB XTAL_0 D0 LSB GDAC_0 D8 Fieldstrength_20 D7 not used D6 Multipath_26 Result Misc Subaddress 83H D5 Multipath_25 Bit Function D4 Multipath_24 MSB D7 IF_Window D3 Multipath_23 D6 IF_Center D2 Multipath_22 D5 Fieldstrength_Comp D1 Multipath_21 D4 Multipath_Comp D0 LSB Multipath_20 D3 Res D2 Res D1 Res D0 LSB Res Semiconductor Group 21 1.6.99 Specification TUA 4401 Status, Subaddress 00H MSB D15 LSB MSB D14 D13 0 0 1 0 0 D12 D11 D10 D9 D8 0 0 0 0 D7 LSB D6 D5 D4 D3 D2 D1 D0 Function these bits must be = 0 opendrain Port_2 output = high level opendrain Port_2 output = low level 0 1 opendrain Port_1 output = high level 0 0 opendrain Port_1 output = low level 0 1 0 0 Loopamp currentsource high (ILOOPAMP=2.4mA) for high speed tuning Loopamp currentsource low (ILOOPAMP=1.2mA) 0 0 0 1 7 bit AD Converter enabled for single mode, stop 0 1 0 1 7 bit AD Converter enabled for single mode start. To restart single mode write the same bits once more. 0 0 1 1 7 bit AD Converter enabled for continuos mode run. 0 x x 1 7 bit AD Converter enabled for single or continous mode 0 x x 0 7 bit AD Converter disabled for single and continous mode 0 1 IF_DAC4 enabled (see subaddress 07H) 0 0 IF_DAC4 disabled (see subaddress 07H) 0 1 0 0 Phase detector 1 Phase detector 0 0 1 1 Chargepump current Icp3 = 4mA 0 1 0 Chargepump current Icp2 = 2mA 0 0 1 Chargepump current Icp1 = 1mA 0 0 0 Chargepump current Icp0 = 500uA 0 1 Chargepump enabled 0 0 Chargepump disabled Subaddress 01H, R_Counter and Subaddress 02H, N_Counter MSB LSB MSB LSB Function D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Divider by 65535 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 Divider by 2000 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 0 Divider by 1230 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 Divider by 1000 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 Divider by 615 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 Divider by 100 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Divider by 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Divider by 2 Semiconductor Group 22 1.6.99 Specification Subaddress 05H, IF_Count_P2, Centerfrequency = CF, CFstep= 6.25kHz / 12.5kHz) Subaddress 03H, Mute_DAC7 MSB D7 LSB D6 D5 D4 D3 D2 TUA 4401 D1 D0 MSB Function D7 LSB D6 D5 D4 D3 D2 D1 D0 Function 1 Mute_DAC7 enabled 1 Centerfequency CF1 0 x x x x x x x Mute_DAC7 disabled, full mute 0 Centerfequency CF0 1 1 1 1 1 1 1 1 Mute_DAC full scale mute off 1 1 1 1 1 1 1 1 CF1= 22.3875 MHz typical attenuation 0 1 1 1 1 1 1 1 CF0= 11.1937 MHz 1 1 1 1 0 0 0 1 Mute -5 dB 1 1 1 0 1 0 0 1 Mute - 10 dB 1 1 0 0 0 0 0 0 CF1= 22.600 MHz 1 1 1 0 0 0 1 0 Mute - 15 dB 0 1 0 0 0 0 0 0 CF0= 10.800 MHz 1 1 0 1 1 0 1 1 Mute - 20 dB 1 1 0 1 0 0 1 1 Mute - 25 dB 1 0 1 1 0 0 0 1 CF1= 21.4125 MHz 1 1 0 0 1 1 0 0 Mute - 30 dB 0 0 1 1 0 0 0 1 CF0= 10.70625 MHz 1 1 0 0 0 1 0 0 Mute - 35 dB 1 0 1 1 0 0 0 0 CF1= 21.400 MHz 1 0 1 1 1 1 0 1 Mute - 40 dB 0 0 1 1 0 0 0 0 CF0= 10.700 MHz 1 0 1 0 1 1 1 1 CF1= 21.3875 MHz 0 0 1 0 1 1 1 1 CF0= 10.69375 MHz 1 0 1 0 0 0 0 0 CF1= 21.200 MHz 0 0 1 0 0 0 0 0 CF0= 10.600 MHz 1 0 0 1 0 0 0 0 Full mute 1 0 0 1 0 0 0 0 Full mute 1 0 0 1 0 0 0 0 Full mute Subaddress 04H, IF_Count_P1 MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 Function 1 0 0 1 0 0 0 0 CF1= 21.000 MHz 0 0 0 1 0 0 0 0 CF0= 10.500 MHz 1 IF_Count enabled 0 IF_Count disabled 1 0 0 0 0 0 0 0 CF1= 20.800 MHz not used (must be=0) 0 0 0 0 0 0 0 0 CF0= 10.400 MHz 0 1 0 0 Window=+/-100kHz* 0 1 1 Window=+/-50kHz* Centerfrequencies for 0 1 0 Window=+/-25kHz* D7=1 0 0 1 Window=+/-12.5kHz* D7=0 0 0 0 Window=+/-6.25kHz* 1 1 1 Gatetime= 40.96ms 1 1 0 Gatetime= 20.48ms 1 0 1 Gatetime= 10.24ms 1 0 0 Gatetime= 5.12ms 0 1 1 Gatetime= 2.56ms 0 1 0 Gatetime= 1.28ms 0 0 1 Gatetime= 640us 0 0 0 Gatetime= 320us CF1= 20.800 MHz +n*12.5 kHz, CFStep=12.5kHz CF0= 10.400 MHz +n*6.25 kHz, CFStep=12.5kHz n=0...127 * Valid for D7= 0 in subaddress 05H Multiply window value with 2 for D7= 1 in subaddress 05H (e. g. D7= 0 D7= 1 Window =+/- 6.25 kHz Window =+/- 12.5 kHz) Semiconductor Group 23 1.6.99 Specification Subaddress 06H, Specials Subaddress 07H, IF_DAC4 MSB D7 LSB D6 D5 D4 D3 TUA 4401 D2 D1 D0 1 MSB Function XTAL_DIV6 enabled LSB D7 D6 D5 D4 x x x x D3 D2 D1 D0 Function not used XTAL_DIV6 disabled 1 1 1 1 IF_DAC Gain adj. typ. 16 dB 1 1st LO divided by 1 1 1 1 0 IF_DAC Gain adj. 0 1st LO divided by 2 1 1 0 1 IF_DAC Gain adj. 1 1 0 0 IF_DAC Gain adj. 0 0 0 Prest. AGC threshold typ. 15 mV 0 1 Prest. AGC threshold typ. 30 mV 1 0 1 1 IF_DAC Gain adj. typ. 21 dB 1 0 Prest. AGC threshold typ. 45 mV 1 0 1 0 IF_DAC Gain adj. 1 1 Prest. AGC threshold typ. 60 mV 1 0 0 1 IF_DAC Gain adj. 1 1 1 1 XTAL_adjust CL = 15 pF 1 0 0 0 IF_DAC Gain adj. 1 1 1 0 XTAL_adjust CL = 14pF 0 1 1 1 IF_DAC Gain adj. 1 1 0 1 XTAL_adjust CL = 13 pF 0 1 1 0 IF_DAC Gain adj. 1 1 0 0 XTAL_adjust CL = 12 pF 0 1 0 1 IF_DAC Gain adj. 1 0 1 1 XTAL_adjust CL = 11 pF 0 1 0 0 IF_DAC Gain adj. typ. 24 dB 1 0 1 0 XTAL_adjust CL = 10 pF 0 0 1 1 IF_DAC Gain adj. 1 0 0 1 XTAL_adjust CL = 9 pF 0 0 1 0 IF_DAC Gain adj. 1 0 0 0 XTAL_adjust CL = 8 pF 0 0 0 1 IF_DAC Gain adj. 0 1 1 1 XTAL_adjust CL = 7 pF 0 0 0 0 IF_DAC Gain adj. typ. 26 dB 0 1 1 0 XTAL_adjust CL = 6 pF 0 1 0 1 XTAL_adjust CL = 5 pF 0 1 0 0 XTAL_adjust CL = 4 pF 0 0 1 1 XTAL_adjust CL = 3 pF 0 0 1 0 XTAL_adjust CL = 2 pF 0 0 0 1 XTAL_adjust CL = 1pF 0 0 0 0 XTAL_adjust CL = 0pF Subaddress 0BH, Comp preset MSB D15 D14 D13 D12 D11 D10 D9 LSB MSB D8 D7 X LSB D6 D5 D4 D3 D2 D1 D0 X 6 FP2 FP2 5 FP2 4 3 FP2 2 FP2 1 FP2 FP2 Function not used 0 Preset value Fieldstrength MP26 MP25 MP24 MP23 MP22 MP21 MP20 Preset value Multipath Subaddress 82H, Read Results from Fieldstrength, Multipath and IF counter MSB D15 LSB MSB D14 D13 D12 D11 D10 D9 D8 D7 LSB D6 D5 D4 D3 D2 D1 D0 Function 1 1 IF_counter result: IF frequency is outside the desired window. IF frequency is lower as the desired IF frequency. 0 1 IF_counter result: IF frequency is outside the desired window.IF frequency is higher as the desired IF frequency. x 0 IF_counter result: IF frequency is inside the desired window M26 M25 M24 M23 M22 M21 M20 Result multipath byte M6...M0 F26 Semiconductor Group F25 F24 24 F23 F22 F21 F20 Result Fieldstrength byte F6...F0 1.6.99 Specification TUA 4401 Subaddress 83H, Read results misc MSB Semiconductor Group LSB D7 D6 1 D5 D4 Function D3 D2 D1 D0 1 Res Res Res Res IF_counter result: IF frequency is outside the desired window. IF frequency is lower as the desired IF frequency. 0 1 Res Res Res Res IF_counter result: IF frequency is outside the desired window.IF frequency is higher as the desired IF frequency. x 0 Res Res Res Res IF_counter result: IF frequency is inside the desired window 1 Fieldstrengthsignal is higher as the preseted value in subaddres 0BH (D8...D14) 0 Fieldstrengthsignal is lower as the preseted value in subaddres 0BH (D8...D14) 1 Multipathsignal is higher as the preseted value in subaddres 0BH (D0...D6) 0 Multipathsignal is lower as the preseted value in subaddres 0BH (D0...D6) 25 1.6.99 Specification TUA 4401 8.13.2 I2C Bus Timing BUS_MODE = LOW tBUF SDA tHD.STA tR tSP tF tLOW SCL tHD.STA P S tHD.DAT tHIGH tSU.DAT tSU.STA tSU.STO P S tHIGH BUS_ENA pulsed or mandatory low tSU.ENASDA tSU.ENASDA tSU.ENASDA 3W-Bus Timing BUS_MODE = HIGH SDA S tHD.STA SCL tSP tLOW t R tF tHD.DAT tHIGH P tSU.DAT tSU.STO BUS_ENA tSU.STAENA tSU.STOENA tWHEN Semiconductor Group 26 1.6.99 Specification Parameter Symbol LOW level input voltage (SDA, SCL, BUS_ENA, BUS_MODE) HIGH level input voltage (SDA, SCL, BUS_ENA, BUS_MODE) TUA 4401 Limit Values Unit min. max. VIL -0.5 0.90 V VIH 2.10 5.50 V Pulse widh of spikes which must be suppressed by the tSP input filter 0 50 ns LOW level output voltage 3mA sink current (SDA) VOL 0 0.40 V Output fall time from VIHmin to VILmax with a bus capcitance from 10pF to 400pFwith up to 3mA tfOF 20+0.1Cb3) 250 ns fSCL 0 kHz tBUF 1.3 us Hold time (repeated) START condition. After this period, the first clock pulse is generated. 1) tHO.STA 0.6 us LOW period of the SCL clock tLOW 1.3 us tHIGH 0.6 us tSU.STA 0.6 us Data hold time tHD.DAT 0 ns Data set -up time tSU.DAT 100 SCL clock frequency Bus free time between a STOP and START condition 1) HIGH period of the SCL clock Set-up time for a repeated START condition 1) Rise, fall time of both SDA and SCL signals Set-up time for STOP condition 1) Capacitive load for each bus line Setup time SCL to BUS_ENA tR, tF 20+0.1Cb tSU.STO 0.6 H-pulsewidth (BUS_ENA) ns 3) 300 ns us 400 Cb 2) 400 pF tSU.SCLEN 0.6 us tWHEN 0.6 us 1) only in I2C bus mode only in 3W bus mode 3) Cb= capacitance of one bus line in pF. Note that the maximum tF for the SDA and SCL bus lines quoted at 300ns is longer than the specified maximum tOF for the output stages (250ns).This allows series protection resistors to be connected between the SDA / SCL pins and the SDA /SCL bus lines without exceeding the maximum specified tF. 2) Semiconductor Group 27 1.6.99 Specification 9 TUA 4401 Electrical Characteristics 9.1 Absolute Maximum Ratings The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the IC will result. Parameter Symbol ESD-Protection all bipolar pins HBM ( R=1.5kΩ , C=100pF ) Limit Values Units min. max. VESD -2 2 kV ESD-Protection all CMOS pins HBM ( R=1.5kΩ , C=100pF ) VESD t.b.d. t.b.d. kV Total power dissipation Ptot 900 mW Ambient temperature TA 85 °C Junction temperature Tj 150 °C Storage temperature Tstg 125 °C Thermal resistance P-MQFP-64 (sys-air) TthSA 54 K/W - 40 - 40 All values are referred to ground (pin), unless stated otherwise. All currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from Vs across the designated pin), it has a positive sign. Semiconductor Group 28 1.6.99 Specification TUA 4401 9.2 Operating Range Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed. Parameter Symbol Supply voltage VVCC Current consumption Ivcc Ambient temperature TA Limit Values Unit min max 8 9 V 100 mA 85 °C - 40 Test Conditions 9.3 AC/DC Characteristics AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. Parameter TA = 25 °C,VVCC = 8.5V Symbol Limit Values min typ max Unit Test conditions Power supply Total current consumption 85 IVCC mA 1st local oscillator Frequency range f1st LO 50 250 MHz Frequency range f1st LO 80 150 MHz Q factor of coil > tbf Frequency range f1st LO 160 250 MHz coil tbf; see SUB06h Negative input impedance Z27-28 Ω f = 100 MHz - tbf RF mixer Input frequency f31-32 60 140 MHz Max input RF level V31-32 120 Input impedance single ended R31/32 tbf Ω C31/32 tbf pF Mixer gain Amix tbf dB tbf dBµV dBµV Input IP3 Noise Figure F tbf dB Reference voltage RF section V39 4.8 V Prestage AGC outputs AGC threshold range V31-32 15 60 6.4 AGC voltage for MOSFET Gate 2 V30 0.1 AGC voltage for MOSFET Gate 2 V30 12 mV see diagram SUB06h V V31-32 = 0 mV V V31-32 = 200 mV mA V31-32 = 0 mV mA V31-32 = 200 mV mA V31-32 = 200 mV mA V31-32 = 0 mV AGC current normal polarity I35 AGC current normal polarity I35 AGC current inverse polarity I34 AGC current inverse polarity I34 Integrator current I30 -50 µA V31-32 = 0 mV; Vm = 3V Integrator current I30 50 µA V31-32 = 200 mV; Vm = 3V Semiconductor Group 0.1 12 0.1 29 1.6.99 Specification Parameter TA = 25 °C,VVCC = 8.5V Symbol TUA 4401 Limit Values min typ max Unit Test conditions IF amplifier DC input voltage V41 4 V Input resistance R41 330 Ω Output resistance R45 330 Ω Voltage gain A45-41 26 dB V44 = 1.5 V; see also diagram SUB07h Voltage gain A45-41 16 dB V44 = 3.5 V; see also diagram SUB07h Noise figure F 7 dB RG = 330 Ω IF limiter amplifier / fieldstrength generator Input voltage for limiter threshold V49 25 µVrms fin = 10.7 MHz; V54 - 3 dB AM suppression AAM 80 dB m = 30 % Fieldstrength voltage V55 V V49 = 0 mVrms Fieldstrength voltage V55 tbf V V49 = 1 mVrms Fieldstrength voltage V55 tbf V V49 = 10 mVrms Fieldstrength voltage V55 4.5 V V49 = 200 mVrms Fieldstrength dynamic range V55dyn 90 dB Fieldstrength linearity V55lin ±1 dB Fieldstrength temperature drift V55temp 0.5 ±3 dB FM demodulator / soft mute AF output voltage V54 600 mVrms ∆F = 75 kHz; fIF=10.7 MHz AF output voltage V54 300 mVrms ∆F = 75 kHz; fIF= 21.4 MHz Total harmonic distortion THD54 0.5 % ∆F = 75 kHz 0.8 % fin = 10.7 MHz ± 50 kHz; ∆F = 75 kHz 38 dB V53 = 0 V; see diagram SUB03h dB V53 = 0 V; see diagram SUB03h Total harmonic distortion detuned THD54 AF mute depth range a54 0 AF full mute a54 80 Multipath detector Attack current I58*) 800 µA V56 = 1 Vpp; Vm = 5 V Recovery current I58*) -9 µA V56 = 0 Vpp; Vm = 3.6 V Start voltage V59Def 4.7 V V56 = 0 Vpp Detector characteristic V59 V59Def - 0.1 V V f56 = 25 kHz V56 = 160 mVpp Detector characteristic V59 V59Def -1V V f56 = 200 kHz V56 = 160 mVpp Reference voltage IF V43 4.8 V Semiconductor Group 30 1.6.99 Specification Parameter TA = 25 °C,VVCC = 8.5V Symbol TUA 4401 Limit Values min typ max Unit Test conditions *) Detector currents are measured between the output pin (pole) and a voltage source Vm Crystal oscillator Operating frequency f16-17 61.5 MHz 3rd harmonic Negative input impedance Z16-17 - 250 Ω f = 61.5 MHz Negative input impedance Z16-17 1.4 kΩ f = 20.5 MHz Input impedance crystal Rcr tbd Ω 3rd harmonic Spurious harmonics crystal asp - 20 dB f < 200 MHz Bus controlled adjust range ∆fadj ± 40 ppm see diagram SUB06h Bus controlled output XTAL_DIV6 VXTAL_DIV6 on AC 500 mVpp f = 10.25 MHz, Cload = 10 pF Bus controlled output XTAL_DIV6 VXTAL_DIV6 on DC 1.5 VDC f = 10.25 MHz, Cload = 10 pF Bus controlled output XTAL_DIV6 VXTAL_DIV6 off DC 50 mVDC Cload = 10 pF Chargepump output (Loopfilter input) 2.5 V locked DC voltage VPD_0/1 DC current ±IPD_0/1_3 3.2 4 4.8 mA DC current ±IPD_0/1_2 1.6 2 2.4 mA DC current ±IPD_0/1_1 0.8 1 1.2 mA DC current ±IPD_0/1_0 400 500 600 uA Tristate output current ±IPD_0/ 0.1 10 nA VPD_0/1 = 1.5V , guaranteed by design 1_OFF see Status, Subaddress 00H, bit D1, D2 VPD_0/1 = 1.5V Loop amplifier tuningvoltage output (Loopfilter output) LOW output voltage VPDA_L 0 tbd. 400 mV ITUNE = 100 uA HIGH output voltage VPDA_H VVCC0.5V tbd. VCC mV ITUNE = -100 uA mA VTUNE = 4V, VPD_0/1 = 0V (see Status, Subaddress 00H, bit D11) mA VTUNE = 4V, VPD_0/1 = 0V (see Status, Subaddress 00H, bit D11) kHz f crystal = 61.5 MHz HIGH output current source LOW output current source 2.4 IPDA_H 1.2 IPDA_L PLL for synthesizer (see PLL Synthesizer on page 17) PLL / VCO step size (programmable via R-counter) fref 6.25 100 N-counter divide ratio N 2 65535 16-Bit R-counter divide ratio R 2 65535 16-Bit Semiconductor Group 31 1.6.99 Specification Parameter TA = 25 °C,VVCC = 8.5V Symbol TUA 4401 Limit Values min typ Unit Test conditions 400 mV IP = 1 mA 100 nA VP = 5 V max Port outputs, PORT_1, PORT_2, IF_CENT, IF_WINDOW (see Output ports on page 16) LOW output voltage VP 0 HIGH Leackage current IP_LEACK 0 100 I2C / 3-Wire-bus (BUS_MODE, SCL, SDA, BUS_ENA) (see I2C Bus Timing on page 26 and Bus Data Format on page 20) H-input voltage VIH 2.10 5.50 V L-input voltage VIL -0.5 0.90 V Hysteresis of Schmitt trigger inputs (BUS_MODE, SCL, SDA, BUS_ENA) Vhys Input capacity CI Semiconductor Group 0.30 V 5 32 pF 1.6.99 Specification TUA 4401 10 Package Outline Semiconductor Group 33 1.6.99