INFINEON TUA6100B6

Components
for Satellite Receiver Units
DCR Sat-Frontend
TUA6100B6
Gain controlled I/Q Mixer
for digital QPSK Sat signals
Preliminary Specification 01.2001
V219
Edition 01.2001
Published by Infineon AG ,
Marketing-Communication,
Balanstr. 73,
81541 Munich
© Infineon AG 1999.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties
are concerned, liability is only assumed for
components, not for applications, processes
and circuits implemented within components
or assemblies.
The information describes the type of component and shall not be considered as assured
characteristics.
Terms of delivery and rights to change design
reserved.
For questions on technology, delivery and
prices please contact the Semiconductor
Group Offices in Germany or the Siemens
Companies and Representatives worldwide
(see address list).
Due to technical requirements components
may contain dangerous substances. For information on the types in question please contact
your nearest Infineon Office, Semiconductor
Group.
Infineon AG iGr is an approved CECC manufacturer.
Packing
Please use the recycling operators known to
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You must bear the costs of transport.
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Components used in life-support devices
or systems must be expressly authorized
for such purpose!
Critical components1 of the Semiconductor
Group of Infineon AG iGr, may only be used in
life-support devices or systems2 with the
express written approval of the Semiconductor
Group of Infineon AG iGr.
1 A critical component is a component used
in a life-support device or system whose
failure can reasonably be expected to
cause the failure of that life-support device
or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are
intended (a) to be implanted in the human
body, or (b) to support and/or maintain and
sustain human life. If they fail, it is reasonable to assume that the health of the user
may be endangered.
Ausgabe 01.2001
Herausgegeben von Infineon AG ,
Marketing-Kommunikation,
Balanstraße 73,
81541 München
© Infineon AG 1999.
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daß die Gesundheit des Anwenders
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TUA6100B6
Revision History:Current Version: 01.2001 , V219
Previous version:10.2000 , V217 -> V218
old Page
new Page
Subjects (major changes since last revision)
cover
cover
copper lead frame removed
cover
cover
Edition date
cover
cover
Spec version
20
20
Hysteresis of Schmitt trigger inputs, new
22
22
ESD note, updated
22
22
Ambient temperature, updated
22
22
Thermal resistance P-TSSOP28 + PCB board, removed
22
22
Detailed description of the needed thermal resistance, removed
22
22
Air gap package tolerances, removed
22
22
Thermal resistance junction case, new
22
22
Detailed description of the maximum junction temperature , new
23
23
RF input (950-2150MHz) section, definition changed to symm. balanced input,
referenced to test circuit
23
23
Input RF level min. value corrected, test condition changed
23
23
Input gain control range, test condition changed
23
23
Quadrature error, phase + gain, test condition added
23
23
Quadrature error, gain, value corrected
27
27
Test circuit , new
27
28
Application circuits , updated input configuration
28
29
Application circuits , updated input configuration + crystal series capacitor
Previous version:12.2000 , V218
old Page
new Page
Subjects (major changes since last revision)
cover
cover
Edition date
cover
cover
Spec version
2
2
Ordering Information, packages updated
22
22
Ambient temperature note, updated
23
23
Minimum input RF level , new description
23
23
Maximum input RF level , new description
27, 28
28, 29
Application circuits , updated input configuration
41
41
Plastic Package, P-TSSOP-28-1 alloy leadframe, added
Data Classification
Maximum Ratings
Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to
the integrated circuit.
Characteristics
The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics
specify mean values expected over the production spread. If not otherwise specified, typical characteristics
apply at TA = 25 C and the given supply voltage.
Operating Range
In the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about "Processing Guidelines" and
"Quality Assurance" for ICs, see our "Product Overview".
TUA6100B6
Table of Contents
1
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.11.1
8.11.2
8.11.3
8.12
8.12.1
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Input Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Baseband Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reference Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Crystal Oscillator Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Synthesizer Loop filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Synthesizer VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Phase Shift 0 / 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
GHz VCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
GHz PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional GHz PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GHz PLL programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Synthesizer VCO band switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Synthesizer PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Serial Bus Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3-wire bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Dual Modulus Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
R-Counter and A- / N-Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Phase Comparator (Frequency/Phase Detector). . . . . . . . . . . . . . . . . . . . . . . . . . 11
Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Lock Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Synthesizer PLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Divide ratio programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Phase detector outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chipaddress Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Subaddress Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Byte Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.12.2
8.12.3
8.12.4
8.13
8.13.1
8.13.2
8.13.3
8.13.4
8.13.5
High-Frequency-Products
i
26.1.01
Preliminary Specification
TUA6100B6
9
9.1
9.2
9.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC/DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11
Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
high side synthesizer VCO narrow band loop filter example . . . . . . . . . . . . . . . . . 28
high side synthesizer VCO wide band loop filter example . . . . . . . . . . . . . . . . . . . 29
Phase noise performance of application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Optimum phase detector current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VCO steepness + phase detector current ranges . . . . . . . . . . . . . . . . . . . . . . . . . 31
VCO tuning voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Receiving frequency band splitting into 2 or 3 ranges . . . . . . . . . . . . . . . . . . . . . . 32
12
Base band filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Frequency response incl. the two base band amplifiers + output load . . . . . . . . . 33
Group delay incl. the two +16 dB base band amplifiers + output load. . . . . . . . . . 33
13
13.1
13.2
13.3
13.8
Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Frequency flatness of base band outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Group delay of base band outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Frequency response of base band outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Group delay at low frequencies, dependent on coupling capacitor . . . . . . . . . . . . 36
RF gain control range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RF input impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
RF input impedance continued, Smith diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Base band output impedance pin 13, 14 (filtered), Smith diagram . . . . . . . . . . . . 38
Base band output impedance pin 19, 20 , Smith diagram . . . . . . . . . . . . . . . . . . . 39
Base band output impedance Pin 19, 20 (Ohm) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Base band output inductance Pin 19, 20 (Henry) . . . . . . . . . . . . . . . . . . . . . . . . . 40
Base band Input Impedance (filtered) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
14
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.4
13.5
13.6
13.7
High-Frequency-Products
ii
26.1.01
DCR Sat-Frontend
Gain controlled I/Q Mixer
for digital QPSK Sat signals
TUA6100B6
Preliminary Specification
1
2
BICMOS
Features
Low impedance gain controlled RF input
Dual matched double balanced mixer
Digital generation of 0/90 LO signal
Direct down conversion from 1. IF
(LNB output) to base band 0-30 MHz
IF filter not necessary
I / O for external baseband filter
CMOS PLL-Synthesizer
Active loop filter (high voltage)
3 high current switch outputs
Buffered crystal oscillator output
Low noise reference voltage
3-wire bus and
I2C bus with 4 addresses + subaddresses
Splitting of Sat tuning range into 2/3 bands
LO - frequency below and above
input frequency possible
TSSOP-28
Package
General Description
The TUA 6100 is a low cost chip in the newest Infineon high speed BICMOS technology B6HFC. It is designed
to implement the direct conversion receiver principle for digital QPSK-Sat receiving systems.
The DCR architecture eliminates the need for expensive RF-Filters for image rejection and IF-Frequencies for
channel selection. Instead, an inexpensive base band low-pass filter is used for channel selection, and no
image rejection filter is required.
These base band filter enable the possibility for an on chip integration. (not part of TUA6100)
The DCR system is the most promising architecture to lower the cost of digital set-top boxes front end.
Via a gain controlled RF preamplifier (not part of TUA6100) with approx. 30 dB gain and some selectivity, the
RF signal is symmetrical fed to two low input impedance double balanced mixers .
The mixers have common inputs with internal power splitting and incorporate a new patented direct gain
control in the mixer input stage and an additional gain control at the mixer output to improve S/N ratio.
The signal of the synthesizer tuning VCO is multiplied to 4 x RF input frequency via a complete internal
3.8-8.6 GHz PLL system.
To drive the mixers, this 3.8-8.6 GHz signal is split into quadrature components by a Johnson-counter .
The mixers are followed by 2 matched 16 dB fixed gain base band amplifiers making available the first linear
DC-coupled base band outputs with approx. 224 mVpp for the I and Q signal .
Two additional 16 dB fixed gain base band amplifiers with approx. 1 Vpp output voltage enable the possibility
to use system adapted external AC-coupled base band filter and eliminate undesirable DC-components of the
first amplifiers .
High-Frequency-Products
1
26.1.01
Preliminary Specification
TUA6100B6
The TUA 6100 contains
– 2 double balanced mixer cells with new patented direct gain control,
– a digital generation of the 0/90 local oscillator phase shifted signal to ensure minimum quadrature
phase error,
– an internal synthesizer VCO with programmed band splitting and external varactor and resonator,
– 2 internal GHz VCO’s and a PLL for generation of 4 x RF input frequency,
(necessary for the accurate digital generation of the LO I/Q components)
– a CMOS PLL-synthesizer controlled by I2C or 3-wire bus,
– an active synthesizer loopfilter with high voltage and high current output,
– an on chip reference oscillator (external crystal) which can be overridden by an external oscillator, and
– 4 ultra linear base band output amplifiers with approx. 16dB gain each.
The PLL-synthesizer is programmable to work with reference frequencies > 4kHz and up to 2 MHz, for more
information see Divide ratio programming on page 14. A programmable phase detector output current makes
it easy to select several transconductances controlled by bus.
A simple Windows control-program for I2C / 3-wire bus with short description is available.
3
Ordering Information
Type
Ordering Code
Package
TUA6100B6
Q 67037-A 1034 A 701
P-TSSOP-28-1
TUA6100B6
not yet available
P-TSSOP-28-5
4
Pin Configuration
top view
2-pin synthesizer VCO configuration
High-Frequency-Products
1
28
Xtalout
VCC
2
27
SDA
PDLOOP
3
26
SCL
TUNE
4
25
CAS
GND
5
24
P0
P1
6
23
RFINY
OB1
7
22
RFINX
OB2
8
21
GAIN
P2
9
20
QOUT
PDOUT
10
19
IOUT
BUSMODE
11
18
VCC1
GND1
12
17
IFIN
IFOUT
13
16
GND2
QFOUT
14
15
QFIN
P-TSSOP-28-1
QOSZ
2
26.1.01
Preliminary Specification
5
TUA6100B6
Pin Definitions and Functions
Pin No.
Symbol
Function
P-TSSOP-28
6
1
QOSZ
Reference oscillator input / Crystal
2
VCC
3
PDLOOP
4
TUNE
Synthesizer Loop filter high voltage tuning output
5
GND
Ground for I2C / 3-wire bus and synthesizer
6
P1
7
OB1
VCO for synthesizer, stripline input 1
8
OB2
VCO for synthesizer, stripline input 2
9
P2
10
PDOUT
11
BUSMODE
12
GND1
Ground for analog part; LO and 0/90 phase generator
13
IFOUT
Base band I output
14
QFOUT
Base band Q output
15
QFIN
Q baseband filtered input signal
16
GND2
Base band Ground
17
IFIN
18
VCC1
Power supply voltage for analog part; LO and 0/90phase generator
19
IOUT
Base band I output for base band filter
20
QOUT
Baseband Q output for baseband filter
21
GAIN
AGC voltage input
22
RFINX
23
RFINY
24
P0
25
CAS
CAS input for I2C bus, Enable input for 3-Wire-bus
26
SCL
Clock input for I2C bus, Clock input for 3-Wire-bus
27
SDA
SDA input/output for I2C bus, Data input for 3-Wire-bus
28
Xtalout
Power supply voltage for I2C / 3-wire bus and synthesizer
Synthesizer Phase detector Charge pump output / Loop filter input
Port 1 output
Port 2 output
Phase detector loop filter of internal GHz-PLL
Selection of I2C / 3-wire bus
I baseband filtered input signal
RF differential input signal (950-2150MHz)
Port 0 output
Buffered crystal oscillator output
Applications
DBS, DVB-S, DSS Set-Top Boxes,
any I/Q Downconverter from 950 MHz - 2150 MHz to frequencies 0 - 30 MHz
High-Frequency-Products
3
26.1.01
7
Port
-55...-15 dBm
@ 50 Ω symm.
- 9 dBm
30 MHz
Basebandfilter
Xtalout
SDA
Clock
CAS
P0
RFinY
RFinX
GAIN
Qout
Iout
28
27
26
25
24
23
22
21
20
19
digital
power
supply
Ports
Buffer
4
Tuning
16
Synthesizer VCO
analog
power
supply
2
3
4
5
6
7
8
9
10
QOSZ
VCC
PDLOOP
TUNE
GND
P1
OB1
OB2
P2
PDout
Tank Circuit
9 MHz
Loopfilter
11
Busmode
12
13
14
Gnd1
IFout
QFout
+ 4 dBm output
26.1.01
TUA6100B6
1
2 kHz
Loopfilter
15
Dual 16 dB
Baseband
Amplifier
Low Noise
Bandgap
Crystal
QFin
Loop
Active
Loopfilter
Crystal
Oscillator
Gnd2
Power
Regulation
GHz PLL (4 x Fin)
Quadratur Phase
Generator
GHz
Prescaler
17
Dual 16 dB
Baseband
Amplifier
-10..30 dB Gain
CMOS
Synthesizer
PLL
18
IFin
Preliminary Specification
Dual
I /Q
Mixer
VCC1
Block Diagram
High-Frequency-Products
Bus Control
Preliminary Specification
8
TUA6100B6
Circuit Description
The main function of the chip is split into bipolar analog signal processing, bipolar digital signal
generation of 0/ 90 LO-signal and a CMOS synthesizer.
Extremely symmetrical layout with matched structures promises best phase and gain balance of the
inphase and quadraturephase signals.
8.1 Input Mixer
Parameter see RF input (950-2150MHz) symm. balanced signal on page 23
Main function is the conversion of a preselected satellite 1. IF band into the inphase and
quadraturephase baseband signals.
The input stage of the mixer is directly combined with a new patented differential input gain control of
30 dB control range and a double balanced mixer with additional gain control of 15 dB in the output.
The integration of the gain control into the mixer cell results in high compression point / IP3 at full
attenuation and requires low chip area .
The differential input has low impedance and is designed for 50 systems with a certain mismatch.
Due to the built in gain control the mixer conversion gain varies between -10 and +35 dB.
The output is internal DC-coupled to the first base band amplifier.
For best performance the 0/ 90 LO-signal is fed to the mixer via open collector stages with well
defined output impedance and levels.
The AGC voltage input is positive DC-controlled, that means 0.5V - min. gain, 3V - max. gain,
with MOS high impedance input.
The characteristic of the RF gain control range is mainly non linear .
8.2 Baseband Amplifier
Parameter see Base band I / Q output, on page 23
and Base band I / Q output filtered, on page 24
The 4 base band amplifiers are of wide-band operational type with high overshoot margin.
The DC reference voltage is internal set to 2.15 V dc .
All the amplifiers have a fixed gain of 16 dB and 30 MHz-0dB bandwidth.
The distribution of the whole DC-gain into two AC-coupled 16 dB amplifiers ensures that the
base band amplifiers are not overdriven by a large DC-voltage that may be caused by mixer offset or
mixer LO feedback to the input.
All 4 outputs can be disabled by bus control. (Register 02,D14)
In this state the outputs switch to low voltage and low impedance.
8.3 Output Ports
Parameter see Port outputs, P0, P1, P2 on page 26
The output ports are designed with open collector transistor for high current pull down and slow
switching application.
8.4 Reference Voltage
Parameter see Power supply on page 23
The central reference voltage is a low noise high PSSR bandgap with approx. 2.4 V DC and
low temperature drift.
8.5 Reference Oscillator
Parameter see Reference oscillator input / Crystal on page 24
The reference oscillator input is the low impedance feedback of a cascode amplifier and uses the
low series resonance of a crystal to generate an oscillation condition.
For a wide characteristic range the reference oscillator can use crystals from 1 - 16 MHz and may be
used as external AC-coupled reference input if no crystal is present.
High-Frequency-Products
5
26.1.01
Preliminary Specification
TUA6100B6
8.6 Crystal Oscillator Output
Parameter see Crystal oscillator output on page 26
To reduce the amount of application components in combination with a digital QPSK demodulator, the
TUA 6100 offers an buffered Push-Pull output of the crystal oscillator. The frequency is the crystal
frequency and is not programmable, the output signal is always on.
8.7 Synthesizer Loop filter
Parameter see Synthesizer Loop filter high voltage tuning output on page 25
The synthesizer active loop filter consists of a simple inverting BICMOS amplifier with MOS input and a
special open collector output transistor which can handle high voltage and high output currents.
The loop filter input is internal connected to the phase detector / charge pump output.
The BICMOS amplifier output may be disabled (high Z) by bus, control register (Register 00,D0).
8.8 Synthesizer VCO
Parameter see Synthesizer VCO on page 26 .
The synthesizer VCO is a symmetrical Colpitts type oscillator with an external tank circuit.
The tank circuit consists of two microstrip lines connected to the oscillator bases and at the
microstrip line ends two serial connected varicap diodes. These diodes are driven by the
tuning voltage.
The synthesizer VCO oscillates at a programmed offset to the input frequency.
This guarantees minimum oscillator pulling and self-mixing with the result of undesirable
DC-signal voltage.
The offset may be at low side or high side of the input signal or zero (that means Fvco = Finput ).
The VCO tuning range is digital split into 2 or 3 bands controlled by the internal GHz PLL.
(not possible if operation Fvco = Finput is desired for the hole tuning range)
Advantages :
• only one optimized VCO for the complete tuning range which is approx. 1 : 2.34
(due to the KVCO and Loop bandwidth variation it is difficult to obtain this range by one
conventional VCO with constant low phase noise) .
• reduced external components
• smaller package
• lower phase noise due to the reduced tuning range of VCO
• lower synthesizer loop filter bandwidth variation
• lower maximum tuning voltage.
Detailed programming tables see GHz PLL programming on page 9 .
8.9 Phase Shift 0 / 90
Parameter see Synthesizer PLL on page 25
To get minimum quadrature phase error, a digital generation of the 0/90 phase shifted local
oscillator signal is implemented by a 3.8-8.6 GHz Johnson-counter This counter is designed in high speed stacked ECL bipolar technology.
8.10 GHz VCO
Two On-Chip bipolar LC-Oscillators (3.4-6.2 GHz and 6.0-8.6 GHz) controlled via On-Chip PLL .
The GHz VCO’s oscillate at 4 x of the input frequency and are current controlled.
The resonant circuit is an on chip symmetrical inductor driven by differential pair amplifier whose
current variable parasitic capacitance is used for frequency tuning.
The used special multi-tanh gilbert cell makes a wide tuning range possible.
The complete GHz VCO’s are under control of a 3.8-8.6 GHz PLL system.
The reference frequency of this system is the output of the synthesizer VCO divided by a
programmable counter; variation is 118-538 MHz(depending on the selected synthesizer tuning range).
At the same time this is the operating frequency range of the phase detector / charge pump.
The high speed charge pump is completely on chip and designed in BICMOS technology with an
external loop filter bandwidth set to 9 MHz.
The GHz VCO frequency is fed to the phase detector via the high speed ECL Johnson counter 4
and a lower speed programmable ECL counter.
High-Frequency-Products
6
26.1.01
Preliminary Specification
TUA6100B6
8.11 GHz PLL
Normally in DCR systems it is necessary that the synthesizer VCO oscillates exact at the desired
receiving frequency.
The following description shows a new patent pending double PLL tuning system without this
requirement and enables some features that other concepts do not have.
The main benefit of this new concept is :
–
–
–
–
–
the accurate 0 / 90° generation of the LO signals for the RF input mixer,
no oscillator on input frequency,
a programmed frequency offset of synthesizer VCO to the RF input frequency and due to that a
very low VCO oscillator pulling and self mixing according to power crosstalk of RF input and
the possibility of splitting the tuning range into bands.
Responsible for these advantages is a 2nd GHz PLL system with two VCO’s at 4 x Fin.
This 2nd GHz PLL system is located in the broken up feedback of the synthesizer PLL 1 between the
VCO1 and the programmable counter input N1. This represents a system of two cascaded PLL’s.
PLL 1 (Synthesizer)
Fref
R1
PD1
PLL 2
VCO1
CP1
R2
PD2
VCO2
CP2
interrupted
PLL 1
X
N : main counter
N1
R : reference counter
PD : phase detector
CP : charge pump
VCO : voltage controlled oscillator
Q2 : Quadraturphase + prescaler
cascaded PLL system
N2
Q2
LO I/Q output
to mixer
This location enables a shift of the synthesizer VCO1 to other frequencies, independent of the
required input LO frequency of the RF mixers.
In this case the synthesizer VCO must not oscillate at the required LO frequency of the mixer input.
Nevertheless the synthesizer PLL is referenced to the LO frequency of the mixer input which makes it
easy to program the PLL because it is set exact to the receiving frequency.
Another benefit is the exact mapping of the PLL stepsize to the tuning frequency.
This is not possible in a conventional PLL tuning system with the feedback of the VCO1 direct to the
programmable counters N1, if the VCO1 is not running on the RF input frequency.
This may become clear in the above concept, if the interrupted PLL 1 is closed and the LO I/Q
output is cut off from node x.
In this case step size and tuning frequency have additional terms of calculation. Depending on the
system concept. they do not fit to the programmed values of the synthesizer PLL 1, because it is
referenced to the VCO1 and no longer to the LO I/Q output.
( following dependencies will become valid, Ftune = (N2 / R2)Fvco1 and Fstep = (N2 / R2)PLL1step ).
The R2 and N2 counters of the GHz PLL enable a programmable frequency offset of the synthesizer
VCO to the RF input as well as a splitting of the required RF tuning range.
For the band splitting feature the counters R2 and N2 of the GHz PLL must be used with 2 different
values (e.g. 4/2 and 4/3). As a result VCO1 will pass his range twice, while the LO I/Q output to mixer
will have a tuning range which is split into 2 bands.
In the feedback of the GHz PLL is located the high speed Johnson-counter (Q2) which acts as
prescaler for the two 3.4 - 8.6 GHz VCO’s and accurate 0 / 90° LO generator.
The complete GHz PLL is designed in high speed ECL cascoded technology which enables counter
frequencies up to 15 GHz , oscillator frequencies up to 10 GHz and phase detector / charge pump
signal slopes of less then 100 ps.
High-Frequency-Products
7
26.1.01
Preliminary Specification
TUA6100B6
8.11.1 Functional GHz PLL Block Diagram
2nd GHz PLL (Quadrature Phase loop)
loop filter
VCO2 4 x Fin
9 MHz
3.4-6.2GHz
6.0-8.6GHz
programming lines
0.95-2.15
R2
N2
GHz
programmable
counter 2/3/4
phase detector
type 4
100-550 MHz
programmable
counter 2/ 3/4
counter2
counter 2
0.4 - 3.3 GHz
Fpd2
counter 2
0.9 - 2.2 GHz
0/90°counter2
2nd loop
reference input
detailed
to the
mixer
I
Q
2nd loop output
drawing
2
F vco = F IQ R
------
N2
2nd GHz-PLL , performing
Quadrature Phase Generator,
Band splitting and VCO offset
Fvco
conventional synthesizer loop
Fvco
Synthesizer VCO
0.4 - 2.9 GHz
reference
oscillator
1-16 MHz
programming lines
I2C / 3-wire bus
programming
Interface
loop filter
2 kHz
synthesizer
input = Fpr
N+A
R
programmable
counter 2-1023
0.5 - 16 MHz
input
Fref
P
modulus.prescaler
32 / 33 ; 64 / 65
programmable
counter 2-2023
phase detector
type 4
DC - 2 MHz
0.5 - 100 MHz
FN
0.2 - 2.5 GHz
programming lines
Synthesizer Loop
High-Frequency-Products
8
26.1.01
Preliminary Specification
TUA6100B6
8.11.2 GHz PLL programming
programmable tuning ranges of the synthesizer VCO controlled by GHz PLL for Fin = 950 - 2150 MHz
F VC O
F I nput
------------------
0.5
0.66
0.75
1
1
1
1.33
1.5
2
2
--4
2
--3
3
--4
2
--2
3
--3
4
--4
4
--3
3
--2
4
--2
Possibilities of 2 band splitting without VCO at input frequency
GHz-PLL
R 2 R-Counter
------N 2 N-Counter
1:1.51 tuning range
Fvcomin
Fvcomax
712
712
<- + ->
1076
1076
1900
2870
<- + ->
1900
2870
MHz
Finmin
Finmax
949
1424
<- + ->
1434
2152
1425
2152
<- + ->
950
1435
MHz
Possibilities of 3 band splitting without VCO at input frequency
1:1.53 tuning range
Fvcomin
Fvcomax
700
1075
830
934
712
934
2173
2867
2182
2445
1900
2910
MHz
Finmin
Finmax
1400
2150
1245
1400
949
1245
1630
2150
1455
1630
950
1455
MHz
low side VCO
VCO at Fin
R2
F vco = ------- F in
N2
band switching
at 1430 MHz
R2
F vco = ------- F in
N2
band switching
at 1455, 1630
1245, 1400 MHz
high side VCO
Note: the maximum operating frequency of the synthesizer VCO is 2.9 GHz
for the low side VCO mode and VCO at Fin application is not yet available.
8.11.3 Synthesizer VCO band switching
Programming tables of the synthesizer VCO band switching controlled by the GHz-PLL
Register 01
Subaddress 01H
D23
GHz VCO
Switch
0
3.4-6.2 GHz
1
6-8.6 GHz
Register 01
Subaddress 01H
N12
D21
N02 N-Counter
D20 GHz-PLL
R12
D13
R02 R-Counter
D12 GHz-PLL
0
0
:3
0
0
:3
0
1
:4
0
1
:4
1
0
:2
1
0
:2
1
1
:3
1
1
:3
recommended
switching at 1525 MHz
RFin below 1525 MHz
Register 02
Subaddress 02H
recommended switching for band splitting
(high side VCO), Fvco = 1900 - 2870 MHz
1
0
:2
0
1
:4
3.4-6.2 GHz
1
0
:2
0
0
:3
RFin above 1525 MHz
0
0
:3
0
1
:4
0
1
6-8.6 GHz
RFin
2 band
RFin
3 band
< 1430 MHz < 1455 MHz
not used
1455-1620
MHz
> 1430 MHz > 1620 MHz
(low side VCO), Fvco = 712 - 1076 MHz
0
1
:4
0
0
:3
0
0
:3
1
0
:2
0
1
:4
1
0
:2
< 1430 MHz < 1245 MHz
not used
1245-1400
MHz
> 1430 MHz > 1400 MHz
The GHz VCO must be switched in any case at RFin =1525 MHz if a tuning range including frequencies below
and above 1525 MHz is used.
High-Frequency-Products
9
26.1.01
Preliminary Specification
TUA6100B6
8.12 Synthesizer PLL
Parameter see Synthesizer Phase detector Charge pump output / Loop filter input and Synthesizer PLL
( page 25).
The PLL block forms a digitally programmable phase locked loop (PLL) with a serial bus control.
The circuit consists of a serial control logic, a high frequency dual modulus prescaler, an A- and
a N-counter with dual modulus control logic, a reference- (R-) counter, and a phase detector with
lock detector and charge pump output.
8.12.1 Serial Bus Control Logic
For TUA6100 the combi-bus is selectable between I 2C and 3-wire-busmode by pin
BUSMODE ( I2C = low, 3W = high ).
All bus pins (CLOCK, DATA, ENABLE and BUSMODE) are Schmitt-triggered with input buffer for
3V or 5V C.
Programming of the IC is done by a serial data protocol with sub addressing. The contents of the
message is assigned to the functional units according to the preceded sub addresses.
Before programming the counters the control register (sub address 00Hex) should be set.
The data bit stream starts with the most significant bit (MSB) and is shifted in on the low to high
transition of the clock signal.
• I2C bus mode
In this mode four different chip addresses can be set by appropriate DC level at pin ENABLE which has
in this case the function of a chip address select (CAS). The pin DATA is a bidirectional input/output pin
for serial data (SDA) from and the acknowledge bit (ACK) to the microcontroller (µC).
Data Transition:
Data transition on the pin DATA must only occur when the serial clock (SCL) is low.
SDA transitions while SCL is high will be interpreted as start or stop condition.
Start Condition (STA):
A start condition is defined by a high to low transition of the SDA line while SCL is at a stable high
level.This start condition must precede any command and initiate a data transfer onto the bus.
Stop Condition (STO):
A stop condition is defined by a low to high transition of the SDA while the SCL line is at a stable
high level. This condition terminate the communication between the devices and forces the bus
interface into the initial conditions.
Acknowledge (ACK):
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data.
During the 9th clock cycle the receiver will pull the SDA line to low level to indicate it has received
the 8 bits of data correctly.
Data Transfer Write Mode:
To start the communication, the bus master must initiate a start condition, followed by the 8bit chip
address (write). The chip address for the TUA 6100 is fixed as ”11000xyz” (MSB at first).
The last significant bit (LSB=z) of the chip address byte defines the type of operation to be
performed: z=1 means, a read operation is selected and z=0 means, a write operation is selected.
After the successful comparison of the transmitted chip address with the fixed one include the
hard-switched chip address select bits CAS2=x and CAS1=y, the serial control logic of the TUA6100
will generate an ACK. Otherwise the processor must break off the data transfer.
After this device addressing the desired subaddress byte and data bytes must be followed. The
subaddresses determines which one of the data bytes (00H...03H) is transmitted first.
At the end of the data transition the master must generate the stop condition.
High-Frequency-Products
10
26.1.01
Preliminary Specification
TUA6100B6
Data Transfer Read Mode:
To start the communication in the read mode, the bus master must initiate a start condition,
followed by the 8bit chip address (write: z=0) and by the subaddress (80H) of the read register.
Then followed by the chip address (read: z=1). After that procedure the 8bit data register 80H
is read out. When the first byte(s) read out the µC mandatory send LOW during the ACK-clock, but
after the last byte is read out the µC mandatory send HIGH (neg. ACK) during the ACK-clock.
At the end of data transition the master must be generate the stop condition.
• 3-wire bus mode
Pin DATA is in this mode only data input. There is no data output. Pin ENABLE is used to activate the
bus interface and to allow the transfer of data to the device. When ENABLE is in an inactive high state,
shifting is inhibited.
Data Transition:
Data transition on the pin DATA must only occur when the clock SCL is low. To transfer data to
the device, ENABLE (which must start inactive high) is taken low. A serial data transfer is made
via DATA and CLOCK when ENABLE is taken back high. The bit stream doesn’t need a chip
address.
Data Transfer Write Mode:
To start the communication, the signal ENABLE is taken low. The desired subaddress byte and
data bytes must be followed. The subaddresses determines which one of the data bytes (00H...03H)
is transmitted first. At the end of the data transition the bus ENABLE must be high.
Data Transfer Read Mode:
To start the communication in the read mode, the ENABLE is taken low, followed by the subaddress
read (xxH). After that the device is ready to read out the xbit data register xxH. At the end of the
data transition the ENABLE must be high.
• Dual Modulus Prescaler
The dual modulus prescaler up to 2.5 GHz is switchable between divide ratio 32/33 and 64/65 by the
bit D22 in the A/N-counter subaddress (01H). Input frequency of the prescaler is the divided
GHz-VCO-frequency 4 with the range of 950 MHz .. 2150 MHz.
• R-Counter and A- / N-Counter
The TUA 6100 has a 10-bit counter for the R-path and a 7-bit and 11-bit counter for the A-/N-path.
The input frequency for the R-counter is the buffered XTAL-frequency (1-16 MHz). Tuning steps can be
selected by the programmable R-counter from fR = 31.25 kHz ..1 MHz (fXTAL=16MHz).
The output frequency of the prescaler (14 MHz..70 MHz) passes the programmable dual modulus
A-/N-counter which switches the prescaler and make available the comparison frequency fV for the
digital frequency / phase detector.
• Phase Comparator (Frequency/Phase Detector)
The digital phase and frequency sensitive phase detector generates a phase error signal UP or DOWN
according to the phase difference between fR (R-counter output) and fV (N-counter output).
This phase error signal drives the charge pump current generator.
Polarity is changeable via bus (bit D4 of the control register), it must be negative for TUA6100
application note.
If the positive edge of the divided VCO signal appears prior to the positive edge of the reference signal,
the DOWN-output pulses for the duration of the phase difference.
In the reverse case the UP-output pulses.
If the two signals are in phase (PLL is locked), the phase detector produces an output signal with fixed
anti-backlash impulses in order to prevent a dead zone for very small phase deviations.
Therefore phase differences of less than 100 ps can be resolved.
In general the shortest anti-backlash pulse gives the best system performance.
High-Frequency-Products
11
26.1.01
Preliminary Specification
TUA6100B6
• Charge Pump
The charge pump generates defined pulses of current (I+ and I-) by the phase detector UP- and DOWN
signals. If the PLL is locked and the bit D1 of the control register is LOW, the charge pump
output (pin 3: PDLOOP) goes into the high-impedance state.
There are four current values selectable by bit D2 and D3 of the control register (subaddress 00H).
Note : only 100µA and 1mA are optimized.
The synthesizer charge pump output may be disabled (high Z) by bus, control register(Register 00, D1).
• Lock Detector
The lock detector indicates when the PLL is locked (lock_in: LD_out = high).
It is possible to put out the lock detect signal to the ports P0 or P2, by the control register
bits D5 and D6.
In this case the content of the respective control register bit for port P0 or P2
( D18 of subaddress 01H or D10 of subaddress 02H ) is not active.
Parallel the lock detector information may be read out by bus ( D7 of subaddress 80H ).
High-Frequency-Products
12
26.1.01
ri
fR
10-Bit R-Counter
fV
Status
SCL / CLK
PD
IDOWN
Data Reg. Ctr. 2
CPext
8-Bit Shift Register
SDA / DA
8-Bit Shift Register
8-Bit Shift Register
LockDetector
CAS-
13
CAS /
I+
Phase
Detector
Decoder
Data Register
Data Register
Data Reg. Ctr. 1
Vcc
GND
LD
Port 0
(LD)
Test mode
7-Bit A-Counter
rf
Prescaler
64 / 65
32 / 33
11-Bit N-Counter
4-bit
fi
Dual Modulus Control
Xtal out
VCO
Switch
26.1.01
TUA6100B6
rf
P / (P+1)
Port 2
(LD)
8-Bit Load SR
5-bit
fi =
Port 1
Preliminary Specification
Data Register
Serial
Control
Logic
UP
Iref
8.12.2 Functional Synthesizer PLL Block Diagram
High-Frequency-Products
Charge
Pump
Preliminary Specification
TUA6100B6
8.12.3 Divide ratio programming
Because of DCR concept the tuning frequency of the RF input controlled by the PLL is given below:
rf =
ri
M
P N + A ---- = ----- ri
R
R
with
rf :
ri :
P:
A:
N:
R:
M = (PN)+A :
frequency of RFinput
reference frequency input (crystal oscillator)
divide ratio of the prescaler [ P/(P+1) = (32/33) or (64/65) ]
divide ratio of the A-counter (max. 7 bit)
divide ratio of the N-counter (max. 11 bit)
divide ratio of the R-counter (max. 10 bit)
total divide ratio of the PLL (with A<N)
Note :
for continuous frequency steps following condition is necessary
AN
P N + A P P – 1 8.12.4 Phase detector outputs
fR
fV
UP
Polarity (internal Signal)
pos.
DOWN
Polarity (internal Signal)
pos.
PD
Polarity
pos.
PD
Polarity
neg.
P-Channel (I+)
Tri-State.
N-Channel (I-)
P-Channel (I+)
Tri-State.
N-Channel (I-)
Frequency fV < fR
or fV lagging
High-Frequency-Products
Frequency fV > fR
or fV leading
14
Frequency fV = fR
(PLL is locked)
26.1.01
Preliminary Specification
TUA6100B6
8.13 Bus Interface
Pin Function
Pin name
BUSMODE
Function
Bus-Mode-Select Serial data
2
I C-mode (I2C)
Data
Low
Data in / out
3Wire mode (3W) High
Data in / out
Clock
Enable
Clock
Enable (3W) / Chip-Address-Select (I2C)
Clock in
Four Chip-Addresses (see below)
High=Inactive, Low=Active
8.13.1 Chipaddress Organisation
(only I2C-Mode)
Chip Address
MSB
LSB
Function
1
1
0
0
0
CAS2 CAS1
0
Chip Address Write
1
1
0
0
0
CAS2 CAS1
1
Chip Address Read
Chip-Address-Select (CAS)
Voltage on Pin
CAS1)
How to do?
CAS2 CAS1
Chip-Address
Hex
Dec
0...0,5 V
Pin CAS external on GND
0
0
C0
192
open circuit
Pin CAS = 1,25 V (intern)
0
1
C2
194
2,0..3,0 V
Rext = 68 kOhm external on
Vcc , tolerance for R ext +-20%
1
0
C4
196
> 4,5
Pin CAS external on Vcc
1
1
C6
198
1) Vcc = 5V, voltage is a function of resistor divider from Vcc
8.13.2 Subaddress Organisation
Sub Addresses of Write Data Registers
MSB
LSB Hex
Function
0
0
0
0
0
0
0
0
00
Control-Register
0
0
0
0
0
0
0
1
01
A/N-Counter
0
0
0
0
0
0
1
0
02
R-Counter
0
0
0
0
0
0
1
1
03
for future use
1
0
0
0
0
0
0
0
80
Status-Register
High-Frequency-Products
15
26.1.01
Preliminary Specification
TUA6100B6
8.13.3 Bus Data Format
I2C-bus write mode
Bit
Function
STA
1
0
0
Bit
MSB
1
CHIP
ADDRESS
(WRITE)
0
0
0
CAS2
CAS1
CAS1
LSB
ACK
S7
S4
S3
S2
MSB
SUB
ADDRESS
(WRITE)
00H...03H
LSB
1
0
0
Function
Bit
Function
S7
MSB
S7
MSB
S5
SUB
ADDRESS
(READ) 80H
S4
S3
0
S2
0
S1
0
LSB
MSB
STA
restart
1
MSB
1
D5
0
D3
Bit
S6
0
...
D4
MSB
3W-bus read mode
S6
SUB
ADDRESS
(WRITE)
00H...03H
S5
S4
S3
S2
S1
S0
LSB
S0
LSB
DX
MSB
DX
MSB
DATA_IN X...0
(X=7, 15 or 23)
0
0
CHIP
ADDRESS
(READ)
...
...
D5
D5
D4
D3
DATA_IN X...0
(X=7, 15 or 23)
D4
D3
D2
CAS2
D2
D2
D1
CAS1
D1
D1
D0
SUB
ADDRESS
(READ) 80H
ACK
ACK
DX
3W-bus write mode
LSB
0
S1
S0
0
CHIP
ADDRESS
(WRITE)
ACK
S6
S5
MSB
1
CAS2
0
Function
STA
1
0
I2C-bus read mode
LSB
1
ACK
ACK
STO
DX
LSB
D0
LSB
D0
DATA_OUT
FROM
SUB ADD
X...0 (X=7)
LSB
MSB
...
D5
D4
D3
D2
DATA_OUT
FROM
SUB ADD
X...0 (X=7)
D1
D0
LSB
1
STO
High-Frequency-Products
16
26.1.01
Preliminary Specification
TUA6100B6
8.13.4 Data Byte Specification
Register 00
Subaddress 00H
Control - Register
Register 01
Subaddress 01H
A/N-Counter,Ports,VCO
Register 02
Subaddress 02H
R-Counter,Ports,VCO
Register 03
Subaddress 03H
for future use
Bit
Bit
Bit
Bit
Function
MSB Test-Mode /
D7
Normal-Mode
Function
MSB
GHz VCO Switch
D23
Function
MSB not used
D15 (must be=0)
Function
MSB
D7
D6
Test-Modes (in/out)
LockDetect (on/off)
D22
Prescaler Switch
32/33 <--> 64/65
D14
Base band
amplifier disable
D6
-
D5
LockDetect-Out
on Port 0 / 2
D21
N12
D13
R12
D5
-
D4
Phase Detector
polarity (+/-)
D20
N02
D12
R02
D4
-
D19
Port 1
D11
not used
D3
-
D18
Port 0
D10
Port 2
D2
-
0
D9
29
D1
-
D0
LSB
-
D3
D2
ChargePump current
100/500µA ,1/2mA
2
N-Counter
GHz-PLL
1
R-Counter
GHz-PLL
Charge Pump
(on/off)
D17
D0
Loop filter OP
LSB (on/off)
D16
29
D8
28
D15
28 divide
D7
27
D14
27
D6
26
D13
26
D5
D12
25 synthesizer
D4
D3
25 synthesizer
24
R-Counter
23
D1
ratio of the
Register 80
Subaddress 80H
Status - Register (READ)
D11
24
D10
2
3
D9
22 2 ....2047
D1
Bit
Function
D8
21
D0
20
LSB
MSB
LockDetect-Out
D7
D7
20
D6
D6
26
D5
D5
25
D4
D4
24 ratio of the
D3
23
D2
22
D1
D1
21 A-Counter
D0
LSB
D0
LSB
20 0 ....127
D3
D2
for future use
all bits high
High-Frequency-Products
N-Counter
D2
divide
ratio of the
22 2 ....1023
21
divide
synthesizer
17
26.1.01
Preliminary Specification
Control-Register
(Register 00) ---> Subaddress 00H
Bit
Test-Mode:
It is possible to switch into an internal chip test mode
by bit D7 of the control register (subaddress 00H).
If test mode is activated there are two test options
available by bit D6 of the control register:
Function
MSB
D7
0
Normal-Mode
1
Test-Mode
D7 must be = 1 (Test-Mode)
D6
0
R-counter / 2 -> output to Port P0
N-counter / 2 -> output to Port P1
1
Port P0 -> input to R-counter
Port P1 -> input to N-counter
D6 = 0 --> Test-Mode1:
In this case the output frequencies of the
counters divided by 2 ( ! ) are put out to the
Ports P0 ( R-counter output frequency / 2 )
and P1 ( N-counter output frequency / 2 )
Nevertheless the phase detector and the
charge pump are in function
( lock detector = OFF ).
D7 must be = 0 (Normal-Mode)
0
Bit D5 not active
1
Bit D5 active
D6 = 1 --> Test-Mode2:
In this case the phase detector, charge pump
and lock detector (= ON) can be tested by
external frequencies which are applied to the
Ports P0 (path of the R-counter frequency)
and P1 (path of the N-counter frequency).
( Note: LD_out only on port P2 visible! )
D5 is only active for D6 = 1, D7 = 0
D5
D4
0
LockDetect output on Port 0
1
LockDetect output on Port 2
0
PhaseDetector polarity negative
1
PhaseDetector polarity positive
D3 D2 Synthesizer ChargePump current
D3
D2
D1
D0
LSB
0
0
100µA
0
1
500µA
1
0
1mA
1
1
2mA
D18
Bit
Function
MSB
D7
0
synthesizer PLL unlocked
1
synthesizer PLL locked
Synthesizer ChargePump disabled
D6
1
1
Synthesizer ChargePump enabled
.....
1
0
Synthesizer Loopfilter OP disabled
1
Synthesizer Loopfilter OP enabled
D0
LSB
1
for future use, all bits = 1
Prescaler, Ports, GHz-PLL
(Register 01) ---> Subaddress 01H
Ports, GHz-PLL
(Register 02) ---> Subaddress 02H
Bit
Bit
D22
D19
Status-Register (READ)
(Register 128) ---> Subaddress 80H
0
MSB
D23
D21
D20
TUA6100B6
Function
0
GHz VCO = 3.4-6.2 GHz
1
GHz VCO = 6-8.6 GHz
0
Prescaler divide ratio 32/33
1
Prescaler divide ratio 64/65
D21
D20
N-Counter GHz-PLL
0
0
:3
MSB
D15
D14
D13
D12
Function
0
not used (must be=0)
0
base band amplifier enabled
1
base band amplifier disabled
D13
D12
R-Counter GHz-PLL
0
0
:3
0
1
:4
0
1
:4
1
0
:2
1
0
:2
1
1
:3
1
1
:3
0
Port_1 output = low level
1
Port_1 output = high level
0
Port_0 output = low level
1
Port_0 output = high level
High-Frequency-Products
D11
D10
18
0
-
1
-
0
Port_2 output = low level
1
Port_2 output = high level
26.1.01
Preliminary Specification
TUA6100B6
8.13.5 Bus Timing
I2C Bus
BUS_MODE = LOW
tBUF
SDA
tLOW tR
tSP
tF
SCL
S tHD.STA
P
tHD.DAT tHIGH
tSU.DAT
tHD.STA
S
tSU.STA
tSU.STO
P
CAS
(ENABLE)
tSU.ENASDA
tSU.ENASDA
tSU.ENASDA
S - START condition
P - STOP condition
3W-Bus
BUS_MODE = HIGH
DATA
tLOW tR
tSP
tF
CLOCK
tWHEN
tHD.STA
tHD.DAT tHIGH
tSU.DAT
tSU.STO
ENABLE
S
P
tSU.SCLENA
tSU.SCLENA
High-Frequency-Products
19
26.1.01
Preliminary Specification
Parameter
see also I2C and 3-Wire-bus on page 26
Symbol
LOW level input voltage
(DATA, CLOCK, ENABLE, BUS_MODE)
TUA6100B6
Limit Values
Unit
min.
max.
VIL
-0.5
0.96
V
HIGH level input voltage
(DATA, CLOCK, ENABLE, BUS_MODE)
VIH
2.24
5.5
V
Hysteresis of Schmitt trigger inputs
VHys
1.12
V
Pulse width of spikes
which must be suppressed by the input filter
tSP
0
50
ns
LOW level output voltage (DATA), only I2C-bus
at 3mA sink current
at 6mA sink current
VOL
0
0.4
0.6
V
tOF
20+0.1C b1) 250
ns
fSCL
0
400
kHz
tBUF
1.3
--
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is generated. 2)
tHD.STA
0.6
--
µs
LOW period of the SCL clock
tLOW
1.3
--
µs
HIGH period of the SCL clock
tHIGH
0.6
--
µs
Set-up time for a repeated START condition 2)
tSU.STA
0.6
--
µs
Data hold time
tHD.DAT
0
Data set-up time
tSU.DAT
100
Rise time, fall time of SDA and SCL signals
tR, tF
20+0.1C b1) 300
ns
Set-up time for STOP condition 2)
tSU.STO
0.6
--
µs
Setup time BUS_ENA to SDA 2)
tSU.ENASDA 0.6
--
µs
tSU.SCLENA 0.6
--
µs
Output fall time from VIH min to VIL max with
a bus capacitance from 10pF to 400pF
with up to 3mA sink current at VOL
SCL clock frequency
Bus free time between a STOP and START condition
Setup time CLOCK to BUS_ENA
2)
3)
ns
--
ns
H-pulse width (BUS_ENA) for new data protocol 3)
tWHEN
0.6
--
µs
Capacitive load for each bus line
Cb
--
400
pF
1) Cb= capacitance of one bus line in pF
Note that the maximum tF for the SDA and SCL bus lines quoted in table above (300ns) is longer than the specified maximum tOF
for the output stages (250ns).This allows series protection resistors to be connected between the SDA/SCL pins and the SDA/SCL
bus lines without exceeding the maximum specified tF .
2) only for I2C bus mode
3) only for I2C bus mode
High-Frequency-Products
20
26.1.01
Preliminary Specification
9
TUA6100B6
Electrical Characteristics
9.1 Absolute Maximum Ratings
The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as
permanent damage to the IC will result.
Parameter
Symbol
Supply voltage
Limit Values
Units
min.
max.
VVCC
- 0.3
5.5
V
Supply voltage 1
VVCC1
- 0.3
5.5
V
Crystal oscillator
VQOSZ
VVCC-3 > 0
VVCC-1 > 0
V
Crystal oscillator buffered output
VXTALOUT
0
VVCC
V
Synthesizer Charge pump out Loop filter in
VPDLOOP
0
VVCC
V
Synthesizer Loop filter tuning output
VTUNE
- 0.3
35
V
VCO inputs
VOB1,VOB2
0
VVCC
V
VP0,P1,P2
0
VVCC
V
IP0,P1,P2
15
mA
IP0,P1,P2
30
mA
t Imax
1
ms
Port outputs
Port outputs , VP0,P1,P2 = VVCC, I=max
GHz-PLL Charge pump out
VPDOUT
0
VVCC
V
Baseband outputs I / Q
VIOUT , QOUT
IIOUT , QOUT
0
VVCC1
V
4
mA
Baseband filtered inputs I / Q
VIFIN,VQFIN
0
VVCC1
V
VIFOUT , QFOUT
0
VVCC1
V
4
mA
Baseband filtered Output I / Q
IIFOUT , QFOUT
AGC voltage
VAGC
0
VVCC1
V
RF input
VRFINX , RFINY
0
1.5 < VVCC1
V
I2C / 3-Wire-Bus
SCL, SDA,CAS
- 0.3
BUSMODE
VVCC+0.3
V
All values are referred to ground (pin), unless stated otherwise.
All currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink
(the current flows into the stated pin to internal ground), it has a negative sign,
and if it is a source (the current flows from Vs across the designated pin), it has a positive sign.
High-Frequency-Products
21
26.1.01
Preliminary Specification
Parameter
TUA6100B6
Limit Values
Symbol
min.
max.
Units
Absolute Maximum Ratings continued
ESD-Protection pin 4, Tune 1)
VESD
- 500
500
V
ESD-Protection all other bipolar pins 1)
VESD
-1
1
kV
ESD-Protection all CMOS pins 1)
VESD
-1
1
kV
Total power dissipation
Ptot
687.5
mW
Ambient temperature
TA
see note
°C 2)
Junction temperature
Tj
125
°C
Storage temperature
Tstg
150
°C
Thermal resistance junction case
Rth
2
K/W
- 20
- 40
1) all ESD tests done according to EIA/JESD22-A114-B (HBM incircuit test), as a single device incircuit contact discharge test.
2) The maximum ambient temperature dependends on the mounting conditions of the package.
Any application mounting must guarantee not to exceed the maximum junction temperature of 125 °C.
As reference the thermal resistance junction to case is given.
To reach a high ambient temperature, a good solution is a 2-layer PCB board with complete GND plane under the chip body and
a 2nd complete layer ground plane. Additional the area under the chip body should be equipped with as many via holes as
possible, solded to the 2nd layer. Not used pins should be solded to GND if possible (e.g. unused ports).
9.2 Operating Range
Within the operational range the IC operates as described in the circuit description.
The AC / DC characteristic limits are not guaranteed.
Parameter
Symbol
Supply voltage
Limit Values
Unit
min
max
VVCC
4.5
5.5
V
Supply voltage 1
VVCC1
4.5
5.5
V
Difference between VCC...VCC1
and between GND...GND1
-0.3
0.3
V
Current consumption
Ivcc+vcc1
125
mA
Input frequency range of mixer
fRFIN
950
2150
MHz
VCO frequency range
fVCO
0.7
3
GHz
Synthesizer Loop filter tuning output
VTUNE
0.5
33
V
Ambient temperature
TA
- 20
see note
C
High-Frequency-Products
V
22
Test Conditions
2)
26.1.01
Preliminary Specification
TUA6100B6
9.3 AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient
temperature range. Typical characteristics are the median of the production.
Parameter
TA = 25 C,VVCC, VVCC1 = 5V
Symbol
Limit Values
min
typ
max
110
125
Unit
Test conditions
mA
RL>1M ,C L<1.5pf
Power supply
Total current consumption
IVCC+IVCC1
RF input (950-2150MHz) symm. balanced signal
(see Input Mixer on page 5) RF source impedance 50
Input frequency
fRFIN
minimum input RF level
VRFIN
maximum input RF level
VRFIN
Input impedance differential
without any application
balanced input, test circuit see page 27
950
-55
2150
MHz
balanced
-50
dBm
balanced 1100 MHz
-15
dBm
balanced 1100 MHz
f = 0.9 - 2.2 GHz
see diagrams
13.5 and page 38
R RFIN
15
LRFIN
1.3
n
Input gain control range
A
40
Internal mixer gain
A
-10
43
45
dB
30
dB
VGAIN=0.4...2.6V
see diagrams 13.4
VCO power present at RF input
- 60
- 50
dBm
LO power present at RF input
- 74
- 70
dBm
f = R2 / N2 x fin
f = fin
input compression point -1 dB
-7
-5
dBm
minimum gain
output compression point -1 dB
+ 13
+ 15
dBm
minimum gain,Vcc=5V
Input IP2
+ 28
+ 32
dBm
minimum gain
Input IP3
+1
+5
dBm
minimum gain
Output IP3
+ 21
+ 25
dBm
minimum gain
dB
maximum gain, SSB
Noise Figure @1400 MHz
F
15
16
Base band I / Q output,
IOUT, QOUT, pin 19, 20 ( see Baseband Amplifier on page 5)
DC voltage
VIOUT
VQOUT
2.15
V
RL>1M DC quiescent current
IIOUT,IQOUT
2.7
mA
RL>1M Baseband I/Q output voltage
VIOUT
VQOUT
225
mV pp
RL>1M 35
MHz
f -1 dB
70
MHz
no filter,
IOUT-IFIN 47nF
QOUT-QFIN 47nF
Baseband I/Q output flatness
0.05
0.1
dB
up to 25 MHz
Quadrature error, phase
1
3
deg
Quadrature error, gain
1
2.5
dB
Internal amplifier gain
A
16
Baseband I/Q output impedance
R IOUT,
R QOUT
Baseband I/Q output bandwidth
both amplifiers in series
see diagrams 13.1 and 13.3
High-Frequency-Products
f -0.1 dB
25
1000
50
23
balanced @ 1100 MHz
RFin= -35 dBm,
test circuit
see page 27
dB
internal from mixer
output to I / Q OUT
dynamic resistance
26.1.01
Preliminary Specification
Parameter
TA = 25 C,VVCC, VVCC1 = 5V
Symbol
Limit Values
min
typ
max
TUA6100B6
Unit
Test conditions
I / Q base band filtered input signal
IFIN, QFIN, pin 15, 17 (see Baseband Amplifier on page 5)
DC voltage
VIFIN,V QFIN
2.1
V
see filter on page 33
Baseband I/Q input impedance
R IFIN,QFIN
18
k
see diagrams 13.8
Base band I / Q output filtered,
IFOUT, QFOUT, pin 13, 14 ( see Baseband Amplifier on page 5) symm. balanced input application
DC voltage
VIFOUT
VQFOUT
2.1
V
RL>1M DC quiescent current
IIFOUT
IQFOUT
2.7
mA
RL>1M Baseband I/Q output voltage
VIFOUT
VQFOUT
1
Vpp
RL>1M f - 0.5 dB
3.5
20
22
MHz
f - 1 dB
A
27
30
MHz
no filter,15pf/1k load
IOUT-IFIN 47nF
QOUT-QFIN 47nF
16
dB
VI,QFOUT / VI,QFIN
Group delay variation, see 13.2
both amplifiers in series
-250
250
ps
100kHz ..... 100MHz
Baseband I/Q output impedance
R IFOUT,
R QFOUT
50
dynamic resistance
S/N @ 45 Mbaud
IFOUT,QFOUT
24
26
dB
maximum gain, 1Vpp
S/N @ 45 Mbaud
IFOUT,QFOUT
30
32
dB
minimum gain, 1Vpp
VGAIN
0.4
V
see diagrams 13.4
Base band I/Q output bandwidth
both amplifiers in series
see diagrams 13.1 and 13.3
Amplifier gain
t
AGC voltage input
(see Input Mixer on page 5)
Gain control range
100
2.6
Gain control input impedance
R GAIN
100e
Gain control input clamp voltage
VGAINmax
3.75
Gain control input clamp current
IGAINmax
180
6
V
protected by resistor
A
VGAIN = Vcc1
V
locked
2
mA
see Control-Register
1
nA
VPDLOOP = 2 V ,
guaranteed by design
500
Synthesizer Phase detector Charge pump output / Loop filter input
(see Synthesizer Loop filter on page 6)
DC voltage
VPDLOOP
DC current
IPDLOOP
Tristate output current
IPDLOOP
1.8
0.1
0.1
Reference oscillator input / Crystal
(see Reference Oscillator on page 5)
3.4
DC voltage
VQOSZ
Crystal frequency
f
1
Crystal resistance
f
10
negative input impedance
ZQOSZ
- 500
Drive current
IQOSZ
High-Frequency-Products
4
- 700
135
24
V
16
MHz
series resonance
100
series resonance
- 900
f = 4 MHz
Arms
f = 16 MHz, Cs=18pF
26.1.01
Preliminary Specification
Parameter
TA = 25 C,VVCC, VVCC1 = 5V
Symbol
Limit Values
min
typ
max
TUA6100B6
Unit
Test conditions
Synthesizer Loop filter high voltage tuning output
(see Synthesizer Loop filter on page 6)
LOW output voltage
VTUNE
0
0.5
V
ITUNE = 1.5 mA
HIGH output current
ITUNE
0
10
A
VTUNE = 33V
N-counter divide ratio
N
2
2047
11-Bit, CMOS
A-counter divide ratio
A
0
127
7- Bit, CMOS
R-counter divide ratio
R
2
1023
10-Bit, CMOS
P-counter divide ratio
P
32/33
64/65
Synthesizer PLL
(see Synthesizer PLL on page 10)
-164
Equivalent phase noise at phase
detector input,
@ 1 kHz offset, within loop band
width, 6 kHz loop BW, SSB
-159
-158
-155
-149
Quadrature phase mismatch
1)
1
5/6-Bit, Bipolar
dBc /
Hz
dBc
/Hz
dBc
/Hz
dBc /
Hz
dBc
/Hz
3
Fref = 30 kHz
Fref = 100 kHz
Fref = 125 kHz
Fref = 250 kHz
Fref = 1000 kHz
deg
Total divide ratio
see see 8.12.3 on page 14
M
992
4032
65.631
131.135
PLL tuning step size
(programmable via R-counter)
see Register 02
fref
0.9775
3.91
125
15.650
500
2000
8000 2)
kHz
f crystal = 1 MHz
f crystal = 4 MHz
f crystal = 16 MHz
Continuous step size see 8.12.3
(programmable via R-counter)
fref
32.759
957.66
kHz
P = 32/33
f in = 950 - 2150 MHz
Continuous step size see 8.12.3
(programmable via R-counter)
fref
16.395
235.61
kHz
P = 64/65
f in = 950 - 2150 MHz
f
950
950
950
992
1984
1025
2050
2150
2150
2150
MHz
fref = 15.625 kHz
fref = 31.250 kHz
fref = 62.5 ...500 kHz
fref = 1.000 MHz
fref = 2.000 MHz
Frequency range with
continuous step size
for P = 64/65 3)
f
950
950
1008
2016
2048
2150
2150
2150
MHz
fref = 15.625 kHz
fref = 31.25...166.7 kHz
fref = 250 kHz
fref = 500 kHz
R-counter values for
166.666 kHz step size
R
Frequency range with
continuous step size
for P = 32/33
6
24
96
P=32/33
P=64/65
f crystal = 1 MHz
f crystal = 4 MHz
f crystal = 16 MHz
1)
The minimum total divide ratio is only important for continuous frequency step size, if lower divide ratios
are used not all frequencies are possible. To find out the missing frequencies our Windows control
program for I2C / 3-wire bus may be used.
2) Step sizes > 2 MHz are not guaranteed, 1 MHz continuous step size is only possible for RFin > 992 MHz
3) For low power dissipation the use of the 64/65 prescaler should be preferred if the desired step size fits
High-Frequency-Products
25
26.1.01
Preliminary Specification
Parameter
TA = 25 C,VVCC, VVCC1 = 5V
Symbol
Limit Values
min
typ
max
TUA6100B6
Unit
Test conditions
Synthesizer VCO
(see Synthesizer VCO on page 6)
DC voltage
VOB1,VOB2
high side VCO frequency range
fVCO
1900
2870
MHz
2 band split, page 32
high side VCO frequency range
fVCO
1900
2910
MHz
3 band split, page 32
low side VCO frequency range
fVCO
712
1076
MHz
2 band split, page 32
low side VCO frequency range
fVCO
700
1075
MHz
3 band split, page 32
high side VCO frequency range
fVCO
1424
2151
MHz
+VCO at fin, band split
low side VCO frequency range
fVCO
950
1434
MHz
+VCO at fin, band split
1.9
V
VCO1)
- 53
- 56
- 60
dBc
1 kHz offset, SSB
Phase noise high side VCO
1)
- 73
- 76
- 80
dBc
10 kHz offset, SSB
Phase noise high side VCO
1)
- 93
- 96
- 100
dBc
100 kHz offset, SSB
Phase noise high side
1)
Note : This is the phase noise of the free running VCO, not for the overall system performance at
baseband output. For detailed system phase noise information see diagrams page 30 and page 31 and
our separate application note.
Port outputs, P0, P1, P2
(see Output Ports on page 5)
Supply voltage
VP
0
5.5
V
max. Vcc
LOW output voltage
VP
0
0.5
V
IP = 15 mA
LOW output current
IP
15
mA
HIGH output current
IP
10
A
VP = 5 V
Port outputs, I=max
t Imax
1
ms
VP0,P1,P2=VVCC
Vpp
RL>1M Vcc=5V,
CL = 10 pF, f = 16 MHz
0
Crystal oscillator output
(see Crystal Oscillator Output on page 6)
Buffer output voltage 1)
VXtalout
Buffer output current
IXtalout
Buffer output impedance
R Xtalout
1.1
1
mA
350
I2C and 3-Wire-bus
Clock, Data, Enable, BUS_MODE (see Bus Data Format on page 16 and 8.13.5 Bus Timing on page 19)
HIGH level input voltage
VIH
2.24
VVCC
V
LOW level input voltage
VIL
-0.5
0.96
V
LOW level output voltage
(DATA), only I2C-bus
VOL
0
0.4
0.6
V
Hysteresis of Schmitt trigger inputs Vhys
H-input current
IH
0.2
L-input current
IL
-60
Input capacity
CI
1
3mA sink current
6mA sink current
V
10
5
A
VI = VVCC = 5.5V
A
VI = GND
pF
1) output voltage is dependant on Vcc
High-Frequency-Products
26
26.1.01
100pF
+ 5V P0
100pF
RF
Gain
100 Ω
SDA
Bus Control CAS
10 Test circuit
High-Frequency-Products
100pF
100 Ω
4.7nF
6.8pF
6.8pF
SCL
2.2kΩ
4.7nF
4.7nF
+ 5V
10pF
10pF
100 Ω
Xtalout
825Ω
3.3kΩ
28
27
26
25
24
23
20
27
CMOS
Synthesizer
PLL
Tuning
16
15
Loop
Active
Loopfilter
Crystal
Oscillator
17
Power
Regulation
GHz PLL (4 x Fin)
Quadratur Phase
Generator
GHz
Prescaler
18
Dual 16 dB
Baseband
Amplifier
Wide band
Loop Filter
25 kHz
19
Dual 16 dB
Baseband
Amplifier
Dual
I /Q
Mixer
-10..30 dB Gain
Ports
Buffer
21
Synthesizer VCO
analog
power
supply
Low Noise
Bandgap
1
2
3
4
Preliminary Specification
digital
power
supply
22
825Ω
5
6
7
8
12pF
18pF
9
10
11
12
13
14
12pF
147Ω
100pF
4.7kΩ
147Ω
4.7kΩ
16 MHz
3.3kΩ
+ 33V
33kΩ
1nF
5.6kΩ
100nF
5.6kΩ
1nF
3.3kΩ
1nF
100kΩ
BB857
BB857
+ 5V P1
26.1.01
4.7kΩ
P2 + 5V
1.2nF
100kΩ
I
Q
TUA6100B6
+ 5V
100 Ω
+ 5V P0
100pF
100 Ω
SDA
Bus Control CAS
3.9pF
SCL
3.9pF
47nF
47nF
l=min. 5mm
d=0.65mm
100 Ω
Xtalout
Gain
10Ω
+ 5V
1µH
4.7kΩ
150Ω
28
27
26
25
24
39pF
23
Narrow band
Loop Filter
28
CMOS
Synthesizer
PLL
3 kHz
20
19
18
17
39pF
16
Dual 16 dB
Baseband
Amplifier
Power
Regulation
Loop
Active
Loopfilter
Synthesizer VCO
analog
power
supply
Low Noise
Bandgap
1
2
3
4
5
6
7
8
12pF
18pF
4.7kΩ
15
Dual 16 dB
Baseband
Amplifier
GHz PLL (4 x Fin)
Quadratur Phase
Generator
GHz
Prescaler
Tuning
Crystal
Oscillator
21
Dual
I /Q
Mixer
-10..30 dB Gain
Ports
Buffer
4.7pF
9
10
11
12
13
14
Preliminary Specification
digital
power
supply
22
1µH
150Ω
4.7nF
10pF
22pF
22pF
4.7pF
4.7nF
11 Application circuits
3 kHz typ.
100pF
• high side synthesizer VCO narrow band loop filter example
High-Frequency-Products
RF
100pF
12pF
1nF
4.7kΩ
4 MHz
1nF
+ 33V
220nF
2.2kΩ
4.7nF
10kΩ
1kΩ
I
BB835
BB835
33kΩ
1kΩ
2.2kΩ
4.7nF
Q
26.1.01
TUA6100B6
+ 5V
25 kHz typ.
100pF
100 Ω
+ 5V P0
100pF
100 Ω
SDA
Bus Control CAS
3.9pF
SCL
3.9pF
47nF
47nF
l=min. 5mm
d=0.65mm
100 Ω
Xtalout
Gain
10Ω
+ 5V
1µH
4.7kΩ
150Ω
28
27
26
25
24
39pF
23
21
20
Dual
I /Q
Mixer
-10..30 dB Gain
Ports
Buffer
29
CMOS
Synthesizer
PLL
17
39pF
16
Dual 16 dB
Baseband
Amplifier
Power
Regulation
Synthesizer VCO
analog
power
supply
Low Noise
Bandgap
1
2
3
4
5
6
7
8
12pF
18pF
15
Loop
Active
Loopfilter
Crystal
Oscillator
18
GHz PLL (4 x Fin)
Quadratur Phase
Generator
GHz
Prescaler
Tuning
19
Dual 16 dB
Baseband
Amplifier
Wide band
Loop Filter
25 kHz
4.7pF
9
10
11
12
13
Preliminary Specification
digital
power
supply
22
1µH
150Ω
4.7nF
10pF
22pF
22pF
4.7pF
4.7nF
• high side synthesizer VCO wide band loop filter example
High-Frequency-Products
RF
100pF
14
12pF
4.7kΩ
4.7kΩ
16 MHz
1nF
+ 33V
100nF
2.2kΩ
4.7kΩ
1kΩ
I
BB835
BB835
33kΩ
1kΩ
2.2kΩ
1.2nF
Q
26.1.01
TUA6100B6
+ 5V
Preliminary Specification
TUA6100B6
• Phase noise performance of application
The over all system phase noise at base band of the TUA 6100 is strongly dependent on several
parameter :
1.programming of the 2nd PLL (GHz-PLL setting of the R2 and N2 counter)
2.programming of the 1st synthesizer PLL
- receiving frequency (variation of the VCO steepness due to non linearity of the varicap),
- phase detector current,
- crystal frequency,
- step size = Fref,
- loop filter parameter. ( bandwidth )
A well balanced phase noise over the whole tuning range requires an optimized parameter
programming of the synthesizer PLL for each receiving frequency
- 1st you have to decide for the optimum loop filter bandwidth for your application.
Narrow band loop filter :
achieves better PLL outband phase noise at high frequencies offset but lower PLL inband phase noise at
low frequency offset.
Wide band loop filter :
achieves better PLL inband phase noise at low frequencies offset but lower PLL outband phase noise at
high frequency offset.
- 2nd you have to decide for the crystal frequency for your application.
Higher crystal frequency achieves better PLL inband phase noise.
- 3rd you have to decide for the varicap for your application.
Linear varicaps achieves better balanced phase noise than non linear varicaps.
- 4th you have to decide for the main stepsize for your application.
Higher step size achieve better PLL inband phase noise.
- 5th during programming the desired receiving frequency you have to set step size and phase detector
output current for each frequency. This is necessary to compensate the non linearity of the varicap.
All this is done in our separate application note with the above two application
circuits which obtain the following worst case phase noise values :
Narrow band loop filter
3
3
3
3
kHz
Offset Frequency
1
10
100
1000
kHz
Measured phase noise at base band
- 55
- 76
- 98
- 100
dBc/Hz
Wide band loop filter
30
30
30
30
kHz
Offset Frequency
1
10
100
1000
kHz
Measured phase noise at base band
- 75
- 77
- 91
- 100
dBc/Hz
For detailed information see our separate application note version B5.
High-Frequency-Products
30
26.1.01
Preliminary Specification
TUA6100B6
.
• Optimum phase detector current
valid for the two applications above, band splitting into 2 ranges
Optimum Chargepump current for constant loop bandwidth and phasenoise
3,0
2,8
available current of TUA 6100
low band (ratio 2)
border between 2 currents
high band (ratio 4/3)
2,6
2,4
2,2
2,0
1,8
1,6
1,4
1,2
1,0
0,8
0,6
0,4
0,2
0,0
950
1050
1150
1250
1350
1450
1550
1650
1750
1850
1950
2050
2150
Fin [MHz]
• VCO steepness + phase detector current ranges
valid for the two applications above, band splitting into 2 ranges
Kvco
200
180
Ratio=2
Ratio=4/3
160
140
MHz / V
120
100
80
60
40
0.5mA
20
950
1050
1mA
1150
1250
1350
0.5mA
2mA
1450
1550
1650
1mA
1750
1850
1950
2mA
2050
2150
Finput [MHz]
High-Frequency-Products
31
26.1.01
Preliminary Specification
TUA6100B6
• VCO tuning voltage
valid for the two applications above, band splitting into 2 ranges
F input
2200
2100
2000
1900
Ratio=4/3
1800
Ratio=2
[MHz]
1700
1600
1500
1400
1300
1200
1100
1000
900
2
3
4
5
6
7
8
9
10
Tuning Voltage [V]
11
12
13
14
15
• Receiving frequency band splitting into 2 or 3 ranges
3 band programming reduces the VCO pulling in the frequency range from 1430 to 1630 MHz
high side VCO splitting , 2 + 3 ranges
2900
2800
VCO frequency range
2700
vco 2 ranges
vco 3 ranges
Fvco [MHz]
2600
2500
R2/N2 =4/2 =2.0
R2/N2 = 3/2 = 1.5
R2/N2 = 4/3 = 1.333
2400
2300
1455
1630
2200
Receiving frequency range
2100
2000
1900
900
1430
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
Finput [MHz]
High-Frequency-Products
32
26.1.01
Preliminary Specification
TUA6100B6
12 Base band filter
for 45 MBaud signals
BW = 25 MHz -1dB
Baseband
amplifier
150Ω
47nF
.
.
from
mixer
Baseband
amplifier
4.7pF
.
.
1µH
+16dB
22pF
Baseband
output
15pF
1kΩ
+16dB
39pF
TUA 6100 internal
parasitic
TUA 6100 internal
• Frequency response incl. the two base band amplifiers + output load
40.0
fLow: 25.258meg
-1dB
30.0
fLow: 30.676meg
-3dB
20.0
fLow: 47.546meg
-20dB
dB(V)
10.0
fLow: 56.469meg
-30dB
0.0
fLow: 63.302meg
-40dB
-10.0
fLow: 67.177meg
-50dB
-20.0
-30.0
2meg
3meg
5meg
7meg
10meg
20meg
30meg
50meg
70meg
100meg
200meg
f(Hz)
• Group delay incl. the two +16 dB base band amplifiers + output load
4n
group delay (s)
3n
2n
1n
0.0
-1n
2meg
3meg
5meg
7meg
10meg
20meg
30meg
50meg
70meg
100meg
200meg
f(Hz)
High-Frequency-Products
33
26.1.01
Preliminary Specification
TUA6100B6
13 Electrical Diagrams
13.1 Frequency flatness of base band outputs
without base band filter, both base band amplifiers in series, coupling capacitor 47nF
32.0
31.8
31.6
31.4
31.2
31.0
30.8
(20.033meg, 30.872)
Delta Y: -0.47584
30.6
30.4
dB(V)
30.2
(30.076meg, 30.278)
Delta Y: -1.068
30.0
29.8
29.6
29.4
(40.007meg, 29.511)
Delta Y: -1.8355
29.2
29.0
28.8
28.6
(50.034meg, 28.617)
Delta Y: -2.7339
28.4
28.2
28.0
100.0k
200.0k
500.0k
1meg
2meg
5meg
10meg
20meg
50meg
100meg
50meg
100meg
f(Hz)
13.2 Group delay of base band outputs
without base band filter, both base band amplifiers in series, coupling capacitor 47nF
0.0
-10p
-20p
-30p
-40p
group delay (s)
-50p
-60p
-70p
-80p
-90p
-100p
-110p
-120p
-130p
-140p
-150p
100.0k
200.0k
500.0k
1meg
2meg
5meg
10meg
20meg
f(Hz)
High-Frequency-Products
34
26.1.01
Preliminary Specification
TUA6100B6
13.3 Frequency response of base band outputs
without base band filter, both base band amplifiers in series, coupling capacitor 47nF
35.0
30.0
fHigh: 371.24
-1dB
fLow: 29.503meg
-1dB
25.0
fLow: 53.587meg
-3dB
fHigh: 189.23
-3dB
20.0
15.0
dB(V)
10.0
5.0
0.0
-5.0
-10.0
-15.0
-20.0
1.0
3.0
10.0
30.0
100.0
0.3k
1.0k
3.0k
10.0k
30.0k
f(Hz)
100.0k 300.0k
1meg
3meg
10meg 30meg 100meg 300meg
1g
grop delay (s)
Group delay (coupling capacitor 47nF, low frequencies response is dependent on coupling capacitor)
0.0
-2u
-4u
-6u
-8u
-10u
-12u
-14u
-16u
1.0
3.0
10.0
30.0
100.0
0.3k
1.0k
3.0k
10.0k
30.0k
f(Hz)
100.0k 300.0k
1meg
3meg
10meg 30meg 100meg 300meg
1g
1.0
3.0
10.0
30.0
100.0
0.3k
1.0k
3.0k
10.0k
30.0k
f(Hz)
100.0k 300.0k
1meg
3meg
10meg 30meg 100meg 300meg
1g
30.0k
f(Hz)
100.0k 300.0k
1meg
3meg
10meg 30meg 100meg 300meg
1g
grop delay (s)
0.0
-20n
-40n
grop delay (s)
-60n
0.0
-20p
-40p
-60p
-80p
-100p
-120p
-140p
-160p
1.0
3.0
10.0
30.0
High-Frequency-Products
100.0
0.3k
1.0k
3.0k
10.0k
35
26.1.01
Preliminary Specification
•
TUA6100B6
Group delay at low frequencies, dependent on coupling capacitor
Group delay versus coupling condensator at low frequencies
0.0
-20n
CK=4700nF
CK=47nF
CK=470nF
CK=4.7nF
-40n
group delay (s)
-60n
-80n
-100n
-120n
-140n
-160n
100.0
0.2k
0.5k
1.0k
2.0k
5.0k
10.0k
f(Hz)
20.0k
50.0k
100.0k
200.0k
500.0k
1meg
13.4 RF gain control range
64.0
62.0
60.0
58.0
56.0
54.0
52.0
50.0
48.0
gain variation (dB)
46.0
44.0
42.0
40.0
38.0
36.0
34.0
32.0
30.0
28.0
26.0
24.0
22.0
20.0
18.0
16.0
0.0
0.2
0.4
High-Frequency-Products
0.6
0.8
1.0
1.2
1.4
1.6
gain control voltage (V)
36
1.8
2.0
2.2
2.4
2.6
2.8
3.0
26.1.01
Preliminary Specification
TUA6100B6
13.5 RF input impedance
18.5
18.0
Input resistance (Ohm)
17.5
17.0
16.5
16.0
15.5
800meg
1g
1.2g
1.4g
1.6g
1.8g
2g
2.2g
2.4g
2.6g
2.8g
3g
2g
2.2g
2.4g
2.6g
2.8g
3g
f(Hz)
1.37n
1.36n
1.35n
Input Inductance (H)
1.34n
1.33n
1.32n
1.31n
1.3n
1.29n
800meg
1g
1.2g
1.4g
1.6g
1.8g
f(Hz)
High-Frequency-Products
37
26.1.01
Preliminary Specification
TUA6100B6
50
10
25
0
30
75
35
40
45
• RF input impedance continued, Smith diagram
20
15
0
15
3 GHz
200
250
2 GHz
10
1 GHz
500
1k
5
1k
500
250
200
150
100
75
40
45
50
35
30
25
20
15
5
0
10
800 MHz
1k
5
500
10
250
200
15
15
0
50
45
40
35
75
30
10
25
0
20
13.6 Base band output impedance pin 13, 14 (filtered), Smith diagram
identical to pin 19, 20
45
40
80
50
90
100
70
60
10
25
50
20
14
0
40
0
13
0
30
120
75
35
110
15
150
15
30
200
250
20
10
160
0
500
10
170
100 M
30 M
5
1k
500
250
200
150
100
75
40
45
50
35
30
25
20
15
10
5
0
180
1k
0
1M
200
-30
0
-15
250
-160
500
-170
1k
-20
10
-10
5
15
0
10
25
-90
40
50
-80
45
-70
35
75
30
-1
-60
38
0
-100
-12
-1
0
30
0
-110
High-Frequency-Products
-5
40
0
15
-4
20
26.1.01
Preliminary Specification
TUA6100B6
13.7 Base band output impedance pin 19, 20 , Smith diagram
45
40
80
50
90
100
70
60
10
25
20
14
50
40
0
1
30
0
30
120
75
35
110
15
150
15
30
200
250
20
10
160
0
500
10
170
100 M
30 M
5
1k
500
250
200
150
100
75
40
45
50
35
30
25
20
15
10
5
0
180
1k
0
1M
200
15
0
20
10
-1
75
-90
40
50
-80
45
-70
35
-60
30
30
0
25
-5
0
0
-1
-4
40
15
0
-15
250
-160
500
-170
1k
-30
-100
-
120
-110
•
-20
10
-10
5
Base band output impedance Pin 19, 20 (Ohm)
12.0
11.0
10.0
9.0
8.0
Ohm
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
100.0k
200.0k
300.0k
High-Frequency-Products
600.0k
1meg
2meg
3meg
f(Hz)
39
6meg
10meg
20meg
30meg
60meg
100meg
26.1.01
Preliminary Specification
•
TUA6100B6
Base band output inductance Pin 19, 20 (Henry)
35n
Henry
30n
25n
20n
15n
100.0k
200.0k
300.0k
600.0k
1meg
2meg
3meg
f(Hz)
6meg
10meg
20meg
30meg
60meg
100meg
50
45
10
25
0
30
75
35
40
13.8 Base band Input Impedance (filtered)
20
15
0
15
200
250
10
500
5
0 MHz
1k
500
250
200
150
100
75
40
45
50
35
30
25
20
15
5
10
1k
0
100 MHz
1k
5
500
10
250
200
15
15
0
High-Frequency-Products
45
50
40
35
75
30
25
0
10
20
40
26.1.01
Preliminary Specification
TUA6100B6
14 Package Outlines
Plastic Package, P-TSSOP-28-1 alloy leadframe
(Plastic Thin Shrink Small Outline)
0.9
Plastic Package, P-TSSOP-28-5 copper leadframe
(Plastic Thin Shrink Small Outline)
High-Frequency-Products
41
26.1.01