INFINEON TUA4401K

Wireless Components
FM Car Radio IC with PLL
TUA 4401K V 2.1
Specification 17.02.00
DS 1
Revision History: Current Version: 02.00
Previous Version:Data Sheet 23.09.1999
Page
(in previous
Version)
Page
(in current
Version)
Subjects (major changes since last revision)
3-7
3-7
Functional description pin 41 corrected
3-11
3-11
Functional description pin 41 corrected
5-3
5-3
Sequence tests 310 to 317 changed (Item)
5-5
5-5
Values attack current changed
5-5
5-5
Values recovery current changed
5-5
5-5
Values detector characteristic changed
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Edition 03.99
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TUA 4401K
Productinfo
Productinfo
General Description
Features
Package
The TUA 4401K is the first Infineon
Carradio IC using BICMOS technology.
The combination of an analog FM
receiver circuit and a digital PLL synthesizer on the same chip reduces the
over all pin count in comparison to two
separate IC’s and in addition the
number of necessary external components. This gives the flexibility both for
high performance and low cost applications.
The recommended applications for this
device are FM only carradios and background receivers, capable for all world
standards.
Double balanced RF mixer with low CMOS PLL-Synthesizer
noise figure, high IP3 and wide
Resolution between 100 kHz and
dynamic range
6.25kHz
Strictly symmetrical RF circuitry
Search tuning stop with IF counter
IF amplifier with adjustable gain
Double frequency 1st LO option
7 stage limiter amplifier with dB
linear fieldstrength output
Low distortion coincidence
and Fieldstrength/Multipath
evaluation
ADC’s for fieldstr. and multipath
detector
I2C Bus operation
demodulator
Multipath detector with analog
output
Applications
FM only car radio receiver, background receiver
Ordering Information
Type
Ordering Code
TUA 4401K
Wireless Components
Package
MQFP-44
Product Info
Specification, 17.02.00
1
Table of Contents
1 Table of Contents
1-1
2 Product Description
2-1
2.1
General Description
2-2
2.2
Applications
2-3
2.3
Features
2-3
2.4
Package Outlines
2-4
3 Functional Description
3-1
3.1
Pin Configuration
3-2
3.2
Block Diagram
3-12
3.3
Functional Block Diagram
3-13
3.4
Circuit Description
3-14
4 Applications
4.1
Application and Circuits
5 Reference
4-1
4-2
5-1
5.1
5.1.1
5.1.2
5.1.3
Electrical Data
Absolute Maximum Range
Operating Range
AC/DC Characteristics
5-2
5-2
5-2
5-3
5.2
Phase detector outputs
5-7
5.3
Bus Interface
5-8
5.4
I2C Bus Timing
5-13
2
Product Description
Contents of this Chapter
2.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
TUA 4401K
Product Description
2.1 General Description
The TUA 4401K is the first Infineon Carradio IC using BICMOS technology.
The combination of an analog FM receiver circuit and a digital PLL synthesizer
on the same chip reduces the over all pin count in comparison to two separate
IC’s and in addition the number of necessary external components. This gives
the flexibility both for high performance and low cost applications.
The recommended applications for this device are FM only carradios and background receivers, capable for all world standards.
TUA 4401K features:
Frontend
High level, high impedance mixer input with improved dynamic range
High input / output 3rd order intercept point
Integrated prestage AGC generation and control for PIN diodes and MOS
tetrode
Bus controlled AGC threshold
2 pin 1st local oscillator with improved low phase noise, internally coupled to
PLL. Double frequency operation possible
Strictly symmetrical RF parts
PLL with fast acquisition mode
Resolution 100 kHz, 50 kHz, 25 kHz, 12,5 kHz, 10 kHz and 6.25 kHz
High running (61.5 MHz) crystal oscillator to avoid interference with bus
controlled adjustment
IF amplification, demodulation and STS
Low noise IF amplifier
Gain adjust with DC control voltage or serial bus possible
7 stage IF limiter with extended fieldstrength range suitable for the IF frequency range of 10.7 MHz ... 21.4 MHz
Fieldstrength DC output and ADC output available
Low distortion coincidence demodulator (using short loop AFC principle)
with MPX output
Wideband multipath detector with analog output and ADC output
IF counter for search tuning stop with selectable IF center frequency,
window width and programmable thresholds for fieldstrength and multipath
evaluation
STS informations -in window-,-below-,-beyond- available
Wireless Components
2-2
Specification, 17.02.00
TUA 4401K
Product Description
I2C Bus
I2C bus (2 wire, fast mode device with 400 kbit/s) operation possible
Bus interface with low threshold voltage Schmitt Trigger inputs for interfacing 3V or 5V microprocessors
2.2 Applications
FM only car radio receiver, background receiver
2.3 Features
Double balanced RF mixer with low noise figure, high IP3 and wide dynamic
range
Strictly symmetrical RF circuitry
Double frequency 1st LO option
IF amplifier with adjustable gain
7 stage limiter amplifier with dB linear fieldstrength output
Low distortion coincidence demodulator
Multipath detector with analog output
CMOS PLL-Synthesizer
Resolution between 100 kHz and 6.25kHz
Search tuning stop with IF counter and
Fieldstrength/Multipath evaluation
ADC’s for fieldstr. and multipath detector
I2C Bus operation
Wireless Components
2-3
Specification, 17.02.00
TUA 4401K
Product Description
2.4 Package Outlines
MQFP 44
Wireless Components
2-4
Specification, 17.02.00
3
Functional Description
Contents of this Chapter
3.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.3
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.4
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
TUA 4401K
Functional Description
VCCIF
IFAMPC
IFOUTFM
IFIN
IFINFM
GNDIF1
VREFRF
IF1
IF2
AGCOUT_P
FM2
3.1 Pin Configuration
33
32
31
30
29
28
27
26
25
24
23
F M IF IN
34
22
FM 1
F M IB IAS
35
21
PR E _C A P
G N D IF 2
36
20
VC C R F
M PXOUT
37
19
OSC2
FSOUT
38
18
OSC1
M P A_ IN
39
17
GNDRF
M P AC AP
40
16
PD _ 0
M P A _O U T
41
15
PD A
D E M AF C
42
14
PO R T _ 1
PH02
43
13
GNDD
PH01
44
12
VC C D
1
2
3
4
5
6
7
8
9
10
11
FS_ADC
MPA_ADC
Station_Detect
SCL
SDA
VREFD5V
VREFD3V
XTAL_DIV6
PORT_2
QUARTZ1
QUARTZ2
M Q F P 44
Pin_config.wmf
Figure 3-1
IC Pin Configuration
Table 3-1 Pin Configuration
Pin No.
Symbol
Equivalent I/O-Schematic
Function
+5V
1
1
1:
ADC input fieldstrength
FS_ADC
+5V
5 pF
2
MPA_ADC
2
2:
ADC input multipath
detector
GNDD
Wireless Components
3-2
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued)
Pin No.
Symbol
Equivalent I/O-Schematic
Function
+ 5V
3
3:
IF counter output station
detector
3
Station_Detect
GNDD
+ 5V
4
4
SCL
4:
I2C bus clock input
330
+5V
GNDD
+ 5V
5
5
330
5:
I2C bus data in/output
SDA
GNDD
6
VREFD5V
6:
Reference voltage digital
section (5V)
7
VREFD3V
7:
Reference voltage digital
section (3V)
V+ 3V
8
XTAL_DIV6
8
2k
8:
Crystal oscillator auxiliary output (10.25 MHz)
2 0 0 fF
GNDD
Wireless Components
3-3
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued)
Pin No.
Symbol
Equivalent I/O-Schematic
Function
+5V
9
9:
Switch port output 2(open
drain)
9
330
PORT_2
GNDD
+V
10:
Reference oscillator input
/ Crystal
10
QUARTZ1
2,5 k
10
11
12
VCCD
13
GNDD
14
PORT_1
11:
Reference oscillator input
/ Crystal
5k
QUARTZ2
5k
11
12:
Positive power supply
voltage for serial bus and
synthesizer
13:
Ground for serial bus and
synthesizer
+5V
14
330
14:
Switch port output 1
(open drain)
GNDD
Wireless Components
3-4
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued)
Pin No.
Symbol
Equivalent I/O-Schematic
Function
VCCD
IPDA
+5 V
15:
PLL phasedetector output
analog (Tuningvoltage)
15
12
PDA
3k
15
GNDD
PD
+5 V
PD
16
+5 V
16:
PLL chargepump output
(Phase detector tristate
chargepump output)
PD_0
+5 V
17
16
GNDRF
Wireless Components
NC
17:
Ground for RF part
3-5
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued)
Pin No.
Symbol
Equivalent I/O-Schematic
+V
18
OSC1
19
OSC2
Function
+V
18
19
18:
1st local oscillator circuit
19:
1st local oscillator circuit
2 ,2 V
20
VCCRF
20:
Positive power supply
voltage for RF part
+V
21:
Prestage AGC time constant capacitor; output for
MOS tetrode gate 2
21
21
PRE_CAP
6 ,4 V
Wireless Components
3-6
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued)
Pin No.
22
Symbol
Equivalent I/O-Schematic
FM1
25
Function
26
+V
22:
FM 1st mixer symmetrical
input
22
23:
FM 1st mixer symmetrical
input
23
2,0k
FM2
2,0k
23
2 ,6 V
24
24
+V
24:
Prestage AGC current
output for PIN diode normal polarity
AGCOUT_P
Wireless Components
3-7
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued)
Pin No.
Symbol
Equivalent I/O-Schematic
25
25
IF2
Function
26
25:
1st mixer output (open
collector)
+V
22
26:
1st mixer output (open
collector)
23
2,0k
IF1
2,0k
26
2 ,6 V
27
VREFRF
27:
Reference voltage RF
section (4.8V)
28
GNDIF1
28:
Ground for IF amplifier
+V
IFINFM
29:
10.7 MHz IF amplifier
input
30
330
29
IFIN
17k
30
17k
29
30:
10.7 MHz IF amplifier
operation point
3 ,8 V
Wireless Components
3-8
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued)
Pin No.
Symbol
Equivalent I/O-Schematic
Function
330
+V
31
31
31:
10.7 MHz IF amplifier output
IFOUTFM
+V
IFAMPC
33
VCCIF
32:
10.7 MHz IF amplifier DC
gain control adjust blocking capacitor
32
8k
32
33:
Positive power supply
voltage for IF amplifier
+V
35
FMIFIN
34:
FM limiter input
330
34
35
FMIFBIAS
5 ,5 V
36
GNDIF2
Wireless Components
33k
33k
34
35:
FM limiter input bias
decoupling capacitor
36:
Ground for limiter amplifier
3-9
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued)
Pin No.
Symbol
Equivalent I/O-Schematic
Function
+V
37
37
MPXOUT
37:
FM MPX signal output
+V
NC
+V
38:
Fieldstrength output
FSOUT
34k
66k
38
38
+V
86k
39
MPA_IN
Wireless Components
39
39:
Multipath detector input
3 - 10
Specification, 17.02.00
TUA 4401K
Functional Description
Table 3-1 Pin Configuration (continued)
Symbol
Equivalent I/O-Schematic
40
Pin No.
40
MPACAP
41
MPA_OUT
Function
+V
40:
Multipath detector rectifier
capacitor
41:
Multipath detector output
+V
41
+V
42
DEMAFC
42:
Demodulator AFC blocking capacitor
42
76k
3 ,5 V
+V
43
PH02
43:
Demodulator circuit
15p
15k
44
4 3 /4 4
44:
Demodulator circuit
PH01
4 ,8 V
Wireless Components
3 - 11
Specification, 17.02.00
TUA 4401K
Functional Description
F M IF IN
34
F M IF B IA S
VCCIF
IFAMPC
IFOUTFM
IFIN
IFINFM
GNDIF1
VREFRF
IF1
IF2
AGC_OUT_P
FM2
3.2 Block Diagram
33
32
31
30
29
28
27
26
25
24
23
22
FM 1
35
21
PRE_CAP
G N D IF 2
36
20
VCCRF
M PXOUT
37
19
OSC2
FSOUT
38
18
OSC1
M P A _ A IN
39
17
GNDRF
M PACAP
40
16
PD_0
M PA_O UT
41
15
PDA
DEM AFC
42
14
PO RT_1
PH02
43
13
GNDD
PH01
44
C ryst
O SC 1 2
10
11
VCCD
IF A M P
V re f
F M L im / D e m /
F S / M P -D e t
M ixe r 1 st L O
P re se t A G C
3
4
5
6
7
8
9
MPA_ADC
Station_Detect
SCL
SDA
VREFD5V
VREFD3V
XTAL_DIV6
PORT_2
QUARTZ2
2
QUARTZ1
1
FS_ADC
P L L S yn th .
S e ria l B u s
IF co u n te r
A D C /D A C
Funct_block.wmf
Figure 3-2
Main Block Diagram
Wireless Components
3 - 12
Specification, 17.02.00
MOS
tetrode
VCC RF
17
27
19
18
20
23
22
24
VREF
RF
1. LO
OSC
Div 2
OSC
Buffer /
FM
AGC
prest
26
25
5
4
SOCCAR
Bus
N counter
15
Charge
pump
16
PD
or Amp
Data Bus
10.7 MHz
CER Filter
2 bit DAC
Prest. AGC thresh.
SCL
Pin Diode 1
External
SDA
FM
14
29
9
Port
R counter
4 bit DAC
IF gain
10.7 MHz
CER Filter
P1
21
P2
3 - 13
30
10
32
11
adj crystal
IF amp
gain adj.
28
VRef
IF
31
8
12
div/6
10.7 MHz 35
CER Filter
VCCD
Figure 3-3
34
VCC IF
6
33
7
Clock
counter
Gate
time
counter
Field
strength
FM IF
limiter
36
44
3
IF
counter
AfC
loop
Dem
43
Station_Detect
Wireless Components
Gate2
42
MPX out
13
7 Bit ADC
37
MP det in
MP
det.
39
2
1
38
41
40
Fieldstrength
MP det out
TUA 4401K
Functional Description
3.3 Functional Block Diagram
Funct_block.wmf
Functional Block Diagram
Specification, 17.02.00
TUA 4401K
Functional Description
3.4 Circuit Description
The TUA 4401K is a one chip FM car radio system consisting of RF frontend,
gain adjustable IF amplifier, FM-IF limiter amplifier, demodulator, PLL synthesizer, IF counter for STS and ADC’s for fieldstrength and multipath detector.
The serial bus is a I2C type.
1. FM frontend
The frontend consists of a two pin varactor tuned oscillator, a double balanced mixer and a prestage AGC control circuit. The mixer has an improved
intermodulation behaviour and converts the RF signal to the 10,7 MHz IF
range . Two inputs allow both symmetrical and unsymmetrical operation.
The integrated AGC stage for prestage control drives MOSFETS as well as
PIN diodes a with cur- rent driver. The AGC threshold can be set with a serial
bus controlled 2 Bit DAC. For background receiver application the oscillator
is able run at double frequency, a subsequent frequency divider by 2 is activated by serial bus to provide the correct mixer frequency.
2. FM IF amplifier
After the mixer an IF amplifier is present for IF post amplification. Input and
output impedance are both 330 Ohms for matching with ceramic filters. For
adjusting the over all gain the IF amplifier gain can be adjusted with a serial
bus controlled 4 Bit DAC.
3. FM limiter and demodulator
The FM IF amplifier includes a seven stage capacitive coupled limiter amplifier and a fieldstrength generator with high linearity and increased dynamic
range. The coincidence demodulator has an additional AFC short loop circuit with integrated varactor diode in parallel to the external tank circuit to
improve the distortion bahaviour in case of detuning.
4. Multipath detector
A wideband multipath detector with analog output is available.
5. A/D converter for fieldstrength and multipath detector
The 7 bit A/D converter has two input channels and works as successive
approximation converter. The conversion time for both input signals is t = 32
µs. The 7-bit digital-words from both channels (14 bit) are read out together
via bus into two bytes with the read subaddress 82H. The input voltage
range for both channels is 0...VREFD5V.
6. IF counter and multipath/fieldstrength evaluation for STS
FM center frequencies ar available in two ranges set by bit D7 in subaddress
05H. For D7=1 the range of centerfrequency is 20.800 MHz...22.3875 MHz
in 128 steps (12.5 kHz per step). For D7=0 the range of centerfrequency is
10.400 MHz...11.1937 MHz in 128 steps (6.25 kHz per step).
The gate time is adjustable in 8 steps from 320us...40.96ms and the tolerance of the accepted count value, the window is adjustable in 5 steps from
+/- (6.25kHz...100kHz) for D7=0 in sub-address 05H and
Wireless Components
3 - 14
Specification, 17.02.00
TUA 4401K
Functional Description
+/- (12.5 kHz...200 kHz) for D7=1 in subaddress 05H. The results IF_CENT
and IF_WINDOW are read out via bus (read-subaddress 82H&83H) or pin
Station_Detect.
If the IF frequency is into the preselected window, Station_Detect goes from
high to low level. If the IF frequency is outside the preselected window,
Station_Detect is high. The bit IF_WINDOW is a hint IF-frequency that is to
low (IF_WINDOW=high) or is to high (IF_WINDOW=low).
In addition to the frequency measurement, thresholds for multipath and fieldstrength voltages can be programmed via bus (subaddress 0BH).
Station_Detect will only go to low level in case of field-strength and multipath
voltages are beyond the thresholds and the frequency is inside the window.
When setting the thresholds to zero multipath and fieldstrength evaluation is
disabled.
7. Crystal oscillator
A master crystal oscillator provides all necessary clock frequencies for the
whole IC. A 61.5 MHz crystal is used in 3rd harmonic mode.
The oscillator frequency can fine tuned with a serial bus controlled 4 bit D/A
converter.
The crystal frequency is used as reference frequency for the PLL oscillator
and IF counter. It is also used as clock for the ADC’s. Finally the crystal frequency divided by 6 (10.25 MHz) is available at a pin as low pass filtered
voltage, it can be disabled with the serial bus.
8. Output ports
PORT_1 / 2 are NMOS Open drain outputs.
9. I2C Bus
The TUA4401K supports the I2C bus protocol (2 wire). All bus pins ( SCL,
SDA) are Schmitt triggered input buffer for 3V or 5V µC.
The bit stream begins with the most significant bit (MSB), is shifted in (write
mode) on the low to high transition of CLK and is shifted out (read mode) on
the high to low transition of CLK
I2C bus mode:
Data Transition:
Data transition on the pin SDA must only occur when the clock SCL is low.
SDA transitions while SCL is high will be interpreted as start or stop condition.
Start Condition (STA):
A start condition is defined by a high to low transition of the SDA line while
SCL is at a stable high level.This start condition must precede any command
and initiate a data transfer onto the bus.
Stop Condition (STO):
A stop condition is defined by a low to high transition of the SDA while the
SCL line is at a stable high level. This condition terminate the communication
between the devices and forces the bus interface into the initial conditions.
Wireless Components
3 - 15
Specification, 17.02.00
TUA 4401K
Functional Description
Acknowledge (ACK):
Indicates a successful data transfer. The transmitter will release the bus
after sending 8 bit of data. During the 9th clock cycle the receiver will pull the
SDA line to low level to indicate it has receive the 8 bits of data correctly.
Data Transfer Write Mode:
To start the communication, the bus master must initiate a start condition,
followed by the 8bit chip address (write). The chip address for the TUA 4401
is fixed as ”1100110” (MSB at first). The last bit (LSB=A0) of the chip
address byte defines the type of operation to be performed:
A0=1, a read operation is selected and A0=0, a write operation is selected.
After this comparison the TUA 4401 will generate an ACK.
After this device addressing the desired subaddress byte and data bytes
must be followed. The subaddresses determines which one of the 9 data
bytes (00H...07H, 0BH) is transmitted first. At the end of data transition the
master must be generate the stop condition.
Data Transfer Read Mode:
To start the communication in the read mode, the bus master must initiate a
start condition, followed by the 8bit chip address (write: A0=0), followed by
the sub address read (82H/83H), followed by the chip address (read: A0=1).
After that procedure the 16bit/8bit data register 82H/83H is read out. After
the first 8 bit read out, the uP mandatory send LOW during the ACK-clock.
After the second 8 bit read out the uP mandatory send HIGH during the
ACK-clock. At the end of data transition the master must be generate the
stop condition.
10.PLL Synthesizer
R / N Counter
The TUA 4401K has 2 identical 16bit counter for R and N path. Input frequency for the R-counter is the buffered XTAL-frequency (61.5MHz). Tuning
steps can be selected by the 16bit R-counter from fR= 6.25kHz...100kHz.
Input frequency for the N-counter is the buffered LO-frequency (in FM mode
98.2MHz...118.7MHz).
Three State Phase Comparator
The phase comparator generates a phase error signal according to phase
difference between fR (R counter output) and fN (N counter output).This
phase error signal drives the charge pump current generator.
Charge Pump
The charge pump generates signed pulses of current. 4 current values are
available.
Loop Amp
The integrated rail to rail loop amplifier allows an active loop filter design with
external components.
Two modes are available with status bit D11: high speed and normal mode.
Wireless Components
3 - 16
Specification, 17.02.00
4
Applications
Contents of this Chapter
4.1
Application and Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
3,3k
68p
43
TOKO 600BNS-A1004HM
44
2
MPA_ADC
1uF
3
MPD-out
41
4
42
SCL
DemAFC
IF-CENT
1k
1
5
10n
40
MDP-Cap
SDA
47n
200kHz
38
8
37
MPX-out
Xtal/6
10k
9
3,3k
36
Port2
N-counter
audio measure system
Fieldstrength
MDP-in
39
7
Vref3V
6
10k
Vref5V
51
FS_ADC
100
33n
22n
35
FMIFbias
10
12
VccD
22n
34
FMIFin
RF-source 10.7MHz
22n
33
VccIF
13
32
IFampC
22n
TUA4401K
11
51
33n
1k
22n
14
+
31
IFout_FM
Port1
R-counter
3,3k
-
22n
RF-measure 10.7MHz
1k
61.5MHz
100
+
100uH
-
330
time measurement
15
150p
16
PD_0
29
IFinFM
6,8n
1k
RF-source 10.7MHz
22n
30
IFin
PD
1k
33k
51
time measurement
22n
1n
28
17
33n
1n
1k
4,7k
27
VrefRF
1n
26
MIX1
19
22k
1uH
23
RF-measure 10.7MHz
-
51
RF-source 110.7MHz
FM2
24
25
AGCout_p
22
MIX2
1n
1n
FM1
21
10n
PreCap
20
22n
100
VccRF
TOKO 218FCS-2166N
local oscill
18
1n
BB914
10n
RF-source
BAR63
time measurement
4,7k
1k
22k
100
4-2
+
I2C-Bus
10
10uH
1k
Wireless Components
330
Figure 4-1
10n
ramp
TUA 4401K
Applications
4.1 Application and Circuits
FM only car radio receiver, background receiver
4401K_Test_circ.wmf
Test Circuit
Specification, 17.02.00
TUA 4401K
Applications
4401K_SPEC.eps
Figure 4-2
Wireless Components
Application Circuit
4-3
Specification, 17.02.00
5
Reference
Contents of this Chapter
5.1
5.1.1
5.1.2
5.1.3
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Absolute Maximum Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.2
Phase detector outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.3
Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.4
I2C Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
TUA 4401K
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Range
The maximal ratings may not be exceeded under any circumstances, not even
momentary and individual, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Range
Parameter
Symbol
Limit Values
min
max
Unit
ESD-Protection all bipolar pins
HBM ( R=1.5kΩ , C=100pF )
VESD
-1
1
kV
ESD-Protection all CMOS pins
HBM ( R=1.5kΩ , C=100pF )
VESD
-1
1
kV
900
mW
85
°C
150
°C
125
°C
65
K/W
Total power dissipation
Ptot
Ambient temperature
TA
Junction temperature
Tj
Storage temperature
Tstg
Thermal resistance P-MQFP-44 (sys-air)
TthSA
- 40
- 40
All values are referred to ground (pin), unless stated otherwise.
All currents are designated according to the source and sink principle, i.e. if the device
pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it
has a negative sign, and if it is a source (the current flows from Vs across the designated
pin), it has a positive sign.
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit
description.
The AC / DC characteristic limits are not guaranteed.
Table 5-2 Operating Ratings
Parameter
Supply voltage
Symbol
VVCC
Current consumption
Ivcc
Ambient temperature
TA
Wireless Components
Limit Values
Unit
min
max
8
9
V
111
mA
85
°C
- 40
5-2
Test Conditions
L
Item
Specification, 17.02.00
TUA 4401K
Reference
5.1.3
AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified
supply voltage and ambient temperature range. Typical characteristics are the
median of the production.
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 8.5 V
Symbol
Limit Values
min
Unit
typ
max
85
111
mA
Test Conditions
L
Item
Power Supply
Total current consumption
IVCC
1st local oscillator
Frequency range
f1st LO
50
250
MHz
Frequency range
f1st LO
50
150
MHz
Q factor of coil > 90
Frequency range
f1st LO
160
250
MHz
coil tbf; see
SUB06h
Negative input impedance
Z18-19
Ω
f = 100 MHz
- 1000
L
RF mixer
Imix
11
Input frequency
f22-23
60
Max input RF level
V22-23
120
Input impedance
single ended
R22-23
1.8
kΩ
L
C22-23
2.5
pF
L
Mixer current
Mixer gain
Amix
12
Input IP3
Noise Figure
Reference voltage RF section
F
14
17
mA
140
MHz
101
dBµV
15
18
dB
126
dBµV
6
dB
259
IM = 60 dB
L
L
V27
4.3
4.8
5.3
V
104
AGC threshold range
V22-23
48
60
72
mV
see diagram
SUB06h
310
311
AGC threshold range
V22-23
36
45
54
mV
see diagram
SUB06h
312
313
AGC threshold range
V22-23
24
30
36
mV
see diagram
SUB06h
314
315
AGC threshold range
V22-23
10
15
20
mV
see diagram
SUB06h
316
317
AGC voltage for MOSFET
Gate 2
V21
5.7
6.4
V
V22-23 = 0 mV
106
AGC voltage for MOSFET
Gate 2
V21
V
V22-23 = 200 mV
300
AGC current normal polarity
I24
mA
V22-23 = 0 mV
115
Prestage AGC outputs
Wireless Components
0.1
10
13
5-3
Specification, 17.02.00
TUA 4401K
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 8.5 V (continued)
Symbol
Limit Values
min
typ
Unit
Test Conditions
L
Item
max
AGC current normal polarity
I24
0.1
mA
V22-23 = 200 mV
301
Integrator current
I21
-75
-50
-25
µA
V22-23 = 0 mV;
Vm = 3V
117
Integrator current
I21
25
50
75
µA
V22-23 = 200 mV;
Vm = 3V
303
DC input voltage
V29
3.4
3.7
4.0
V
Input resistance
R29
330
Ω
L
Output resistance
R31
330
Ω
L
Max. Voltage gain
A31-29
23
26
29
dB
see
diagram SUB07h
403
Min. Voltage gain
A31-29
10
13
16
dB
see
diagram SUB07h
405
dB
RG = 330 Ω
µVrm
fin = 10.7 MHz;
V37 - 3 dB
IF amplifier
Noise figure
F
7
108
IF limiter amplifier / fieldstrength generator
Input voltage for limiter
threshold
V34
AM suppression
AAM
Fieldstrength voltage
V38
Fieldstrength voltage
V38
Fieldstrength voltage
Fieldstrength voltage
25
45
s
70
80
dB
m = 30 %,
V34=100mV
469
0.4
0.8
V
V34 = 0 mVrms
450
1.5
1.9
2.3
V
V34 = 1 mVrms
451
V38
2.4
2.9
3.4
V
V34 = 10 mVrms
452
V38
3.6
4.2
4.8
V
V34 = 200 mVrms
471
∆F = 75 kHz;
fIF=10.7 MHz
455
Fieldstrength dynamic range
V38dyn
90
dB
Fieldstrength linearity
V38lin
±1
dB
Fieldstrength temperature
drift
470
V38temp
±3
dB
720
mVrm
FM demodulator
AF output voltage
V37
500
600
s
AF output voltage
V37
Total harmonic distortion
THD37
Total harmonic distortion
detuned
THD37
Wireless Components
s
∆F = 75 kHz;
fIF= 21.4 MHz
0.6
%
∆F = 75 kHz
456
0.8
%
fin = 10.7 MHz
± 50 kHz;
∆F = 75 kHz
457
300
0.3
5-4
mVrm
L
Specification, 17.02.00
TUA 4401K
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 8.5 V (continued)
Symbol
Limit Values
Unit
min
typ
max
Test Conditions
L
Item
Multipath detector
Attack current
I40*)
700
900
1200
µA
V39 = 350 mVrms;
Vm = 5 V
801
Recovery current
I40*)
-8
-13
-18
µA
V39= 0 Vrms;
Vm = 3.6 V
802
V
V39 = 0 Vrms
114
V
f39 = 200 kHz
V39 = 40 mVrms
800
Start voltage
Detector characteristic
V41Def
V41
4.7
V41Def
-3.1 V
V41Def
-2.8 V
V41Def
-2.5 V
*) Detector currents are measured between the output pin (-pole) and a voltage source Vm
Crystal oscillator
Operating frequency
f10-11
61.5
MHz
3rd harmonic
Negative input impedance
Z10-11
- 250
Ω
f = 61.5 MHz
Negative input impedance
Z10-11
1.4
kΩ
f = 20.5 MHz
Input impedance crystal
Rcr
70
Ω
3rd harmonic
Spurious harmonics crystal
asp
- 20
dB
f < 200 MHz
Bus controlled adjust range
∆fadj
± 40
ppm
see diagram
SUB06h
Bus controlled output
XTAL_DIV6
VXTAL_DIV6
on AC
500
mVpp
f = 10.25 MHz,
Cload = 10 pF
Bus controlled output
XTAL_DIV6
VXTAL_DIV6
on DC
2.0
VDC
f = 10.25 MHz,
Cload = 10 pF
180
Bus controlled output
XTAL_DIV6
VXTAL_DIV6
off DC
50
mVDC
Cload = 10 pF
197
1.0
1.5
Chargepump output (Loopfilter input)
DC voltage
VPD_0
2.3
2.5
2.7
V
locked
251
252
DC current
± IPD_03
3.2
4
5.2
mA
220
DC current
± IPD_02
1.6
2
2.6
mA
DC current
± IPD_01
0.8
1
1.3
mA
see Status,
Subaddress 00H,
bit D1, D2
VPD_0 = 2.5V
DC current
± IPD_00
400
500
700
uA
0.1
10
nA
VPD_0 = 2.5V ,
guaranteed by
design
228
Tristate output current
to
227
± IPD_0OFF
Loop amplifier tuningvoltage output (Loopfilter output)
LOW output voltage
VPDA_L
0
400
mV
ITUNE = 100 uA
231
HIGH output voltage
VPDA_H
VVCC
-0.5V
VCC
mV
ITUNE = -100 uA
230
Wireless Components
5-5
Specification, 17.02.00
TUA 4401K
Reference
Table 5-3 AC/DC Characteristics with TA 25 °C, VVCC = 8.5 V (continued)
Symbol
Limit Values
Unit
min
typ
max
HIGH output current source
IPDA_H
-1.9
-2.4
-2.9
mA
LOW output current source
IPDA_L
-0.9
-1.2
-1.5
mA
Test Conditions
L
VTUNE = 4V,
VPD_0 = 0V
(see Status,
Subaddress 00H,
bit D11)
Item
232
233
PLL for synthesizer (see PLL Synthesizer on page 3-16)
PLL / VCO step size
(programmable via Rcounter)
fref
6.25
100
kHz
f crystal = 61.5 MHz
N-counter divide ratio
N
2
65535
16-Bit
200
to
207
R-counter divide ratio
R
2
65535
16-Bit
210
to
216
Port outputs, PORT_1, PORT_2, IF_CENT, IF_WINDOW (see Output ports on page 3-15)
LOW output voltage
HIGH Leakage current
VP
0
IP_LEACK
0
100
400
mV
IP = 1 mA
*1)
100
nA
VP = 5 V
*2)
*1) 830, 840, 831, 834
*2) 118, 119, 124, 125
I2C bus (SCL, SDA) (see I2C Bus Timing on page 5-12 and Bus Data Format on page 3-15)
H-input voltage
VIH
2.10
5.50
V
150
L-input voltage
VIL
-0.5
0.90
V
150
Hysteresis of Schmitt trigger
inputs (SCL, SDA)
Vhys
0.30
Input capacity
I2C bus leakage current
V
CI
I_LEACK
0
5
pF
1
µA
Values only valid for
applied VCC
L
Ref voltages
Ref voltage
V6
4.5
5.0
5.5
V
102
Ref voltage
V7
2.7
3.0
3.3
V
103
Wireless Components
5-6
Specification, 17.02.00
TUA 4401K
Reference
5.2 Phase detector outputs
fr
fn
PD_O
Polarity
pos.
P-Channel
Tri-State.
N-Channel
Frequency fn < fr
or fV lagging
Wireless Components
Frequency fn > fr
or fV leading
5-7
Frequency fn = fr
Specification, 17.02.00
TUA 4401K
Reference
5.3 Bus Interface
1. Bus Interface
I2C Bus
2. Bus Data Format
I2C Bus Write Mode
STA
MSB
CHIP ADDRESS (WRITE)
1
1
0
0
1
1
LSB
0
0
ACK
MSB
SUB ADDRESS (WRITE)
00H...07H, 0BH
S7
S6
S5
S4
S3
LSB
S2
S1
S0
ACK
MSB
DATA IN X...0 (X=7 or 15)
DX
...
D5
MSB
CHIP ADDRESS (READ)
1
1
D4
D3
D2
LSB
D1
D0
ACK
STO
2
I C Bus Read Mode
STA
MSB
CHIP ADDRESS (WRITE)
1
1
0
0
1
1
LSB
0
0
ACK
MSB
SUB ADDRESS (READ) 82H/83H
LSB
1
0
0
0
0
0
0
MSB
DATA OUT FROM SUB ADD 82H
LSB
R15
R14
R8
R13
R12
R11
R10
R9
1
ACK1)
ACK
STA
0
0
1
MSB
DATA OUT FROM SUB ADD 82H/83H
LSB
R7
R6
R0
R5
R4
R3
R2
R1
LSB
1
ACK2)
0
1
STO
1): mandatory LOW send by uP, 2): mandatory HiGH send by uP
Chipaddress Organisation
Chip Address
MSB
LSB
Function
1
1
0
0
1
1
0
0
Chip Address Write
1
1
0
0
1
1
0
1
Chip Address Read
Subaddress Organisation
Sub Addresses of Data Registers Write
LSB
Hex
Function
0
MSB Bin
0
0
0
0
0
0
0
00H
Status
0
0
0
0
0
0
0
1
01H
R_Counter
0
0
0
0
0
0
1
0
02H
N_Counter
0
0
0
0
0
0
1
1
03H
Mute_DAC7
0
0
0
0
0
1
0
0
04H
IF_COUNT_P1
0
0
0
0
0
1
0
1
05H
IF_COUNT_P2
0
0
0
0
0
1
1
0
06H
Specials
0
0
0
0
0
1
1
1
07H
Gain_DAC4
0
0
0
0
1
0
1
1
0BH
COMP-PRESET
LSB
Hex
Function
Sub Address of Data Register Read
MSB Bin
Wireless Components
1
0
0
0
0
0
1
0
82H
Result Multipath,
Fieldstrength,
IF_Window and
IF_Center
1
0
0
0
0
0
1
1
83H
Result-MISC
5-8
Specification, 17.02.00
ACK
TUA 4401K
Reference
Data Byte Specification
Status
Subaddress 00H
Bit
R_Counter
Subaddress 01H
Results Fieldstrength, Multipath
and IF counter
Subaddress 82H (read address)
N_Counter
Subaddress 02H
Function
Bit
Function
Bit
Function
Bit
Function
MSB
D15
not used (must be=0)
MSB
D15
215
MSB
D15
215
MSB
D15
IF_window
D14
Port_2 (0=low, 1=high)
D14
214
D14
214
D14
Multipath_26
D13
213
D13
213
D13
Multipath_25
D12
2
12
D12
12
2
D12
Multipath_24
D11
211
D11
Multipath_23
D10
210
D13
D12
Port_1 (0=low, 1=high)
not used (must be=0)
D11
Loopamp current
D11
211
D10
not used (must be=0)
D10
210
D9
D8
not used (must be=0)
not used (must be=0)
9
D10
Multipath_22
D9
9
2
D9
Multipath_21
D9
2
D8
28
D8
28
D8
Multipath_20
D7
27
D7
IF_center
D6
26
D6
Fieldstrength_26
D5
5
2
D5
Fieldstrength_25
D7
ADC_Single
D7
27
D6
ADC_Mode
D6
26
D5
2
5
D4
24
D4
24
D4
Fieldstrength_24
3
D3
3
2
D3
Fieldstrength_23
D5
D4
ADC_ON
IF_DAC4
D3
not used (must be=0)
D3
2
D2
CP_Current 2
D2
22
D2
22
D2
Fieldstrength_22
D1
21
D1
Fieldstrength_21
D0
LSB
20
D0
LSB
Fieldstrength_20
D1
CP_Current 1
D1
21
D0
LSB
CP_Mode
D0
LSB
20
Mute_DAC7
Subaddress 03H
IF_Count_P1
Subaddress 04H
IF_Count_P2
Subaddress 05H
Specials
Subaddress 06H
IF_DAC4
Subaddress 07H
COMP_PRESET
Subaddress 0BH
Bit
Function
Bit
Function
Bit
Function
Bit
Function
Bit
Function
Bit
Function
MSB
D7
Enable
MSB
D7
Enable
MSB
D7
CF_Mod
e
MSB
D7
XTAL_DIV6
MSB
D7
not used
MSB
D15
not used
D6
MDAC_6
D6
not used
D6
CF_6
D6
VCO_2
D6
not used
D14
Fieldstrength_26
D5
MDAC_5
D5
Win_2
D5
CF_5
D5
AGC_1
D5
not used
D13
Fieldstrength_25
D4
MDAC_4
D4
Win_1
D4
CF_4
D4
AGC_0
D4
not used
D12
Fieldstrength_24
D3
MDAC_3
D3
Win_0
D3
CF_3
D3
XTAL_3
D3
GDAC_3
D11
Fieldstrength_23
D2
MDAC_2
D2
Gate_2
D2
CF_2
D2
XTAL_2
D2
GDAC_2
D10
Fieldstrength_22
D1
MDAC_1
D1
Gate_1
D1
CF_1
D1
XTAL_1
D1
GDAC_1
D9
Fieldstrength_21
D0
LSB
MDAC_0
D0
LSB
Gate_0
D0
LSB
CF_0
D0
LSB
XTAL_0
D0
LSB
GDAC_0
D8
Fieldstrength_20
D7
not used
Result Misc
Subaddress 83H
D6
Multipath_2 6
Bit Function
D5
Multipath_2 5
MSB
D7
IF_Window
D4
Multipath_2 4
D6
IF_Center
D3
Multipath_2 3
D5
Fieldstrength_Comp
D2
Multipath_2 2
D4
Multipath_Comp
D1
Multipath_2 1
D3
Res
D0
LSB
Multipath_2 0
D2
Res
Wireless Components
5-9
Specification, 17.02.00
TUA 4401K
Reference
D1
Res
D0
LSB
Res
Status, Subaddress 00H
MSB
D15
LSB MSB
D14
D13 D12
0
D11
0
0
1
0
0
D10 D9
D8
0
0
0
D7
LSB
D6
D5
D4
D3
D2
D1
D0
0
Function
these bits must be = 0
opendrain Port_2 output = high level
opendrain Port_2 output = low level
0
1
opendrain Port_1 output = high level
0
0
opendrain Port_1 output = low level
0
1
0
0
Loopamp currentsource high (ILOOPAMP=2.4mA) for
high speed tuning
Loopamp currentsource low (ILOOPAMP=1.2mA)
0
0
0
1
7 bit AD Converter enabled for single mode, stop
0
1
0
1
7 bit AD Converter enabled for single mode start. To
restart single mode write the same bits once more.
0
0
1
1
7 bit AD Converter enabled for continuous mode run.
0
x
x
1
7 bit AD Converter enabled for single or continuous
mode
0
x
x
0
7 bit AD Converter disabled for single and continuous
mode
0
1
IF_DAC4 enabled (see subaddress 07H)
0
0
IF_DAC4 disabled (see subaddress 07H)
0
1
1
Chargepump current Icp3 = 4mA
0
1
0
Chargepump current Icp2 = 2mA
0
0
1
Chargepump current Icp1 = 1mA
0
0
0
Chargepump current Icp0 = 500uA
0
1
Chargepump enabled
0
0
Chargepump disabled
Subaddress 01H, R_Counter and
Subaddress 02H, N_Counter
MSB
LSB MSB
LSB
Function
D15
D14
D13
D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Divider by 65535
0
0
0
0
0
1
1
1
1
1
0
1
0
0
0
0
Divider by 2000
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
0
Divider by 1230
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
0
Divider by 1000
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
Divider by 615
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
Divider by 100
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
Divider by 10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Divider by 2
Wireless Components
5 - 10
Specification, 17.02.00
TUA 4401K
Reference
Subaddress 05H, IF_Count_P2,
Centerfrequency = CF, CFstep= 6.25kHz) / 12.5 kHz
Subaddress 03H, Mute_DAC7
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
MSB
Function
D7
LSB
D6
D5
D4
D3
D2
D1
D0
1
Centerfrequency CF1
0
1
1
1
1
1
1
1
1
not used (must be 1)
Function
Centerfrequency CF0
1
1
1
1
1
1
1
1
CF1= 22.3875 MHz
0
1
1
1
1
1
1
1
CF0= 11.1937 MHz
Subaddress 04H, IF_Count_P1
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
1
Function
1
1
0
0
0
0
0
0
CF1= 22.600 MHz
0
1
0
0
0
0
0
0
CF0= 10.800 MHz
IF_Count enabled
0
0
IF_Count disabled
1
0
1
1
0
0
0
1
CF1= 21.4125 MHz
not used (must be=0)
0
0
1
1
0
0
0
1
CF0= 10.70625 MHz
1
0
0
Window=+/-100kHz*
1
0
1
1
0
0
0
0
CF1= 21.400 MHz
0
1
1
Window=+/-50kHz*
0
0
1
1
0
0
0
0
CF0= 10.700 MHz
0
1
0
Window=+/-25kHz*
1
0
1
0
1
1
1
1
CF1= 21.3875 MHz
0
0
1
Window=+/-12.5kHz*
0
0
1
0
1
1
1
1
CF0= 10.69375 MHz
0
0
0
Window=+/-6.25kHz*
1
1
1
Gatetime= 40.96ms
1
0
1
0
0
0
0
0
CF1= 21.200 MHz
1
1
0
Gatetime= 20.48ms
0
0
1
0
0
0
0
0
CF0= 10.600 MHz
1
0
1
Gatetime= 10.24ms
1
0
0
Gatetime= 5.12ms
1
0
0
1
0
0
0
0
CF1= 21.000 MHz
0
1
1
Gatetime= 2.56ms
0
0
0
1
0
0
0
0
CF0= 10.500 MHz
0
1
0
Gatetime= 1.28ms
0
0
1
Gatetime= 640us
1
0
0
0
0
0
0
0
CF1= 20.800 MHz
0
0
0
Gatetime= 320us
0
0
0
0
0
0
0
0
CF0= 10.400 MHz
* Valid for D7= 0 in subaddress 05H
Centerfrequencies for
Multiply window value with 2 for D7= 1 in subaddress 05H
D7=1
CF1= 20.800 MHz +n*12.5 kHz, CF Step=12.5 kHz
(e. g. D7= 0
D7=0
CF0= 10.400 MHz +n*6.25 kHz, CFStep=6.25 kHz
D7= 1
Window =+/- 6.25 kHz
Window =+/- 12.5 kHz)
Wireless Components
n=0...127
5 - 11
Specification, 17.02.00
TUA 4401K
Reference
Subaddress 06H, Specials
Subaddress 07H, IF_DAC4
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
1
MSB
Function
XTAL_DIV6 enabled
LSB
D7
D6
D5
D4
x
x
x
x
D3
D2
D1
D0
Function
not used
XTAL_DIV6 disabled
1
1
1
1
IF_DAC Gain adj.
typ. 16 dB
1
1st LO divided by 1
1
1
1
0
IF_DAC Gain adj.
0
1st LO divided by 2
1
1
0
1
IF_DAC Gain adj.
1
1
0
0
IF_DAC Gain adj.
0
0
0
Prest. AGC threshold typ.
15 mV
0
1
Prest. AGC threshold typ.
30 mV
1
0
1
1
IF_DAC Gain adj.
typ. 21 dB
1
0
Prest. AGC threshold typ.
45 mV
1
0
1
0
IF_DAC Gain adj.
1
1
Prest. AGC threshold typ.
60 mV
1
0
0
1
IF_DAC Gain adj.
1
1
1
1
XTAL_adjust CL = 15 pF
1
0
0
0
IF_DAC Gain adj.
1
1
1
0
XTAL_adjust CL = 14pF
0
1
1
1
IF_DAC Gain adj.
1
1
0
1
XTAL_adjust CL = 13 pF
0
1
1
0
IF_DAC Gain adj.
1
1
0
0
XTAL_adjust CL = 12 pF
0
1
0
1
IF_DAC Gain adj.
0
IF_DAC Gain adj.
typ. 24 dB
1
0
1
1
XTAL_adjust CL = 11 pF
1
0
1
0
XTAL_adjust CL = 10 pF
0
0
1
1
IF_DAC Gain adj.
1
0
0
1
XTAL_adjust CL = 9 pF *)
0
0
1
0
IF_DAC Gain adj.
1
0
0
0
XTAL_adjust CL = 8 pF *)
0
0
0
1
IF_DAC Gain adj.
0
IF_DAC Gain adj.
typ. 26 dB
0
1
1
1
XTAL_adjust CL = 7 pF
0
1
1
0
XTAL_adjust CL = 6 pF
0
1
0
1
XTAL_adjust CL = 5 pF
0
1
0
0
XTAL_adjust CL = 4 pF
0
0
1
1
XTAL_adjust CL = 3 pF
0
0
1
0
XTAL_adjust CL = 2 pF
0
0
0
1
XTAL_adjust CL = 1pF
0
0
0
0
XTAL_adjust CL = 0pF
0
1
0
0
0
0
*) For continuous tuning characteristic it is recommended to skip steps 8 and 9
Subaddress 0BH, Comp preset
MSB
D15
LSB
MSB
D14
D13
D12
D11
D10
D9
D8
D7
FP26
FP25
FP24
FP23
FP22
FP21
FP20
X
LSB
D6
D5
D4
D3
D2
X
D0
Function
not used
Preset value Fieldstrength
MP26 MP25 MP24 MP23
Wireless Components
D1
5 - 12
MP22
MP21 MP20 Preset value Multipath
Specification, 17.02.00
TUA 4401K
Reference
Subaddress 82H, Read results from Fieldstrength, Multipath and IF counter
MSB
D15
LSB MSB
D14
D13 D12
D11
D10 D9
D8
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Function
1
1
IF_counter result: IF frequency is outside the
desired window. IF frequency is lower as the
desired IF frequency.
0
1
IF_counter result: IF frequency is outside the
desired window.IF frequency is higher as the
desired IF frequency.
x
0
IF_counter result: IF frequency is inside the
desired window
M26
M25
M24
M23
M22
M21
M20
Result multipath byte M6...M0
F26
F25
F24
F23
F22
F21
F20
Result fieldstrength byte F6...F0
Subaddress 83H, Read results misc
MSB
LSB
D7
D6
1
D5
D4
Function
D3
D2
D1
D0
1
Res
Res
Res
Res
IF_counter result: IF frequency is outside the
desired window. IF frequency is lower as the
desired IF frequency.
0
1
Res
Res
Res
Res
IF_counter result: IF frequency is outside the
desired window.IF frequency is higher as the
desired IF frequency.
x
0
Res
Res
Res
Res
IF_counter result: IF frequency is inside the
desired window
1
Fieldstrength is higher as the preseted value in
subaddress 0BH (D8...D14)
0
Fieldstrength is lower as the preseted value in
subaddress 0BH (D8...D14)
1
Multipathsignal is higher as the preseted value in
subaddress 0BH (D0...D6)
0
Multipathsignal signal is lower as the preseted
value in subaddress 0BH (D0...D6)
5.4 I2C Bus Timing
BUS_MODE = LOW
tBUF
SDA
tHD.STA
tR
tSP
tF
tLOW
SCL
P
tHD.STA
S
Wireless Components
tHD.DAT
tHIGH
tSU.DAT
5 - 13
tSU.STA
tSU.STO
S
P
Specification, 17.02.00
TUA 4401K
Reference
Table 5-4
Parameter
Symbol
min
max
Unit
LOW level input voltage (SDA, SCL)
VIL
-0.5
0.90
V
HIGH level input voltage (SDA, SCL)
VIH
2.10
5.50
V
Pulse width of spikes which must be suppressed by the input filter
tSP
0
50
ns
LOW level output voltage 3mA sink current (SDA)
VOL
0
0.40
V
Output fall time from VIHmin to VILmax with a bus capacitance
from 10pF to 400pFwith up to 3mA
tOF
20+0.1Cb2)
250
ns
SCL clock frequency
fSCL
0
400
kHz
Bus free time between a STOP and START condition
tBUF
1.3
µs
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
tHO.STA
0.6
µs
LOW period of the SCL clock
tLOW
1.3
µs
HIGH period of the SCL clock
tHIGH
0.6
µs
Set-up time for a repeated START condition
tSU.STA
0.6
µs
Data hold time
tHD.DAT
0
ns
Data set -up time
tSU.DAT
100
ns
Rise, fall time of both SDA and SCL signals
tR, tF
Set-up time for STOP condition
tSU.STO
Capacitive load for each bus line
Cb
20+0.1Cb2)
300
0.6
ns
µs
400
pF
2)
Cb= capacitance of one bus line in pF.
Note that the maximum tF for the SDA and SCL bus lines quoted at 300ns is
longer than the specified maximum tOF for the output stages (250ns).This
allows series protection resistors to be connected between the SDA / SCL pins
and the SDA /SCL bus lines without exceeding the maximum specified tF.
Wireless Components
5 - 14
Specification, 17.02.00