UC1526 UC2526 UC3526 Regulating Pulse Width Modulator FEATURES DESCRIPTION • 8 To 35V Operation • 5V Reference Trimmed To ±1% • 1Hz To 400kHz Oscillator Range • Dual 100mA Source/Sink Outputs • Digital Current Limiting • Double Pulse Suppression • Programmable Deadtime • Under-Voltage Lockout • Single Pulse Metering • Programmable Soft-Start • Wide Current Limit Common Mode Range • TTL/CMOS Compatible Logic Ports The UC1526 is a high performance monolithic pulse width modulator circuit designed for fixed-frequency switching regulators and other power control applications. Included in an 18-pin dual-in-line package are a temperature compensated voltage reference, sawtooth oscillator, error amplifier, pulse width modulator, pulse metering and setting logic, and two low impedance power drivers. Also included are protective features such as soft-start and under-voltage lockout, digital current limiting, double pulse inhibit, a data latch for single pulse metering, adjustable deadtime, and provision for symmetry correction inputs. For ease of interface, all digital control ports are TTL and B-series CMOS compatible. Active LOW logic design allows wired-OR connections for maximum flexibility. This versatile device can be used to implement single-ended or push-pull switching regulators of either polarity, both transformerless and transformer coupled. The UC1526 is characterized for operation over the full military temperature range of -55°C to +125°C. The UC2526 is characterized for operation from -25°C to +85°C, and the UC3526 is characterized for operation from 0° to +70°C. • Symmetry Correction Capability • Guaranteed 6 Unit Synchronization BLOCK DIAGRAM 6/93 Powered by ICminer.com Electronic-Library Service CopyRight 2003 UC1526 UC2526 UC3526 ABSOLUTE MAXIMUM RATINGS (Note 1, 2) RECOMMENDED OPERATING CONDITIONS (Note 3) Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Collector Supply Voltage (+VC) . . . . . . . . . . . . . . . . . . . . . +40V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN Source/Sink Load Current (each output) . . . . . . . . . . . . . 200mA Reference Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Logic Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Power Dissipation at TA = +25°C (Note 2) . . . . . . . . . . 1000mW Power Dissipation at TC = +25°C (Note 2) . . . . . . . . . . 3000mW Operating Junction Temperature . . . . . . . . . . . . . . . . . . +150°C Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (soldering, 10 seconds) . . . . . . . . . . +300°C Note 1: Values beyond which damage may occur. Note 2: Consult packaging section of databook for thermal limitations and considerations of package. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V to +35V Collector Supply Voltage . . . . . . . . . . . . . . . . . . . +4.5V to +35V Sink/Source Load Current (each output) . . . . . . . . . 0 to 100mA Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA Oscillator Frequency Range . . . . . . . . . . . . . . . . 1Hz to 400kHz Oscillator Timing Resistor . . . . . . . . . . . . . . . . . . . 2kΩ to 150kΩ Oscillator Timing Capacitor . . . . . . . . . . . . . . . . . . . 1nF to 20µF Available Deadtime Range at 40kHz . . . . . . . . . . . . . 3% to 50% Operating Ambient Temperature Range UC1526 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C UC2526 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C UC3526 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0°C to +70°C Note 3: Range over which the device is functional and parameter limits are guaranteed. CONNECTION DIAGRAMS DIL-18, SOIC-18 (TOP VIEW) J or N Package, DW Package PACKAGE PIN FUNCTION FUNCTION PIN PLCC-20, LCC-20 (TOP VIEW) Q and L Packages N/C +Error -Error Comp. CSS _ _____ Reset - Current Sense + Current Sense _________ Shutdown RTIMING CT RD Sync Output A VC N/C Ground Output B +VIN VREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ELECTRICAL CHARACTERISTICS: +VIN = 15V, and over operating ambient temperature, unless otherwise specified, TA = TJ. PARAMETER TEST CONDITIONS UC1526 / UC2526 UC3526 UNITS MIN TYP MAX MIN TYP MAX 4.95 5.00 5.05 4.90 5.00 5.10 V 10 20 10 30 mV Reference Section (Note 4) Output Voltage TJ = + 25°C Line Regulation +VIN = 8 to 35V Load Regulation IL = 0 to 20mA 10 30 10 50 mV Temperature Stability Over Operating TJ 15 50 15 50 mV Total Output Voltage Range Over Recommended Operating Conditions 4.90 5.00 5.10 4.85 5.00 5.15 V Short Circuit Current VREF = 0V 25 50 100 25 50 100 mA 0.2 0.4 0.2 0.4 V Under -Voltage Lockout _______ RESET Output Voltage VREF = 3.8V VREF = 4.8V 2.4 Note 4: IL = 0mA. Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 4.8 2.4 4.8 V UC1526 UC2526 UC3526 ELECTRICAL CHARACTERISTICS: +VIN = 15V, and over operating ambient temperature, unless otherwise specified, TA = TJ. PARAMETER TEST CONDITIONS UC1526 / UC2526 MIN TYP MAX UC3526 MIN UNITS TYP MAX Oscillator Section (Note 5) Initial Accuracy TJ = + 25°C ±3 ±8 ±3 ±8 % Voltage Stability +VIN = 8 to 35V 0.5 1 0.5 1 % Temperature Stability Over Operating TJ 7 10 3 Minimum Frequency RT = 150kΩ Ω, CT = 20µ µF Maximum Frequency RT = 2kΩ Ω, CT = 1.0nF Sawtooth Peak Voltage +VIN = 35V Sawtooth Valley Voltage +VIN = 8V 1 400 % Hz 400 3.0 0.5 5 1 3.5 1.0 kHz 3.0 0.5 3.5 1.0 V V Error Amplifier Section (Note 6) Input Offset Voltage RS ≤ 2kΩ Ω Input Bias Current Input Offset Current 2 5 2 10 mV -350 -1000 -350 -2000 nA 35 100 35 200 nA DC Open Loop Gain RL ≥ 10MΩ Ω 64 72 60 72 dB HIGH Output Voltage VPIN1-VPIN2 ≥ 150mV, ISOURCE = 100µ µA 3.6 4.2 3.6 4.2 V LOW Output Voltage µA VPIN2-VPIN1 ≥ 150mV, ISINK = 100µ Common Mode Rejection Rs ≤ 12kΩ 70 94 70 94 dB Supply Voltage Rejection +VIN = 12 to 18V 66 80 66 80 dB 0.2 0.4 0.2 0.4 V PWM Comparator (Note 5) Minimum Duty Cycle VCOMPENSATION = +0.4V Maximum Duty Cycle VCOMPENSATION = +3.6V 0 45 49 2.4 4.0 0 45 49 2.4 4.0 % % Digital Ports (SYNC, SHUTDOWN, and RESET) HIGH Output Voltage ISOURCE =40µ µA LOW Output Voltage ISINK = 3.6mA HIGH Input Current VIH = +2.4V -125 -200 LOW Input Current VIL = +0.4V -225 -360 100 110 -3 -10 0.2 0.4 0.2 V 0.4 V -125 -200 µA -225 -360 µA 100 120 mV -3 -10 µA Current LImit Comparator (Note 7) Sense Voltage RS ≤ 50Ω Ω 90 Input Bias Current 80 Soft-Start Section Error Clamp Voltage RESET = +0.4V Cs Charging Current RESET =+2.4V 0.1 0.4 50 100 150 ISOURCE = 20mA 12.5 13.5 ISOURCE = 100mA 12 0.1 0.4 V 50 100 150 µA 12.5 13.5 Output Drivers (Each Output) (Note 8) HIGH Output Voltage LOW Output Voltage 13 ISINK = 20mA 0.2 ISINK = 100mA VC = 40V Rise Time Fall Time ____________ SHUTDOWN = +0.4V Collector Leakage Power Consumption (Note 9) Standby Current 12 V 13 V 0.3 0.2 1.2 2.0 1.2 2.0 V 50 150 50 150 µA CL = 1000pF 0.3 0.6 0.3 0.6 µs CL = 1000pF 0.1 0.2 0.1 0.2 µs 18 30 18 30 mA Note 4: IL = 0mA. Note 5: FOSC = 40kHz (RT = 4.12kΩ ± 1%, CT = 0.1µF ± 1%, RD = 0Ω) Powered by ICminer.com Electronic-Library Service CopyRight 2003 Note 6: VCM = 0 to +5.2V Note 8: VC = +15V Note 9: +VIN = +35V, RT = 4.12kΩ 3 0.3 V UC1526 UC2526 UC3526 APPLICATIONS INFORMATION Voltage Reference The reference regulator of the UC1526 is based on a temperature compensated zener diode. The circuitry is fully active at supply voltages above +8V, and provides up to 20mA of load current to external circuitry at +5.0V. In systems where additional current is required, an external PNP transistor can be used to boost the available current. A rugged low frequency audio-type transistor should be used, and lead lengths between the PWM and transistor should be as short as possible to minimize the risk of oscillations. Even so, some types of transistors may require collector-base capacitance for stability. Up to 1 amp of load current can be obtained with excellent regulation if the device selected maintains high current gain. Figure 2. Under-Voltage Lockout Schematic Soft-Start Circuit The soft-start circuit protects the power transistors and rectifier diodes from high current surges during power supply turn-on. When supply voltage is first applied to the _______ UC1526, the under-voltage lockout circuit holds RESET LOW with Q3. Q1 is turned on, which holds the soft-start capacitor voltage at zero. The second collector of Q1 clamps the output of the error amplifier to ground, guaranteeing zero duty cycle at the driver outputs. When the _______ supply voltage reaches normal operating range, RESET will go HIGH. Q1 turns off, allowing the internal 100mA current source to charge CS. Q2 clamps the error amplifier output to 1VBE above the voltage on CS. As the softstart voltage ramps up to +5V, the duty cycle of the PWM linearly increases to whatever value the voltage regulation loop requires for an error null. Figure 1. Extending Reference Output Current Under-Voltage Lockout The under-voltage lockout circuit protects the UC1526 and the power devices it controls from inadequate supply voltage, If +VIN is too low, the circuit disables the output _______ drivers and holds the RESET pin LOW. This prevents spurious output pulses while the control circuitry is stabilizing, and holds the soft-start timing capacitor in a discharged state. The circuit consists of a +1.2V bandgap reference and comparator circuit which is active when the reference voltage has risen to 3VBE or +1.8V at 25°C. When the reference voltage rises to approximately +4.4V, the circuit _______ enables the output drivers and releases the RESET pin, allowing a normal soft-start. The comparator has 200mV of hysteresis to minimize oscillation at the trip point. When +VIN to the PWM is removed and the reference _______ drops to +4.2V, the under-voltage circuit pulls RESET LOW again. The soft-start capacitor is immediately discharged, and the PWM is ready for another soft-start cycle. Figure 3. Soft-Start Circuit Schematic Digital Control Ports The three digital control ports of the UC1526 are bi-directional. Each pin can drive TTL and 5V CMOS logic directly, up to a fan-out of 10 low-power Schottky gates. Each pin can also be directly driven by open-collector The UC1526 can operate from a +5V supply by connecting the VREF pin to the +VIN pin and maintaining the supply between +4.8 and +5.2V. Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 UC1526 UC2526 UC3526 APPLICATIONS INFORMATION (cont.) TTL, open-drain CMOS, and open-collector voltage comparators; fan-in is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin_____ is pulled LOW _ to activate the particular function. Driving SYNC LOW initiates a discharge cycle in the oscillator. Pulling ____________ SHUTDOWN LOW immediately inhibits all PWM output _______ pulses. Holding RESET LOW discharges the soft-start capacitor. The logic threshold is +1.1V at +25°C. Noise immunity can be gained at the expense of fan-out with an external 2k pull-up resistor to +5V. Multiple devices can be synchronized together by programming one master unit for the desired frequency and then sharing its sawtooth and clock waveforms with the slave units. All CT terminals ______ are connected to the CT pin of the master, _____ and _all SYNC terminals are likewise connected to the SYNC pin of the master. Slave RT terminals are left open or connected to VREF. Slave RD terminals may be either left open or grounded. Error Amplifier The error amplifier is a transconductance design, with an output impedance of 2MΩ . Since all voltage gain takes place at the output pin, the open-loop gain/frequency characteristics can be controlled with shunt reactance to ground. When compensated for unity-gain stability with 100pF, the amplifier has an open-loop pole at 800Hz. The input connections to the error amplifier are determined by the polarity of the switching supply output voltage. For positive supplies, the common-mode voltage is +5.0V and the feedback connections in Figure 6A are used. With negative supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the +5.0V reference voltage, as shown in Figure 6B. Figure 4. Digital Control Port Schematic Oscillator The oscillator is programmed for frequency and dead time with three components: RT, CT and RD. Two waveforms are generated: a sawtooth waveform at pin 10 for pulse width modulation, and a logic clock at pin 12. The following procedure is recommended for choosing timing values: Output Drivers The totem-pole output drivers of the UC1526 are designed to source and sink 100mA continuously and 200mA peak. Loads can be driven either from the output pins 13 and 16, or from the +VC, as required. Since the bottom transistor of the totem-pole is allowed to saturate, there is a momentary conduction path from the +VC terminal to ground during switching. To limit the resulting current spikes a small resistor in series with pin 14 is always recommended. The resistor value is determined by the driver supply voltage, and should be chosen for 200mA peak currents. 1. With RD = 0 (pin 11 shorted to ground) select values for RT and CT from Figure 7 to give the desired oscillator period. Remember that the frequency at each driver output is half the oscillator frequency, and the frequency at the +VC terminal is the same as the oscillator frequency. 2. If more dead time is required, select a large value of RD. At 40kHz dead time increases by 400ns/Ω . 3. Increasing the dead time will cause the oscillator frequency to decrease slightly. Go back and decrease the value of RT slightly to bring the frequency back to the nominal design value. The UC1526 can be synchronized to an external logic clock by programming the oscillator to free-run at a frequency 10% slower than the sync frequency. A periodic ______ LOW logic pulse approximately 0.5µs wide at the SYNC pin will then lock the oscillator to the external frequency. Figure 5. Oscillator Connections and Waveforms Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 UC1526 UC2526 UC3526 Figure 6. Error Amplifier Connections Figure 8. Single-Ended Configuration Figure 7. Push-Pull Configuration Figure 9. Driving N-channel Power Mosfets TYPICAL CHARACTERISTICS Oscillator Period vs RT and CT Oscillation Period Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 UC1526 UC2526 UC3526 TYPICAL CHARACTERISTICS Output Driver Deadtime vs RD Value Under Voltage Lockout Characteristic Error Amplifier Open Loop Gain vs Frequency Current Limit Transfer Function Shutdown Delay Output Driver Saturation Voltage UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated Powered by ICminer.com Electronic-Library Service CopyRight 2003