UC1846-SP SLUS871B – JANUARY 2009 – REVISED OCTOBER 2011 www.ti.com RAD-TOLERANT CLASS-V, CURRENT-MODE PWM CONTROLLER Check for Samples: UC1846-SP FEATURES 1 • • • • • • • • • • • (1) Radiation tolerance is a typical value based upon initial device qualification with dose rate = 10 mrad/sec. Radiation Lot Acceptance Testing is available - contact factory for details. FK PACKAGE (TOP VIEW) VREF C/L SS NC Shsutdown VIN QML-V Qualified, SMD 5962-86806 Rad-Tolerant: 30 kRad (Si) TID (1) Automatic Feed-Forward Compensation Programmable Pulse-by-Pulse Current Limiting Automatic Symmetry Correction in Push-Pull Configuration Enhanced Load Response Characteristics Parallel-Operation Capability for Modular Power Systems Differential Current-Sense Amplifier With Wide Common-Mode Range Double-Pulse Suppression 500-mA (Peak) Totem-pole Outputs ±1% Bandgap Reference Undervoltage Lockout Soft-Start Capability Shutdown Terminal 500-kHz Operation C/S– C/S+ NC E/A+ E/A– 4 3 2 1 20 19 18 17 16 5 6 7 8 15 14 9 10 11 12 13 B Out VC NC Gnd A Out Comp CT NC RT Sync • • • • J OR W PACKAGE (TOP VIEW) C/L SS VREF C/S– C/S+ E/A+ E/A– Comp CT 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 Shutdown VIN B Out VC Gnd A Out Sync RT DESCRIPTION The UC1846 control devices provide all of the necessary features to implement fixed frequency, current mode control schemes while maintaining a minimum external parts count. The superior performance of this technique can be measured in improved line regulation, enhanced load response characteristics, and a simpler, easier-to-design control loop. Topological advantages include inherent pulse-by-pulse current limiting capability, automatic symmetry correction for push-pull converters, and the ability to parallel “power modules" while maintaining equal current sharing. Protection circuitry includes built-in under-voltage lockout and programmable current limit in addition to soft start capability. A shutdown function is also available which can initiate either a complete shutdown with automatic restart or latch the supply off. Other features include fully latched operation, double-pulse suppression, deadline adjust capability, a ±1% trimmed bandgap reference, and low outputs in the OFF state. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated UC1846-SP SLUS871B – JANUARY 2009 – REVISED OCTOBER 2011 www.ti.com ORDERING INFORMATION (1) TA –55°C to 125°C (1) PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING CDIP – J 5962-8680603VEA UC1846J-SP CFP - W 5962-8680603VFA UC1846W-SP LCCC – FK 5962-8680603V2A UC1846FK-SP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. BLOCK DIAGRAM 5.1 V REFERENCE REGULATOR VIN 15 2 VREF 13 VC SYNC 10 RT UVLO LOCKOUT Q CT 8 C/S- 3 11 A OUT T OSC Q Output Stage COMP X3 C/S+ F/F 9 S R Q 4 S 14 B OUT 0.5 V + 0.5 mA E/A+ 5 E/A– 6 COMP 7 12 GND E/A 1 C/L SS 16 SHUTDOWN 350 mV 6k NOTE: Pin numbers shown are for the J package. 2 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): UC1846-SP UC1846-SP SLUS871B – JANUARY 2009 – REVISED OCTOBER 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage 40 V Collector supply voltage 40 V IO Output current, source or sink 500 mA VI Analog input voltage (C/S-, C/S+, E/A+, E/A-, Shutdown) –0.3 V to VIN Reference output current –30 mA Sync output current –5 mA Error amplifier output current –5 mA Soft-start sink current 50 mA Oscillator charging current TJ Junction temperature TJmax Maximum junction temperature Tstg Storage temperature range Tlead Lead temperature (soldering, 10 seconds) (1) (2) 5 mA J package 9.6°C/W W package 8.2°C/W FK package 9.4°C/W 150°C –65°C to 150°C 300°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground. Currents are positive into, negative out of the specified terminal. ELECTRICAL CHARACTERISTICS VIN = 15 V, RT = 10kΩ, CT = 4.7 nF, TA = TJ = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 5.04 UNIT Reference Section Output voltage TJ = 25°C, IO = 1 mA 5.10 5.16 Line regulation VIN = 8 V to 40 V 5 20 mV Load regulation IL = 1 mA to 10 mA 3 15 mV Temperature stability Over operating range Total output variation Over line, load, and temperature (1) Output noise voltage 10 Hz ≤ f ≤ 10 kHz, TJ = 25°C (1) Long-term stability TJ = 125°C, 1000 hr Short-circuit output current VREF = 0 V Initial accuracy TJ = 25°C Voltage stability Temperature stability 0.4 5 V mV/°C 5.2 V 100 μV 5 mV –10 –45 mA 39 43 47 kHz VIN = 8 V to 40 V –1 2 % Over operating range –1 % 4.35 V Oscillator Section Sync output high level 3.9 Sync output low level 2.3 Sync input high level CT = 0 V Sync input low level CT = 0 V Sync input current Sync = 3.9 V, CT = 0 V 2.5 3.9 V V 2.5 V 1.3 1.5 mA 0.5 5 mV Error Amp Section Input offset voltage Input bias current -1 Input offset current (1) –0.6 40 Common mode range VIN = 8 V to 40 V Open-loop voltage gain ΔVO = 1.2 V to 3 V, VCM = 2 V 250 VIN – 2 0 80 μA 105 nA V dB Parameters ensured by design and/or characterization, if not production tested. Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): UC1846-SP 3 UC1846-SP SLUS871B – JANUARY 2009 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 15 V, RT = 10kΩ, CT = 4.7 nF, TA = TJ = –55°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT Unity-gain bandwidth TJ = 25°C 0.7 1 CMRR VCM = 0 V to 38 V, VIN = 40 V 75 100 PSRR VIN = 8 V to 40 V 80 105 dB Output sink current VID = -15 mV to -5 V, Comp = 1.2 V 2 6 mA Output source current VID = 15 mV to 5 V, Comp = 2.5 V High-level output voltage RL = (Comp) 15 kΩ Low-level output voltage RL = (Comp) 15 kΩ –0.5 4.3 MHZ dB -0.4 4.6 mA V 0.7 1 2.5 2.75 3.1 1.1 1.2 V Current Sense Amplifier Section Amplifier gain VC/S– = 0 V, C/L SS open (2) Maximum differential input signal (VC/S+ – VC/S–) C/L SS open (2), RL (Comp)= 15 kΩ Input offset voltage VC/L CMRR VCM = 1 V to 12 V 60 83 dB PSRR VIN = 8 V to 40 V 60 84 dB -10 –2.5 SS (3) = 0.5 V, Comp open (2) (4) Input bias current VC/L SS = 0.5 V, Comp open Input offset current VC/L SS = 0.5 V, Comp open (4) 5 TJ = 25°C V 25 mV μA 1 μA VIN – 3 V 200 500 ns 0.45 0.5 0.55 -30 –10 250 350 0.08 Input common-mode range Delay to outputs V/V (5) Current Limit Adjust Section Current limit offset VC/S– = 0 V, VC/S+ = 0 V, Comp open (4) Input bias current VE/A+ = VREF, VE/A– = 0 V V μA Shutdown Terminal Section Threshold voltage Input voltage range Minimum latching current (IC/S SS) 0 (6) 3 Maximum non-latching current (IC/S SS) (7) Delay to outputs TJ = 25°C (5) 400 mV VIN V 1.5 mA 1.5 0.8 mA 300 600 ns 200 μA 0.1 0.4 V 0.4 2.1 V Output Section Collector-emitter voltage Collector leakage current Output low-level voltage Output high-level voltage 40 V VC = 40 V ISINK = 20 mA ISINK = 100 mA ISOURCE = 20 mA 13 13.5 V ISOURCE = 100 mA 12 13.5 V Rise time CL = 1 nF, TJ = 25°C (5) 50 300 ns Fall time CL = 1 nF, TJ = 25°C (5) 50 300 ns 7.7 8 V Undervoltage Lockout Section Start-up threshold Threshold hysteresis 0.75 V Total Standby Current Supply current (2) (3) (4) (5) (6) (7) 4 17 21 mA Parameter measured at trip point of latch with VE/A+ = VREF, VE/A– = 0 V. Amplifier gain defined as: G = ΔVComp/ΔVC/S+; VC/S+ = 0 to 1 V. Parameter measured at trip point of latch with VE/A+ = VREF, VE/A– = 0 V. Parameters ensured by design and/or characterization, if not production tested. Current into C/S SS required to latch circuit in shutdown state. Current into C/S SS assured not to latch circuit in shutdown state. Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): UC1846-SP UC1846-SP SLUS871B – JANUARY 2009 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION Output deadtime is determined by the external capacitor, C T, according to the formula: τ d (µs ) = 145CT (µf ) ID = Oscillator discharge current at 25°C is typically 7.5. For large values of R T: τ d (µs ) ≈ 145CT (µf ). Oscillator frequency is approximated by the formula: fT (kHz ) ≈ ID . 3.6 ID RT (kΩ ) 2.2 . RT (k Ω ) • CT (µf ) Figure 1. Oscillator Circuit Figure 2. Error Amplifier Output Configuration Figure 3. Error Amplifier Gain and Phase vs Frequency Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): UC1846-SP 5 UC1846-SP SLUS871B – JANUARY 2009 – REVISED OCTOBER 2011 www.ti.com Figure 4. Error Amplifier Open-Logic Gain vs Load Resistance Figure 5. Parallel Operation 6 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): UC1846-SP UC1846-SP SLUS871B – JANUARY 2009 – REVISED OCTOBER 2011 www.ti.com R 2 VREF − 0.5 R1 + R 2 Peak Current (I S) is determined by the formula: IS = 3RS Figure 6. Pulse-by-Pulse Current Limiting Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): UC1846-SP 7 UC1846-SP SLUS871B – JANUARY 2009 – REVISED OCTOBER 2011 www.ti.com Figure 7. Soft-Start and Shutdown/Restart Functions A small RC filter may be required in some applications to reduce switch transients. Differential input allows remote, noise free sensing. Figure 8. Current-Sense Amplifier Connection 8 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): UC1846-SP UC1846-SP SLUS871B – JANUARY 2009 – REVISED OCTOBER 2011 www.ti.com Figure 9. Open-Loop Test Circuit Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): UC1846-SP 9 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan 5962-8680601V2A ACTIVE LCCC FK 20 1 TBD 5962-8680601VEA ACTIVE CDIP J 16 1 TBD (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type 5962-8680603V2A ACTIVE LCCC FK 20 1 TBD 5962-8680603VEA ACTIVE CDIP J 16 1 TBD POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type 5962-8680603VFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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