GM62093A GM62093A 12 × 8 CROSSPOINT SWITCH WITH CONTROL MEMORY Pin Configuration Description The GM62093A contains a 12 × 8 array of crosspoint together with a 7 to 96 Line decoder and latch circuits. The GM62093A employs LG’s advanced high voltage CMOS process technology. It provides extra low operating current and low power dissipation. Anyone of the 96 switchs can be addressed by selecting the ap-propriate 7 input bits. The selected turned on or off by applying a logical one or zero to the data in and the strobe input at logical one. A reset signal can be used to turn off all the switches together when is switched at logical one. The GM62093A is avail-able in a 40 lead dual in-line plastic and ceramic package. (Top View) Feature • CMOS 12 × 8 Cross Point Switch with Control Memory • Low On Resistance • Internal Control Latches • ∆Ron 15 Ω Max • Less Than 1% Total Distortion at 0 dbm • Extra Low Operating Current • Extra Low Cross-Talk Between Any Two Switches • Standard CMOS Noise Immunity • TTL Compatible Input X0 DATA RESET 1 0 7 8 88 95 8 ADDRESS AY0 AY1 Xi iInput (I=0~11) AX3 LATCHES AX2 7 TO 96 DECODER AX0 AX1 AY2 96 Y0 1 40 VDD 2 39 Y2 RESET 3 38 DATA AX3 4 37 Y1 AX0 5 36 NC NC 6 35 Y0 NC 7 34 NC X6 8 33 X0 X7 9 32 X1 X8 10 31 X2 X9 11 30 X3 X10 12 29 X4 X11 13 28 X5 NC 14 27 NC Y7 15 26 NC NC 16 25 AY1 Y6 17 24 AY0 STROBE 18 23 AX2 Y5 19 22 AX1 VSS 20 21 Y4 Application • PBX Systems • Mobile Radio • Test Eqiepment Instrumentation • Analog/ Digital Multiplexer Block Diagram STROBE Y3 AY2 Yi Input (i=0~7) Y7 1 X11 GM62093A Absolute Maximum Rating SYMBOL VDD VIN IIN P(P-DIP) (C-DIP) TOPR TSTG PARAMETER DC Supply Voltage Input Voltage Range DC Input current Power Dissipation MIN -0.5 -0.5 Operation Temperature Range Storage Temperature Range 0 -65 MAX 18 V+0.5 ±10 0.6 1 70 150 UNIT V V mA W MAX 16 VDD 70 UNIT V V °C °C Recommended Operating Range SYMBOL VDD VIN TOPR PARAMETER DC Supply Input Voltage Range Operation Temperature Range MIN 8 0 0 °C Static Electrical Characteristics: ( TA = 0°C to 70°C , VCC = 14V ) SYMBOL PARAMETER TEST CONDITION Quiescent Supply Current All Digital Input at Vss or VDD Ron On Resistance VDD = 3.5V and I(thru S/W)=10mA Ron Ron Difference Between Any Two Switchs Asc Analog Signal Capability VDD = 14V All Switchs On Vis = 14V and I(thru S/W)= −100µA I LOFF Off Leakage All Switch off V=V=0 to V MIN TYP MAX UNIT CROSS POINT I DD All Digital Input at 2.4 V 7 13.96 100 µA 15 mA 65 15 Ω Ω 14.0 V ±500 nA 0.8 V CONTROLS VIL VIH I LEAK Input Low Voltage Input High Voltage Input Leakage 2.4 VIN = 0 to VDD 2 V ±500 nA GM62093A Dynamic Electrical Characteristics : ( TA SYMBOL PARAMETER = 25°C , CL = 50pF , VDD = 14V TEST CONDITION MIN ) TYP MAX UNIT 30 NS CROSS POINT tP f RES CX CY C DI Propagation Delay Time R L = 1kΩ, VDC = 5V VIS = 2VPP Frequency Response [20log(VOUT/VIN)=-3dB] R L = 1kΩ, VDC = 5V VIS = 2VPP , C L = 3p F 40 MHz Sine Wave Response(Distortion) R L = 1kΩ, VDC = 5V , VIS = 2VPP , f = 1MHz 1 % Feedthrough (All S/W’s Off) R L = 1kΩ, VDC = 5V VIS = 2VPP , f = 10KHz -80 dB Crosstalk Between Any Two Channels R S = 50Ω, R L = 1kΩ , VIS = 2VPP , f = 1KHz -95 dB -110 Capacitance (XN to Ground) Switch Off 20 pF Capacitance (YN to Ground) Switch Off 30 pF Digital Input Capacitance 5 pF CONTROL t DS t DD t DA t DR t SD t SA t HD t HA t SW t RW Strobe to Switch Delay R L = 1kΩ, t r = t f = 20nS 160 nS Data to Switch Delay R L = 1kΩ, t r = t f = 20nS 180 nS Address to Switch Delay R L = 1kΩ, t r = t f = 20nS 200 nS Reset to Switch Delay R L = 1kΩ, t r = t f = 20nS 200 nS Data Setup Time Address Setup Time R L = 1kΩ, t r = t f = 20nS 30 nS Data Hold Time Address Hold Time R L = 1kΩ, t r = t f = 20nS 30 nS Minimum Strobe Pulse Width Minimum Reset Pulse Width R L = 1kΩ, t r = t f = 20nS 200 nS Functional Description DATA pin may be held high to turn the switch on, or low to turn it off. Finally a positive pulse to the STROBE pin initiates the ac-tion determined by the ADDRESS and DATA pins. All 96 switches can be turned off by forcing the RESET pin high. The GM62093A contains a 12 × 8 array of analog switches, each with a latch to maintain its on(closed)or off(opened) state. Seven ADDRESS lines(AX0~AX3, AY0~AY2) are provided to address any one of the 96 switches. After any one of the switches is selected, the 3 GM62093A Timing Diagram t SW STROBE t DS t HA t SA ADDRESS t DA t HD t SD DATA t DD t RW RESET t DR ANALOG OUTPUT Truth Table AX0 0 1 0 1 0 1 0 1 0 1 0 1 0 AX1 0 0 1 1 0 0 0 0 1 1 0 0 0 AX2 0 0 0 0 1 1 0 0 0 0 1 1 0 Address AX3 0 0 0 0 0 0 1 1 1 1 1 1 0 AY0 0 0 0 0 0 0 0 0 0 0 0 0 1 AY1 0 0 0 0 0 0 0 0 0 0 0 0 0 AY2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 X11-Y1 X0-Y2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ Connections X0-Y0 X1-Y0 X2-Y0 X3-Y0 X4-Y0 X5-Y0 X6-Y0 X7-Y0 X8-Y0 X9-Y0 X10-Y0 X11-Y0 X0-Y1 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 1 0 0 0 1 0 1 0 0 1 1 1 0 0 X11-Y2 X0-Y3 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 1 0 0 0 1 0 1 0 1 0 1 0 0 1 X11-Y3 X0-Y4 1 1 X11-Y4 X0-Y5 1 1 X11-Y5 X0-Y6 1 1 X11-Y6 X0-Y7 X11-Y7 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 1 0 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 A X =0110, 1110, 0111 and 1111 and not allowed 4 0 0 0 1 1 1 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ GM62093A Test circuit and Characteristics. l CROSSTALK vs. FREQUENCY dB Fig.1-Crosstalk -80 l TEST CIRCUIT VIN -90 S/W ON S/W ON VOUT 50Ω 1KΩ 1KΩ -100 1KΩ -110 5V 5V 5V 5V -120 -130 VDD = 14 V VIN =2Vp-p 10 2 10 103 f(KHz) l RESULT Fig.2 –analog signal capability(Vin vs. Vout) VOUT (V) VDD = 16 l TEST CIRCUIT 16 VDD VDD = 12 12 VIN S/W ON VDD = 8 VOUT 8 VDD = 4 4 VIN = 0 ~ 20 V VCONTROL = 5 V 0 5 4 8 12 16 (V) VIN GM62093A l RESULT Fig.3-Ron measurement R ON Ω l TEST CIRCUIT VDD S.W 60 50 10mA ON 40 3.5V 30 +Ä V R ON = ˜ V ˜ V = I ON 10mA 20 6 8 10 12 14 16 VCONTROL = 5V VDD = 6 ~ 18 V l BANDWIDTH (-3dB point: ABOUT 45MHz) Fig.4-Frequency response. l TEST CIRCUIT dB 0 -2 VIN VOUT -4 S/W ON -6 15KΩ -8 VDD = 14 V VIN=2Vp-p -10 1 10 10 2 f(MHz) 6 VDD