ISO-CMOS MT8808 8 x 8 Analog Switch Array Features ISSUE 2 • Internal control latches and address decoder • Short set-up and hold times • Wide operating voltage: 4.5V to 13.2V • 12Vpp analog signal capability • • R ON 65Ω max. @ V DD=12V, 25°C ∆R ON ≤ 10Ω @ V DD=12V, 25°C • Full CMOS switch for low distortion • Minimum feedthrough and crosstalk • Separate analog and digital reference supplies • Low power consumption ISO-CMOS technology Ordering Information MT8808AC 28 Pin Ceramic DIP MT8808AE 28 Pin Plastic DIP MT8808AP 28 Pin PLCC -40° to 85°C Description The Mitel MT8808 is fabricated in MITEL’s ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8 x 8 array of crosspoint switches along with a 6 to 64 line decoder and latch circuits. Any one of the 64 switches can be addressed by selecting the appropriate six address bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. VSS is the ground reference of the digital inputs. The range of the analog signal is from VDD to VEE. Applications • Key systems • PBX systems • Mobile radio • Test equipment /instrumentation • Analog/digital multiplexers • Audio/Video switching STROBE November 1988 DATA RESET 1 VDD VEE VSS 1 AX0 AX2 AY0 8 x 8 6 to 64 Decoder Switch Latches Array AY1 AY2 64 •••••••••••••••• AX1 Xi I/O (i=0-7) 64 ••••••••••••••••••• Yi I/O (i=0-7) Figure 1 - Functional Block Diagram 3-15 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AY1 AY0 AX2 AX1 AX0 X1 X3 X5 X7 VDD Y0 Y1 Y2 Y3 4 3 2 1 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VSS X0 X2 X4 X6 RESET Y7 5 6 7 8 9 10 11 • 12 13 14 15 16 17 18 AY2 STROBE VEE DATA VSS X0 X2 X4 X6 RESET Y7 Y6 Y5 Y4 DATA VEE STROBE AY2 AY1 AY0 AX2 ISO-CMOS 25 24 23 22 21 20 19 AX1 AX0 X1 X3 X5 X7 VDD Y6 Y5 Y4 Y3 Y2 Y1 Y0 MT8808 28 PIN PLCC 28 PIN CERDIP/PLASTIC DIP Figure 2 - Pin Connections Pin Description Pin # Name 1 AY2 2 Description AY2 Address Line (Input). STROBE STROBE (Input): enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. 3 VEE 4 DATA 5 VSS 6-9 X0, X2, X4, X6 X0, X2, X4 and X6 Analog (Inputs/Outputs): these are connected to the X0, X2, X4 and X6 rows of the switch array. 10 RESET Master RESET (Input): this is used to turn off all switches. Active High. 11-18 Y7 - Y0 Y7 - Y0 Analog (Inputs/Outputs): these are connected to the Y0 - Y7 columns of the switch array. 19 VDD 20-23 X7, X5, X3, X1 24-26 AX0AX2 27,28 3-16 Negative Power Supply. DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. Digital Ground Reference . Positive Power Supply. X7, X5, X3 and X1 Analog (Inputs/Outputs): these are connected to the X7, X5, X3 and X1 rows of the switch array. AX0 - AX2 Address Lines (Inputs). AY0, AY1 AY0 and AY1 Address Lines (Inputs). ISO-CMOS MT8808 Functional Description Address Decode The MT8808 is an analog switch matrix with an array size of 8 x 8. The switch array is arranged such that there are 8 columns by 8 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs. The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high degree of isolation when turned off. The control memory consists of a 64 bit write only RAM in which the bits are selected by the address inputs (AY0-AY2, AX0-AX2). Data is presented to the memory on the DATA input. Data is asynchro-nously written into memory whenever the STROBE input is high and is latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y inputs/ outputs can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input will asynchronously return all memory locations to logical “0” turning off all crosspoint switches. Two voltage reference pins (V SS and VEE) are provided for the MT8808 to enable switching of negative analog signals. The range for digital signals is from V DD to V SS while the range for analog signals is from V DD to VEE. VSS and V EE pins can be tied together if a single voltage reference is needed. The six address inputs along with the STROBE are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low while the address and data are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on the falling edge of STROBE in order for correct data to be written to the latch. 3-17 MT8808 ISO-CMOS Absolute Maximum Ratings*- Voltages are with respect to VEE unless otherwise stated. Parameter Symbol Min Max Units 1 Supply Voltage VDD VSS -0.3 -0.3 15.0 VDD+0.3 V V 2 Analog Input Voltage VINA -0.3 VDD+0.3 V 3 Digital Input Voltage VIN VSS-0.3 VDD+0.3 V 4 Current on any I/O Pin I ±15 mA 5 Storage Temperature TS +150 °C 6 Package Power Dissipation 0.6 1.0 W W PLASTIC DIP CERDIP -65 PD PD * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to VEE unless otherwise stated. Characteristics Sym Min Typ Max Units TO -40 25 85 °C 1 Operating Temperature 2 Supply Voltage VDD VSS 4.5 VEE 13.2 VDD-4.5 V V 3 Analog Input Voltage VINA VEE VDD V 4 Digital Input Voltage VIN VSS VDD V DC Electrical Characteristics†Characteristics 1 Voltages are with respect to VEE=VSS=0V, VDD =12V unless otherwise stated. Sym Quiescent Supply Current Test Conditions Min IDD Typ‡ Max Units Test Conditions 1 100 µA All digital inputs at VIN=VSS or VDD 0.4 1.5 mA All digital inputs at VIN=2.4 + VSS ; VSS =7.0V 5 15 mA ±1 ±500 nA All digital inputs at VIN=3.4V IVXi - VYjI = VDD - VEE See Appendix, Fig. A.1 0.8+VSS V VSS =7.5V; VEE=0V VSS =6.5V; VEE=0V 2 Off-state Leakage Current (See G.9 in Appendix) IOFF 3 Input Logic “0” level VIL 4 Input Logic “1” level VIH 2.0+VSS V 5 Input Logic “1” level VIH 3.3 V 6 Input Leakage (digital pins) ILEAK 0.1 10 µA All digital inputs at VIN = VSS or VDD † DC Electrical Characteristics are over recommended temperature range. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins. Characteristics Sym 25°C Typ Max 70°C Typ Max 85°C Typ Units Test Conditions Max 1 On-state VDD=12V Resistance VDD=10V VDD= 5V (See G.1, G.2, G.3 in Appendix) RON 45 55 120 65 75 185 75 85 215 80 90 225 Ω Ω Ω VSS=VEE=0V,VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2 2 Difference in on-state resistance between two switches (See G.4 in Appendix) ∆RON 5 10 10 10 Ω VDD=12V, VSS=VEE=0, VDC=VDD/2, IVXi-VYjI = 0.4V See Appendix, Fig. A.2 3-18 ISO-CMOS MT8808 AC Electrical Characteristics† - Crosspoint Performance-Voltages are with respect to VDD=5V, VSS=0V, VEE=-7V, unless otherwise stated. Characteristics Sym Typ‡ Min Max Units Test Conditions 1 Switch I/O Capacitance CS 20 pF f=1 MHz 2 Feedthrough Capacitance CF 0.2 pF f=1 MHz 3 Frequency Response Channel “ON” 20LOG(VOUT/VXi)=-3dB F3dB 45 MHz Switch is “ON”; VINA = 2Vpp sinewave; RL = 1kΩ See Appendix, Fig. A.3 4 Total Harmonic Distortion (See G.5, G.6 in Appendix) THD 0.01 % Switch is “ON”; VINA = 2Vpp sinewave f= 1kHz; RL=1kΩ 5 Feedthrough Channel “OFF” Feed.=20LOG (VOUT/VXi) (See G.8 in Appendix) FDT -95 dB All Switches “OFF”; VINA= 2Vpp sinewave f= 1kHz; RL= 1kΩ. See Appendix, Fig. A.4 6 Crosstalk between any two channels for switches Xi-Yi and Xj-Yj. Xtalk -45 dB VINA=2Vpp sinewave f= 10MHz; RL = 75Ω. -90 dB VINA=2Vpp sinewave f= 10kHz; RL = 600Ω. -85 dB VINA=2Vpp sinewave f= 10kHz; RL = 1kΩ. -80 dB VINA=2Vpp sinewave f= 1kHz; RL = 10kΩ. Refer to Appendix, Fig. A.5 for test circuit. ns RL=1kΩ; CL=50pF Xtalk=20LOG (VYj/VXi). (See G.7 in Appendix). 7 Propagation delay through switch 30 tPS † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5dB better. AC Electrical Characteristics† - Control and I/O Timings- Voltages are with respect to VDD=5V, VSS=0V, VEE=-7V, unless otherwise stated. Characteristics 1 Control Input crosstalk to switch (for CS, DATA, STROBE, Address) 2 Sym Min Typ‡ Max Units Test Conditions CXtalk 30 mVpp Digital Input Capacitance CDI 10 pF 3 Switching Frequency FO 4 Setup Time DATA to STROBE tDS 10 ns RL= 1kΩ, CL=50pF 5 Hold Time DATA to STROBE tDH 10 ns RL= 1kΩ, CL=50pF 6 Setup Time Address to STROBE tAS 10 ns RL= 1kΩ, CL=50pF 7 Hold Time Address to STROBE tAH 10 ns RL= 1kΩ, CL=50pF 8 STROBE Pulse Width tSPW 20 ns RL= 1kΩ, CL=50pF 9 RESET Pulse Width tRPW 40 ns RL= 1kΩ, CL=50pF 10 STROBE to Switch Status Delay tS 40 100 ns RL= 1kΩ, CL=50pF 11 DATA to Switch Status Delay tD 50 100 ns RL= 1kΩ, CL=50pF 12 RESET to Switch Status Delay tR 35 100 ns RL= 1kΩ, CL=50pF 20 VIN=3V squarewave; RIN=1kΩ, RL=10kΩ. See Appendix, Fig. A.6 f=1MHz MHz † Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details. Digital Input rise time (tr) and fall time (tf) = 5ns. ‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Refer to Appendix, Fig. A.7 for test circuit. 3-19 MT8808 ISO-CMOS tRPW 50% RESET 50% tSPW STROBE 50% 50% 50% tAS ADDRESS 50% 50% tAH DATA 50% 50% tDS tDH ON SWITCH* OFF tR tS tD tR Figure 3 - Control Memory Timing Diagram * See Appendix, Fig. A.7 for switching waveform AY2 AY1 AY0 AX2 AX1 AX0 Connection AY2 AY1 AY0 AX2 AX1 AX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 X0 X1 X2 X3 X4 X5 X6 X7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 X0 X1 X2 X3 X4 X5 X6 X7 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 X0 X1 X2 X3 X4 X5 X6 X7 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 X0 X1 X2 X3 X4 X5 X6 X7 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 0 1 0 1 0 1 0 1 X0 X1 X2 X3 X4 X5 X6 X7 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 X0 X1 X2 X3 X4 X5 X6 X7 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 0 1 0 1 0 1 0 1 X0 X1 X2 X3 X4 X5 X6 X7 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 X0 X1 X2 X3 X4 X5 X6 X7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Table 1. Address Decode Truth Table 3-20 Connection