NEC UPD4482361GF-C75

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4482161, 4482181, 4482321, 4482361
8M-BIT CMOS SYNCHRONOUS FAST SRAM
FLOW THROUGH OPERATION
Description
The µPD4482161 is a 524,288-word by 16-bit, the µPD4482181 is a 524,288-word by 18-bit, the µPD4482321 is a
262,144-word by 32-bit and the µPD4482361 is a 262,144-word by 36-bit synchronous static RAM fabricated with
advanced CMOS technology using Full-CMOS six-transistor memory cell.
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The µPD4482161, µPD4482181, µPD4482321 and µPD4482361 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
• 3.3 V or 2.5 V core supply
• Synchronous operation
• Operating temperature : TA = 0 to 70 °C (-A65, -A75, -A85, -C75, -C85)
TA = −40 to +85 °C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)
• Internally self-timed write control
• Burst read / write : Interleaved burst and linear burst sequence
• Fully registered inputs for flow through operation
• All registers triggered off positive clock edge
• 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
• Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)
• Asynchronous output enable : /G
• Burst sequence selectable : MODE
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
• Separate byte write enable : /BW1 to /BW4, /BWE (µPD4482321, µPD4482361)
/BW1, /BW2, /BWE (µPD4482161, µPD4482181)
Global write enable : /GW
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M14521EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
The mark  shows major revised points.
2000
µPD4482161, 4482181, 4482321, 4482361
Ordering Information
Part number
(1/2)
Access
Clock
Core Supply
Time
Frequency
Voltage
ns
MHz
V
I/O Interface
Package
Temperature
°C
Note
µPD4482161GF-A65
6.5
133
µPD4482161GF-A75
7.5
117
µPD4482161GF-A85
8.5
100
µPD4482181GF-A65
6.5
133
3.3 V LVTTL Note
µPD4482181GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
µPD4482181GF-A85
8.5
100
µPD4482321GF-A65
6.5
133
3.3 V LVTTL Note
µPD4482321GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
µPD4482321GF-A85
8.5
100
µPD4482361GF-A65
6.5
133
3.3 V LVTTL Note
µPD4482361GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
µPD4482361GF-A85
8.5
100
µPD4482161GF-C75
7.5
117
µPD4482161GF-C85
8.5
100
µPD4482181GF-C75
7.5
117
µPD4482181GF-C85
8.5
100
µPD4482321GF-C75
7.5
117
µPD4482321GF-C85
8.5
100
µPD4482361GF-C75
7.5
117
µPD4482361GF-C85
8.5
100
3.3 ± 0.165
Operating
3.3 V LVTTL
3.3 V or 2.5 V LVTTL
2.5 ± 0.125
0 to 70
100-pin PLASTIC
LQFP (14 × 20)
2.5 V LVTTL
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75 (117 MHz).
2
Data Sheet M14521EJ3V0DS
µPD4482161, 4482181, 4482321, 4482361
(2/2)
Part number
Access
Clock
Core Supply
Time
Frequency
Voltage
ns
MHz
V
I/O Interface
Package
Temperature
°C
Note
µPD4482161GF-A65Y
6.5
133
µPD4482161GF-A75Y
7.5
117
µPD4482161GF-A85Y
8.5
100
µPD4482181GF-A65Y
6.5
133
3.3 V LVTTL Note
µPD4482181GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
µPD4482181GF-A85Y
8.5
100
µPD4482321GF-A65Y
6.5
133
3.3 V LVTTL Note
µPD4482321GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
µPD4482321GF-A85Y
8.5
100
µPD4482361GF-A65Y
6.5
133
3.3 V LVTTL Note
µPD4482361GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
µPD4482361GF-A85Y
8.5
100
µPD4482161GF-C75Y
7.5
117
µPD4482161GF-C85Y
8.5
100
µPD4482181GF-C75Y
7.5
117
µPD4482181GF-C85Y
8.5
100
µPD4482321GF-C75Y
7.5
117
µPD4482321GF-C85Y
8.5
100
µPD4482361GF-C75Y
7.5
117
µPD4482361GF-C85Y
8.5
100
3.3 ± 0.165
Operating
3.3 V LVTTL
3.3 V or 2.5 V LVTTL
2.5 ± 0.125
−40 to +85
100-pin PLASTIC
LQFP (14 × 20)
2.5 V LVTTL
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75Y (117 MHz).
Data Sheet M14521EJ3V0DS
3
µPD4482161, 4482181, 4482321, 4482361
Pin Configurations
/××× indicates active low signal.
100-pin PLASTIC LQFP (14 x 20)
[µPD4482161GF, µPD4482181GF]
A9
A8
/ADV
/AP
/AC
/G
/BWE
/GW
CLK
VSS
VDD
/CE2
/BW1
/BW2
NC
NC
CE2
/CE
A7
A6
Marking Side
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
1
80
A18
NC
2
79
NC
NC
3
78
NC
VDDQ
4
77
VDDQ
VSSQ
5
76
VSSQ
NC
6
75
NC
NC
7
74
I/OP1, NC
I/O9
8
73
I/O8
I/O10
9
72
I/O7
VSSQ
10
71
VSSQ
VDDQ
11
70
VDDQ
I/O11
12
69
I/O6
I/O12
13
68
I/O5
NC
14
67
VSS
VDD
15
66
NC
NC
16
65
VDD
VSS
17
64
ZZ
I/O13
18
63
I/O4
I/O14
19
62
I/O3
VDDQ
20
61
VDDQ
VSSQ
21
60
VSSQ
I/O15
22
59
I/O2
I/O16
23
58
I/O1
I/OP2, NC
24
57
NC
NC
25
56
NC
VSSQ
26
55
VSSQ
VDDQ
27
54
VDDQ
NC
28
53
NC
NC
29
52
NC
NC
30
51
NC
Remark Refer to Package Drawing for the 1-pin index mark.
4
Data Sheet M14521EJ3V0DS
A16
A15
A14
A13
A12
A11
A10
NC
A17
VSS
VDD
NC
NC
A0
A1
A2
A3
A4
A5
MODE
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
µPD4482161, 4482181, 4482321, 4482361
Pin Identification (µPD4482161GF, µPD4482181GF)
Symbol
A0 to A18
Pin No.
Description
37, 36, 35, 34, 33, 32, 100, 99, 82,
Synchronous Address Input
81, 44, 45, 46, 47, 48, 49, 50, 43, 80
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9,
Synchronous Data In,
12, 13, 18, 19, 22, 23
Synchronous / Asynchronous Data Out
Note
74
Synchronous Data In (Parity),
I/OP2, NC Note
24
Synchronous / Asynchronous Data Out (Parity)
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1, /BW2, /BWE
93, 94, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
I/OP1, NC
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
VDD
15, 41, 65, 91
Power Supply
VSS
17, 40, 67, 90
Ground
VDDQ
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
VSSQ
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30,
No Connection
38, 39, 42, 51, 52, 53, 56, 57, 66, 75,
78, 79, 95, 96
Note NC (No Connection) is used in the µPD4482161GF.
I/OP1 and I/OP2 are used in the µPD4482181GF.
Data Sheet M14521EJ3V0DS
5
µPD4482161, 4482181, 4482321, 4482361
100-pin PLASTIC LQFP (14 x 20)
[µPD4482321GF, µPD4482361GF]
A9
A8
/ADV
/AP
/AC
/G
/BWE
/GW
CLK
VSS
VDD
/CE2
/BW1
/BW2
/BW3
/BW4
CE2
/CE
A7
A6
Marking Side
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3, NC
1
80
I/OP2, NC
I/O17
2
79
I/O16
I/O18
3
78
I/O15
VDDQ
4
77
VDDQ
VSSQ
5
76
VSSQ
I/O19
6
75
I/O14
I/O20
7
74
I/O13
I/O21
8
73
I/O12
I/O22
9
72
I/O11
VSSQ
10
71
VSSQ
VDDQ
11
70
VDDQ
I/O23
12
69
I/O10
I/O24
13
68
I/O9
NC
14
67
VSS
VDD
15
66
NC
NC
16
65
VDD
VSS
17
64
ZZ
I/O25
18
63
I/O8
I/O26
19
62
I/O7
VDDQ
20
61
VDDQ
VSSQ
21
60
VSSQ
I/O27
22
59
I/O6
I/O28
23
58
I/O5
I/O29
24
57
I/O4
I/O30
25
56
I/O3
VSSQ
26
55
VSSQ
VDDQ
27
54
VDDQ
I/O31
28
53
I/O2
I/O32
29
52
I/O1
I/OP4, NC
30
51
I/OP1, NC
Remark Refer to Package Drawing for the 1-pin index mark.
6
Data Sheet M14521EJ3V0DS
A16
A15
A14
A13
A12
A11
A10
A17
NC
VSS
VDD
NC
A0
NC
A1
A2
A3
A4
A5
MODE
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
µPD4482161, 4482181, 4482321, 4482361
Pin Identification (µPD4482321GF, µPD4482361GF)
Symbol
A0 to A17
Pin No.
Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 43
I/O1 to I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72,
Synchronous Data In,
73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13,
Synchronous / Asynchronous Data Out
18, 19, 22, 23, 24, 25, 28, 29
Note
51
Synchronous Data In (Parity),
I/OP2, NC Note
80
Synchronous / Asynchronous Data Out (Parity)
I/OP3, NC Note
1
I/OP1, NC
I/OP4, NC
Note
30
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1 to /BW4, /BWE
93, 94, 95, 96, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
ZZ
64
Asynchronous Power Down State Input
VDD
15, 41, 65, 91
Power Supply
VSS
17, 40, 67, 90
Ground
VDDQ
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
VSSQ
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
14, 16, 38, 39, 42, 66
No Connection
Do not change state during normal operation
Note NC (No Connection) is used in the µPD4482321GF.
I/OP1 to I/OP4 are used in the µPD4482361GF.
Data Sheet M14521EJ3V0DS
7
µPD4482161, 4482181, 4482321, 4482361
Block Diagrams
[µPD4482161, µPD4482181]
A0 to A18
19
Address
register
MODE
/ADV
CLK
19
17
19
A0, A1
Binary Q1
A1’
counter
and logic
CLR
Q0
A0’
/AC
/AP
/BW1
Byte 1
Write register
/BW2
Byte 2
Write register
Row and column
decoders
8/9
8/9
Byte 1
Write driver
Memory cell array
Byte 2
Write driver
512 × 16 columns
(8,388,608 bits)
512 × 18 columns
1,024 rows
(9,437,184 bits)
/BWE
16/18
16/18
Input
register
/GW
Enable
register
/CE
CE2
/CE2
/G
2
16/18
I/O1 to I/O16
I/OP1 to I/OP2
Power down control
ZZ
Burst Sequence
[µPD4482161, µPD4482181]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
A18 to A2, A1, A0
1st Burst Address
A18 to A2, A1, /A0
2nd Burst Address
A18 to A2, /A1, A0
3rd Burst Address
A18 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
1st Burst Address
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
2nd Burst Address
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
3rd Burst Address
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
8
Data Sheet M14521EJ3V0DS
Output
buffer
µPD4482161, 4482181, 4482321, 4482361
[µPD4482321, µPD4482361]
A0 to A17
18
Address
register
MODE
/ADV
CLK
18
16
18
A0, A1
Binary Q1
A1’
counter
and logic
CLR
Q0
A0’
/AC
/AP
/BW1
Byte 1
Write register
/BW2
Byte 2
Write register
/BW3
Byte 3
Write register
Row and column
decoders
8/9
8/9
8/9
Byte 2
Write driver
Byte 3
Write driver
8/9
Byte 4
Write register
/BW4
/BWE
Byte 1
Write driver
Byte 4
Write driver
32/36
Memory cell array
1,024 rows
256 × 32 columns
(8,388,608 bits)
256 × 36 columns
(9,437,184 bits)
32/36
Input
register
/GW
Output
buffer
Enable
register
/CE
CE2
/CE2
/G
4
32/36
I/O1 to I/O32
I/OP1 to I/OP4
Power down control
ZZ
Burst Sequence
[µPD4482321, µPD4482361]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
A17 to A2, A1, A0
1st Burst Address
A17 to A2, A1, /A0
2nd Burst Address
A17 to A2, /A1, A0
3rd Burst Address
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
1st Burst Address
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
2nd Burst Address
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
3rd Burst Address
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
Data Sheet M14521EJ3V0DS
9
µPD4482161, 4482181, 4482321, 4482361
Asynchronous Truth Table
Operation
/G
I/O
Read Cycle
L
Dout
Read Cycle
H
High-Z
Write Cycle
×
High-Z, Din
Deselected
×
High-Z
Remark × : don’t care
Synchronous Truth Table
/CE
CE2
/CE2
/AP
/AC
/ADV
/WRITE
CLK
Address
Deselected
Note
Operation
H
×
×
×
L
×
×
L→H
None
Deselected
Note
L
L
×
L
×
×
×
L→H
None
Deselected
Note
L
×
H
L
×
×
×
L→H
None
Deselected
Note
L
L
×
H
L
×
×
L→H
None
Deselected
Note
L
×
H
H
L
×
×
L→H
None
Read Cycle / Begin Burst
L
H
L
L
×
×
×
L→H
External
Read Cycle / Begin Burst
L
H
L
H
L
×
H
L→H
External
Read Cycle / Continue Burst
×
×
×
H
H
L
H
L→H
Next
Read Cycle / Continue Burst
H
×
×
×
H
L
H
L→H
Next
Read Cycle / Suspend Burst
×
×
×
H
H
H
H
L→H
Current
Read Cycle / Suspend Burst
H
×
×
×
H
H
H
L→H
Current
Write Cycle / Begin Burst
L
H
L
H
L
×
L
L→H
External
Write Cycle / Continue Burst
×
×
×
H
H
L
L
L→H
Next
Write Cycle / Continue Burst
H
×
×
×
H
L
L
L→H
Next
Write Cycle / Suspend Burst
×
×
×
H
H
H
L
L→H
Current
Write Cycle / Suspend Burst
H
×
×
×
H
H
L
L→H
Current
Note Deselect status is held until new “Begin Burst” entry.
Remarks 1. × : don’t care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW
or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1 to /BW4 and /GW are HIGH, and /BWE is LOW.
10
Data Sheet M14521EJ3V0DS
µPD4482161, 4482181, 4482321, 4482361
Partial Truth Table for Write Enables
[µPD4482161, µPD4482181]
Operation
/GW
/BWE
/BW1
/BW2
Read Cycle
H
H
×
×
Read Cycle
H
L
H
H
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
H
L
L
H
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
H
L
H
L
Write Cycle / All Bytes
H
L
L
L
Write Cycle / All Bytes
L
×
×
×
/GW
/BWE
/BW1
/BW2
/BW3
/BW4
Read Cycle
H
H
×
×
×
×
Read Cycle
H
L
H
H
H
H
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
H
L
L
H
H
H
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
H
L
H
L
H
H
Write Cycle / Byte 3 (I/O [17:24], I/OP3)
H
L
H
H
L
H
Write Cycle / Byte 4 (I/O [25:32], I/OP4)
H
L
H
H
H
L
Write Cycle / All Bytes
H
L
L
L
L
L
Write Cycle / All Bytes
L
×
×
×
×
×
Remark × : don’t care
[µPD4482321, µPD4482361]
Operation
Remark × : don’t care
ZZ (Sleep) Truth Table
ZZ
Chip Status
≤ 0.2 V
Active
Open
Active
≥ VDD − 0.2 V
Sleep
Data Sheet M14521EJ3V0DS
11
µPD4482161, 4482181, 4482321, 4482361
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Conditions
VDD
-A65, -A75, -A85
MIN.
TYP.
MAX.
Unit
–0.5
+4.0
V
–0.5
+3.0
V
Notes
-A65Y, -A75Y, -A85Y
-C75, -C85
-C75Y, -C85Y
Output supply voltage
VDDQ
–0.5
VDD
V
Input voltage
VIN
–0.5
VDD + 0.5
V
1, 2
Input / Output voltage
VI/O
–0.5
VDDQ + 0.5
V
1, 2
Operating ambient
TA
°C
temperature
-A65, -A75, -A85, -C75, -C85
-A65Y, -A75Y, -A85Y, -C75Y, -C85Y
Storage temperature
Tstg
0
70
–40
+85
–55
+125
°C
Notes 1. –2.0 V (MIN.)(Pulse width : 2 ns)
2. VDDQ + 2.3 V (MAX.)(Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions
Parameter
Symbol
(1/2)
Conditions
-A65, -A75, -A85
Unit
-A65Y, -A75Y, -A85Y
Supply voltage
MIN.
TYP.
MAX.
VDD
3.135
3.3
3.465
V
VDDQ
2.375
2.5
2.9
V
2.5 V LVTTL interface
Output supply voltage
High level input voltage
VIH
Low level input voltage
VIL
1.7
–0.3
Note
VDDQ + 0.3
V
+0.7
V
3.3 V LVTTL interface
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
3.135
VIH
2.0
VIL
–0.3
3.3
Note
3.465
V
VDDQ + 0.3
V
+0.8
V
Note –0.8 V (MIN.)(Pulse width : 2 ns)
Recommended DC Operating Conditions
Parameter
Symbol
(2/2)
Conditions
-C75, -C85
Unit
-C75Y, -C85Y
Supply voltage
Output supply voltage
High level input voltage
Low level input voltage
MIN.
TYP.
MAX.
VDD
2.375
2.5
2.625
V
VDDQ
2.375
2.5
2.625
V
VIH
1.7
VDDQ + 0.3
V
+0.7
V
VIL
–0.3
Note –0.8 V (MIN.)(Pulse width : 2 ns)
12
Data Sheet M14521EJ3V0DS
Note
µPD4482161, 4482181, 4482321, 4482361
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input leakage current
ILI
VIN (except ZZ, MODE) = 0 V to VDD
–2
+2
µA
I/O leakage current
ILO
VI/O = 0 V to VDDQ, Outputs are disabled.
–2
+2
µA
Operating supply current
IDD
Device selected,
-A65
250
mA
Cycle = MAX.
-A65Y
VIN ≤ VIL or VIN ≥ VIH,
-A75, -C75
II/O = 0 mA
-A75Y, -C75Y
Note
225
-A85, -C85
200
-A85Y, -C85Y
IDD1
Suspend cycle, Cycle = MAX.
150
/AC, /AP, /ADV, /GW, /BWEs ≥ VIH
VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA
Standby supply current
ISB
Device deselected, Cycle = 0 MHz
30
mA
VIN ≤ VIL or VIN ≥ VIH, All inputs are static.
ISB1
Device deselected, Cycle = 0 MHz
15
VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V
VI/O ≤ 0.2 V, All inputs are static.
ISB2
Device deselected, Cycle = MAX.
110
VIN ≤ VIL or VIN ≥ VIH
Power down supply current
ISBZZ
ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V
VOH
IOH = –2.0 mA
1.7
IOH = –1.0 mA
2.1
15
mA
2.5 V LVTTL interface
High level output voltage
Low level output voltage
VOL
V
IOL = +2.0 mA
0.7
IOL = +1.0 mA
0.4
V
3.3 V LVTTL interface
High level output voltage
VOH
IOH = –4.0 mA
Low level output voltage
VOL
IOL = +8.0 mA
2.4
V
0.4
V
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
VIN = 0 V
6.0
pF
Input / Output capacitance
CI/O
VI/O = 0 V
8.0
pF
Clock input capacitance
Cclk
Vclk = 0 V
6.0
pF
Remark These parameters are periodically sampled and not 100% tested.
Data Sheet M14521EJ3V0DS
13
µPD4482161, 4482181, 4482321, 4482361
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
2.5 V LVTTL interface
Input waveform (Rise / Fall time ≤ 2.4 ns)
2.4 V
1.2 V
Test points
1.2 V
1.2 V
Test points
1.2 V
1.5 V
Test points
1.5 V
1.5 V
Test points
1.5 V
VSS
Output waveform
3.3 V LVTTL interface
Input waveform (Rise / Fall time ≤ 3.0 ns)
3.0 V
VSS
Output waveform
Output load condition
CL : 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
External load at test
VT = +1.2 V / +1.5 V
50 Ω
ZO = 50 Ω
I/O (Output)
CL
Remark CL includes capacitances of the probe and jig, and stray capacitances.
14
Data Sheet M14521EJ3V0DS
µPD4482161, 4482181, 4482321, 4482361
Read and Write Cycle (2.5 V LVTTL Interface)
Parameter
Symbol
-A65, -A75, -C75
-A85, -C85
-A65Y, -A75Y, -C75Y
-A85Y, -C85Y
(117 MHz)
(100MHz)
Unit Note
Standard
Alias
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TCYC
8.6
–
10.0
–
ns
Clock access time
TKHQV
TCD
–
7.5
–
8.5
ns
Output enable access time
TGLQV
TOE
–
3.5
–
3.5
ns
Clock high to output active
TKHQX1
TDC1
2.5
–
2.5
–
ns
Clock high to output change
TKHQX2
TDC2
2.5
–
2.5
–
ns
TGLQX
TOLZ
0
–
0
–
ns
Output disable to output High-Z TGHQZ
TOHZ
0
3.5
0
3.5
ns
Output enable to output active
Clock high to output High-Z
TKHQZ
TCZ
2.5
5.0
2.5
5.0
ns
Clock high pulse width
TKHKL
TCH
2.5
–
2.5
–
ns
Clock low pulse width
TKLKH
TCL
2.5
–
2.5
–
ns
Setup times Address
TAVKH
TAS
1.5
–
2.0
–
ns
TADSVKH
TSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
0.5
–
0.5
–
ns
Address status
Hold times
Address advance TADVVKH
–
Chip enable
TEVKH
–
Address
TKHAX
TAH
TKHADSX
TSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Address status
Address advance TKHADVX
–
Chip enable
TKHEX
–
Power down entry time
TZZE
TZZE
–
8.6
–
10.0
ns
Power down recovery time
TZZR
TZZR
–
8.6
–
10.0
ns
Data Sheet M14521EJ3V0DS
15
µPD4482161, 4482181, 4482321, 4482361
Read and Write Cycle (3.3 V LVTTL Interface)
Parameter
-A65
-A75
-A85
-A65Y
-A75Y
-A85Y
(133 MHz)
(117 MHz)
(100MHz)
Symbol
Unit Note
Standard
Alias
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TCYC
7.5
–
8.6
–
10.0
–
ns
Clock access time
TKHQV
TCD
–
6.5
–
7.5
–
8.5
ns
Output enable access time
TGLQV
TOE
–
3.5
–
3.5
–
3.5
ns
Clock high to output active
TKHQX1
TDC1
2.5
–
2.5
–
2.5
–
ns
Clock high to output change
TKHQX2
TDC2
2.5
–
2.5
–
2.5
–
ns
TGLQX
TOLZ
0
–
0
–
0
–
ns
Output disable to output High-Z TGHQZ
TOHZ
0
3.5
0
3.5
0
3.5
ns
Output enable to output active
Clock high to output High-Z
TKHQZ
TCZ
2.5
5.0
2.5
5.0
2.5
5.0
ns
Clock high pulse width
TKHKL
TCH
2.5
–
2.5
–
2.5
–
ns
Clock low pulse width
TKLKH
TCL
2.5
–
2.5
–
2.5
–
ns
Setup times Address
TAVKH
TAS
1.5
–
1.5
–
2.0
–
ns
TADSVKH
TSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
0.5
–
0.5
–
0.5
–
ns
Address status
Hold times
Address advance TADVVKH
–
Chip enable
TEVKH
–
Address
TKHAX
TAH
TKHADSX
TSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Address status
Address advance TKHADVX
–
Chip enable
TKHEX
–
Power down entry time
TZZE
TZZE
–
7.5
–
8.6
–
10.0
ns
Power down recovery time
TZZR
TZZR
–
7.5
–
8.6
–
10.0
ns
16
Data Sheet M14521EJ3V0DS
READ CYCLE
TKHKH
CLK
TADSVKH
TKHKL
TKHADSX
TKLKH
/AP
TADSVKH
TKHADSX
/AC
TAVKH
TKHAX
A1
Address
A2
TADVVKH
A3
TKHADVX
TWVKH
TKHWX
TWVKH
TKHWX
/BWE
/BWs
/GW
TEVKH
TKHEX
/CEsNote
/G
High-Z
TGLQV
Data In
TGLQX
High-Z
Data Out
TGHQZ
TKHQX2
High-Z
Q1(A1)
Q1(A2)
TKHQV
Q2(A2)
TKHQZ
Q3(A2)
Q4(A2)
Q1(A2)
Q1(A3)
Note /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Remark Qn(A2) refers to output from address A2. Q1 to Q4 refer to outputs according to burst sequence.
High-Z
17
µPD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
/ADV
18
WRITE CYCLE
TKHKH
CLK
TADSVKH TKHADSX
TKHKL
TKLKH
/AP
TADSVKH TKHADSX
/AC
TAVKH
Address
TKHAX
A1
A2
A3
TKHADVX
TWVKH
/BWENote1
/BWs
TWVKH
/GWNote1
/CEsNote2
TEVKH
TKHWX
TKHWX
TKHEX
/G
Data In
High-Z
TDVKH
D1(A1)
TGHQZ
Data Out
D1(A2)
TKHDX
D2(A2)
D2(A2)
D3(A2)
D4(A2)
D1(A3)
D2(A3)
D3(A3)
High-Z
Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
µPD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
TADVVKH
/ADV
READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TADSVKH TKHADSX
/AP
TADSVKH TKHADSX
/AC
TAVKH
TKHAX
A1
Address
A2
A3
TADVVKH
TKHADVX
TWVKH
TKHWX
TWVKH
TKHWX
/BWENote1
/BWs
/GWNote1
TEVKH
TKHEX
/CEsNote2
/G
High-Z
Data In
TGHQZ
TKHQV
High-Z TKHQX1
Data Out
Q1(A1)
TDVKH
TKHDX
High-Z
D1(A2)
High-Z
TGLQX
Q1(A3)
High-Z
Q2(A3)
Q3(A3)
Q4(A3)
Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
19
µPD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
/ADV
20
SINGLE READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TADSVKH TKHADSX
/AC
TAVKH TKHAX
Address
A5
A4
A3
A2
A1
A7
A6
A8
A9
TWVKH TKHWX
/BWE Note1
/BWs
TWVKH TKHWX
TEVKH
TKHEX
/CEs Note2
/G
TDVKH TKHDX
High-Z
Data In
Data Out
High-Z
D1(A5)
TGLQV
TGLQX
Q1(A1)
TGHQZ
Q1(A2)
Q1(A3)
Q1(A4)
D1(A6)
D1(A7)
High-Z
TKHQV
High-Z
TKHQZ
Note3
Q1(A8)
Q1(A9)
Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Outputs
are disabled within one clock cycle after deselect.
3.
Remark
/AP is HIGH and /ADV is don't care.
µPD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
/GW Note1
POWER DOWN (ZZ) CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A1
A2
/BWE
/BWs
/GW
/CEs
/G
High-Z
Data Out
High-Z
Q1(A1)
TZZE
Q1(A2)
TZZR
ZZ
Power Down (ISBZZ) State
Q2(A2)
21
µPD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
/ADV
22
STOP CLOCK CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A2
A1
/BWE
/BWs
/GW
/CE
/G
High-Z
High-Z
Data In
Data Out
High-Z
High-Z
Q1(A1)
Power Down State (ISB1)Note
Note VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, VI/O ≤ 0.2 V
Q1(A2)
Q2(A2)
µPD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
/ADV
µPD4482161, 4482181, 4482321, 4482361
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
22.0±0.2
B
20.0±0.2
C
14.0±0.2
D
16.0±0.2
F
0.825
G
0.575
H
0.32 +0.08
−0.07
I
J
0.13
0.65 (T.P.)
K
1.0±0.2
L
0.5±0.2
M
0.17 +0.06
−0.05
N
0.10
P
1.4
Q
0.125±0.075
R
3° +7°
−3°
S
1.7 MAX.
S100GF-65-8ET-1
Data Sheet M14521EJ3V0DS
23
µPD4482161, 4482181, 4482321, 4482361
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD4482161, 4482181, 4482321 and 4482361.
Types of Surface Mount Devices
µPD4482161GF : 100-pin PLASTIC LQFP (14 x 20)
µPD4482181GF : 100-pin PLASTIC LQFP (14 x 20)
µPD4482321GF : 100-pin PLASTIC LQFP (14 x 20)
µPD4482361GF : 100-pin PLASTIC LQFP (14 x 20)
24
Data Sheet M14521EJ3V0DS
µPD4482161, 4482181, 4482321, 4482361
Revision History
Edition/
Date
3rd edition/
Page
Type of
This
Previous
edition
edition
Throughout
Throughout
Dec. 2002
Location
Description
(Previous edition → This edition)
revision
Modification
−
Preliminary Data Sheet → Data Sheet
Addition
−
Extended operating temperature products
(TA = −40 to +85 °C)
p.20
−
Addition
Timing Chart
Data Sheet M14521EJ3V0DS
SINGLE READ / WRITE CYCLE
25
µPD4482161, 4482181, 4482321, 4482361
[MEMO]
26
Data Sheet M14521EJ3V0DS
µPD4482161, 4482181, 4482321, 4482361
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M14521EJ3V0DS
27
µPD4482161, 4482181, 4482321, 4482361
• The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
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appear in this document.
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1