DATA SHEET MOS INTEGRATED CIRCUIT µPD70325 V25+TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER The µPD70325 (V25+) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA controller, interrupt controller, etc. are all integrated. The µPD70325 is software compatible with the 16/8-bit singlechip microcontroller µPD70320 (V25TM). The V25+ greatly improves the DMA responsivity and transfer rate compared to the V25. FEATURES • • • • • Software compatible with V25 Software compatible with µPD70108/70116 (in native mode) (some instructions added) Internal 16-bit architecture and external 8-bit data bus 3-stage pipeline method Minimum instruction cycle : 250 ns/8 MHz (external 16 MHz) : 200 ns/10 MHz (external 20 MHz) • • • • • • Memory space 1 Mbyte On-chip RAM : 256 words × 8 bits Register bank (memory mapped method) : 8 banks Input port (port T) with comparator : 8 bits I/O lines (input port : 4 bits, input/output ports : 20 bits) Serial interface : 2 channels • Internal dedicated baud rate generator • Asynchronous mode and I/O interface mode • Interrupt controller • Programmable priority (8 levels) • 3 types of interrupt response method Vectored interrupt function, register bank switching function, macro service function • • DRAM and pseudo SRAM refreshing function DMA controller : 2 channels • 4 types of DMA transfer mode • Transfer rate Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release mode) Maximum 2 Mbytes/second (when stop control is executed by DMARQ pin in demand release mode, or burst mode) • Address pointer (linear) : 20 bits • Terminal counter : 16 bits • • • • • 16-bit timer : 2 channels Time base counter (20 bits) : 1 channel On-chip clock generator Programmable wait function Standby function (STOP, HALT) The information in this document is subject to change without notice. Document No. U12850EJ7V0DS00 (7th edition) Date Published November 1997 N Printed in Japan The mark shows major revised points. © 1996 1995 µPD70325 ORDERING INFORMATION Part Number Package External Clock (MHz) µPD70325GJ-8-5BG 94-pin plastic QFP (20 × 20 mm) 16 µPD70325GJ-10-5BG 94-pin plastic QFP (20 × 20 mm) 20 µPD70325L-8 84-pin plastic QFJ (1150 × 1150 mil) 16 µPD70325L-10 84-pin plastic QFJ (1150 × 1150 mil) 20 2 µPD70325 Comparison between V25 and V25+ V25 V35TM V25+ V35+TM µPD70320 µPD70330 µPD70325 µPD70335 Transfer processing method Depends on microprogram Depends on dedicated hardware Maximum transfer rate (8-MHz operation) 0.6 Mbytes/second 0.8 Mbytes/second Sampling timing of DMA request Between instruction execution cycles Between bus cycles DMA service channel In on-chip RAM area In special function register 4 Mbytes/second 5.3 Mbytes/second Specification method of transfer address Segment method Linear method Execution format in single-step mode 1 DMA transfer/1 instruction execution 1 DMA transfer/1 bus cycle DMA Interrupt request during DMA transfer Accepts only NMI function (demand release mode) Not accepted Number of necessary waits when stop is controlled by DMARQ (demand release mode) Not necessary 2 waits Transfer processing units Byte/word TC (terminal counter) setting value Number of times of DMA transfer Byte/word Byte Byte/word (Number of times of DMA transfer) – 1 Generation timing of terminal counter TC = 0 TC = FFFFH TC output low-level width Fixed Expanded by wait insertion Transmit clock output in asynchronous mode (channel 0) Not available Available (SCK0 pin) Yes Serial status register No In serial status register Transmit buffer empty flag No In serial status register All sent flag No In serial status register No Yes Serial error register Serial interface Receive buffer full flag Interrupt Interrupt source register function External data bus 8 bits Maximum operating frequency 8 MHz 16 bits 8 bits 16 bits 10 MHz 3 µPD70325 PIN CONFIGURATION (Top View) 94-Pin Plastic QFP µPD70325GJ-8-5BG P06 P07/CLKOUT D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 NC A11 µPD70325GJ-10-5BG 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 P05 A12 1 70 NC NC 2 69 IC A13 3 68 P04 A14 4 67 P03 A15 5 66 P02 A16 6 65 P01 A17 7 64 P00 A18 8 63 EA A19 9 62 MREQ RxD0 10 61 IOSTB GND 11 60 MSTB CTS0 12 59 R/W TxD0 13 58 REFRQ RxD1 14 57 RESET CTS1 15 56 VDD TxD1 16 55 VDD P20/DMARQ0 17 54 X2 IC 18 53 X1 VDD 19 52 GND VDD 20 51 GND P21/DMAAK0 21 50 NC NC 22 49 NC P22/TC0 23 48 VTH Remarks 1. NC : Non-Connection 2. IC : Internally Connected Cautions 1. Fix IC pin individually to high level via a pull-up resistor externally. 2. Fix EA pin to low level. 4 IC PT7 PT6 NC PT5 PT4 PT3 PT2 PT1 PT0 P17/READY P16/SCK0 P15/TOUT P14/INT/POLL P13/INTP2/INTAK P12/INTP1 P11/INTP0 NMI (P10) P27/HLDRQ P26/HLDAK P25/TC1 P24/DMAAK1 IC P23/DMARQ1 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 µPD70325 84-Pin Plastic QFJ µPD70325L-8 IC 1 84 83 82 81 80 79 78 77 76 75 VTH IOSTB 2 GND MREQ 3 X1 EA 4 X2 P00 5 VDD P01 RESET P02 6 R/W P03 7 MSTB P04 8 P05 11 10 9 P06 IC REFRQ µPD70325L-10 P07/CLKOUT 12 74 PT7 D0 13 73 PT6 D1 14 72 PT5 D2 15 71 PT4 D3 16 70 PT3 D4 17 69 PT2 D5 18 68 PT1 D6 19 67 PT0 D7 20 66 P17/READY A0 21 65 P16/SCK0 A1 22 64 P15/TOUT A2 23 63 P14/INT/POLL A3 24 62 P13/INTP2/INTAK A4 25 61 P12/INTP1 A5 26 60 P11/INTP0 A6 27 59 NMI (P10) A7 28 58 P27/HLDRQ A8 29 57 P26/HLDAK A9 30 56 P25/TC1 A10 31 55 P24/DMAAK1 A11 32 54 P23/DMARQ1 IC P22/TC0 P21/DMAAK0 VDD IC P20/DMARQ0 TxD1 CTS1 RxD1 TxD0 CTS0 GND A19 RxD0 A18 A17 A16 A15 A14 A13 A12 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Remark IC: Internally Connected Cautions 1. Fix IC pin individually to high level via a pull-up resistor externally. 2 Fix EA pin to low level. 5 LC etc. ALU PFP INC RESET HLDAK/P26 PSW TA TB TC HLDRQ/P27 Note SERIAL INTERFACE INTERNAL RAM 256 byte • GR • MACRO SERVICE CHANNEL BAUD RATE GENERATOR INTERNAL ROM 8 Kbyte (reserved) BUS CONTROL LOGIC PC TxD0 RxD0 P16/SCK0 CTS0 TxD1 RxD1 CTS1 ADM STAGING LATCH STAGING LATCH PROGRAMMABLE DMA CONTROLLER READY/P17 INTERNAL BLOCK DIAGRAM 6 P20/DMARQ0 P21/DMAAK0 P22/TC0 P23/DMARQ1 P24/DMAAK1 P25/TC1 A0 to A19 MREQ MSTB R/W IOSTB POLL/INT/P14 NMI (P10) P11/INTP0 P12/INTP1 P13/INTP2/INTAK P14/INT/POLL PROGRAMMABLE INTERRUPT CONTROLLER INSTRUCTION DECODER MICRO SEQUENSER MICRO ROM QUEUE (6 byte) EA D0 to D7 16-BIT TIMER TIME BASE COUNTER PORT with COMPARATOR PORT X1 CG X2 VDD TOUT/P15 REFRQ CLKOUT/P07 P0 P1 P2 PT0 to 7 VTH µPD70325 Note The internal ROM of 8 Kbytes is reserved for specific use such as testing and not user-accessible. GND µPD70325 CONTENTS 1. PIN FUNCTIONS .................................................................................................................................. 8 1.1 Port Pins ....................................................................................................................................................... 8 1.2 Non-port Pins ............................................................................................................................................... 9 2. INSTRUCTION SETS ......................................................................................................................... 10 2.1 Comparison between µPD70108 and 70116 ........................................................................................... 10 2.2 Instruction Set Operation ......................................................................................................................... 12 2.3 Instruction Set Table ................................................................................................................................. 16 2.4 Number of Clocks Table ........................................................................................................................... 38 3. ELECTRICAL SPECIFICATIONS ...................................................................................................... 49 4. PACKAGE DRAWINGS ..................................................................................................................... 74 5. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 76 7 µPD70325 1. 1.1 PIN FUNCTIONS Port Pins Pin Name P00 to P06 P07/CLKOUT NMI (P10) Input/Output Port Function Control Function Input & output 8-bit input/output ports, each to — Input & output/output Input P11/INTP0 P14/POLL/INT System clock output Used as non-maskable interrupt request input (input port) — Used as both external interrupt request input and input port P12/INTP1 P13/INTP2/INTAK be specified bit-by-bit Input/input/output Input & output/input/input INT acknowledge signal output Used as both specifiable input/ External interrupt request input output port and POLL input P15/TOUT Input & output/output P16/SCK0 P17/READY Input & output/input P20/DMARQ0 Input & output/input P21/DMAAK0 Input & output/input Input/output port specifiable bit-by-bit Timer output Serial clock output READY input 8-bit input/output port specifiable DMA request input (CH0) bit-by-bit DMA acknowledge output (CH0) P22/TC0 DMA end output (CH0) P23/DMARQ1 Input & output/input DMA request input (CH1) P24/DMAAK1 Input & output/output DMA acknowledge output (CH1) P25/TC1 DMA end output (CH1) P26/HLDAK Input & output/output HOLD acknowledge output P27/HLDRQ Input & output/input HOLD input PT0 to PT7 Input 8-bit input port with comparator — Remark All port pins become input ports after reset is released. When using P13/INTP2/INTAK as a INTAK pin, be sure to pull up the pin to avoid a malfunction of external interrupt controller after reset is released. 8 µPD70325 1.2 Non-port Pins Pin Name TxD0 Input/Output Output Function Serial data output TxD1 RxD0 Input Serial data input RxD1 CTS0 CTS1 REFRQ VTH Input & output Input Output Input CTS input in asynchronous mode, receive clock input/output in I/O interface mode CTS input DRAM refresh pulse output Comparator reference voltage input RESET Reset signal input EA Fix to low level X1 Used to connect crystal resonator for oscillating system clock. External clock is entered by entering reverse phase clock to both X1 and X2 pins. X2 D0 to D7 Input & output A0 to A19 Output 8-bit data bus 20-bit address output MREQ Output used to indicate that memory bus cycle has been started MSTB Memory read/memory write strobe output R/ W Read cycle/write cycle ID signal output IOSTB I/O read/ I/O write strobe output VDD Positive power supply pins (all pins should be connected) GND GND pins (all pins should be connected) IC Internally connected (fix to high level via a pull-up resistor externally) 9 µPD70325 2. INSTRUCTION SETS The µPD70325 instruction sets are compatible with those of µPD70320. 2.1 Comparison between µPD70108 and 70116 The µPD70325 instruction sets are upward-compatible with those of µPD70108/70116 in native mode. The following instructions are newly added to the µPD70108/70116. (1) Conditional branch instruction • BTCLR ······· Bit test instruction used for special function registers If, when this BTCLR is executed, the target special function register bit status is “1”, the bit is reset (0) and the program is branched to short-label described in the operand. If the target bit status is “0”, the program is moved to the next instruction. PSW is not changed in this instruction. (Descriptive format) Operand Mnemonic Special Function Register Address Special Function Register Bit Branch Address sfr imm3 short-label BTCLR (2) Interrupt instructions • RETRBI ······ Return instruction used for register banks This instruction is used to return the program from the interrupt service routine in which the register bank switching function is used. It cannot be used for returning from vectored interrupt servicing. (Descriptive format) Mnemonic Operand RETRBI None • FINT ··········· This instruction is used to report the interrupt controller that interrupt servicing has ended. If an interrupt other than NMI, INT, and software interrupt is used, this instruction must be executed prior to the instruction for returning from interrupt servicing. It should not be used for NMI, INT and software interrupts. (Descriptive format) Mnemonic Operand FINT None (3) CPU instruction • STOP ········· Instruction for transition to STOP state (Descriptive format) 10 Mnemonic Operand STOP None µPD70325 (4) Register bank switch instructions • BRKCS ······ Used to switch register banks A register bank is switched to the register bank indicated by the lower 3 bits in the 16-bit register described in the operand. The program is also branched with this instruction to the address obtained from the PS stored in advance in the new register bank and the vector PC. The RETRBI instruction is used to return the program from the new register bank. (Descriptive format) Mnemonic Operand BRKCS reg16 • TSKSW ······ Used to switch register banks Just like the BRKCS instruction, this instruction is also executed to select a register bank. The program is branched to the address obtained from the PS stored in advance in the new register bank and the address obtained from the PC save area. (Descriptive format) Mnemonic Operand TSKSW reg16 (5) Data transfer instructions • MOVSPA ··· Used to transfer SS and SP values This instruction is executed to transfer both SS and SP values before the register bank is switched to SS and SP of the current (post-switching) register bank. (Descriptive format) Mnemonic Operand MOVSPA None • MOVSPB ··· Used to transfer SS and SP values This instruction is executed to transfer the SS and SP values of the current (pre-switching) register bank to the SS and SP of the new register bank indicated by the lower 3 bits in the 16bit register described in the operand. (Descriptive format) Mnemonic Operand MOVSPB reg16 Some µPD70108/ 70116 instructions should be much cared as shown below when used for the µPD70325. • I/O instruction, primitive I/O instruction If PSW IBRK flag is reset (0), an interrupt is generated without executing this instruction. Be sure to set (1) the IBRK flag when using the I/O instruction. • FPO instruction An interrupt is generated without executing this instruction. 11 µPD70325 2.2 Instruction Set Operation Table 2-1. Operand Identifier Identifier Description reg, reg’ 8-/16-bit general register reg8, reg8’ 8-bit general register reg16, reg16’ 16-bit general register dmem 8-/16-bit memory location mem 8-/16-bit memory location mem8 8-bit memory location mem16 16-bit memory location mem32 32-bit memory location sfr 8-bit special function register location imm Constant within 0 to FFFFH imm3 Constant within 0 to 7 imm4 Constant within 0 to FH imm8 Constant within 0 to FFH imm16 Constant within 0 to FFFFH acc Register AW or AL sreg Segment register src-table 256-byte conversion table name src-block Register IX-addressed block name dst-block Register IY-addressed block name near-proc Procedure in the current program segment far-proc Procedure in another program segment near-label Label in the current program segment short-label Label within end of instruction to –128 to +127 bytes far-label Label in another program segment memptr16 Word including location offset in the current program segment to which control is to be passed memptr32 Double-word including location offset in another program segment to which control is to be passed and segment base address regptr16 16-bit general register including location offset in another program segment to which control is to be passed pop-value Number of bytes to be abandoned from stack (0 to 64K, normally even number) fp-op Immediate value to judge instruction code of external floating point operation chip R Register set 12 µPD70325 Table 2-2. Operation Code Identifier Identifier Description W Byte/word specification bit (0: byte, 1: word). However, when s = 1, the sign extended byte data should be 16-bit operand even when W is 1. reg, reg’ Register field (000 to 111) mem Memory field (000 to 111) mod Mode field (00 to 10) s Sign extension specification bit (0: Sign is not extended, 1: Sign is extended) X, XXX, YYY, ZZZ Data used to judge instruction code of external floating-point operation chip Table 2-3. Operation Identifier (1/2) Identifier Description AW Accumulator (16 bits) AH Accumulator (upper byte) AL Accumulator (lower byte) BW Register BW (16 bits) CW Register CW (16 bits) CL Register CW (lower byte) DW Register DW (16 bits) SP Stack pointer (16 bits) PC Program counter (16 bits) PSW Program status word (16 bits) IX Index register (source) (16 bits) IY Index register (destination) (16 bits) PS Program segment register (16 bits) DS1 Data segment 1 register (16 bits) DS0 Data segment 0 register (16 bits) SS Stack segment register (16 bits) AC Auxiliary carry flag CY Carry flag P Parity flag S Sign flag Z Zero flag DIR Direction flag IE Interrupt enable flag V Overflow flag BRK Break flag (···) Contents in memory shown in ( ) disp Displacement (8/16 bits) ext-disp8 16 bits obtained by extending sign of 8-bit displacement 13 µPD70325 Table 2-3. Operation Identifier (2/2) Identifier Description temp Temporary register (8/16/32 bits) tmpcy Temporary carry flag (1 bit) seg Immediate segment data (16 bits) offset Immediate offset data (16 bits) ← Transfer direction + Addition – Subtraction × Multiplication ÷ Division % Modulo ∧ ∨ ∨ AND OR Exclusive OR ××H 2-digit hexadecimal number ××××H 4-digit hexadecimal number Table 2-4. Flag Operation Identifier Identifier Description (Blank) No change 0 Cleared to 0 1 × Set to 1 U Not defined R The previously saved value is restored. Set or cleared according to the result Table 2-5. Memory Addressing mem mod 0 1 1 0 0 0 0 BW + IX BW + IX + disp 8 BW + IX + disp 16 0 0 1 BW + IY BW + IY + disp 8 BW + IY + disp 16 0 1 0 BP + IX BP + IX + disp 8 BP + IX + disp 16 0 1 1 BP + IY BP + IY + disp 8 BP + IY + disp 16 1 0 0 IX IX + disp 8 IX + disp 16 1 0 1 IY IY + disp 8 IY + disp 16 1 1 0 1 1 1 14 0 0 DIRECT ADDRESS BW BP + disp 8 BP + disp 16 BW + disp 8 BW + disp 16 µPD70325 Table 2-6. 8/16-Bit General Register Selection reg, reg’ W=0 W=1 000 AL AW 001 CL CW 010 DL DW 011 BL BW 100 AH SP 101 CH BP 110 DH IX 111 BH IY Table 2-7. Segment Register Selection sreg 00 DS1 01 PS 10 SS 11 DS0 15 MOV Operand Operation Bytes AC CY V 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg,reg’ 1 0 0 0 1 0 1 W 1 1 reg reg’ mem,reg 1 0 0 0 1 0 0 W mod reg mem 2 to 4 (mem) ← reg reg,mem 1 0 0 0 1 0 1 W mod reg mem 2 to 4 reg ← (mem) mem,imm 1 1 0 0 0 1 1 W mod 0 0 0 mem 3 to 6 (mem) ← imm reg,imm 1 0 1 1 W reg 2 to 3 reg ← imm acc,dmem 1 0 1 0 0 0 0 W 3 dmem,acc 1 0 1 0 0 0 1 W 3 sreg,reg16 1 0 0 0 1 1 1 0 1 1 0 sreg reg sreg,mem16 1 0 0 0 1 1 1 0 mod 0 sreg mem reg16,sreg 1 0 0 0 1 1 0 0 1 1 0 sreg reg mem16,sreg 1 0 0 0 1 1 0 0 mod 0 sreg mem 2 to 4 1 1 0 0 0 1 0 1 mod reg mem 2 to 4 1 1 0 0 0 1 0 0 mod reg mem 2 to 4 DS0,reg16, mem32 DS1,reg16, mem32 2 2 2 to 4 2 sreg ← reg16 sreg : SS, DS0, DS1 sreg ← (mem16) sreg : SS, DS0, DS1 × reg16 ← (mem32) DS0 ← (mem32 + 2) reg16 ← (mem32) DS1 ← (mem32 + 2) PSW,AH 1 0 0 1 1 1 1 0 1 S, Z, F1, AC, F0, P, IBRK, CY ← AH LDEA reg16,mem16 1 0 0 0 1 1 0 1 TRANS src-table 1 1 0 1 0 1 1 1 XCH reg,reg’ 1 0 0 0 0 1 1 W 1 1 reg reg’ 1 0 0 0 0 1 1 W mod reg mem 2 to 4 reg16 ← mem16 1 AL ← (BW + AL) 2 reg ↔ reg’ 2 to 4 (mem) ↔ reg 1 AW ↔ reg16 0 0 0 0 1 1 1 1 0 0 1 0 0 1 0 1 2 New register bank SS and SP ← old register bank SS and SP MOVSPB Note reg16 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 1 3 SS and SP of reg16-indicated new register bank ← old register bank SS and SP × × µPD70325 MOVSPA Note Note These instructions are newly added to the µPD70108/70116. × (mem16) ← sreg AH ← S, Z, F1, AC, F0, P, IBRK, CY 1 1 1 1 1 reg × reg16 ← sreg 1 1 0 0 1 0 reg Z When W = 0, AL ← (dmem) When W = 1, AH ← (dmem + 1), AL ← (dmem) When W = 0, (dmem) ← AL When W = 1, (dmem + 1) ← AH, (dmem) ← AL 1 0 0 1 1 1 1 1 mem,reg reg,mem AW,reg16 reg16,AW S reg ← reg’ AH,PSW mod reg mem P Instruction Set Table Data transfer Mnemonic 2.3 16 Flags Operation Code Group Flags Operation Code Group Mnemonic Operand Bytes 7 6 5 4 3 2 1 0 Repeat prefix Operation AC CY V 7 6 5 4 3 2 1 0 REPC 0 1 1 0 0 1 0 1 1 REPNC 0 1 1 0 0 1 0 0 1 REP 1 1 1 1 0 0 1 1 1 Executes the primitive block transfer instruction in the continued byte while CW ≠ 0, and decrements CW by one. If any interruption is held at this time, it is processed. The program exits the loop when the primitive block transfer instruction is CMPBK or CMPM, and when Z ≠ 1. 1 1 1 1 0 0 1 0 1 Same as above. The program exits the loop when Z ≠ 0. 1 0 1 0 0 1 0 W 1 1 0 1 0 0 1 1 W 1 REPE REPZ REPNE P S Z Executes the primitive block transfer instruction in the continued byte while CW ≠ 0, and decrements CW by one. If any interruption is held at this time, it is processed. The program exits the loop when CY ≠ 1. Same as above. The program exits the loop when CY ≠ 0. REPNZ Primitive block transfer MOVBK dst-block, src-block CMPBK src-block, dst-block CMPM dst-block 1 0 1 0 1 1 1 W 1 LDM src-block 1 0 1 0 1 1 0 W 1 STM dst-block 1 0 1 0 1 0 1 W 1 When W = 0, (IY) ← (IX) DIR = 0: IX ← IX + 1, IY ← IY + 1 DIR = 1: IX ← IX – 1, IY ← IY – 1 When W = 1, (IY + 1, IY) ← (IX + 1, IX) DIR = 0: IX ← IX + 2, IY ← IY + 2 DIR = 1: IX ← IX – 2, IY ← IY – 2 When W = 0, (IX) – (IY) DIR = 0: IX ← IX + 1, IY ← IY + 1 DIR = 1: IX ← IX – 1, IY ← IY – 1 When W = 1, (IX + 1, IX) – (IY + 1, IY) DIR = 0: IX ← IX + 2, IY ← IY + 2 DIR = 1: IX ← IX – 2, IY ← IY – 2 When W = 0, AL – (IY) DIR = 0: IY ← IY + 1; DIR = 1: IY ← IY – 1 When W = 1, AW – (IY + 1, IY) DIR = 0: IY ← IY + 2; DIR = 1: IY ← IY – 2 When W = 0, AL ← (IX) DIR = 0: IX ← IX + 1; DIR = 1: IX ← IX – 1 When W = 1, AW ← (IX + 1, IX) DIR = 0: IX + 2; DIR = 1: IX ← IX – 2 When W = 0, (IY) ← AL DIR = 0: IY ← IY + 1; DIR = 1: IY ← IY – 1 When W = 1, (IY + 1, IY) ← AW DIR = 0: IY ← IY + 2; DIR = 1: IY ← IY – 2 × × × × × × × × × × × × µPD70325 17 18 Flags Operation Code Group Bit field operation Mnemonic Operand reg8,reg8’ INS 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 3 16-bit field ← AW 0 0 1 1 1 0 0 1 4 16-bit field ← AW 0 0 1 1 0 0 1 1 3 AW ← 16-bit field 0 0 1 1 1 0 1 1 4 AW ← 16-bit field reg’ reg8,reg8’ reg8,imm4 reg’ I/O IN OUT Primitive I/O Note Note Z reg 0 0 0 0 1 1 1 1 1 1 0 0 0 S reg 0 0 0 0 1 1 1 1 1 1 P reg 0 0 0 0 1 1 1 1 1 1 0 0 0 EXT AC CY V 7 6 5 4 3 2 1 0 1 1 reg8,imm4 Operation Bytes reg acc,imm8 1 1 1 0 0 1 0 W 2 acc,DW 1 1 1 0 1 1 0 W 1 imm8,acc 1 1 1 0 0 1 1 W 2 DW,acc 1 1 1 0 1 1 1 W 1 INM Note dst-block,DW 0 1 1 0 1 1 0 W 1 OUTM Note DW,src-block 0 1 1 0 1 1 1 W 1 When W = 0, AL ← (imm8) When W = 1, AH ← (imm8 + 1), AL ← (imm8) When W = 0, AL ← (DW) When W = 1, AH ← (DW + 1), AL ← (DW) When W = 0, (imm8) ← AL When W = 1, (imm8 + 1) ← AH, (imm8) ← AL When W = 0, (DW) ← AL When W = 1, (DW + 1) ← AH, (DW) ← AL When W = 0, (IY) ← (DW) DIR = 0: IY ← IY + 1; DIR = 1: IY ← IY – 1 When W = 1, (IY + 1, IY) ← (DW + 1, DW) DIR = 0: IY ← IY + 2; DIR = 1: IY ← IY – 2 When W = 0, (DW) ← (IX) DIR = 0: IX ← IX + 1; DIR = 1: IX ← IX – 1 When W = 1, (DW + 1, DW) ← (IX + 1, IX) DIR = 0: IX ← IX + 2; DIR = 1: IX ← IX – 2 Note When IBRK = 0, a software interrupt is generated automatically and the instruction is not executed. µPD70325 Flags Operation Code Group Addition/ subtraction Mnemonic ADD ADDC SUB SUBC Operand Operation Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg,reg’ 0 0 0 0 0 0 1 W 1 1 reg mem,reg 0 0 0 0 0 0 0 W mod reg mem reg,mem 0 0 0 0 0 0 1 W reg,imm AC CY V P S Z reg ← reg + reg’ × × × × × × 2 to 4 (mem) ← (mem) + reg × × × × × × mod reg mem 2 to 4 reg ← reg + (mem) × × × × × × 1 0 0 0 0 0 s W 1 1 0 0 0 3 to 4 reg ← reg + imm × × × × × × mem,imm 1 0 0 0 0 0 s W mod 0 0 0 mem 3 to 6 (mem) ← (mem) + imm × × × × × × acc,imm 0 0 0 0 0 1 0 W 2 to 3 When W = 0, AL ← AL + imm When W = 1, AW ← AW + imm × × × × × × reg,reg’ 0 0 0 1 0 0 1 W 1 1 reg ← reg + reg’ + CY × × × × × × mem,reg 0 0 0 1 0 0 0 W mod reg mem 2 to 4 (mem) ← (mem) + reg + CY × × × × × × reg,mem 0 0 0 1 0 0 1 W mod reg mem 2 to 4 reg ← reg + (mem) + CY × × × × × × reg,imm 1 0 0 0 0 0 s W 1 1 0 1 0 reg 3 to 4 reg ← reg + imm + CY × × × × × × mem,imm 1 0 0 0 0 0 s W mod 0 1 0 mem 3 to 6 (mem) ← (mem) + imm + CY × × × × × × acc,imm 0 0 0 1 0 1 0 W 2 to 3 When W = 0, AL ← AL + imm + CY When W = 1, AW ← AW + imm + CY × × × × × × reg,reg’ 0 0 1 0 1 0 1 W 1 1 reg reg’ reg ← reg – reg’ × × × × × × mem,reg 0 0 1 0 1 0 0 W mod reg mem 2 to 4 (mem) ← (mem) – reg × × × × × × reg,mem 0 0 1 0 1 0 1 W mod reg mem 2 to 4 reg ← reg – (mem) × × × × × × reg,imm 1 0 0 0 0 0 s W 1 1 1 0 1 reg 3 to 4 reg ← reg – imm × × × × × × mem,imm 1 0 0 0 0 0 s W mod 1 0 1 mem 3 to 6 (mem) ← (mem) – imm × × × × × × 2 to 3 When W = 0, AL ← AL – imm When W = 1, AW ← AW – imm × × × × × × reg ← reg – reg’ – CY × × × × × × reg reg’ reg reg’ 2 2 2 0 0 1 0 1 1 0 W reg,reg’ 0 0 0 1 1 0 1 W 1 1 mem,reg 0 0 0 1 1 0 0 W mod reg mem 2 to 4 (mem) ← (mem) – reg – CY × × × × × × reg,mem 0 0 0 1 1 0 1 W mod reg mem 2 to 4 reg ← reg – (mem) – CY × × × × × × reg,imm 1 0 0 0 0 0 s W 1 1 0 1 1 reg 3 to 4 reg ← reg – imm – CY × × × × × × mem,imm 1 0 0 0 0 0 s W mod 0 1 1 mem 3 to 6 (mem) ← (mem) – imm – CY × × × × × × 2 to 3 When W = 0, AL ← AL – imm – CY When W = 1, AW ← AW – imm – CY × × × × × × acc,imm 0 0 0 1 1 1 0 W reg reg’ 2 µPD70325 19 acc,imm 20 Flags Operation Code Group BCD operation Mnemonic Operand Operation Bytes AC CY V S Z U U U × × U U U × × U U U × 7 6 5 4 3 2 1 0 ADD4S 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 2 dst BCD string ← dst BCD string + src BCD string Note U × SUB4S 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 2 dst BCD string ← dst BCD string – src BCD string Note U CMP4S 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 2 dst BCD string – src BCD string Note U 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 3 ROL4 reg8 AL L 1 1 0 0 0 mem8 reg 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 3 to 5 AL L mod 0 0 0 mem ROR4 reg8 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 3 AL L 1 1 0 0 0 reg mem8 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 3 to 5 AL L mod 0 0 0 mem Increment/ decrement P 7 6 5 4 3 2 1 0 INC DEC reg8 1 1 1 1 1 1 1 0 1 1 0 0 0 mem 1 1 1 1 1 1 1 W mod 0 0 0 mem reg16 0 1 0 0 0 reg reg8 1 1 1 1 1 1 1 0 1 1 0 0 1 mem 1 1 1 1 1 1 1 W mod 0 0 1 mem reg16 0 1 0 0 1 reg reg reg reg Upper Lower Byte Byte mem Upper Lower Byte Byte reg Upper Lower Byte Byte mem Upper Lower Byte Byte reg8 ← reg8 + 1 × × × × × (mem) ← (mem) + 1 × × × × × 1 reg16 ← reg16 + 1 × × × × × 2 reg8 ← reg8 – 1 × × × × × (mem) ← (mem) – 1 × × × × × reg16 ← reg16 – 1 × × × × × 2 2 to 4 2 to 4 1 Note The number of BCD digits is given in the CL register. The value can be set within 1 to 254. µPD70325 Flags Operation Code Group Multiplication Mnemonic MULU reg8 mem8 reg16 mem16 MUL reg8 mem8 reg16 mem16 Operation Bytes Operand 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1 1 1 0 1 1 0 1 1 1 0 0 reg 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 reg16, mem16, imm8 0 1 1 0 1 0 1 1 reg16, (reg16’,) Note imm16 0 1 1 0 1 0 0 1 reg16, mem16, imm16 0 1 1 0 1 0 0 1 1 1 1 0 0 reg mod 1 0 0 mem 1 1 1 0 1 reg mod 1 0 1 mem 1 1 1 0 1 reg mod 1 0 1 mem 1 1 reg reg’ mod reg mem 1 1 reg reg’ mod reg mem 2 to 4 2 2 to 4 2 2 to 4 2 2 to 4 3 3 to 5 4 4 to 6 Note The 2nd operand is omissible. If omitted, the 1st operand is assumed. P S Z AW ← AL × reg8 AH = 0: CY ← 0, V ← 0 AH ≠ 0: CY ← 1, V ← 1 U × × U U U AW ← AL × (mem8) AH = 0: CY ← 0, V ← 0 AH ≠ 0: CY ← 1, V ← 1 U × × U U U DW, AW ← AW × reg16 DW = 0: CY ← 0, V ← 0 DW = 1: CY ← 1, V ← 1 U × × U U U DW, AW ← AW × (mem16) DW = 0: CY ← 0, V ← 0 DW = 1: CY ← 1, V ← 1 U × × U U U AW ← AL × reg8 Extension of AH = AL sign: CY ← 0, V ← 0 Extension of AH ≠ AL sign: CY ← 1, V ← 1 U × × U U U AW ← AL × (mem8) Extension of AH = AL sign: CY ← 0, V ← 0 Extension of AH ≠ AL sign: CY ← 1, V ← 1 U × × U U U DW, AW ← AW × reg16 Extension of DW = AW sign: CY ← 0, V ← 0 Extension of DW ≠ AW sign: CY ← 1, V ← 1 U × × U U U DW, AW ← AW × (mem16) Extension of DW = AW sign: CY ← 0, V ← 0 Extension of DW ≠ AW sign: CY ← 1, V ← 1 U × × U U U reg16 ← reg16’ × imm8 Product ≤ 16 bits: CY ← 0, V ← 0 Product > 16 bits: CY ← 1, V ← 1 U × × U U U reg16 ← (mem16) × imm8 Product ≤ 16 bits: CY ← 0, V ← 0 Product > 16 bits: CY ← 1, V ← 1 U × × U U U reg16 ← reg16’ × imm16 Product ≤ 16 bits: CY ← 0, V ← 0 Product > 16 bits: CY ← 1, V ← 1 U × × U U U reg16 ← (mem16) × imm16 Product ≤ 16 bits: CY ← 0, V ← 0 Product > 16 bits: CY ← 1, V ← 1 U × × U U U µPD70325 21 reg16, (reg16’,) Note imm8 mod 1 0 0 mem 2 AC CY V 22 Operation Code Group Unsigned division Mnemonic DIVU Flags Bytes Operand 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg8 1 1 1 1 0 1 1 0 1 1 1 1 0 reg mem8 1 1 1 1 0 1 1 0 mod 1 1 0 mem reg16 1 1 1 1 0 1 1 1 1 1 1 1 0 reg mem16 1 1 1 1 0 1 1 1 mod 1 1 0 mem Operation AC CY V P S Z 2 temp ← AW When temp ÷ reg8 ≤ FFH AH ← temp%reg8, AL ← temp ÷ reg8 When temp ÷ reg8 > FFH (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0) U U U U U U 2 to 4 temp ← AW When temp ÷ (mem8) ≤ FFH AH ← temp%(mem8), AL ← temp ÷ (mem8) When temp ÷ (mem8) > FFH (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0) U U U U U U 2 temp ← DW, AW When temp ÷ reg16 ≤ FFFFH DW ← temp%reg16, AW ← temp ÷ reg16 When temp ÷ reg16 > FFFFH (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0) U U U U U U 2 to 4 temp ← DW, AW When temp ÷ (mem16) ≤ FFFFH DW ← temp%(mem16), AW ← temp ÷ (mem16) When temp ÷ (mem16) > FFFFH (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0) U U U U U U µPD70325 Operation Code Group Signed division Mnemonic DIV Operand Flags Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg8 1 1 1 1 0 1 1 0 1 1 1 1 1 reg mem8 1 1 1 1 0 1 1 0 mod 1 1 1 mem reg16 1 1 1 1 0 1 1 1 1 1 1 1 1 reg mem16 1 1 1 1 0 1 1 1 mod 1 1 1 mem Operation AC CY V P S Z temp ← AW When temp ÷ reg8 > 0 and temp ÷ reg8 ≤ 7FH or temp ÷ reg8 < 0 and temp ÷ reg8 > 0 – 7FH – 1 AH ← temp%reg8, AL ← temp ÷ reg8 When temp ÷ reg8 > 0 and temp ÷ reg8 > 7FH or temp ÷ reg8 > 0 and temp ÷ reg8 < 0 – 7FH – 1 (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0) U U U U U U 2 to 4 temp ← AW When temp ÷ (mem8) > 0 and temp ÷ (mem8) ≤ 7FH or temp ÷ (mem8) < 0 and temp ÷ (mem8) > 0 – 7FH – 1 AH ← temp%(mem8), AL ← temp ÷ (mem8) When temp ÷ (mem8) > 0 and temp ÷ (mem8) > 7FH or temp ÷ (mem8) > 0 and temp ÷ (mem8) < 0 – 7FH – 1 (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0) U U U U U U 2 temp ← DW, AW When temp ÷ reg16 > 0 and temp ÷ reg16 ≤ 7FFFH or temp ÷ reg16 < 0 and temp ÷ reg16 > 0 – 7FFFH – 1 DW ← temp%reg16, AW ← temp ÷ reg16 When temp ÷ reg16 > 0 and temp ÷ reg16 > 7FFFH or temp ÷ reg16 > 0 and temp ÷ reg16 < 0 – 7FFFH – 1 (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0) U U U U U U temp ← DW, AW When temp ÷ (mem16) > 0 and temp ÷ (mem16) ≤ 7FFFH or temp ÷ (mem16) < 0 and temp ÷ (mem16) > 0 – 7FFFH – 1 DW ← temp%(mem16), AW ← temp ÷ (mem16) When temp ÷ (mem16) > 0 and temp ÷ (mem16) > 7FFFH or temp ÷ (mem16) > 0 and temp ÷ (mem16) < 0 – 7FFFH – 1 (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0, PS ← (3, 2), PC ← (1, 0) U U U U U U 2 2 to 4 µPD70325 23 24 Flags Operation Code Group Mnemonic Operand 7 6 5 4 3 2 1 0 BCD adjustment Data conversion Compare Complement operation AC CY V 7 6 5 4 3 2 1 0 S Z U U U U × × U × × × × × U U U U × × U × × × AH ← AL ÷ 0AH, AL ← AL%0AH U U U × × × 2 AL ← AH × 0AH + AL, AH ← 0 U U U × × × 1 0 0 1 1 0 0 0 1 When AL < 80H, AH ← 0. In other cases, AH ← FFH. 1 0 0 1 1 0 0 1 1 When AW < 8000H, DW ← 0. In other cases, DW ← FFFFH. 2 reg – reg’ × × × × × × 1 ADJ4A 0 0 1 0 0 1 1 1 1 ADJBS 0 0 1 1 1 1 1 1 1 ADJ4S 0 0 1 0 1 1 1 1 1 CVTBD 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 2 CVTDB 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 CVTBW CVTWL NEG P × 0 0 1 1 0 1 1 1 NOT When AL ∧ 0FH > 9 or AC = 1, AL ← AL + 6 AH ← AH + 1, AC ← 1, CY ← AC, AL ← AL ∧ 0FH When AL ∧ 0FH > 9 or AC = 1, AL ← AL + 6, AC ← 1 When AL > 9FH or CY = 1, AL ← AL + 60H, CY ← 1 × ADJBA CMP Operation Bytes reg’ When AL ∧ 0FH > 9 or AC = 1, AL ← AL – 6, AH ← AH – 1, AC ← 1 CY ← AC, AL ← AL ∧ 0FH When AL ∧ 0FH > 9 or AC = 1, AL ← AL – 6, AC ← 1 When AL > 9FH or CY = 1, AL ← AL – 60H, CY ← 1 reg,reg’ 0 0 1 1 1 0 1 W 1 1 reg mem,reg 0 0 1 1 1 0 0 W mod reg mem 2 to 4 (mem) – reg × × × × × × reg,mem 0 0 1 1 1 0 1 W mod reg mem 2 to 4 reg – (mem) × × × × × × reg,imm 1 0 0 0 0 0 s W 1 1 1 1 1 reg 3 to 4 reg – imm × × × × × × mem,imm 1 0 0 0 0 0 s W mod 1 1 1 mem 3 to 6 (mem) – imm × × × × × × acc,imm 0 0 1 1 1 1 0 W 2 to 3 When W = 0, AL – imm When W = 1, AW – imm × × × × × × reg 1 1 1 1 0 1 1 W 1 1 0 1 0 reg mem 1 1 1 1 0 1 1 W mod 0 1 0 mem reg 1 1 1 1 0 1 1 W 1 1 0 1 1 reg reg ← reg + 1 × × × × × × mem 1 1 1 1 0 1 1 W mod 0 1 1 mem (mem) ← (mem) + 1 × × × × × × 2 2 to 4 2 2 to 4 reg ← reg (mem) ← (mem) µPD70325 Flags Operation Code Group Logical operation Mnemonic TEST AND OR XOR Operand Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg,reg’ 1 0 0 0 0 1 0 W 1 1 reg’ mem,reg reg,mem 1 0 0 0 0 1 0 W mod reg mem reg,imm 1 1 1 1 0 1 1 W mem,imm 1 1 1 1 0 1 1 W Operation AC CY V P S Z reg ∧ reg’ U 0 0 × × × 2 to 4 (mem) ∧ reg U 0 0 × × × 1 1 0 0 0 reg 3 to 4 reg ∧ imm U 0 0 × × × mod 0 0 0 mem 3 to 6 (mem) ∧ imm U 0 0 × × × 2 to 3 When W = 0, AL ∧ imm8 When W = 1, AW ∧ imm16 U 0 0 × × × reg ← reg ∧ reg’ U 0 0 × × × reg 2 acc,imm 1 0 1 0 1 0 0 W reg,reg’ 0 0 1 0 0 0 1 W 1 1 reg mem,reg 0 0 1 0 0 0 0 W mod reg mem 2 to 4 (mem) ← (mem) ∧ reg U 0 0 × × × reg,mem 0 0 1 0 0 0 1 W mod reg mem 2 to 4 reg ← reg ∧ (mem) U 0 0 × × × reg,imm 1 0 0 0 0 0 0 W 1 1 1 0 0 reg 3 to 4 reg ← reg ∧ imm U 0 0 × × × mem,imm 1 0 0 0 0 0 0 W mod 1 0 0 mem 3 to 6 (mem) ← (mem) ∧ imm U 0 0 × × × 2 to 3 When W = 0, AL ← AL ∧ imm8 When W = 1, AW ← AW ∧ imm16 U 0 0 × × × reg ← reg ∨ reg’ U 0 0 × × × reg’ 2 acc,imm 0 0 1 0 0 1 0 W reg,reg’ 0 0 0 0 1 0 1 W 1 1 reg mem,reg 0 0 0 0 1 0 0 W mod reg mem 2 to 4 (mem) ← (mem) ∨ reg U 0 0 × × × reg,mem 0 0 0 0 1 0 1 W mod reg mem 2 to 4 reg ← reg ∨ (mem) U 0 0 × × × reg,imm 1 0 0 0 0 0 0 W 1 1 0 0 1 reg 3 to 4 reg ← reg ∨ imm U 0 0 × × × mem,imm 1 0 0 0 0 0 0 W mod 0 0 1 mem 3 to 6 (mem) ← (mem) ∨ imm U 0 0 × × × 2 to 3 When W = 0, AL ← AL ∨ imm8 When W = 1, AW ← AW ∨ imm16 U 0 0 × × × reg ← reg ∨ reg’ U 0 0 × × × reg’ 2 0 0 0 0 1 1 0 W reg,reg’ 0 0 1 1 0 0 1 W 1 1 reg mem,reg 0 0 1 1 0 0 0 W mod reg mem 2 to 4 (mem) ← (mem) ∨ reg U 0 0 × × × reg,mem 0 0 1 1 0 0 1 W mod reg mem 2 to 4 reg ← reg ∨ (mem) U 0 0 × × × reg,imm 1 0 0 0 0 0 0 W 1 1 1 1 0 reg 3 to 4 reg ← reg ∨ imm U 0 0 × × × mem,imm 1 0 0 0 0 0 0 W mod 1 1 0 mem 3 to 6 (mem) ← (mem) ∨ imm U 0 0 × × × acc,imm 0 0 1 1 0 1 0 W 2 to 3 When W = 0, AL ← AL ∨ imm8 When W = 1, AW ← AW ∨ imm16 U 0 0 × × × reg’ 2 25 µPD70325 acc,imm 26 Flags Operation Code Group Mnemonic Operand 7 6 5 4 3 2 1 0 TEST1 NOT1 reg8,CL 0 0 0 1 0 0 0 0 AC CY V 7 6 5 4 3 2 1 0 1 1 0 0 0 reg mem8,CL 0 0 0 0 mod 0 0 0 mem reg16,CL 0 0 0 1 1 1 0 0 0 reg mem16,CL 0 0 0 1 mod 0 0 0 mem reg8,imm3 1 0 0 0 1 1 0 0 0 reg mem8,imm3 1 0 0 0 mod 0 0 0 mem reg16,imm4 1 0 0 1 1 1 0 0 0 reg mem16,imm4 1 0 0 1 mod 0 0 0 mem reg8,CL 0 1 1 0 1 1 0 0 0 reg mem8,CL 0 1 1 0 mod 0 0 0 mem reg16,CL 0 1 1 1 1 1 0 0 0 reg mem16,CL 0 1 1 1 mod 0 0 0 mem reg8,imm3 1 1 1 0 1 1 0 0 0 reg mem8,imm3 1 1 1 0 mod 0 0 0 mem reg16,imm4 1 1 1 1 1 1 0 0 0 reg mem16,imm4 1 1 1 1 mod 0 0 0 mem 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 reg8 bit No. CL = 0: Z ← 1 reg8 bit No. CL = 1: Z ← 0 (mem8) bit No. CL = 0: Z ← 1 (mem8) bit No. CL = 1: Z ← 0 reg16 bit No. CL = 0: Z ← 1 reg16 bit No. CL = 1: Z ← 0 (mem16) bit No. CL = 0: Z ← 1 (mem16) bit No. CL = 1: Z ← 0 reg8 bit No. imm3 = 0: Z ← 1 reg8 bit No. imm3 = 1: Z ← 0 (mem8) bit No. imm3 = 0: Z ← 1 (mem8) bit No. imm3 = 1: Z ← 0 reg16 bit No. imm4 = 0: Z ← 1 reg16 bit No. imm4 = 1: Z ← 0 (mem16) bit No. imm4 = 0: Z ← 1 (mem16) bit No. imm4 = 1: Z ← 0 P S Z U 0 0 U U × U 0 0 U U × U 0 0 U U × U 0 0 U U × U 0 0 U U × U 0 0 U U × U 0 0 U U × U 0 0 U U × reg8 bit No. CL ← reg8 bit No. CL (mem8) bit No. CL ← (mem8) bit No. CL reg16 bit No. CL ← reg16 bit No. CL (mem16) bit No. CL ← (mem16) bit No. CL reg8 bit No. imm3 ← reg8 bit No. imm3 (mem8) bit No. imm3 ← (mem8) bit No. imm3 reg16 bit No. imm4 ← reg16 bit No. imm4 (mem16) bit No. imm4 ← (mem16) bit No. imm4 Bit manipulation Operation Bytes 2nd byte NOT1 CY Note 1 1 1 1 0 1 0 1 3rd byte Note Note 1st byte = 0FH 1 CY ← CY × µPD70325 Operation Code Group Bit manipulation Mnemonic CLR1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 reg mem8,CL 0 0 1 0 mod 0 0 0 mem reg16,CL 0 0 1 1 1 1 0 0 0 reg mem16,CL 0 0 1 1 mod 0 0 0 mem reg8,imm3 1 0 1 0 1 1 0 0 0 reg mem8,imm3 1 0 1 0 mod 0 0 0 mem reg16,imm4 1 0 1 1 1 1 0 0 0 reg mem16,imm4 1 0 1 1 mod 0 0 0 mem reg8,CL 0 1 0 0 1 1 0 0 0 reg mem8,CL 0 1 0 0 mod 0 0 0 mem reg16,CL 0 1 0 1 1 1 0 0 0 reg mem16,CL 0 1 0 1 mod 0 0 0 mem reg8,imm3 1 1 0 0 1 1 0 0 0 reg mem8,imm3 1 1 0 0 mod 0 0 0 mem reg16,imm4 1 1 0 1 1 1 0 0 0 reg mem16,imm4 1 1 0 1 mod 0 0 0 mem Operation AC CY V P S Z reg8 bit No. CL ← 0 3 3 to 5 (mem8) bit No. CL ← 0 reg16 bit No. CL ← 0 3 3 to 5 (mem16) bit No. CL ← 0 reg8 bit No. imm3 ← 0 4 4 to 6 (mem8) bit No. imm3 ← 0 reg16 bit No. imm4 ← 0 4 4 to 6 (mem16) bit No. imm4 ← 0 reg8 bit No. CL ← 1 3 3 to 5 (mem8) bit No. CL ← 1 reg16 bit No. CL ← 1 3 3 to 5 (mem16) bit No. CL ← 1 reg8 bit No. imm3 ← 1 4 4 to 6 (mem8) bit No. imm3 ← 1 reg16 bit No. imm4 ← 1 4 4 to 6 (mem16) bit No. imm4 ← 1 SET1 reg8,CL Flags Bytes Operand 2nd byte Note CLR1 CY 1 1 1 1 1 0 0 0 1 CY ← 0 DIR 1 1 1 1 1 1 0 0 1 DIR ← 0 CY 1 1 1 1 1 0 0 1 1 CY ← 1 DIR 1 1 1 1 1 1 0 1 1 DIR ← 1 0 1 27 µPD70325 SET1 Note 1st byte = 0FH 3rd byte Note 28 Operation Code Group Shift Mnemonic SHL Flags Operation Bytes Operand 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg,1 1 1 0 1 0 0 0 W 1 1 1 0 0 reg mem,1 1 1 0 1 0 0 0 W mod 1 0 0 mem reg,CL 1 1 0 1 0 0 1 W 1 1 1 0 0 reg mem,CL 1 1 0 1 0 0 1 W mod 1 0 0 mem reg,imm8 1 1 0 0 0 0 0 W 1 1 1 0 0 reg mem,imm8 1 1 0 0 0 0 0 W mod 1 0 0 mem 2 2 to 4 2 2 to 4 3 3 to 5 AC CY V P S Z CY ← reg MSB, reg ← reg × 2 When reg MSB ≠ CY, V ← 1 When reg MSB = CY, V ← 0 U × × × × × CY ← (mem) MSB, (mem) ← (mem) × 2 When (mem) MSB ≠ CY, V ← 1 When (mem) MSB = CY, V ← 0 U × × × × × U × U × × × U × U × × × U × U × × × U × U × × × The following operations are repeated while temp ← CL and temp ≠ 0. CY ← reg MSB, reg ← reg × 2 temp ← temp – 1 The following operations are repeated while temp ← CL and temp ≠ 0. CY ← (mem) MSB, (mem) ← (mem) × 2 temp ← temp – 1 The following operations are repeated while temp ← imm8 and temp ≠ 0. CY ← reg MSB, reg ← reg × 2 temp ← temp – 1 The following operations are repeated while temp ← imm8 and temp ≠ 0. CY ← (mem) MSB, (mem) ← (mem) × 2 temp ← temp – 1 µPD70325 Flags Operation Code Group Shift Mnemonic SHR SHRA Bytes Operand 7 6 5 4 3 2 1 0 reg,1 1 1 0 1 0 0 0 W 1 1 1 0 1 reg mem,1 1 1 0 1 0 0 0 W mod 1 0 1 mem reg,CL 1 1 0 1 0 0 1 W 1 1 1 0 1 reg mem,CL 1 1 0 1 0 0 1 W mod 1 0 1 mem reg,imm8 1 1 0 0 0 0 0 W 1 1 1 0 1 reg mem,imm8 1 1 0 0 0 0 0 W mod 1 0 1 mem reg,1 1 1 0 1 0 0 0 W 1 1 1 1 1 reg mem,1 1 1 0 1 0 0 0 W mod 1 1 1 mem reg,CL 1 1 0 1 0 0 1 W 1 1 1 1 1 reg mem,CL 1 1 0 1 0 0 1 W mod 1 1 1 mem reg,imm8 1 1 0 0 0 0 0 W 1 1 1 1 1 reg mem,imm8 1 1 0 0 0 0 0 W mod 1 1 1 mem 2 2 to 4 2 2 to 4 3 3 to 5 2 2 to 4 2 2 to 4 3 3 to 5 AC CY V P S Z CY ← reg LSB, reg ← reg ÷ 2 reg MSB ≠ bit following reg MSB: V ← 1 reg MSB = bit following reg MSB: V ← 0 U × × × × × CY ← (mem) LSB, (mem) ← (mem) ÷ 2 (mem) MSB ≠ bit following (mem) MSB: V ← 1 (mem) MSB = bit following (mem) MSB: V ← 0 U × × × × × U × U × × × U × U × × × U × U × × × U × U × × × U × 0 × × × U × 0 × × × U × U × × × U × U × × × U × U × × × U × U × × × The following operations are repeated while temp ← CL and temp ≠ 0. CY ← reg LSB, reg ← reg ÷ 2 temp ← temp – 1 The following operations are repeated while temp ← CL and temp ≠ 0. CY ← (mem) LSB, (mem) ← (mem) ÷ 2 temp ← temp – 1 The following operations are repeated while temp ← imm8 and temp ≠ 0. CY ← reg LSB, reg ← reg ÷ 2 temp ← temp – 1 The following operations are repeated while temp ← imm8 and temp ≠ 0. CY ← (mem) LSB, (mem) ← (mem) ÷ 2 temp ← temp – 1 CY ← reg LSB, reg ← reg ÷ 2, V ← 0 The operand MSB remains the same status. CY ← (mem) LSB, (mem) ← (mem) ÷ 2, V ← 0 The operand MSB remains the same status. The following operations are repeated while temp ← CL and temp ≠ 0. CY ← reg LSB, reg ← reg ÷ 2 temp ← temp – 1 The operand MSB remains the same status. The following operations are repeated while temp ← CL and temp ≠ 0. CY ← (mem) LSB, (mem) ← (mem) ÷ 2 temp ← temp – 1 The operand MSB remains the same status. The following operations are repeated while temp ← imm8 and temp ≠ 0. CY ← reg LSB, reg ← reg ÷ 2 temp ← temp – 1 The operand MSB remains the same status. The following operations are repeated while temp ← imm8 and temp ≠ 0. CY ← (mem) LSB, (mem) ← (mem) ÷ 2 temp ← temp – 1 The operand MSB remains the same status. 29 µPD70325 7 6 5 4 3 2 1 0 Operation 30 Flags Operation Code Group Rotate Mnemonic ROL ROR Bytes Operand 7 6 5 4 3 2 1 0 reg,1 1 1 0 1 0 0 0 W 1 1 0 0 0 reg mem,1 1 1 0 1 0 0 0 W mod 0 0 0 mem reg,CL 1 1 0 1 0 0 1 W 1 1 0 0 0 reg mem,CL 1 1 0 1 0 0 1 W mod 0 0 0 mem reg,imm8 1 1 0 0 0 0 0 W 1 1 0 0 0 reg mem,imm8 1 1 0 0 0 0 0 W mod 0 0 0 mem reg,1 1 1 0 1 0 0 0 W 1 1 0 0 1 reg mem,1 1 1 0 1 0 0 0 W mod 0 0 1 mem reg,CL 1 1 0 1 0 0 1 W 1 1 0 0 1 reg mem,CL 1 1 0 1 0 0 1 W mod 0 0 1 mem reg,imm8 1 1 0 0 0 0 0 W 1 1 0 0 1 reg mem,imm8 1 1 0 0 0 0 0 W mod 0 0 1 mem Operation AC CY V 2 2 to 4 2 2 to 4 3 3 to 5 2 2 to 4 2 2 to 4 3 3 to 5 CY ← reg MSB, reg ← reg × 2 + CY reg MSB ≠ CY: V ← 1 reg MSB = CY: V ← 0 × × CY ← (mem) MSB, (mem) ← (mem) × 2 + CY (mem) MSB ≠ CY: V ← 1 (mem) MSB = CY: V ← 0 × × × U × U × U × U × × × × × U × U × U × U The following operations are repeated while temp ← CL and temp ≠ 0. CY ← reg MSB, reg ← reg × 2 + CY temp ← temp – 1 The following operations are repeated while temp ← CL and temp ≠ 0. CY ← (mem) MSB, (mem) ← (mem) × 2 + CY temp ← temp – 1 The following operations are repeated while temp ← imm8 and temp ≠ 0. CY ← reg MSB, reg ← reg × 2 + CY temp ← temp – 1 The following operations are repeated while temp ← imm8 and temp ≠ 0. CY ← (mem) MSB, (mem) ← (mem) × 2 + CY temp ← temp – 1 CY ← reg LSB, reg ← reg ÷ 2 reg MSB ← CY reg MSB ≠ bit following reg MSB: V ← 1 reg MSB = bit following reg MSB: V ← 0 CY ← (mem) LSB, (mem) ← (mem) ÷ 2 (mem) MSB ← CY (mem) MSB ≠ bit following (mem) MSB: V ← 1 (mem) MSB = bit following (mem) MSB: V ← 0 The following operations are repeated while temp ← CL and temp ≠ 0. CY ← reg LSB, reg ← reg ÷ 2 reg MSB ← CY temp ← temp – 1 The following operations are repeated while temp ← CL and temp ≠ 0. CY ← (mem) LSB, (mem) ← (mem) ÷ 2 (mem) MSB ← CY temp ← temp – 1 The following operations are repeated while temp ← imm8 and temp ≠ 0. CY ← reg LSB, reg ← reg ÷ 2 reg MSB ← CY temp ← temp – 1 The following operations are repeated while temp ← imm8 and temp ≠ 0. CY ← (mem) LSB, (mem) ← (mem) ÷ 2 (mem) MSB ← CY temp ← temp – 1 P S Z µPD70325 7 6 5 4 3 2 1 0 Operation Code Group Mnemonic Operand 7 6 5 4 3 2 1 0 Rotate ROLC Flags Bytes Operation 7 6 5 4 3 2 1 0 reg,1 1 1 0 1 0 0 0 W 1 1 0 1 0 reg mem,1 1 1 0 1 0 0 0 W mod 0 1 0 mem reg,CL 1 1 0 1 0 0 1 W 1 1 0 1 0 reg mem,CL 1 1 0 1 0 0 1 W mod 0 1 0 mem reg,imm8 1 1 0 0 0 0 0 W 1 1 0 1 0 reg mem,imm8 1 1 0 0 0 0 0 W mod 0 1 0 mem AC CY V 2 2 to 4 2 2 to 4 tmpcy ← CY, CY ← reg MSB reg ← reg × 2 + tmpcy reg MSB ≠ CY: V ← 1 reg MSB = CY: V ← 0 tmpcy ← CY, CY ← (mem) MSB (mem) ← (mem) × 2 + tmpcy (mem) MSB ≠ CY: V ← 1 (mem) MSB = CY: V ← 0 The following operations are repeated while temp ← CL and temp ≠ 0. tmpcy ← CY, CY ← reg MSB reg ← reg × 2 + tmpcy temp ← temp – 1 The following operations are repeated while temp ← CL and temp ≠ 0. tmpcy ← CY, CY ← (mem) MSB (mem) ← (mem) × 2 + tmpcy temp ← temp – 1 × × × × × U × U 3 The following operations are repeated while temp ← imm8 and temp ≠ 0. tmpcy ← CY, CY ← reg MSB reg ← reg × 2 + tmpcy temp ← temp – 1 × U 3 to 5 The following operations are repeated while temp ← imm8 and temp ≠ 0. tmpcy ← CY, CY ← (mem) MSB (mem) ← (mem) × 2 + tmpcy temp ← temp – 1 × U P S Z µPD70325 31 32 Operation Code Group Rotate Mnemonic RORC Operand Flags Bytes 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 reg,1 1 1 0 1 0 0 0 W 1 1 0 1 1 reg mem,1 1 1 0 1 0 0 0 W mod 0 1 1 mem reg,CL 1 1 0 1 0 0 1 W 1 1 0 1 1 reg mem,CL 1 1 0 1 0 0 1 W mod 0 1 1 mem reg,imm8 1 1 0 0 0 0 0 W 1 1 0 1 1 reg mem,imm8 1 1 0 0 0 0 0 W mod 0 1 1 mem Operation AC CY V tmpcy ← CY, CY ← reg LSB reg ← reg ÷ 2 reg MSB ← tmpcy reg MSB ≠ bit following reg MSB: V ← 1 reg MSB = bit following reg MSB: V ← 0 × × tmpcy ← CY, CY ← (mem) LSB (mem) ← (mem) ÷ 2 (mem) MSB ← tmpcy (mem) MSB ≠ bit following (mem) MSB: V ← 1 (mem) MSB = bit following (mem) MSB: V ← 0 × × 2 The following operations are repeated while temp ← CL and temp ≠ 0. tmpcy ← CY, CY ← reg LSB reg ← reg ÷ 2 reg MSB ← tmpcy temp ← temp – 1 × U 2 to 4 The following operations are repeated while temp ← CL and temp ≠ 0. tmpcy ← CY, CY ← (mem) LSB (mem) ← (mem) ÷ 2 (mem) MSB ← tmpcy temp ← temp – 1 × U × U × U 2 2 to 4 3 3 to 5 The following operations are repeated while temp ← imm8 and temp ≠ 0. tmpcy ← CY, CY ← reg LSB reg ← reg ÷ 2 reg MSB ← tmpcy temp ← temp – 1 The following operations are repeated while temp ← imm8 and temp ≠ 0. tmpcy ← CY, CY ← (mem) LSB (mem) ← (mem) ÷ 2 (mem) MSB ← tmpcy temp ← temp – 1 P S Z µPD70325 Flags Operation Code Group Mnemonic Operand 7 6 5 4 3 2 1 0 Subroutine control CALL 3 1 1 1 0 1 0 0 0 regptr16 1 1 1 1 1 1 1 1 1 1 0 1 0 reg memptr16 1 1 1 1 1 1 1 1 mod 0 1 0 mem far-proc 1 0 0 1 1 0 1 0 memptr32 1 1 1 1 1 1 1 1 pop-value pop-value AC CY V 7 6 5 4 3 2 1 0 near-proc RET Operation Bytes mod 0 1 1 mem 2 2 to 4 P S Z (SP – 1, SP – 2) ← PC, SP ← SP – 2 PC ← PC + disp (SP – 1, SP – 2) ← PC, PC ← regptr16 SP ← SP – 2 (SP – 1, SP – 2) ← PC, SP ← SP – 2 PC ← (memptr16) 5 (SP – 1, SP – 2) ← PS, (SP – 3, SP – 4) ← PC SP ← SP – 4 PS ← seg, PC ← offset 2 to 4 (SP – 1, SP – 2) ← PS, (SP – 3, SP – 4) ← PC SP ← SP – 4 PS ← (memptr32 + 2), PC ← (memptr32) PC ← (SP + 1, SP) SP ← SP + 2 PC ← (SP + 1, SP) SP ← SP + 2, SP ← SP + pop-value 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 3 1 1 0 0 1 0 1 1 1 PC ← (SP + 1, SP) PS ← (SP + 3, SP + 2) SP ← SP + 4 1 1 0 0 1 0 1 0 3 PC ← (SP + 1, SP) PS ← (SP + 3, SP + 2) SP ← SP + 4, SP ← SP + pop-value µPD70325 33 34 Flags Operation Code Group Mnemonic Operand 7 6 5 4 3 2 1 0 Stack manipulation PUSH POP PREPARE BR AC CY V 7 6 5 4 3 2 1 0 mod 1 1 0 mem 2 to 4 1 1 1 1 1 1 1 1 reg16 0 1 0 1 0 reg 1 sreg 0 0 0 sreg 1 1 0 1 PSW 1 0 0 1 1 1 0 0 1 R 0 1 1 0 0 0 0 0 1 imm8 0 1 1 0 1 0 1 0 2 imm16 0 1 1 0 1 0 0 0 3 mem16 1 0 0 0 1 1 1 1 reg16 0 1 0 1 1 sreg 0 0 0 sreg 1 1 1 1 PSW 1 0 0 1 1 1 0 1 1 R 0 1 1 0 0 0 0 1 1 Pop registers from the stack imm16,imm8 1 1 0 0 1 0 0 0 4 Prepare New Stack Frame 1 1 0 0 1 0 0 1 1 Dispose of Stack Frame near-label 1 1 1 0 1 0 0 1 3 PC ← PC + disp short-label 1 1 1 0 1 0 1 1 2 PC ← PC + ext-disp8 regptr16 1 1 1 1 1 1 1 1 1 1 1 0 0 2 PC ← regptr16 memptr16 1 1 1 1 1 1 1 1 mod 1 0 0 mem mod 0 0 0 mem 1 reg far-label 1 1 1 0 1 0 1 0 memptr32 1 1 1 1 1 1 1 1 2 to 4 reg 2 to 4 5 mod 1 0 1 mem 2 to 4 P S Z R R R (SP – 1, SP – 2) ← (mem16) SP ← SP – 2 (SP – 1, SP – 2) ← reg16 SP ← SP – 2 (SP – 1, SP – 2) ← sreg SP ← SP – 2 (SP – 1, SP – 2) ← PSW SP ← SP – 2 mem16 DISPOSE Branch Operation Bytes Push registers on the stack (SP – 1, SP – 2) ← imm8 sign extension SP ← SP – 2 (SP – 1, SP – 2) ← imm16 SP ← SP – 2 (mem16) ← (SP + 1, SP) SP ← SP + 2 reg16 ← (SP + 1, SP) SP ← SP + 2 sreg ← (SP + 1, SP) SP ← SP + 2 PSW ← (SP + 1, SP) SP ← SP + 2 sreg: SS, DS0, DS1 R R R PC ← (memptr16) PS ← seg PC ← offset PS ← (memptr32 + 2) PC ← (memptr32) µPD70325 Flags Operation Code Group Mnemonic Operand 7 6 5 4 3 2 1 0 Conditional branch Operation Bytes AC CY V 7 6 5 4 3 2 1 0 BV short-label 0 1 1 1 0 0 0 0 2 if V = 1 PC ← PC + ext-disp8 BNV short-label 0 0 0 1 2 if V = 0 PC ← PC + ext-disp8 short-label 0 0 1 0 2 if CY = 1 PC ← PC + ext-disp8 short-label 0 0 1 1 2 if CY = 0 PC ← PC + ext-disp8 short-label 0 1 0 0 2 if Z = 1 PC ← PC + ext-disp8 short-label 0 1 0 1 2 if Z = 0 PC ← PC + ext-disp8 BNH short-label 0 1 1 0 2 if CY ∨ Z = 1 PC ← PC + ext-disp8 BH short-label 0 1 1 1 2 if CY ∨ Z = 0 PC ← PC + ext-disp8 BN short-label 1 0 0 0 2 if S = 1 PC ← PC + ext-disp8 BP short-label 1 0 0 1 2 if S = 0 PC ← PC + ext-disp8 BPE short-label 1 0 1 0 2 if P = 1 PC ← PC + ext-disp8 BPO short-label 1 0 1 1 2 if P = 0 PC ← PC + ext-disp8 BLT short-label 1 1 0 0 2 if S ∨ V = 1 PC ← PC + ext-disp8 BGE short-label 1 1 0 1 2 if S ∨ V = 0 PC ← PC + ext-disp8 BLE short-label 1 1 1 0 2 if (S ∨ V) ∨ Z = 1 PC ← PC + ext-disp8 BGT short-label 1 1 1 1 2 if (S ∨ V) ∨ Z = 0 PC ← PC + ext-disp8 CW = CW – 1 if Z = 0 and CW ≠ 0 CW = CW – 1 if Z = 1 and CW ≠ 0 CW = CW – 1 if CW ≠ 0 PC ← PC + ext-disp8 PC ← PC + ext-disp8 BC BL BNC BNL BE BZ BNE BNZ DBNZNE short-label 1 1 1 0 0 0 0 0 2 DBNZE short-label 0 0 0 1 2 DBNZ short-label 0 0 1 0 2 BCWZ short-label 0 0 1 1 2 if CW = 0 sfr, imm3, short-label 0 0 0 0 1 1 1 1 5 When (sfr) bit No. imm3 = 1, PC ← PC + ext-disp8 and (sfr) bit No. imm3 ← 0. Note 1 0 0 1 1 1 0 0 Note This instruction is newly added to the µ PD70108/70116. S Z PC ← PC + ext-disp8 PC ← PC + ext-disp8 35 µPD70325 BTCLR P 36 Operation Code Group Mnemonic Bytes 7 6 5 4 3 2 1 0 Interrupt Register bank switch Flags Operand Operation AC CY V 7 6 5 4 3 2 1 0 P S Z (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS, (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0 PS ← (15, 14), PC ← (13, 12) (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS, (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0 PS ← (n × 4 + 3, n × 4 + 2), PC ← (n × 4 + 1, n × 4) n = imm8 3 1 1 0 0 1 1 0 0 1 imm8 ( ≠ 3) 1 1 0 0 1 1 0 1 2 BRKV 1 1 0 0 1 1 1 0 1 RETI 1 1 0 0 1 1 1 1 1 PC ← (SP + 1, SP), PS ← (SP + 3, SP + 2), PSW ← (SP + 5, SP + 4), SP ← SP + 6 R R R R R R RETRBI Note 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 2 PC ← Save PC, PSW ← Save PSW R R R R R R FINT Note 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 0 2 Reports the CPU internal interrupt controller that interrupt service routine operation has ended. × × × × × × BRK CHKIND reg16,mem32 0 1 1 0 0 0 1 0 mod BRKCS Note reg16 0 0 0 0 1 1 1 1 0 0 1 0 1 1 0 1 3 RB2 – 0 ← lower 3 bits of reg16, IE ← 0, BRK ← 0 Save PSW ← PSW, Save PC ← PC, PC ← Vector PC 1 0 0 1 0 1 0 0 3 RB2 – 0 ← lower 3 bits of reg16, Old register bank Save PSW and Save PC ← PSW and PC, PSW and PC ← New register bank Save PSW and Save PC 1 1 0 0 0 TSKSW Note reg16 mem 2 to 4 When (mem32) > reg16 or (mem32 + 2) < reg16, (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS, (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0 PS ← (23, 22), PC ← (21, 20) reg 0 0 0 0 1 1 1 1 1 1 1 1 1 reg When V = 1, (SP – 1, SP – 2) ← PSW, (SP – 3, SP – 4) ← PS, (SP – 5, SP – 6) ← PC, SP ← SP – 6 IE ← 0, BRK ← 0 PS ← (19, 18), PC ← (17, 16) reg Note These instructions are newly added to the µ PD70108/70116. µPD70325 Flags Operation Code Group Mnemonic Operand CPU control STOP 0 0 0 0 1 1 1 1 AC CY V 7 6 5 4 3 2 1 0 1 1 1 1 0 1 0 0 HALT Operation Bytes 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 CPU Halt 2 CPU Stop P S Z Note 2 POLL 1 0 0 1 1 0 1 1 1 Poll and wait DI 1 1 1 1 1 0 1 0 1 IE ← 0 EI 1 1 1 1 1 0 1 1 1 IE ← 1 BUSLOCK 1 1 1 1 0 0 0 0 1 Bus Lock Prefix No Operation FPO1 Note 3 FPO2 Note 3 NOP Note 1 fp-op 1 1 0 1 1 X X X 1 1 Y Y Y Z Z Z 2 fp-op,mem 1 1 0 1 1 X X X mod Y Y Y mem 2 to 4 fp-op 0 1 1 0 0 1 1 X 1 1 Y Y Y Z Z Z 2 fp-op,mem 0 1 1 0 0 1 1 X mod Y Y Y mem 2 to 4 data bus ← (mem) No Operation data bus ← (mem) 1 0 0 1 0 0 0 0 1 No Operation 0 0 1 sreg 1 1 0 1 Segment override prefix Notes 1. DS0:, DS1:, PS: and SS: 2. This instruction is newly added to the µ PD70108/70116. 3. In the µPD70320, an interrupt is generated without executing these instructions. µPD70325 37 µPD70325 2.4 Number of Clocks Table (1) Legend The number of clocks, for memory operand, differs among addressing modes. So, use the following values for “EA” items shown in Table 2-9 Number of Clocks. Table 2-8. Number of Clocks for Each Memory Addressing mod 00 mem Clocks 01 Clocks 10 Clocks 000 BW + IX 3 BW + IX + disp8 3 BW + IX + disp16 4 001 BW + IY 3 BW + IY + disp8 3 BW + IY + disp16 4 010 BP + IX 3 BP + IX + disp8 3 BP + IX + disp16 4 011 BP + IY 3 BP + IY + disp8 3 BP + IY + disp16 4 100 IX 3 IX + disp8 3 IX + disp16 4 101 IY 3 IY + disp8 3 IY + disp16 4 110 Direct address 3 BP + disp8 3 BP + disp16 4 111 BW 3 BW + disp8 3 BW + disp16 4 “T” indicates the number of wait states. Use any number of waits starting at “0” (no wait). 38 µPD70325 (2) Number of clocks Table 2-9. Number of Clocks (1/10) Number of Clocks Group Data transfer Mnemonic MOV Byte Processing Operands Word Processing On-chip RAM Access Enable On-chip RAM Access Disable On-chip RAM Access Enable On-chip RAM Access Disable reg, reg’ 2 2 2 2 mem, reg EA + 4 + T EA + 2 EA + 6 + 2·T EA + 2 reg, mem EA + 6 + T EA + 6 + T EA + 8 + 2·T EA + 8 + 2·T mem, imm EA + 5 + T EA + 5 + T EA + 5 + 2·T EA + 5 + T 5 5 6 6 acc, dmem 9+T 9+T 11 + 2·T 11 + 2·T dmem, acc 7+T 5 9 + 2·T 5 sreg, reg16 — — 4 4 sreg, mem16 — — EA + 10 + 2·T EA + 10 + 2·T reg16, sreg — — 3 3 mem16, sreg — — EA + 7 + 2·T EA + 3 DS0, reg16, mem32 — — EA + 19 + 4·T EA + 19 + 4·T DS1, reg16, mem32 — — EA + 19 + 4·T EA + 19 + 4·T AH, PSW 2 2 — — PSW, AH 3 3 — — reg, imm LDEA reg16, mem16 — — EA + 2 EA + 2 TRANS src-table 10 + T 10 + T — — XCH reg, reg’ 3 3 3 3 EA + 10 + 2·T EA + 8 + 2·T EA + 14 + 2·T EA + 10 + 2·T — — 4 4 — — 16 16 — — 11 11 mem, reg/ reg, mem AW, reg16/ reg16, AW MOVSPA MOVSPB Repeat prefix Primitive block transfer reg16 REPC 2 2 2 2 REPNC 2 2 2 2 REP/REPE/ REPZ 2 2 2 2 REPNE/ REPNZ 2 2 2 2 MOVKB Note 1 Note 2 CMPKB Note 1 Note 2 dst-block, src-block dst-block, src-block 20 + 2·T 16 + T 24 + 4·T 20 + 2·T 16 + (16 + 2·T)·n 16 + (12 + T)·n 16 + (20 + 4·T)·n 16 + (12 + 2·T)·n 23 + 2·T 19 + T 27 + 4·T 21 + 4·T 16 + (21 + 2·T)·n 16 + (21 + 2·T)·n 16 + (25 + 4·T)·n 16 + (25 + 2·T)·n Notes 1. Not repeated 2. Repeated, n: number of transfer times (n ≥ 1) 39 µPD70325 Table 2-9. Number of Clocks (2/10) Number of Clocks Group Primitive block transfer Mnemonic CMPM Note 1 Note 2 LDM Note 1 STM tion INS EXT I/O IN On-chip RAM Access Enable On-chip RAM Access Disable 17 + T 19 + 2·T 19 + 2·T 16 + (15 + T)·n 16 + (15 + T)·n 16 + (17 + 2·T)·n 16 + (17 + 2·T)·n src-block 12 + T 12 + T 14 + 2·T 14 + 2·T 16 + (10 + T)·n 16 + (10 + T)·n 16 + (12 + 2·T)·n 16 + (12 + 2·T)·n 12 + T 10 14 + 2·T 10 16 + (8 + T)·n 16 + (6 + T)·n 16 + (10 + 2·T)·n 16 + (6 + 2·T)·n dst-block reg8, reg8’ 63 to 155 (The processing differs among bit lengths.) reg8, imm4 64 to 156 (The processing differs among bit lengths.) reg8, reg8’ 41 to 121 (The processing differs among bit lengths.) reg8, imm4 42 to 122 (The processing differs among bit lengths.) acc, imm8 14 + T 14 + T 16 + 2·T 16 + 2·T Note 3 acc, DW 13 + T 13 + T 15 + 2·T 15 + 2·T imm8, acc 10 + T 10 + T 10 + 2·T 10 + 2·T Note 3 DW, acc 9+T 9+T 9 + 2·T 9 + 2·T 19 + 2·T 17 + 2·T 21 + 4·T 17 + 4·T 18 + (13 + 2·T)·n 18 + (11 + 2·T)·n 18 + (15 + 4·T)·n 18 + (11 + 4·T)·n 19 + 2·T 17 + 2·T 21 + 4·T 17 + 4·T 18 + (13 + 2·T)·n 18 + (11 + 2·T)·n 18 + (15 + 4·T)·n 18 + (11 + 4·T)·n reg, reg’ 2 2 2 2 mem, reg EA + 8 + 2·T EA + 6 + T EA + 12 + 4·T EA + 8 + 2·T reg, mem EA + 6 + T EA + 6 + T EA + 8 + 2·T EA + 8 + 2·T reg, imm 5 5 6 6 OUT Primitive I/O On-chip RAM Access Disable 17 + T Note 2 Bit field manipula- INM dst-block, DW Note 3 OUTM DW, src-block Note 3 Addition/ ADD subtraction mem, imm ADDC EA + 9 + 2·T EA + 7 + 2·T EA + 14 + 4·T EA + 10 + 4·T acc, imm 5 5 6 6 reg, reg’ 2 2 2 2 mem, reg EA + 8 + 2·T EA + 6 + T EA + 12 + 4·T EA + 8 + 2·T reg, mem EA + 6 + T EA + 6 + T EA + 8 + 2·T EA + 8 + 2·T reg, imm 5 5 6 6 EA + 9 + 2·T EA + 7 + 2·T EA + 14 + 4·T EA + 10 + 4·T 5 5 6 6 mem, imm acc, imm Notes 1. Not repeated 2. Repeated, n: number of transfer times (n ≥ 1) 3. When IBRK = 1 40 Word Processing On-chip RAM Access Enable dst-block src-block Note 2 Note 1 Byte Processing Operands µPD70325 Table 2-9. Number of Clocks (3/10) Number of Clocks Group Mnemonic Addition/ SUB subtraction Operands On-chip RAM Access Disable On-chip RAM Access Enable On-chip RAM Access Disable reg, reg’ 2 2 2 2 mem, reg EA + 8 + 2·T EA + 6 + T EA + 12 + 4·T EA + 8 + 2·T reg, mem EA + 6 + T EA + 6 + T EA + 8 + 2·T EA + 8 + 2·T reg, imm 5 5 6 6 EA + 9 + 2·T EA + 7 + 2·T EA + 14 + 4·T EA + 10 + 4·T acc, imm 5 5 6 6 reg, reg’ 2 2 2 2 mem, reg EA + 8 + 2·T EA + 6 + T EA + 12 + 4·T EA + 8 + 2·T reg, mem EA + 6 + T EA + 6 + T EA + 8 + 2·T EA + 8 + 2·T reg, imm 5 5 6 6 EA + 9 + 2·T EA + 7 + 2·T EA + 14 + 4·T EA + 10 + 4·T mem, imm acc, imm BCD operation 5 5 6 6 ADD4S Note 22 + (27 + 3·T)·n 22 + (25 + 3·T)·n — — SUB4S Note 22 + (27 + 3·T)·n 22 + (25 + 3·T)·n — — CMP4S Note 22 + (23 + 3·T)·n 22 + (23 + 3·T)·n — — ROL4 reg8 17 17 — — EA + 18 + 2·T EA + 16 + 2·T — — 21 21 — — EA + 24 + 2·T EA + 22 + 2·T — — 5 5 — — mem8 EA + 11 + 2·T EA + 9 + 2·T EA + 15 + 4·T EA + 11 + 4·T reg16 — — 2 2 mem8 ROR4 reg8 mem8 Increment / INC decrement DEC Multiplication Word Processing On-chip RAM Access Enable mem, imm SUBC Byte Processing MULU reg8 5 5 — — mem8 reg8 EA + 11 + 2·T EA + 9 + 2·T EA + 15 + 4·T EA + 11 + 4·T reg16 — — 2 2 24 24 — — mem8 reg8 EA + 26 + T EA + 26 + T — — reg16 — — 32 32 mem16 — — EA + 34 + 2·T EA + 34 + 2·T Note n: 1/2 of the number of BCD digits 41 µPD70325 Table 2-9. Number of Clocks (4/10) Number of Clocks Byte Processing Group Multiplication Unsigned division Mnemonic MUL On-chip RAM Access Enable On-chip RAM Access Disable On-chip RAM Access Enable On-chip RAM Access Disable 31 to 40 31 to 40 — — EA + 33 + T to EA + 33 + T to — — EA + 42 + T EA + 42 + T reg16 — — 39 to 48 39 to 48 mem16 — — EA + 43 + 2·T to EA + 52 + 2·T EA + 43 + 2·T to EA + 52 + 2·T reg16, (reg16’,) imm8 — — 39 to 49 39 to 49 reg16, mem16, imm8 — — EA + 43 + 2·T to EA + 53 + 2·T EA + 43 + 2·T to EA + 53 + 2·T reg16, (reg16’,) imm16 — — 40 to 50 40 to 50 reg16, mem16, imm16 — — EA + 44 + 2·T to EA + 54 + 2·T EA + 44 + 2·T to EA + 54 + 2·T reg8 mem8 DIVU Word Processing Operands reg8 31 31 — — mem8 EA + 33 + T EA + 33 + T — — reg16 — — 39 39 mem16 — — EA + 43 + 2·T EA + 43 + 2·T 46 to 56 46 to 56 — — mem8 EA + 48 + T to EA + 58 + T EA + 48 + T to EA + 58 + T — — reg16 — — 54 to 64 54 to 64 mem16 — — EA + 58 + 2·T to EA + 68 + 2·T EA + 58 + 2·T to EA + 68 + 2·T BCD ADJBA adjustment ADJ4A 17 17 — — 9 9 — — ADJBS 17 17 — — ADJ4S 9 9 — — Data CVTBD conversion CVTDB 19 19 — — 20 20 — — Signed division Compare DIV reg8 CVTBW 3 3 — — CVTWL — — 8 8 reg, reg’ 2 2 2 2 mem, reg EA + 6 + T EA + 6 + T EA + 8 + 2·T EA + 8 + 2·T reg, mem EA + 6 + T EA + 6 + T EA + 8 + 2·T EA + 8 + 2·T reg, imm 5 5 6 6 EA + 7 + T EA + 7 + T EA + 10 + 2·T EA + 10 + 2·T 5 5 6 6 CMP mem, imm acc, imm 42 µPD70325 Table 2-9. Number of Clocks (5/10) Number of Clocks Group Comple ment operation Mnemonic NOT Operands reg mem NEG reg mem Logical operation TEST Byte Processing reg, reg’ Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable 5 5 5 5 EA + 11 + 2·T EA + 9 + T EA + 15 + 4·T EA + 11 + 2·T 5 5 5 5 EA + 11 + 2·T EA + 9 + T EA + 15 + 4·T EA + 11 + 2·T 4 4 4 4 EA + 8 + T EA + 8 + T EA + 10 + 2·T EA + 10 + 2·T 7 7 8 8 EA + 11 + T EA + 11 + T EA + 11 + 2·T EA + 11 + 2·T acc, imm 5 5 6 6 reg, reg’ 2 2 2 2 mem, reg EA + 8 + 2·T EA + 6 + T EA + 12 + 4·T EA + 8 + 2·T reg, mem EA + 6 + T EA + 6 + T EA + 8 + 2·T EA + 8 + 2·T reg, imm 5 5 6 6 EA + 9 + T EA + 7 + T EA + 14 + 4·T EA + 10 + 4·T 5 5 6 6 mem, reg/ reg, mem reg, imm mem, imm AND mem, imm acc, imm OR reg, reg’ 2 2 2 2 mem, reg EA + 8 + 2·T EA + 6 + T EA + 12 + 4·T EA + 8 + 2·T reg, mem EA + 6 + T EA + 6 + T EA + 8 + 2·T EA + 8 + 2·T reg, imm 5 5 6 6 EA + 9 + T EA + 7 + T EA + 14 + 4·T EA + 10 + 4·T acc, imm 5 5 6 6 reg, reg’ 2 2 2 2 mem, reg EA + 8 + 2·T EA + 6 + T EA + 12 + 4·T EA + 8 + 2·T reg, mem EA + 6 + T EA + 6 + T EA + 8 + 2·T EA + 8 + 2·T reg, imm 5 5 6 6 mem, imm XOR mem, imm Bit manipulation TEST1 NOT1 EA + 9 + T EA + 7 + T EA + 14 + 4·T EA + 10 + 4·T acc, imm 5 5 6 6 reg8, CL 7 7 — — mem8, CL EA + 11 + T EA + 11 + T — — reg16, CL — — 7 7 mem16, CL — — EA + 13 + 2·T EA + 13 + 2·T reg8, imm3 6 6 — — mem8, imm3 EA + 8 + T EA + 8 + T — — reg16, imm4 — — 6 6 mem16, imm4 — — EA + 10 + 2·T EA + 10 + 2·T 7 7 — — mem8, CL reg8, CL EA + 13 + 2·T EA + 11 + T — — reg16, CL — — 7 7 43 µPD70325 Table 2-9. Number of Clocks (6/10) Number of Clocks Byte Processing Group Bit manipulation Bit manipula- Mnemonic NOT1 mem16, CL reg8, imm3 On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable — — EA + 17 + 4·T EA + 13 + 2·T 6 6 — — mem8, imm3 EA + 10 + 2·T EA + 8 + T — — reg16, imm4 — — 6 6 mem16, imm4 — — EA + 14 + 4·T EA + 10 + 2·T NOT1 CY 2 2 2 2 CLR1 reg8, CL 8 8 — — mem8, CL EA + 14 + 2·T EA + 12 + T — — reg16, CL — — 8 8 mem16, CL — — EA + 18 + 4·T EA + 14 + 2·T reg8, imm3 7 7 — — mem8, imm3 EA + 11 + 2·T EA + 9 + T — — reg16, imm4 — — 7 7 mem16, imm4 — — EA + 15 + 4·T EA + 10 + 2·T reg8, CL 7 7 — — mem8, CL EA + 13 + 2·T EA + 11 + T — — reg16, CL — — 7 7 mem16, CL — — EA + 17 + 4·T EA + 13 + 2·T tion SET1 reg8, imm3 6 6 — — mem8, imm3 EA + 10 + 2·T EA + 8 + T — — reg16, imm4 — — 6 6 mem16, imm4 — — EA + 14 + 4·T EA + 10 + 2·T CY 2 2 2 2 DIR 2 2 2 2 SET1 CY 2 2 2 2 DIR 2 2 2 2 SHL reg,1 8 8 8 8 mem, 1 EA + 14 + 2·T EA + 12 + T EA + 18 + 4·T EA + 14 + 2·T reg, CL 11 + 2·n 11 + 2·n 11 + 2·n 11 + 2·n CLR1 Shift Word Processing Operands mem, CL EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n Note reg, imm8 mem, imm8 SHR reg, 1 mem, 1 Note n: Shift count 44 9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n 8 8 8 8 EA + 14 + 2·T EA + 12 + T EA + 18 + 4·T EA + 14 + 2·T µPD70325 Table 2-9. Number of Clocks (7/10) Number of Clocks Group Shift Mnemonic SHR Byte Processing Operands reg, CL mem, CL Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable 11 + 2·n 11 + 2·n 11 + 2·n 11 + 2·n EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n Note reg, imm8 mem, imm8 SHRA reg,1 9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n 8 8 8 8 mem, 1 EA + 14 + 2·T EA + 12 + T EA + 18 + 4·T EA + 14 + 2·T reg, CL 11 + 2·n 11 + 2·n 11 + 2·n 11 + 2·n mem, CL EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n Note reg, imm8 mem, imm8 Rotate ROL reg,1 9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n 8 8 8 8 mem, 1 EA + 14 + 2·T EA + 12 + T EA + 18 + 4·T EA + 14 + 2·T reg, CL 11 + 2·n 11 + 2·n 11 + 2·n 11 + 2·n mem, CL EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n Note reg, imm8 mem, imm8 ROR reg,1 mem, 1 reg, CL mem, CL 9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n 8 8 8 8 EA + 14 + 2·T EA + 12 + T EA + 18 + 4·T EA + 14 + 2·T 11 + 2·n 11 + 2·n 11 + 2·n 11 + 2·n EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n Note reg, imm8 mem, imm8 ROLC reg,1 9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n 8 8 8 8 mem, 1 EA + 14 + 2·T EA + 12 + T EA + 18 + 4·T EA + 14 + 2·T reg, CL 11 + 2·n 11 + 2·n 11 + 2·n 11 + 2·n mem, CL EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n Note reg, imm8 mem, imm8 RORC reg,1 mem, 1 9 + 2·n 9 + 2·n 9 + 2·n 9 + 2·n EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n 8 8 8 8 EA + 14 + 2·T EA + 12 + T EA + 18 + 4·T EA + 14 + 2·T Note n: Shift count 45 µPD70325 Table 2-9. Number of Clocks (8/10) Number of Clocks Group Rotate Mnemonic RORC Byte Processing Operands reg, CL mem, CL Word Processing On-chip RAM Access Enable On-chip RAM Access Disable On-chip RAM Access Enable On-chip RAM Access Disable 11 + 2·n 11 + 2·n 11 + 2·n 11 + 2·n EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n Note 1 reg, imm8 mem, imm8 Subroutine CALL control 9 + 2·n near-proc — POP PREPARE Note 2 — 22 + 2·T 18 + 2·T — — 22 + 2·T 18 + 2·T memptr16 — — EA + 26 + 4·T EA + 24 + 4·T far-proc — — 38 + 4·T 34 + 4·T memptr32 — — EA + 36 + 8·T EA + 24 + 8·T — — 20 + 2·T 20 + 2·T — — 20 + 2·T 20 + 2·T — — 29 + 4·T 29 + 4·T pop-value — — 30 + 4·T 30 + 4·T mem16 — — EA + 18 + 4·T EA + 14 + 4·T reg16 — — 10 + 2·T 6 sreg — — 11 + 2·T 7 PSW — — 10 + 2·T 6 R — — 82 + 16·T 50 imm8 — — 13 + 2·T 9 imm16 — — 14 + 2·T 10 mem16 — — EA + 16 + 4·T EA + 12 + 2·T reg16 — — 12 + 2·T 12 + 2·T sreg — — 13 + 2·T 13 + 2·T PSW — — 14 + 2·T 14 + 2·T R — — 82 + 16·T 58 imm16, imm8 When imm8 = 0, 27 + 2·T When imm8 = 1, 39 + 4·T When imm8 = n, n > 1, 46 + 19(n – 1) + 4·T DISPOSE Notes 1. n: Shift count 2. Depth of procedure block (lexical level) 46 9 + 2·n regptr16 pop-value PUSH 9 + 2·n EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n RET Stack manipulation 9 + 2·n — — 12 + 2·T 12 + 2·T µPD70325 Table 2-9. Number of Clocks (9/10) Number of Clocks Byte Processing Group Branch Mnemonic BR near-label On-chip RAM Access Enable On-chip RAM Access Disable On-chip RAM Access Enable On-chip RAM Access Disable — — 12 12 short-label — — 12 12 regptr16 — — 13 13 memptr16 — — EA + 17 + 2·T EA + 17 + 2·T far-label — — 15 15 memptr32 — — EA + 25 + 4·T EA + 25 + 4·T short-label — — 15/8 15/8 short-label — — 15/8 15/8 BC/BL short-label — — 15/8 15/8 BNC/BNL short-label — — 15/8 15/8 BE/BZ short-label — — 15/8 15/8 BNE/BNZ short-label — — 15/8 15/8 BNH short-label — — 15/8 15/8 BH short-label — — 15/8 15/8 BN short-label — — 15/8 15/8 BP short-label — — 15/8 15/8 BPE short-label — — 15/8 15/8 BPO short-label — — 15/8 15/8 BLT short-label — — 15/8 15/8 Conditional BV branchNote BNV Interrupt Word Processing Operands BGE short-label — — 15/8 15/8 BLE short-label — — 15/8 15/8 BGT short-label — — 15/8 15/8 DBNZNE short-label — — 17/8 17/8 DBNZE short-label — — 17/8 17/8 DBNZ short-label — — 17/8 17/8 BCWZ short-label — — 15/8 15/8 BTCLR sfr, imm3, short-label 29/21 29/21 — — BRK 3 — — 55 + 10·T 43 + 10·T imm8 (≠ 3) — — 56 + 10·T 44 + 10·T BRKV — — 55 + 10·T 43 + 10·T RETI — — 45 + 6·T 37 + 2·T RETRBI — — 12 12 FINT 2 2 2 2 — — EA + 26 + 4·T EA + 26 + 4·T CHKIND reg16, mem32 Note In the number of clocks, the value on the left side of / indicates the number of clocks when the condition is true, and the value on the right side indicates the number of clocks when the condition is false. 47 µPD70325 Table 2-9. Number of Clocks (10/10) Number of Clocks Group Mnemonic Byte Processing Operands On-chip RAM Access Enable Register BRKCS bank switch TSKSW CPU control On-chip RAM Access Disable On-chip RAM Access Enable On-chip RAM Access Disable reg16 — — 15 15 reg16 — — 20 20 HALT — — — — STOP — — — — POLL — — — — DI 4 4 4 4 EI 12 12 12 12 BUSLOCK FPO1 FPO2 NOP Segment override prefix (DS0:, DS1:, PS: and SS:) 48 Word Processing 2 2 2 2 fp-op — — 60 + 10·T 48 + 10·T fp-op, mem — — 60 + 10·T 48 + 10·T fp-op — — 60 + 10·T 48 + 10·T fp-op, mem — — 60 + 10·T 48 + 10·T 4 4 4 4 2 2 2 2 µPD70325 3. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Parameter Rating Unit VDD – 0.5 to +7.0 V VTH – 0.5 to VDD + 0.5 V Input Voltage VI – 0.5 to VDD + 0.5 V Output Voltage VO Output Current Low IOL Supply Voltage Output Current High Symbol IOH Test Conditions – 0.5 to VDD + 0.5 V Each output pin 4.0 mA Total 50 mA Each output pin –2.0 mA Total –20 mA Operating Ambient Temperature TA –10 to +70 °C Storage Temperature Tstg – 65 to +150 °C Cautions 1. Do not make direct connections of the output (or input/output) pins of the IC product with each other, and also avoid direct connections to VDD, VCC or GND. However, the open drain pins or the open collector pins can be directly connected with each other. For the external circuit designed with the timing specifications so that any collision of the outputs from the pins subject to high-impedance state may be prevented, direct connection can be also made. 2. Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. The normal operation and reliability of the product can be only assured with the specifications and the conditions indicated as the DC and AC characteristics. 49 µPD70325 OSCILLATOR CHARACTERISTICS µPD70325-8 (TA = –10 to +70°C, VDD = +5.0 V ±10%, VSS = 0 V, 0 V ≤ VTH ≤ VDD + 0.1 V) µPD70325-10 (TA = –10 to +70°C, VDD = +5.0 V ±5%, VSS = 0 V, 0 V ≤ VTH ≤ VDD + 0.1 V) Resonator Recommended Circuit Ceramic or Crystal Resonator X1 X2 C1 External Clock 1 Parameter µPD70325-8 µPD70325-10 Unit MIN. MAX. MIN. MAX. Oscillation frequency (fXX) 4 16 4 20 MHz X1 input frequency (fX) 4 16 4 20 MHz X1 input rise/ fall time (tXR, tXF) 0 20 0 15 ns X1 input high-/ low-level width (tWXH, tWXL) 20 C2 X1 X2 HCMOS Inverter or 2 X1 X2 Open HCMOS Inverter 16 Cautions 1. Mount the oscillation circuit as close to pins X1 and X2 as possible. 2. Do not route other signal lines through the area within the dotted line. RECOMMENDED OSCILLATOR CONSTANT (1) The following ceramic resonator and external capacity are recommended. Manufacturer Murata Mfg. Co., Ltd. TDK Part Number CSA16.00MX040 Recommended Constants C1 [pF] C2 [pF] 30 30 CSA20.00MX040 10 10 FCR16.0M2G 30 30 (2) The following crystal resonator and external capacity are recommended. Manufacturer Kinseki Co., Ltd. Part Number Recommended Constants C1 [pF] C2 [pF] HC-49/U(KR-100) 22 22 HC-49/U(KR-160) 22 22 HC-49/U(KR-200) 22 22 Remark For more details on the characteristics of the resonators, please contact the manufacturer. 50 ns µPD70325 CAPACITANCE (TA = 25°C, VDD = 0 V) Parameter Symbol Input Capacitance CI Output Capacitance CO Input/output Capacitance CIO Test Conditions MIN. TYP. fC = 1 MHz Unmeasured pins returned to 0 V. MAX. Unit 10 pF 20 pF 20 pF MAX. Unit 0.8 V 2.2 VDD V 0.8VDD VDD V 0.45 V DC CHARACTERISTICS µPD70325-8 (TA = –10 to +70°C, VDD = +5.0 V ±10%) µPD70325-10 (TA = –10 to +70°C, VDD = +5.0 V ±5%) Parameter Input Voltage Low Input Voltage High Symbol Test Conditions MIN. VIL TYP. 0 VIH1 Except RESET, P10/NMI, X1, X2 VIH2 RESET, P10/NMI, X1, X2 Output Voltage Low VOL IOL = 1.6 mA Output Voltage High VOH IOH = –0.4 mA Input Current II EA, P10/NMI; 0 ≤ VI ≤ VDD ±20 µA Input Leakage Current ILI Except EA, P10/NMI; 0 ≤ VI ≤ VDD ±10 µA Output Leakage Current ILO 0 ≤ VO ≤ VDD ±10 µA VTH Current ITH 0 V ≤ VTH ≤ VDD VDD Supply Current IDD1 Operating mode IDD2 IDD3 HALT mode VDD – 1.0 V 0.5 1.0 mA µPD70325-8 65 120 mA µPD70325-10 95 130 mA µPD70325-8 25 50 mA µPD70325-10 30 55 mA 10 30 µA STOP mode AC CHARACTERISTICS (1) µPD70325-8 (TA = –10 to +70°C, VDD = +5.0 V ±10%) Parameter Symbol Test Conditions MIN. MAX. 250 X1 Input Cycle Time tCYX 62 X1 Input High-/Low-Level Width tWXH, tWXL 20 X1 Input Rise/Fall Time tXR, tXF CLKOUT Output Cycle Time tCYK CLKOUT Output High-/Low-Level Width tWKH, tWKL CLKOUT Output Rise/Fall Time tKR, tKF Input Rise/Fall Time tIR, tIF Output Rise/Fall Time fX /2, T = tCYK 125 Unit ns ns 20 ns 2000 ns 0.5T – 15 ns 15 ns Except RESET, NMI, X1 and X2 20 ns tIRS, tIFS RESET, NMI 30 ns tOR, tOF Except CLKOUT 20 ns 51 µPD70325 Parameter Address Delay Time from CLKOUT Symbol Test Conditions tDKA MIN. MAX. Unit 15 90 ns Data Input Delay Time from Address tDADR (n + 1.5)T – 70 ns Data Delay Time from MREQ ↓ tDMRD (n + 1)T – 60 ns Data Delay Time from MSTB ↓ tDMSD (n + 0.5)T – 60 ns MSTB ↓ Delay Time from MREQ ↓ tDMRMS 0.5T – 35 0.5T + 35 ns MREQ Low-Level Width tWMRL (n + 1)T – 30 (n + 1)T + 30 ns Address Hold Time (from MREQ ↑) tHMA 0.5T – 30 ns Data Input Hold Time (from MREQ ↑) tHMDR 0 ns Control Signal Recovery Time tRVC Data Output Delay Time from Address tDADW 0.5T – 35 Address Setup Time (to MREQ ↓) tDAMR 0.5T – 30 Address Setup Time (to MSTB ↓) tDAMS T – 30 MSTB Low-Level Width tWMSL (n + 0.5)T – 30 Data Output Setup Time (to MSTB ↑) tSDM (n + 1)T – 50 ns Data Output Hold Time (from MSTB ↑) tHMDW 0.5T – 30 ns Address Setup Time (to IOSTB ↓) tDAIS 0.5T – 30 ns Data Delay Time from IOSTB ↓ tDISD IOSTB Low-Level Width tWISL (n + 1)T – 30 ns Address Hold Time (from IOSTB ↑) tHISA 0.5T – 30 ns Data Input Hold Time (from IOREQ ↑) tHISDR 0 ns Data Output Setup Time (to IOSTB ↑) tSDIS (n + 1)T – 50 ns Data Output Hold Time (from IOSTB ↑) tHISDW DMARQ Setup Time (to MREQ ↓) tSDADQ Demand release mode, n ≥ 2 DMARQ Hold Time (from DMAAK ↓) tHDADQ Demand release mode DMAAK Output Low-Level Width tWDMRL Read operation TC ↓ Delay Time from DMAAK ↓ tDDATC TC Low-Level Width tWTCL DMAAK Output Low-Level Width tWDMWL Address Setup Time (to REFRQ ↓) tDARF 0.5T – 30 ns REFRQ Low-Level Width tWRFL (n + 1)T – 30 ns Address Hold Time (from REFRQ ↑) tHRFA 0.5T – 30 ns RESET Low-Level Width tWRSL1 STOP mode release/ power-ON reset 30 ms tWRSL2 System reset 5 tSCRY0 n≥2 T – 100 ns tSCRY n≥3 (n – 1)T – 100 ns READY Setup Time (to MREQ ↓, IOSTB ↓) T – 25 ns (n + 0.5)T + 30 0.5T – 30 ns ns ns (n – 1)T – 50 ns 0 ns (n + 1.5)T – 30 ns 0.5T + 50 Write operation ns ns (n + 1)T – 60 Remark n indicates the number of wait states. No wait is “n = 0”. 52 ns 0.5T + 50 ns (n + 2)T – 30 ns (n + 1)T – 30 ns µs µPD70325 Parameter READY Hold Time (from MREQ ↓, IOSTB ↓) Symbol Test Conditions MIN. MAX. Unit tHCRY0 n=2 T ns tHCRY n≥3 (n – 1)T ns tHCRY1 n≥3 (n – 2)T ns 30 ns HLDRQ Setup Time (to CLKOUT ↑) tSHQK HLDAK ↓ Delay Time from CLKOUT ↑ tDKHA 15 HLDAK ↓ Delay Time from Bus Float tCFHA T – 50 ns Bus Output Delay Time from HLDAK ↑ tDHAC T – 50 ns HLDAK ↑ Delay Time from HLDRQ ↓ tDHQHA Bus Output Delay Time from HLDRQ ↓ tDHQC 3T + 30 ns HLDRQ Low-Level Width tWHQL 1.5T ns HLDAK Low-Level Width tWHAL T ns INT, DMARQ Setup Time (to CLKOUT ↑) tSIQK 30 ns INT, DMARQ High-/Low-Level Width tWIQH, tWIQL 8T ns POLL Setup Time (to CLKOUT ↑) tSPLK 30 ns NMI High-/Low-Level Width tWNIH, tWNIL 5 µs CTS Low-Level Width tWCTL 2T ns INT Setup Time (to CLKOUT ↑) tSIRK 30 ns INTAK ↓ Delay Time from CLKOUT ↓ tDKIA 15 INT Hold Time (from INTAK ↓) tHIAIQ 0 ns INTAK Low-Level Width tWIAL 2T – 30 ns INTAK High-Level Width tWIAH T – 30 ns Data Delay Time from INTAK ↓ tDIAD Data Hold Time (from INTAK ↑) tHIAD 0 SCK0 Cycle Time tCYTK 1000 ns SCK0 High-/Low-Level Width tWSTH, tWSTL 450 ns TxD Delay Time from SCK0 ↓ tDTKD TxD Hold Time (from SCK0 ↓) tHTKD 20 ns CTS0 Cycle Time tCYRK 1000 ns CTS0 High-/Low-Level Width tWSRH, tWSRL 420 ns RxD Setup/Hold Time (to/from CTS0 ↑) tSRDK, tHKRD 80 ns 80 3T + 160 80 ns ns ns 2T – 130 ns 0.5T ns 210 ns Remark n indicates the number of wait states. No wait is “n = 0”. 53 µPD70325 (2) µPD70325-10 (TA = –10 to +70°C, VDD = +5.0 V ±5%) Parameter MIN. MAX. Unit tCYX 49 250 ns X1 Input High-/Low-Level Width tWXH, tWXL 16 X1 Input Rise/Fall Time tXR, tXF CLKOUT Output Cycle Time tCYK X1 Input Cycle Time Symbol Test Conditions fX /2, T = tCYK CLKOUT Output High-/Low-Level Width tWKH, tWKL 100 ns 15 ns 2000 ns 12 ns 0.5T – 12 ns CLKOUT Output Rise/Fall Time tKR, tKF Input Rise/Fall Time tIR, tIF Except RESET, NMI, X1 and X2 20 ns tIRS, tIFS RESET, NMI 30 ns Output Rise/Fall Time tOR, tOF Except CLKOUT Address Delay Time from CLKOUT tDKA Data Input Delay Time from Address tDADR Data Delay Time from MREQ ↓ tDMRD (n + 1)T – 50 ns Data Delay Time from MSTB ↓ tDMSD (n + 0.5)T – 50 ns MSTB ↓ Delay Time from MREQ ↓ tDMRMS 0.5T – 20 0.5T + 30 ns MREQ Low-Level Width tWMRL (n + 1)T – 25 (n + 1)T + 25 ns Address Hold Time (from MREQ ↑) tHMA 0.5T – 30 ns Data Input Hold Time (from MREQ ↑) tHMDR 0 ns Control Signal Recovery Time tRVC T – 25 ns Data Output Delay Time from Address tDADW 0.5T – 30 Address Setup Time (to MREQ ↓) tDAMR 0.5T – 30 ns Address Setup Time (to MSTB ↓) tDAMS T – 30 ns MSTB Low-Level Width tWMSL (n + 0.5)T – 25 Data Output Setup Time (to MSTB ↑) tSDM (n + 1)T – 50 ns Data Output Hold Time (from MSTB ↑) tHMDW 0.5T – 30 ns Address Setup Time (to IOSTB ↓) tDAIS 0.5T – 30 ns Data Delay Time from IOSTB ↓ tDISD IOSTB Low-Level Width tWISL (n + 1)T – 25 ns Address Hold Time (from IOSTB ↑) tHISA 0.5T – 30 ns Data Input Hold Time (from IOREQ ↑) tHISDR 0 ns Data Output Setup Time (to IOSTB ↑) tSDIS (n + 1)T – 50 ns Data Output Hold Time (from IOSTB ↑) tHISDW 0.5T – 30 ns DMARQ Setup Time (to MREQ ↓) tSDADQ Demand release mode, n ≥ 2 DMARQ Hold Time (from DMAAK ↓) tHDADQ Demand release mode DMAAK Output Low-Level Width tWDMRL Read operation TC ↓ Delay Time from DMAAK ↓ tDDATC TC Low-Level Width tWTCL DMAAK Output Low-Level Width tWDMWL Address Setup Time (to REFRQ ↓) 15 15 ns 75 ns (n + 1.5)T – 60 ns 0.5T + 50 (n + 0.5)T + 25 (n + 1)T – 50 (n – 1)T – 50 ns ns ns ns 0 ns (n + 1.5)T – 25 ns 0.5T + 35 ns (n + 2)T – 25 ns (n + 1)T – 25 ns tDARF 0.5T – 30 ns REFRQ Low-Level Width tWRFL (n + 1)T – 25 ns Address Hold Time (from REFRQ ↑) tHRFA 0.5T – 30 ns Write operation Remark n indicates the number of wait states. No wait is “n = 0”. 54 µPD70325 Parameter RESET Low-Level Width Symbol Test Conditions MIN. MAX. Unit tWRSL1 STOP mode release/ power-ON reset 30 ms tWRSL2 System reset 5 µs READY Setup Time (to MREQ ↓, IOSTB ↓) tSCRY0 n≥2 T – 80 ns tSCRY n≥3 (n – 1)T – 80 ns READY Hold Time (from MREQ ↓, IOSTB ↓) tHCRY0 n=2 T ns tHCRY n≥3 (n – 1)T ns tHCRY1 n≥3 (n – 2)T ns HLDRQ Setup Time (to CLKOUT ↑) tSHQK 25 HLDAK ↓ Delay Time from CLKOUT ↑ tDKHA 15 HLDAK ↓ Delay Time from Bus Float tCFHA T – 35 ns Bus Output Delay Time from HLDAK ↑ tDHAC T – 35 ns HLDAK ↑ Delay Time from HLDRQ ↓ tDHQHA Bus Output Delay Time from HLDRQ ↓ tDHQC 3T + 30 ns HLDRQ Low-Level Width tWHQL 1.5T ns HLDAK Low-Level Width tWHAL ns 70 3T + 160 ns ns T ns INT, DMARQ Setup Time (to CLKOUT ↑) tSIQK 25 ns INT, DMARQ High-/Low-Level Width tWIQH, tWIQL 8T ns POLL Setup Time (to CLKOUT ↑) tSPLK 25 ns NMI High-/Low-Level Width tWNIH, tWNIL 5 µs CTS Low-Level Width tWCTL 2T ns INT Setup Time (to CLKOUT ↑) tSIRK 25 ns INTAK ↓ Delay Time from CLKOUT ↓ tDKIA 15 INT Hold Time (from INTAK ↓) tHIAIQ 0 ns INTAK Low-Level Width tWIAL 2T – 25 ns INTAK High-Level Width tWIAH T – 25 ns Data Delay Time from INTAK ↓ tDIAD Data Hold Time (from INTAK ↑) tHIAD 0 SCK0 Cycle Time tCYTK 1000 SCK0 High-/Low-Level Width tWSTH, tWSTL 450 TxD Delay Time from SCK0 ↓ tDTKD TxD Hold Time (from SCK0 ↓) tHTKD 20 ns CTS0 Cycle Time tCYRK 1000 ns CTS0 High-/Low-Level Width tWSRH, tWSRL 420 ns RxD Setup/Hold Time (to/from CTS0 ↑) tSRDK, tHKRD 80 ns 70 ns 2T – 100 ns 0.5T ns ns ns 210 ns Remark n indicates the number of wait states. No wait is “n = 0”. 55 µPD70325 COMPARATOR CHARACTERISTICS µPD70325-8 (TA = –10 to +70°C, VDD = +5.0 V ±10%) µPD70325-10 (TA = –10 to +70°C, VDD = +5.0 V ±5%) Parameter Symbol Test Conditions MIN. MAX. Unit ±100 mV VDD + 0.1 V 64 65 tCYK 0 VDD V Comparator Accuracy VACOMP Threshold Voltage VTH 0 Compare Time tCOMP PT Input Voltage VIPT TYP. DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA HOLDING CHARACTERISTICS (TA = –10 to +70°C) MIN. MAX. Unit Data Hold Supply Voltage Parameter VDDDR 2.5 5.5 V VDD Rise/Fall Time tRVD, tFVD 200 56 Symbol Test Conditions µs µPD70325 DATA HOLDING TIMING 90% 10% VDDDR tFVD tRVD AC TEST INPUT WAVEFORM (Except RESET, NMI, X1 and X2) 2.2 V 2.2 V Test Points 0.8 V 0.8 V tIF tIR AC TEST INPUT WAVEFORM (RESET, NMI, X1 and X2) 0.8 VDD 0.8 VDD Test Points 0.8 V 0.8 V tIFS tIRS AC TEST OUTPUT TEST POINTS Output load condition: 100 pF 2.2 V 2.2 V Test Points 0.8 V 0.8 V LOAD CONDITION DUT CL = 100 pF Caution When the load capacity exceeds 100 pF depending on the circuit configuration, make the load capacity of this device less than 100 pF by inserting a buffer, etc. 57 µPD70325 CLOCK TIMING tCYX 0.8 VDD X1 0.8 V tWXH tXR tWXL tXF tCYK 2.2 V CLKOUT 0.8 V tWKH tKR tWKL tKF POLL INPUT TIMING CLKOUT tSPLK tSPLK POLL CTS0 AND CTS1 INPUT TIMING tWCTL CTS0 and CTS1 58 µPD70325 INTERRUPT INPUT/DMA INPUT TIMING CLKOUT tWNIH tWNIL NMI tSIQK tSIQK Note tWIQH tWIQL Note INTP0 to INTP2, DMARQ0 to DMARQ1 RESET INPUT TIMING When STOP mode is released/at power-on reset: CLKOUTNote Hi-Z tWRSL1 RESET Note CLKOUT signal is output after CLKOUT output is set. When system is reset: Hi-Z CLKOUTNote tWRSL2 RESET Note CLKOUT output is set to input port by RESET input. 59 µPD70325 READY TIMING When 2 wait states are inserted: T1 TAW TAW T2 MREQNote 1 IOSTBNote 2 tHCRY0 tSCRY0 READY When (n – 2) extra wait states are inserted [n ≥ 3]: T1 TAW TAW TW × (n – 2) T2 MREQNote 1 IOSTBNote 2 tHCRY tHCRY1 tSCRY tSCRY0 READY Notes 1. In case of memory cycle 2. In case of I/O cycle Caution The wait state insertion by the external READY signal is necessary to make the value of wait control register (WTC) “11” (2 waits + insertion state by READY pin). 60 µPD70325 SERIAL OPERATION When transmitting data in I/O interface mode tCYTK tWSTL tWSTH SCK0 tDTKD tHTKD TxD When receiving data in I/O interface mode tCYRK tWSRL tWSRH CTS0 RxD tSRDK tHKRD 61 µPD70325 READ OPERATION tCYK CLKOUT tDKA tDKA A19 to A0 tDADR tHMA Hi-Z D7 to D0 Hi-Z tDMRD tHMDR R/W tDAMR tWMRL tRVC MREQ tDMRMS tDMSD MSTB tDAMS IOSTB REFRQ DMAAK1 to DMAAK0 62 tWMSL µPD70325 WRITE OPERATION tCYK CLKOUT tDKA tDKA A19 to A0 tDADW D7 to D0 tHMA Hi-Z Hi-Z tSDM tHMDW R/ W tDAMR tWMRL tRVC MREQ tDMRMS MSTB tDAMS tWMSL IOSTB REFRQ DMAAK1 to DMAAK0 63 µPD70325 I/O READ TIMING tCYK CLKOUT tDKA tDKA A19 to A0 tDADR tHISA Hi-Z D7 to D0 Hi-Z tDISD tHISDR R/ W MREQ MSTB H tDAIS IOSTB REFRQ DMAAK1 to DMAAK0 64 tWISL tRVC µPD70325 I/O WRITE TIMING tCYK CLKOUT tDKA tDKA A19 to A0 tDADW tHISA Hi-Z Hi-Z D7 to D0 tSDIS tHISDW R/ W MREQ MSTB H tDAIS tWISL tRVC IOSTB REFRQ DMAAK1 to DMAAK0 65 µPD70325 DMA (I/O → MEMORY) TIMING tCYK CLKOUT tDKA A19 to A0 Hi-Z D7 to D0 R/W tDAMR tWMRL tHMA MREQ tRVC tDMRMS MSTB tDAMS tWMSL IOSTB tSDADQ DMARQ1 to DMARQ0 tHDADQ DMAAK1 to DMAAK0 tWDMRL TC1 to TC0 tDDATC 66 tWTCL µPD70325 DMA (MEMORY → I/O) TIMING tCYK CLKOUT tDKA A19 to A0 Hi-Z D7 to D0 R/W tDAMR tWMRL tHMA MREQ tRVC MSTB tDAMS tWMSL IOSTB tSDADQ DMARQ1 to DMARQ0 tHDADQ DMAAK1 to DMAAK0 tWDMWL TC1 to TC0 tDDATC tWTCL 67 µPD70325 REFRESH TIMING tCYK CLKOUT tDKA A19 to A0 Hi-Z D7 to D0 R/ W MREQ MSTB H IOSTB tDARF tWRFL tHRFA REFRQ tRVC DMAAK1 to DMAAK0 68 µPD70325 HOLD REQUEST/ACKNOWLEDGE TIMING Normal mode CLKOUT tSHQK tSHQK HLDRQ tDKHA tWHQL Hi-Z Note tDHAC tCFHA tDHQHA HLDAK tWHAL Releasing HOLD mode at refreshing time CLKOUT tSHQK HLDRQ tWHQL Hi-Z Note tDHQC tDKHA HLDAK Note A19 to A0, D7 to D0, MREQ, MSTB, IOSTB, R/W EXTERNAL INTERRUPT REQUEST/ACKNOWLEDGE TIMING CLKOUT tSIRK INT tDKIA tHIAIQ INTAK tWIAL D0 to D7 tWIAH tDIAD tHIAD Hi-Z tRVC tRVC MREQ IOSTB 69 µPD70325 CLOCK SYNCHRONIZATION TIMING The V25 Family is designed to create access signals to memory and I/O, based on the MREQ signal and IOSTB signal. When V25 Family products are connected with memory and I/O, design is possible even if there are no AC characteristics based on the clock. The clock synchronization timing shown below is for executing accurate READY input control using the system clock. (1) µPD70325-8 (TA = –10 to +70°C, VDD = +5.0 V ±10%) Parameter MIN. MAX. Unit tDKD 65 115 ns Data Input Setup Time tSDK 15 ns Data Input Hold Time tHKD 40 ns MREQ Delay Time tDKMR 10 55 ns IOSTB Delay Time tDKIS 10 55 ns READY Setup Time tSRYK 20 ns READY Hold Time tHKRY 40 ns Data Delay Time from CLKOUT Symbol Test Conditions (2) µPD70325-10 (TA = –10 to +70°C, VDD = +5.0 V ±5%) Parameter Symbol Test Conditions MIN. MAX. Unit 110 ns Data Delay Time from CLKOUT tDKD 60 Data Input Setup Time tSDK 10 Data Input Hold Time tHKD 35 MREQ Delay Time tDKMR 10 55 ns IOSTB Delay Time tDKIS 10 55 ns READY Setup Time tSRYK 15 ns READY Hold Time tHKRY 40 ns 70 ns ns µPD70325 READY TIMING When 2 wait states are inserted: T1 TAW TAW T2 CLKOUT A19 to A0 MREQ IOSTB tSRYK tHKRY READY When 1 extra wait state is inserted: T1 TAW TAW TW T2 CLKOUT A19 to A0 MREQ IOSTB tSRYK tSRYK READY tHKRY tHKRY 71 µPD70325 MEMORY READ OPERATION tCYK CLKOUT tDKA tDKA A19 to A0 tSDK D7 to D0 tHKD Hi-Z Hi-Z R/W tDKMR tDKMR tDKMR MREQ MEMORY WRITE OPERATION tCYK CLKOUT tDKA tDKA A19 to A0 tDKD D7 to D0 Hi-Z Hi-Z R/W tDKMR MREQ 72 tDKMR tDKMR µPD70325 I/O READ TIMING tCYK CLKOUT tDKA tDKA A19 to A0 tSDK D7 to D0 tHKD Hi-Z Hi-Z R/W tDKMR MREQ tDKIS tDKIS tDKIS IOSTB I/O WRITE TIMING tCYK CLKOUT tDKA tDKA A19 to A0 tDKD D7 to D0 Hi-Z Hi-Z R/W tDKMR MREQ tDKIS tDKIS tDKIS IOSTB 73 µPD70325 4. PACKAGE DRAWINGS 94 PIN PLASTIC QFP ( 20) F2 A B 71 72 48 47 F1 Q R S C D detail of lead end 94 1 G1 24 23 G2 H I M J M P K N L NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.2±0.4 0.913 +0.017 –0.016 B 20.0±0.2 0.787 +0.009 –0.008 C 20.0±0.2 0.787 +0.009 –0.008 D 23.2±0.4 0.913 +0.017 –0.016 F1 1.6 0.063 F2 0.8 0.031 G1 1.6 0.063 G2 0.8 0.031 H 0.35±0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.6±0.2 0.063±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P Q 3.7 0.146 R 0.1±0.1 5°±5° 0.004±0.004 5°±5° S 4.0 MAX. 0.158 MAX. S94GJ-80-5BG-3 74 µPD70325 84 PIN PLASTIC QFJ ( 1150 mil) A C F E G H U J 84 1 D B T I Q K M N M P84L-50A3-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 30.2 ± 0.2 1.189 ± 0.008 B 29.28 1.153 C 29.28 1.153 D 30.2 ± 0.2 1.189 ± 0.008 E 1.94 ± 0.15 0.076+0.007 –0.006 F 0.6 0.024 G 4.4 ± 0.2 0.173+0.009 –0.008 H 2.8 ± 0.2 0.110 –0.008 +0.009 I 0.9 MIN. 0.035 MIN. J 3.4 0.134 K 1.27 (T.P.) 0.050 (T.P.) M 0.40 ± 0.10 0.016+0.004 –0.005 N 0.12 0.005 P 28.20 ± 0.20 1.110 +0.009 –0.008 Q 0.15 0.006 T R 0.8 R 0.031 U 0.20+0.10 –0.05 0.008+0.004 –0.002 75 µPD70325 5. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met when soldering this product. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales office when using other soldering process or under different soldering conditions. Table 5-1. Surface Mount Type Soldering Conditions (1) µPD70325GJ-8-5BG : 94-pin plastic QFP (20 × 20 mm) µPD70325GJ-10-5BG : 94-pin plastic QFP (20 × 20 mm) Soldering Conditions Symbol Infrared ray reflow Soldering Process Package peak temperature: 235°C, Reflow time: 30 seconds or less (at 210°C or higher), Number of reflow processes: 3 or less Exposure limitNote: 7 days (36 hours pre-baking is required at 125°C afterwards) IR35-367-3 VPS Package peak temperature: 215°C, Reflow time: 40 seconds or less (at 200°C or higher), Number of reflow processes: 3 or less Exposure limitNote: 7 days (36 hours pre-baking is required at 125°C afterwards) VP15-367-3 Wave soldering Solder temperature: 260°C or below, Flow time: 10 seconds or less, Number of flow processes: 1 Exposure limitNote: 7 days (36 hours pre-baking is required at 125°C afterwards) WS60-367-1 Pre-heating temperature: 120°C max. (package surface temperature) Partial heating method Pin temperature: 300°C or below, Flow time: 3 seconds or less (per side of device) — (2) µPD70325L-8 : 84-pin plastic QFJ (1150 × 1150 mil) µPD70325L-10 : 84-pin plastic QFJ (1150 × 1150 mil) Soldering Process Soldering Conditions Symbol VPS Package peak temperature: 215°C, Reflow time: 40 seconds or less (at 200°C or higher), Number of reflow processes: 1 Exposure limitNote: 2 days (16 hours pre-baking is required at 125°C afterwards) VP15-162-1 Partial heating method Pin temperature: 300°C or below, Flow time: 3 seconds or less (per side of device) — Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25°C and relative humidity at 65% or less. Caution 76 Use of more than one soldering process should be avoided (except for partial heating method). µPD70325 [MEMO] 77 µPD70325 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 78 µPD70325 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J97. 8 79 µPD70325 Related documents Reference document V25+, V35+ User's Manual — Hardware IEU-706 (Japanese version) V25, V35 Family User's Manual — Instructions U12120J (Japanese version) Electrical Characteristics for Microcomputer IEI-601 (Japanese version) The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V25, V25+, V35, and V35+ are trademarks of NEC Corporation. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5