DATA SHEET MOS INTEGRATED CIRCUIT µPD70208H, 70216H V40HLTM, V50HLTM 16/8, 16-BIT MICROPROCESSOR DESCRIPTION The µ PD70208H (V40HL) is a high-speed, low-power 16-/8-bit microprocessor based on the µ PD70208 (V40TM) with 16-bit architecture, 8-bit data bus, and general-purpose peripheral functions. The µ PD70216H (V50HL) is a high-speed, low-power 16-bit microprocessor based on the µ PD70216 (V50TM ) with 16bit architecture, 16-bit data bus, and general-purpose peripheral functions. The V40HL and V50HL offer 20 MHz operation, and in addition to the conventional standby functions, also allows the clock to be stopped by the use of fully static internal circuitry, thus achieving greatly reduced power consumption. It is also capable of 3 V operation in addition to the previous 5 V operation, making it ideally suited to battery driven systems. Details are given in the following manuals. Be sure to read when carrying out design work. • V40HL, V50HL User’s Manual – Hardware (U11610E) • 16-bit V seriesTM User’s Manual – Instruction (U11301J: Japanese version) FEATURES • • High-speed, low-power version of V40 and V50 High-performance CPU (V20TM /V30TM software compatible) • Minimum instruction execution time: 100 ns (20 MHz, 5 V) 200 ns (10 MHz, 3 V) • Memory addressing space: 1M bytes • High-speed multiply/divide instructions: 0.95 to 2.8 µs (20 MHz, 5 V) 1.9 to 5.6 µs (10 MHz, 3 V) • Maskable (ICU) & non-maskable (NMI) interrupt inputs • µPD8080AF emulation function • Standby functions, clock stoppage capability • Standard peripheral LSI functions on chip • • • • • • • • Clock generator (CG) Programmable wait control unit (WCU) Refresh control unit (REFU) Timer/counter unit (TCU) ··· µ PD71054 subset Serial control unit (SCU) ··· µ PD71051 subset Interrupt control unit (ICU) ··· µ PD71059 subset DMA control unit (DMAU) ··· µ PD71071/71037 subset (functions of either selectable) Operating frequency: 10/12.5/16/20 MHz (at 5 V, with 20/25/32/40 MHz supplied externally) 5/6.25/8/10 MHz (at 3 V, with 10/12.5/16/20 MHz supplied externally) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13225EJ4V0DS00 (4th edition) Date Published April 1999 N CP(K) Printed in Japan The mark shows the the major revised points. © 1995 µPD70208H, 70216H ORDERING INFORMATION (1) V40HL Part Number µPD70208HGF-10-3B9 µPD70208HGF-12-3B9 µPD70208HGF-16-3B9 µPD70208HGF-20-3B9 µPD70208HGK-10-9EU µPD70208HGK-12-9EU µPD70208HGK-16-9EU µPD70208HGK-20-9EU µPD70208HLP-10 µPD70208HLP-12 µPD70208HLP-16 µPD70208HLP-20 Max. Operating Frequency (MHz) Package 80-pin plastic QFP (14 × 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 × 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 × 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 × 20 mm) (Resin thickness 2.7 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 68-pin plastic QFJ (950 × 950 mil) 68-pin plastic QFJ (950 × 950 mil) 68-pin plastic QFJ (950 × 950 mil) 68-pin plastic QFJ (950 × 950 mil) 10 12.5 16 20 × 12 mm) 10 × 12 mm) 12.5 × 12 mm) 16 × 12 mm) 20 10 12.5 16 20 (2) V50HL Part Number µPD70216HGF-10-3B9 µPD70216HGF-12-3B9 µPD70216HGF-16-3B9 µPD70216HGF-20-3B9 µPD70216HGK-10-9EU µPD70216HGK-12-9EU µPD70216HGK-16-9EU µPD70216HGK-20-9EU µPD70216HLP-10 µPD70216HLP-12 µPD70216HLP-16 µPD70216HLP-20 2 Max. Operating Frequency (MHz) Package 80-pin plastic QFP (14 × 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 × 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 × 20 mm) (Resin thickness 2.7 mm) 80-pin plastic QFP (14 × 20 mm) (Resin thickness 2.7 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 80-pin plastic TQFP (Fine pitch) (12 (Resin thickness 1.0 mm) 68-pin plastic QFJ (950 × 950 mil) 68-pin plastic QFJ (950 × 950 mil) 68-pin plastic QFJ (950 × 950 mil) 68-pin plastic QFJ (950 × 950 mil) 10 12.5 16 20 × 12 mm) 10 × 12 mm) 12.5 × 12 mm) 16 × 12 mm) 20 Data Sheet U13225EJ4V0DS00 10 12.5 16 20 µPD70208H, 70216H PIN CONFIGURATION (Top View) (1) V40HL • 80-pin Plastic QFP (14 × 20 mm) µPD70208HGF-10-3B9 A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ HLDAK RESOUT VDD VDD RESET READY NMI BS2 BS1 BS0 MRD µPD70208HGF-12-3B9 µPD70208HGF-16-3B9 µPD70208HGF-20-3B9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 IORD NC MWR IOWR BUSLOCK BUFR/W BUFEN CLKOUT X1 X2 GND NC GND High ASTB QS0 QS1 POLL TCTL2 TOUT2 TCLK NC INTP7 INTP6 DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD IC INTAK/SRDY/TOUT1 VDD INTP1 INTP2 INTP3 INTP4 INTP5 A16/PS0 NC A15 A14 A13 A12 A11 A10 A9 A8 GND NC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC NC END/TC Caution Leave IC pin open. Data Sheet U13225EJ4V0DS00 3 µPD70208H, 70216H • 80-pin Plastic TQFP (Fine pitch) (12 × 12 mm) µPD70208HGK-10-9EU NC A16/PS0 A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ HLDAK RESOUT VDD VDD RESET READY NMI BS2 BS1 BS0 MRD IORD NC µPD70208HGK-12-9EU µPD70208HGK-16-9EU µPD70208HGK-20-9EU 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC END/TC DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD INTAK/SRDY/TOUT1 VDD INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 NC A15 NC A14 A13 A12 A11 A10 A9 A8 GND GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC 4 Data Sheet U13225EJ4V0DS00 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 NC MWR IOWR BUSLOCK BUFR/W BUFEN CLKOUT X1 X2 GND GND High ASTB QS0 QS1 POLL TCTL2 TOUT2 TCLK NC µPD70208H, 70216H • 68-pin Plastic QFJ (950 × 950 mil) µPD70208HLP-10 IORD MRD BS0 BS1 BS2 NMI READY RESET VDD 56 BUFEN A10 15 55 CLKOUT A9 16 54 X1 A8 17 53 X2 GND 18 52 GND AD7 19 51 High AD6 20 50 ASTB AD5 21 49 QS0 AD4 22 48 QS1 AD3 23 47 POLL AD2 24 46 TCTL2 AD1 25 45 TOUT2 AD0 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Data Sheet U13225EJ4V0DS00 TCLK INTP7 INTP6 14 INTP5 BUFR/W A11 INTP4 57 INTP3 13 INTP2 BUSLOCK A12 INTP1 58 INTAK/SRDY/TOUT1 12 DMAAK3/TXD IOWR A13 DMARQ3/RXD 59 DMAAK2 11 DMARQ2 4 3 RESOUT HLDAK HLDRQ REFRQ A19/PS3 MWR A14 DMAAK1 2 1 68 67 66 65 64 63 62 61 60 DMARQ1 7 6 5 DMAAK0 10 DMARQ0 A15 END/TC 9 8 A18/PS2 A17/PS1 A16/PS0 µPD70208HLP-12 µPD70208HLP-16 µPD70208HLP-20 5 µPD70208H, 70216H (2) V50HL • 80-pin Plastic QFP (14 × 20 mm) µPD70216HGF-10-3B9 A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ HLDAK RESOUT VDD VDD RESET READY NMI BS2 BS1 BS0 MRD µPD70216HGF-12-3B9 µPD70216HGF-16-3B9 µPD70216HGF-20-3B9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD IC INTAK/SRDY/TOUT1 VDD INTP1 INTP2 INTP3 INTP4 INTP5 A16/PS0 NC AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 GND NC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC NC END/TC Caution Leave IC pin open. 6 Data Sheet U13225EJ4V0DS00 IORD NC MWR IOWR BUSLOCK BUFR/W BUFEN CLKOUT X1 X2 GND NC GND UBE ASTB QS0 QS1 POLL TCTL2 TOUT2 TCLK NC INTP7 INTP6 µPD70208H, 70216H • 80-pin Plastic TQFP (Fine pitch) (12 × 12 mm) µPD70216HGK-10-9EU NC A16/PS0 A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ HLDAK RESOUT VDD VDD RESET READY NMI BS2 BS1 BS0 MRD IORD NC µPD70216HGK-12-9EU µPD70216HGK-16-9EU µPD70216HGK-20-9EU 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 NC MWR IOWR BUSLOCK BUFR/W BUFEN CLKOUT X1 X2 GND GND UBE ASTB QS0 QS1 POLL TCTL2 TOUT2 TCLK NC NC END/TC DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD INTAK/SRDY/TOUT1 VDD INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 NC AD15 NC AD14 AD13 AD12 AD11 AD10 AD9 AD8 GND GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC Data Sheet U13225EJ4V0DS00 7 µPD70208H, 70216H • 68-pin Plastic QFJ (950 × 950 mil) µPD70216HLP-10 8 IORD MRD BS0 BS1 BS2 NMI READY RESET VDD BUFEN AD10 15 55 CLKOUT AD9 16 54 X1 AD8 17 53 X2 GND 18 52 GND AD7 19 51 UBE AD6 20 50 ASTB AD5 21 49 QS0 AD4 22 48 QS1 AD3 23 47 POLL AD2 24 46 TCTL2 AD1 25 45 TOUT2 AD0 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Data Sheet U13225EJ4V0DS00 INTP7 56 INTP6 14 INTP5 BUFR/W AD11 INTP4 57 INTP3 13 INTP2 BUSLOCK AD12 INTP1 58 INTAK/SRDY/TOUT1 12 DMAAK3/TXD IOWR AD13 DMARQ3/RXD 59 DMAAK2 11 DMAAK1 MWR AD14 DMARQ2 4 3 RESOUT HLDAK HLDRQ REFRQ A19/PS3 2 1 68 67 66 65 64 63 62 61 60 DMARQ1 7 6 5 DMAAK0 10 DMARQ0 AD15 END/TC 9 8 A18/PS2 A17/PS1 A16/PS0 µPD70216HLP-12 µPD70216HLP-16 µPD70216HLP-20 TCLK µPD70208H, 70216H PIN NAMES A8-A15 : Address Bus A16/PS0-A19/PS3 AD0-AD15 : Address/Processor Status : Address Bus/Data Bus ASTB BS0-BS2 : Address Strobe : Bus Status BUFEN BUFR/W : Buffer Enable : Buffer Read/Write BUSLOCK CLKOUT : Bus Lock : Clock Output DMAAK0-DMAAK2 DMAAK3/TXD : DMA Acknowledge : DMA Acknowledge/Transmit Data DMARQ0-DMARQ2 DMARQ3/RXD : DMA Request : DMA Request/Receive Data END/TC GND : End/Terminal Count : Ground High HLDAK : High Level Output : Hold Acknowledge HLDRQ IC : Hold Request : Internally Connected INTAK/SRDY/TOUT1 INTP1-INTP7 : Interrupt Acknowledge/Serial Ready/Timer Output 1 : Interrupt Request from Peripherals IORD IOWR : I/O Read : I/O Write MRD MWR : Memory Read : Memory Write NC NMI : No Connection : Non-Maskable Interrupt Request POLL QS0, QS1 : Poll : Queue Status READY REFRQ : Ready : Refresh Request RESET RESOUT : Reset : Reset Output TCLK TCTL2 : Timer Clock : Timer Control 2 TOUT2 UBE : Timer Output 2 : Upper Byte Enable VDD X1, X2 : Power Supply : Crystal Data Sheet U13225EJ4V0DS00 9 QS0 QS1 BS0-BS2 RXD SRDY T XD (1) V40HL A8-A15 A16/PS0-A19/PS3 BLOCK DIAGRAM AD0-AD7 µPD70208H, 70216H TOUT2 POLL TOUT1 BUSLOCK BIU SCU TCU TCTL2 BUFEN TCLK BUFR/W High ASTB IOWR IORD INTP7 MWR INTP6 WCU MRD INTP5 INTP4 READY ICU RESOUT INTP3 CPU RESET INTP2 INTP1 INTAK HLDAK BAU NMI HLDRQ X2 CG REFU DMAU 10 CPU : CG : Central Processing Unit Clock Generator REFU : TCU : Reflesh Control Unit Timer/Count Unit BIU : BAU : Bus Interface Unit Bus Arbitration Unit SCU ICU Serial Control Unit Interrupt Control Unit WCU : Wait Control Unit DMAU : : : DMA Control Unit Data Sheet U13225EJ4V0DS00 REFRQ END/TC DMAAK3 DMARQ3 DMAAK2 DMARQ2 DMAAK1 DMARQ1 DMAAK0 DMARQ0 CLKOUT X1 µPD70208H, 70216H QS0 QS1 BS0-BS2 AD0-AD15 A16/PS0-A19/PS3 RXD SRDY T XD (2) V50HL TOUT2 POLL TOUT1 SCU TCU BUSLOCK BIU TCTL2 BUFEN TCLK BUFR/W UBE ASTB IOWR IORD INTP7 MWR INTP6 WCU MRD INTP5 INTP4 READY ICU RESOUT INTP3 RESET CPU INTP2 INTP1 INTAK HLDAK BAU NMI HLDRQ X2 CG DMAU REFU Data Sheet U13225EJ4V0DS00 REFRQ END/TC DMAAK3 DMARQ3 DMAAK2 DMARQ2 DMAAK1 DMARQ1 DMAAK0 DMARQ0 CLKOUT X1 11 µPD70208H, 70216H DIFFERENCES FROM V40 AND V50 Item Operating supply voltage V40HL, V50HL V40, V50 3 V, 5 V 5V VDD = 5 V MAX. : 10, 12.5, 16, 20 MHz MIN. : DC MAX. : 8, 10 MHz MIN. : 2 MHz VDD = 3 V MAX. : 5, 6.25, 8, 10 MHz MIN. : DC No operation Variable scaling factor Fixed scaling factor Variable instruction cycle time Fixed instruction cycle time Maximum input frequency: 40 MHz Maximum input frequency: 20 MHz Internal I/O relocation function Switchable 8-bit boundary or 16-bit boundary relocation function V40: Relocation possible on 8-bit boundary V50: Relocation possible on 16-bit boundary Wait control unit (WCU) Memory space: 5 divisionsNote 1 Memory space: 3 divisions I/O space: 3 divisionsNote 2 I/O space: Not divided Refresh control unit (REFU) Refresh address: 16 bits Refresh address: 9 bits REFRQ extended timing supported No REFRQ extended timing Serial control unit (SCU) Dedicated baud rate generator incorporated No dedicated baund rate generator incorporated DMA control unit (DMAU) µPD71071/71037 subset (either function selectable) µPD71071 subset Standby functions HALT mode, STOP mode HALT mode only Operating frequency Clock generator (CG) Notes 1. Divided into 3 when a reset is performed. 2. Not divided when a reset is performed. 12 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H CONTENTS 1. PIN FUNCTIONS ................................................................................................................................... 15 1.1 LIST OF PIN FUNCTIONS ........................................................................................................................... 15 1.2 PROCESSING OF UNUSED PINS .............................................................................................................. 17 MEMORY AND I/O CONFIGURATION ................................................................................................ 19 2.1 MEMORY SPACE ......................................................................................................................................... 19 2.2 I/O SPACE .................................................................................................................................................... 21 3. CPU ........................................................................................................................................................ 22 4. CG (CLOCK GENERATOR) ................................................................................................................. 24 5. BIU (BUS INTERFACE UNIT) .............................................................................................................. 24 6. BAU (BUS ARBITRATION UNIT) ........................................................................................................ 25 7. WCU (WAIT CONTROL UNIT) ................................................................................................................ 27 2. 7.1 FEATURES ................................................................................................................................................... 27 7.2 RELATION BETWEEN WCU AND READY PIN ........................................................................................ 28 REFU (REFRESH CONTROL UNIT) .................................................................................................... 29 8.1 FEATURES ................................................................................................................................................... 29 8.2 REFRESH OPERATIONS ............................................................................................................................ 29 TCU (TIMER/COUNTER UNIT) ............................................................................................................ 30 9.1 FEATURES ................................................................................................................................................... 30 9.2 TCU INTERNAL BLOCK DIAGRAM ........................................................................................................... 30 10. SCU (SERIAL CONTROL UNIT) .......................................................................................................... 31 10.1 FEATURES ................................................................................................................................................... 31 10.2 SCU INTERNAL BLOCK DIAGRAM ........................................................................................................... 31 11. ICU (INTERRUPT CONTROL UNIT) .................................................................................................... 32 11.1 FEATURES ................................................................................................................................................... 32 11.2 ICU INTERNAL BLOCK DIAGRAM ............................................................................................................ 32 12. DMAU (DMA CONTROL UNIT) ............................................................................................................ 33 12.1 FEATURES ................................................................................................................................................... 33 12.2 DMAU INTERNAL BLOCK DIAGRAM ....................................................................................................... 33 13. STANDBY FUNCTIONS ........................................................................................................................ 34 14. RESET OPERATION ............................................................................................................................. 34 15. INSTRUCTION SET ............................................................................................................................... 35 8. 9. Data Sheet U13225EJ4V0DS00 13 µPD70208H, 70216H 16. ELECTRICAL SPECIFICATIONS ......................................................................................................... 66 16.1 AT 5 V OPERATION .................................................................................................................................... 66 16.2 AT 3 V OPERATION .................................................................................................................................... 75 17. PACKAGE DRAWINGS ........................................................................................................................ 100 18. RECOMMENDED SOLDERING CONDITIONS ................................................................................... 103 14 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H 1. PIN FUNCTIONS 1.1 LIST OF PIN FUNCTIONS Pin Name Input/Output AD0 to AD15Note 1, 3 3-state I/O Time-division address/data bus AD0 to AD7Note 2, 3 3-state I/O Time-division address/data bus A8 to A15Note 2, 3 A16/PS0 to A19/PS3Note 3 Function 3-state output Address bus 3-state output Time-division address/processor status REFRQ Output Refresh request HLDRQ Input Bus hold request HLDAK Output RESET Input RESOUT Output Bus hold acknowledge Reset System reset output READY Input Bus cycle end NMI Input Non-maskable interrupt MRDNote 3 3-state output Memory read strobe MWRNote 3 3-state output Memory read strobe IORDNote 3 3-state output I/O read strobe IOWRNote 3 3-state output I/O write strobe Output Address strobe ASTB UBENote 1, 3 3-state output Data bus upper byte enable HighNote 2 3-state output High level output BUSLOCKNote 3 3-state output Bus lock POLL Input Floating-point operation processor polling BUFR/WNote 3 3-state output Buffer read/write BUFENNote 3 3-state output Buffer enable X1 Input X2 — CLKOUT BS0 to Output BS2 Note 3 3-state output Crystal/external clock Clock output Bus status QS0, QS1 Output Queue status TOUT2 Output Timer 2 output TCTL2 Input Timer 2 control TCLK Input Timer clock INTP1 to INTP7 Input Maskable interrupts INTAK/SRDY/TOUT1 Output Interrupt acknowledge/serial reception ready/timer 1 output Notes 1. V50HL only 2. V40HL only 3. These pins are provided with a latch. Therefore, when they go into a high-impedance state, they hold the status before the high-impedance state until driven by an external device. It is not necessary to pull up or down the data bus. To invert the level of the pin that goes into a high-impedance state by an external device, a drive current higher than the latch invert current (IILH, IILL) is necessary. Data Sheet U13225EJ4V0DS00 15 µPD70208H, 70216H Pin Name Input/Output DMAAK3/TXD Output DMARQ3/RXD Input DMAAK0 to DMAAK2 Output DMARQ0 to DMARQ2 Input Function DMA acknowledge 3/serial transmit data DMA request 3/serial receive data DMA acknowledge DMA request END/TC I/O DMA service forcible termination/DMA service completion VDD — Positive power supply pin GND — Ground potential pin IC — Internal connection pin (External connection impossible) 16 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H 1.2 PROCESSING OF UNUSED PINS Table 1-1 shows the processing (recommended connection) of the unused pins. Use of a resistor with a resistance of 1 to 10 kΩ is recommended to connect these pins to VDD or GND via resistor. Table 1-1. Processing of Unused Pins Pin Name Input/Output AD0 to AD15Note 1 3-state I/O AD0 to AD7Note 2 3-state I/O A15Note 2 3-state output A16/PS0 to A19/PS3 3-state output A8 to Recommended Connection Open REFRQ Output HLDRQ Input HLDAK Output Open RESOUT Output Open Connect to GND via resistor READY Input Connect to VDD via resistor NMI Input Connect to GND via resistor MRD 3-state output MWR 3-state output IORD 3-state output IOWR 3-state output ASTB Output UBENote 1 3-state output HighNote 2 Output BUSLOCK 3-state output POLL Input BUFR/W 3-state output BUFEN 3-state output CLKOUT BS0 to BS2 Output Connect to GND via resistor Open Open 3-state output QS0, QS1 Output TOUT2 Output TCTL2 Input TCLK Input INTP1 to INTP7 Input INTAK/SRDY/TOUT1 Output DMAAK3/TxD Output DMARQ3/RxD Input DMAAK0 to DMAAK2 Output DMARQ0 to DMARQ2 Input END/TC Open I/O Connect to GND via resistor Open Connect to GND via resistor Open Connect to GND via resistor Individually connect to VDD via resistor Notes 1. V50HL only 2. V40HL only Data Sheet U13225EJ4V0DS00 17 µPD70208H, 70216H Remark The circuit configuration of the latch is as illustrated below. To invert the level of the pin with a latch, a drive current higher than the latch invert current is necessary. (1) Output pin Output buffer Latch Output pin address bus, control bus Hi-Z control (2) I/O pin Output buffer Latch I/O pin (data bus) Hi-Z control Input buffer 18 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H 2. MEMORY AND I/O CONFIGURATION 2.1 MEMORY SPACE The V40HL and V50HL can access a 1M-byte (512K-word) memory space. Figure 2-1. Memory Map FFFFFH Reserved FFFFCH FFFFBH Dedicated FFFF0H FFFEFH General Use 00400H 003FFH Interrupt Vector Table 00000H Figure 2-2. Interface with Memory (1/2) (a) V40HL A0-A19 Address Bus (20) Memory 1M Byte 8 D0-D7 Data Bus (8) Data Sheet U13225EJ4V0DS00 19 µPD70208H, 70216H Figure 2-2. Interface with Memory (2/2) (b) V50HL A1-A19 Address Bus (19) A0 19 UBE 19 BSEL BSEL Memory Upper Bank 512K Byte 8 D0-D15 20 Memory Lower Bank 512K Byte D8-D15 8 D0-D7 Data Bus (16) Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H 2.2 I/O SPACE In the V40HL and V50HL, I/Os up to 64K bytes (32K words) can be accessed in an area independent of the memory. The various on-chip peripheral LSIs are set by accessing the system I/O area. Extended functions added to those of the V40 and V50 are mapped onto unused V40 and V50 registers and the reserved area. The I/O map is shown in Figure 2-3. Figure 2-3. I/O Map FFFFH System I/O Area Area used for setting of I/O boundary, WCU, REFU, baud rate generator, etc., and DMAU, ICU, TCU and SCU allocation. FFE0H FFDFH Reserved Area FF00H FEFFH DMAU ICU The DMAU, ICU, TCU and SCU are allocated within any 256 bytes. 256 Bytes TCU SCU Internal I/O Area External I/O Area 0000H Data Sheet U13225EJ4V0DS00 21 µPD70208H, 70216H 3. CPU The CPU has the same functions as the V20HLTM and V30HLTM. In hardware terms, there are some changes regarding the use of the bus with on-chip peripherals, but in software terms the CPU is fully compatible. The internal block diagram of the CPU is shown in Figure 3-1. Figure 3-1. Internal Block Diagram of CPU (1/2) (a) V40HL Internal Address/Data Bus (20) To BIU ADM PS SS DS0 DS1 PFP DP TEMP Q0 Q1 Q2 Q3 T-STATE CONTROL CYCLE DECISION INTERRUPT CONTROL QUEUE CONTROL STANDBY CONTROL NMI INT (From ICU) CLOCK (From CG) BCU EXU LC PC AW BW CW DW IX IY BP SP SHIFTER µADDRESS REGISTER Queue Data Bus (8) TC TA TB EFFECTIVE ADDRESS GENERATOR µ INSTRUCTION 29 Micro Data Bus ROM µSEQUENCE CONTROL INSTRUCTION DECODER ALU PSW Sub Data Bus (16) 22 Main Data Bus (16) Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H Figure 3-1. Internal Block Diagram of CPU (2/2) (b) V50HL Internal Address/Data Bus (20) To BIU ADM PS SS DS0 DS1 PFP DP TEMP Q0 Q1 Q2 Q3 Q4 Q5 T-STATE CONTROL CYCLE DECISION INTERRUPT CONTROL QUEUE CONTROL STANDBY CONTROL NMI INT (From ICU) CLOCK (From CG) BCU EXU LC PC AW BW CW DW IX IY BP SP SHIFTER µADDRESS REGISTER Queue Data Bus (8) TC TA TB EFFECTIVE ADDRESS GENERATOR µINSTRUCTION 29 Micro Data Bus ROM µSEQUENCE CONTROL INSTRUCTION DECODER ALU PSW Sub Data Bus (16) Main Data Bus (16) Data Sheet U13225EJ4V0DS00 23 µPD70208H, 70216H 4. CG (CLOCK GENERATOR) The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1 and X2 pins, supplies it as the CPU operating clock and outputs it externally as the CLKOUT pin output. The interrupt cycle time can be changed according to the oscillator scaling factor. The scaling factor can be set by a system I/O area register. Figure 4-1. Internal Block Diagram of CG X1 Oscillator fXX Divide-by-2 Scaler X2 fX Divide-by-1-to-8 Scaler CPU, DMAU, REFU, SCU CLKOUT Baud Rate Counter (BRC) Divide-by-2-to-16 Scaler TCU 5. BIU (BUS INTERFACE UNIT) The BIU controls the data bus, address bus and control bus pins. These buses are used by the CPU, DMAU (DMA control unit) and REFU (refresh control unit). The BIU synchronizes the RESET input signal and READY input signal using the CLOCK signal generated by the clock generator (CG). In addition to being supplied to the inside of the V40HL and V50HL, the synchronized reset signal is also output externally from the RESOUT pin. The synchronized READY signal is supplied to the internal CPU, DMAU and REFU. Figure 5-1. RESET and READY Signal Synchronization CLOCK RESET D CK ↓ Q RESOUT To Internal Units READY 24 D CK ↑ Q D Data Sheet U13225EJ4V0DS00 CK ↓ Q To Internal Units µPD70208H, 70216H 6. BAU (BUS ARBITRATION UNIT) The BAU performs bus arbitration among bus masters. A list of bus masters (units which can acquire the bus) is shown below. Table 6-1. Bus Masters Bus Master Bus Cycle CPU Program fetch, data read/write DMAU DMA cycle REFU Refresh cycle External bus master (HLDRQ pin input) Bus cycle driven by external device The relative priorities of the bus masters are shown below. High CPU (when BUSLOCK prefix is used) REFU (highest priority: when given number of requests are reached) DMAU HLDRQ pin CPU (normal CPU cycle) Low REFU (lowest priority: cycle steal) BAU bus arbitration is performed as follows. A bus master such as the CPU, DMAU, REFU, etc., incorporated in the V40HL and V50HL normally release the bus at the end of the bus cycle currently being executed, as shown in Figure 6-1. However, in the case of a bus master connected to the HLDRQ pin, or cascaded external DMA controllers, for instance, the situation is as shown in Figure 6-2. The V40HL and V50HL request return of the bus by inactivating the acknowledge signal (HLDAK), and on receiving this request, the external bus master holding the bus should release the bus by dropping the bus hold request signal (HLDRQ). The V40HL and V50HL-internal bus master with the highest priority is kept waiting until the bus hold request signal is dropped. This is called a bus wait operation. Data Sheet U13225EJ4V0DS00 25 µPD70208H, 70216H Figure 6-1. Internal Bus Cycles Bus Cycle CPU CPU DMA Refresh Refresh Refresh Internal DMA Request Internal Refresh Request (Highest Priority) Figure 6-2. Bus Wait Operation Bus Wait Bus Cycle Bus Release Note Refresh HLDRQ Pin HLDAK Pin Internal Refresh Request (Highest Priority) Note The period in which the external bus master which has been given the bus after its release by the V40HL and V50HL can use the bus. 26 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H 7. WCU (WAIT CONTROL UNIT) The WCU has the function of automatically inserting a wait state (TW) of 0 to 3 clock cycles in a CPU, DMAU or REFU bus cycle. 7.1 • • • • • • • FEATURES Automatic setting of 0 to 3 waits for a CPU memory bus cycle 1M-byte memory space can be divided into 5 64K-byte I/O space can be divided into 3 Automatic setting of 0 to 3 waits for an external I/O cycle Automatic setting of 0 to 3 waits for a DMA cycle Automatic setting of 0 to 3 waits for a refresh cycle Same as V40 and V50 directly after a reset (memory space divided into 3, no division of I/O space) Figure 7-1. Example of Memory Space Division Upper Sub Memory Block FFFFFH Upper Memory Block 1 M-Byte Memory Area Middle Memory Block Lower Memory Block Lower Sub Memory Block 00000H Remark The division specification and the size of each block are set by means of a system I/O area register. Data Sheet U13225EJ4V0DS00 27 µPD70208H, 70216H Figure 7-2. Example of I/O Space Division FFFFH Upper I/O Block 64K-Byte I/O Area Middle I/O Block Lower I/O Block 0000H Remark The division specification and the size of each block are set by means of a system I/O area register. 7.2 RELATION BETWEEN WCU AND READY PIN When wait cycles exceeding 3 clock cycles are necessary, the WCU and the READY signal pin can be used in combination. The number of wait cycles specified by the WCU set value or the number of wait cycles under READY control, whichever is larger, is inserted. Figure 7-3. WCU and READY Control V40HL/V50HL WCU Bus Control READY 28 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H 8. REFU (REFRESH CONTROL UNIT) The REFU generates refresh cycles required for refreshing of external DRAM. Refresh enabling/disabling and the refresh interval can be set programmably. 8.1 • • • • FEATURES Lowest-priority refreshing/highest-priority refreshing 7-refresh queue 16-bit refresh address REFRQ extended timing supported (REFRQ active from T1 state) 8.2 REFRESH OPERATIONS The REFU has two priorities. Normally, it has the lowest priority, and a refresh cycle cannot be started unless the bus is completely idle. However, if there are 7 or more pending refresh requests, it is given the highest priority, and it requests the bus master holding the bus to relinquish it. (See 6. BAU.) The refresh address is output on A0 to A15. Every refresh cycle the refresh address is incremented by 1 (for the V40HL) or by 2 (for the V50HL), and the next refresh address is generated. In a refresh cycle, a low-level signal is output on the low address pins (A16 to A19). This refresh address is not affected by a reset. When the device is powered on, the refresh address is undefined. Data Sheet U13225EJ4V0DS00 29 µPD70208H, 70216H 9. TCU (TIMER/COUNTER UNIT) The TCU incorporates 3 counters, and can be used as a timer, event counter, rate generator, etc. Functionally it is a subset of the µPD71054. 9.1 • • • • • 9.2 FEATURES 3 × 16-bit counters Six programmable count modes Binary/BCD count Multiple latch command Choice of two input clocks: internal/external TCU INTERNAL BLOCK DIAGRAM TCU Selection Note 2 Signal IORD IOWR Note 1 TCLK (External) TCTL1=High TOUT1 (External) TCTL2 (External) TOUT2 (External) To INTL2/SCU CLOCK TCTL0=High TOUT0 (To INTL0) Prescaler SW SW SW TCT #0 Read/Write Control Control Logic Status Register TMD (Mode Register) Down Counter (16) (8) (16) (16) Status Latch H(8) L(8) Count Register H(8) L(8) Count Latch (8) (8) (8) Internal Data Bus Notes 1. A0 or A1 (Set by a system I/O area register) 2. A1 or A2 (Set by a system I/O area register) 30 Data Sheet U13225EJ4V0DS00 TCT #1 TCT #2 µPD70208H, 70216H 10. SCU (SERIAL CONTROL UNIT) The SCU performs control of serial communication (asynchronous). Its functions are a subset of the µPD71051 excluding synchronous communication. Also, what was the control word register in the µPD71051 has been divided into two: a command register and a mode register. 10.1 FEATURES Dedicated baud rate generator incorporated (using internal clock) • • • • • • • • • • • • Asynchronous serial communication Clock rate: baud rate × 16, × 64 Baud rate: DC – 500 kbps Character length: 7/8 bits Transmit stop bits: 1/2 bits Break transmission Automatic break detection Full-duplex double-buffer system Parity addition/checking Error detection: parity, overrun, framing Interrupt generation maskable 10.2 SCU INTERNAL BLOCK DIAGRAM Baud Rate Generator From CG RESET CLOCK From TCU (TOUT1 Output) Selector SST Status Register Internal Data Bus SCM Command Register SCU Status Control Bus IORD SRB Receive Data Buffer (8) STB Transmit Data Buffer (8) IOWR Read/Write Control Note 1 Note 2 SCU Selection Signal Receiver (Including Receive Buffer) SRDY (External) RXD (External) TXD (External) Transmitter (Including Transmit Buffer) RTCLK SMD Mode Register SIMK Interrupt Mask Register Interrupt Generation Logic SINT (To INTL1) Notes 1. A0 or A1 (Set by a system I/O area register) 2. A1 or A2 (Set by a system I/O area register) Data Sheet U13225EJ4V0DS00 31 µPD70208H, 70216H 11. ICU (INTERRUPT CONTROL UNIT) The ICU arbitrates among up to 8 interrupt requests (maskable interrupts) generated inside and outside the V40HL and V50HL, and transfers one of them to the CPU. The ICU functions comprise the functions of the V40HL and V50HL minus those functions not required by the V40HL and V50HL. 11.1 FEATURES 8 interrupt inputs • • • • • • µPD71059 cascading possible Edge- or level-triggered request input (input from internally connected TCU is edge-triggered only) Interrupt requests individually maskable Programmable interrupt request priority order Polling operation capability 11.2 ICU INTERNAL BLOCK DIAGRAM IORD IOWR Note 1 Note 2 ICU Selection Signal Initialize & Command Word Register Group Read/Write Control A8 A9 A10 To BIU INTAK (From CPU) Control Logic Interrupt In-Service Register (IIS) Priority Determination Logic Interrupt Mask Register (IMK) INT (To CPU) Interrupt Request Register (IRQ) Internal Data Bus Notes 1. A0 or A1 (Set by a system I/O area register) 2. A1 or A2 (Set by a system I/O area register) 32 SA0 SA1 SA2 Slave Control Data Sheet U13225EJ4V0DS00 INTL0 INTL1 INTL2 INTL3 INTL4 INTL5 INTL6 INTL7 TOUT0 (From TCU) SINT (From SCU) TOUT1 (From TCU) SW SW INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 External Pins µPD70208H, 70216H 12. DMAU (DMA CONTROL UNIT) The DMAU has 4 DMA channels, and provides the functions (subset) of two LSIs, the µPD71071 and µPD71037. 12.1 FEATURES Two operating modes (µPD71071 mode, µPD71037 mode) • • • • • • • • • • • • • • 20-bit address register 16-bit count register Four independent DMA channels Byte transfer/word transfer selectable Three transfer modes (settable on an individual channel basis) Single transfer mode, demand transfer mode, block transfer mode Two bus modes (common to all channels: in µPD71037 mode, bus release mode only) Bus release mode Bus hold mode DMA requests maskable on an individual channel basis Auto initialization function Transfer address increment/decrement Two channel priority systems (fixed priority/rotating priority) TC output at end of transfer Forced termination of service by END input Cascading capability 12.2 DMAU INTERNAL BLOCK DIAGRAM Internal Address Bus (20) Internal Data Bus (8) DMAU Address Bus (20) Internal Bus Interface Address Registers Address Increment/ Decrement (20) Current Address (20 × 4) Base Address (20 × 4) Internal Control Bus Control Register Group Channel Note 1 Device Control BUSRQ BAU DMAU Data Bus BUSAK Status Mode Control Count Registers DMARQ0DMARQ3 External DMAAK0pins DMAAK3 (4) (10) (8) (7 × 4) Base Count (16 × 4) Mask (4) Current Count (16 × 4) Request Note 2 (4) Priority Control END/TC Terminal Count Count Decrementer (16) Notes 1. In µPD71071 mode 2. In µPD71037 mode Data Sheet U13225EJ4V0DS00 33 µPD70208H, 70216H 13. STANDBY FUNCTIONS The V40HL and V50HL have two modes, the HALT mode and STOP mode, as standby functions. (1) HALT mode When the HALT instruction is executed, the clock to internal CPU circuitry (excluding the HALT mode release circuit) is stopped. (2) STOP mode When the HALT instruction is executed, all clocks to the CPU and internal I/Os are stopped. STOP mode should be used when a resonator is connected to the X1 and X2 pins. Remark Switching between HALT mode and STOP mode is performed by setting a system I/O area register. 14. RESET OPERATION When the RESET pin is driven low and this level is held for 4 clock cycles or more from the fall of the signal, the CPU and on-chip peripheral LSIs are reset. When the RESET pin subsequently returns to the high level, the CPU begins an instruction prefetch from address FFFF0H. When the V40HL and V50HL are reset, its status is fully compatible with the V40 and V50. Extended functions added to those of the V40 and V50 are mapped onto unused V40 and V50 registers and the reserved area. Table 14-1 shows the main statuses of the on-chip peripheral LSIs when a reset is performed. Table 14-1. Main Statuses of On-Chip Peripheral LSIs After Reset WCU Memory, external I/O, DMA & refresh Upper & lower memory blocks REFU Refresh cycle Refresh enabling/disabling SCU Baud rate Character Parity Stop bits Break detection DMAU µPD71071 mode Demand mode Auto initialization disabled Verify transfer, byte transfer Bus release mode DMA enabled : : : : : : 3-wait insertion : set to 512 KB : set to 72 clock cycles : not affected by reset x 64 7 bits None 1 bit None Caution When a reset is performed, the SCU, TCU, ICU and DMAU cannot be used. 34 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H 15. INSTRUCTION SET Table 15-1. Operand Type Legend Identifier reg Description 8/16-bit general register (destination register in an instruction using two 8/16-bit general registers) reg’ Source register in an instruction using two 8/16-bit general registers reg8 8-bit general register (destination register in an instruction using two 8-bit general registers) reg8’ Source register in an instruction using two 8-bit general registers reg16 16-bit general register (destination register in an instruction using two 16-bit general registers) reg16’ Source register in an instruction using two 16-bit general registers dmem 8/16-bit memory location mem 8/16-bit memory location mem8 8-bit memory location mem16 16-bit memory location mem32 32-bit memory location imm Constant in range 0 to FFFFH imm3 Constant in range 0 to 7 imm4 Constant in range 0 to FH imm8 Constant in range 0 to FFH imm16 Constant in range 0 to FFFFH acc Accumulator AW or AL sreg Segment register src-table Name of 256-byte conversion translation table src-block Name of block addressed by register IX dst-block Name of block addressed by register IY near-proc Procedure in current program segment far-proc Procedure in a different program segment near-label Label in current program segment short-label Label in range –128 to +127 bytes from end of instruction far-label Label in a different program segment memptr16 Word containing location offset in a different program segment to which control is to be shifted and segment base address memptr32 Doubleword containing location offset in a different program segment to which control is to be shifted and segment base address regptr16 General register containing location offset in a different program segment to which control is to be shifted pop-value Number of bytes to be removed from stack (0 to 64K, normally an even number) fp-op Immediate value which identifies external floating-point operation coprocessor operation code R Register set Data Sheet U13225EJ4V0DS00 35 µPD70208H, 70216H Table 15-2. Operation Code Legend Identifier Description W Byte/word specification bit (0: byte, 1: word). However, when s =1, byte data of sign extension is 16-bit operand if W = 1. reg Register field (000 to 111) reg’ Register field (000 to 111) (source register in instruction which uses two registers) mem Memory field (000 to 111) mod Mode field (00 to 10) s Sign-extended specification bit (0: without sign extension, 1: with sign extension) X, XXX, YYY, ZZZ Data used to determine external floating-point coprocessor operation code 36 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H Table 15-3. Operand Description Legend Identifier AW AH AL BW CW CL DW BP SP PC PSW IX IY PS SS DS0 DS1 AC CY P S Z DIR IE V BRK MD (...) disp ext-disp8 temp TA TB TC tmpcy seg offset ← + – × ÷ % ∨ ∨ ∨ ××H ××××H Description Accumulator (16-bit) Accumulator (high-order byte) Accumulator (low-order byte) Register BW (16-bit) Register CW (16-bit) Register CL (low-order byte) Register DW (16-bit) Base pointer (16-bit) Stack pointer (16-bit) Program counter (16-bit) Program status word (16-bit) Index register (source) (16-bit) Index register (destination) (16-bit) Program segment register (16-bit) Stack segment register (16-bit) Data segment 0 register (16-bit) Data segment 1 register (16-bit) Auxiliary carry flag Carry flag Parity flag Sign flag Zero flag Direction flag Interrupt enable flag Overflow flag Break flag Mode flag Contents of memory indicated by contents of ( ) Displacement (8/16-bit) 16 bits with 8-bit displacement sign-extended Temporary register (8/16/32-bit) Temporary register A (16-bit) Temporary register B (16-bit) Temporary register C (16-bit) Temporary carry flag (1-bit) Immediate segment data (16-bit) Immediate offset data (16-bit) Transfer direction Addition Subtraction Multiplication Division Modulo Logical product Logical sum Exclusive logical sum Two-digit hexadecimal number Four-digit hexadecimal number Data Sheet U13225EJ4V0DS00 37 µPD70208H, 70216H Table 15-4. Flag Operation Legend Identifier Description (Blank) No change 0 Cleared to 0 1 Set to 1 × Set or cleared depending upon result U Undefined R Previously saved value is restored Table 15-5. Memory Addressing mod 00 mem 01 000 BW + IX BW + IX + disp 8 BW + IX + disp 16 001 BW + IY BW + IY + disp 8 BW + IY + disp 16 010 BP + IX BP + IX + disp 8 BP + IX + disp 16 011 BP + IY BP + IY + disp 8 BP + IY + disp 16 100 IX IX + disp 8 IX + disp 16 101 IY IY + disp 8 IY + disp 16 110 DIRECT ADDRESS BP + disp 8 BP + disp 16 111 BW BW + disp 8 BW + disp 16 Table 15-6. 8/16-Bit General Register Selection Table 15-7. Segment Register Selection reg, reg’ W=0 W=1 sreg 000 AL AW 00 DS1 001 CL CW 01 PS 010 DL DW 10 SS BL BW 11 DS0 100 AH SP 101 CH BP 110 DH IX 111 BH IY 011 38 10 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H The instruction set is shown in tabular form on the following pages. Clock cycle shown in table is the time required for execution of instruction by the execution unit and is based on the following conditions. • Prefetch time and wait time for using bus, etc. are not included. • 0 wait is assumed for memory access. That is, the clock number of one bus cycle is four clock cycle. • 0 wait is assumed for I/O access. • Primitive block transfer instruction and primitive input/output instruction is included repeat prefixes. The number of clock cycle of instruction with byte processing and word processing (with W bit) is shown as the followings. (1) V40HL On the left of "/" : The value corresponding to byte processing (W= 0) or word processing (W = 1) of even address On the right of "/": The value corresponding to word processing (W =1) of odd address For the clock of block transfer related instruction of V40HL, see Table 15-8. Table 15-8. Number of Clock Cycles in Block Transfer Related Instruction (V40HL) Number of Clock Cycles Instruction Byte Processing (W = 0) Word Processing (W = 1) MOVBK 9 + 8 × rep (9) 9 + 16 × rep (17) CMPBK 7 + 14 × rep 7 + 22 × rep (13) (21) CMPM 7 + 10 × rep (7) 7 + 14 × rep (11) LDM 7 + 9 × rep (7) 7 + 13 × rep (11) STM 5 + 4 × rep 5 + 8 × rep (5) (9) INM 9 + 8 × rep (10) 9 + 16 × rep (18) OUTM 9 + 8 × rep (10) 9 + 16 × rep (18) Remark The figures in parentheses apply to one-time processing only. Data Sheet U13225EJ4V0DS00 39 µPD70208H, 70216H (2) V50HL On the left of "/" : On the right of "/" : The value corresponding to byte processing (W= 0) or word processing (W = 1) of even address The value corresponding to word processing (W =1) of odd address For the clock of block transfer related instruction of V50HL, see Table 15-9. Table 15-9. Number of Clock Cycles in Block Transfer Related Instruction V50HL (1/2) Number of Clock Cycles Instruction Byte Processing Word Processing (W = 1) (W = 0) Odd/Odd Address Odd/Even Address Even/Even Address MOVBK 9 + 8 × rep (9) 9 + 16 × rep (17) 9 + 12 × rep (13) 9 + 8 × rep (9) CMPBK 7 + 14 × rep (13) 7 + 22 × rep (21) 7 + 18 × rep (17) 7 + 14 × rep (13) INM 9 + 8 × rep 9 + 16 × rep 9 + 12 × rep 9 + 8 × rep (10) (18) (14) (10) 9 + 8 × rep (10) 9 + 16 × rep (18) 9 + 12 × rep (14) 9 + 8 × rep (10) OUTM Remark The figures in parentheses apply to one-time processing only. Table 15-9. Number of Clock Cycles in Block Transfer Related Instruction (V50HL) (2/2) Number of Clock Cycles Instruction Byte Processing Word Processing (W = 1) (W = 0) Odd Address Even Address 7 + 10 × rep 7 + 14 × rep 7 + 10 × rep (7) (11) (7) LDM 7 + 9 × rep (7) 7 + 13 × rep (11) 7 + 9 × rep (7) STM 5 + 4 × rep (5) 5 + 8 × rep (9) 5 + 4 × rep (5) CMPM Remark The figures in parentheses apply to one-time processing only. 40 Data Sheet U13225EJ4V0DS00 Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Data transfer instructions MOV Operand(s) Operation Code 76543210 76543210 reg, reg’ 1000101W 11 mem, reg 1000100W reg, mem Bytes Clock Cycles Flags Operation V40HL V50HL AC CY V 2 2 mod reg mem 2-4 7/11 7/11 (mem) ← reg 1000101W mod reg mem 2-4 10/14 10/14 reg ← (mem) mem, imm 1100011W mod 0 0 0 mem 3-6 9/13 9/13 (mem) ← imm reg, imm 1 0 1 1 W reg 2-3 4 4 acc, dmem 1010000W 3 10/14 10/14 If W=0: AL ← (dmem) If W=1: AH ← (dmem + 1), AL ← (dmem) dmem, acc 1010001W 3 9/13 9/13 If W=0: (dmem) ←AL If W=1: (dmem + 1) ← AH, (dmem) ←AL sreg, reg16 1000111 0 1 1 0 sreg reg 2 2 2 sreg, mem16 1000111 0 mod 0 sreg mem 2-4 14 10/14 reg16, sreg 1000110 0 1 1 0 sreg reg 2 2 2 mem16, sreg 1000110 0 mod 0 sreg mem 2-4 12 8/12 (mem16) ← sreg DS0, reg16, mem32 1100010 1 mod reg mem 2-4 25 17/25 reg16← (mem32) DS0 ← (mem32 + 2) DS1, reg16, mem32 1100010 0 mod reg mem 2-4 25 17/25 reg16 ← (mem32) DS1 ← (mem32 + 2) AH, PSW 1001111 1 1 2 2 AH ← S, Z, ×, AC, ×, P, ×, CY PSW, AH 1001111 0 1 3 3 S, Z, ×, AC, ×, P, ×, CY← AH 2-4 4 4 reg16 ←mem16 1 9 9 AL← (BW + AL) 2 3 3 reg ↔ reg’ 2-4 13/21 13/21 (mem) ↔ reg 1 3 3 AW ↔ reg16 reg16, mem16 1 0 0 0 1 1 0 1 TRANS src-table 1101011 1 XCH reg, reg’ 1000011W 1 1 reg reg’ mem, reg reg, mem 1000011W mod reg mem AW, reg16 reg16, AW 1 0 0 1 0 reg mod reg mem Z × × × reg ← imm sreg ← reg16 sreg:SS, DS0, DS1 sreg ← (mem16) sreg:SS, DS0, DS1 reg16 ← sreg × × 41 µPD70208H, 70216H LDEA S reg ← reg’ 2 reg reg’ P Repeat prefixes 42 Instruction Group Mnemonic Operand(s) Operation Code 76543210 Bytes 76543210 Clock Cycles AC CY V V40HL V50HL REPC 01100101 1 2 2 While CW ≠ 0, the following byte primitive block transfer instruction is executed and CW is decremented (–1). If there is a pending interrupt, it is serviced. If CY ≠ 1 the loop is exited. REPNC 01100100 1 2 2 Same as above If CY ≠ 0 the loop is exited. REP 11110011 1 2 2 While CW ≠ 0, the following byte primitive block transfer instruction is executed and CW is decremented (–1). If there is a pending interrupt, it is serviced. If the primitive block transfer instruction is CMPBK or CMPM and Z ≠ 1 the loop is exited. 11110010 1 2 2 Same as above If Z ≠ 0 the loop is exited. 1010010W 1 See Table 15-8 See Table 15-9 REPE REPZ REPNE REPNZ dst-block, src-block P S Z If W = 0: (IY) ← (IX) DIR = 0 : IX ← IX + 1, IY ← IY + 1 DIR = 1 : IX ← IX – 1, IY ← IY – 1 If W = 1: (IY + 1, IY) ← (IX + 1, IX) DIR = 0 : IX ← IX + 2, IY ← IY + 2 DIR = 1 : IX ← IX – 2, IY ← IY – 2 CMPBK src-block, 1010011W 1 dst-block See Table 15-8 See Table 15-9 If W = 0: (IX) – (IY) DIR = 0 : IX ← IX + 1, IY ← IY + 1 DIR = 1 : IX ← IX – 1, IY ← IY – 1 × × × × × × × × × × × × If W = 1: (IX + 1, IX) – (IY + 1, IY) DIR = 0 : IX ← IX + 2, IY ← IY + 2 DIR = 1 : IX ← IX – 2, IY ← IY – 2 CMPM LDM STM dst-block src-block dst-block 1010111W 1010110W 1010101W 1 1 1 See Table 15-8 See Table 15-9 If W = 0: AL – (IY) DIR = 0 : IY ← IY + 1; DIR = 1 : IY ← IY – 1 See Table 15-8 See Table 15-9 If W = 0: AL ← (IX) DIR = 0 : IX ← IX + 1; DIR = 1 : IX ← IX – 1 See Table 15-8 See Table 15-9 If W = 0: (IY) ← AL DIR = 0 : IY ← IY + 1; DIR = 1 : IY ← IY – 1 If W = 1: AW – (IY + 1, IY) DIR = 0 : IY ← IY + 2; DIR = 1 : IY ← IY – 2 If W = 1: AW ← (IX + 1, IX) DIR = 0 : IX + 2; DIR = 1 : IX ← IX – 2 If W = 1: (IY + 1, IY) ← AW DIR = 0 : IY ← IY + 2; DIR = 1 : IY ← IY – 2 µPD70208H, 70216H Primitive block transfer instructions Data Sheet U13225EJ4V0DS00 MOVBK Flags Operation Instruction Group Mnemonic INS Operand(s) reg8, reg8’ Operation Code 76543210 76543210 00001111 00110001 Bytes Clock Cycles 3 Bit field manipulation instructions 00001111 reg8, reg8’ 00001111 00001111 00111001 4 Input/output instructions INM 35-133 00110011 3 34-59 Note OUTM 26-55/ AW ← 16-bit field 34-59 00111011 4 34-59 26-55/ AW ← 16-bit field 34-59 acc, imm8 1110010W 2 9/13 9/13Note If W = 0: AL ← (imm8) If W = 1: AH ← (imm8 + 1), AL ← (imm8) acc, DW 1110110W 1 8/12 8/12Note If W = 0: AL ← (DW) If W = 1: AH ← (DW + 1), AL ← (DW) imm8, acc 1110011W 2 8/12 8/12Note If W = 0: (imm8) ← AL If W = 1: (imm8 + 1) ← AH, (imm8) ← AL DW, acc 1110111W 1 8/12 8/12Note If W = 0: (DW) ← AL If W = 1: (DW + 1) ← AH, (DW) ← AL dst-block, DW 0110110W 1 See See Table Table 15-8 15-9 If W = 0: (IY) ← (DW) DIR = 0 : IY ← IY + 1 ; DIR = 1 : IY ← IY – 1 See See Table Table 15-8 15-9 If W = 0: (DW) ← (IX ) DIR = 0 : IX ← IX + 1 ; DIR = 1 : IX ← IX – 1 DW, src-block 0110111W 1 If W = 1: (IY + 1, IY) ← (DW + 1, DW) DIR = 0 : IY ← IY + 2 ; DIR = 1 : IY ← IY – 2 If W = 1: (DW + 1, DW) ← (IX + 1, IX) DIR = 0 : IX ← IX + 2 ; DIR = 1 : IX ← IX – 2 In case of IN/OUT instruction to internal DMAU, the number of word processing clock cycles applied is always that to the right of "/". 43 µPD70208H, 70216H Primitive input/output instructions Data Sheet U13225EJ4V0DS00 OUT Z 35-133 31-117/ 16-bit field ← AW 1 1 0 0 0 reg IN S 35-133 1 1 reg’ reg reg8, imm4 P 35-133 31-117/ 16-bit field ← AW 1 1 0 0 0 reg EXT Flags AC CY V V40HL V50HL 1 1 reg’ reg reg8, imm4 Operation 44 Instruction Group Mnemonic ADD Data Sheet U13225EJ4V0DS00 Addition/subtraction instructions ADDC SUB Operation Code Bytes Clock Cycles 76543210 76543210 reg, reg’ 0000001W 1 1 reg reg’ 2 2 2 mem, reg 0000000W mod reg mem 2-4 13/21 reg, mem 0000001W mod reg mem 2-4 reg, imm 100000sW 1 1 0 0 0 reg mem, imm 100000sW mod 0 0 0 mem acc, imm 0000010W reg, reg’ 0001001W mem, reg Flags Operation AC CY V V40HL V50HL P S Z reg ← reg + reg’ × × × × × × 13/21 (mem) ← (mem) + reg × × × × × × 10/14 10/14 reg ← reg + (mem) × × × × × × 3-4 4 4 reg ← reg + imm × × × × × × 3-6 15/23 15/23 (mem) ← (mem) + imm × × × × × × 2-3 4 4 If W = 0: AL ← AL + imm If W = 1: AW ← AW + imm × × × × × × 1 1 reg reg’ 2 2 2 reg ← reg + reg’+ CY × × × × × × 0001000W mod reg mem 2-4 13/21 13/21 (mem) ← (mem) + reg + CY × × × × × × reg, mem 0001001W mod reg mem 2-4 10/14 10/14 reg ← reg + (mem) + CY × × × × × × reg, imm 100000s W 1 1 0 1 0 reg 3-4 4 4 reg ← reg + imm + CY × × × × × × mem, imm 100000sW mod 0 1 0 mem 3-6 15/23 15/23 (mem) ← (mem) + imm + CY × × × × × × acc, imm 0001010W 2-3 4 4 If W = 0: AL ← AL + imm + CY If W = 1: AW ← AW + imm + CY × × × × × × reg, reg’ 0010101W 1 1 reg reg’ 2 2 2 reg ← reg – reg’ × × × × × × mem, reg 0010100W mod reg mem 2-4 13/21 13/21 (mem) ← (mem) – reg × × × × × × reg, mem 0010101W mod reg mem 2-4 10/14 10/14 reg ← reg – (mem) × × × × × × reg, imm 100000sW 1 1 1 0 1 reg 3-4 4 4 reg ← reg – imm × × × × × × mem, imm 100000sW mod 1 0 1 mem 3-6 15/23 15/23 (mem) ← (mem) – imm × × × × × × acc, imm 0010110W 2-3 4 4 If W = 0: AL ← AL – imm If W = 1: AW ← AW – imm × × × × × × reg, reg’ 0001101W 1 1 reg reg’ 2 2 2 reg ← reg – reg’– CY × × × × × × mem, reg 0001100W mod reg mem 2-4 13/21 13/21 (mem) ← (mem) – reg – CY × × × × × × reg, mem 0001101W mod reg mem 2-4 10/14 10/14 reg ← reg – (mem) – CY × × × × × × reg, imm 100000sW 1 1 0 1 1 reg 3-4 4 4 reg ← reg – imm – CY × × × × × × mem, imm 100000sW mod 0 1 1 mem 3-6 15/23 15/23 (mem) ← (mem) – imm – CY × × × × × × acc, imm 0001110W 2-3 4 4 If W = 0: AL ← AL – imm – CY If W = 1: AW ← AW imm– CY × × × × × × µPD70208H, 70216H SUBC Operand(s) BCD operation instructions Instruction Group Mnemonic Operand(s) Operation Code Bytes Clock Cycles 76543210 76543210 ADD4S 00001111 00100000 2 19 × n 19 × n dst BCD string ← dst BCD string + src BCD string* +7 +7 SUB4S 00001111 00100010 2 CMP4S 00001111 00100110 2 00001111 00101000 3 ROL4 reg8 AC CY V P S Z U × U U U × 19 × n 19 × n dst BCD string ← dst BCD string – src BCD string* +7 +7 U × U U U × 19 × n 19 × n dst BCD string – src BCD string* +7 +7 U × U U U × V40HL V50HL 13 00001111 00101000 3-5 25 00001111 00101010 3 17 mem8 00001111 00101010 3-5 29 DEC reg8 11111110 1 1 0 0 0 reg mem 1111111W mod 0 0 0 mem reg16 0 1 0 0 0 reg reg8 11111110 1 1 0 0 1 reg mem 1111111W mod 0 0 1 mem reg16 0 1 0 0 1 reg mem Upper Lower ALL reg Upper Lower ALL mem Upper Lower 29 mod 0 0 0 mem INC ALL 17 1 1 0 0 0 reg Increment/decrement instructions Data Sheet U13225EJ4V0DS00 reg8 reg Upper Lower 25 mod 0 0 0 mem ROR4 ALL 13 1 1 0 0 0 reg mem8 Flags Operation reg8 ← reg8 + 1 × × × × × (mem) ← (mem) + 1 × × × × × 2 reg16 ← reg16 + 1 × × × × × 2 2 reg8 ← reg8 – 1 × × × × × 2-4 13/21 13/21 (mem) ← (mem) – 1 × × × × × 1 2 2 reg16 ← reg16 – 1 × × × × × 2 2 2 2-4 13/21 13/21 1 2 2 * The number of BCD digits is given by the CL register: a value between 1 and 254 can be set. 45 µPD70208H, 70216H n: 1/2 the number of BCD digits 46 Instruction Group Mnemonic MULU Data Sheet U13225EJ4V0DS00 Multiplication instructions MUL Operand(s) Operation Code 76543210 reg8 11110110 1 1 1 0 0 reg mem8 11110110 mod 1 0 0 mem reg16 11110111 1 1 1 0 0 reg mem16 11110111 mod 1 0 0 mem reg8 11110110 1 1 1 0 1 reg mem8 11110110 mod 1 0 1 mem reg16 11110111 1 1 1 0 1 reg mem16 11110111 mod 1 0 1 mem reg16, (reg16’,)Note imm8 reg16, mem16, imm8 reg16, (reg16’,)Note imm16 reg16, mem16, imm16 01101011 11 01101011 mod reg mem 01101001 11 01101001 mod reg mem reg reg’ reg reg’ Clock Cycles AC CY V V40HL V50HL 2 21-22 21-22 2-4 26-27 26-27 2 29-30 29-30 2-4 38-39 34-35/ 38-39 2 33-39 33-39 2-4 38-44 38-44 2 41-47 41-47 2-4 3 3-5 4 4-6 50-56 46-52/ 50-56 28-34 28-34 37-43 33-39/ 37-43 36-42 36-42 45-51 41-47/ 45-51 Flags Operation AW ← AL × reg8 AH = 0: CY ← 0, V ← 0 AH ≠ 0: CY ← 1, V ← 1 AW ← AL × (mem8) AH = 0: CY ← 0, V ← 0 AH ≠ 0: CY ← 1, V ← 1 DW, AW ← AW × reg16 DW = 0: CY ← 0, V ← 0 DW ≠ 0: CY ← 1, V ← 1 DW, AW ← AW × (mem16) DW = 0: CY ← 0, V ← 0 DW ≠ 0: CY ←1, V ← 1 AW ←AL × reg8 AH = AL sign extension: CY ← 0, V ← 0 AH ≠ AL sign extension: CY ← 1, V ← 1 AW ← AL × (mem8) AH = AL sign extension: CY ← 0, V ← 0 AH ≠ AL sign extension: CY ← 1, V ← 1 DW, AW ← AW × reg16 DW = AW sign extension: CY ← 0, V ← 0 DW ≠ AW sign extension: CY ← 1, V ← 1 DW, AW ← AW × (mem16) DW = AW sign extension: CY ← 0, V ← 0 DW ≠ AW sign extension: CY ← 1, V ← 1 reg16 ← reg16’ × imm8 Product ≤ 16 bits : CY ← 0, V ← 0 Product > 16 bits : CY ← 1, V ← 1 reg16 ← (mem16) × imm8 Product ≤ 16 bits : CY ← 0, V ← 0 Product > 16 bits : CY ← 1, V ← 1 reg16 ← reg16’ × imm16 Product ≤ 16 bits : CY ← 0, V ← 0 Product > 16 bits : CY ← 1, V ← 1 reg16 ← (mem16) × imm16 Product ≤ 16 bits : CY ← 0, V ← 0 Product > 16 bits : CY ← 1, V ← 1 Note The 2nd operand can be omitted, in which case the same register as the 1st operand is taken as being specified. P S Z U × × U U U U × × U U U U × × U U U U × × U U U U × × U U U U × × U U U U × × U U U U × × U U U U × × U U U U × × U U U U × × U U U U × × U U U µPD70208H, 70216H 76543210 Bytes Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Unsigned division instructions DIVU Operand(s) Operation Code 76543210 76543210 reg8 11110110 1 1 1 1 0 reg mem8 11110110 mod 1 1 0 mem reg16 11110111 1 1 1 1 0 reg mem16 11110111 mod 1 1 0 mem Bytes Clock Cycles Flags Operation AC CY V V40HL V50HL P S Z 19 19 temp ← AW If temp ÷ reg8 ≤ FFH AH ← temp%reg8, AL ←temp ÷ reg8 If temp ÷ reg8 > FFH TA ← (001H, 000H), TC ← (003H, 002H) SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA U U U U U U 2-4 24 24 temp ← AW If temp ÷ (mem8) ≤ FFH AH ← temp%(mem8), AL ←temp ÷ (mem8) If temp ÷ (mem8) > FFH TA ← (001H, 000H), TC ← (003H, 002H) SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA U U U U U U 2 25 25 temp ← DW, AW If temp ÷ reg16 ≤ FFFFH DW ← temp%reg16, AW ←temp ÷ reg16 If temp ÷ reg16 > FFFFH TA ← (001H, 000H), TC ← (003H, 002H) SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA U U U U U U 2-4 34 30/34 temp ← DW, AW If temp ÷ (mem16) ≤ FFFFH DW ← temp%(mem16), AW ←temp ÷ (mem16) If temp ÷ (mem16) > FFFFH TA ← (001H, 000H), TC ← (003H, 002H) SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA U U U U U U 47 µPD70208H, 70216H 2 48 Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Signed division instructions DIV Operand(s) Operation Code 76543210 reg8 11110110 1 1 1 1 1 reg mem8 11110110 mod 1 1 1 mem reg16 11110111 1 1 1 1 1 reg mem16 11110111 mod 1 1 1 mem Clock Cycles Flags Operation AC CY V V40HL V50HL P S Z 2 29-34 29-34 temp ← AW If temp ÷ reg8 > 0 and temp ÷ reg8 ≤ 7FH or temp ÷ reg8 < 0 and temp ÷ reg8 > 0 – 7FH –1 AH ← temp%reg8, AL ← temp ÷ reg8 If temp ÷ reg8 > 0 and temp ÷ reg8 > 7FH or temp ÷ reg8 < 0 and temp ÷ reg8 ≤ 0 – 7FH –1 TA ← (001H, 000H), TC ← (003H, 002H) SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA U U U U U U 2-4 34-39 34-39 temp ← AW If temp ÷ (mem8) > 0 and temp ÷ (mem8) ≤ 7FH or temp ÷ (mem8) < 0 and temp ÷ (mem8) > 0 – 7FH –1 AH ← temp%(mem8), AL ← temp ÷(mem8) If temp ÷ (mem8) > 0 and temp ÷ (mem8) > 7FH or temp ÷ (mem8) < 0 and temp ÷ (mem8) ≤ 0 – 7FH –1 TA ← (001H, 000H), TC ← (003H, 002H) SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA U U U U U U 2 38-43 38-43 temp ← DW, AW If temp ÷ reg16 > 0 and temp ÷ reg16 ≤ 7FFFH or temp ÷ reg16 < 0 and temp ÷ reg16 > 0 – 7FFFH –1 DW ← temp%reg16, AW ← temp ÷ reg16 If temp ÷ reg16 > 0 and temp ÷ reg16 > 7FFFH or temp ÷ reg16 < 0 and temp ÷ reg16 ≤ 0 – 7FFFH –1 TA ← (001H, 000H), TC ← (003H, 002H) SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA U U U U U U 2-4 47-52 43-48/ temp ← DW, AW 47-52 If temp ÷ (mem16) > 0 and temp ÷ (mem16) ≤ 7FFFH or temp ÷ (mem16) < 0 and temp ÷ (mem16) > 0 – 7FFFH –1 DW ← temp%(mem16), AW ← temp ÷ (mem16) If temp ÷ (mem16) > 0 and temp ÷ (mem16) > 7FFFH or temp ÷ (mem16) < 0 and temp ÷ (mem16) ≤ 0 – 7FFFH –1 TA ← (001H, 000H), TC ← (003H, 002H) SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 U U U U U U µPD70208H, 70216H 76543210 Bytes 76543210 ADJBA Bytes 76543210 Flags Operation AC CY V V40HL V50HL 7 7 If AL 0FH > 9 or AC = 1: AL ← AL + 6 AH ← AH + 1, AC ← 1, CY ← AC, AL ← AL S Z × × U U U U × × U × × × × × U U U U 0FH 00100111 1 3 3 If AL 0FH > 9 or AC = 1 AL ← AL + 6, CY ← CY ∨ AC , AC← 1 If AL > 9FH or CY = 1 AL ← AL + 60H, CY ← 1 ADJBS 00111111 1 7 7 If AL 0FH > 9 or AC = 1 AL ← AL – 6, AH ← AH – 1 , AC← 1 CY ← AC, AL ← AL 0FH ADJ4S 00101111 1 3 3 If AL 0FH > 9 or AC = 1 AL ← AL –6, CY ← CY ∨ AC , AC← 1 If AL > 9FH or CY = 1 AL ← AL – 60H, CY ← 1 × × U × × × CVTBD 11010100 0 0 00 1 0 1 0 2 15 15 AH ← AL ÷ 0AH, AL ← AL%0AH U U U × × × CVTDB 11010101 0 0 00 1 0 1 0 2 7 7 AL ← AH × 0AH + AL, AH ← 0 U U U × × × CVTBW 10011000 1 2 2 If AL < 80H: AH ← 0, otherwise: AH ← FFH CVTWL 10011001 1 4-5 4-5 2 2 2 reg – reg’ × × × × × × Complement operation instructions NOT NEG reg reg’ ∨ CMP If AW < 8000H: DW ← 0, otherwise: DW ← FFFFH reg, reg’ 0011101W 11 mem, reg 0011100W mod reg mem 2-4 10/14 10/14 (mem) – reg × × × × × × reg, mem 0011101W mod reg mem 2-4 10/14 10/14 reg – (mem) × × × × × × reg, imm 100000sW 1 1 1 1 1 reg 3-4 4 4 reg – imm × × × × × × mem, imm 100000sW mod 1 1 1 mem 3-6 12/16 12/16 (mem) – imm × × × × × × acc, imm 0011110W 2-3 4 4 If W = 0: AL – imm If W = 1: AW – imm × × × × × × reg 1111011W 1 1 0 1 0 reg 2 2 2 reg ← reg mem 1111011W mod 0 1 0 mem 2-4 13/21 13/21 reg 1111011W 1 1 0 1 1 reg 2 2 2 reg ← reg + 1 × × × × × × mem 1111011W mod 0 1 2-4 13/21 13/21 (mem) ← (mem) + 1 × × × × × × mem (mem) ← (mem) 49 µPD70208H, 70216H Comparison instructions ADJ4A ∨ Data Sheet U13225EJ4V0DS00 BCD adjustment instructions 1 P Data conversion instructions 00110111 Clock Cycles ∨ Operation Code ∨ Operand(s) ∨ Mnemonic ∨ Instruction Group 76543210 76543210 reg, reg’ 1000010W 11 mem, reg reg, mem 1000010W reg, imm Clock Cycles Flags Operation AC CY V V40HL V50HL P S Z U 0 0 × × × U 0 0 × × × imm U 0 0 × × × U 0 0 × × × ∨ ∨ If W = 0: AL imm8 If W = 1: AW imm16 U 0 0 × × × reg ← reg reg’ U 0 0 × × × U 0 0 × × × ∨ (mem) U 0 0 × × × ∨ imm U 0 0 × × × U 0 0 × × × If W = 0: AL ← AL imm8 If W = 1: AW ← AW imm16 U 0 0 × × × reg ← reg ∨ reg’ U 0 0 × × × 13/21 (mem) ← (mem) ∨ reg U 0 0 × × × 10/14 10/14 reg ← reg ∨ (mem) U 0 0 × × × 3-4 4 4 reg ← reg ∨ imm U 0 0 × × × 3-6 15/23 15/23 (mem) ← (mem) ∨ imm U 0 0 × × × 2-3 4 4 If W = 0: AL ← AL ∨ imm8 If W = 1: AW ← AW ∨ imm16 U 0 0 × × × reg’ 2 2 2 reg ← reg ∨ reg’ U 0 0 × × × mod reg mem 2-4 13/21 13/21 (mem) ← (mem) ∨ reg U 0 0 × × × 0011001W mod reg mem 2-4 10/14 10/14 reg ← reg ∨ (mem) U 0 0 × × × reg, imm 1000000W 11110 reg 3-4 4 4 reg ← reg ∨ imm U 0 0 × × × mem, imm 1000000W mod 1 1 0 mem 3-6 15/23 15/23 (mem) ← (mem) ∨ imm U 0 0 × × × acc, imm 0011010W 2-3 4 4 If W = 0: AL ← AL ∨ imm8 If W = 1: AW ← AW ∨ imm16 U 0 0 × × × 2 2 2 mod reg mem 2-4 9/13 9/13 1111011W 11000 reg 3-4 4 4 mem, imm 1111011W mod 0 0 0 mem 3-6 10/14 10/14 acc, imm 1010100W 2-3 4 4 reg, reg’ 0010001W 11 reg’ 2 2 2 mem, reg 0010000W mod reg mem 2-4 13/21 13/21 (mem) ← (mem) reg, mem 0010001W mod reg mem 2-4 10/14 10/14 reg ← reg reg, imm 1000000W 11100 reg 3-4 4 4 reg ← reg mem, imm 1000000W mod 1 0 0 mem 3-6 15/23 15/23 acc, imm 0010010W 2-3 4 4 reg, reg’ 0000101W 11 reg’ 2 2 2 mem, reg 0000100W mod reg mem 2-4 13/21 reg, mem 0000101W mod reg mem 2-4 reg, imm 1000000W 11001 reg mem, imm 1000000W mod 0 0 1 mem acc, imm 0000110W reg, reg’ 0011001W 11 mem, reg 0011000W reg, mem reg’ (mem) reg (mem) reg imm (mem) ← (mem) ∨ reg imm ∨ reg reg ∨ reg’ reg ∨ ∨ Data Sheet U13225EJ4V0DS00 Logical operation instructions Bytes ∨ AND Operation Code ∨ TEST Operand(s) ∨ Mnemonic ∨ 50 Instruction Group OR reg µPD70208H, 70216H XOR reg Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Bit manipulation instructions TEST1 NOT1 Operand(s) reg8, CL Operation Code 76543210 76543210 00010000 1 1 0 0 0 reg Clock Cycles Flags Operation AC CY V V40HL V50HL P S Z 3 3 3 reg8 bit NO.CL = 0 : Z ← 1 reg8 bit NO.CL = 1 : Z ← 0 U 0 0 U U × mem8, CL 0000 mod 0 0 0 mem 3-5 7 7 (mem8) bit NO.CL = 0 : Z← 1 (mem8) bit NO.CL = 1 : Z← 0 U 0 0 U U × reg16, CL 0001 1 1 0 0 0 mem 3 3 3 reg16 bit NO.CL = 0 : Z ← 1 reg16 bit NO.CL = 1 : Z ← 0 U 0 0 U U × mem16, CL 0001 mod 0 0 0 mem 3-5 11 7/11 (mem16) bit NO.CL = 0 : Z← 1 (mem16) bit NO.CL = 1 : Z← 0 U 0 0 U U × reg8, imm3 1000 1 1 0 0 0 reg 4 4 4 reg8 bit NO.imm3 = 0 : Z ← 1 reg8 bit NO.imm3 = 1 : Z ← 0 U 0 0 U U × mem8, imm3 1000 mod 0 0 0 mem 4-6 8 8 (mem8) bit NO.imm3 = 0 : Z← 1 (mem8) bit NO.imm3 = 1 : Z← 0 U 0 0 U U × reg16, imm4 1001 1 1 0 0 0 reg 4 4 4 reg16 bit NO.imm4 = 0 : Z ← 1 reg16 bit NO.imm4 = 1 : Z ← 0 U 0 0 U U × mem16, imm4 1001 mod 0 0 0 mem 4-6 12 8/12 (mem16) bit NO.imm4 = 0 : Z← 1 (mem16) bit NO.imm4 = 1 : Z← 0 U 0 0 U U × reg8, CL 0110 1 1 0 0 0 reg 3 4 4 reg8 bit NO.CL← reg8 bit NO.CL mem8, CL 0110 mod 0 0 0 mem 3-5 10 10 (mem8) bit NO.CL← (mem8) bit NO.CL reg16, CL 0111 1 1 0 0 0 reg 3 4 4 reg16 bit NO.CL← reg16 bit NO.CL mem16, CL 0111 mod 0 0 0 mem 3-5 18 10/18 reg8, imm3 1110 1 1 0 0 0 reg 4 5 5 reg8 bit NO.imm3← reg8 bit NO.imm3 mem8, imm3 1110 mod 0 0 0 mem 4-6 11 11 (mem8) bit NO.imm3← (mem8) bit NO.imm3 reg16, imm4 1111 1 1 0 0 0 reg 4 5 5 reg16 bit NO.imm4← reg16 bit NO.imm4 mem16, imm4 1111 mod 0 0 0 mem 4-6 19 11/19 CY 11110101 3rd byte* (mem16) bit NO.CL← (mem16) bit NO.CL (mem16) bit NO.imm4← (mem16) bit NO.imm4 * 1st byte = 0FH 1 2 2 CY← CY × 51 µPD70208H, 70216H 2nd byte* NOT1 Bytes 52 Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Bit manipulation instructions CLR1 SET1 Operand(s) reg8, CL Operation Code 76543210 76543210 00010010 1 1 0 0 0 reg AC CY V V40HL V50HL 3 5 5 reg8 bit NO.CL ← 0 0010 mod 0 0 0 mem 3-5 11 11 (mem8) bit NO.CL ← 0 reg16, CL 0011 1 1 0 0 0 mem 3 5 5 reg16 bit NO.CL ← 0 mem16, CL 0011 mod 0 0 0 mem 3-5 19 11/19 reg8, imm3 1010 1 1 0 0 0 reg 4 6 6 reg8 bit NO.imm3 ← 0 mem8, imm3 1010 mod 0 0 0 mem 4-6 12 12 (mem8) bit NO.imm3 ← 0 reg16, imm4 1011 1 1 0 0 0 reg 4 6 6 reg16 bit NO.imm4 ← 0 mem16, imm4 1011 mod 0 0 0 mem 4-6 20 12/20 reg8, CL 0100 1 1 0 0 0 reg 3 4 4 reg8 bit NO.CL ← 1 mem8, CL 0100 mod 0 0 0 mem 3-5 10 10 (mem8) bit NO.CL ← 1 reg16, CL 0101 1 1 0 0 0 reg 3 4 4 reg16 bit NO.CL ← 1 mem16, CL 0101 mod 0 0 0 mem 3-5 18 10/18 reg8, imm3 1100 1 1 0 0 0 reg 4 5 5 reg8 bit NO.imm3 ← 1 mem8, imm3 1100 mod 0 0 0 mem 4-6 11 11 (mem8) bit NO.imm3 ← 1 reg16, imm4 1101 1 1 0 0 0 reg 4 5 5 reg16 bit NO.imm4 ← 1 mem16, imm4 1101 mod 0 0 0 mem 4-6 19 11/19 3rd byte* Flags Operation P S Z (mem16) bit NO.CL ← 0 (mem16) bit NO.imm4 ← 0 (mem16) bit NO.CL ← 1 (mem16) bit NO.imm4 ← 1 * 1st byte = 0FH CY 11111000 1 2 2 CY ← 0 DIR 11111100 1 2 2 DIR ← 0 CY 11111001 1 2 2 CY ← 1 DIR 11111101 1 2 2 DIR ← 1 0 1 µPD70208H, 70216H SET1 Clock Cycles mem8, CL 2nd byte* CLR1 Bytes Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Shift instructions SHL Operand(s) Operation Code Bytes Clock Cycles 76543210 76543210 reg, 1 1101000W 1 1 1 0 0 reg 2 6 6 mem, 1 1101000W mod 1 0 0 mem 2-4 13/21 reg, CL 1101001W 1 1 1 0 0 reg 2 mem, CL 1101001W mod 1 0 0 mem reg, imm8 1100000W mem, imm8 1100000W Flags Operation V40HL V50HL AC CY V P S Z CY ← reg MSB, reg ← reg × 2 If reg MSB ≠ CY: V ← 1 If reg MSB = CY: V ← 0 U × × × × × 13/21 CY ← (mem) MSB, (mem) ← (mem) × 2 If (mem) MSB ≠ CY: V ← 1 If (mem) MSB = CY: V ← 0 U × × × × × 7+n 7+n temp ← CL, while temp ≠0 the following operation are repeated: CY ← reg MSB, reg ← reg × 2 temp ← temp – 1 U × U × × × 2-4 16/24 +n 16/24 +n temp ← CL, while temp ≠0 the following operation are repeated: CY ← (mem) MSB, (mem) ← (mem) × 2 temp ← temp – 1 U × U × × × 1 1 1 0 0 reg 3 7+n 7+n temp ← imm8, while temp ≠ 0 the following operations are repeated: CY ← reg MSB, reg← reg × 2 temp ← temp – 1 U × U × × × mod 1 0 0 mem 3-5 16/24 +n 16/24 +n temp ← imm8, while temp ≠ 0 the following operations are repeated: CY ← (mem) MSB, (mem) ← (mem) × 2 temp ← temp – 1 U × U × × × n: Number of shifts µPD70208H, 70216H 53 54 Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Shift instructions SHR Operand(s) Operation Code Bytes Clock Cycles 76543210 76543210 reg, 1 1101000W 1 1 1 0 1 reg 2 6 6 mem, 1 1101000W mod 1 0 1 mem 2-4 13/21 reg, CL 1101001W 1 1 1 0 1 reg 2 mem, CL 1101001W mod 1 0 1 mem reg, imm8 1100000W mem, imm8 1100000W Flags Operation V40HL V50HL AC CY V P S Z CY ← reg LSB, reg ← reg ÷ 2 If reg MSB ≠ bit after reg MSB : V ← 1 If reg MSB = bit after reg MSB : V ← 0 U × × × × × 13/21 CY ← (mem) LSB, (mem) ← (mem) ÷ 2 If (mem) MSB ≠ bit after (mem) MSB : V ← 1 If (mem) MSB = bit after (mem) MSB : V ← 0 U × × × × × 7+n 7+n temp ← CL, while temp ≠ 0 the following operations are repeated: CY ← reg LSB, reg ← reg ÷ 2 temp ← temp – 1 U × U × × × 2-4 16/24 +n 16/24 +n temp ← CL, while temp ≠ 0 the following operations are repeated: CY ← (mem) LSB, (mem) ← (mem) ÷ 2 temp ← temp – 1 U × U × × × 1 1 1 0 1 reg 3 7+n 7+n temp ← imm8, while temp ≠ 0 the following operations are repeated: CY ← reg LSB, reg ← reg ÷ 2 temp ← temp – 1 U × U × × × mod 1 0 1 mem 3-5 16/24 +n 16/24 +n temp ← imm8, while temp ≠ 0 the following operations are repeated: CY ← (mem) LSB,(mem) ← (mem) ÷ 2 temp ← temp – 1 U × U × × × µPD70208H, 70216H n: Number of shifts Instruction Group Mnemonic SHRA Operand(s) Operation Code Bytes Clock Cycles Data Sheet U13225EJ4V0DS00 76543210 76543210 reg, 1 1101000W 1 1 1 1 1 reg 2 6 6 mem, 1 1101000W mod 1 1 1 mem 2-4 13/21 reg, CL 1101001W 1 1 1 1 1 reg 2 mem, CL 1101001W mod 1 1 1 mem reg, imm8 1100000W mem, imm8 1100000W Flags Operation V40HL V50HL AC CY V P S Z CY ← reg LSB, reg ← reg ÷ 2, V ← 0 MSB of operand is unchanged. U × 0 × × × 13/21 CY ← (mem) LSB,(mem) ← (mem) ÷ 2, V ← 0 MSB of operand is unchanged. U × 0 × × × 7+n 7+n temp ← CL, while temp ≠ 0 the following operations are repeated: CY ← reg LSB, reg ← reg ÷ 2 temp ← temp – 1, MSB of operand is unchanged. U × U × × × 2-4 16/24 +n 16/24 +n temp ← CL, while temp ≠ 0 the following operations are repeated: CY ← (mem) LSB, (mem) ← (mem) ÷ 2 temp ← temp – 1, MSB of operand is unchanged. U × U × × × 1 1 1 1 1 reg 3 7+n 7+n temp ← imm8, while temp ≠ 0 the following operations are repeated: CY ← reg LSB, reg ← reg ÷ 2 temp ← temp – 1, MSB of operand is unchanged. U × U × × × mod 1 1 1 mem 3-5 16/24 +n 16/24 +n temp ← imm8, while temp ≠ 0 the following operations are repeated: CY ← (mem) LSB,(mem) ← (mem) ÷ 2 temp ← temp – 1, MSB of operand is unchanged. U × U × × × n: Number of shifts µPD70208H, 70216H 55 56 Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Rotate instructions ROL Operand(s) Operation Code Bytes Clock Cycles 76543210 76543210 reg, 1 1101000W 1 1 0 0 0 reg 2 6 6 mem, 1 1101000W mod 0 0 0 mem 2-4 13/21 reg, CL 1101001W 1 1 0 0 0 reg 2 mem, CL 1101001W mod 0 0 0 mem reg, imm8 1100000W mem, imm8 1100000W Flags Operation AC CY V V40HL V50HL CY ← reg MSB, reg ← reg × 2 + CY reg MSB ≠ CY : V ← 1 reg MSB = CY : V ← 0 × × 13/21 CY ← (mem) MSB, (mem) ← (mem) × 2 + CY (mem) MSB ≠ CY : V ← 1 (mem) MSB = CY : V ← 0 × × 7+n 7+n temp ← CL, while temp ≠ 0 the following operations are repeated: CY ← reg MSB, reg ← reg × 2 + CY temp ← temp – 1 × U 2-4 16/24 +n 16/24 +n temp ← CL, while temp ≠ 0 the following operations are repeated: CY ← (mem) MSB, (mem) ← (mem) × 2 + CY temp ← temp – 1 × U 1 1 0 0 0 reg 3 7+n 7+n temp ← imm8, while temp ≠ 0 the following operations are repeated: CY ← reg MSB, reg ← reg × 2 + CY temp ← temp – 1 × U mod 0 0 0 mem 3-5 16/24 +n 16/24 +n temp ← imm8, while temp ≠ 0 the following operations are repeated: CY ← (mem) MSB, (mem) ← (mem) × 2 + CY temp ← temp – 1 × U P S Z n: Number of shifts µPD70208H, 70216H Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Rotate instructions ROR Operand(s) Operation Code Bytes Clock Cycles 76543210 76543210 reg, 1 1101000W 1 1 0 0 1 reg 2 6 6 mem, 1 1101000W mod 0 0 1 mem 2-4 13/21 reg, CL 1101001W 1 1 0 0 1 reg 2 mem, CL 1101001W mod 0 0 1 mem reg, imm8 1100000W mem, imm8 1100000W Flags Operation AC CY V V40HL V50HL CY ← reg LSB, reg← reg ÷ 2 reg MSB ← CY reg MSB ≠ bit after reg MSB : V ← 1 reg MSB = bit after reg MSB : V ← 0 × × 13/21 CY ← (mem) LSB, (mem) ← (mem) ÷ 2 (mem) MSB ← CY (mem) MSB ≠ bit after (mem) MSB : V ← 1 (mem) MSB = bit after (mem) MSB : V ← 0 × × 7+n 7+n temp ← CL, while CL ≠ 0 the following operations are repeated: CY ← reg LSB, reg ← reg ÷ 2 reg MSB ← CY temp ← temp – 1 × U 2-4 16/24 +n 16/24 +n temp ← CL, while CL ≠ 0 the following operations are repeated: CY ← (mem) LSB,(mem) ← (mem) ÷ 2 (mem) MSB ← CY temp ← temp – 1 × U 1 1 0 0 1 reg 3 7+n 7+n temp ← imm8, while CL ≠ 0 the following operations are repeated: CY ← reg LSB,reg ← reg ÷ 2 reg MSB ← CY temp ← temp – 1 × U mod 0 0 1 mem 3-5 16/24 +n 16/24 +n temp ← imm8, while CL ≠ 0 the following operations are repeated: CY ← (mem) LSB,(mem) ← (mem) ÷ 2 (mem) MSB ← CY temp ← temp – 1 × U S Z 57 µPD70208H, 70216H n: Number of shifts P 58 Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Rotate instructions ROLC Operand(s) Operation Code Bytes Clock Cycles 76543210 76543210 reg, 1 1101000W 1 1 0 1 0 reg 2 6 6 mem, 1 1101000W mod 0 1 0 mem 2-4 13/21 reg, CL 1101001W 1 1 0 1 0 reg 2 mem, CL 1101001W mod 0 1 0 mem reg, imm8 1100000W 1 1 0 1 0 reg Flags Operation AC CY V V40HL V50HL tmpcy ← CY, CY ← reg MSB reg ← reg × 2 + tmpcy reg MSB ≠ CY : V ← 1 reg MSB = CY : V ← 0 × × 13/21 tmpcy ← CY, CY ← (mem) MSB (mem)← (mem) × 2 + tmpcy (mem) MSB ≠ CY : V ← 1 (mem) MSB = CY : V ← 0 × × 7+n 7+n temp ← CL, while CL ≠ 0 the following operations are repeated: tmpcy← CY, CY ← reg MSB reg ← reg × 2 + tmpcy temp ← temp – 1 × U 2-4 16/24 +n 16/24 +n temp ← CL, while CL ≠ 0 the following operations are repeated: tmpcy ← CY, CY ← (mem) MSB (mem) ← (mem) × 2 + tmpcy temp ← temp – 1 × U 3 7+n 7+n temp ← imm8, while CL ≠ 0 the following operations are repeated: × U × U P S Z tmpcy ← CY, CY ← reg MSB reg ← reg × 2 + tmpcy temp ← temp – 1 mem, imm8 1100000W mod 0 1 0 mem 3-5 16/24 +n 16/24 +n n: Number of shifts µPD70208H, 70216H temp ← imm8, while CL ≠ 0 the following operations are repeated: tmpcy ← CY, CY ← (mem) MSB (mem) ← (mem) × 2 + tmpcy temp ← temp – 1 Instruction Group Mnemonic Data Sheet U13225EJ4V0DS00 Rotate instructions RORC Operand(s) Operation Code 76543210 reg, 1 1101000W 1 1 0 1 1 reg mem, 1 1101000W mod 0 1 1 mem reg, CL 1101001W 1 1 0 1 1 reg mem, CL 1101001W mod 0 1 1 mem reg, imm8 1100000W 1 1 0 1 1 reg mem, imm8 1100000W mod 0 1 1 mem Clock Cycles Flags Operation AC CY V V40HL V50HL tmpcy ← CY, CY ← reg LSB reg ← reg ÷ 2 reg MSB ← tmpcy reg MSB ≠ bit after reg MSB : V ← 1 reg MSB = bit after reg MSB : V ← 0 × × 13/21 tmpcy ← CY, CY ← (mem) LSB (mem) ← (mem) ÷ 2 (mem) MSB ← tmpcy (mem) MSB ≠ bit after (mem) MSB : V ← 1 (mem) MSB = bit after (mem) MSB : V ← 0 × × 7+n 7+n temp ← CL, while CL ≠ 0 the following operations are repeated: tmpcy ← CY, CY ← reg LSB reg ← reg ÷ 2 reg MSB ← tmpcy temp ← temp – 1 × U 2-4 16/24 +n 16/24 +n temp ← CL, while CL ≠ 0 the following operations are repeated: tmpcy ← CY, CY ← (mem) LSB (mem) ← (mem) ÷ 2 (mem) MSB ← tmpcy temp ← temp – 1 × U 3 7+n 7+n temp ←imm8, while CL ≠ 0 the following operations are repeated: tmpcy ← CY, CY ← reg LSB reg ← reg ÷ 2 reg MSB ← tmpcy temp ← temp – 1 × U 3-5 16/24 +n 16/24 +n temp ← imm8, while CL ≠ 0 the following operations are repeated: tmpcy ← CY, CY ← (mem) LSB (mem) ← (mem) ÷ 2 (mem) MSB ← tmpcy temp ← temp – 1 × U 2 6 6 2-4 13/21 2 n: Number of shifts P S Z 59 µPD70208H, 70216H 76543210 Bytes 60 Instruction Group Mnemonic Operation Code 76543210 CALL Data Sheet U13225EJ4V0DS00 Subroutine control instructions Operand(s) SP ← SP – 2, (SP + 1, SP) ← PC PC ← PC + disp 1 1 0 1 0 reg 2 18 14/18 SP ← SP – 2, (SP + 1, SP) ← PC PC ← regptr16 mod 0 1 0 mem 2-4 31 23/31 TA ← (memptr16) SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA 5 29 21/29 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← seg SP ← SP – 2, (SP + 1, SP) ← PC, PC ← offset 2-4 47 31/47 TA ← (memptr32),TB ← (memptr32 + 2) SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TB SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA 11000011 1 19 15/19 PC ← (SP + 1, SP) SP ← SP + 2 11000010 3 24 20/24 PC ← (SP + 1, SP) SP ← SP + 2, SP ← SP + pop-value 11001011 1 29 21/29 PC ← (SP + 1, SP) PS ← (SP + 3, SP + 2) PS ← SP + 4 11001010 3 32 24/32 PC ← (SP + 1, SP) PS ← (SP + 3, SP + 2) SP ← SP + 4, SP ← SP + pop-value 11111111 memptr16 11111111 far-proc 10011010 memptr32 11111111 mod 0 1 1 mem Flags AC CY V V40HL V50HL 16/20 regptr16 pop-value Operation 20 11101000 pop-value 76543210 Clock Cycles 3 near-proc RET Bytes P S Z µPD70208H, 70216H Instruction Group Mnemonic Operation Code 76543210 76543210 mem16 11111111 mod 1 1 0 mem reg16 Bytes Clock Cycles AC CY V V40HL V50HL 23 15/23 SP ← SP – 2 (SP + 1, SP) ← (mem16) 0 1 0 1 0 reg 1 10 6/10 SP ← SP – 2 (SP + 1, SP) ← reg16 sreg 0 0 0 sreg 1 1 0 1 10 6/10 SP ← SP – 2 (SP + 1, SP) ← sreg PSW 10011100 1 10 6/10 SP ← SP – 2 (SP + 1, SP) ← PSW R 01100000 1 65 33/65 Push registers on the stack imm8 01101010 2 9 5/9 SP ← SP – 2 (SP + 1, SP) ← imm8, sign of extension imm16 01101000 3 10 6/10 SP ← SP – 2 (SP + 1, SP) ← imm16 mem16 10001111 2-4 24 16/24 (mem16) ← (SP + 1, SP) SP ← SP + 2 reg16 0 1 0 1 1 reg 1 12 8/12 reg16← (SP + 1, SP) SP ← SP + 2 sreg 0 0 0 sreg 1 1 1 1 12 8/12 sreg← (SP + 1, SP) SP ← SP + 2 PSW 10011101 1 12 8/12 PSW← (SP + 1, SP) SP ← SP + 2 R 01100001 1 75 43/75 Pop registers from the stack PREPARE imm16, imm8 11001000 4 DISPOSE 11001001 1 Data Sheet U13225EJ4V0DS00 POP 2. If imm8 = 0 If imm8 ≥ 1 16 21 + 16 (imm8 – 1) 12/16 {17 + 8 (imm8 – 1)} / {21 + 16 (imm8 – 1)} P S Z R R R sreg : SS, DS0, DS1 R R R Note 1 Note 2 Prepare New Stack Frame 10 6/10 Dispose of Stack Frame 61 µPD70208H, 70216H Notes 1. If imm8 = 0 If imm8 ≥ 1 mod 0 0 0 mem Flags Operation 2-4 PUSH Stack manipulation instructions Operand(s) 62 Instruction Group Mnemonic Operation Code 76543210 BR Branch instructions Operand(s) Bytes 76543210 Clock Cycles Operation AC CY V V40HL V50HL near-label 11101001 3 13 13 PC ← PC+ dsip short-label 11101011 2 12 12 PC ← PC+ ext-disp8 regptr16 11111111 1 1 1 0 0 reg 2 11 11 PC ← regptr16 memptr16 11111111 mod 1 0 0 mem 2-4 23 19/23 far-label 11101010 5 15 15 memptr32 11111111 2-4 34 26/34 mod 1 0 1 mem Flags P S Z PC ← (memptr16) PS ← seg PC ← offset PS ← (memptr32 + 2) PC ← (memptr32) Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H Data Sheet U13225EJ4V0DS00 Conditional branch instructions Instruction Group Mnemonic Operand(s) Operation Code 76543210 Bytes 76543210 Clock CyclesNote Operation AC CY V V40HL V50HL short-label 01110000 2 14/4 14/4 if V = 1 PC ← PC + ext-disp8 BNV short-label 0001 2 14/4 14/4 if V = 0 PC ← PC + ext-disp8 BC BL short-label 0010 2 14/4 14/4 if CY = 1 PC ← PC + ext-disp8 BNC BNL short-label 0011 2 14/4 14/4 if CY = 0 PC ← PC + ext-disp8 BE BZ short-label 0100 2 14/4 14/4 if Z = 1 PC ← PC + ext-disp8 BNE BNZ short-label 0101 2 14/4 14/4 if Z = 0 PC ← PC + ext-disp8 BNH short-label 0110 2 14/4 14/4 if CY ∨ Z = 1 PC ← PC + ext-disp8 BH short-label 0111 2 14/4 14/4 if CY ∨ Z = 0 PC ← PC + ext-disp8 BN short-label 1000 2 14/4 14/4 if S = 1 PC ← PC + ext-disp8 BP short-label 1001 2 14/4 14/4 if S = 0 PC ← PC + ext-disp8 BPE short-label 1010 2 14/4 14/4 if P = 1 PC ← PC + ext-disp8 BPO short-label 1011 2 14/4 14/4 if P = 0 PC ← PC + ext-disp8 BLT short-label 1100 2 14/4 14/4 if S ∨ V = 1 PC ← PC + ext-disp8 BGE short-label 1101 2 14/4 14/4 if S ∨ V = 0 PC ← PC + ext-disp8 BLE short-label 1110 2 14/4 14/4 if (S ∨ V) ∨ Z = 1 PC ← PC + ext-disp8 BGT short-label 1111 2 14/4 14/4 if (S ∨ V) ∨ Z = 0 PC ← PC + ext-disp8 DBNZNE short-label 11100000 2 14/5 14/5 CW = CW – 1 if Z = 0 and CW ≠ 0 PC ← PC + ext-disp8 DBNZE short-label 11100001 2 14/5 14/5 CW = CW – 1 if Z = 1 and CW ≠ 0 PC ← PC + ext-disp8 DBNZ short-label 11100010 2 13/5 13/5 CW = CW – 1 if CW ≠ 0 PC ← PC + ext-disp8 BCWZ short-label 11100011 2 13/5 13/5 if CW = 0 PC ← PC + ext-disp8 P S Z 63 µPD70208H, 70216H BV Note Condition determination: true/false Flags 64 Instruction Group Mnemonic 76543210 Bytes 76543210 Clock Cycles AC CY V V40HL V50HL 11001100 1 50 38/50 TA ← (00DH, SP ← SP – 2, SP ← SP – 2, SP ← SP – 2, imm8 ( = 3) 11001101 2 50 38/50 TA ← (4 n + 1, 4n), TC ← (4n + 3, 4n + 2) n = imm8 SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA BRKV 11001110 1 Note 1 Note 2 If V = 1 TA ← (011H, 010H), TC ← (013H, 012H) SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA RETI 11001111 1 39 27/39 PC ← (SP + 1, SP), PS ← (SP + 3, SP + 2), PSW ← (SP + 5, SP + 4), SP ← SP + 6 3 50 38/50 TA ← (4 n + 1, 4n), TC ← (4n + 3, 4n + 2) n = imm8 SP ← SP – 2, (SP + 1, SP) ← PSW, MD ← 0 MD is set to write enabled SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC Data Sheet U13225EJ4V0DS00 BRKEM imm8 00001111 11111111 Flags Operation 3 BRK Interrupt instructions Operation Code Operand(s) P S Z R R R 00CH), TC ← (00FH, 00EH) (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 (SP + 1, SP) ← PS, PS ← TC (SP + 1, SP) ← PC, PC ← TA R R R SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA CHKIND 01100010 mod reg mem 2-4 Note 3 Note 4 When V = 1: 52 2. When V = 0: 3 When V = 1: 40/52 3. When V = 0: 3 When interrupt condition is established : 72 to 75 4. When interrupt condition is not established When interrupt condition is established : 25 : (52 to 55)/(72 to 75) When interrupt condition is not established : 17/25 If (mem32) > reg16 or (mem32 + 2) < reg16 TA ← (015H, 014H), TC ← (017H, 016H) SP ← SP – 2, (SP + 1, SP) ← PSW, IE ← 0, BRK ← 0 SP ← SP – 2, (SP + 1, SP) ← PS, PS ← TC SP ← SP – 2, (SP + 1, SP) ← PC, PC ← TA µPD70208H, 70216H Notes 1. reg16, mem32 CPU control instructions Instruction Group Mnemonic Operand(s) Operation Code 76543210 Bytes 76543210 Clock Cycles AC CY V V40HL V50HL HALT 11110100 1 POLL 10011011 1 DI 11111010 1 2 2 IE ← 0 EI 11111011 1 2 2 IE ← 1 BUSLOCK 11110000 1 2 2 Bus Lock Prefix No Operation FPO1 FPO2 2 2 11011X X X 11YYYZ Z Z 2 2 2 fp-op, mem 11011X X X mod Y Y Y mem 2-4 14 10/14 fp-op 0110011X 11YYYZ Z Z 2 2 2 fp-op, mem 0110011X mod Y Y Y mem 2-4 14 10/14 P Data Sheet U13225EJ4V0DS00 S Z P S Z R R R CPU Halt 2 + 5n 2 + 5n Poll and wait fp-op Flags Operation n: Number of times POLL pin is sampled data bus ← (mem) No Operation data bus ← (mem) NOP 10010000 1 3 3 No Operation * 0 0 1 sreg 1 1 0 1 2 2 Segment override prefix * DS0:, DS1:, PS:, and SS:. Instruction Group Mnemonic Operand(s) CALLN imm8 Bytes Clock Cycles Flags Operation 76543210 76543210 AC CY V 11101101 11111101 2 39 27/39 PC ← (SP + 1, SP), PS ← (SP + 3, SP + 2), R PSW ← (SP + 5, SP + 4), SP ← SP + 6, MD is set to write disabled 11101101 11101101 3 58 38/58 TA ← (4n + 1, SP ← SP – 2, SP ← SP – 2, SP ← SP – 2, V40HL V50HL 4n), TC ← (4n + 3, 4n + 2) n = imm8 (SP + 1, SP) ← PSW, MD ← 1 (SP + 1, SP) ← PS, PS ← TC (SP + 1, SP) ← PC, PC ← TA R R 65 µPD70208H, 70216H 8080 RETEM Operation Code µPD70208H, 70216H 16. ELECTRICAL SPECIFICATIONS Applied standard The electrical characteristics shown below are applied to devices other than the old models conforming to K mask. Therefore, these characteristics are different from those conforming to the K mask. For the electrical characteristics of the K mask, consult NEC. “Others” in the table below means products conforming to the masks other than E, P, X, and M (but conforming to the L, F mask). 16.1 AT 5 V OPERATION OPERATING RANGE E, P, X, M Mask Model µPD70208H, 70216H-10/12/16 Others VDD = 5 V ±10% µPD70208H, 70216H-20 VDD = 5 V ±5% — ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Supply voltage Symbol Test Conditions VDD VDD = 5 V ±10% (µPD70208H, 70216H-10/12/16) VDD = 5 V ±5% (µPD70208H, 70216H-20) Rating Unit –0.5 to +7.0 V –0.5 to VDD + 0.3 V –0.5 to VDD + 1.0 V –0.5 to VDD + 0.3 V Input voltage VI Clock input voltage VK Output voltage VO Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Cautions 1. Do not directly connect the output pins of two or more IC products and do not directly connect the output pins to VDD or VCC and GND. However, open-drain pins or open-collector pins may be connected directly. Moreover, an external circuit whose timing is designed to avoid output collision can be connected to pins that go into a high-impedance state. 2. If even one of the above parameters exceeds the absolute maximum rating even momentarily, the quality of the program may be degraded. Absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. Use the program keeping all the parameters within these rated values. The standards and conditions shown in DC and AC Characteristics below specify the range within which the normal operation of the product is guaranteed. 66 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 5 V ±10% (µPD70208H, 70216H-10/12/16), VDD = 5 V ±5% (µPD70208H, 70216H-20)) Parameter Input voltage high Symbol VIH Test Conditions MAX. Unit 2.2 VDD+0.3 V 0.8 VDD VDD+0.3 2.2 VDD+0.3 0.8 VDD VDD+0.3 2.4 VDD+0.3 Except RESET –0.5 +0.8 RESET –0.5 0.2VDD E, P, X, M Except RESET masks RESET Others Except RESET, INTP1 to INTP7 RESET INTP1 to INTP7 Input voltage low VIL MIN. TYP. V Clock input voltage high VKH 3.9 VDD+1.0 V Clock input voltage low VKL –0.5 +0.6 V Output voltage high VOH Output voltage low VOL IOH = –2.5 mA 0.7 VDD IOH = –100 µA VDD – 0.4 V Except END/TC : IOL = 2.5 mA END/TC 0.4 V : IOL = 5.0 mA Input leak current high ILIH VI = VDD 10 µA Input leak current low ILIL Except INTP:VI = 0 V –10 µA INTP input current low ILIPL INTP input:VI = 0 V –300 µA Output leak current high ILOH VO = VDD 10 µA Output leak current low ILOL VO = 0 V –10 µA Latch leak current high ILLH VI = 3.0 V –50 –300 µA Latch leak current low ILLL VI = 0.8 V 50 300 µA Latch inversion current (L → H) IILH 400 µA Latch inversion current (H → L) IILL –400 µA mA Supply currentNote IDD E, P, X, M On operation 5.5 fX 9.0 fX masks On standby (HALT) 1.5 fX 2.5 fX On standby (STOP) Others µA mA On operation 4.5 fX 6.0 fX On standby (HALT) 1.5 fX 2.2 fX On standby (STOP) Note 50 50 µA MAX. Unit The unit of constant values (1.5, 2.2, 2.5, 4.5, 5.5, 6.0 and 9.0) is mA/MHz. CAPACITANCE (TA = 25 ˚C, VDD = 0 V) Parameter Symbol Test Conditions MIN. TYP. Input capacitance CI fC = 1 MHz 10 pF Input/output capacitance CIO 0 V other than test pin. 15 pF Data Sheet U13225EJ4V0DS00 67 µPD70208H, 70216H AC CHARACTERISTICS (1) µ PD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, V DD = 5 V ±10%) (1/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µ PD70208H-10 µ PD70216H-10 µ PD70208H-12 µ PD70216H-12 MIN. MAX. MIN. MAX. DC 40 DC µPD70208H-16 µPD70216H-16 MIN. External clock input cycle <1> t CYX 50 External clock input high-level width (VKH=3.0 V) <2> t XXH 19 14 12 ns External clock input low-level width (VKL =1.5 V) <3> t XXL 19 14 12 ns External clock input rise time (1.5→3.0 V) <4> t XR 5 5 5 ns External clock input fall time (3.0→1.5 V) <5> t XF 5 5 5 ns Clock output cycle <6> t CYK 100 Clock output high-level width (VOH=3.0 V) <7> t KKH 0.5tCYK –5 0.5tCYK–5 0.5t CYK–5 ns Clock output low-level width (VOL =1.5 V) <8> t KKL 0.5tCYK –5 0.5tCYK–5 0.5t CYK–5 ns Clock output rise time (1.5→3.0 V) <9> t KR Clock output fall time (3.0→1.5 V) <10> t KF 5 5 5 ns CLKOUT delay time (vs. external clock) <11> t DXK 40 35 20 ns Input rise time (except external clock) (0.8→2.2 V) <12> t IR 15 15 15 ns Input fall time (except external clock) (2.2→0.8 V) <13> t IF 10 10 10 ns E, P, X, M masks <14> t OR 15 15 15 ns Others 10 10 10 ns 10 10 10 ns Output rise time (except CLKOUT) (0.8→2.2 V) Output fall time (except CLKOUT) (2.2→0.8 V) RESET setup time (vs. RESET hold time (vs. CLKOUT↓)Note 1 CLKOUT↓)Note 1 DC 80 5 <15> t OF <16> t SRESK 20 DC 31.25 Unit MAX. 62.5 5 20 DC DC 5 20 ns ns ns <17> t HKRES 25 RESOUT output delay time (vs. CLKOUT↓) <18> t DKRES 5 READY inactive setup time (vs. CLKOUT↑) <19> t SRYLK 15 10 7 ns READY inactive hold time (vs. CLKOUT↑) <20> t HKRYL 20 15 15 ns READY active setup time (vs. CLKOUT↑) <21> t SRYHK 15 10 7 ns READY active hold time (vs. CLKOUT↑) <22> t HKRYH 20 20 15 ns NMI setup time (vs. CLKOUT↑) <23> t SNMIK 15 15 15 ns POLL setup time (vs. CLKOUT↑) <24> t SPOLK 20 20 20 ns Data setup time (vs. CLKOUT↓) <25> tSDK 15 10 7 ns Data hold time (vs. CLKOUT↓) <26> tHKD 5 5 5 ns CLKOUT → address delay timeNote 2 <27> tDKA 5 CLKOUT → address hold time <28> tHKA 5 CLKOUT↓ → PS delay time <29> tDKP 5 50 5 40 5 30 ns CLKOUT↓ → PS float delay time <30> tFKP 5 50 5 40 5 30 ns <31> tSAST tKKL –20 <32> tFKA t HKA Address setup time (vs. ASTB↓) CLKOUT↓ → address float delay CLKOUT↓ → ASTB↑ delay time time Note 3 <33> tDKSTH 25 ns 50 50 5 5 15 40 40 5 40 t HKA 5 ns 30 28 5 t KKL–10 50 5 30 t HKA ns ns t KKL–10 40 ns ns 30 ns 25 ns Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing. 2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. 3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. 68 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H (1) µ PD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, V DD = 5 V ±10%) (2/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µ PD70208H-10 µ PD70216H-10 MIN. MAX. µ PD70208H-12 µ PD70216H-12 MIN. MAX. µPD70208H-16 µPD70216H-16 MIN. Unit MAX. CLKOUT↑ → ASTB↓ delay time <34> tDKSTL ASTB high-level width <35> tSTST tKKL –10 t KKL–10 t KKL–10 ns ASTB↓ → address hold time <36> tHSTA t KKH–20 tKKH–10 t KKH–10 ns CLKOUT → control 1Note 1 45 35 30 ns delay time <37> tDKCT1 5 60 5 50 5 40 ns CLKOUT → control 2Note 2 delay time <38> tDKCT2 5 55 5 45 5 35 ns Address float → RD↓ delay time <39> tDAFRL 0 CLKOUT↓ → RD↓ delay time <40> tDKRL 5 65 CLKOUT↓ → RD↑ delay time <41> tDKRH 5 60 RD↑ → address delay time <42> tDRHA t CYK–40 tCYK–20 t CYK–10 ns RD low-level width <43> tRR 2tCYK–40 2tCYK–20 2tCYK–20 ns BUFEN↑ → BUFR/W delay time (read cycle) <44> tDBECT tKKL –20 t KKL–10 t KKL–10 ns CLKOUT↓ → data output delay time <45> tDKD 5 55 5 40 5 30 ns CLKOUT↓ → data float delay time <46> tFKD 5 55 5 40 5 30 ns WR low-level width <47> tWW 2tCYK–40 2tCYK–20 2tCYK–20 ns WR↑ → BUFEN↑ or BUFR/W↓ (write cycle) <48> tDWCT tKKL –20 t KKL–10 t KKL–10 ns CLKOUT↑ → BS↓ delay time <49> tDKBL 5 55 5 40 5 30 ns CLKOUT↓ → BS↑ delay time <50> tDKBH 5 55 5 40 5 30 ns HLDRQ setup time (vs. CLKOUT↓) <51> tSHQK 15 CLKOUT↓ → HLDAK delay time <52> tDKHA 5 60 5 50 5 40 ns CLKOUT↑ → DMAAK delay time <53> tDKHDA 5 55 5 45 5 35 ns CLKOUT↓ → DMAAK delay time (cascade mode) <54> tDKLDA 5 80 5 70 5 55 ns WR low-level width DMA extended write <55> tWW1 2tCYK–40 2tCYK–20 2tCYK–20 ns (DMA cycle) DMA normal write <56> tWW2 t CYK–40 tCYK–20 t CYK–15 ns RD↓, WR↓ delay time (vs. DMAAK↓) <57> tDDARW t KKH–30 tKKH–20 t KKH–15 ns DMAAK↑ delay time (vs. RD↑) <58> tDRHDAH tKKL –30 t KKL–20 t KKL–15 ns RD↑ delay time (vs. WR↑) <59> tDWHRH 3 3 3 ns TC output delay time (vs. CLKOUT↑) <60> tDKTCL TC OFF delay time (vs. CLKOUT↑) <61> tDKTCF TC low-level width <62> tTCTCL TC pull-up delay time (vs. CLKOUT↑) <63> tDKTCH END setup time (vs. CLKOUT↑) <64> tSEDK 30 25 20 ns END low-level width <65> tEDEDL 80 65 50 ns DMARQ setup time (vs. CLKOUT↑) <66> tSDQK 30 20 15 ns INTPn low-level width <67> tIPIPL 80 80 80 ns RXD setup time (vs. SCU internal clock↓) <68> tSRX 500 500 500 ns Notes 1. 2. 3. 4. 0 0 5 50 5 45 10 55 5 40 5 35 7 35 45 tCYK–10 Note 3 35 t CYK–10 Note 4 ns ns ns 45 55 t CYK–15 ns ns ns ns Note 4 ns MWR and IOWR signals in DMA cycle MWR and IOWR signals in CPU cycles and BUFEN, BUFR/W, INTAK and REFRQ signals. tKKH + 2tCYK – 10 (Reference value when a 1.1-kΩ pull-up resistor is connected.) tKKH + 2tCYK – 5 (Reference value when a 1.1-kΩ pull-up resistor is connected.) Data Sheet U13225EJ4V0DS00 69 µPD70208H, 70216H (1) µ PD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, V DD = 5 V ±10%) (3/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µPD70208H-10 µPD70216H-10 MIN. MAX. MIN. MAX. MIN. Unit MAX. <69> t HRX CLKOUT↓ → SRDY delay time <70> t DKSR TOUT1↓ → TXD delay time <71> t DTX TCTL2 setup time (vs. CLKOUT↓) <72> t SGK 40 40 40 ns TCTL2 setup time (vs. TCLK↑) <73> t SGTK 40 40 40 ns TCTL2 hold time (vs. CLKOUT↓) <74> t HKG 80 80 80 ns TCTL2 hold time (vs. TCLK↑) <75> t HTKG 40 40 40 ns TCTL2 high-level width <76> t GGH 40 40 40 ns TCTL2 low-level width <77> t GGL 40 40 40 ns TOUT output delay time (vs. CLKOUT↓) <78> t DKTO 150 150 150 TOUT output delay time (vs. TCLK↓) <79> t DTKTO 100 100 100 ns TOUT output delay time (vs. TCTL2↓) <80> t DGTO 90 90 90 ns TCLK rise time <81> t TKR 25 25 25 ns TCLK fall time <82> t TKF 25 25 25 ns TCLK high-level width <83> t TKTKH 45 40 30 ns TCLK low-level width <84> t TKTKL 45 40 30 ns TCLK cycle <85> t CYTK 100 Access REFRQ↑ delay time (vs. <86> t AI MRD↑)Note 2 RESET pulse width Note 3 500 µ PD70208H-16 µ PD70216H-16 RX D hold time (vs. SCU internal clock↓) intervalNote 1 500 µPD70208H-12 µPD70216H-12 100 100 200 DC 500 100 200 80 DC ns 200 62.5 DC ns ns ns ns 2tCYK–40 2tCYK–25 2tCYK–20 ns <87> t DRQHRH t KKL–30 t KKL–15 tKKL –10 ns <88> t WRESL 4tCYK 4tCYK 4tCYK ns Notes 1. Specification to guarantee read/write recovery time for I/O device. 2. Specification to guarantee that REFRQ↑ is always later than MRD↑. Only guaranteed when the EREF bit of the SCTL register is 0. 3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used. 70 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H (2) µ PD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 5 V ±5%) (1/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µPD70208H-20 µPD70216H-20 Unit MIN. MAX. External clock input cycle <1> tCYX 25 DC External clock input high-level width (VKH =3.0 V) <2> tXXH 10 External clock input low-level width (V KL=1.5 V) <3> tXXL 10 External clock input rise time (1.5→3.0 V) <4> tXR 5 ns External clock input fall time (3.0→1.5 V) <5> tXF 5 ns Clock output cycle <6> tCYK 50 DC ns Clock output high-level width (VOH =3.0 V) <7> tKKH 0.5t CYK–5 ns Clock output low-level width (V OL=1.5 V) <8> tKKL 0.5t CYK–5 ns Clock output rise time (1.5→3.0 V) <9> tKR 5 ns Clock output fall time (3.0→1.5 V) <10> tKF 5 ns CLKOUT delay time (vs. external clock) <11> tDXK 20 ns Input rise time (except external clock) (0.8→2.2 V) <12> tIR 15 ns Input fall time (except external clock) (2.2→0.8 V) <13> tIF 10 ns Output rise time (except CLKOUT) (0.8→2.2 V) <14> tOR 10 ns Output fall time (except CLKOUT) (2.2→0.8 V) <15> tOF CLKOUT↓) Note 1 ns ns ns 10 ns <16> tSRESK 20 ns RESET hold time (vs. CLKOUT↓) Note 1 <17> tHKRES 10 ns RESOUT output delay time (vs. CLKOUT↓) <18> tDKRES 5 READY inactive setup time (vs. CLKOUT↑) <19> tSRYLK 7 ns READY inactive hold time (vs. CLKOUT↑) <20> tHKRYL 10 ns READY active setup time (vs. CLKOUT↑) <21> tSRYHK 7 ns READY active hold time (vs. CLKOUT↑) <22> tHKRYH 10 ns NMI setup time (vs. CLKOUT↑) <23> tSNMIK 10 ns POLL setup time (vs. CLKOUT↑) <24> tSPOLK 20 ns Data setup time (vs. CLKOUT↓) <25> tSDK 7 ns Data hold time (vs. CLKOUT↓) <26> tHKD 5 ns CLKOUT → address delay <27> tDKA 5 CLKOUT → address hold time <28> tHKA 5 CLKOUT ↓ → PS delay time <29> tDKP 5 30 ns CLKOUT ↓ → PS float delay time <30> tFKP 5 30 ns <31> tSAST t KKL–10 <32> tFKA tHKA 25 ns RESET setup time (vs. timeNote 2 Address setup time (vs. ASTB↓) CLKOUT ↓ → address float delay timeNote 3 25 25 ns ns ns ns CLKOUT ↓ → ASTB ↑ delay time <33> tDKSTH 20 ns CLKOUT ↑ → ASTB ↓ delay time <34> tDKSTL 20 ns ASTB high-level width <35> tSTST t KKL–10 ns Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing. 2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. 3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. Data Sheet U13225EJ4V0DS00 71 µPD70208H, 70216H (2) µPD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 5 V ±5%) (2/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µPD70208H-20 µPD70216H-20 MIN. Unit MAX. ASTB ↓ → address hold time <36> tHSTA tKKH–10 CLKOUT → control delay time <37> tDKCT1 5 25 ns CLKOUT → control 2Note 2 delay time <38> tDKCT2 5 30 ns Address float → RD ↓ delay time <39> tDAFRL 0 CLKOUT ↓ → RD ↓ delay time <40> tDKRL 5 25 CLKOUT ↓ → RD ↑ delay time <41> tDKRH 5 28 RD ↑ → address delay time <42> tDRHA tCYK–5 ns RD low-level width <43> tRR 2tCYK–15 ns BUFEN ↑ → BUFR/W delay time (read cycle) <44> tDBECT tKKL–10 ns CLKOUT ↓ → data output delay time <45> tDKD 5 25 ns CLKOUT ↓ → data float delay time <46> tFKD 5 25 ns WR low-level width <47> tWW 2tCYK–15 ns WR ↑ → BUFEN ↑ or BUFR/W ↓ (write cycle) <48> tDWCT tKKL–10 ns CLKOUT ↑ → BS ↓ delay time <49> tDKBL 5 30 ns CLKOUT ↓ → BS ↑ delay time <50> tDKBH 5 25 ns HLDRQ setup time (vs. CLKOUT ↓) <51> tSHQK 7 CLKOUT ↓ → HLDAK delay time <52> tDKHA 5 25 ns CLKOUT ↑ → DMAAK delay time <53> tDKHDA 5 25 ns CLKOUT ↓ → DMAAK delay time (cascade mode) <54> tDKLDA 5 45 ns DMA extended write <55> tWW1 2tCYK–15 ns DMA normal write <56> tWW2 tCYK–15 ns RD ↓, WR ↓ delay time (vs. DMAAK ↓) <57> tDDARW tKKH–10 ns DMAAK ↑ delay time (vs. RD ↑) <58> tDRHDAH tKKL–10 ns RD ↑ delay time (vs. WR ↑) <59> tDWHRH 3 ns TC output delay time (vs. CLKOUT ↑) <60> tDKTCL TC OFF delay time (vs. CLKOUT ↑) <61> tDKTCF TC low-level width <62> tTCTCL TC pull-up delay time (vs. CLKOUT ↑) <63> tDKTCH END setup time (vs. CLKOUT ↑) <64> tSEDK 20 ns END low-level width <65> tEDEDL 40 ns DMARQ setup time (vs. CLKOUT ↑) <66> tSDQK 10 ns INTPn low-level width <67> tIPIPL 60 ns RxD setup time (vs. SCU internal clock ↓) <68> tSRX 500 ns RxD hold time (vs. SCU internal clock ↓) <69> tHRX 500 CLKOUT ↓ → SRDY delay time <70> tDKSR 1Note 1 WR low-level width (DMA cycle) Notes 1. MWR and IOWR signals in DMA cycle 2. MWR and IOWR signals in BUFEN, BUFR/W, INTAK, REFRQ, and CPU cycles 3. tKKH + 2tCYK – 5 (reference value when a 1.1-kΩ pull-up resistor is connected) 72 Data Sheet U13225EJ4V0DS00 ns ns ns ns ns 25 ns 25 ns tCYK–10 ns Note 3 ns ns 100 ns µPD70208H, 70216H (2) µPD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 5 V ±5%) (3/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µPD70208H-20 µPD70216H-20 MIN. Unit MAX. TOUT1 ↓ → TxD delay time <71> tDTX TCTL2 setup time (vs. CLKOUT ↓) <72> tSGK 40 ns TCTL2 setup time (vs. TCLK ↑) <73> tSGTK 40 ns TCTL2 hold time (vs. CLKOUT ↓) <74> tHKG 80 ns TCTL2 hold time (vs. TCLK ↑) <75> tHTKG 40 ns TCTL2 high-level width <76> tGGH 40 ns TCTL2 low-level width <77> tGGL 40 TOUT output delay time (vs. CLKOUT ↓) <78> tDKTO 150 ns TOUT output delay time (vs. TCLK ↓) <79> tDTKTO 100 ns TOUT output delay time (vs. TCTL2 ↓) <80> tDGTO 90 ns TCLK rise time <81> tTKR 25 ns TCLK fall time <82> tTKF 25 ns TCLK high-level width <83> tTKTKH 23 ns TCLK low-level width <84> tTKTKL 23 ns TCLK cycle <85> tCYTK Access intervalNote 1 <86> tAI REFRQ ↑ delay time (vs. MRD ↑)Note 2 widthNote 3 RESET pulse 200 50 ns ns DC ns 2tCYK–15 ns <87> tDRQHRH tKKL–10 ns <88> tWRESL 4tCYK ns Notes 1. This rating is to guarantee the read/write recovery time for the I/O device. 2. This rating is to guarantee that REFRQ ↑ is always behind MRD ↑, and guaranteed only when the EREF bit of the STCL register is 0. 3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used. Data Sheet U13225EJ4V0DS00 73 µPD70208H, 70216H RECOMMENDED OSCILLATOR The clock input circuits (1) and (2) shown below are recommended. (1) Ceramic resonator connection (TA = –40 to +85 °C, VDD = 5 V ±10% (µPD70208H, 70216H-10/12/16), VDD = 5 V ±5% (µPD70208H, 70216H-20)) X2 X1 C2 C1 Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins. 2. No other signal lines should pass through the area enclosed in dashed line. 3. For matching between V40HL, V50HL and resonator, the efficient evaluation should be carried out. 4. The values of the oscillator constants C1 and C2 depend on the characteristics of the resonator used. Evaluate them with the resonator actually used. Manufacturer Frequency (fXX) [MHz] Product Name Recommended Constant C1 [pF] Murata Mfg. Co., Ltd. TDK Corp. C2 [pF] 40 CSA40.00MXZ040 3 3 32 CSA32.00MXZ040 5 5 25 CSA25.00MXZ040 5 5 20 CSA20.00MXZ040 10 10 32 FCR32.0M2G 5 5 25 FCR25.0M2G 5 5 20 FCR20.0M2G 10 10 (2) External clock input X1 X1 X2 X2 Open or High-speed CMOS Inverter High-speed CMOS Inverter External Clock External Clock Caution The high-speed CMOS inverter should be as close as possible to the X1 and X2 pins. 74 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H 16.2 AT 3 V OPERATION OPERATING RANGE E, P, X, M Masks µPD70208H, 70216H-10/12/16 Others VDD = 3 V ±10% µPD70208H, 70216H-20 VDD = 3 V ±10% — ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Symbol Test Conditions Rating Unit Supply voltage VDD –0.5 to +7.0 V Input voltage VI –0.5 to VDD + 0.3 V Clock input voltage VK –0.5 to VDD + 1.0 V Output voltage VO –0.5 to VDD + 0.3 V Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C VDD = 3 V ±10% Cautions 1. Do not directly connect the output pins of two or more IC products and do not directly connect the output pins to VDD or VCC and GND. However, open-drain pins or open-collector pins may be connected directly. Moreover, an external circuit whose timing is designed to avoid output collision can be connected to pins that go into a high-impedance state. 2. If even one of the above parameters exceeds the absolute maximum rating even momentarily, the quality of the program may be degraded. Absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. Use the program keeping all the parameters within these rated values. The standards and conditions shown in DC and AC Characteristics below specify the range within which the normal operation of the product is guaranteed. Data Sheet U13225EJ4V0DS00 75 µPD70208H, 70216H DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 3 V ±10%) Parameter Input voltage high Input voltage low Symbol VIH VIL Test Conditions MIN. TYP. MAX. Unit V Except RESET 0.7 VDD VDD+0.3 RESET 0.8 VDD VDD+0.3 –0.5 0.2 VDD V Except RESET RESET Clock input voltage high VKH 0.8 VDD VDD+0.5 V Clock input voltage low VKL –0.5 0.2 VDD V Output voltage high VOH Output voltage low VOL IOH = –2.5 mA 0.7 VDD IOH = –100 µA VDD – 0.4 V Except END/TC : IOL = 2.5 mA END/TC 0.4 V 10 µA : IOL = 5.0 mA Input leak current high ILIH VI = VDD Input leak current low ILIL VI = 0 V : Except INTP –10 µA INTP input current low ILIPL VI = 0 V : INTP input –300 µA Output leak current high ILOH VO = VDD 10 µA Output leak current low ILOL VO = 0 V –10 µA Latch leak current high ILLH VI = 3.0 V –50 –300 µA Latch leak current low ILLL VI = 0.8 V 50 300 µA Latch inversion current (L → H) IILH 400 µA Latch inversion current (H → L) IILL –400 µA Supply currentNote IDD mA E, P, X, M On Operation 3.0 fX 5.5 fX masks On standby (HALT) 0.9 fX 1.5 fX On standby (STOP) Others 30 µA mA On Operation 2.5 fX 4.0 fX On standby (HALT) 0.9 fX 1.5 fX On standby (STOP) 30 µA MAX. Unit Note The unit of constant values (0.9, 1.5, 2.5, 3.0, 4.0 and 5.5) is mA/MHz. CAPACITANCE (TA = 25˚C, VDD = 0 V) Parameter Symbol Test Conditions MIN. TYP. Input capacitance CI fC = 1 MHz 10 pF Input/output capacitance CIO 0 V other than test pin. 15 pF 76 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H AC CHARACTERISTICS (1) µ PD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, V DD = 3 V ±10%) (1/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µ PD70208H-10 µ PD70216H-10 µ PD70208H-12 µ PD70216H-12 µPD70208H-16 µPD70216H-16 Unit MIN. MAX. MIN. MAX. MIN. MAX. External clock input cycle <1> tCYX 100 DC 83 DC 62.5 DC External clock input high-level width (VKH=0.8 V DD) <2> tXXH 40 30 20 ns External clock input low-level width (V KL=0.2 V DD) <3> tXXL 40 30 20 ns External clock input rise time (0.2 V DD→0.8 VDD) <4> tXR 10 10 10 ns External clock input fall time (0.8 VDD→0.2 VDD) <5> tXF 10 10 10 ns Clock output cycle <6> tCYK DC ns Clock output high-level width (VOH =0.7 VDD) <7> tKKH 0.5t CYK–7 Clock output low-level width (V OL=0.2 V DD) <8> tKKL 0.5t CYK–7 Clock output rise time (0.2 V DD→0.7 VDD) <9> tKR 7 7 7 ns Clock output fall time (0.7 VDD→0.2 VDD) <10> tKF 7 7 7 ns CLKOUT delay time (vs. external clock) <11> tDXK 75 65 55 ns Input rise time (except external clock) (0.2 VDD→0.7 VDD) <12> tIR 20 20 20 ns Input fall time (except external clock) (0.7 VDD→0.2 VDD) <13> tIF 12 12 12 ns Output rise time (except CLKOUT) (0.2 VDD→0.7 VDD) <14> tOR 20 20 20 ns Output fall time (except CLKOUT) (0.7 V DD→0.2 VDD) <15> tOF 12 12 12 ns CLKOUT↓) Note 1 200 DC 166 DC 0.5tCYK–7 125 0.5t CYK–7 0.5tCYK–7 ns ns 0.5t CYK–7 ns <16> tSRESK 25 25 25 ns RESET hold time (vs. CLKOUT↓) Note 1 <17> tHKRES 35 35 35 ns RESOUT output delay time (vs. CLKOUT↓) <18> tDKRES 5 READY inactive setup time (vs. CLKOUT↑) <19> tSRYLK 20 20 15 ns READY inactive hold time (vs. CLKOUT↑) <20> tHKRYL 30 30 25 ns READY active setup time (vs. CLKOUT↑) <21> tSRYHK 20 20 15 ns READY active hold time (vs. CLKOUT↑) <22> tHKRYH 30 30 25 ns NMI setup time (vs. CLKOUT↑) <23> tSNMIK 15 15 15 ns POLL setup time (vs. CLKOUT↑) <24> tSPOLK 20 20 20 ns Data setup time (vs. CLKOUT↓) <25> tSDK 20 20 15 ns Data hold time (vs. CLKOUT↓) <26> tHKD 5 5 5 ns CLKOUT → address delay <27> tDKA 5 CLKOUT → address hold time <28> tHKA 5 CLKOUT↓ → PS delay time <29> tDKP 5 80 5 70 5 60 ns CLKOUT↓ → PS float delay time <30> tFKP 5 80 5 70 5 60 ns <31> tSAST tKKL –30 RESET setup time (vs. time Note 2 Address setup time (vs. ASTB↓) CLKOUT↓ → address float delay time Note 3 80 75 5 5 70 65 5 5 5 60 55 5 t KKL–30 ns ns ns t KKL–30 ns <32> tFKA 5 80 5 70 5 60 ns CLKOUT↓ → ASTB↑ delay time <33> tDKSTH 5 65 5 55 5 45 ns CLKOUT↑ → ASTB↓ delay time <34> tDKSTL 5 70 5 60 5 50 ns ASTB high-level width <35> tSTST tKKL –10 t KKL–10 t KKL–10 ns Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing. 2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. 3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. Data Sheet U13225EJ4V0DS00 77 µPD70208H, 70216H (1) µ PD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, V DD = 3 V ±10%) (2/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µPD70208H-10 µPD70216H-10 MIN. ASTB↓ → address hold time <36> t HSTA t KKH–30 MAX. µPD70208H-12 µPD70216H-12 MIN. MAX. t KKH–30 µPD70208H-16 µPD70216H-16 MIN. Unit MAX. t KKH–20 ns CLKOUT → control 1Note 1 delay time <37> t DKCT1 5 90 5 80 5 70 ns CLKOUT → control 2Note 2 delay time 80 5 70 5 60 ns <38> t DKCT2 5 Address float → RD↓ delay time <39> t DAFRL 0 CLKOUT↓ → RD↓ delay time <40> t DKRL 5 95 5 85 5 75 ns CLKOUT↓ → RD↑ delay time <41> t DKRH 5 90 5 80 5 70 ns RD↑ → address delay time <42> t DRHA t CYK–70 t CYK–60 t CYK–50 ns RD low-level width <43> t RR 2tCYK–70 2tCYK–60 2tCYK–50 ns BUFEN↑ → BUFR/W delay time (read cycle) <44> t DBECT t KKL–30 t KKL–30 tKKL –20 ns CLKOUT↓ → data output delay time <45> t DKD 5 80 5 70 5 60 ns CLKOUT↓ → data float delay time <46> t FKD 5 80 5 70 5 60 ns WR low-level width <47> t WW 2tCYK–50 2tCYK–50 2tCYK–40 ns WR↑ → BUFEN↑ or BUFR/W↓ (write cycle) <48> t DWCT t KKL–30 t KKL–30 tKKL –20 ns CLKOUT↑ → BS↓ delay time <49> t DKBL 5 80 5 70 5 60 ns CLKOUT↓ → BS↑ delay time <50> t DKBH 5 80 5 70 5 60 ns HLDRQ setup time (vs. CLKOUT↓) <51> t SHQK 25 CLKOUT↓ → HLDAK delay time <52> t DKHA 5 90 5 80 5 70 ns CLKOUT↑ → DMAAK delay time <53> t DKHDA 5 80 5 70 5 60 ns CLKOUT↓ → DMAAK delay time (cascade mode) <54> t DKLDA 5 110 5 100 5 90 ns WR low-level width (DMA cycle) DMA extended write <55> t WW1 2tCYK–50 2tCYK–50 2tCYK–40 ns DMA normal write <56> t WW2 t CYK–50 t CYK–50 t CYK–40 ns RD↓ WR↓ delay time (vs. DMAAK↓) <57> t DDARW t KKH–40 t KKH–40 t KKH–30 ns DMAAK↑ delay time (vs. RD↑) <58> t DRHDAH t KKL–40 t KKL–40 tKKL –30 ns RD↑ delay time (vs. WR↑) <59> t DWHRH 5 TC output delay time (vs. CLKOUT↑) <60> t DKTCL 5 80 5 70 5 60 ns TC OFF delay time (vs. CLKOUT↑) <61> t DKTCF 5 80 5 70 5 60 ns TC low-level width <62> t TCTCL t CYK–25 TC pull-up delay time (vs. CLKOUT↑) <63> t DKTCH END setup time (vs. CLKOUT↑) <64> t SEDK 45 40 35 ns END low-level width <65> t EDEDL 140 120 100 ns DMARQ setup time (vs. CLKOUT↑) <66> t SDQK 45 40 35 ns INTPn low-level width <67> t IPIPL 100 100 100 ns RX D setup time (vs. SCU internal clock↓) <68> t SRX 1000 1000 1000 ns RX D hold time (vs. SCU internal clock↓) <69> t HRX 1000 1000 1000 ns CLKOUT↓ → SRDY delay time <70> t DKSR Notes 1. 2. 3. 4. 78 0 0 25 20 5 150 ns t CYK–15 Note 4 ns Note 4 150 MWR and IOWR signals in DMA cycle MWR and IOWR signals in CPU cycles and BUFEN, BUFR/W, INTAK and REFRQ signals. t KKH + 2tCYK – 20 (Reference value when a 1.1-kΩ pull-up resistor is connected) t KKH + 2tCYK – 10 (Reference value when a 1.1-kΩ pull-up resistor is connected) Data Sheet U13225EJ4V0DS00 ns 5 t CYK–25 Note 3 ns 150 ns ns µPD70208H, 70216H (1) µ PD70208H, 70216H-10/12/16 (TA = –40 to +85 °C, V DD = 3 V ±10%) (3/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µPD70208H-10 µPD70216H-10 MIN. MAX. µPD70208H-12 µPD70216H-12 MIN. MAX. µ PD70208H-16 µ PD70216H-16 MIN. Unit MAX. TOUT1↓→ TX D delay time <71> t DTX TCTL2 setup time (vs. CLKOUT↓) <72> t SGK 50 50 50 ns TCTL2 setup time (vs. TCLK↑) <73> t SGTK 50 50 50 ns TCTL2 hold time (vs. CLKOUT↓) <74> t HKG 100 100 100 ns TCTL2 hold time (vs. TCLK↑) <75> t HTKG 50 50 50 ns TCTL2 high-level width <76> t GGH 50 50 50 ns TCTL2 low-level width <77> t GGL 50 50 50 ns TOUT output delay time (vs. CLKOUT↓) <78> t DKTO 200 200 200 ns TOUT output delay time (vs. TCLK↓) <79> t DTKTO 150 150 150 ns TOUT output delay time (vs. TCTL2↓) <80> t DGTO 120 120 120 ns TCLK rise time <81> t TKR 25 25 25 ns TCLK fall time <82> t TKF TCLK high-level width <83> t TKTKH 60 55 50 ns TCLK low-level width <84> t TKTKL 60 55 50 ns TCLK cycle <85> t CYTK 200 Access interval Note 1 <86> t AI 500 500 25 DC 500 25 166 DC 25 125 DC ns ns ns 2tCYK–70 2tCYK–60 2tCYK–50 ns REFRQ↑ delay time (vs. MRD↑)Note 2 <87> t DRQHRH t KKL–50 t KKL–40 tKKL –30 ns RESET pulse width Note 3 <88> t WRESL 4tCYK 4tCYK 4tCYK ns Notes 1. Specification to guarantee read/write recovery time for I/O device. 2. Specification to guarantee that REFRQ↑ is always later than MRD↑. Only guaranteed when the EREF bit of the SCTL register is 0. 3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used. Data Sheet U13225EJ4V0DS00 79 µPD70208H, 70216H (2) µ PD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 3 V ±10%) (1/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µPD70208H-20 µPD70216H-20 Unit MIN. MAX. External clock input cycle <1> tCYX 50 DC External clock input high-level width (VKH=0.8 V DD) <2> tXXH 19 ns External clock input low-level width (V KL=0.2 V DD) <3> tXXL 19 ns External clock input rise time (0.2 V DD→0.8 VDD) <4> tXR 5 ns External clock input fall time (0.8 VDD→0.2 VDD) <5> tXF 5 ns Clock output cycle <6> tCYK 100 DC ns Clock output high-level width (VOH =0.7 VDD) <7> tKKH 0.5tCYK –7 Clock output low-level width (V OL=0.2 V DD) <8> tKKL 0.5tCYK –7 Clock output rise time (0.2 V DD→0.7 VDD) <9> tKR 7 ns Clock output fall time (0.7 VDD→0.2 VDD) <10> tKF 7 ns CLKOUT delay time (vs. external clock) <11> tDXK 45 ns Input rise time (except external clock) (0.2 V DD→0.7 VDD) <12> tIR 15 ns Input fall time (except external clock) (0.7 VDD→0.2 VDD) <13> tIF 10 ns Output rise time (except CLKOUT) (0.2 VDD→0.7 VDD) <14> tOR 15 ns Output fall time (except CLKOUT) (0.7 V DD→0.2 VDD) <15> tOF 10 ns RESET setup time (vs. CLKOUT↓) Note 1 ns ns ns <16> tSRESK 25 ns RESET hold time (vs. CLKOUT↓) Note 1 <17> tHKRES 25 ns RESOUT output delay time (vs. CLKOUT↓) <18> tDKRES 5 READY inactive setup time (vs. CLKOUT↑) <19> tSRYLK 15 ns READY inactive hold time (vs. CLKOUT↑) <20> tHKRYL 20 ns READY active setup time (vs. CLKOUT↑) <21> tSRYHK 15 ns READY active hold time (vs. CLKOUT↑) <22> tHKRYH 20 ns NMI setup time (vs. CLKOUT↑) <23> tSNMIK 15 ns POLL setup time (vs. CLKOUT↑) <24> tSPOLK 20 ns Data setup time (vs. CLKOUT↓) <25> tSDK 15 ns Data hold time (vs. CLKOUT↓) <26> tHKD 5 ns CLKOUT → address delay <27> tDKA 5 CLKOUT → address hold time <28> tHKA 5 CLKOUT ↓ → PS delay time <29> tDKP 5 50 ns CLKOUT ↓ → PS float delay time <30> tFKP 5 50 ns <31> tSAST tKKL –20 <32> tFKA t HKA time Note 2 Address setup time (vs. ASTB↓) CLKOUT ↓ → address float delay timeNote 3 50 50 ns ns ns ns 50 ns CLKOUT ↓ → ASTB ↑ delay time <33> tDKSTH 40 ns CLKOUT ↑ → ASTB ↓ delay time <34> tDKSTL 45 ns ASTB high-level width <35> tSTST tKKL –10 ns Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing. 2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. 3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing. 80 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H (2) µ PD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 3 V ±10%) (2/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µPD70208H-20 µPD70216H-20 MIN. ASTB ↓ → address hold time <36> tHSTA t KKH–20 Unit MAX. ns CLKOUT → control 1Note 1 delay time <37> t DKCT1 5 60 ns CLKOUT → control 2Note 2 delay time 55 ns <38> t DKCT2 5 Address float → RD ↓ delay time <39> t DAFRL 0 CLKOUT ↓ → RD ↓ delay time <40> tDKRL 5 65 ns CLKOUT ↓ → RD ↑ delay time <41> t DKRH 5 60 ns RD ↑ → address delay time <42> t DRHA RD low-level width <43> tRR BUFEN ↑ → BUFR/W delay time (read cycle) <44> t DBECT CLKOUT ↓ → data output delay time <45> tDKD CLKOUT ↓ → data float delay time WR low-level width WR ↑ → BUFEN ↑ or BUFR/W ↓ (write cycle) ns t CYK–40 ns 2tCYK–40 ns tKKL –20 ns 5 55 ns <46> tFKD 5 55 ns <47> t WW 2tCYK–40 ns <48> t DWCT tKKL –20 ns CLKOUT ↑ → BS ↓ delay time <49> t DKBL 5 55 ns CLKOUT ↓ → BS ↑ delay time <50> t DKBH 5 55 ns HLDRQ setup time (vs. CLKOUT ↓) <51> t SHQK 15 CLKOUT ↓ → HLDAK delay time <52> t DKHA 5 60 ns CLKOUT ↑ → DMAAK delay time <53> t DKHDA 5 55 ns 80 ns CLKOUT ↓ → DMAAK delay time (cascade mode) ns <54> t DKLDA 5 DMA extended write <55> t WW1 2tCYK–40 ns DMA normal write <56> t WW2 t CYK–40 ns RD ↓, WR ↓ delay time (vs. DMAAK ↓) <57> t DDARW t KKH–30 ns DMAAK ↑ delay time (vs. RD ↑) <58> t DRHDAH tKKL –30 ns RD ↑ delay time (vs. WR ↑) <59> t DWHRH 3 ns TC output delay time (vs. CLKOUT ↑) <60> t DKTCL 55 ns TC OFF delay time (vs. CLKOUT ↑) <61> t DKTCF 55 ns TC low-level width <62> t TCTCL TC pull-up delay time (vs. CLKOUT ↑) <63> t DKTCH END setup time (vs. CLKOUT ↑) <64> t SEDK 30 ns END low-level width <65> t EDEDL 80 ns DMARQ setup time (vs. CLKOUT ↑) <66> t SDQK 30 ns INTPn low-level width <67> t IPIPL 80 ns RxD setup time (vs. SCU internal clock ↓) <68> t SRX 500 ns RxD hold time (vs. SCU internal clock ↓) <69> t HRX 500 ns CLKOUT ↓ → SRDY delay time <70> t DKSR WR low-level width (DMA cycle) t CYK–15 ns Note 3 100 ns ns Notes 1. MWR and IOWR signals in DMA cycle 2. MWR and IOWR signals in CPU cycles and BUFEN, BUFR/W, INTAK and REFRQ signals. 3. tKKH + 2tCYK – 10 (reference value when a 1.1-kΩ pull-up resistor is connected) Data Sheet U13225EJ4V0DS00 81 µPD70208H, 70216H (2) µPD70208H, 70216H-20 (TA = –40 to +85 °C, VDD = 3 V ±10%) (3/3) Output Pin Load Capacitance: CL = 100 pF Parameter Symbol µPD70208H-20 µPD70216H-20 MIN. Unit MAX. TOUT1 ↓ → TxD delay time <71> tDTX TCTL2 setup time (vs. CLKOUT ↓) <72> tSGK 40 ns TCTL2 setup time (vs. TCLK ↑) <73> tSGTK 40 ns TCTL2 hold time (vs. CLKOUT ↓) <74> tHKG 80 ns TCTL2 hold time (vs. TCLK ↑) <75> tHTKG 40 ns TCTL2 high-level width <76> tGGH 40 ns TCTL2 low-level width <77> tGGL 40 ns TOUT output delay time (vs. CLKOUT ↓) <78> tDKTO 150 ns TOUT output delay time (vs. TCLK ↓) <79> tDTKTO 100 ns TOUT output delay time (vs. TCTL2 ↓) <80> tDGTO 90 ns TCLK rise time <81> tTKR 25 ns TCLK fall time <82> tTKF 25 ns TCLK high-level width <83> tTKTKH TCLK low-level width <84> tTKTKL 45 TCLK cycle <85> tCYTK 100 Access intervalNote 1 REFRQ ↑ delay time (vs. MRD RESET pulse <86> tAI ↑)Note 2 widthNote 3 200 45 ns ns ns DC ns 2tCYK–40 ns <87> tDRQHRH tKKL–30 ns <88> tWRESL 4tCYK ns Notes 1. This rating is to guarantee the read/write recovery time for the I/O device. 2. This rating is to guarantee that REFRQ ↑ is always behind MRD ↑, and is guaranteed only when the EREF bit of the STCL register is 0. 3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the resonator and oscillator actually used. 82 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H RECOMMENDED OSCILLATOR The clock input circuits (1) and (2) shown below are recommended. (1) Ceramic resonator connection (TA = –40 to +85 °C, VDD = 3 V ±10%Note) X2 X1 C2 C1 Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins. 2. No other signal lines should pass through the area enclosed in dashed line. 3. V40HL, V50HL and resonator matching requires careful evaluation. 4. The values of the oscillator constants C1 and C2 depend on the characteristics of the resonator used. Evaluate them with the resonator actually used. Manufacturer Frequency (fXX) [MHz] Product Name Recommended Constant C1 [pF] CSA20.00MXZ040Note 10 10 CSA16.00MXZ040 15 15 CSA16.00MXW0C3 – – CSA12.5MTZ 30 30 CSA12.5MTW – – CSA10.0MTZ 30 30 CST10.0MXW – – 20 FCR20.0M2G 10 10 16 FCR16.0M2G 15 15 10 FCR10.0MC – – 20 Murata Mfg. Co., Ltd. 16 12.5 10 TDK Corp. Note C2 [pF] Use the CAS20.00MXZ040 within the range of VDD = 2.9 to 3.3 V. (2) External clock input X1 X1 X2 X2 Open or High-speed CMOS Inverter High-speed CMOS Inverter External Clock External Clock Caution The high-speed CMOS inverter should be as close as possible to the X1 and X2 pins. Data Sheet U13225EJ4V0DS00 83 µPD70208H, 70216H AC Test Input Waveform (Except X1 and X2) (at 5 V operation) 2.4 V 2.2 V Test points 0.8 V 0.4 V 2.2 V 0.8 V AC Test Output Test Points (at 5 V operation) 2.2 V 0.8 V Test points 2.2 V 0.8 V AC Test Input Waveform (Except X1 and X2) (at 3 V operation) 0.8 VDD 0.7 VDD 0.4 V 0.2 VDD Test points 0.7 VDD 0.2 VDD AC Test Output Waveform (at 3 V operation) 0.7 VDD 0.2 VDD Test points 0.7 VDD 0.2 VDD Load Conditions DUT C L = 100pF Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, the load capacitance of this device should be reduced to 100 pF or less by insertion of a buffer, etc. 84 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H Clock Timing <1> <4> <5> <2> External Clock (Input) (X1) <11> <3> <11> <6> <9> <10> <7> CLKOUT (Output) <8> Reset Timing CLKOUT (Output) <16> <17> <16> <88> RESET (Input) Note <18> <18> RESOUT (Output) Ready Timing (1) T1 T2 T3 T4 T1 CLKOUT (Output) <22> <21> READY (Input) Variation Range Variation Range Ready Timing (2) T1 T2 T3 TW T4 CLKOUT (Output) <22> <19> READY (Input) <21> Note Variation Range Variation Range <20> Note Variation range Data Sheet U13225EJ4V0DS00 85 µPD70208H, 70216H Read Timing T4 T1 T2 T3 T4 CLKOUT (Output) <27> <30> <28> A16/PS0A19/PS3 (Output) A16-A19 PS0-PS3 <27> <31> <29> <27> <31> <28> <32> A8-A15 (Output): V40HL UBE (Output): V50HL AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL <25> A0-A7(Output) : V40HL A0-A15(Output) : V50HL <33> D0-D7(Intput) : V40HL D0-D15(Intput): V50HL <36> <35> <26> ASTB (Output) <34> <38> <38> Note BUFEN (Output) <38> <38> <44> <39> BUFR/W (Output) <40> <41> MRD (Output) IORD (Output) Note <43> BS0-BS2 (Output) Bus Status <49> <50> Note High-level signal is output in case of internal access. Remark A dashed line indicates high impedance. 86 Data Sheet U13225EJ4V0DS00 <42> µPD70208H, 70216H Write Timing T4 T1 T2 T3 T4 CLKOUT (Output) <27> A16/PS0A19/PS3 (Output) <28> <30> A16-A19 <27> PS0-PS3 <29> <31> A8-A15 (Output): V40HL UBE (Output): V50HL <27> AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL <45> A0-A7 (Output) : V40HL A0-A15 (Output) : V50HL <46> D0-D7 (Output) : V40HL D0-D15 (Output) : V50HL <28> <31> <35> ASTB (Output) <34> <33> <36> <38> <38> BUFEN (Output) Note <48> <38> <38> BUFR/W (Output) <38> MWR (Output) IOWR (Output) <38> Note <47> Bus Status BS0-BS2 (Output) <49> <50> Note High-level signal is output in case of internal access. Remark A dashed line indicates high impedance. Data Sheet U13225EJ4V0DS00 87 µPD70208H, 70216H Status Timing T4 T1 T2 T3 T4 CLKOUT (Output) <28> <27> A16/PS0A19/PS3 (Output) <30> <29> A16-A19 <27> PS0-PS3 <31> A8-A15 (Output): V40HL UBE (Output): V50HL <25> <27> AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL <28> <32> <31> <26> A0-A7 (Output) : V40HL A0-A15 (Output): V50HL <33> D0-D7 (Input) : V40HL D0-D15 (Input): V50HL <36> <42> <35> ASTB (Output) <34> <50> Bus Status BS0-BS2 (Output) <39> <49> Note 1 <41> Note 2 <27> <40> <43> QS0, QS1 (Output) Notes 1. MRD, IORD, MWR, IOWR (all output) 2. High-level signal is output in case of internal access. Remark A dashed line indicates high impedance. 88 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H Interrupt Acknowledge Timing (V40HL) T1 T2 T3 T4 T2 T1 T3 TI CLKOUT (Output) A8-A15 (Output) Note 1 <27> <32> <32> Note 1 AD0-AD7 (I/O) <25> <26> Note 2 Vector Number ASTB (Output) <38> INTAK (Output) <38> <38> Note 3 BUFEN (Output) Note 3 BUFR/W (Output) <27> BUSLOCK (Output) Notes 1. Slave address in case of interrupt from external µPD71059. Invalid data in case of interrupt from internal ICU. 2. Data read as vector address in case of interrupt from external µPD71059. High impedance in case of interrupt from internal ICU. * 3. Low-level output in case of interrupt from external µPD71059. High-level output in case of interrupt from internal ICU. Remark A dashed line indicates high impedance. Data Sheet U13225EJ4V0DS00 89 µPD70208H, 70216H Interrupt Acknowledge Timing (V50HL) T2 T1 T3 TI×3 T4 T1 T2 T3 TI <25> <26> CLKOUT (Output) <27> <32> <32> Note 1 AD0-AD15 (I/O) Note 2 Vector Number ASTB (Output) <38> INTAK (Output) <38> <38> BUFEN (Output) Note 3 BUFR/W (Output) <27> BUSLOCK (Output) Notes 1. Slave address in case of interrupt from external µPD71059. Invalid data in case of interrupt from internal ICU. 2. Data read as vector address in case of interrupt from external µPD71059. High impedance in case of interrupt from internal ICU. * 3. Low-level output in case of interrupt from external µPD71059. High-level output in case of interrupt from internal ICU. Remark A dashed line indicates high impedance. 90 Data Sheet U13225EJ4V0DS00 Note 3 µPD70208H, 70216H HLDRQ/HLDAK Timing (1) TI TI T4 T1 CLKOUT (Output) <51> <51> HLDRQ (Input) <52> <52> HLDAK (Output) <27> <32> Note <27> <32> BS0-BS2 (Output) Note A16/PS0 to A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR (all output): V40HL, V50HL A8-A15 (output): V40HL AD0-AD7 (input/output): V40HL AD0-AD15 (input/output) V50HL Remark A dashed line indicates high impedance. HLDRQ/HLDAK Timing (2) TI TI TI TI T4 T1 T2 CLKOUT (Output) <51> HLDRQ (Input) Variation Range <52> <6> or longer HLDAK (Output) <27> Highest-Priority Refresh Cycle or DMA Cycle Note <49> BS0-BS2 (Output) Note Highest-Priority Refresh Cycle or DMA Cycle A16/PS0 to A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR (all output): V40HL, V50HL A8-A15 (output): V40HL AD0-AD7 (input/output): V40HL AD0-AD15 (input/output) V50HL Remark A dashed line indicates high impedance. Data Sheet U13225EJ4V0DS00 91 µPD70208H, 70216H POLL, NMI Input Timing Tn CLKOUT (Output) <24> POLL (Input) <23> NMI (Input) BUSLOCK Output Timing CLKOUT (Output) <27> <27> BUSLOCK (Output) Access Interval <86> MRD (Output) IORD (Output) <86> <86> MWR (Output) IOWR (Output) <86> 92 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H Refresh Timing (V40HL) T4 T1 T2 T3 T4 CLKOUT (Output) <28> <27> A16/PS0A19/PS3 (Output) <29> Invalid <27> Refresh Address A8-A15 (Output) <27> <28> <31> <32> Refresh Address AD0-AD7 (I/O) <33> <36> <35> ASTB (Output) <34> BUFEN (Output) <41> <39> <40> MRD (Output) <43> <38> <38> REFRQ (Output) <49> BS0-BS2 (Output) <50> BS2 = 1, BS1 = 0, BS0 = 1 Remark A dashed line indicates high impedance. Data Sheet U13225EJ4V0DS00 93 µPD70208H, 70216H Refresh Timing (V50HL) T4 T1 T2 T3 T4 CLKOUT (Output) <28> <27> A16/PS0A19/PS3 (Output) <29> Invalid <27> UBE (Output) <27> AD0-AD15 (I/O) <28> <32> <31> Refresh Address <33> <36> <35> ASTB (Output) <34> BUFEN (Output) <39> <41> <40> MRD (Output) <38> <43> REFRQ (Output) <49> BS0-BS2 (Output) <50> BS2 = 1, BS1 = 0, BS0 = 1 Remark A dashed line indicates high impedance. 94 Data Sheet U13225EJ4V0DS00 <38> µPD70208H, 70216H TCU Timing (1) CLKOUT (Output) <72> <72> <76> <77> <74> <74> TCTL2 (Input) <80> Note <78> TOUTn (Output) (n=1, 2) Note Applies to TOUT2 output. TCU Timing (2) <81> <82> <83> <85> TCLK (Input) <84> <75> <73> <76> <73> <75> TCTL2 (Input) <77> Note <80> <79> TOUTn (Output) (n=1, 2) Note Applies to TOUT2 output. Data Sheet U13225EJ4V0DS00 95 µPD70208H, 70216H SCU Timing RxD (Input) <68> <69> TOUT1 (Output) 16 Cycles or 64 Cycles 16 Cycles or 64 Cycles TxD (Output) <71> CLKOUT (Output) <70> SRDY (Output) 96 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H DMAU Timing (1) T4 T1 T2 T3 T4 CLKOUT (Output) <49> <50> Bus Status BS0-BS2 (Output) <33> <36> <35> ASTB (Output) <27> <34> <29> <28> A16/PS0A19/PS3 (Output) <27> A8-A15 (Output): V40HL UBE (Output): V50HL <27> <28> <32> AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL <53> <53> DMAAK (Output) <39> <40> <57> MRD (Output) IORD (Output) <37> <57> <41> <37> <37> <55> <56> MWR (Output) IOWR (Output) <58> <43> <59> Note Note Low-level signal is output in extended write mode. Remark A dashed line indicates high impedance. Data Sheet U13225EJ4V0DS00 97 µPD70208H, 70216H DMAU Timing (2) T1 T2 T3 T4 CLKOUT (Output) <61> <60> <63> TC (Input/Output) <64> <62> <65> END (Input/Output) CLKOUT (Output) <66> DMARQn (Input) (n=0-3) 98 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H DMAU Timing (3) (Cascade Mode) In Normal Operation: T1 T4 CLKOUT (Output) <66> <66> DMARQ (Input) <54> <54> DMAAK (Output) When Refresh Cycle is Inserted: CLKOUT (Output) DMARQ (Input) <54> <54> DMAAK (Output) ICU Timing <67> INTPn (Input) (n=1-7) Data Sheet U13225EJ4V0DS00 99 µPD70208H, 70216H 17. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14x20) A B 41 40 64 65 detail of lead end S C D Q R 25 24 80 1 F G J H I M K P M N S L S NOTE 1. Controlling dimension millimeter. ITEM 2. Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 23.6±0.4 0.929±0.016 B 20.0±0.2 0.795 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.6±0.4 0.693±0.016 F 1.0 0.039 G 0.8 0.031 H 0.37 +0.08 –0.07 0.015 +0.003 –0.004 0.006 I 0.15 J 0.8 (T.P.) 0.031 (T.P.) K 1.8±0.2 0.071 +0.008 –0.009 L 0.8±0.2 0.031 +0.009 –0.008 M 0.17 +0.08 –0.07 0.007 +0.003 –0.004 N 0.10 0.004 P 2.7±0.1 0.106 +0.005 –0.004 Q 0.1±0.1 0.004±0.004 R S 5°±5° 5°±5° 3.0 MAX. 0.119 MAX. P80GF-80-3B9-4 100 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H 80 PIN PLASTIC TQFP (FINE PITCH) ( 12) A B 41 60 61 40 Q F 80 21 1 G R S D C detail of lead end 20 H I M J M P K N L NOTE ITEM Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 14.0±0.2 0.551±0.008 B 12.0±0.2 0.472 +0.009 –0.008 C 12.0±0.2 0.472 +0.009 –0.008 D 14.0±0.2 0.551±0.008 F 1.25 0.049 G 1.25 0.049 H 0.22±0.05 0.009+0.002 –0.003 I 0.10 0.004 J 0.5 (T.P.) 0.020 (T.P.) K 1.0±0.2 0.039+0.009 –0.008 L 0.5±0.2 0.020+0.008 –0.009 M 0.145±0.05 0.006 +0.002 –0.003 N 0.10 0.004 P 1.0±0.05 0.040 +0.002 –0.003 Q 0.1±0.05 0.004±0.002 R 3° +7° –3° 3° +7° –3° S 1.2 MAX. 0.048 MAX. S80GK-50-9EU Data Sheet U13225EJ4V0DS00 101 µPD70208H, 70216H 68 PIN PLASTIC QFJ (950 x 950 mil) A B 68 1 G H C D J E F S U K Q M N S M P I NOTES 1. Controlling dimension T ITEM MILLIMETERS 25.2±0.2 0.992±0.008 B 24.20±0.1 0.953 +0.004 −0.005 C 24.20±0.1 0.953 +0.004 −0.005 D 25.2±0.2 0.992±0.008 E 1.94±0.15 0.076 +0.007 −0.006 millimeter. 2. Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. INCHES A F 0.6 0.024 G 4.4±0.2 0.173 +0.009 −0.008 H 2.8±0.2 0.110 +0.009 −0.008 I 0.9 MIN. 0.035 MIN. J 3.4±0.1 0.134 +0.004 −0.005 K 1.27 (T.P.) 0.050 (T.P.) M 0.42±0.08 0.017 +0.003 −0.004 N 0.12 0.005 P 23.12±0.2 0.910 +0.009 −0.008 Q 0.15 0.006 T R 0.8 R 0.031 U 0.22 +0.08 −0.07 0.009 +0.003 −0.004 P68L-50A1-3 102 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H 18. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For the details of recommended soldering conditions for the surface mounting type, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our salesman. Table 18-1. Soldering Conditions (1) µ PD70208HGF-×-3B9 : 80-pin plastic QFP (14 × 20 mm) µ PD70216HGF-×-3B9 : 80-pin plastic QFP (14 × 20 mm) (a) K, E, X masks Soldering Method Soldering Conditions Recommended Conditions Symbol Infrared reflow Package peak temperature : 230 °C, Time: 30 sec. max. (210 °C min.), Number of times: 1, Number of daysNote : 7 days (after this, prebaking is necessary at 125 °C for 10 hours) IR30-107-1 VPS Package peak temperature: 215 °C, Time: 40 sec. max. (200 °C min.), VP15-107-1 Number of times: 1, Number of daysNote: 7 days (after this, prebaking is necessary at 125 °C for 10 hours) Solder bath temperature: 260 °C max. Time: 10 sec. max., Number of times: 1, Preheating temperature: 120 °C max. (Package surface temperature), Number of Wave soldering WS60-107-1 days Note: 7 days (after this, prebaking is necessary at 125 °C for 10 hours). Partial pin heating Pin temperature: 300 °C max., Time: 3 sec. max. (per device side) — (b) P, M masks Soldering Method Soldering Conditions Recommended Conditions Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 sec. max. (210 °C min.), Number of times: 2 max., Number of daysNote: 7 days (after this, prebaking is necessary at 125 °C for 20 hours). IR35-207-2 VPS Package peak temperature: 215 °C, Time: 40 sec. (200 °C min.) VP15-207-2 Number of times: 2 max., Number of daysNote: 7 days (after this prebaking is necessary at 125 °C for 20 hours). Solder bath temperature: 260 °C max., Time: 10 sec. max., Number of times: 1, Preheating temperature: 120 °C max. (Package surface Wave soldering WS60-207-1 temperature). Number of daysNote: 7 days (after this, prebaking is necessary at 125 °C for 20 hours). Partial pin heating Note Pin temperature: 300 °C max., Time: 3 sec. max. (per device side) — This means the number of days after unpacking the dry pack. Storage conditions are 25 °C and 65% RH max. Data Sheet U13225EJ4V0DS00 103 µPD70208H, 70216H (c) L, F masks Soldering Method Soldering Conditions Recommended Conditions Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 sec. max. (210 ˚C min.), Number of times: 3 max. IR35-00-3 VPS Package peak temperature: 215 °C, Time: 40 sec. (200 °C min.) Number of times: 3 max. VP15-00-3 Wave soldering Solder bath temperature: 260 °C max., Time: 10 sec. max., Number of times: 1, Preheating temperature: 120 °C max. (Package surface temperature) WS60-00-1 Partial pin heating Pin temperature: 300 °C max., Time: 3 sec. max. (per device side) — Caution Do not use one soldering method in combination with another. (however, partial pin heating can be performed with other soldering methods). 104 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H (2) µPD70208HGK-×-9EU : 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD70216HGK-×-9EU : 80-pin plastic TQFP (fine pitch) (12 × 12 mm) (a) K, E, X masks Soldering Method Soldering Conditions Recommended Conditions Symbol Infrared reflow Package peak temperature : 230 °C, Time: 30 sec. max. (210 °C min.), Number of timers: 1, Number of daysNote: 1 day (after this, prebaking is necessary at 125 °C for 10 hours) IR30-101-1 VPS Package peak temperature: 215 °C, Time: 40 sec. max. (200 °C min.), Number of times: 1, Number of daysNote: 1 day (after this, prebaking is necessary at 125 °C for 10 hours) VP15-101-1 Partial pin heating Pin temperature: 300 °C max., Time: 3 sec. max. (per device side) — (b) P, M, L, F masks Soldering Method Soldering Conditions Recommended Conditions Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 sec. max. (210 °C min.), Number of times: 2 max., Number of daysNote: 7 days (after this, prebaking is necessary at 125 °C for 10 hours). IR35-107-2 VPS Package peak temperature: 215 °C, Time: 40 sec. (200 °C min.), Number of times: 2 max., Number of daysNote: 7 days (after this prebaking is necessary at 125 °C for 10 hours). VP15-107-2 Partial heating Pin temperature: 300 °C max., Time: 3 sec. max. (per device side) Note — This means the number of days after unpacking the dry pack. Storage conditions are 25 °C and 65% RH max. Caution Do not use one soldering method in combination with another. (however, partial pin heating can be performed with other soldering methods). Data Sheet U13225EJ4V0DS00 105 µPD70208H, 70216H (3) µPD70208HLP-× : 68-pin plastic QFJ (950 × 950 mil) µPD70216HLP-× : 68-pin plastic QFJ (950 × 950 mil) (a) K, E, X masks Soldering Method Soldering Conditions Recommended Conditions Symbol Infrared reflow Package peak temperature : 230 °C, Time: 30 sec. max. (210 °C min.), Number of timers: 1, Number of daysNote: 7 days (after this, prebaking is necessary at 125 °C for 36 hours) IR30-367-1 VPS Package peak temperature: 215 °C, Time: 40 sec. max. (200 °C min.), Number of times: 1, Number of daysNote: 7 days (after this, prebaking is necessary at 125 °C for 36 hours) VP15-367-1 Partial pin heating Pin temperature: 300 °C max., Time: 3 sec. max. (per device side) — (b) P, M, L, F masks Soldering Method Soldering Conditions Recommended Conditions Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 sec. max. (210 ˚C min.), Number of times: 3 max., Number of daysNote: 7 days (after this, prebaking is necessary at 125 °C for 36 hours). IR35-367-3 VPS Package peak temperature: 215 °C, Time: 40 sec. (200 °C min.), Number of times: 3 max., Number of daysNote: 7 days (after this prebaking is necessary at 125 °C for 36 hours). VP15-367-3 Partial pin heating Pin temperature: 300 °C max., Time: 3 sec. max. (per device side) Note — This means the number of days after unpacking the dry pack. Storage conditions are 25 °C and 65% RH max. Caution Do not use one soldering method in combination with another. (however, partial pin heating can be performed with other soldering methods). 106 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H [MEMO] Data Sheet U13225EJ4V0DS00 107 µPD70208H, 70216H NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 108 Data Sheet U13225EJ4V0DS00 µPD70208H, 70216H Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. 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Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U13225EJ4V0DS00 109 µPD70208H, 70216H [MEMO] V20, V20HL, V30, V30HL, V40, V40HL, V50, V50HL and V series are trademarks of NEC Corporation. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. 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