NEC UPD703102GJ-33

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703100-33, 703100-40, 703101-33, 703102-33
TM
V850E/MS1
32/16-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD703101-33 and µPD703102-33 are members of the V850 FamilyTM of 32-bit single-chip microcontrollers
designed for real-time control operations. These microcontrollers provide on-chip features, including a 32-bit CPU
core, ROM, RAM, interrupt controller, real-time pulse unit, serial interface, A/D converter, and DMA controller.
The µPD703100-33 and µPD703100-40 are ROM-less versions of the µPD703101-33 and µPD703102-33
products.
The µPD703100-A33, µPD703100-A40, µPD703101-A33, and µPD703102-A33 are also available as products
having a 3.3-V power supply for external pins.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850E/MS1 User’s Manual Hardware:
U12688E
V850E/MS1 User’s Manual Architecture: U12197E
FEATURES
• Number of instructions: 81
• Minimum instruction execution time 25 ns (@ 40-MHz operation) ····· µPD703100-40
30 ns (@ 33-MHz operation) ····· µPD703100-33, 703101-33, 703102-33
• General registers 32 bits × 32
• Instruction set optimized for control applications
• Internal memory ROM : None (µPD703100-33, 703100-40),
96 Kbytes (µPD703101-33),
128 Kbytes (µPD703102-33)
RAM : 4 Kbytes
• Advanced on-chip interrupt controller
• Real-time pulse unit suitable for control operations
• Powerful serial interface (on-chip dedicated baud rate generator)
• On-chip clock generator
• 10-bit resolution A/D converter: 8 channels
• DMA controller: 4 channels
• Power saving functions
APPLICATIONS
• Office automation equipment: printers, facsimile machines, PPCs, etc.
• Multimedia equipment: digital still cameras, video printers, etc.
• Consumer equipment: single-lens reflex cameras, etc.
• Industrial equipment: motor controllers, NC machine tools, etc.
The information in this document is subject to change without notice.
Document No. U13995EJ1V0DS00 (1st edition)
Date Published April 1999 N CP(K)
Printed in Japan
©
1999
µPD703100-33, 703100-40, 703101-33, 703102-33
ORDERING INFORMATION
Part Number
Package
Maximum Operating
Frequency (MHz)
Internal ROM
(bytes)
µPD703100GJ-33-8EU
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
33 MHz
None
µPD703100GJ-40-8EU
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
40 MHz
None
µPD703101GJ-33-xxx-8EU
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
33 MHz
96 Kbytes
µPD703102GJ-33-xxx-8EU
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
33 MHz
128 Kbytes
Remark xxx indicates ROM code suffix.
PIN CONFIGURATION (Top view)
144-pin plastic LQFP (fine pitch) (20 × 20 mm)
• µPD703101GJ-33-xxx-8EU
• µPD703100GJ-40-8EU
• µPD703102GJ-33-xxx-8EU
144
142
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
VDD
D0/P40
D1/P41
D2/P42
D3/P43
D4/P44
D5/P45
D6/P46
D7/P47
VSS
D8/P50
D9/P51
D10/P52
D11/P53
D12/P54
D13/P55
D14/P56
D15/P57
HVDD
A0/PA0
A1/PA1
A2/PA2
A3/PA3
A4/PA4
A5/PA5
A6/PA6
A7/PA7
VSS
A8/PB0
A9/PB1
A10/PB2
A11/PB3
A12/PB4
A13/PB5
A14/PB6
A15/PB7
• µPD703100GJ-33-8EU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
NMI/P20
P21
TXD0/SO0/P22
RXD0/SI0/P23
SCK0/P24
TXD1/SO1/P25
RXD1/SI1/P26
SCK1/P27
VDD
INTP133/SCK2/P37
INTP132/SI2/P36
INTP131/SO2/P35
INTP130/P34
TI13/P33
TCLR13/P32
TO131/P31
TO130/P30
INTP143/SCK3/P117
INTP142/SI3/P116
INTP141/SO3/P115
INTP140/P114
TI14/P113
TCLR14/P112
TO141/P111
TO140/P110
CVDD
X2
X1
CVSS
CKSEL
MODE0
MODE1
MODE2
MODE3
RESET
INTP153/ADTRG/P127
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
INTP103/DMARQ3/P07
INTP102/DMARQ2/P06
INTP101/DMARQ1/P05
INTP100/DMARQ0/P04
TI10/P03
TCLR10/P02
TO101/P01
TO100/P00
VSS
INTP113/DMAAK3/P17
INTP112/DMAAK2/P16
INTP111/DMAAK1/P15
INTP110/DMAAK0/P14
TI11/P13
TCLR11/P12
TO111/P11
TO110/P10
INTP123/TC3/P107
INTP122/TC2/P106
INTP121/TC1/P105
INTP120/TC0/P104
TI12/P103
TCLR12/P102
TO121/P101
TO120/P100
ANI7/P77
ANI6/P76
ANI5/P75
ANI4/P74
ANI3/P73
ANI2/P72
ANI1/P71
ANI0/P70
AVDD
AVSS
AVREF
2
Preliminary Data Sheet U13995EJ1V0DS00
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
HVDD
CS0/RAS0/P80
CS1/RAS1/P81
CS2/RAS2/P82
CS3/RAS3/P83
CS4/RAS4/IOWR/P84
CS5/RAS5/IORD/P85
CS6/RAS6/P86
CS7/RAS7/P87
LCAS/LWR/P90
UCAS/UWR/P91
RD/P92
WE/P93
BCYST/P94
OE/P95
HLDAK/P96
HLDRQ/P97
VSS
REFRO/PX5
WAIT/PX6
CLKOUT/PX7
TO150/P120
TO151/P121
TCLR15/P122
TI15/P123
INTP150/P124
INTP151/P125
INTP152/P126
µPD703100-33, 703100-40, 703101-33, 703102-33
PIN NAMES
A0 to A23
: Address Bus
P50 to P57
: Port 5
ADTRG
: AD Trigger Input
P60 to P67
: Port 6
ANI0 to ANI7
: Analog Input
P70 to P77
: Port 7
AVDD
: Analog Power Supply
P80 to P87
: Port 8
AVREF
: Analog Reference Voltage
P90 to P97
: Port 9
AVSS
: Analog Ground
P100 to P107
: Port 10
BCYST
: Bus Cycle Start Timing
P110 to P117
: Port 11
CKSEL
: Clock Generator Operating Mode Select
P120 to P127
: Port 12
CLKOUT
: Clock Output
PA0 to PA7
: Port A
CS0 to CS7
: Chip Select
PB0 to PB7
: Port B
CVDD
: Clock Generator Power Supply
PX5 to PX7
: Port X
CVSS
: Clock Generator Ground
RAS0 to RAS7
: Row Address Strobe
D0 to D15
: Data Bus
RD
: Read
DMAAK0 to DMAAK3 : DMA Acknowledge
REFRQ
: Refresh Request
DMARQ0 to DMARQ3 : DMA Request
RESET
: Reset
HLDAK
: Hold Acknowledge
RXD0, RXD1
: Receive Data
HLDRQ
: Hold Request
SCK0 to SCK3
: Serial Clock
HVDD
: Power Supply for External Pins
SI0 to SI3
: Serial Input
INTP100 to INTP103, : Interrupt Request from Peripherals
SO0 to SO3
: Serial Output
INTP110 to INTP113,
TC0 to TC3
: Terminal Count Signal
INTP120 to INTP123,
TCLR10 to TCLR15 : Timer Clear
INTP130 to INTP133,
TI10 to TI15
: Timer Input
INTP140 to INTP143,
TO100, TO101,
: Timer Output
INTP150 to INTP153
TO110, TO111,
IORD
: I/O Read Strobe
TO120, TO121,
IOWR
: I/O Write Strobe
TO130, TO131,
LCAS
: Lower Column Address Strobe
TO140, TO141,
LWR
: Lower Write Strobe
TO150, TO151
MODE0 to MODE3
: Mode
TXD0, TXD1
: Transmit Data
NMI
: Non-Maskable Interrupt Request
UCAS
: Upper Column Address Strobe
OE
: Output Enable
UWR
: Upper Write Strobe
P00 to P07
: Port 0
VDD
: Power Supply for Internal Unit
P10 to P17
: Port 1
VSS
: Ground
P20 to P27
: Port 2
WAIT
: Wait
P30 to P37
: Port 3
WE
: Write Enable
P40 to P47
: Port 4
X1, X2
: Crystal
Preliminary Data Sheet U13995EJ1V0DS00
3
µPD703100-33, 703100-40, 703101-33, 703102-33
INTERNAL BLOCK DIAGRAM
HLDRQ
NMI
INTP100 to INTP103,
INTP110 to INTP113,
INTP120 to INTP123,
INTP130 to INTP133,
INTP140 to INTP143,
INTP150 to INTP153
CPU
ROM
BCU
HLDAK
INTC
CS0 to CS7/RAS0 to RAS7
IOWR
Instruction queue
IORD
Multiplier
(32 × 32 → 64)
Note
DRAMC
REFRQ
BCYST
PC
TO100, TO101,
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141,
TO150, TO151
WE
RD
Barrel
shifter
RPU
RAM
Page ROM
controller
System registers
OE
UWR/UCAS
LWR/LCAS
TCLR10 to TCLR15
4 Kbytes
TI10 to TI15
WAIT
ALU
General registers
(32 bits × 32)
A0 to A23
D0 to D15
DMAC
DMARQ0 to DMARQ3
DMAAK0 to DMARQ3
SIO
SO0/TXD0
SI0/RXD0
SCK0
TC0 to TC3
UART0/CSI0
BRG0
SO1/TXD1
SI1/RXD1
SCK1
CKSEL
Port
UART1/CSI1
CLKOUT
CG
HVDD
P00 to P07
P20
P10 to P17
P21 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
P100 to P107
PA0 to PA7
P110 to P117
BRG2
SO3
SI3
SCK3
P120 to P127
CSI2
PB0 to PB7
SO2
SI2
SCK2
PX5 to PX7
BRG1
X1
X2
CVDD
CVSS
System
controller
MODE0 to MODE3
RESET
CSI3
VDD
ANI0 to ANI7
AVREF
AVSS
AVDD
ADTRG
VSS
ADC
Note µPD703100-33, 703100-40: None
µPD703101-33: 96 Kbytes (mask ROM)
µPD703102-33: 128 Kbytes (mask ROM)
4
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
CONTENTS
1.
DIFFERENCES AMONG PRODUCTS...........................................................................................
7
2.
PIN FUNCTIONS .............................................................................................................................
8
2.1
2.2
2.3
3.
Port Pins .................................................................................................................................
Non-port Pins .........................................................................................................................
Pin I/O Circuits and Recommended Connection of Unused Pins.....................................
8
11
15
FUNCTION BLOCKS ......................................................................................................................
18
3.1
Internal Units ..........................................................................................................................
18
3.1.1
CPU ...........................................................................................................................................
18
3.1.2
Bus control unit (BCU) ...............................................................................................................
18
3.1.3
ROM ..........................................................................................................................................
18
3.1.4
RAM...........................................................................................................................................
19
3.1.5
Ports ..........................................................................................................................................
19
3.1.6
Interrupt controller (INTC)..........................................................................................................
19
3.1.7
Clock generator (CG).................................................................................................................
19
3.1.8
Real-time pulse unit (RPU) ........................................................................................................
19
3.1.9
Serial interface (SIO) .................................................................................................................
19
3.1.10 A/D converter (ADC) ..................................................................................................................
19
4.
CPU FUNCTIONS............................................................................................................................
20
5.
BUS CONTROL FUNCTIONS........................................................................................................
20
6.
MEMORY ACCESS CONTROL FUNCTIONS ..............................................................................
21
6.1
6.2
SRAM Connection..................................................................................................................
Page ROM Controller (ROMC) ..............................................................................................
21
22
6.2.1
Features.....................................................................................................................................
22
6.2.2
Page ROM connection...............................................................................................................
22
DRAM Controller ....................................................................................................................
24
6.3.1
Features.....................................................................................................................................
24
6.3.2
DRAM Connections ...................................................................................................................
24
7.
DMA FUNCTIONS (DMA CONTROLLER) ...................................................................................
26
8.
INTERRUPT/EXCEPTION PROCESSING FUNCTIONS...............................................................
28
8.1
Features ..................................................................................................................................
28
CLOCK GENERATION FUNCTIONS ............................................................................................
33
10. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT).....................................................
34
6.3
9.
Preliminary Data Sheet U13995EJ1V0DS00
5
µPD703100-33, 703100-40, 703101-33, 703102-33
11. SERIAL INTERFACE FUNCTION ..................................................................................................
11.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1).......................................................
11.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3) ...................................................................
11.3 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)..................................................
37
37
38
40
12. A/D CONVERTER............................................................................................................................ 41
13. PORT FUNCTIONS ......................................................................................................................... 42
14. RESET FUNCTION .......................................................................................................................... 53
15. INSTRUCTION SET ......................................................................................................................... 54
16. ELECTRICAL SPECIFICATIONS (PRELIMINARY VALUES)...................................................... 64
17. PACKAGE DRAWING ..................................................................................................................... 120
18. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 121
6
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
1. DIFFERENCES AMONG PRODUCTS
µPD703100
Product Name
Item
–33
Internal ROM
Maximum operating
frequency
HVDD
–40
µPD703101
–A33
–A40
None
33 MHz
–33
–A33
96 Kbytes
(mask ROM)
40 MHz
4.5 to 5.5 V
33 MHz
40 MHz
3.0 to 3.6 V
µPD703102
–33
–A33
µPD70F3102
–33
–A33
128 Kbytes
(mask ROM)
128 Kbytes
(flash memory)
4.5 to
5.5 V
4.5 to
5.5 V
33 MHz
4.5 to
5.5 V
3.0 to
3.6 V
3.0 to
3.6 V
3.0 to
3.6 V
Operation mode
Single-chip
mode 0, 1
None
Provided
Flash memory
programming
mode
None
Provided
Flash memory
programming pin
None
Provided (VPP)
Electrical
specifications
Power consumptions differ (refer to the data sheet of each product).
Package
144LQFP
Others
Noise tolerance and noise radiation will differ due to the differences in circuit scale and mask layout.
144LQFP
157FBGA
144LQFP
144LQFP
157FBGA
144LQFP
144LQFP
157FBGA
144LQFP
144LQFP
157FBGA
Remark 144LQFP: 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
157FBGA: 157-pin plastic FBGA (14 × 14 mm)
Preliminary Data Sheet U13995EJ1V0DS00
7
µPD703100-33, 703100-40, 703101-33, 703102-33
2. PIN FUNCTIONS
2.1 Port Pins
(1/3)
Pin Name
P00
I/O
I/O
P01
Port 0
8-bit I/O port
Input/output mode can be specified in 1-bit units
Alternate Function
TO100
TO101
P02
TCLR10
P03
TI10
P04
INTP100/DMARQ0
P05
INTP101/DMARQ1
P06
INTP102/DMARQ2
P07
INTP103/DMARQ3
P10
I/O
P11
Port 1
8-bit I/O port
Input/output mode can be specified in 1-bit units
TO110
TO111
P12
TCLR11
P13
TI11
P14
INTP110/DMAAK0
P15
INTP111/DMAAK1
P16
INTP112/DMAAK2
P17
INTP113/DMAAK3
P20
I
P21
I/O
P22
P23
P24
Port 2
P20 is an input only port.
When a valid edge is input, this pin operates as NMI input. Also, bit 0
of the P2 register indicates the NMI input status.
P21 to P27 are 7-bit I/O port.
Input/output mode can be specified in 1-bit units
NMI
–
TXD0/SO0
RXD0/SO0
SCK0
P25
TXD1/SO1
P26
RXD1/SI1
P27
SCK1
P30
I/O
P31
Port 3
8-bit I/O port.
Input/output mode can be specified in 1-bit units
TO130
TO131
P32
TCLR13
P33
TI13
P34
INTP130
P35
INTP131/SO2
P36
INTP132/SI2
P37
INTP133/SCK2
P40 to P47
8
Function
I/O
Port 4
8-bit I/O port
Input/output mode can be specified in 1-bit units
Preliminary Data Sheet U13995EJ1V0DS00
D0 to D7
µPD703100-33, 703100-40, 703101-33, 703102-33
(2/3)
Pin Name
I/O
Function
Alternate Function
P50 to P57
I/O
Port 5
8-bit I/O port
Input/output mode can be specified in 1-bit units
D8 to D15
P60 to P67
I/O
Port 6
8-bit I/O port
Input/output mode can be specified in 1-bit units
A16 to A23
P70 to P77
I
Port 7
8-bit input only port
ANI0 to ANI7
Port 8
8-bit I/O port
Input/output mode can be specified in 1-bit units
CS0/RAS0
P80
I/O
P81
CS1/RAS1
P82
CS2/RAS2
P83
CS3/RAS3
P84
CS4/RAS4/IOWR
P85
CS5/RAS5/IORD
P86
CS6/RAS6
P87
CS7/RAS7
P90
I/O
P91
Port 9
8-bit I/O port
Input/output mode can be specified in 1-bit units
LCAS/LWR
UCAS/UWR
P92
RD
P93
WE
P94
BCYST
P95
OE
P96
HLDAK
P97
HLDRQ
P100
I/O
P101
Port 10
8-bit I/O port
Input/output mode can be specified in 1-bit units
TO120
TO121
P102
TCLR12
P103
TI12
P104
INTP120/TC0
P105
INTP121/TC1
P106
INTP122/TC2
P107
INTP123/TC3
P110
P111
I/O
Port 11
8-bit I/O port
Input/output mode can be specified in 1-bit units
TO140
TO141
P112
TCLR14
P113
TI14
P114
INTP140
P115
INTP141/SO3
P116
INTP142/SI3
P117
INTP143/SCK3
Preliminary Data Sheet U13995EJ1V0DS00
9
µPD703100-33, 703100-40, 703101-33, 703102-33
(3/3)
Pin Name
P120
I/O
I/O
P121
Function
Port 12
8-bit I/O port
Input/output mode can be specified in 1-bit units
Alternate Function
TO150
TO151
P122
TCLR15
P123
TI15
P124
INTP150
P125
INTP151
P126
INTP152
P127
INTP153/ADTRG
PA0
I/O
PA1
Port A
8-bit I/O port
Input/output mode can be specified in 1-bit units
A0
A1
PA2
A2
PA3
A3
PA4
A4
PA5
A5
PA6
A6
PA7
A7
PB0
I/O
PB1
Port B
8-bit I/O port
Input/output mode can be specified in 1-bit units
A8
A9
PB2
A10
PB3
A11
PB4
A12
PB5
A13
PB6
A14
PB7
A15
PX5
PX6
I/O
Port X
3-bit I/O port
Input/output mode can be specified in 1-bit units
PX7
10
REFRQ
WAIT
CLKOUT
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
2.2 Non-port Pins
(1/4)
Pin Name
TO100
I/O
O
Function
Pulse signal output for timers 10 to 15
Alternate Function
P00
TO101
P01
TO110
P10
TO111
P11
TO120
P100
TO121
P101
TO130
P30
TO131
P31
TO140
P110
TO141
P111
TO150
P120
TO151
P121
TCLR10
I
External clear signal input for timers 10 to 15
P02
TCLR11
P12
TCLR12
P102
TCLR13
P32
TCLR14
P112
TCLR15
P122
TI10
I
External count clock input for timers 10 to 15
P03
TI11
P13
TI12
P103
TI13
P33
TI14
P113
TI15
P123
INTP100
I
INTP101
External maskable interrupt request input, shared as external capture
trigger input for timer 10
P04/DMARQ0
P05/DMARQ1
INTP102
P06/DMARQ2
INTP103
P07/DMARQ3
INTP110
I
INTP111
External maskable interrupt request input, shared as external capture
trigger input for timer 11
P14/DMAAK0
P15/DMAAK1
INTP112
P16/DMAAK2
INTP113
P17/DMAAK3
INTP120
INTP121
I
External maskable interrupt request input, shared as external capture
trigger input for timer 12
P104/TC0
P105/TC1
INTP122
P106/TC2
INTP123
P107/TC3
Preliminary Data Sheet U13995EJ1V0DS00
11
µPD703100-33, 703100-40, 703101-33, 703102-33
(2/4)
Pin Name
INTP130
I/O
I
INTP131
Function
External maskable interrupt request input, shared as external capture
trigger input for timer 13
Alternate Function
P34
P35/SO2
INTP132
P36/SI2
INTP133
P37/SCK2
INTP140
I
INTP141
External maskable interrupt request input, shared as external capture
trigger input for timer 14
P114
P115/SO3
INTP142
P116/SI3
INTP143
P117/SCK3
INTP150
I
INTP151
External maskable interrupt request input, shared as external capture
trigger input for timer 15
P124
P125
INTP152
P126
INTP153
P127/ADTRG
SO0
O
Serial transmit data output (3-wire) for CSI0 to CSI3
P22/TXD0
SO1
P25/TXD1
SO2
P35/INTP131
SO3
P115/INTP141
SI0
I
Serial receive data input (3-wire) for CSI0 to CSI3
P23/RXD0
SI1
P26/RXD1
SI2
P36/INTP132
SI3
P116/INTP142
SCK0
I/O
Serial clock I/O (3-wire) for CSI0 to CSI3
P24
SCK1
P27
SCK2
P37/INTP133
SCK3
P117/INTP143
TXD0
O
Serial transmit data output for UART0 and UART1
TXD1
RXD0
P25/SO1
I
Serial receive data input for UART0 and UART1
RXD1
D0 to D7
P23/SI0
P26/SI1
I/O
16-bit data bus for external memory
D8 to D15
A0 to A7
P22/SO0
P40 to P47
P50 to P57
O
24-bit address bus for external memory
PA0 to PA7
A8 to A15
PB0 to PB7
A16 to A23
P60 to P67
LWR
O
Lower byte write-enable signal output for external data bus
P90/LCAS
UWR
O
Higher byte write-enable signal output for external data bus
P91/UCAS
RD
O
Read strobe signal output for external data bus
P92
WE
O
Write enable signal output for DRAM
P93
OE
O
Output enable signal output for DRAM
P95
12
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(3/4)
Pin Name
I/O
Function
Alternate Function
LCAS
O
Column address strobe signal output for DRAM’s lower data
P90/LWR
UCAS
O
Column address strobe signal output for DRAM’s higher data
P91/UWR
RAS0 to RAS3
O
Low address strobe signal output for DRAM
P80/CS0 to P83/CS3
RAS4
P84/CS4/IOWR
RAS5
P85/CS5/IORD
RAS6
P86/CS6
RAS7
P87/CS7
BCYST
O
Strobe signal output indicating start of bus cycle
P94
CS0 to CS3
O
Chip select signal output
P80/RAS0 to
P83/RAS3
CS4
P84/RAS4/IOWR
CS5
P85/RAS5/IORD
CS6
P86/RAS6
CS7
P87/RAS7
WAIT
I
Control signal input for inserting waits in bus cycle
PX6
REFRQ
O
Refresh request signal output for DRAM
PX5
IOWR
O
DMA write strobe signal output
P84/RAS4/CS4
IORD
O
DMA read strobe signal output
P85/RAS5/CS5
DMARQ0 to
DMARQ3
I
DMA request signal input
P04/INTP100 to
P07/INTP103
DMAAK0 to
DMAAK3
O
DMA acknowledge signal output
P14/INTP110 to
P17/INTP113
TC0 to TC3
O
DMA end (terminal count) signal output
P104/INTP120 to
P107/INTP123
HLDAK
O
Bus hold acknowledge output
P96
HLDRQ
I
Bus hold request input
P97
ANI0 to ANI7
I
Analog input to A/D converter
P70 to P77
NMI
I
Non-maskable interrupt request input
P20
CLKOUT
O
System clock output
PX7
CKSEL
I
Input for specifying clock generator’s operation mode
–
MODE0 to
MODE3
I
Specify operation modes
–
RESET
I
System reset input
–
X1
I
–
X2
–
Oscillator connection for system clock. Input is via X1 when using an
external clock.
ADTRG
I
A/D converter external trigger input
AVREF
I
Reference voltage input for A/D converter
–
AVDD
–
Positive power supply for A/D converter
–
AVSS
–
Ground potential for A/D converter
–
Preliminary Data Sheet U13995EJ1V0DS00
–
P127/INTP153
13
µPD703100-33, 703100-40, 703101-33, 703102-33
(4/4)
Pin Name
I/O
Function
Alternate Function
CVDD
–
Positive power supply for dedicated clock generator
–
CVSS
–
Ground potential for dedicated clock generator
–
VDD
–
Positive power supply (power supply for internal units)
–
HVDD
–
Positive power supply (power supply for external pins)
–
VSS
–
Ground potential
–
14
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows
the various circuit types using partially abridged diagrams.
When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 kΩ is recommended.
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (1/2)
Pin
I/O Circuit Type
P00/TO100, P01/TO101
5
P02/TCLR10, P03/TI10
5-K
Recommended Connection of Unused Pins
Input : Independently connect to HVDD or VSS via a resistor
Output: Leave open
P04/INTP100/DMARQ0 to
P07/INTP103/DMARQ3
P10/TO110, P11/TO111
5
P12/TCLR11, P13/TI11
5-K
P14/INTP110/DMAAK0 to
P17/INTP113/DMAAK3
P20/NMI
2
Connect directly to VSS
P21
5
Input : Independently connect to HVDD or VSS via a resistor
Output: Leave open
P22/TXD0/SO0
P23/RXD0/SI0
5-K
P24/SCK0
P25/TXD1/SO1
5
P26/RXD1/SI1
5-K
P27/SCK1
P30/TO130, P31/TO131
P32/TCLR13,P33/TI13
5
5-K
P34/INTP130
P35/INTP131/SO2
P36/INTP132/SI2
P37/INTP133/SCK2
P40/D0 to P47/D7
5
P50/D8 to P57/D15
P60/A16 to P67/A23
P70/ANI0 to P77/ANI7
9
Connect directly to VSS
P80/CS0/RAS0 to P83/CS3/RAS3
5
Input : Independently connect to HVDD or VSS via a resistor
Output: Leave open
P84/CS4/RAS4/IOWR,
P85/CS5/RAS5/IORD
P86/CS6/RAS6, P87/CS7/RAS7
P90/LCAS/LWR
P91/UCAS/UWR
Preliminary Data Sheet U13995EJ1V0DS00
15
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (2/2)
Pin
P92/RD
I/O Circuit Type
5
P93/WE
Recommended Connection of Unused Pins
Input : Independently connect to HVDD or VSS via a resistor
Output: Leave open
P94/BCYST
P95/OE
P96/HLDAK
P97/HLDRQ
P100/TO120, P101/TO121
P102/TCLR12, P103/TI12
5-K
P104/INTP120/TC0 to
P107/INTP123/TC3
P110/TO140, P111/TOI41
5
P112/TCLR14, P113/TI14
5-K
P114/INTP140
P115/INTP141/SO3
P116/INTP142/SI3
P117/INTP143/SCK3
P120/TO150, P121/TO151
5
P122/TCLR15, P123/TI15
5-K
P124/INTP150 to P126/INTP152
P127/INTP153/ADTRG
PA0/A0-PA7/A7
5
PB0/A8-PB7/A15
PX5/REFRQ
PX6/WAIT
PX7/CLKOUT
CKSEL
1
RESET
2
Connect directly to HVDD
–
MODE0 to MODE2
MODE3
Connect to VSS via a resistor (RVPP)
AVREF, AVSS
–
Connect directly to VSS
AVDD
–
Connect directly to HVDD
16
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 2-1. Pin I/O Circuits
Type 5-K
Type 1
VDD
VDD
data
P-ch
IN/OUT
P-ch
IN
output
disable
N-ch
N-ch
input
enable
Type 9
Type 2
P-ch
IN
IN
+
–
N-ch
Comparator
VREF (threshold voltage)
input enable
Schmitt trigger input with hysteresis characteristics
Type 5
VDD
data
P-ch
IN/OUT
output
disable
N-ch
input
enable
Caution Replace VDD by HVDD when referencing the circuit diagrams shown above.
Preliminary Data Sheet U13995EJ1V0DS00
17
µPD703100-33, 703100-40, 703101-33, 703102-33
3. FUNCTION BLOCKS
3.1 Internal Units
3.1.1 CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits → 32 bits, or 32 bits × 32 bits → 64
bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.
3.1.2 Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU
generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an
internal instruction queue of the CPU.
The BCU contains DRAM controller (DRAMC), page ROM controller, and DMA controller (DMAC).
(a) DRAM controller (DRAMC)
The DRAM controller generates the RAS, UCAS, and LCAS signals (2CAS control) and controls access to the
DRAM.
It supports high-speed page DRAM and EDO DRAM, and has two types of cycles for accessing DRAM.
These types of cycles are referred to as normal access (off-page) and page access (on-page).
The DRAM controller also has a refresh function that is associated with the CBR refresh cycle.
(b) Page ROM controller
The page ROM controller supports access to ROM that has the page access function.
It compares the address with that of the preceding bus cycle and controls the waits for normal access (offpage) and page access (on-page). The page ROM controller can support page sizes of 8 to 64 bytes.
(c) DMA controller (DMAC)
The DMA controller transfers data between memory and an I/O device in place of the CPU.
The two address modes are flyby (one-cycle) transfer and two-cycle transfer. The three bus modes are single
transfer, single-step transfer, and block transfer.
3.1.3 ROM
The µPD703101-33 contains 96-Kbytes mask ROM, and the µPD703102-33 contains 128-Kbytes mask ROM.
The CPU can access ROM in one clock cycle when an instruction is fetched.
When single-chip mode 0 is set, ROM is mapped to the address space starting at 00000000H. When single-chip
mode 1 is set, ROM is mapped to the address space starting at 00100000H. When ROM-less mode 0 or 1 is set,
ROM cannot be accessed.
The µPD703100-33 and µPD703100-40 have no internal ROM.
18
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
3.1.4 RAM
RAM is mapped to the 4-Kbyte address space starting at FFFFE000H. The CPU can access RAM in one clock
cycle when an instruction is fetched or data is accessed.
3.1.5 Ports
In addition to the 123 pins (ports 0 to 12, A, B, and X) comprising I/O ports (of which nine pins comprise an inputonly port), various port pin and control pin functions can be selected for these pins.
3.1.6 Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP100 to INTP103, INTP110 to INTP113, INTP120 to
INTP123, INTP130 to INTP133, INTP140 to INTP143, and INTP150 to INTP153) from on-chip peripheral I/O and
external hardware.
Eight interrupt priority levels can be specified for these interrupt requests, and multiplexed
servicing control can be performed for interrupt sources.
3.1.7 Clock generator (CG)
A frequency of five times (using an on-chip PLL) or one-half times (not using an on-chip PLL) that of the input
clock (fXX) is supplied as the internal system clock (φ). Either an external oscillator is connected to pins X1 and X2
(only when the on-chip PLL synthesizer is used) or an external clock is input from the X1 pin as the input clock.
3.1.8 Real-time pulse unit (RPU)
The RPU includes a six-channel 16-bit timer/event counter and a two-channel 16-bit interval timer, which enables
measurement of pulse intervals and frequency as well as programmable pulse output.
3.1.9 Serial interface (SIO)
Four channels are comprised of two kinds of serial interfaces: an asynchronous serial interface (UART) and a
clocked serial interface (CSI). Two of these four channels are switchable between the UART and CSI and the other
two channels are fixed as CSI.
For UART, data is transferred via the TXD and RXD pins. For CSI, data is transferred via the SO, SI, and SCK
pins.
The serial clock source can be selected from dedicated baud rate generator output or the internal system clock.
3.1.10 A/D converter (ADC)
This is a high-speed, high-resolution 10-bit A/D converter that includes eight analog input pins. It converts using
the successive approximation method.
Preliminary Data Sheet U13995EJ1V0DS00
19
µPD703100-33, 703100-40, 703101-33, 703102-33
4. CPU FUNCTIONS
{ RISC-based architecture
{ Uses five-stage pipeline control to enable single-clock execution of almost all instructions
25 ns (@ 40-MHz operation) ... µPD703100-40
{ Minimum instruction execution time
30 ns (@ 33-MHz operation) ... µPD703100-33, 703101-33, 703102-33
{ Memory space
Program space : 64-Mbyte linear
Data space
: 4-Gbyte linear
{ General registers 32 bits × 32
{ Internal 32-bit architecture
{ 5-stage pipeline control
{ Multiply/divide instructions
{ Saturated operation instructions
{ 32-bit shift instruction: 1 clock
{ Long/short format
{ Four types of bit manipulation instructions
•
Set
•
Clear
•
Not
•
Test
5. BUS CONTROL FUNCTIONS
{ 16-bit/8-bit data bus sizing function
{ 8-space chip select output function
{ Wait functions
•
Programmable wait function for up to seven states for each memory block
•
External wait function using WAIT pin
{ Idle state insertion function
{ Bus mastering arbitration function
{ Bus hold function
{ Alternate function for port pins are connectable to external bus
20
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
6. MEMORY ACCESS CONTROL FUNCTIONS
6.1 SRAM Connection
The following figure shows an SRAM connection example.
Figure 6-1. SRAM Connection Example
A1 to A17
A0 to A16
D0 to D7
I/O1 to I/O8
D8 to D15
CS
CSn
UWR
WE
LWR
OE
RD
HVDD
5V
5V
VCC
1-Mbit (128 K × 8) SRAM
V850E/MS1
A0 to A16
I/O1 to I/O8
CS
WE
OE
5V
VCC
1-Mbit (128 K × 8) SRAM
Remark n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
21
µPD703100-33, 703100-40, 703101-33, 703102-33
6.2 Page ROM Controller (ROMC)
The page ROM controller (ROMC) supports access to ROM (page ROM) that has the page access function.
It compares the address with that of the preceding bus cycle and performs wait control for normal access (offpage) and page access (on-page). The page ROM controller can support page widths of 8 to 64 bytes.
6.2.1 Features
{ Can be connected directly to 8-bit or 16-bit page ROM
{ For 16-bit bus width, it supports 4-, 8-, 16-, or 32-word page access
For 8-bit bus width, it supports 8-, 16-, 32-, or 64-word page access
{ Enables waits to be set (0 to 7 waits) independently for off-page and on-page access
6.2.2 Page ROM connection
The following figure shows page ROM connection examples.
Figure 6-2. Page ROM Connection Examples (1/2)
(a) 16-Mbit (1 M × 16) page ROM
A1 to A20
A0 to A19
D0 to D15
O1 to O16
RD
OE
CSn
CE
VDD
WORD/BYTE
16-Mbit (1 M × 16) page ROM
V850E/MS1
Remark n = 0 to 7
22
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 6-2. Page ROM Connection Examples (2/2)
(b) 16-Mbit (2 M × 8) page ROM
A1 to A20
A0 to A19
D0 to D7
O0 to O7
RD
OE
CSn
CE
WORD/BYTE
D8 to D15
16-Mbit (2 M × 8) page ROM
V850E/MS1
A0 to A19
O0 to O7
OE
CE
WORD/BYTE
16-Mbit (2 M × 8) page ROM
Remark n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
23
µPD703100-33, 703100-40, 703101-33, 703102-33
6.3 DRAM Controller
6.3.1 Features
{ Generates the RAS, UCAS, and LCAS signals
{ Can be connected directly to high-speed page DRAM and EDO DRAM
{ Supports RAS hold mode
{ Can assign 4 types of DRAM to 8 memory block spaces
{ Supports 2CAS type DRAM
{ Can be switched between row and column address multiplex widths
{ Can insert waits (0 to 3 waits) at each of the following timings
•
Row address pre-charge wait
•
Row address hold wait
•
Data access wait
•
Column address pre-charge wait
{ Supports CBR refresh and CBR self refresh
6.3.2 DRAM Connections
The following figure shows DRAM connection examples.
Figure 6-3. DRAM Connection Examples (1/2)
(a) 16-Mbit (1 M × 16) DRAM
A1 to A10
A0 to A9
D0 to D15
I/O1 to I/O16
RASn
RASn
LCAS
LCAS
UCAS
UCAS
V850E/MS1
WE
WE
OE
OE
16-Mbit (1 M × 16) DRAM
Remark n = 0 to 7
24
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 6-3. DRAM Connection Examples (2/2)
(b) 4-Mbit (1 M × 4) DRAM
A0 to A9
A0 to A9
I/O1 to I/O4
I/O1 to I/O4
RASn
RAS
RAS
LCAS
CAS
CAS
WE
WE
WE
OE
OE
OE
A1 to A10
D0 to D7
D8 to D15
UCAS
V850E/MS1
4-Mbit (1 M × 4) DRAM
4-Mbit (1 M × 4) DRAM
A0 to A9
A0 to A9
I/O1 to I/O4
I/O1 to I/O4
RAS
RAS
CAS
CAS
WE
WE
OE
OE
4-Mbit (1 M × 4) DRAM
4-Mbit (1 M × 4) DRAM
Remark n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
25
µPD703100-33, 703100-40, 703101-33, 703102-33
7. DMA FUNCTIONS (DMA CONTROLLER)
{ 4 independent DMA channels
{ Transfer units: 8 or 16 bits
16
{ Maximum transfer count: 65536 (2 )
{ Two types of transfer
•
Flyby (one-cycle) transfer
•
Two-cycle transfer
{ Three transfer modes
•
Single transfer mode
•
Single-step transfer mode
•
Block transfer mode
{ Transfer requests
•
DMARQ0 to DMARQ3 pin (× 4)
•
Requests from on-chip peripheral I/O (serial interface and real-time pulse unit)
•
Requests by software
{ Transfer objects
•
Memory to I/O and vice versa
•
Memory to memory and vice versa
{ DMA transfer end output signal (TC0 to TC3)
26
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 7-1. DMA Function Block Diagram
Internal RAM
Internal peripheral I/O
Internal bus
Internal peripheral I/O bus
CPU
Data control
Address control
DMA source address
register (DSAnH/DSAnL)
DMA destination address
register (DDAnH/DDAnL)
TCn
Count control
DMA byte count register
(DBCn)
DMA addressing control
register (DADCn)
DMA channel control
register (DCHCn)
NMI
INTPmn
Request from on-chip
peripheral I/O
Channel control
DMA disable status
register (DDISn)
DMA restart register
(DRSTn)
DMARQn
DMAAKn
DMA trigger source
register (DTFRn)
DMAC
Bus interface
V850E/MS1
External bus
External I/O
External RAM
External ROM
Remark m = 10 to 15, n=0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
27
µPD703100-33, 703100-40, 703101-33, 703102-33
8. INTERRUPT/EXCEPTION PROCESSING FUNCTIONS
8.1 Features
{ Interrupts
•
Non-maskable interrupt: 1 source
•
Maskable interrupt
•
8-level programmable priority control
•
Multiple interrupt control based on priority levels
•
Mask specification for each maskable interrupt request
•
Noise elimination, edge detection, and valid edge specification for external interrupt requests
: 47 sources
{ Exceptions
28
•
Software exceptions: 32 sources
•
Exception trap
: 1 source (invalid instruction code exception)
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 8-1. Interrupt Control Function Block Diagram
Internal bus
ISPR register
xxICn register
Note
INTP110
INTP111
INTP112
INTP113
Note
INTM2
(edge detection)
INTP120
INTP121
INTP122
INTP123
Note
INTM3
(edge detection)
INTP130
INTP131
INTP132
INTP133
Note
INTM4
(edge detection)
INTP140
INTP141
INTP142
INTP143
Note
INTM5
(edge detection)
INTP150
INTP151
INTP152
INTP153
Note
INTM6
(edge detection)
INTM1
(edge detection)
DMAC
CSI0
UART0
SIO
CSI1
UART1
CSI2
CSI3
INTOV10
INTOV11
INTOV12
INTOV13
INTOV14
INTOV15
INTP100/INTCC100
INTP101/INTCC101
INTP102/INTCC102
INTP103/INTCC103
INTP110/INTCC110
INTP111/INTCC111
INTP112/INTCC112
INTP113/INTCC113
INTP120/INTCC120
INTP121/INTCC121
INTP122/INTCC122
INTP123/INTCC123
INTP130/INTCC130
INTP131/INTCC131
INTP132/INTCC132
INTP133/INTCC133
INTP140/INTCC140
INTP141/INTCC141
INTP142/INTCC142
INTP143/INTCC143
INTP150/INTCC150
INTP151/INTCC151
INTP152/INTCC152
INTP153/INTCC153
INTCM40
INTCM41
INTDMA0
INTDMA1
INTDMA2
INTDMA3
INTCSI0
INTSER0
INTSR0
INTST0
INTCSI1
INTSER1
INTSR1
INTST1
INTCSI2
INTCSI3
INTAD
A/D converter
OVIF10
OVIF11
OVIF12
OVIF13
OVIF14
OVIF15
P10IF0
P10IF1
P10IF2
P10IF3
P11IF0
P11IF1
P11IF2
P11IF3
P12IF0
P12IF1
P12IF2
P12IF3
P13IF0
P13IF1
P13IF2
P13IF3
P14IF0
P14IF1
P14IF2
P14IF3
P15IF0
P15IF1
P15IF2
P15IF3
CMIF40
CMIF41
DMAIF0
DMAIF1
DMAIF2
DMAIF3
CSIF0
SEIF0
SRIF0
STIF0
CSIF1
SEIF1
SRIF1
STIF1
CSIF2
CSIF3
ADIF
Handler
address
generator
CPU
PSW
xxPRn0 to xxPRn3 (interrupt priority order specification bit)
RPU
INTP100
INTP101
INTP102
INTP103
3210
3210 3210
3210 3210
3210 3210
3210 3210
3210 3210
3210
Selector
Selector
Selector
Selector
Selector
Selector
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
xxMKn (interrupt mask flag)
ID
Interrupt request
Interrupt request
acknowledge
HALT mode
release signal
NMI
Note Noise elimination
Remark xx: OV, CM, P10 to P15, DMA, CS, SE, SR, ST, AD
n: None, or 10 to 15, 40, 41, 0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
29
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 8-1. List of Interrupts (1/3)
Interrupt/Exception Source
Type
Default
Category
Name
Reset
Interrupt
RESSET
Control
Register
–
Generation Source
RESET input
Generat-
Priority
ing Unit
Pin
–
Exception
Code
0000H
Handler
Restore
Address
PC
00000000H
Undefined
Non-
Interrupt
NMI
–
NMI input
–
TRAP instruction
Pin
–
–
–
0010H
00000010H
nextPC
Note
00000040H
nextPC
Note
00000050H
nextPC
maskable
Software
exception
Exception
Exception
Note
TRAP0n
Note
TRAP1n
–
TRAP instruction
–
–
Exception
ILGOP
–
Illegal instruction
–
–
0060H
00000060H
nextPC
005n
H
code
Interrupt
INTOV10
OVIC10
Timer 10 overflow
RPU
0
0080H
00000080H
nextPC
Interrupt
INTOV11
OVIC11
Timer 11 overflow
RPU
1
0090H
00000090H
nextPC
Interrupt
INTOV12
OVIC12
Timer 12 overflow
RPU
2
00A0H
000000A0H
nextPC
Interrupt
INTOV13
OVIC13
Timer 13 overflow
RPU
3
00B0H
000000B0H
nextPC
Interrupt
INTOV14
OVIC14
Timer 14 overflow
RPU
4
00C0H
000000C0H
nextPC
Interrupt
INTOV15
OVIC15
Timer 15 overflow
RPU
5
00D0H
000000D0H
nextPC
INTP100/
P10IC0
Pin/RPU
6
0100H
00000100H
nextPC
Pin/RPU
7
0110H
00000110H
nextPC
Pin/RPU
8
0120H
00000120H
nextPC
Pin/RPU
9
0130H
00000130H
nextPC
Pin/RPU
10
0140H
00000140H
nextPC
Pin/RPU
11
0150H
00000150H
nextPC
Pin/RPU
12
0160H
00000160H
nextPC
Pin/RPU
13
0170H
00000170H
nextPC
Pin/RPU
14
0180H
00000180H
nextPC
Pin/RPU
15
0190H
00000190H
nextPC
Pin/RPU
16
01A0H
000001A0H
nextPC
Interrupt
INTCC100
Interrupt
INTP101/
Interrupt
INTP102/
P10IC1
INTP103/
P10IC2
INTP110/
P10IC3
INTP111/
P11IC0
INTP112/
P11IC1
INTP113/
P11IC2
INTP120/
P11IC3
INTP121/
P12IC0
INTP122/
INTCC122
Match between
INTP120 and CC120
P12IC1
INTCC121
Interrupt
Match between
INTP113 and CC113
INTCC120
Interrupt
Match between
INTP112 and CC112
INTCC113
Interrupt
Match between
INTP111 and CC111
INTCC112
Interrupt
Match between
INTP110 and CC110
INTCC111
Interrupt
Match between
INTP103 and CC103
INTCC110
Interrupt
Match between
INTP102 and CC102
INTCC103
Interrupt
Match between
INTP101 and CC101
INTCC102
Interrupt
Match between
INTP100 and CC100
INTCC101
Match between
INTP121 and CC121
P12IC2
Match between
INTP122 and CC122
Note n = 0 to FH
30
H
Exception
trap
Maskable
004n
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 8-1. List of Interrupts (2/3)
Interrupt/Exception Source
Type
Default
Category
Name
Maskable
Interrupt
INTP123/
Control
Register
P12IC3
INTCC123
Interrupt
INTP130/
INTP131/
P13IC0
INTP132/
P13IC1
INTP133/
P13IC2
INTP140/
P13IC3
INTP141/
P14IC0
INTP142/
P14IC1
INTP143/
P14IC2
INTP150/
P14IC3
INTP151/
P15IC0
INTP152/
P15IC1
INTP153/
Match between
Pin/RPU
18
01C0H
000001C0H
nextPC
Match between
Pin/RPU
19
01D0H
000001D0H
nextPC
Match between
Pin/RPU
20
01E0H
000001E0H
nextPC
Match between
Pin/RPU
21
01F0H
000001F0H
nextPC
Match between
Pin/RPU
22
0200H
00000200H
nextPC
Match between
Pin/RPU
23
0210H
00000210H
nextPC
Match between
Pin/RPU
24
0220H
00000220H
nextPC
Match between
Pin/RPU
25
0230H
00000230H
nextPC
Match between
Pin/RPU
26
0240H
00000240H
nextPC
Match between
Pin/RPU
27
0250H
00000250H
nextPC
Pin/RPU
28
0260H
00000260H
nextPC
Pin/RPU
29
0270H
00000270H
nextPC
INTP151 and CC151
P15IC2
INTCC152
Interrupt
nextPC
INTP150 and CC150
INTCC151
Interrupt
000001B0H
INTP143 and CC143
INTCC150
Interrupt
01B0H
INTP142 and CC142
INTCC143
Interrupt
17
INTP141 and CC141
INTCC142
Interrupt
Pin/RPU
INTP140 and CC140
INTCC141
Interrupt
PC
INTP133 and CC133
INTCC140
Interrupt
Restore
Address
INTP132 and CC132
INTCC133
Interrupt
Code
Handler
INTP131 and CC131
INTCC132
Interrupt
ing Unit
tion
INTP130 and CC130
INTCC131
Interrupt
Match between
Priority
Excep-
INTP123 and CC123
INTCC130
Interrupt
Generation Source
Generat-
Match between
INTP152 and CC152
P15IC3
INTC153
Match between
INTP153 and CC153
Interrupt
INTCM40
CMIC40
CM40 match signal
RPU
30
0280H
00000280H
nextPC
Interrupt
INTCM41
CMIC41
CM41 match signal
RPU
31
0290H
00000290H
nextPC
Interrupt
INTDMA0
DMAIC0
DMAC
32
02A0H
000002A0H
nextPC
DMAC
33
02B0H
000002B0H
nextPC
DMAC
34
02C0H
000002C0H
nextPC
DMAC
35
02D0H
000002D0H
nextPC
SIO
36
0300H
000000300H
nextPC
SIO
37
0310H
000000310H
nextPC
DMA channel 0
transfer completion
Interrupt
INTDMA1
DMAIC1
DMA channel 1
transfer completion
Interrupt
INTDMA2
DMAIC2
DMA channel 2
transfer completion
Interrupt
INTDMA3
DMAIC3
DMA channel 3
transfer completion
Interrupt
INTCSI0
CSIC0
CSI0 send/receive
completion
Interrupt
INTSER0
SEIC0
UART0 receive error
Note n = 0 to FH
Preliminary Data Sheet U13995EJ1V0DS00
31
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 8-1. List of Interrupts (3/3)
Interrupt/Exception Source
Type
Default
Category
Name
Maskable
Interrupt
INTSR0
Control
Register
SRIC0
Generation Source
UART0 receive
Generat-
Priority
ing Unit
Exception
Code
Handler
Restore
Address
PC
SIO
38
0320H
00000320H
nextPC
SIO
39
0330H
00000330H
nextPC
SIO
40
0340H
00000340H
nextPC
UART1 receive error
SIO
41
0350H
00000350H
nextPC
UART1 receive
SIO
42
0360H
00000360H
nextPC
SIO
43
0370H
00000370H
nextPC
SIO
44
0380H
00000380H
nextPC
SIO
45
03C0H
000003C0H
nextPC
ADC
46
0400H
00000400H
nextPC
completion
Interrupt
INTST0
STIC0
UART0 send
completion
Interrupt
INTCSI1
CSIC1
CSI1 send/receive
completion
Interrupt
INTSER1
SEIC1
Interrupt
INTSR1
SRIC1
completion
Interrupt
INTST1
STIC1
UART1 send
completion
Interrupt
INTCSI2
CSIC2
CSI2 send/receive
completion
Interrupt
INTCSI3
CSIC3
CSI3 send/receive
completion
Interrupt
INTAD
ADIC
A/D conversion
completion
Remarks 1. Default priority: Priority that takes precedence when two or more maskable interrupt requests having
the same priority level are generated at the same time. The highest priority is 0.
Restore PC: The PC value that is saved in EIPC or FEPC when the interrupt or exception
processing is started. However, the restore PC value that is saved when an interrupt is
acknowledged during the execution of a division instruction (DIV, DIVH, DIVU, or
DIVHU), is the PC value of the current instruction (DIV, DIVH, DIVU, or DIVHU).
2. The execution address of the illegal instruction when an illegal opcode exception occurs is obtained
according to the calculation “restore PC - 4.”
32
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
9. CLOCK GENERATION FUNCTIONS
{ Multiplier function using a PLL (Phase locked loop) synthesizer
{ Clock sources
•
Oscillation by connecting an oscillator: fXX = φ/5
•
External clock: fXX = 2 × φ or φ/5
{ Power saving modes
•
HALT mode
•
IDLE mode
•
Software STOP mode
•
Clock output inhibit mode
{ Internal system clock output function
Figure 9-1. Block Diagram of Clock Generation Function
X1
(fXX)
X2
φ
Clock generator
(CG)
CKSEL
CPU, on-chip peripheral I/O
CLKOUT
Time base counter (TBC)
Remark φ : internal system clock frequency
FXX: external oscillator or external clock frequency
Preliminary Data Sheet U13995EJ1V0DS00
33
µPD703100-33, 703100-40, 703101-33, 703102-33
10. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)
{ Measures the pulse interval and frequency, and outputs a programmable pulse
•
16-bit measurements are possible
•
Can generate a variety of pulse patterns (interval pulse, one-shot pulse)
{ Timer 1
•
16-bit timer/event counter
•
Count clock sources: 2 types (division of internal system clock, and external pulse input)
•
Capture/compare common registers: 24
•
Count clear pins: TCLR10 to TCLR15
•
Interrupt sources: 30 types
•
External pulse outputs: 12
{ Timer 4
34
•
16-bit interval timer
•
Count clock can select division for internal system clock
•
Compare registers: 2
•
Interrupt sources: 2
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 10-1. Block Diagram of Timer 1 (16-bit Timer/Event Counter)
Internal system
clock ( φ )
TM10
TCLR10
Edge detection
PRS100, ETI10
PRS101
1/8
1/16
INTP100
INTP101
INTP102
Noise
elimination
Edge
detection
(INTM1)
INTP103
Note 1
OVF10
INTOV10
TM10 (16 bits)
ALV101 ALV100
CC100
CC101
S
Q
RNote 3 Q
CC102
S
Q
RNote 3 Q
CC103
Selector
1/4
Note 2
Clear and
count control
Clear and
start
Selector
1/4
Edge detection
φm
Selector
1/2
Selector
TI10
Selector
PRM
101
TO100
TO101
IMS100 IMS101 IMS102 IMS103
Selector
Selector
Selector
Selector
TM11
INTOV11
TO110
TO111
INTP110/INTCC110
INTP111/INTCC111
INTP112/INTCC112
INTP113/INTCC113
···
TCLR11
TI11
INTP110
INTP111
INTP112
INTP113
INTP100/INTCC100
INTP101/INTCC101
INTP102/INTCC102
INTP103/INTCC103
TCLR15
TI15
INTP150
INTP151
INTP152
INTP153
TM15
INTOV15
TO150
TO151
INTP150/INTCC150
INTP151/INTCC151
INTP152/INTCC152
INTP153/INTCC153
Notes 1. Internal count clock
2. External count clock
3. Reset priority
Preliminary Data Sheet U13995EJ1V0DS00
35
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 10-2. Block Diagram of Timer 4 (16-bit Interval Timer)
Internal system
clock
(φ )
TM40
1/4
1/8
PRS400
1/16
φm
1/32
Selector
1/2
Selector
PRM400, PRM401
Internal count
clock
TM40 (16 bits)
Clear and
start
CM40
INTCM40
TM41
INTCM41
36
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
11. SERIAL INTERFACE FUNCTION
The serial interface function provides two 6-channel serial interfaces.
Up to four channels can be used at the same time.
(1) Asynchronous serial interface (UART0 and UART1): 2 channels
(2) Clocked serial interface (CSI0 to CSI3): 4 channels
Caution UART0 and CSI0 share a pin, as do UART1 and CSI1. One or the other of each pair can be
selected via a register (ASIM00, ASIM10).
11.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
{ Transfer rate
150 bps to 76800 bps (using the dedicated baud rate generator when the internal system clock is
33 MHz)
Maximum 4.125 Mbps (using the φ/2 clock when the internal system clock is 33 MHz)
{ Full duplex communications
On-chip receive buffer (RXBn)
{ 2-pin configuration
TXDn : Transmit data output pin
RXDn: Receive data input pin
{ Receive error detection functions
•
Parity error
•
Framing error
•
Overrun error
{ Interrupt sources: 3 types
•
Receive error interrupt (INTSERn)
•
Receive completion interrupt (INTSRn)
•
Transmission completion interrupt (INTSTn)
{ The character length of transmission/reception data is specified by the ASIMn0 and ASIMn1 registers.
{ Character length
7, 8 bits
9 bits (when adding an expansion bit)
{ Parity function: odd, even, 0, none
{ Transmission stop bit: 1, 2 bits
{ On-chip dedicated baud rate generator
{ Serial clock (SCKn) output function
Remark n = 0, 1
Preliminary Data Sheet U13995EJ1V0DS00
37
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 11-1. Block Diagram of Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
UART0
RXE0
RXB0/RXB0L
Receive shift
register
RXD0
Receive buffer
TXS0/TXS0L
Transmit shift
register
TXD0
Transmit
control
parity addition
INTST0
Receive
control
parity check
INTSER0
SCLS01, SCLS00
1/16
1/16
1/2
Selector
SCK0
INTSR0
Internal system
clock (φ )
BRG0
INTST1
RXD1
INTSER1
TXD1
UART1
SCK1
INTSR1
BRG1
11.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)
{ High-speed transfer
Maximum 10 Mbps (when the internal system clock is operating at 40 MHz) ... µPD703100-40
Maximum 8.25 Mbps (when the internal system clock is operating at 33 MHz) ... µPD703100-33, µPD703101-33,
µPD703102-33
{ Half-duplex communications
{ Character length: 8 bits
{ Can switch between MSB first or LSB first for data
{ Either external serial clock input or internal serial clock output can be selected
{ 3-wire type
SOn:
Serial data output
SIn:
Serial data input
SCKn: Serial clock input/output
{ Interrupt source: 1 type
•
Transmission/reception completion interrupt (INTCSIn)
Remark n = 0 to 3
38
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 11-2. Block Diagram of Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)
CSI0
CTXE0
Internal system
clock (φ )
SO0
CRXE0
SI0
SO latch
Serial I/O shift register
(SIO0)
D
CLS00, CLS01
Q
SCK0
Selector
1/2
Serial clock control
circuit
Serial clock counter
Interrupt
control circuit
1/4
BRG0
INTCSI0
1/2
SO1
1/4
SI1
CSI1
SCK1
BRG1
INTCSI1
1/2
SO2
1/4
SI2
CSI2
SCK2
BRG2
INTCSI2
1/2
SO3
1/4
SI3
CSI3
SCK3
INTCSI3
Preliminary Data Sheet U13995EJ1V0DS00
39
µPD703100-33, 703100-40, 703101-33, 703102-33
11.3 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)
{ Serial clock can be selected via either dedicated baud rate generator output or internal system clock (φ)
{ Identical baud rates during transmission and reception
Figure 11-3. Block Diagram of Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)
BRG0
BRGC0
CSI0
BRCE0
Match
UART0
BPR00 to BPR02
Internal system
clock (φ )
Clear
TMBRG0
Prescaler
CSI1
BRG1
UART1
CSI2
BRG2
CSI3
40
Preliminary Data Sheet U13995EJ1V0DS00
1/2
µPD703100-33, 703100-40, 703101-33, 703102-33
12. A/D CONVERTER
{ Analog input: 8 channels
{ On-chip 10-bit A/D converter
{ On-chip A/D conversion result registers (ADCR0 to ADCR7)
10 bits × 8
{ A/D conversion trigger modes
A/D trigger mode
Timer trigger mode
External trigger mode
{ Successive approximation method
Figure 12-1. A/D Converter Block Diagram
Series resistor string
ANI0
Sample & hold circuit
Input circuit
Tap selector
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
Voltage comparator
ANI7
9
R/2
AVREF
R
R/2
AVSS
AVDD
0
SAR (10)
10
10
INTAD
9
0
ADCR0
INTCC110
INTCC111
INTCC112
INTCC113
ADCR1
Controller
ADCR2
ADCR3
ADTRG
Noise
Edge
elimination detection
ADCR4
ADCR5
7
0
7
0
ADM0 (8)
ADM1 (8)
8
8
ADCR6
ADCR7
10
Internal bus
Preliminary Data Sheet U13995EJ1V0DS00
41
µPD703100-33, 703100-40, 703101-33, 703102-33
13. PORT FUNCTIONS
{ Number of ports
Dedicated input ports: 9
Input/output ports
: 114
{ Shares pins with other peripheral function I/O
{ Input and output can be specified in 1-bit units
The block diagrams of the various ports are divided into 16 block types identified by A to P as shown in Table 131. Figures 13-1 to 13-16 show the block diagrams of each type.
Table 13-1. List of Port Block Types
Port Name
Pin Name
Port Function
Port 0
P00 to P07
8-bit input/output
Input/output of real-time pulse unit (RPU), external
interrupt input, DMA controller (DMAC) input
A, B, M
Port 1
P10 to P17
8-bit input/output
Input/output of real-time pulse unit (RPU), external
interrupt input, DMA controller (DMAC) output
A, B, K
Port 2
P20 to P27
1-bit input,
7-bit input/output
NMI input, serial interface (UART0/CSI0, UART1/CSI1)
input/output
A, C, D, I, J
Port 3
P30 to P37
8-bit input/output
Input/output of real-time pulse unit (RPU), external
interrupt input, serial interface (CSI2) input/output
A, B, K, M,
N
Port 4
P40 to P47
8-bit input/output
External data bus (D0 to D7)
E
Port 5
P50 to P57
8-bit input/output
External data bus (D8 to D15)
E
Port 6
P60 to P67
8-bit input/output
External address bus (A16 to A23)
F
Port 7
P70 to P77
8-bit input/output
A/D converter (ADC) analog input
G
Port 8
P80 to P87
8-bit input/output
External bus interface control signal output
O, P
Port 9
P90 to P97
8-bit input/output
External bus interface control signal input/output
H, O
Port 10
P100 to
P107
8-bit input/output
Input/output of real-time pulse unit (RPU), external
interrupt input, DMA controller (DMAC) output
A, B, K
Port 11
P110 to
P117
8-bit input/output
Input/output of real-time pulse unit (RPU), external
interrupt input, serial interface (CSI3) input/output
A, B, K, M,
N
Port 12
P120 to
P127
8-bit input/output
Input/output of real-time pulse unit (RPU), external
interrupt input, A/D converter (ADC) external trigger input
A, B
Port A
PA0 to PA7
8-bit input/output
External address bus (A0 to A7)
F
Port B
PB0 to PB7
8-bit input/output
External address bus (A8 to A15)
F
Port X
PX5 to PX7
3-bit input/output
Refresh request signal output, wait insertion signal input,
internal system clock output
A, L
42
Function in Control Mode
Preliminary Data Sheet U13995EJ1V0DS00
Block Type
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-1. Block Diagram of Type A
WRPMC
PMCmn
WRPM
WRPORT
Output signal
in control mode
Selector
Internal bus
PMmn
Pmn
RDIN
Selector
Selector
Pmn
Address
Remark m: port number
n : bit number
Figure 13-2. Block Diagram of Type B
WRPMC
PMCmn
WRPM
WRPORT
Pmn
Selector
Pmn
Selector
Internal bus
PMmn
Address
RDIN
Input signal in
control mode
Noise elimination
Edge detection
Remark m: port number
n : bit number
Preliminary Data Sheet U13995EJ1V0DS00
43
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-3. Block Diagram of Type C
WRPMC
SCKx output
enable signal
PMCmn
WRPM
Output signal in
control mode
Selector
Pmn
Pmn
Selector
WRPORT
Selector
Internal bus
PMmn
Address
RDIN
Input signal in
control mode
Remark mn: 24, 27
x : 0 (when mn = 24), 1 (when mn = 27)
Figure 13-4. Block Diagram of Type D
WRPMC
PMCmn
WRPM
WRPORT
Pmn
Selector
Pmn
Selector
Internal bus
PMmn
Address
RDIN
Input signal in
control mode
Remark m: port number
n : bit number
44
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-5. Block Diagram of Type E
MODE0 to MODE3
MM0 to MM3
I/O control circuit
WRPM
Output signal in
control mode
Selector
Pmn
Pmn
Selector
WRPORT
Selector
Internal bus
PMmn
Address
RDIN
Input signal in
control mode
Remark m: port number
n : bit number
Figure 13-6. Block Diagram of Type F
MODE0 to MODE3
MM0 to MM3
I/O control circuit
WRPM
Output signal in
control mode
Selector
Pmn
Pmn
Selector
WRPORT
Selector
Internal bus
PMmn
Address
RDIN
Remark m: port number
n : bit number
Preliminary Data Sheet U13995EJ1V0DS00
45
µPD703100-33, 703100-40, 703101-33, 703102-33
Internal bus
Figure 13-7. Block Diagram of Type G
P7n
RDIN
Input signal in
control mode
ANIn
Sample & hold circuit
Remark n = 0 to 7
Figure 13-8. Block Diagram of Type H
MODE0 to MODE3
MM0 to MM3
I/O control circuit
WRPM
WRPORT
Pmn
Selector
P97
Selector
Internal bus
PMmn
Address
RDIN
46
Input signal in
control mode
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
1
Selector
Internal bus
Figure 13-9. Block Diagram of Type I
Noise elimination
P20
Address
RDIN
NMI
Edge detection
Figure 13-10. Block Diagram of Type J
WRPM
WRPORT
Pmn
RDIN
Selector
Pmn
Selector
Internal bus
PMmn
Address
Remark m: port number
n : bit number
Preliminary Data Sheet U13995EJ1V0DS00
47
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-11. Block Diagram of Type K
WRPCS
PCSmn
WRPMC
PMCmn
Internal bus
WRPM
PMmn
Output signal in
control mode
Selector
Selector
Pmn
Pmn
Selector
WRPORT
Address
RDIN
Input signal in
control mode
Noise elimination
Edge detection
Remark m: port number
n : bit number
48
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-12. Block Diagram of Type L
WRPMC
PMCmn
WRPM
WRPORT
Pmn
Selector
Pmn
Selector
Internal bus
PMmn
Address
RDIN
Input signal in
control mode
Remark m: port number
n : bit number
Preliminary Data Sheet U13995EJ1V0DS00
49
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-13. Block Diagram of Type M
WRPCS
PCSmnNote
WRPMC
PMCmn
Internal bus
WRPM
PMmn
WRPORT
Pmn
Selector
Selector
Pmn
Address
RDIN
INTP100 to INTP103,
INTP132, INTP142
Noise elimination
Edge detection
DMARQ0 to DMARQ3,
SI2, SI3
Note When mn = 36:
PCS35
When mn = 116: PCS115
Remark mn: 04 to 07, 36, 116
50
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-14. Block Diagram of Type N
WRPCS
PCSm5
SCKx output
enable signal
WRPMC
PMCmn
Internal bus
WRPM
Output signal in
control mode
Selector
Pmn
Pmn
Selector
WRPORT
Selector
PMmn
Address
RDIN
INTP133, INTP143
Noise elimination
Edge detection
SCK2, SCK3
Remark mn: 37, 117
x: 2 (when mn = 37), 3 (when mn = 117)
Preliminary Data Sheet U13995EJ1V0DS00
51
µPD703100-33, 703100-40, 703101-33, 703102-33
Figure 13-15. Block Diagram of Type O
MODE0 to MODE3
WRPMC
MM0 to MM3
PMCmn
I/O control circuit
WRPM
Output signal in
control mode
Selector
Pmn
Pmn
Selector
WRPORT
Selector
Internal bus
PMmn
Address
RDIN
Remark m: port number
n : bit number
Figure 13-16. Block Diagram of Type P
WRPCS
PCSmn
MODE0 to MODE3
MM0 to MM3
WRPMC
PMCmn
I/O control circuit
Internal bus
WRPM
Selector
Pmn
Pmn
Selector
Output signal in
control mode
Selector
WRPORT
Selector
PMmn
Address
RDIN
Remark m: port number
n : bit number
52
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
14. RESET FUNCTION
When low-level signal is input to the RESET pin, a system reset is performed and the various on-chip hardware
devices are initialized.
When the RESET input changes from low to high, the reset state is canceled and the CPU begins program
execution. (the contents of the various registers should be initialized within the program as necessary.)
An on-chip noise elimination circuit, which uses analog delay ( = 60 ns) to eliminate noise, is provided for the
RESET pin.
Preliminary Data Sheet U13995EJ1V0DS00
53
µPD703100-33, 703100-40, 703101-33, 703102-33
15. INSTRUCTION SET
Table 15-1. Symbols Used to Describe Operands
Symbol
Description
reg1
General registers (r0 to r31): used as source registers
reg2
General registers (r0 to r31): used mainly as destination registers
reg3
General registers (r0 to r31): used mainly to store the remainders of division results and the higher 3 bits
of multiplication results
imm×
×-bit immediate
disp×
×-bit displacement
regID
System register number
bit#3
3-bit data for specifying the bit number
ep
Element pointer (r30)
cccc
4-bit data indicating the condition code
vector
5-bit data used for specifying the trap vector (00H to 1FH)
list×
List of × registers
Table 15-2. Symbols Used to Describe Opcodes
Symbol
Description
R
1-bit data of code specifying reg1 or regID
r
1-bit data of code specifying reg2
w
1-bit data of code specifying reg3
d
1-bit displacement data
i
1-bit immediate data
cccc
4-bit data indicating condition code
bbb
3-bit data for specifying bit number
L
1-bit data specifying register list
54
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 15-3. Symbols Used in Operation
Symbol
Description
←
Input for
GR [ ]
General register
SR [ ]
System register
zero-extend (n)
Extend n with zeros until word length
sign-extend (n)
Extend n with signs until word length
load-memory (a, b)
Read data of size b from address a
store-memory (a, b, c)
Write data b of address a by size c
load-memory-bit (a, b)
Read bit b of address a
store-memory-bit (a, b, c)
Write c to bit b of address a
saturated (n)
Execute saturation processing of n (n is a two’s complement)
If, as a result of the calculation,
n ≥ 7FFFFFFFH, let it be 7FFFFFFFH.
n ≤ 80000000H, let it be 80000000H
result
Reflect the result in a flag
Byte
Byte (8 bits)
Half-word
Half word (16 bits)
Word
Word (32 bits)
+
Add
−
Subtract
||
Bit concatenation
×
Multiply
÷
Divide
%
Remainder of division result
AND
Logical AND
OR
Logical OR
XOR
Exclusive OR
NOT
Logical NOT
logically shift left by
Logical shift left
logically shift right by
Logical shift right
arithmetically shift right by
Arithmetic shift right
Table 15-4. Symbols Used for Execution Clock
Symbol
Description
i : issue
When executing another instruction immediately after executing an instruction
r : repeat
When repeating the same instruction immediately after executing the instruction
l : latency
When referring to instruction execution results in the next instruction
Preliminary Data Sheet U13995EJ1V0DS00
55
µPD703100-33, 703100-40, 703101-33, 703102-33
Table 15-5. Symbols Used in Flag Operations
Identifier
Description
(Blank)
No change
0
Clear to 0
×
Set or cleared according to the results
R
Previously saved values are restored
Table 15-6. Condition Codes
Condition
Name (cond)
Condition Code
(cccc)
Condition Formula
Description
V
0000
OV = 1
Overflow
NV
1000
OV = 0
No overflow
C/L
0001
CY = 1
Carry
Lower (Less than)
NC/NL
1001
CY = 0
No carry
Not lower (Greater than or equal)
Z/E
0010
Z=1
Zero
Equal
NZ/NE
1010
Z=0
Not zero
Not equal
NH
0011
(CY or Z) = 1
Not higher (Less than or equal)
H
1011
(CY or Z) = 0
Higher (Greater than)
N
0100
S=1
Negative
P
1100
S=0
Positive
T
0101
SA
1101
SAT = 1
Saturated
LT
0110
(S xor OV) = 1
Less than signed
GE
1110
(S xor OV) = 0
Greater than or equal signed
LE
0111
((S xor OV) or Z) = 1
Less than or equal signed
GT
1111
((S xor OV) or Z) = 0
Greater than signed
56
–
Preliminary Data Sheet U13995EJ1V0DS00
Always (unconditional)
µPD703100-33, 703100-40, 703101-33, 703102-33
Instruction Set
(1/7)
Execution
Mnemonic
ADD
ADDI
Operand
Opcode
Flags
Clock
Operation
i
r
l
CY
OV
S
Z
reg1,reg2
rr r r r 0 0 1 1 1 0 R R R R R GR[reg2]←GR[reg2]+GR[reg1]
1
1
1
×
×
×
×
imm5,reg2
rr r r r 0 1 0 0 1 0 i i i i i GR[reg2]←GR[reg2]+sign-extend(imm5)
1
1
1
×
×
×
×
imm16,reg1,reg2
r r r r r 1 1 0 0 0 0 r r r r r GR[reg2]←GR[reg1]+sign-extend(imm16)
1
1
1
×
×
×
×
SAT
i i ii i i i i i i i i i i i i
AND
reg1,reg2
rr r r r 0 0 1 0 1 0 R R R R R GR[reg2]←GR[reg2]AND GR[reg1]
1
1
1
0
×
×
ANDI
imm16,reg1,reg2
rr r r r 1 1 0 1 1 0 R R R R R GR[reg2]←GR[reg1]AND zero-
1
1
1
0
0
×
2
2
2
i i i i i i i i i i i i i i i i extend(imm16)
Bcond
disp9
dd d d d 1 0 1 1 d d d c c c c if conditions are satisfied
Note 1 then PC ← PC+signextend(disp9)
When
conditions are
Note 2 Note 2 Note 2
satisfied
When
1
1
1
1
1
1
×
0
×
×
1
1
1
×
0
×
×
4
4
4
3
3
3
conditions are
not satisfied
BSH
reg2,reg3
rr r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3]←GR[reg2] (23 : 16) II GR[reg2]
ww w w w 0 1 1 0 1 0 0 0 0 1 0 (31 : 24) II GR[reg2] (7 : 0) II GR[reg2] (15 : 8)
BSW
reg2,reg3
rr r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3]←GR[reg2] (7 : 0) II GR[reg2] (15 : 8) II
ww w w w 0 1 1 0 1 0 0 0 0 0 0 GR[reg2] (23 : 16) II GR[reg2] (31 : 24)
CALLT
imm6
0 0 0 0 0 0 1 0 0 0 i i i i i i CTPC←PC+2(return PC)
CTPSW←PSW
adr←CTBP+zero-extend(imm6 logically
shift left by 1)
PC←CTBP+zero-extend(Loadmemory(adr, Half-word))
CLR1
bit#3,
1 0 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
disp 16[reg1]
dd d d d d d d d d d d d d d d Z flags←Not(Load-memory-bit(adr,bit#3))
×
Note 3 Note 3 Note 3
Store-memory-bit (adr,bit#3,0)
reg2,[reg1]
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 Z flags←Not(Load-memory-bit(adr,reg2))
3
3
×
3
Note 3 Note 3 Note 3
Store-memory-bit (adr,reg2,0)
CMOV
cccc,imm5,reg2,
rr r r r 1 1 1 1 1 1 i i i i i if condition are satisfied then
reg3
ww w w w 0 1 1 0 0 0 c c c c 0 GR[reg3]←sign-extended(imm5)
1
1
1
1
1
1
else GR[reg3]←GR[reg2]
cccc,reg1,reg2,
rr r r r 1 1 1 1 1 1 R R R R R if conditions are satisfied
reg3
ww w w w 0 1 1 0 0 1 c c c c 0 then GR[reg3]←GR[reg1]
else GR[reg3]←GR[reg2]
CMP
CTRET
reg1,reg2
rr r r r 0 0 1 1 1 1 R R R R R result←GR[reg2]−GR[reg1]
1
1
1
×
×
×
×
imm5,reg2
rr r r r 0 1 0 0 1 1 i i i i i result←GR[reg2]−sign-extend(imm5)
1
1
1
×
×
×
×
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PC←CTPC
3
3
3
R
R
R
R
1
1
1
R
0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 PSW←CTPSW
DI
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID←1
00 0 0 0 0 0 1 0 1 1 0 0 0 0 0
Preliminary Data Sheet U13995EJ1V0DS00
57
µPD703100-33, 703100-40, 703101-33, 703102-33
(2/7)
Execution
Mnemonic
Operand
Opcode
i
DISPOSE
imm5,list12
Flags
Clock
Operation
r
l
CY
OV
S
Z
0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left N+1 N+1 N+1
Note 4 Note 4 Note 4
LL L L L L L L L L L 0 0 0 0 0 by 2)
GR[reg in list12]←Load-memory(sp,Word)
sp←sp+4
repeat 2 steps above untill all regs in list12
is loaded
imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shif left
N+3 N+3 N+3
Note 4 Note 4 Note 4
LL L L L L L L L L L R R R R R by 2)
Note 5 GR[reg in list12]←Load-memory(sp,Word)
sp←sp+4
repeat 2 steps above until all regs in list 12
is loaded
PC←GR[reg1]
DIV
reg1,reg2,reg3
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1]
35
35
35
r r r r r 0 0 0 0 1 0 R R R R R GR[reg2]←GR[reg2]÷GR[reg1] Note 6
35
35
35
×
×
×
Note 6
35
35
35
×
×
×
34
34
34
×
×
×
34
34
34
×
×
×
1
1
1
1
1
1
1
1
1
×
0
×
2
2
2
w w w w w 0 1 0 1 1 0 0 0 0 0 0 GR[reg3]←GR[reg2]%GR[reg1]
DIVH
reg1,reg2
reg1,reg2,reg3
r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1]
w w w w w 0 1 0 1 0 0 0 0 0 0 0 GR[reg3]←GR[reg2]%GR[reg1]
DIVHU
reg1,reg2,reg3
r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1] Note 6
w w w w w 0 1 0 1 0 0 0 0 0 1 0 GR[reg3]←GR[reg2]%GR[reg1]
DIVU
reg1,reg2,reg3
r r r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]÷GR[reg1]
w w w w w 0 1 0 1 1 0 0 0 0 1 0 GR[reg3]←GR[reg2]%GR[reg1]
EI
1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID←0
00 0 0 0 0 0 1 0 1 1 0 0 0 0 0
HALT
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 Stop
00 0 0 0 0 0 1 0 0 1 0 0 0 0 0
HSW
reg2,reg3
rr r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3]←GR[reg2] (15 : 0) II GR[reg2]
w w w w w 0 1 1 0 1 0 0 0 1 00
JARL
disp22,reg2
(31: 6)
rr r r r 1 1 1 1 0 d d d d d d GR[reg2]←PC+4
dd d d d d d d d d d d d d d 0 PC←PC+sign–extend(disp22)
Note 7
JMP
[reg1]
0 0 0 0 0 0 0 0 0 1 1 R R R R R PC←GR[reg1]
3
3
3
JR
disp22
0 0 0 0 0 1 1 1 1 0 d d d d d d PC←PC+sign-extend(disp22)
2
2
2
1
1
dd d d d d d d d d d d d d d 0
Note 7
LD.B
disp16[reg1],reg2
rr r r r 1 1 1 0 0 0 R R R R R adr←GR[reg1]+signe-extend(disp16)
dd d d d d d d d d d d d d d d GR[reg2]←sign-extend(Load-memory
(adr,Byte))
58
Preliminary Data Sheet U13995EJ1V0DS00
n
Note 9
×
SAT
µPD703100-33, 703100-40, 703101-33, 703102-33
(3/7)
Execution
Mnemonic
LD.BU
Operand
disp16[reg1],reg2
Opcode
Flags
Clock
Operation
rr r r r 1 1 1 1 0 b R R R R R adr←GR[reg1]+sign-extend(disp16)
i
r
1
1
l
CY
OV
S
Z
SAT
×
×
×
×
×
n
Note 11
dd d d d d d d d d d d d d d 1 GR[reg2]←zero-extend(Load-memory
Notes 8, 10 (adr,Byte))
LD.H
disp16[reg1],reg2
rr r r r 1 1 1 0 0 1 R R R R R adr←GR[reg1]+sign-extend(disp16)
1
1
n
Note 9
dd d d d d d d d d d d d d d 0 GR[reg2]←sign-extend(Load-memory
Note 8 (adr,Half-word))
LD.HU
disp16[reg1],reg2
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]+sign-extend(disp16)
1
1
n
Note 11
dd d d d d d d d d d d d d d 1 GR[reg2]←zero-extend(Load-memory
Note 8 (adr,Half-word))
LD.W
disp16[reg1],reg2
rr r r r 1 1 1 0 0 1 R R R R R adr←GR[reg1]+signe-extend(disp16)
1
1
LDSR
reg2,regID
Other than
regID=PSW
rr r r r 1 1 1 1 1 1 R R R R R SR[regID]←GR[reg2]
00 0 0 0 0 0 0 0 0 1 0 0 0 0 0
Note 12
MOV
n
Note 9
dd d d d d d d d d d d d d d 1 GR[reg2]←Load-memory(adr,Word)
1
1
1
regID=PSW
reg1,reg2
rr r r r 0 0 0 0 0 0 R R R R R GR[reg2]←GR[reg1]
1
1
1
imm5,reg2
rr r r r 0 1 0 0 0 0 i i i i i GR[reg2]←sign-extend(imm5)
1
1
1
imm32,reg1
0 0 0 0 0 1 1 0 0 0 1 R R R R R GR[reg1]←imm32
2
2
2
1
1
1
1
1
1
2
2
ii i i i i i i i i i i i i i i
ii i i i i i i i i i i i i i i
MOVEA
imm16,reg1,reg2
rr r r r 1 1 0 0 0 1 R R R R R GR[reg2]←GR[reg1]+ sign-extend(imm16)
ii i i i i i i i i i i i i i i
MOVHI
imm16,reg1,reg2
rr r r r 1 1 0 0 1 0 R R R R R GR[reg2]←GR[reg1]+(imm16 II 016)
ii i i i i i i i i i i i i i i
MUL
reg1,reg2,reg3
rr r r r 1 1 1 1 1 1 R R R R R GR[reg3] II GR[reg2]←GR[reg2] × GR[reg1]
1
Note 14
ww w w w 0 1 0 0 0 1 0 0 0 0 0
imm9,reg2,reg3
rr r r r 1 1 1 1 1 1 i i i i i GR[reg3] II GR[reg2]←GR[reg2] × sign-
1
2
2
Note 14
w w w w w 0 1 0 0 1 1 1 1 1 0 0 extend(imm9)
Note 13
MULH
reg1,reg2
imm5,reg2
MULHI
imm16,reg1,reg2
Note 6
rr r r r 0 0 0 1 1 1 R R R R R GR[reg2]←GR[reg2]
Note 6
rr r r r 0 1 0 1 1 1 i i i i i GR[reg2]←GR[reg2]
Note 6
× sign-extend (imm5)
Note 6
rr r r r 1 1 0 1 1 R R R R R R GR[reg2]←GR[reg1]
× GR[reg1]
× imm16
1
1
2
1
1
2
1
1
2
ii i i i i i i i i i i i i i i
Preliminary Data Sheet U13995EJ1V0DS00
59
µPD703100-33, 703100-40, 703101-33, 703102-33
(4/7)
Execution
Mnemonic
Operand
Opcode
i
MULU
reg1,reg2,reg3
rr r r r 1 1 1 1 1 1 R R R R R GR[reg3] II GR[reg2]←GR[reg2] × GR[reg1]
1
r r r r r 1 1 1 1 1 1 i i i i i GR[reg3] II GR[reg2]←GR[reg2] × zero-
1
l
2
2
CY
OV
S
Z
0
×
×
SAT
2
2
Note 14
ww w w w 0 1 0 0 1 1 1 1 1 1 0 extend(imm9)
NOP
r
Note 14
w w w w w 0 1 0 0 0 1 0 0 0 10
imm9,reg2,reg3
Flags
Clock
Operation
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Pass at least one clock cycle doing nothing
1
1
1
rr r r r 0 0 0 0 0 1 R R R R R GR[reg2]←NOT(GR[reg1])
1
1
1
3
3
3
NOT
reg1,reg2
NOT1
bit#3,disp16[reg1] 0 1 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d d Z flag←Not(Load-memory-bit(adr,bit#3))
×
Note 3 Note 3 Note 3
Store-memory-bit(adr,bit#3,Z flag)
reg2,[reg1]
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
3
0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 Z flag←Not(Load-memory-bit(adr,reg2))
3
×
3
Note 3 Note 3 Note 3
Store-memory-bit(adr,reg2,Z flag)
OR
reg1,reg2
rr r r r 0 0 1 0 0 0 R R R R R GR[reg2]←GR[reg2] OR GR[reg1]
1
1
1
0
×
×
ORI
imm16,reg1,reg2
rr r r r 1 1 0 1 0 0 R R R R R GR[reg2]←GR[reg1] OR zero-
1
1
1
0
×
×
i i i i i i i i i i i i i i i i extend(imm16)
PREPARE
list12,imm5
0 0 0 0 0 1 1 1 1 0 i i i i i L Store-memory(sp-4,GR[reg in list12],Word)
N+1 N+1 N+1
LL L L L L L L L L L 0 0 0 0 1 sp←sp-4
Note 4 Note 4 Note 4
repeat 1 step above until all regs in list12 is
stored sp←sp-zero-extend(imm5)
list12,imm5,
Note 15
sp/imm
0 0 0 0 0 1 1 1 1 0 i i i i i L Store-memory(sp-4,GR[reg in list12],Word)
N+2 N+2 N+2
LL L L L L L L L L L f f 0 1 1 sp←sp-4
Note 4 Note 4 Note 4
imm16/imm32
repeat 1 step above until all regs in list12 is Note 17 Note 17 Note 17
Note 16 stored sp←sp-zero-extend(imm5)
RETI
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 if PSW.EP=1
0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 then PC
PSW
3
3
3
R
R
R
R
1
1
1
×
0
×
×
1
1
1
×
0
×
×
1
1
1
←EIPC
←EIPSW
else if PSW.NP = 1
then
PC
←FEPC
PSW ←FEPSW
else
PC
←EIPC
PSW ←EIPSW
SAR
reg1,reg2
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2]arithmetically shift right
0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 by GR[reg1]
imm5,reg2
rr r r r 0 1 0 1 0 1 i i i i i GR[reg2]←GR[reg2]arithmetically shift right
by zero-extend(imm5)
SASF
cccc,reg2
rr r r r 1 1 1 1 1 0 c c c c c if conditions are satisfied
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 then GR[reg2]←(GR[reg2] Logically shift
left by 1)
OR 00000001H
else GR[reg2]←(GR[reg2] Logically shift
left by 1)
OR 00000000H
60
Preliminary Data Sheet U13995EJ1V0DS00
R
µPD703100-33, 703100-40, 703101-33, 703102-33
(5/7)
Execution
Mnemonic
SATADD
Operand
Opcode
Flags
Clock
Operation
i
r
l
CY
OV
S
Z
SAT
reg1,reg2
rr r r r 0 0 0 1 1 0 R R R R R GR[reg2]←saturated(GR[reg2]+GR[reg1])
1
1
1
×
×
×
×
×
imm5,reg2
rr r r r 0 1 0 0 0 1 i i i i i GR[reg2]←saturated(GR[reg2]+sign-
1
1
1
×
×
×
×
×
extend(imm5)
SATSUB
reg1,reg2
rr r r r 0 0 0 1 0 1 R R R R R GR[reg2]←saturated(GR[reg2]−GR[reg1])
1
1
1
×
×
×
×
×
SATSUBI
imm16,reg1,reg2
rr r r r 1 1 0 0 1 1 R R R R R GR[reg2]←saturated(GR[reg1]−sign-
1
1
1
×
×
×
×
×
×
×
×
×
×
i i i i i i i i i i i i i i i i extend(imm16)
SATSUBR
reg1,reg2
rr r r r 0 0 0 1 0 0 R R R R R GR[reg2]←saturated(GR[reg1]−GR[reg2])
1
1
1
SETF
cccc,reg2
rr r r r 1 1 1 1 1 1 0 c c c c If conditions are satisfied
1
1
1
3
3
3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 then GR[reg2]←00000001H
else GR[reg2]←00000000H
SET1
bit#3,disp16[reg1] 0 0 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d d Z flag←Not(Load-memory-bit(adr,bit#3))
×
Note 3 Note 3 Note 3
Store-memory-bit(adr,bit#3,1)
reg2,[reg1]
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 Z flag←Not(Load-memory-bit(adr,reg2))
3
3
×
3
Note 3 Note 3 Note 3
Store-memory-bit(adr,reg2,1)
SHL
reg1,reg2
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2] logically shift left by
1
1
1
×
0
×
×
1
1
1
×
0
×
×
1
1
1
×
0
×
×
1
1
1
×
0
×
×
1
1
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 GR[reg1]
imm5,reg2
rr r r r 0 1 0 1 1 0 i i i i i GR[reg2]←GR[reg2] logically shift left by
zero-extend(imm5)
SHR
reg1,reg2
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←GR[reg2] logically shift right by
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 GR[reg1]
imm5,reg2
rr r r r 0 1 0 1 0 0 i i i i i GR[reg2]←GR[reg2] logically shift right by
zero-extend(imm5)
SLD.B
disp7[ep],reg2
rr r r r 0 1 1 0 d d d d d d d adr←ep+zero-extend(disp7)
n
Note 9
GR[reg2]←sign-extend(Loadmemory(adr,Byte))
SLD.BU
disp4[ep],reg2
rr r r r 0 0 0 0 1 1 0 d d d d adr←ep+zero-extend(disp4)
1
1
Note 18
SLD.H
disp8[ep],reg2
n
Note 9
GR[reg2]←zero-extend(Loadmemory(adr,Byte))
rr r r r 1 0 0 0 d d d d d d d adr←ep+zero-extend(disp8)
Note 19
1
1
n
Note 9
GR[reg2]←sign-extend(Loadmemory(adr,Half-word))
SLD.HU
disp5[ep],reg2
rr r r r 0 0 0 0 1 1 1 d d d d adr←ep+zero-extend(disp5)
1
1
Notes 18, 20
SLD.W
disp8[ep],reg2
memory(adr,Half-word))
rr r r r 1 0 1 0 d d d d d d 0 adr←ep+zero-extend(disp8)
Note 21
SST.B
reg2,disp7[ep]
n
Note 9
GR[reg2]←zero-extend(Load-
1
1
rr r r r 0 1 1 1 d d d d d d d adr←ep+zero-extend(disp7)
n
Note 9
GR[reg2]←Load-memory(adr,Word))
1
1
1
Store-memory(adr,GR[reg2],Byte)
Preliminary Data Sheet U13995EJ1V0DS00
61
µPD703100-33, 703100-40, 703101-33, 703102-33
(6/7)
Execution
Mnemonic
SST.H
Operand
reg2,disp8[ep]
Opcode
rr r r r 1 0 0 1 d d d d d d d adr←ep+zero-extend(disp8)
Flags
Clock
Operation
i
r
l
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CY
OV
S
Z
Note 19 Store-memory(adr,GR[reg2],Half-word)
SST.W
reg2,disp8[ep]
rr r r r 1 0 1 0 d d d d d d 1 adr←ep+zero-extend(disp8)
Note 21 Store-memory(adr,GR[reg2],Word)
ST.B
reg2,disp16[reg1]
rr r r r 1 1 1 0 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d d Store-memory(adr,GR[reg2],Byte)
ST.H
reg2,disp16[reg1]
rr r r r 1 1 1 0 1 1 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d 0 Store-memory(adr,GR[reg2],Half-word)
Note 8
ST.W
reg2,disp16[reg1]
rr r r r 1 1 1 0 1 1 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d 1 Store-memory(adr,GR[reg2],Word)
Note 8
STSR
regID,reg2
rr r r r 1 1 1 1 1 1 R R R R R GR[reg2]←SR[regID]
00 0 0 0 0 0 0 0 1 0 0 0 0 0 0
SUB
reg1,reg2
rr r r r 0 0 1 1 0 1 R R R R R GR[reg2]←GR[reg2]−GR[reg1]
1
1
1
×
×
×
×
SUBR
reg1,reg2
rr r r r 0 0 1 1 0 0 R R R R R GR[reg2]←GR[reg1]−GR[reg2]
1
1
1
×
×
×
×
SWITCH
reg1
0 0 0 0 0 0 0 0 0 1 0 R R R R R adr←(PC+2)+(GR[reg1] logically shift left
5
5
5
1
1
1
1
1
1
3
3
3
1
1
1
0
×
×
3
3
3
by 1)
PC←(PC+2)+sign-extend((Loadmemory(adr,Hafl-word))
logically shift left by 1)
SXB
reg1
0 0 0 0 0 0 0 0 1 0 1 R R R R R GR[reg1]←sign-extend
(GR[reg1] (7 : 0)
SXH
reg1
0 0 0 0 0 0 0 0 1 1 1 R R R R R GR[reg1]←sign-extend
(GR[reg1] (15 : 0))
TRAP
vector
0 0 0 0 0 1 1 1 1 1 1 i i i i i EIPC
←PC+4 (restore PC)
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 EIPSW
←PSW
ECR.EICC
←Interrupt code
PSW.EP
←1
PSW.ID
←1
PC
←00000040H (when vector
is 00H to 0FH)
00000050H (when vector
is 10H to 1FH)
TST
reg1,reg2
rr r r r 0 0 1 0 1 1 R R R R R result←GR[reg2] AND GR[reg1]
TST1
bit#3,disp16[reg1] 1 1 b b b 1 1 1 1 1 0 R R R R R adr←GR[reg1]+sign-extend(disp16)
dd d d d d d d d d d d d d d d Z flag←Not(Load-memory-bit(adr,bit#3))
reg2,[reg1]
rr r r r 1 1 1 1 1 1 R R R R R adr←GR[reg1]
0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 Z flag←Not(Load-memory-bit(adr,reg2))
62
Preliminary Data Sheet U13995EJ1V0DS00
×
Note 3 Note 3 Note 3
3
3
3
Note 3 Note 3 Note 3
×
SAT
µPD703100-33, 703100-40, 703101-33, 703102-33
(7/7)
Execution
Mnemonic
Operand
Opcode
Flags
Clock
Operation
i
r
l
CY
OV
S
Z
XOR
reg1,reg2
rr r r r 0 0 1 0 0 1 R R R R R GR[reg2]←GR[reg2] XOR GR[reg1]
1
1
1
0
×
×
XORI
imm16,reg1,reg2
rr r r r 1 1 0 1 0 1 R R R R R GR[reg2]←GR[reg1] XOR zero-extend
1
1
1
0
×
×
ii i i i i i i i i i i i i i i
SAT
(imm16)
ZXB
reg1
0 0 0 0 0 0 0 0 1 0 0 R R R R R GR[reg1]←zero-extend(GR[reg1] (7 : 0))
1
1
1
ZXH
reg1
0 0 0 0 0 0 0 0 1 1 0 R R R R R GR[reg1]←zero-extend(GR[reg1] (15 : 0))
1
1
1
Notes 1. dddddddd: Higher 8 bits of disp9.
2. 3 clocks if the final instruction includes PSW write access.
3. If there is no wait state (3 + the number of read access wait states).
4. N is the total number of list 12 read registers. (according to the number of wait states. Also, if there are
no wait states, N is the number of list 12 registers.)
5. RRRRR other than 00000.
6. Only the lower half word data are valid.
7. ddddddddddddddddddddd: Higher 21 bits of disp22.
8. ddddddddddddddd: Higher 15 bits of disp16.
9. According to the number of wait states (1 if there are no wait states).
10. b: bit 0 of disp16.
11. According to the number of wait states (2 if there are no wait states).
12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
reg1 field is used in the op code. Therefore, the meaning of the register specification in the mnemonic
description and in the opcode differs from other instructions.
rrrrr
: regID specification
RRRRR: reg2 specification
13. 11111: Lower 5 bits of imm9.
1111 : Lower 4 bits of imm9.
14. 1 when r = w (the lower 32 bits of the results are not written in the register) or w = r0 (the higher 32 bits
of the results are not written in the register).
15. sp/imm: specified by bits 19 and 20 of the sub opcode.
16. ff = 00: load sp in ep.
01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: load 32-bit immediate data (bits 63 to 32) in ep.
17. If imm=imm32, N + 3 clocks.
18. rrrrr other than 00000.
19. ddddddd: Higher 7 bits of disp8.
20. dddd: Higher 4 bits of disp5.
21. dddddd: Higher 6 bits of disp8.
Preliminary Data Sheet U13995EJ1V0DS00
63
µPD703100-33, 703100-40, 703101-33, 703102-33
16. ELECTRICAL SPECIFICATIONS (PRELIMINARY VALUES)
Absolute Maximum Ratings (TA = 25°°C)
Parameter
Power supply voltage
Input voltage
Symbol
Rating
Unit
VDD pin
−0.5 to +4.6
V
HVDD
HVDD pin, HVDD ≥ VDD
−0.5 to +7.0
V
CVDD
CVDD pin
−0.5 to +4.6
V
CVSS
CVSS pin
−0.5 to +0.5
V
AVDD
AVDD pin
−0.5 to HVDD + 0.5
V
AVSS
AVSS pin
−0.5 to +0.5
V
−0.5 to HVDD + 0.5
V
MODE3 pin
−0.5 to VDD + 0.5
V
−0.5 to VDD + 1.0
V
VDD
VI
Condition
X1 pin, except MODE3 pin
Clock input voltage
VK
X1, VDD = 3.0 to 3.6 V
Low-level output current
IOL
1 pin
4.0
mA
Total of all pins
100
mA
1 pin
−4.0
mA
Total of all pins
−100
mA
−0.5 to HVDD + 0.5
V
AVDD > HVDD
−0.5 to HVDD + 0.5
V
HVDD ≥ AVDD
−0.5 to AVDD + 0.5
V
AVDD > HVDD
−0.5 to HVDD + 0.5
V
HVDD ≥ AVDD
−0.5 to AVDD + 0.5
V
µPD703100-40
−40 to +70
°C
µPD703100-33, 703101-33, 703102-33
−40 to +85
°C
−60 to +150
°C
High-level output current
LOH
Output voltage
VO
HVDD = 5.0 V ± 10 %
Analog input voltage
VIAN
P70/ANI0 to
P77/ANI7 pins
A/D converter reference input
voltage
Operating ambient temperature
Storage temperature
Caution
AVREF
TA
Tstg
1. Do not make direct connections of the output (or input/output) pins of the IC product with
each other, and also avoid direct connections to VDD, VCC, or GND. However, the open drain
pins or the open collector pins can be directly connected with each other. A direct
connection can also be made for an external circuit designed with timing specifications that
prevent conflicting output from pins subject to high-impedance state.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
64
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Capacitance (TA = 25°°C, VDD = HVDD = CVDD = VSS = 0 V)
Parameter
Symbol
Input capacitance
CI
Input/output capacitance
CIO
Output capacitance
CO
Condition
MIN.
TYP.
fc = 1 MHz
Unmeasured pins returned to 0 V.
MAX.
Unit
15
pF
15
pF
15
pF
Operating Conditions
Operation
Mode
Direct mode
PLL mode
Operating Ambient
Temperature (TA)
Internal Operating Clock Frequency (φ)
µPD703100-40
2 to 40 MHz
−40 to +70°C
µPD703100-33, 703101-33, 703102-33
2 to 33 MHz
−40 to +85°C
µPD703100-40
20 to 40 MHz
−40 to +70°C
µPD703100-33, 703101-33, 703102-33
20 to 33 MHz
−40 to +85°C
Power Supply Voltage
(VDD, HVDD)
VDD = 3.0 to 3.6 V,
HVDD = 5.0 V ±10%
Recommended Oscillation Circuits
(a) Ceramic resonator or crystal resonator connection (TA = –40 to +70°°C ... µPD703100-40,
TA = –40 to +85°°C ... µPD703100-33, µPD703101-33, µPD703102-33)
X1
X2
C1
Cautions
C2
1. Connect the oscillation circuit as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken line.
3. Throughly evaluate the matching between the µPD703100-33, µPD703100-40, µPD703101-33,
and µPD703102-33 and the oscillators.
(b) External clock input (TA = –40 to +70°°C ... µPD703100-40, TA = –40 to +85°°C ... µPD703100-33, µPD70310133, µPD703102-33)
X1
X2
Open
External clock
Caution Input CMOS-level voltage to the X1 pin.
Preliminary Data Sheet U13995EJ1V0DS00
65
µPD703100-33, 703100-40, 703101-33, 703102-33
DC Characteristics (TA = –40 to +70°°C ... µPD703100-40,TA = –40 to +85°°C ... µPD703100-33, µPD703101-33,
µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±10%, VSS=0 V)
Parameter
High-level input voltage
Symbol
Condition
MAX.
Unit
2.2
HVDD + 0.3
V
0.8HVDD
HVDD + 0.3
V
Except Note 1 and Note 2
−0.5
+0.8
V
Note 1
−0.5
0.2HVDD
V
Direct mode
0.8VDD
VDD + 0.3
V
PLL mode
0.8VDD
VDD + 0.3
V
Direct mode
−0.3
0.15VDD
V
PLL mode
−0.3
0.15VDD
V
Except Note 1
VIH
Note 1
Low-level input voltage
High-level clock input voltage
Low-level clock input voltage
Schmitt-triggered input
threshold voltage
Schmitt-triggered input
hysteresis width
High-level output voltage
VIL
VXH
VXL
HVT
HVT
X1 pin
X1 pin
+
−
+
HVT
–HVT−
VOH
MIN.
TYP.
Note 1, rising edge
3.0
V
Note 1, falling edge
2.0
V
Note 1
0.5
V
IOH = −2.5 mA
0.7HVDD
V
IOH = −100 µA
HVDD − 0.4
V
Low-level output voltage
VOL
IOL = 2.5 mA
0.45
V
High-level input leakage
current
ILIH
Except VI = HVDD or Note 2
10
µA
Low-level input leakage
current
ILIL
Except VI = 0 V or Note 2
−10
µA
High-level output leakage
current
ILOH
VO = HVDD
10
µA
Low-level output leakage
current
ILOL
VO = 0 V
−10
µA
Analog pin input leakage
current
ILIAN
Note 2
T.B.D.
µA
otes
1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130, P35/INTP131/SO2, P36/INTP132/S12, P37/INTP133/SCK2, P104/INTP120/TC0 to
P107/INTP123/TC3, Pl14/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3,
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,
P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2,
RESET
2. When the P70/ANI0 to P77/ANI7 pins are used as analog input.
Remark TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
66
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
DC Characteristics (TA = –40 to +70°°C ... µPD703100-40,TA = –40 to +85°°C ... µPD703100-33, µPD703101-33,
µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±10%, VSS = 0 V)
Parameter
Power supply
current
During
normal
operation
Symbol
IDD1
Condition
Direct mode
PLL mode
HALT mode
IDD2
Direct mode
PLL mode
IDLE mode
IDD3
Direct mode
PLL mode
STOP
mode
IDD4
MIN.
TYP.
MAX.
Unit
VDD + CVDD
2.0 × fx
3.6 × fx
mA
HVDD
1.8 × fx
3.0 × fx
mA
VDD + CVDD
2.7 × fx
− 17.0
3.6 × fx
mA
HVDD
1.3 × fx
− 3.6
3.0 × fx
mA
VDD + CVDD
1.4 × fx
2.5 × fx
mA
HVDD
0.8 × fx
1.6 × fx
mA
VDD + CVDD
1.8 × fx
− 10.0
2.5 × fx
mA
HVDD
0.8 × fx
− 1.0
1.6 × fx
mA
VDD + CVDD
1.5
3.0
mA
HVDD
10
50
µA
VDD + CVDD
1.8
3.0
mA
HVDD
10
50
µA
VDD + CVDD
20
100
µA
HVDD
10
50
µA
Remarks 1. TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
2. Direct mode:
fX = 2 to 40 MHz (µPD703100-40)
fX = 2 to 33 MHz (µPD703100-33, µPD703101-33, µPD703102-33)
PLL mode:
fX = 20 to 40 MHz (µPD703100-40)
fX = 20 to 33 MHz (µPD703100-33, µPD703101-33, µPD703102-33)
Preliminary Data Sheet U13995EJ1V0DS00
67
µPD703100-33, 703100-40, 703101-33, 703102-33
Data Hold Characteristics(TA = –40 to +70°°C ... µPD703100-40, TA = –40 to +85°°C ... µPD703100-33, µPD70310133, µPD703102-33)
Parameter
Symbol
Data hold voltage
Condition
VDDDR
MIN.
MAX.
Unit
1.5
3.6
V
VDDDR
5.5
V
T.B.D.
µA
STOP mode, VDD = VDDDR
STOP mode,
HVDD = HVDDDR
HVDDDR
TYP.
Data hold current
IDDDR
VDD = VDDDR
T.B.D.
Power supply voltage rise
time
tRVD
200
µs
Power supply voltage fall time
tFVD
200
µs
Power supply voltage hold
time (to STOP mode setting)
tHVD
0
ms
STOP mode release signal
input time
tDREL
0
ns
Data hold high-level input
voltage
VIHDR
Note
0.8 HVDDDR
HVDDDR
V
Data hold low-level input
voltage
VILDR
Note
0
0.2 HVDDDR
V
Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,
P34/INTP130,
P35/INTP131/SO2,
P107/INTP123/TC3,
P114/INTP140,
P36/INTP132/SI2,
P37/INTP133/SCK2,
P115/INTP141/SO3,
Pl16/INTP142/SI3,
P104/INTP120/TC0
to
P117/INTP143/SCK3,
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12,P113/TI14,
P123/TI15, P20/NMI, P23/RXD0/SI0 ,P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET
Remark TYP. values are reference values for when TA = 25°C.
STOP mode setting
VDDDR
VDD
tFVD
tRVD
tHVD
tDREL
HVDD
VIHDR
RESET (input)
NMI (input)
(Released by falling edge)
VIHDR
NMI (input)
(Released by rising edge)
VILDR
68
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
AC Characteristics (TA = –40 to +70°°C ... µPD703100-40, TA = –40 to +85°°C ... µPD703100-33, µPD703101-33,
µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±10%, VSS = 0 V, output pin load
capacitance: CL = 50 pF)
AC Test Input Waveform
(a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/
INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/
TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/
INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14,
P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/
SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET
HVDD
0.8HVDD
Input signal
0V
Test
points
0.2HVDD
0.8HVDD
0.2HVDD
(b) Pins other than those listed in (a) above
2.4 V
2.2 V
Input signal
0.4 V
Test
points
2.2 V
0.8 V
0.8 V
AC Test Output Test Points
2.4 V
Output Signal
Test
points
0.8 V
Preliminary Data Sheet U13995EJ1V0DS00
2.4 V
0.8 V
69
µPD703100-33, 703100-40, 703101-33, 703102-33
Load Condition
DUT
(Measured Device)
CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert
a buffer or other element to reduce the devide's load capacitance 50 pF.
(1) Clock timing
Parameter
X1 input cycle
X1 input high-level width
X1 input low-level width
X1 input rise time
X1 input fall time
CPU operating frequency
Symbol
<1>
<2>
<3>
<4>
<5>
Condition
tCYX
tWXH
tWXL
tXR
tXF
φ
–
MIN.
MAX.
Unit
Direct
mode
µPD703100-40
12.5
250
ns
µPD703100-33,
703101-33,
703102-33
15
250
ns
PLL mode
µPD703100-40
125
250
ns
µPD703100-33,
703101-33,
703102-33
150
250
ns
Direct mode
5
ns
PLL mode
50
ns
Direct mode
5
ns
PLL mode
50
ns
Direct mode
4
ns
PLL mode
10
ns
Direct mode
4
ns
PLL mode
10
ns
µPD703100-40
2
40
MHz
µPD703100-33, 703101-33,
703102-33
2
33
MHz
500
ns
CLKOUT output cycle
<6>
tCYK
30
CLKOUT input high-level width
<7>
tWKH
0.5T – 7
ns
CLKOUT input low-level width
<8>
tWKL
0.5T – 4
ns
CLKOUT input rise time
<9>
tKR
5
ns
CLKOUT input fall time
<10>
tKF
5
ns
CLKOUT output delay time from X1 ↓
<11>
tDXK
T.B.D.
ns
Direct mode
T.B.D.
Remark T = tCYK
Parameter
Free-running oscillation frequency
70
Symbol
–
φP
Condition
PLL mode
Preliminary Data Sheet U13995EJ1V0DS00
TYP.
Unit
T.B.D.
MHz
µPD703100-33, 703100-40, 703101-33, 703102-33
<1>
<2>
<3>
<4>
<5>
X1
(PLL mode)
<1>
<2>
<3>
<4>
X1
(Direct mode)
<5>
<11>
<11>
CLKOUT (output)
<9>
<10>
<7>
<8>
<6>
(2) Output waveform (other than X1, CLKOUT)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Output rise time
<12>
tOR
10
ns
Output fall time
<13>
tOF
10
ns
<12>
<13>
Signals other than X1, CLKOUT
Preliminary Data Sheet U13995EJ1V0DS00
71
µPD703100-33, 703100-40, 703101-33, 703102-33
(3) Reset timing
Parameter
Symbol
Condition
RESET high-level width
<14>
tWRSH
RESET low-level width
<15>
tWRSL
MIN.
Unit
500
ns
When power supply is on, and
STOP mode has been released
500 + TOS
ns
Other than when power supply is
on, and STOP mode has been
released
500
ns
Remark TOS: Oscillation stabilization time
<14>
RESET (input)
72
MAX.
Preliminary Data Sheet U13995EJ1V0DS00
<15>
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Preliminary Data Sheet U13995EJ1V0DS00
73
µPD703100-33, 703100-40, 703101-33, 703102-33
(4) SRAM, external ROM, or external I/O access timing
(a) Access timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Address, CSn output delay time (from
CLKOUT ↓)
<16>
tDKA
2
10
ns
Address, CSn output hold time (from
CLKOUT ↓)
<17>
tHKA
2
10
ns
RD, IORD ↓ delay time
(from CLKOUT ↑)
<18>
tDKRDL
2
14
ns
RD, IORD ↑ delay time
(from CLKOUT ↑)
<19>
tHKRDH
2
14
ns
UWR, LWR, IOWR ↓ delay time (from
CLKOUT ↑)
<20>
tDKWRL
2
10
ns
UWR, LWR, IOWR ↑ delay time (from
CLKOUT ↑)
<21>
tHKWRH
2
10
ns
BCYST ↓ delay time (from CLKOUT
↓)
<22>
tDKBSL
2
10
ns
BCYST ↑ delay time (from CLKOUT
↓)
<23>
tHKBSH
2
10
ns
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Data input setup time
(to CLKOUT ↑)
<26>
tSKID
18
ns
Data input hold time
(from CLKOUT ↑)
<27>
tHKID
2
ns
Data output delay time
(from CLKOUT ↓)
<28>
tDKOD
2
10
ns
Data output hold time
(from CLKOUT ↓)
<29>
tHKOD
2
10
ns
Remarks 1. Maintain at least one of the data input hold times tHKID and tHRDID.
2. n = 0 to 7
74
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(a) Access timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
<16>
<17>
A0 to A23 (Output)
CSn (Output)
<22>
<23>
BCYCT (Output)
<18>
<19>
<20>
<21>
RD, IORD (Output)
[Read time]
UWR, LWR, IOWR (Output)
[Write time]
<26>
<27>
D0 to 15 (I/O)
[Read time]
<28>
<29>
D0 to 15 (I/O)
[Write time]
<25>
<24>
<25>
<24>
WAIT (Input)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
75
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data input setup time (to address)
<30>
tSAID
(1.5 + wD + w) T – 28
ns
Data input setup time (to RD)
<31>
tSRDID
(1 + wD + w) T – 32
ns
RD, IORD low-level width
<32>
tWRDL
(1 + wD + w) T – 10
ns
RD, IORD high-level width
<33>
tWRDH
T – 10
ns
RD, IORD ↓ delay time from address,
CSn
<34>
tDARD
0.5T – 10
ns
Address delay time from RD, IORD ↑
<35>
tDRDA
(0.5 + i) T – 10
ns
Data input hold time (from RD, IORD ↑)
<36>
tHRDID
0
ns
Data output delay time from RD, IORD ↑
<37>
tDRDOD
(0.5 + i) T – 10
ns
WAIT setup time (to address)
<38>
tSAW
Note
T – 25
ns
WAIT setup time (to BCYST ↓)
<39>
tSBSW
Note
T – 25
ns
WAIT hold time (to BCYST ↑)
<40>
tHBSW
Note
0
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. i: the number of idle states that are inserted when a write cycle follows a read cycle.
5. Maintain at least one of the data input hold times tHKID and tHRDID.
6. n = 0 to 7
76
Preliminary Data Sheet U13995EJ1V0DS00
ns
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
UWR, LWR, IOWR (Output)
<33>
<32>
<35>
RD, IORD (Output)
<34>
<31>
<30>
<37>
<36>
D0 to 15 (I/O)
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
77
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to address)
<38>
tSAW
Note
T – 25
ns
WAIT setup time (to BCYST ↓)
<39>
tSBSW
Note
T – 25
ns
WAIT hold time (from BCYST ↑)
<40>
tHBSW
Note
UWR, LWR, IOWR ↓ delay time from
address, CSn
<41>
Address setup time (to UWR, LWR,
IOWR ↑)
0
ns
tDAWR
0.5T – 10
ns
<42>
tSAWR
(1.5 + wD + w) T – 10
ns
Address delay time from UWR, LWR,
IOWR ↑
<43>
tDWRA
0.5T – 10
ns
UWR, LWR, IOWR high-level width
<44>
tWWRH
T – 10
ns
UWR, LWR, IOWR low-level width
<45>
tWWRL
(1 + wD + w) T – 10
ns
Data output setup time
(to UWR, LWR, IOWR ↑)
<46>
tSODWR
(1.5 + wD + w) T – 10
ns
Data output hold time
(from UWR, LWR, IOWR ↑)
<47>
tHWROD
0.5T – 10
ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. n = 0 to 7
78
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
RD, IORD (Output)
<41>
<42>
<45>
<43>
<44>
UWR, LWR, IOWR (Output)
<46>
<47>
D0 to 15 (I/O)
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
79
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
RD low-level width
<32>
tWRDL
(1 + wD + wF + w)
T – 10
ns
RD high-level width
<33>
tWRDH
T – 10
ns
RD ↓ delay time from address, CSn
<34>
tDARD
0.5T – 10
ns
Address delay time from RD ↑
<35>
tDRDA
(0.5 + i) T – 10
ns
Data output delay time from RD ↑
<37>
tDRDOD
(0.5 + i) T – 10
ns
WAIT setup time (to address)
<38>
tSAW
Note
T – 25
ns
WAIT setup time (to BCYST ↓)
<39>
tSBSW
Note
T – 25
ns
WAIT hold time (from BCYST ↑)
<40>
tHBSW
Note
IOWR ↓ delay time from address
<41>
Address setup time (to IOWR ↑)
0
ns
tDAWR
0.5T – 10
ns
<42>
tSAWR
(1.5 + wD + w) T – 10
ns
Address delay time from UWR, LWR,
IOWR ↑
<43>
tDWRA
0.5T – 10
ns
IOWR high-level width
<44>
tWWRH
T – 10
ns
IOWR low-level width
<45>
tWWRL
(1 + wD + w) T – 10
ns
RD ↑ delay time from IOWR ↑
<48>
tDWRRD
wF = 0
0
ns
wF = 1
T – 10
ns
IOWR ↓ delay time from DMAAKm ↓
<49>
tDDAWR
0.5T – 10
ns
DMAAKm ↑ delay time from IOWR ↑
<50>
tDWRDA
(0.5 + wF) T – 10
ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0 to 7, m = 0 to 3
80
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
<33>
<32>
<35>
RD (Output)
<34>
<48>
UWR, LWR (Output)
DMAAKm (Output)
<49>
<50>
IORD (Output)
<42>
<41>
<43>
<45>
<44>
IOWR (Output)
<37>
D0 to 15 (I/O)
<38>
<24>
<25>
<25>
<24>
WAIT (Input)
<40>
<39>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
81
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
IORD low-level width
<32>
tWRDL
(1 + wD + wF + w)
T – 10
ns
IORD high-level width
<33>
tWRDH
T – 10
ns
IORD ↓ delay time from address, CSn
<34>
tDARD
0.5T – 10
ns
Address delay time from IORD ↑
<35>
tDRDA
(0.5 + i) T – 10
ns
Data output delay time from IORD ↑
<37>
tDRDOD
(0.5 + i) T – 10
ns
WAIT setup time (to address)
<38>
tSAW
Note
T – 25
ns
WAIT setup time (to BCYST ↓)
<39>
tSBSW
Note
T – 25
ns
WAIT hold time (from BCYST ↑)
<40>
tHBSW
Note
UWR, LWR ↓ delay time from address
<41>
Address setup time (to UWR, LWR ↑)
0
ns
tDAWR
0.5T – 10
ns
<42>
tSAWR
(1.5 + wD + w) T – 10
ns
Address delay time from UWR, LWR,
IOWR ↑
<43>
tDWRA
0.5T – 10
ns
UWR, LWR high-level width
<44>
tWWRH
T – 10
ns
UWR, LWR low-level width
<45>
tWWRL
(1 + wD + w) T – 10
ns
IORD ↑ delay time from UWR, LWR↑
<48>
tDWRRD
wF = 0
0
ns
wF = 1
T – 10
ns
IORD ↓ delay time from DMAAKm ↓
<51>
tDDARD
0.5T – 10
ns
DMAAKm ↑ delay time from IORD ↑
<52>
tDRDDA
0.5T – 10
ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0 to 7, m = 0 to 3
82
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
<41>
<42>
<45>
<43>
<35>
<44>
UWR, LWR (Output)
<48>
RD (Output)
<51>
<52>
DMAAKm (Output)
IOWR (Output)
<34>
<33>
<32>
<35>
IORD (Output)
<37>
D0 to 15 (I/O)
<38>
<24>
<25>
<25>
<24>
WAIT (Input)
<40>
<39>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
83
µPD703100-33, 703100-40, 703101-33, 703102-33
(5) Page ROM access timing (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Data input setup time
(to CLKOUT ↑)
<26>
tSKID
18
ns
Data input hold time
(from CLKOUT ↑)
<27>
tHKID
2
ns
Off-page data input setup time (to
address)
<30>
tSAID
(1.5 + wD + w) T – 28
ns
Off-page data input setup time (to RD)
<31>
tSRDID
(1 + wD + w) T – 32
ns
Off-page RD low-level width
<32>
tWRDL
(1 + wD + w) T – 10
ns
RD high-level width
<33>
tWRDH
0.5T – 10
ns
Data input hold time (from RD)
<36>
tHRDID
0
ns
Data output delay time from RD ↑
<37>
tDRDOD
(0.5 + i) T – 10
ns
On-page RD low-level width
<53>
tWORDL
(1.5 + wPR + w)
T – 10
ns
On-page data input setup time
(to address)
<54>
tSOAID
(1.5 + wPR + w) T – 28
ns
On-page data input setup time (to RD)
<55>
tSORDID
(1.5 + wPR + w) T – 32
ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wD: the number of waits due to the DWC1 and DWC2 registers.
4. wPR: the number of waits due to the PRC register.
5. i: the number of idle states that are inserted when a write cycle follows a read cycle.
6. Maintain at least one of the data input hold times tHKID and tHRDID.
84
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(5) Page ROM access timing (2/2)
T1
TDW
TW
T2
TO1
TPRW
TW
TO2
CLKOUT (Output)
Off-page address Note
CSn (Output)
On-page address Note
<26>
<30>
<54>
UWR, LWR (Output)
<33>
<32>
<53>
<55>
<31>
<37>
RD (Output)
<36>
<36>
<26>
<27>
<27>
D0 to 15 (I/O)
<25>
<25>
<24>
<25>
<24>
<24>
<25>
<24>
WAIT (Input)
BCYST (Output)
Note On-page and off-page addresses are as follows.
PRC register
On-page Addresses
Off-page Addresses
0
A0, A1
A2 to A23
0
1
A0 to A2
A3 to A23
1
1
A0 to A3
A4 to A23
1
1
A0 to A4
A5 to A23
MA5
MA4
MA3
0
0
0
0
1
Remarks 1. This is the timing for the following case.
Number of waits due to the DWC1 and DWC2 registers (TDW): 1
Number of waits due to the PRC register (TPRW)
: 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
85
µPD703100-33, 703100-40, 703101-33, 703102-33
(6) DRAM access timing
(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Data input setup time (to CLKOUT ↑)
<26>
tSKID
18
ns
Data input hold time (from CLKOUT ↑)
<27>
tHKID
2
ns
Data output delay time from OE ↑
<37>
tDRDOD
(0.5 + i) T – 10
ns
Row address setup time
<56>
tASR
(0.5 + wRP) T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH) T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA + w) T – 10
ns
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA + w)
T – 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP) T – 10
ns
RAS pulse time
<62>
tRAS
(2.5 + wRH + wDA + w)
T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA + w) T – 10
ns
Column address read time for RAS
<64>
tRAL
(2 + wDA + w) T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA + w) T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRP) T – 10
ns
CAS hold time
<67>
tCSH
(2 + wRH + wDA + w)
T – 10
ns
WE setup time
<68>
tRCS
(2 + wRP + wRH) T – 10
ns
WE hold time (from RAS ↑)
<69>
tRRH
0.5T – 10
ns
WE hold time (from CAS ↑)
<70>
tRCH
T – 10
ns
CAS precharge time
<71>
tCPN
(2 + wRP + wRH) T – 10
ns
Output enable access time
<72>
tOEA
(2 + wRP + wRH + wDA + w)
T – 28
ns
RAS access time
<73>
tRAC
(2 + wRH + wDA + w)
T – 28
ns
Access time from column address
<74>
tAA
(1.5 + wDA + w) T – 28
ns
CAS access time
<75>
tCAC
(1 + wDA + w) T – 28
ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
86
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
RAS column address delay time
<76>
tRAD
(0.5 + wRH) T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH) T – 10
ns
Output buffer turn-off delay time (from
OE ↑)
<78>
tOEZ
0
ns
Output buffer turn-off delay time (from
CAS ↑)
<79>
tOFF
0
Remarks 1. T = tCYK
2. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
Preliminary Data Sheet U13995EJ1V0DS00
87
µPD703100-33, 703100-40, 703101-33, 703102-33
(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)
TRPW
T1
TRHW
T2
TDAW
TW
T3
CLKOUT (Output)
<58>
<56>
<57>
<59>
Row address
A0 to A23 (Output)
Column address
<63>
<64>
<76>
<61>
<62>
RASn (Output)
<60>
<77>
<65>
<66>
<67>
UCAS (Output)
LCAS (Output)
<69>
<71>
<73>
<68>
<75>
<70>
WE (Output)
<79>
<74>
<27>
<72>
<37>
OE (Output)
<78>
<26>
D0 to D15 (I/O)
<24>
<25>
<25>
<24>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
88
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Preliminary Data Sheet U13995EJ1V0DS00
89
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data input setup time (to CLKOUT ↑)
<26>
tSKID
18
ns
Data input hold time (from CLKOUT ↑)
<27>
tHKID
2
ns
Data output delay time from OE ↑
<37>
tDRDOD
(0.5 + i) T – 10
ns
Column address setup time
<58>
tASC
(0.5 + wCP) T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA) T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA) T – 10
ns
Column address read time for RAS
<64>
tRAL
(2 + wCP + wDA) T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA) T – 10
ns
WE setup time (to CAS ↓)
<68>
tRCS
(1 + wCP) T – 10
ns
WE hold time (from RAS ↑)
<69>
tRRH
0.5T – 10
ns
WE hold time (from CAS ↑)
<70>
tRCH
T – 10
ns
Output enable access time
<72>
tOEA
(1 + wCP + wDA) T – 28
ns
Access time from column address
<74>
tAA
(1.5 + wCP + wDA) T – 28
ns
CAS access time
<75>
tCAC
(1 + wDA) T – 28
ns
Output buffer turn-off delay time (from
OE ↑)
<78>
tOEZ
0
ns
Output buffer turn-off delay time (from
CAS ↑)
<79>
tOFF
0
ns
Access time from CAS precharge
<80>
tACP
CAS precharge time
<81>
tCP
(1 + wCP) T – 10
ns
High-speed page mode cycle time
<82>
tPC
(2 + wCP + wDA) T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2.5 + wCP + wDA) T – 10
ns
(2 + wCP + wDA) T – 28
ns
Remarks 1. T = tCYK
2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. i: the number of idle states that are inserted when a write cycle follows a read cycle.
90
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(b) Read timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
<58>
<59>
A0 to A23 (Output)
Column address
<63>
<64>
RASn (Output)
<83>
<81>
<65>
<82>
UCAS (Output)
LCAS (Output)
<69>
<68>
<70>
WE (Output)
<75>
<72>
<79>
<26>
<37>
OE (Output)
<74>
<80>
<78>
<27>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
91
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Row address setup time
<56>
tASR
(0.5 + wRP) T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH) T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA + w) T – 10
ns
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA + w)
T – 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP) T – 10
ns
RAS pulse time
<62>
tRAS
(2.5 + wRH + wDA + w)
T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA + w) T – 10
ns
Column address read time (from RAS ↑)
<64>
tRAL
(2 + wDA + w) T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA + w) T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRH) T – 10
ns
CAS hold time
<67>
tCSH
(2 + wRH + wDA + w)
T – 10
ns
CAS precharge time
<71>
tCPN
(2 + wRP + wRH) T – 10
ns
RAS column address delay time
<76>
tRAD
(0.5 + wRH) T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH) T – 10
ns
WE setup time (to CAS ↓)
<84>
tWCS
(1 + wRP + wRH )
T – 10
ns
WE hold time (from CAS ↓)
<85>
tWCH
(1 + wDA + w) T – 10
ns
Data setup time (to CAS ↓)
<86>
tDS
(1.5 + wRP + wRH) T – 10
ns
Data hold time (from CAS ↓)
<87>
tDH
(1.5 + wDA + w) T – 10
ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
92
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2)
TRPW
T1
TRHW
T2
TDAW
TW
T3
CLKOUT (Output)
<58>
<56>
A0 to A23 (Output)
<57>
<59>
Row address
Column address
<63>
<64>
<76>
<61>
<62>
RASn (Output)
<60>
<77>
<66>
<65>
<67>
UCAS (Output)
LCAS (Output)
<71>
OE (Output)
<84>
<85>
WE (Output)
<86>
<87>
D0 to D15 (I/O)
<24>
<25>
<25>
<24>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
93
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Column address setup time
<58>
tASC
(0.5 + wCP) T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA) T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA) T – 10
ns
Column address read time (from RAS ↑)
<64>
tRAL
(2 + wCP + wDA) T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA) T – 10
ns
CAS precharge time
<81>
tCP
(1 + wCP) T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2.5 + wCP + wDA)
T – 10
ns
WE setup time (to CAS ↓)
<84>
tWCS
wCPT – 10
ns
WE hold time (from CAS ↓)
<85>
tWCH
(1 + wDA) T – 10
ns
Data setup time (to CAS ↓)
<86>
tDS
(0.5 + wCP) T – 10
ns
Data hold time (from CAS ↓)
<87>
tDH
(1.5 + wDA) T – 10
ns
WE read time (from RAS ↑)
<88>
tRWL
wCP = 0
(1.5 + wDA) T – 10
ns
WE read time (from CAS ↑)
<89>
tCWL
wCP = 0
(1 + wDA) T – 10
ns
Data setup time (to WE ↓)
<90>
tDSWE
wCP = 0
0.5T – 10
ns
Data hold time (from WE ↓)
<91>
tDHWE
wCP = 0
(1.5 + wDA) T – 10
ns
WE pulse width
<92>
tWP
wCP = 0
(1 + wDA) T – 10
ns
wCP ≥ 1
Remarks 1. T = tCYK
2. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
94
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(d) Write timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
<58>
A0 to A23 (Output)
<59>
Column address
<63>
<64>
RASn (Output)
<83>
<81>
<65>
UCAS (Output)
LCAS (Output)
<89>
<88>
OE (Output)
<84>
<85>
<92>
WE (Output)
<91>
<90>
<86>
<87>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW ): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
95
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data input setup time (to CLKOUT ↑)
<26>
tSKID
18
ns
Data input hold time (from CLKOUT ↑)
<27>
tHKID
2
ns
Data output delay time from OE ↑
<37>
tDRDOD
(0.5 + i) T – 10
ns
Row address setup time
<56>
tASR
(0.5 + wRP) T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH) T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(0.5 + wDA) T – 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP) T – 10
ns
Column address read time (from RAS ↑)
<64>
tRAL
(2 + wCP + wDA) T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRP) T – 10
ns
CAS hold time
<67>
tCSH
(1.5 + wRH + wDA) T – 10
ns
WE setup time (to CAS ↓)
<68>
tRCS
(2 + wRP + wRH) T – 10
ns
WE hold time (from RAS ↑)
<69>
tRRH
0.5T – 10
ns
WE hold time (from CAS ↑)
<70>
tRCH
1.5T – 10
ns
RAS access time
<73>
tRAC
(2 + wRH + wDA) T – 28
ns
Access time from column address
<74>
tAA
(1.5 + wDA) T – 28
ns
CAS access time
<75>
tCAC
(1 + wDA) T – 28
ns
Column address delay time from RAS
<76>
tRAD
(0.5 + wRH) T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH) T – 10
ns
Output buffer turn-off delay time (from
OE)
<78>
tOEZ
0
ns
Access time from CAS precharge
<80>
tACP
CAS precharge time
<81>
tCP
(0.5 + wCP) T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2 + wCP + wDA) T – 10
ns
Read cycle time
<93>
tHPC
(1 + wDA + wCP) T – 10
ns
RAS pulse width
<94>
tRASP
(2.5 + wRH + wDA) T – 10
ns
CAS pulse width
<95>
tHCAS
(0.5 + wDA) T – 10
ns
Off-page
<96>
tOCH1
(2 + wRH + wDA) T – 10
ns
On-page
<97>
tOCH2
(0.5 + wDA) T – 10
ns
<98>
tDHC
0
ns
CAS hold time from OE
Data input hold time (from CAS ↓)
(1.5 + wCP + wDA) T – 28
ns
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: the number of idle states that are inserted when a write cycle follows a read cycle.
96
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (2/3)
Parameter
Output enable access
time
Symbol
Condition
MIN.
MAX.
Unit
Off-page
<99>
tOEA1
(2 + wPR + wRH + wDA)
T – 28
ns
On-page
<100>
tOEA2
(1 + wCP + wDA) T – 28
ns
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
Preliminary Data Sheet U13995EJ1V0DS00
97
µPD703100-33, 703100-40, 703101-33, 703102-33
(e) Read timing (EDO DRAM) (3/3)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (Output)
<58>
<56>
A0 to A23 (Output)
<57>
Row address
<59>
Column address
Column address
<64>
<76>
<74>
<94>
<61>
RASn (Output)
<67>
<66>
<83>
<77>
<95>
<81>
<75>
UCAS (Output)
LCAS (Output)
<68>
<93>
<69>
<95>
<80>
<70>
WE (Output)
<97>
<96>
<100>
<26>
OE (Output)
<75>
<74>
D0 to D15 (I/O)
<98>
<27>
<27>
<78>
<26>
Data
<73>
<99>
BCYST (Output)
WAIT (Input)
Note For on-page access from another cycle during the RASn low level signal.
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
98
Preliminary Data Sheet U13995EJ1V0DS00
Data
<37>
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Preliminary Data Sheet U13995EJ1V0DS00
99
µPD703100-33, 703100-40, 703101-33, 703102-33
(f) Write timing (EDO DRAM) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Row address setup time
<56>
tASR
(0.5 + wRP) T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH) T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(0.5 + wDA) T – 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP) T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA) T – 10
ns
Column address read time
(from RAS ↑)
<64>
tRAL
(2 + wCP + wDA) T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRP) T – 10
ns
CAS hold time
<67>
tCSH
(1.5 + wRH + wDA) T – 10
ns
Column address delay time from RAS
<76>
tRAD
(0.5 + wRH) T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH) T – 10
ns
CAS precharge time
<81>
tCP
(0.5 + wCP) T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2 + wCP + wDA) T – 10
ns
WE hold time (from CAS ↓)
<85>
tWCH
(1 + wDA) T – 10
ns
Data hold time (from CAS ↓)
<87>
tDH
(0.5 + wDA) T – 10
ns
WE read time
(from RAS ↑)
On-page
<88>
tRWL
wCP = 0
(1.5 + wDA) T – 10
ns
WE read time
(from CAS ↑)
On-page
<89>
tCWL
wCP = 0
(0.5 + wDA) T – 10
ns
WE pulse width
On-page
<92>
tWP
wCP = 0
(1 + wDA) T – 10
ns
Write cycle time
<93>
tHPC
(1 + wDA + wCP) T – 10
ns
RAS pulse width
<94>
tRASP
(2.5 + wRH + wDA) T – 10
ns
CAS pulse width
<95>
tHCAS
(0.5 + wDA) T – 10
ns
Off-page
<101>
tWCS1
(1 + wRP + wRH) T – 10
ns
On-page
<102>
tWCS2
wCPT – 10
ns
Off-page
<103>
tDS1
(1.5 + wRP + wRH) T – 10
ns
On-page
<104>
tDS2
(0.5 + wCP) T – 10
ns
WE setup time
(to CAS ↓)
Data setup time
(to CAS ↓)
wCP ≥ 1
Remarks 1. T = tCYK
2. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
100
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(f) Write timing (EDO DRAM) (2/2)
TRPW
T1
TRHW
T2
TDAW
TCPW
TB
TDAW
TE
CLKOUT (Output)
<58>
<56>
<57>
<59>
Row address
A0 to A23 (Output)
<58>
Column address
<59>
Column address
<76>
<64>
<61>
<94>
RASn (Output)
<67>
<66>
<77>
<83>
<95>
<81>
<63>
UCAS (Output)
LCAS (Output)
<93>
<95>
<89>
<88>
RD (Output)
OE (Output)
<102>
<85>
<101>
<85>
<92>
WE (Output)
<103>
D0 to D15 (I/O)
<87>
Data
<104>
<87>
Data
BCYST (Output)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
101
µPD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Data output delay time from OE ↑
<37>
tDRDOD
(0.5 + i) T – 10
ns
IOWR ↓ delay time from address
<41>
tDAWR
(0.5 + wRP) T – 10
ns
Address setup time
(to UWR, LWR IOWR ↑)
<42>
tSAWR
(2 + wRP + wRH + wDA)
T – 10
ns
Address delay time from IOWR ↑
<43>
tDWRA
0.5T – 10
ns
RD ↑ delay time from IOWR ↑
<48>
tDWRRD
wF = 0
0
ns
wF = 1
T – 10
ns
IOWR low-level width
<50>
tWWRL
(2 + wRH + wDA + w)
T – 10
ns
Row address setup time
<56>
tASR
(0.5 + wRP) T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH) T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA + wF + w)
T – 10
ns
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA +
wF +w) T – 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP) T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA + wF + w)
T – 10
ns
Column address read time for RAS
<64>
tRAL
(2 + wCP + wDA + wF + w)
T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA + wF + w)
T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRP) T – 10
ns
CAS hold time
<67>
tCSH
(2 + wRH + wDA + wF +w)
T – 10
ns
WE setup time (to CAS ↓)
<68>
tRCS
(2 + wRP + wRH) T – 10
ns
WE hold time (from RAS ↑)
<69>
tRRH
0.5T – 10
ns
WE hold time (from CAS ↑)
<70>
tRCH
1.5T – 10
ns
CAS precharge time
<71>
tCPN
(2 + wRP + wRH) T – 10
ns
RAS column address delay time
<76>
tRAD
(0.5 + wRH) T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH) T – 10
ns
102
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
Preliminary Data Sheet U13995EJ1V0DS00
103
µPD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) R external I/O transfer) (2/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Output buffer turn-off delay time (from
OE ↑)
<78>
tOEZ
0
ns
Output buffer turn-off delay time (from
CAS ↑)
<79>
tOFF
0
ns
CAS precharge time
<81>
tCP
(0.5 + wCP) T – 10
ns
High-speed page mode cycle time
<82>
tPC
(2 + wCP + wDA + wF + w)
T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2.5 + wCP + wDA + wF + w)
T – 10
ns
RAS pulse width
<94>
tRASP
(2.5 + wRH + wDA + wF + w)
T – 10
ns
Off-page
<96>
tOCH1
(2.5 + wRP + wRH + wDA
+ wF + w) T – 10
ns
On-page
<97>
tOCH2
(1.5 + wCP + wDA + wF + w)
T – 10
ns
CAS ↓ delay time from DMAAKm ↓
<105>
tDDACS
(1.5 + wRH) T – 10
ns
CAS ↓ delay time from IOWR ↓
<106>
tDRDCS
(1 + wRH) T – 10
ns
OE → CAS hold time
(from CAS ↑)
Remarks 1. T=tCYK
2. w: the number of waits due to WAIT.
3. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. m = 0 to 3
104
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (3/3)
TRPW
T1
T2
TRHW
TDAW
TW
T3
TCPW TO1 TDAW
TW
TO2
CLKOUT (Output)
<58>
<56>
A0 to A23 (Output)
<57>
<59>
Row address
Column address
Column address
<76>
<64>
<61>
<94>
<60>
RASn (Output)
<77>
<65>
<66>
<69>
<83>
<67>
<81>
<63>
UCAS (Output)
LCAS (Output)
<71>
<70>
<82>
<96>
<79>
RD (Output)
OE (Output)
<105>
<48>
<97>
DMAAKm (Output)
<68>
WE (Output)
IORD (Output)
<106>
<42>
<41>
<43>
<78>
<37>
<50>
IOWR (Output)
<24>
D0 to D15 (I/O)
Data
<25>
<24>
Data
<24>
<25>
<25>
WAIT (Input)
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
105
µPD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
IORD low-level width
<32>
tWRDL
(2 + wRH + wDA + wF + w) T – 10
ns
IORD high-level width
<33>
tWRDH
T – 10
ns
IORD ↑ delay time from address, CSn
<34>
tDARD
0.5T – 10
ns
Address delay time from IORD ↑
<35>
tDRDA
(0.5 + i) T – 10
ns
Row address setup time
<56>
tASR
(0.5 + wRP) T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH) T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA + wF) T – 10
ns
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA + wF + w)
T – 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP) T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA + wF) T – 10
ns
Column address read time for RAS
<64>
tRAL
(2 + wCP + wDA + wF + w) T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA + wF) T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRP) T – 10
ns
CAS hold time
<67>
tCSH
(2 + wRH + wDA + wF + w) T – 10
ns
CAS precharge time
<71>
tCPN
(2 + wRP + wRH + w) T – 10
ns
RAS column address delay time
<76>
tRAD
(0.5 + wRH) T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH + w) T – 10
ns
CAS precharge time
<81>
tCP
(0.5 + wCP + w) T – 10
ns
High-speed page mode cycle time
<82>
tPC
(2 + wCP + wDA + wF + w) T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2.5 + wCP + wDA + w) T – 10
ns
WE hold time (from CAS ↓)
<85>
tWCH
(1 + wDA) T – 10
ns
WE read time (from RAS ↑)
<88>
tRWL
wCP = 0
(1.5 + wDA + w) T – 10
ns
WE read time (from CAS ↑)
<89>
tCWL
wCP = 0
(1 + wDA + w) T – 10
ns
WE pulse width
<92>
tWP
wCP = 0
(1 + wDA + w) T – 10
ns
RAS pulse width
<94>
tRASP
(2.5 + wRH + wDA + wF + w) T – 10
ns
Off-page
<101>
tWCS1
wCP = 0
(1 + wRH + wRP + w) T – 10
ns
On-page
<102>
tWCS2
wCP ≥ 1
wCPT – 10
ns
WE setup time
(to CAS ↓)
106
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRP: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: the number of idle states that are inserted when a write cycle follows a read cycle.
9. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
107
µPD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (2/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
CAS ↓ delay time from DMAAKm ↓
<105>
tDDACS
(1.5 + wRH + w) T – 10
ns
CAS ↓ delay time from IORD ↓
<106>
tDRDCS
(1 + wRH + w) T – 10
ns
IORD ↑ delay time from WE ↑
<107>
tDWERD
wF= 0
0
ns
wF= 1
T – 10
ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. m = 0 to 3
108
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (3/3)
TRPW
T1
TRHW
TW
T2
TDAW
T3
TCPW
TW
TO1 TDAW TO2
CLKOUT (Output)
<56>
A0 to A23 (Output)
<57>
<58>
Row address
<59>
Column address
Column address
<76>
<64>
<61>
<94>
<60>
RASn (Output)
<77>
<65>
<66>
<67>
<63>
<81>
UCAS (Output)
LCAS (Output)
<71>
<82>
<83>
RD (Output)
OE (Output)
<101>
<102>
<88>
<89>
<85>
WE (Output)
<92>
<105>
DMAAKm (Output)
IOWR (Output)
<106>
<107>
<35>
<34>
IORD (Output)
<32>
<25>
<33>
D0 to D15 (I/O)
Data
<24>
<24>
Data
<24>
<25>
<25>
WAIT (Input)
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
Preliminary Data Sheet U13995EJ1V0DS00
109
µPD703100-33, 703100-40, 703101-33, 703102-33
(i) CBR refresh timing
Parameter
RAS precharge time
Symbol
<61>
Condition
MIN.
tRP
MAX.
(1.5 + wRRW) T – 10
RAS pulse width
<62>
tRAS
(1.5 + wRCW
Note
CAS hold time
<108>
tCHR
(1.5 + wRCW
Note
ns
) T – 10
(3 + wRRW + wRCW
Unit
ns
) T – 10
ns
Note
ns
) T – 10
REFRQ pulse width
<109>
tWRFL
RAS precharge CAS hold time
<110>
tRPC
(0.5 + wRRW) T – 10
REFRQ active delay time
(from CLKOUT ↑)
<111>
tDKRF
2
10
ns
REFRQ inactive delay time
(from CLKOUT ↑)
<112>
tHKRF
2
10
ns
CAS setup time
<113>
tCSR
T – 10
ns
ns
Note At least one clock cycle is inserted by default for wRCW regardless of the settings of the RCW0 to RCW2 bits
of the RWC register.
Remarks 1. T = tCYK
2. wRRW: the number of waits due to the RRW0 and RRW1 bits of the RWC register.
3. wRCW: the number of waits due to the RCW0 to RCW2 bits of the RWC register.
TRRW
T1
T2
TRCWNote
TRCW
T3
TI
CLKOUT (Output)
<111>
<112>
<109>
REFRQ (Output)
<61>
<62>
RASn (Output)
<110>
<110>
<113>
<108>
UCAS (Output)
LCAS (Output)
Note This TRCW is always inserted regardless of the settings of the RCW0 to RCW2 bits of the RWC register.
Remarks 1. This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 2
2. n = 0 to 7
110
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(j) CBR self-refresh timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
REFRQ active delay time
(from CLKOUT ↑)
<111>
tDKRF
2
10
ns
REFRQ inactive delay time
(from CLKOUT ↑)
<112>
tHKRF
2
10
ns
CAS hold time
<114>
tCHS
−5
ns
RAS precharge time
<115>
tRPS
(1 + 2wSRW) T – 10
ns
Remarks 1. T = tCYK
2. wSRW: the number of waits due to the SRW0 to SRW2 bits of the RWC register.
TRRW
TH
TH
TH
TRCW
TH
TI
TSRW
TSRW
CLKOUT (Output)
<111>
<112>
REFRQ (Output)
<115>
RASn (Output)
<114>
UCAS (Output)
LCAS (Output)
Output signals
other than above
Remarks 1. This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 1
Number of waits due to the SRW0 to SRW2 bits of the RWC register (TSRW): 2
2. The broken lines indicate high impedance.
3. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
111
µPD703100-33, 703100-40, 703101-33, 703102-33
(7) DMAC timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
DMARQn setup time (to CLKOUT ↑)
<116>
tSDRK
15
ns
DMARQn hold time (from CLKOUT ↑)
<117>
tHKDR1
2
ns
<118>
tHKDR2
Until DMAAKn ↓
ns
DMAAKn output delay time
(from CLKOUT ↓)
<119>
tDKDA
2
10
ns
DMAAKn output hold time
(from CLKOUT ↓)
<120>
tHKDA
2
10
ns
TCn output delay time
(from CLKOUT ↓)
<121>
tDKTC
2
10
ns
TCn output hold time
(from CLKOUT ↓)
<122>
tHKTC
2
10
ns
Remark n = 0 to 3
CLKOUT (Output)
<117>
<116>
<118>
DMARQn (Input)
<116>
<119>
<120>
DMAAKn (Output)
<122>
<121>
TCn (Output)
Remark n = 0 to 3
112
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
Preliminary Data Sheet U13995EJ1V0DS00
113
µPD703100-33, 703100-40, 703101-33, 703102-33
(8) Bus hold timing (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
HLDRQ setup time (to CLKOUT ↑)
<123>
tSHRK
15
ns
HLDRQ hold time (from CLKOUT ↑)
<124>
tHKHR
2
ns
HLDAK delay time from CLKOUT ↓
<125>
tDKHA
2
HLDRQ high-level width
<126>
tWHQH
T + 17
ns
HLDAK low-level width
<127>
tWHAL
T–8
ns
Bus float delay time from CLKOUT ↓
<128>
tDKCF
Bus output delay time from HLDAK ↓
<129>
tDHAC
0
ns
HLDAK ↓ delay time from HLDRQ ↓
<130>
tDHQHA1
2.5T
ns
HLDAK ↑ delay time from HLDRQ ↑
<131>
tDHQHA2
0.5T
Remark T = tCYK
114
Preliminary Data Sheet U13995EJ1V0DS00
10
10
1.5T
ns
ns
ns
µPD703100-33, 703100-40, 703101-33, 703102-33
(8) Bus hold timing (2/2)
T1
T2
T3
TI
TH
TH
TH
TI
T1
CLKOUT (Output)
<123>
<124>
<123>
<123>
<124>
<123>
<126>
HLDRQ (Intput)
<125>
<125>
<130>
<131>
HLDAK (Output)
<127>
<128>
A0 to A23 (Output)
D0 to D15 (I/O)
Address
<129>
Undefined
Data
CSn/RASn (Output)
BCYST (Output)
RD (Output)
WE (Output)
UCAS (Output)
LCAS (Output)
WAIT (Input)
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 7
Preliminary Data Sheet U13995EJ1V0DS00
115
µPD703100-33, 703100-40, 703101-33, 703102-33
(9) Interrupt timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
NMI high-level width
<132>
tWNIH
500
ns
NMI low-level width
<133>
tWNIL
500
ns
INTPn high-level width
<134>
tWITH
4T + 10
ns
INTPn low-level width
<135>
tWITL
4T + 10
ns
Remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153
2. T = tCYK
<132>
<133>
<134>
<135>
NMI (Input)
INTPn (Input)
Remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153
(10) RPU timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
TI1n high-level width
<136>
tWTIH
3T + 18
ns
TI1n low-level width
<137>
tWTIL
3T + 18
ns
TCLR1n high-level width
<138>
tWTCH
3T + 18
ns
TCLR1n low-level width
<139>
tWTCL
3T + 18
ns
Remarks 1. n = 0 to 5
2. T = tCYK
<136>
<137>
<138>
<139>
TI1n (Input)
TCLR1n (Input)
Remark n = 0 to 5
116
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
(11) UART0, UART1 timing (clock-synchronized or master mode only)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle
<140>
tCYSK0
Output
250
ns
SCKn high-level width
<141>
tWSK0H
Output
0.5tCYSK0 – 20
ns
SCKn low-level width
<142>
tWSK0L
Output
0.5tCYSK0 – 20
ns
RXDn setup time (to SCKn ↑)
<143>
tSRXSK
30
ns
RXDn hold time (from SCKn ↑)
<144>
tHSKRX
0
ns
TXDn output delay time (from SCKn ↓)
<145>
tDSKTX
TXDn output hold time (from SCKn ↑)
<146>
tHSKTX
20
0.5tCYSK0 – 5
ns
ns
Remark n = 0, 1
<140>
<142>
<141>
SCKn (I/O)
<143>
<144>
Input data
RXDn (Input)
<145>
TXDn (Output)
<146>
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0, 1
Preliminary Data Sheet U13995EJ1V0DS00
117
µPD703100-33, 703100-40, 703101-33, 703102-33
(12) CSI0 to CSI3 timing
(a) Master mode
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle
<147>
tCYSK1
Output
100
ns
SCKn high-level width
<148>
tWSK1H
Output
0.5tCYSK1 – 20
ns
SCKn low-level width
<149>
tWSK1L
Output
0.5tCYSK1 – 20
ns
SIn setup time (to SCKn ↑)
<150>
tSSISK
30
ns
SIn hold time (from SCKn ↑)
<151>
tHSKSI
0
ns
SOn output delay time (from SCKn ↓)
<152>
tDSKSO
SOn output hold time (from SCKn ↑)
<153>
tHSKSO
20
0.5tCYSK1 – 5
ns
ns
Remark n = 0 to 3
(b) Slave mode
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle
<147>
tCYSK1
Input
100
ns
SCKn high-level width
<148>
tWSK1H
Input
30
ns
SCKn low-level width
<149>
tWSK1L
Input
30
ns
SIn setup time (to SCKn ↑)
<150>
tSSISK
10
ns
SIn hold time (from SCKn ↑)
<151>
tHSKSI
10
ns
SOn output delay time (from SCKn ↓)
<152>
tDSKSO
SOn output hold time (from SCKn ↑)
<153>
tHSKSO
30
tWSK1H
Remark n = 0 to 3
<147>
<149>
<148>
SCKn (I/O)
<150>
<151>
Input data
Sln (Input)
<152>
SOn (Output)
<153>
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 3
118
Preliminary Data Sheet U13995EJ1V0DS00
ns
ns
µPD703100-33, 703100-40, 703101-33, 703102-33
A/D Converter Characteristics (TA = –40 to +70°°C ... µPD703100-40, TA = –40 to +85°°C ... µPD703100-33,
µPD703101-33, µPD703102-33, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V ±10%,
VSS = 0 V, HVDD – 0.5 V < AVDD < HVDD, output pin load capacitance: CL = 50
pF)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
10
Unit
Resolution
–
bit
Total error
–
±4
LSB
Quantization error
–
± 1/2
LSB
Conversion time
tCONV
5
µs
Sampling time
tSAMP
833
ns
Zero scale error
–
±2
LSB
Full scale error
–
±2
LSB
Nonlinearity error
–
±1
LSB
AVREF + 0.3
V
Analog input voltage
VIAN
Analog input resistance
RAN
AVREF input voltage
AVREF
AVREF input current
AVDD current
−0.3
2
AVREF = AVDD
4.5
MΩ
5.5
V
AIREF
1.6
mA
AIDD
6
mA
Preliminary Data Sheet U13995EJ1V0DS00
119
µPD703100-33, 703100-40, 703101-33, 703102-33
17. PACKAGE DRAWING
144 PIN PLASTIC LQFP (FINE PITCH) (20 20)
A
B
108
109
73
72
detail of lead end
C
D
S
R
Q
144
1
37
36
F
G
H
I
M
J
K
P
M
N
L
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
22.0±0.2
INCHES
0.866±0.008
B
20.0±0.2
0.787 +0.009
–0.008
C
20.0±0.2
0.787 +0.009
–0.008
D
22.0±0.2
0.866±0.008
F
1.25
0.049
G
1.25
0.049
H
0.22 +0.05
–0.04
0.009±0.002
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
K
1.0±0.2
0.039 +0.009
–0.008
L
0.5±0.2
0.020 +0.008
–0.009
M
0.145 +0.055
–0.045
0.006±0.002
N
0.10
0.004
P
1.4±0.1
0.055±0.004
Q
0.125±0.075
0.005±0.003
R
3° +7°
–3°
3° +7°
–3°
S
1.7 MAX.
0.067 MAX.
S144GJ-50-8EU-2
120
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
18. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 18-1. Surface Mounting Type Soldering Conditions
µPD703100GJ-40-8EU
µPD703100GJ-33-8EU
: 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
: 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
µPD703101GJ-33-xxx-8EU : 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
µPD703102GJ-33-xxx-8EU : 144-pin plastic LQFP (fine pitch) (20 × 20 mm)
Soldering Method
Soldering Conditions
Infrared reflow
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher), Count:
Note
two times or less, Exposure limit: 3 days (after that, prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row)
Recommended
Condition
Symbol
IR35-103-2
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Preliminary Data Sheet U13995EJ1V0DS00
121
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
122
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Related Documents
µPD70F3102-33 Data Sheet (U13844E)
µPD703100-A33, µPD703100-A40, µPD703101-A33, µPD703102-A33 Data Sheet (To be
prepared)
µPD70F3102-A33 Data Sheet (U13845E)
V850 Family Application Note Flash Memory Self-Programming Library (U13261E)
Reference Materials: Electrical Characteristics for Microcomputer (IEI-601
Note
)
Note This document number is that of Japanese version.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
V850E/MS1 Family and V850 are trademarks of NEC Corporation.
Preliminary Data Sheet U13995EJ1V0DS00
123
µPD703100-33, 703100-40, 703101-33, 703102-33
[MEMO]
124
Preliminary Data Sheet U13995EJ1V0DS00
µPD703100-33, 703100-40, 703101-33, 703102-33
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Preliminary Data Sheet U13995EJ1V0DS00
125
µPD703100-33, 703100-40, 703101-33,
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
Lisence not needed
: µPD703100-33, 703100-40
The customer must judge the need for lisence : µPD703101-33, 703102-33
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5