DATA SHEET MOS INTEGRATED CIRCUIT µPD9903 µPD9903 ANALOG SUBSCRIBER LINE LSI (DIGITAL CODEC) The µPD9903 is a digital CODEC that can be used in analog subscriber circuits such as private branch exchangers (PBXs) and switching equipment for central offices. It features three of the functions required for analog subscriber circuits: 2W/4W conversion, CODEC supervision, and subscriber line supervision. Use of the µPD9903 in combination with a BS-SLIC (µPC7073) can reduce the number of components required in analog subscriber circuits. FEATURES • Single-chip monolithic LSI (CMOS) • PCM CODEC → oversampling-type A/D and D/A converters • Programmable functions • Termination impedance • Hybrid balance network • Feed resistance • Feed current • PAD control • A-law and µ-law • Digital gain set function • Ring-Trip function • Single power supply (+5 V) • Low power consumption during standby mode: 20 mW (TYP.) ORDERING INFORMATION Part Number Package µPD9903GT 48-pin plastic shrink SOP (375 mil) The information in this document is subject to change without notice. Document No. S10897EJ3V0DS00 (3rd edition) Date Published June 1997 N Printed in Japan The mark shows major revised points. © 1996 µPD9903 PIN CONFIGURATION (Top View) 48-pin plastic shrink SOP (375 mil) ACOMIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 µ PD9903GT NC NC NC NC NC NC NC NC NC NC AVDD DVDD1 DVDD2 AUX/MODE BSY SUS RST EXS EXD HWR DCLK FS HWX TYPE : ANALOG COMMON VOLTAGE IN DCIN3 DCIN2 DCIN1 DCOUT1 DCOUT2 BBIN ASCN AGDT AIN AOUT ACOMOUT ACOMIN AGND SUB DGND1 DGND2 PD ALM BCUT RC1 RC2 RC3 RTIN0 RTIN1 DGND1, DGND2 : DIGITAL GROUND ACOM OUT : ANALOG COMMON VOLTAGE OUT DVDD1 , DVDD2 : DIGITAL POSITIVE POWER SUPPLY AGDT : ANALOG GROUND DETECTION SIGNAL IN EXD : EXPANSION PORT DATA AGND : ANALOG GROUND EXS : EXPANSION PORT SYNCHRONIZATION A IN : ANALOG SIGNAL IN FS : FRAME SYNCHRONOUS CLOCK IN ALM : ALARM OUT HWR : RECEIVE HIGHWAY DATA IN A OUT : ANALOG SIGNAL OUT HW X : TRANSMIT HIGHWAY DATA OUT ASCN : ANALOG LOOP DETECTION SIGNAL IN NC : NO CONNECTION AUX/MODE : EXTERNAL SIGNAL IN/MODE CONTROL SET PD : POWER DOWN CONTROL OUT AV DD : ANALOG POSITIVE POWER SUPPLY RC 1 - RC3 : RELAY CONTROL OUT BB IN : V BB VOLTAGE INFORMATION IN RST : RESET IN BCUT : BATTERY FEED CUT SIGNAL OUT RT IN0, RT IN1 : RING TRIP SIGNAL IN BSY : BUSY SIGNAL OUT SUB : SUB GROUND DC IN1 - DC IN3 : DC FEEDBACK CONTROL IN SUS : SUSPEND SIGNAL OUT DCLK : DATA CLOCK IN TYPE : TYPE SIGNAL OUT DC OUT1, DCOUT2 : DC FEEDBACK CONTROL OUT 2 µPD9903 BLOCK DIAGRAM RC1 RC2 RC3 DCIN1 ASCN COMP. COMP. COMP. AGDT SUS GDT Waveform shaping guard processing BSY SCN DCIN2 SUS DCIN3 Linear to A or m Channel filter + A/D AIN + HWX DCOUT1 DCOUT2 HZ Feed control A or µ to linear Channel filter + D/A AOUT HB HWR TYPE ACOMIN ACOMOUT Reference voltage BBIN FS Controller BCUT Ring-Trip Timing DCLK ALM PD AUX/MODE RST DVDD AVDD DGND AGND SUB EXS EXD RTIN1 RTIN0 3 µPD9903 CONTENTS 1. PIN FUNCTIONS ...................................................................................................................... 5 2. USE CAUTIONS ....................................................................................................................... 7 3. ELECTRICAL SPECIFICATIONS ........................................................................................... 8 3.1 Discrete unit Ratings ...................................................................................................................... 8 3.2 Combined Specifications with the µ PC7073 ............................................................................. 17 4. SYSTEM APPLICATION EXAMPLE USING THE µ PC7073 AND µ PD9903 ............. 21 5. PACKAGE DRAWING ............................................................................................................. 22 6. RECOMMENDED SOLDERING CONDITIONS ................................................................... 23 4 µPD9903 1. PIN FUNCTIONS Number 1-10 Pin Name I/O Function NC – Leave this pin open. 11 AVDD – +5 V power supply (analog) 12 DVDD1 – +5 V power supply (digital) 13 DVDD2 – +5 V power supply (digital) 14 AUX/MODE I External signaling input 15 BSY O BUSY LED driver output 16 SUS O SUS LED driver output 17 RST I Pin for reset input and power-on reset H: HWX valid, L: HWX output’s internal F/F clear status 18 EXS O SIPO sync signal output for expansion port Note 1 19 EXD O SIPO serial data output for expansion port Note 1 20 HWR I Reception highway input [PCM data (8-bit) + CTL data (8-bit)] 21 DCLK I Clock input (2.048 MHz) 22 FS I 8-kHz sync input 23 HWX O Transmission highway output [PCM data (8-bit) + SCN data (8-bit)] 24 TYPE O HWX data enable 25 RTIN1 I Ring-Trip signal input 2 26 RTIN0 I Ring-Trip signal input 1 27 RC3 O Relay control for network testing [to the µPC7073’s pin 22] 28 RC2 O Relay control for line testing [to the µPC7073’s pin 21] 29 RC1 O Relay control for ringer transmit [to the µPC7073’s pin 20] [to the µPC7073’s pin 19] Rising : Rising : Falling: Falling: HWR PCM data input start HWX PCM data output start HWR CTL data input start HWX SCN data output start 30 BCUT O High and wet control output 31 ALM O Control output for ground-fault/power line contact protection mode [to the µPC7073’s pin 18] 32 PD O Power-down control output 33 DGND2 – Digital ground 2 Note 2 34 DGND1 – Digital ground 1 Note 2 35 SUB – Substrate ground Note 2 36 AGND – Analog ground Note 2 37 ACOMIN I Signal ground input Note 3 Note 3 [to the µPC7073’s pin 17] [to the µPC7073’s pin 11] [to the µPC7073’s pin 11] 38 ACOMOUT O Signal ground output 39 AOUT O Analog signal output for receive side [to the µPC7073’s pin 10] 40 AIN I Analog signal input for transmit side [to the µPC7073’s pin 9] 41 AGDT I Tip-Ring sum current detection input [to the µPC7073’s pin 8] 42 ASCN I Tip-Ring difference current detection input [to the µPC7073’s pin 7] 43 BBIN I VBB voltage information input [to the µPC7073’s pin 6] Notes 1. SIPO: Serial In Parallel Out 2. Short AGND, DGND1, DGND2, and SUB directly under the IC and connect them to an analog ground. 3. Short ACOMIN and ACOMOUT directly under the IC. 5 µPD9903 Number 6 Pin Name I/O Function 44 DCOUT2 O DC feedback bias voltage output [to the µPC7073’s pin 5] 45 DCOUT1 O DC feedback control output [to the µPC7073’s pin 4] 46 DCIN1 I DC feedback control input 1 [to the µPC7073’s pin 3] 47 DCIN2 I DC feedback control input 2 [to the µPC7073’s pin 2] 48 DCIN3 I DC feedback control input 3 [to the µPC7073’s pin 1] µPD9903 2. USE CAUTIONS (1) Combined characteristics of the µPC9903 and µPD7073 • The µPD9903 is designed to be used in combination with the µPC7073. Therefore, the first half of the electrical specifications described below are ratings for the µPD9903 as a discrete unit while the second half are combined ratings with the µPC7073. • Subscriber circuit constants that are determined by factors such as termination impedance are configured to enable setting by external order parameters. Consequently, input of an order that is not suitable for the target impedance may result in failure to obtain the required characteristics. (2) Absolute maximum ratings Application of voltage or current in excess of the absolute maximum ratings may result in damage. Be especially cautious about surges, etc. (3) Load of by-pass capacitor Because the µ PC7073 and µ PD9903 use several internal high-frequency operational amplifiers, high power supply impedance can cause instability in these internal operational amplifiers (such as oscillation). To suppress such instability and eliminate power supply noise, connect by-pass capacitors (C ACOM = approximate 0.1 µ F) having superior high frequency characteristics as close as possible to the µ PC7073’s power supply pins (V BB and V CC) and the µ PD9903’s power supply pins (AVDD and DV DD). (4) Addition of ACOM pin connection capacitor The voltage of the ACOM pin between the µ PC7073 and µ PD9903 is the reference voltage of the signal source between the µ PC9903 and µ PC7073. Superposing of noise on this pin may have adverse effects on transmission characteristics. Therefore, make the wires between the ACOM pins of the two LSIs as short as possible, and connect capacitors (C ACOM = approximate 0.1 µ F) having superior high frequency characteristics as close as possible to the pins. 7 µPD9903 3. ELECTRICAL SPECIFICATIONS 3.1 Discrete unit Ratings Absolute maximum ratings (TA = +25 °C) Parameter Symbol Conditions Rating Units –0.3 to +7.0 V Power supply voltage VDD AVDD, DVDD1, DVDD2 Analog input voltage VAIN AIN, ASCN, AGDT, ACOMIN, BBIN, DCIN1, DCIN2, and DCIN3 pins –0.3 to VDD + 0.3 Digital input voltage VDIN HWR, DCLK, FS, RST, AUX/MODE, RTIN0, and RTIN1 pins –0.3 to VDD + 0.3 Applied voltage to analog output pin VAOUT AOUT, DCOUT1, DCOUT2, and ACOMOUT pins –0.3 to VDD + 0.3 Applied voltage to digital output pin VDOUT HWX, BSY, SUS, RC1, RC2, RC3, EXS, EXD, BCUT, ALM, PD, and TYPE pins –0.3 to VDD + 0.3 Power dissipation PT 500 mW Ambient operating temperature TA 0 to +70 ˚C Storage temperature Tstg –65 to +150 Caution If the absolute maximum rating for any of the above parameters is exceeded even momentarily, it may adversely affect the quality of this product. In other words, these absolute maximum ratings have been set to prevent physical damage to the product. Do not use the product in such a way as to exceed any of these ratings. Recommended operating conditions (TA = 0 to 70 °C, VDD = 5 V ± 5 %, GND = 0 V) (1) DC conditions Parameter Conditions MIN. TYP. MAX. Units Ambient operating temperature TA 0 25 70 ˚C Power supply voltage VDD 4.75 5.0 5.25 V Analog input voltage VAI ASCN, and AGDT pins Analog input driving resistance RLA1 ASCN, and AGDT pins Analog output load resistance RLOAD AOUT pin Analog output load capacitance CLOAD Low level input voltage High level input voltage 8 Symbol 0 VDD 20 kΩ 100 pF V 100 VIL1 FS, DCLK, HWR, and AUX/MODE pins 0 0.8 VIL2 RST, RTIN0, and RTIN1 pins 0 0.2 × VDD VIH1 FS, DCLK, HWR, and AUX/MODE pins 2.0 VDD VIH2 RST, RTIN0, and RTIN1 pins 0.8 × VDD VDD µPD9903 (2) AC conditions Parameter Symbol Conditions MIN. (= 1/tCY) ± 50 ppm TYP. MAX. 2048 Units Data clock frequency fDCLK kHz Data clock pulse width tDCLK Frame sync clock frequency fS High level frame sync pulse width tWHS tCY × 8 ns Low level frame sync pulse width tWLS tCY × 8 ns Clock rise time tR 30 ns Clock fall time tF 30 ns Float in sync timing tCSD1 100 ns 200 ± 50 ppm ns 8.0 kHz tCSD2 40 ns High level width of frame sync clock and data clock tWHSC 100 ns HWR set-up time tDSR Note 1 65 ns HWR hold time tDHR Note 1 120 ns Minimum width of reset pulse PWRST RST pin Note 2 10 µs Notes 1. During timing measurement, use 5 ns as the rise time and fall time for the digital input wave form and clock signal. 2. The µPD9903 is initialized when high level input is applied to the RST pin after applying low level input for several clock widths. (However, use of the RST pin is not guaranteed during low level input. Also, low level input alone does not initialize the µPD9903.) 9 µPD9903 DC Characteristics (TA = 0 to 70 °C, VDD = 5 V ± 0.25 V, VDG = VAG = 0 V, fDCLK = 2048 kHz, all output pins are unloaded) (1) Current consumption Parameter Symbol Conditions MIN. TYP. MAX. Units mA Circuit current IDD During normal mode 15 21 Power-down circuit current IDDPD During power-down mode 46 6 TYP. MAX. Units +10 µA (2) Digital interface Parameter Symbol Conditions MIN. Digital input current IID 0 ≤ VDIN ≤ VDD for FS, DCLK, HWR, RTIN0, RTIN1, and RST pins –10 Digital input pull-up current IIL VDIN = 0 V for AUX/MODE pin –50 3-state leakage current IL 0 ≤ VDIN ≤ VDD for HWX pin –10 Low level output voltage VOL1 IOL = 3.4 mA for HWX pin 0.4 VOL2 IOL = 0.2 mA for RC1, RC2, RC3, BCUT, ALM, PD, EXS, and EXD pins 0.4 VOL3 IOL = 5 mA for BSY and SUS pins 1.1 VOH1 IOH = –0.6 mA for HWX and TYPE pins 2.4 VOH2 IOH = –2.0 mA for RC1, RC2, RC3, BCUT, ALM, PD, EXS, and EXD pins 2.4 VOH3 IOH = 0 mA for BSY and SUS pins COD f = 1 MHz, unmeasured pins returned to 0 V 15 CID f = 1 MHz, unmeasured pins returned to 0 V 10 High level output voltage Output capacitance of digital output pin Input capacitance of digital input pin –7 –0.5 +10 V VDD – 0.5 pF (3) AIN pin Parameter Symbol Input bias current IB Input resistance RIN Input capacitance CIN Conditions Input voltage: MIN. TYP. –10 MAX. +10 1 Units µA MΩ 10 pF MAX. Units +100 mV 50 Ω (4) AOUT pin Parameter Symbol Conditions Output offset voltage VOA HWR PCM data: zero PCM code, referenced to VACOM Output resistance ROUT I/O current: –100 to +100 µA 10 MIN. –100 TYP. µPD9903 (5) ASCN and AGDT output pins Parameter Symbol Input bias current IB Input resistance RIN Conditions Input voltage: 0 to VDD MIN. TYP. –10 MAX. Units +10 µA 1 MΩ (6) ACOMOUT pin Parameter Output voltage Symbol VACOM Conditions I/O current: –0.1 to +0.1 mA MIN. 2380 TYP. MAX. Units 2420 mV 11 µPD9903 AC characteristics (TA = 0 to 70 °C, VDD = 5 V ± 0.25 V, VDG = VAG = 0, fDCLK = 2048 kHz) Parameter MAX. Units HWX and TYPE pins, when FS is delayed longer than DCLK 170 ns tDZX2 HWX and TYPE pins, when DCLK is delayed longer than FS 170 ns Data delay time tDDX HWX pin 180 ns Data hold time tHZX HWX and TYPE pins 200 ns Delay time to EXS falling edge tDEXSf EXS pin 120 ns Delay time to EXS rising edge tDEXSr EXS pin 120 ns EXD data delay time tDEXD EXD pin 120 ns Signaling bit set-up delay tDSIG 2 µs Status bit set-up delay time tDST 2 µs LED driver set-up delay time tDLED 2 µs Delay time to rising edge tTHL 100 ns Delay time to falling edge tTLH 100 ns Transmit delay time to external bit tDAUX 125 µs Data enable delay time Symbol Conditions tDZX1 MIN. 30 TYP. time 12 BSY and SUS pins AUX pin µPD9903 Timing charts (1) PCM data transmission timing (HWX pin) (a) DCLK is later than FS tR tWHS tF FS tCY tCSD2 tR DCLK tDCLK 1 tF 2 8 tDCLK tDDX tDZX2 tHZX Hi-Z HWX (PCM data) MSB 2nd 7th LSB tHZX tDZX2 TYPE Hi-Z Hi-Level Hi-Z (b) FS is later than DCLK FS tCSD1 DCLK tWHSC 1 Hi-Z 2 8 tDZX1 HWX (PCM data) MSB 2nd 7th LSB tDZX1 TYPE Hi-Z Hi-Level Hi-Z 13 µPD9903 (2) SCN data transmission timing (HWX pin) (a) DCLK is later than FS tWLS tF tR FS tCY tCSD2 tR DCLK tDCLK 1 tF 2 8 tHZX tDCLK tDDX tDZX2 Hi-Z HWX (SCN data) MSB 2nd 7th LSB tHZX tDZX2 TYPE Hi-Z Hi-Level Hi-Z (b) FS is later than DCLK FS tCSD1 DCLK tWHSC 1 Hi-Z 2 8 tDZX1 HWX (SCN data) MSB 2nd 7th LSB tDZX1 TYPE 14 Hi-Z Hi-Level Hi-Z µPD9903 (3) PCM data reception timing (HWR pin) (a) DCLK is later than FS tR tWHS tF FS tCY tR tCSD2 1 DCLK tDSR tDCLK 2 8 Note MSB 9 tDCLK tR, tF tDHR HWR (PCM data) tF Note 2nd 7th Note Note 8th Note Don’t care (b) FS is later than DCLK FS tCSD1 tWHSC DCLK 1 2 8 9 15 µPD9903 (4) CTL data reception timing (HWR pin) (a) DCLK is later than FS tWLS tF tR FS tCY tR tCSD2 tDCLK 1 DCLK tDSR 2 8 Note MSB tR, tF Note 2nd 7th Note 8th Note Don’t care (b) FS is later than DCLK FS tCSD1 tWHSC DCLK 16 1 9 tDCLK tDHR HWR (CTL data) tF 2 8 Note µPD9903 3.2 Combined Specifications with the µPC7073 DC characteristics µ PC7073 (V BB = –42 to –58 V, V CC = 5 V ± 0.25 V, TA = 0 to 70 ˚C, 18 ≤ I L ≤ I LMAX (mA)) µ PD9903 (T A = 0 to 70 ˚C, V DD = 5 V ± 0.25 V, V DG = V AG = 0 V, fDCLK = 2048 kHz) Parameter DC feed resistance Minimum loop current Maximum current setting Symbol RBF ILMIN ILMAX MIN. TYP. MAX. Units 200 Ω feed Conditions 180 200 220 Ω 400 Ω feed 360 400 440 VBB = –51 V 200 Ω feed 21.7 22.2 22.6 RL = 1900 Ω 400 Ω feed 18.2 18.8 19.3 ILMAX = 76 mA setting 200 Ω feed 70 76 82 400 Ω feed 50 55 60 ILMAX = 45 mA setting 40 45 50 ILMAX = 35 mA setting 31 35 39 value Pin voltage during on-hook Voltage between lines VTS Normal on-hook, between Tip and GND, VBB = –48 V 2.25 2.55 2.85 VRS Normal on-hook, between Ring and VBB, VBB = –48 V 3.05 3.35 3.65 VTS On-hook transmission, between Tip and GND, VBB = –48 V 2.25 2.55 2.85 VRS On-hook transmission, between Ring and VBB, VBB = –48 V 3.05 3.35 3.65 VTS VBB = –48 V VBB – 7.0 VBB – 5.9 VBB – 5.0 mA mA V V during on-hook Supervisory control – VBB abnormal voltage VBBF 32 35 38 V 17 µPD9903 ParameterNote Loop detection operating Symbol RON1 resistance (during normal transmission) Conditions RON2 RON3 2100 Includes termination resistance Includes termination resistance 3900 3500 200 Ω feed 400 Ω feed 1900 1500 Ω 2960 2560 Ω 5.2 kΩ ILMAX = 45/76 mA 340 Ω ILMAX = 35 mA 480 2840 2440 200 Ω feed 400 Ω feed Loop release operating 200 Ω feed 4540 resistance 400 Ω feed 4140 Ground detection 1 (C/O) operating resistance RON4 Includes termination resistance Ground detection 1 (C/O) non-operating resistance Ground-fault/power line contact detection operating resistance 20 RON6 Includes termination resistance Off-hook state Ground-fault/power line Includes termination contact detection non- resistance operating resistance Ground-fault/power line contact release nonoperating resistance RON7 18 ILMAX = 45/76 mA 870 ILMAX = 35 mA 1130 Includes termination resistance Ground-fault/power line contact release operating resistance Note Ω 2500 400 Ω feed 200 Ω feed 400 Ω feed resistance Units 200 Ω feed Loop detection non-operating resistance (during on hook transmission) Loop release non-operating MAX. resistance 200 Ω feed 400 Ω feed resistance (during on hook transmission) TYP. Includes termination Loop detection non-operating resistance (during normal transmission) Loop detection operating MIN. The above values are resistance-converted values. Ω 1.4 10 kΩ µPD9903 Transmission characteristics µPC7073 (VBB = –42 to –58 V, VCC = 5 V ± 0.25 V, TA = 0 to 70 ˚C, 18 ≤ IL ≤ ILMAX (mA)) µPD9903 (TA = 0 to 70 ˚C, VDD = 5 V ± 0.25 V, VDG= VAG = 0 V, fDCLK = 2048 kHz) Parameter Insertion loss Transfer loss frequency characteristics Gain tracking (tone method) Return loss Symbol IL Conditions MIN. TYP. MAX. Units A-D input signal 0 dBm0 1 kHz –0.45 0.0 +0.45 dB D-A input signal 0 dBm0 1 kHz –0.45 0.0 +0.45 FRX A-D Reference input signal 1015 Hz 0 dBm0 60 200 300 400 to 3000 3200 3400 Hz Hz Hz Hz Hz Hz 24.0 0.6 –0.15 –0.15 –0.15 0.2 – 2.0 +0.21 +0.15 +0.65 0.8 FRR D-A Reference input signal 1015 Hz 0 dBm0 60 200 300 400 to 3000 3200 3400 Hz Hz Hz Hz Hz Hz 0.2 0.1 –0.15 –0.15 –0.15 0.2 4.0 1.0 +0.25 +0.15 +0.65 0.8 GTX A-D Reference input signal –10 dBm0 f = 700 to 1100 Hz +3 to –40 dBm0 –50 dBm0 –55 dBm0 –0.2 –0.5 –1.0 +0.2 +0.5 +1.0 GTR D-A Reference input signal –10 dBm0 f = 700 to 1100 Hz +3 to –40 dBm0 –50 dBm0 –55 dBm0 –0.2 –0.4 –0.8 +0.2 +0.4 +0.8 RL Input signal 0 dBm0 300 Hz 500 to 2000 Hz 16 20 ZT = 600 Ω + 2.16 µF 2000 to 3400 Hz 16 300 Hz 500 to 2500 Hz 3400 Hz 18 22 18 dB dB Echo attenuation TBRL Input signal 0 dBm0 ZT = 600 Ω + 2.16 µF Transmit channel total power distortion factor (tone method) SDX A-D Input signal f = 700 to 1100 Hz +3 to –30 dBm0 –40 dBm0 –45 dBm0 36 30 25 SD R D-A Input signal f = 700 to 1100 Hz +3 to –30 dBm0 –40 dBm0 –45 dBm0 36 30 25 dB dB dB 19 µPD9903 Parameter Symbol Conditions MIN. Absolute delay characteristics DA A-A Input signal 0 dBm0 Absolute delay distortion frequency characteristics DO A-A Intermodulation (2 Tone) IMD A-D Input signal f1, f2: 300 to 3400 Hz –4 to –21 dBm0 Measurement signal: 2 × f1 – f2 level (2 × f1 – f2) vs level (f1, f2) 44.0 D-A Input signal f1, f2: 300 to 3400 Hz –4 to –21 dBm0 Measurement signal: 2 × f1 – f2 level (2 × f1 – f2) vs level (f1, f2) 44.0 500 Hz 600 HZ 1000 to 2600 Hz 2800 Hz Single frequency noise NSF D-A PAD level set at 0 dB Measurement signal up to f = 256 kHz Deviation in gain setting for transmission channel ∆DGSX A-D Difference from reference set value Setting value: +7.5 to +3.0 dB Deviation in gain setting for reception chanel ∆DGSR +3.0 to –3.5 dB D-A Difference from reference set value Setting value: 0.0 to –5.0 dB –5.0 to –8.5 dB Idle circuit noise IDN24 IDN42 2W-4W 4W-2W TYP. MAX. Units 540 µs 1400 700 200 1400 dB –54 dB –0.2 +0.2 –0.1 +0.1 –0.1 +0.1 –0.2 +0.2 A-law Psophometric weighted –67 dBm0p µ-law 23 dBrnc0 A-law Psophometric weighted –76 dBm0p µ-law 14 dBrnc0 C message weighted C message weighted Line to ground balance attenuation LCL RF = 50 Ω Relative accuracy = 0.5 % AC induction noise LFI IL = 0 mA VIN = 6 Vrms 43 IL = 20 mA VIN = 15 Vrms 20 resistance 20 dBm0 f = 300 to 600 Hz f = 600 to 3400 Hz 42 48 dB dBrnc 4. 37 TB 38 Q1 RFT TS RTE 50 Ω Z1(0.5 %, 1 W) D2 D1 24 40 3.6 kΩ (1 %, 1 W) 42 TEST0 RRE D4 32 3.6 kΩ (1 %, 1 W) 50 Ω (0.5 %, 1 W) Q4 T2 44 45 TE TEF TS RS REF RE RB µPC7073 (BS-LSI) 23 47 31 15 46 36 33 34 TEST1 TEST2 TEST3 G CPSR 0.1 µF + (100 V) 0.68 µF (50 V) – + + CDC – 0.68 µF (10 V) Ring-Trip detector VDD (+5 V) BSY 2 kΩ RPULL 23 24 22 21 20 19 18 17 14 HWX TYPE FS DCLK HWR EXD EXS RST AUX/MODE 21 µPD9903 CR VBB (–48 V) CVBB – SUS TX BIAS RX DCOUT3 DCOUT2 DCOUT1 DCIN1 DCIN2 BCUT ALM PD RC1 RC2 RC3 BBOUT ASCN AGDT DVDD1 ACOM VBB TTXIN GND2 GND1 CPSR CDC OPIN+ OPIN– Z2 RS D3 RFR 29 RTIN0 RTIN1 R 27 + T1 T2 AVDD DVDD2 VCC RY1 48 25 T1 RY3 R RY2 1 µF + (6 V) – CVDD CCOM – + RSUS RBSY 0.1 µF 0.1 µF 1 kΩ 1 kΩ (5 V) (6 V) 11 12 13 16 15 11 37 CAC 38 ACOMIN 350.68 µ F (50 V)40 ACOMOUT AIN 9– 39 10 HWX AOUT 48 1 CDIN3 TYPE 47 2 CDIN2 FS 46 3 CDIN1 45 4 DCLK DCOUT1 µ PC9903 44 5 DCOUT2 HWR 30 19 (HCS-LSI) BCUT EXD 31 18 ALM 32 17 EXS PD 29 20 RC1 RST 28 21 RC2 AUX/MODE 27 22 RC3 43 6 BBIN 42 7 ASCN 41 AGDT 8 + CGDT 36 35 34 33 26 25 – 0.68 µ F (10 V) AGND SUB DGND1 DGND2 CVCC SYSTEM APPLICATION EXAMPLE USING THE µPC7073 AND µPD9903 VCC (+5 V) µPD9903 5. PACKAGE DRAWING 48 PIN PLASTIC SHRINK SOP (375 mil) 48 25 3°+7° –3° detail of lead end 1 24 A G H I K F J N E C D M M L B P48GT-65-375B-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 22 ITEM MILLIMETERS INCHES A 16.21 MAX. 0.639 MAX. B 0.63 MAX. 0.025 MAX. C 0.65 (T.P.) 0.026 (T.P.) D 0.30 ± 0.10 0.012+0.004 –0.005 E 0.125 ± 0.075 0.005 ± 0.003 F 2.0 MAX. 0.079 MAX. G 1.7 ± 0.1 0.067 ± 0.004 H 10.0 ± 0.3 0.394 +0.012 –0.013 I 8.0 ± 0.2 0.315 ± 0.008 J 1.0 ± 0.2 0.039+0.009 –0.008 K 0.15+0.10 –0.05 0.006+0.004 –0.002 L 0.5 ± 0.2 0.020+0.008 –0.009 M 0.10 0.004 N 0.10 0.004 µPD9903 6. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, please contact your NEC sales representative. SURFACE MOUNT TYPE µPC9903GT: 48-pin plastic shrink SOP (375 mil) Soldering Method Soldering Conditions Infrared ray reflow Package peak temperature: 235 ˚C Reflow time: 30 sec. max. (210 ˚C or above) Number of times: 1 time Partial heating method Pin temperature: 300 ˚C max. Heat time: 3 sec. max. (per each side of the device) Recommended Condition Symbol IR35-00-1 – 23 µPD9903 [MEMO] 24 µPD9903 [MEMO] 25 µPD9903 [MEMO] 26 µPD9903 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 27 µPD9903 [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5