PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD9611 FOUR-CHANNEL PCM CODEC The µPD9611 incorporates 4-channel A-law/µ-law PCM CODECs compliant with ITU-T Recommendation G.711/ G.714 and is suitable for applications such as PBX analog subscriber line circuits. Its gain setting circuit allows transmit/receive gain to be set for 4 channels independently by externally inputting digital signals. FEATURES • • • • • Single-chip CMOS monolithic LSI ITU-T Recommendation G.711/G.714 compliant Four-channel PCM CODECs integrated on a single chip Compatible with A-law and µ-law Digital gain setting for each channel • Transmit : +7.5 to –8.0 dB (0.5 dB step) • Receive : 0 to –15.5 dB (0.5 dB step) • • • • • Data transfer system: Transmit/receive synchronization Data rate: 2048 kHz +5 V single power supply Power down function for each channel Low power consumption ORDERING INFORMATION Part Number Package µPD9611GT 48-pin shrink SOP (375 mil) The information in this document is subject to change without notice. Document No. S11018EJ2V0DS00 (2nd edition) Date Published October 1996 P Printed in Japan © 1996 µPD9611 PIN CONFIGURATION (Top View) 48-pin shrink SOP (375 mil) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AIN4 AOUT4 NC AIN3 AOUT3 NC ACOMIN3 ACOMOUT3 ACOMIN4 ACOMOUT4 AGND1 AGND2 AGND3 AGND4 SUBGND DGND NC NC NC RST LAW SPDATA SPSYNC SPCLK DX : Transmit PCM data out ACOM OUT1-ACOM OUT 4 : Analog common voltage out FSC : Frame synchronous clock in AGND1-AGND4 : Analog ground LAW : A-law/ µ -law control in A IN1-A IN4 : Analog signal in NC : No connection A OUT1-A OUT4 : Analog signal out PD1-PD4 : Power down control AV DD1-AV DD 4 : Analog power supply RST : Reset in DCLK : Data clock in SPCLK : Serial port data clock in DGND : Digital ground SPDATA : Serial port data in DR : Receive PCM data in SPSYNC : Serial port synchronous clock in DV DD : Digital power supply SUBGND : Sub ground ACOM IN1-ACOM IN4 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 µPD9611GT AIN1 AOUT1 NC AIN2 AOUT2 NC ACOMIN1 ACOMOUT1 ACOMIN2 ACOMOUT2 AVDD1 AVDD2 AVDD3 AVDD4 DVDD NC PD1 PD2 PD3 PD4 FSC DCLK DX DR : Analog common voltage in µPD9611 BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD4 DVDD CH1 AIN1 A/D AOUT1 D/A APD1 DSP Channel FiIter ACOMIN1 CH2 AIN2 AOUT2 APD2 ACOMIN2 CH3 AIN3 AOUT3 DX APD3 DR ACOMIN3 RST SPSYNC CH4 AIN4 AOUT4 APD4 SPCLK I/O Linear ↔ A, µ DGS MUX, DEMUX ACOMIN4 ACOMIN1 SPDATA LAW APD1 PD1 APD2 PD2 APD3 PD3 APD4 PD4 ACOMOUT1 ACOMIN2 ACOMOUT2 Voltage Reference ACOMIN3 FSC Clock Generator ACOMOUT3 DCLK ACOMIN4 ACOMOUT4 AGND1 AGND2 AGND3 AGND4 DGND SUBGND 3 µPD9611 1. PIN DESCRIPTION Pin No. 4 Symbol I/O Name and Function 1 A IN 1 I Transmit analog input pin for channel 1 When not used, connect to ACOMOUT 1 pin. 2 A OUT1 O Receive analog output pin for channel 1 3 NC – Leave this pin open. 4 A IN 2 I Receive analog input pin for channel 2 When not used, connect to ACOMOUT 1 pin. 5 A OUT2 O Transmit analog output pin for channel 2 6 NC – Leave this pin open. 7 ACOMIN 1 I Signal reference voltage input for channel 1 8 ACOMOUT 1 O Signal reference voltage output for channel 1 9 ACOMIN 2 I Signal reference voltage input for channel 2 10 ACOMOUT 2 O Signal reference voltage output for channel 2 11 AV DD 1 – Analog power supply pin for channel 1 +5 ± 0.25 V 12 AV DD 2 – Analog power supply pin for channel 2 +5 ± 0.25 V 13 AV DD 3 – Analog power supply pin for channel 3 +5 ± 0.25 V 14 AV DD 4 – Analog power supply pin for channel 4 +5 ± 0.25 V 15 DV DD – Digital power supply pin +5 ± 0.25 V 16 NC – Leave this pin open. 17 PD1 I Power-down control input pin for channel 1 Channel 1 enters power-down mode when this signal is low level. The output of D X pin for channel 1 becomes high-impedance and AOUT 1 becomes signal reference voltage in the power-down mode. 18 PD2 I Power-down control input pin for channel 2 Channel 2 enters power-down mode when this signal is low level. The output of D X pin for channel 2 becomes high-impedance and AOUT 2 becomes signal reference voltage in the power-down mode. 19 PD3 I Power-down control input pin for channel 3 Channel 3 enters power-down mode when this signal is low level. The output of D X pin for channel 3 becomes high-impedance and AOUT 3 becomes signal reference voltage in the power-down mode. 20 PD4 I Power-down control input pin for channel 4 Channel 4 enters power-down mode when this signal is low level. The output of D X pin for channel 4 becomes high-impedance and AOUT 4 becomes signal reference voltage in the power-down mode. 21 FSC I Frame synchronous clock input pin (8 kHz) 22 DCLK I Data clock input pin (2048 kHz) 23 DX O Transmit PCM data output pin This pin outputs PCM data for channel 1 to 4 in synchronization with rising edges of DCLK after rising edges of FSC. It becomes high-impedance for other timings. 24 DR I Receive PCM data input pin This pin inputs PCM data for channel 1 to 4 in synchronization with falling edges of DCLK after rising edges of FSC. 25 SP CLK I Setting data clock input pin 26 SP SYNC I Setting synchronous clock input pin 27 SP DATA I Setting data input pin µPD9611 Pin No. Symbol I/O Name and Function 28 LAW I A-law/µ -law select pin in common to four channels L: A-law, H: µ -law 29 RST – Reset input, power-on reset pin H: normal operation L : internal registers are in the default status. 30-32 NC – Leave this pin open. 33 DGND – Digital ground pin 34 SUBGND – Substrate ground pin 35 AGND4 – Analog ground pin for channel 4 36 AGND3 – Analog ground pin for channel 3 37 AGND2 – Analog ground pin for channel 2 38 AGND1 – Analog ground pin for channel 1 39 ACOMOUT 4 O Signal reference voltage output for channel 4 40 ACOMIN 4 I Signal reference voltage input for channel 4 41 ACOMOUT 3 O Signal reference voltage output for channel 3 42 ACOMIN 3 I Signal reference voltage input for channel 3 43 NC – Leave this pin open. 44 A OUT3 O Receive analog output pin for channel 3 45 A IN 3 I Transmit analog input pin for channel 3 When not used, connect to ACOMOUT 1 pin. 46 NC – Leave this pin open. 47 A OUT4 O Receive analog output pin for channel 4 48 A IN 4 I Transmit analog input pin for channel 4 When not used, connect to ACOMOUT 1 pin. 5 µPD9611 2. CAUTIONS ON USE (1) Absolute maximum ratings Application of voltage or current in excess of the absolute maximum ratings to the µ PD9611 may result in damage due to latch up, etc. Be especially cautions about power supply noise, etc. (2) Wiring pattern The design of the ground pattern is extremely important for operating the µ PD9611 with high precision. Connect the analog ground pins (AGND1 to AGND4), digital ground pin (DGND) and substrate ground pin (SUBGND) close to the IC pins, and connect to a wide analog ground line on the board. (3) Addition of bypass capacitors for power supply pins Because the µ PD9611 uses many internal high-frequency operational amplifiers, high power supply impedance can cause instability (such as oscillation) in these internal operational amplifiers. To suppress such instability and eliminate power supply noise, connect all power supply pins (AVDD 1 to AV DD4, DV DD) close to the IC pins, and put bypass capacitors (CVDD = approximately 0.1 µ F) having superior high-frequency characteristics very close to the pins. (4) Addition of bypass capacitors for ACOM pins The µ PD9611 incorporates references voltages for signal sources. Superposing of noise on these reference voltages may have adverse effects on transmission characteristics, etc. Therefore, connect the ACOM OUT pin and ACOMIN pin close to the IC pins, and put bypass capacitors (C ACOM = approximately 0.1 µ F) having superior high-frequency characteristics very close to the pins. (5) Control or SPDATA pin on reset When inputting the setting data from the SP DATA pin after the µ PD9611 is reset, first input the following patterns to reset to 0 the couter used to fetch data from the SPDATA pin. 1 clocks or more 16 clocks or more RST SPCLK SPSYNC SPDATA After ther RST pin has been set to the high level, input 1 clock or more to the SPCLK pin, set the SP SYNC pin to the high level and input 16 clocks more to the SP CLK pin. During this operation, the SPDATA pin is held at the low level. Afterwards, input the setting data. 6 µPD9611 3. GENERAL OPERATION (1) PCM data transfer In the transmit section, if FSC pin is set to the high level in synchronization with the rising edge (↑) of the data clock applied to the DCLK pin, the D X pin becomes active and sign bit data (MSB) of channel 1 is output. The following data of 7 bits is clocked out in synchronization with the rising edge (↑) of each data clock. Sign bit data (MSB) of channel 2 is output in synchronization with the rising edge (↑) of the 9th data clock. In the same manner, each data up to channel 4 is output and the rising edge (↑) of the 33rd data clock then sets the DX pin to high-impedance state. Similarly, in the receive section, if the FSC pin is set to the high level in synchronization with the rising edge (↑) of the data clock applied to the DCLK pin, data of DR pin is latched by the falling edges (↓) of the data clock and consecutively clocked in. (2) Power down control The µ PD9611 has the following two methods for power down control and is able to control power-down independently for each channel. • Sets pins PD1 to PD4 to high or low level. • Inputs 8-bit setting data from SPDATA pin (see (5) Control of SP DATA pin). Internal data is the logical sum of PD1 to PD4 pin state and 8-bit setting data input. If the internal data is 0, the channel enters the power-down state. If the internal data is 1, the channel enters the power-up state. In the power down state, PCM data in the channel goes to high-impedance state and analog output becomes the signal reference voltage level. 8-Bit Setting Data (Channel 1) PD1 Pin Internal Data 0 0 0 1 0 1 0 1 1 1 1 1 Remarks 1. 0: Power down, 1: Power up 2. The settings are the same for channel 2 to channel 4. 7 µPD9611 (3) A-law/µ-law control The µ PD9611 has the following two methods for A-law/µ -law control. • Sets LAW pin to high or low level. • Inputs 8-bit setting data from SPDATA pin (see (5) Control of SP DATA pin). Internal data is the logical sum of LAW pin state and 8-bit setting data input. If the internal data is 0, the µ PD9611 enters A-law mode. If the internal data is 1, the µ PD9611 enters µ -law mode. 8-Bit Setting Data LAW Pin Internal Data 0 0 0 1 0 1 0 1 1 1 1 1 Remark 0: A-law, 1: µ -law (4) Gain Setting control for transmit/receive The µ PD9611 can control gain settings independently for the transmit/receive by inputting 8-bit setting data (see (5) Control of SP DATA pin) from the SPDATA pin for four channels. Gain can be set from +7.5 to –8.0 dB for the transmit and +0.0 dB t o –15.5 dB for the receive in 0.5 dB steps. 8-bit setting data input from SP DATA pin specifies the channel set in the first 8 bits, and performs selection of transmit/receive and gain setting in the second 8 bits. 8 µPD9611 (5) Control of SPDATA pin If SP SYNC pin is set to the high level in synchronization with the rising edge (↑) of the data clock applied to the SP CLK pin, data of the SPDATA pin is latched by the falling edge (↓) of the data clock and consecutively fetched in. After the 8-bit data has been fetched, the setting operation is performed according to the data. This setting operation is performed during the 8 clocks after fetching the data and the next data is valid at the 17th clock. Therefore, when setting 1 word (8 bits) of data, input 17 clocks or more to the SPCLK pin. SPSYNC SPCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Don’t care SPDATA Data fetch Setting operation Setting completed (The next data is valid.) Ensure that 17 clocks or more are input to the SPCLK pin between the rising of SPSYNC and the rising of the next SP SYNC . SPSYNC SPCLK 17 clocks or more 9 µPD9611 • A/ µ -law, power down control D7 D6 D5 D4 D3 D2 D1 D0 1 0 – A/µ PD1 PD2 PD3 PD4 0/1 Power down/power up for channel 4 Note 1 0/1 Power down/power up for channel 3 Note 1 0/1 Power down/power up for channel 2 Note 1 0/1 Power down/power up for channel 1Note 1 0/1 Setting of A-law/µ -lawNote 2 Notes 1. 2. – Don’t care 0 Identification code 1 Identification code Default setting is power down mode. Default setting is A-law mode. • Transmit/receive gain setting control (1st word) D7 D6 D5 D4 D3 D2 D1 D0 0 1 – – ch1 ch2 ch3 ch4 0/1 Gain non-setting/setting for channel 4 0/1 Gain non-setting/setting for channel 3 0/1 Gain non-setting/setting for channel 2 0/1 Gain non-setting/setting for channel 1 – Don’t care – Don’t care 1 Identification code 0 Identification code Transmit/receive gain setting control (2nd word) D7 D6 D5 1 1 X/R D4 D3 D2 D1 D0 Setting data 0/1 Gain setting 0/1 Gain setting 0/1 Gain setting 0/1 Gain setting 0/1 Gain setting 0/1 Transmit/receive setting 10 1 Identification code 1 Identification code µPD9611 Table of Gain Setting Codes (1/2) Setting Item Setting Level Gain setting for transmit +7.5 dB 1st Word 2nd Word D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 – – ch1 ch2 ch3 ch4 1 1 0 1 0 0 0 0 +7.0 dB 1 1 0 1 0 0 0 1 +6.5 dB 1 1 0 1 0 0 1 0 +6.0 dB 1 1 0 1 0 0 1 1 +5.5 dB 1 1 0 1 0 1 0 0 +5.0 dB 1 1 0 1 0 1 0 1 +4.5 dB 1 1 0 1 0 1 1 0 +4.0 dB 1 1 0 1 0 1 1 1 +3.5 dB 1 1 0 1 1 0 0 0 +3.0 dB 1 1 0 1 1 0 0 1 +2.5 dB 1 1 0 1 1 0 1 0 +2.0 dB 1 1 0 1 1 0 1 1 +1.5 dB 1 1 0 1 1 1 0 0 +1.0 dB 1 1 0 1 1 1 0 1 +0.5 dB 1 1 0 1 1 1 1 0 0.0 dB Note 1 1 0 1 1 1 1 1 –0.5 dB 1 1 0 0 0 0 0 0 –1.0 dB 1 1 0 0 0 0 0 1 –1.5 dB 1 1 0 0 0 0 1 0 –2.0 dB 1 1 0 0 0 0 1 1 –2.5 dB 1 1 0 0 0 1 0 0 –3.0 dB 1 1 0 0 0 1 0 1 –3.5 dB 1 1 0 0 0 1 1 0 –4.0 dB 1 1 0 0 0 1 1 1 –4.5 dB 1 1 0 0 1 0 0 0 –5.0 dB 1 1 0 0 1 0 0 1 –5.5 dB 1 1 0 0 1 0 1 0 –6.0 dB 1 1 0 0 1 0 1 1 –6.5 dB 1 1 0 0 1 1 0 0 –7.0 dB 1 1 0 0 1 1 0 1 –7.5 dB 1 1 0 0 1 1 1 0 –8.0 dB 1 1 0 0 1 1 1 1 Note Default setting 11 µPD9611 (2/2) Setting Item Setting Gain setting for receive 0.0 dB Note Level Note 12 Default setting 1st Word 2nd Word D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 – – ch1 ch2 ch3 ch4 1 1 1 1 1 1 1 1 –0.5 dB 1 1 1 1 1 1 1 0 –1.0 dB 1 1 1 1 1 1 0 1 –1.5 dB 1 1 1 1 1 1 0 0 –2.0 dB 1 1 1 1 1 0 1 1 –2.5 dB 1 1 1 1 1 0 1 0 –3.0 dB 1 1 1 1 1 0 0 1 –3.5 dB 1 1 1 1 1 0 0 0 –4.0 dB 1 1 1 1 0 1 1 1 –4.5 dB 1 1 1 1 0 1 1 0 –5.0 dB 1 1 1 1 0 1 0 1 –5.5 dB 1 1 1 1 0 1 0 0 –6.0 dB 1 1 1 1 0 0 1 1 –6.5 dB 1 1 1 1 0 0 1 0 –7.0 dB 1 1 1 1 0 0 0 1 –7.5 dB 1 1 1 1 0 0 0 0 –8.0 dB 1 1 1 0 1 1 1 1 –8.5 dB 1 1 1 0 1 1 1 0 –9.0 dB 1 1 1 0 1 1 0 1 –9.5 dB 1 1 1 0 1 1 0 0 –10.0 dB 1 1 1 0 1 0 1 1 –10.5 dB 1 1 1 0 1 0 1 0 –11.0 dB 1 1 1 0 1 0 0 1 –11.5 dB 1 1 1 0 1 0 0 0 –12.0 dB 1 1 1 0 0 1 1 1 –12.5 dB 1 1 1 0 0 1 1 0 –13.0 dB 1 1 1 0 0 1 0 1 –13.5 dB 1 1 1 0 0 1 0 0 –14.0 dB 1 1 1 0 0 0 1 1 –14.5 dB 1 1 1 0 0 0 1 0 –15.0 dB 1 1 1 0 0 0 0 1 –15.5 dB 1 1 1 0 0 0 0 0 µPD9611 Gain setting control is set by inputting 8-bit data fo the 1st word first and inputting 8-bit data of the 2nd word in synchronization with the next rising edge of SPSYNC . However, if data other than the identification code of the 2nd word is input after the input of the 1st word, the contents of the 1st word are ignored. (i) When gain setting control is valid SPCLK SPSYNC SPDATA 1 0 0 0 1 1 1 1 A/µ -law, power down control (valid) 0 1 0 0 1 1 1 1 Gain setting control (1st word) (valid) 1 1 0 1 1 1 1 1 Gain setting control (2nd word) (valid) (ii) When gain setting control is invalid –1 SPCLK SPSYNC SPDATA 0 1 0 0 1 1 1 1 Gain setting control (1st word) (invalid) 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 A/µ -law, power down control (valid) Gain setting control (2nd word) (invalid) Remark Because A/ µ -law, power down control is input after input of gain setting control (1st word), gain setting control (1st word) becomes invalid and gain setting control (2nd word) also becomes invalid. (iii) When gain setting control is invalid –2 SPCLK SPSYNC SPDATA 1 1 0 1 1 1 1 1 Gain setting control (2nd word) (invalid) 0 1 0 0 1 1 1 1 Gain setting control (1st word) (invalid) 1 0 0 0 1 1 1 1 A/µ -law, power down control (valid) Remark Because gain setting control (2nd word) is input before gain setting control (1st word), gain setting control (1st word) becomes invalid. Then, because A/µ -law, power down control is input even if gain setting control (1st word) is input, gain setting control (1st word) becomes invalid. 13 µPD9611 4. ELECTRICAL SPECIFICATIONS (PRELIMINARY) ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Item Symbol Condition Rating Unit –0.3 to +7.0 V Supply voltage V DD AV DD1, AV DD 2, AV DD 3, AV DD 4, DV DD Analog input voltage V AIN A IN 1, A IN2, A IN 3, A IN4, ACOM IN1, ACOM IN 2, ACOM IN 3, ACOM IN 4 –0.3 to V DD +0.3 Digital input voltage V DIN D R, DCLR, FSC, LAW, PD1, PD2, PD3, PD4, SP CLK , SP SYNC, SP DATA, RST –0.3 to VDD +0.3 Voltage applied to analog output pin V AOUT A OUT1, A OUT2, A OUT 3, A OUT4, ACOM OUT1, ACOMOUT 2, ACOM OUT 3, ACOM OUT 4 –0.3 to V DD +0.3 Voltage applied to digital output pin V DOUT DX –0.3 to V DD +0.3 Power dissipation PT 500 mW Ambient operating temperature TA –20 to +85 °C Storage temperature T stg –65 to +150 Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATION CONDITIONS (TA = –20 to +85 °C, VDD = 5 V ± 5 %, GND = 0 V, fDCLK = 2048 kHz) (1) DC condition Item Symbol Condition MIN. TYP. MAX. Unit –20 +25 +85 °C 4.75 5.0 5.25 V Ambient operating temperature TA Supply voltage V DD AV DD1, AV DD 2, AV DD 3, AV DD 4, DV DD Analog input voltage V AI A IN1, A IN 2, AIN 3, AIN 4 (ACOM as reference) –1.0 Analog output load resistance R LOAD Analog output load capacitance C LOAD High level input voltage Low level input voltage 14 A OUT1, A OUT2, A OUT 3, A OUT4 +1.0 50 kΩ 50 pF 2.0 V DD V 0.8×VDD V DD V IH1 D R, DCLK, FSC, LAW, PD1, PD2, PD3, PD4, SP CLK , SP SYNC, SP DATA V IH2 RST V IL1 D R, DCLK, FSC, LAW, PD1, PD2, PD3, PD4, SP CLK , SP SYNC, SP DATA 0 0.8 V IL2 RST 0 0.2×VDD µPD9611 (2) AC condition Item Symbol Data clock frequency f CLK Data clock pulse width t CLK Frame synchronous clock frequency fs Condition MIN. (= 1/t CY) ±50 ppm TYP. MAX. 2048 kHz 200 ±50 ppm Unit ns 8.0 kHz High level frame synchronous pulse width t WHS 200 ns Low level frame synchronous pulse width t WLS 8 µs Clock rise time tR 50 ns Clock fall time tF 50 ns Float in synchronous timing t CSD1 100 ns t CSD2 40 ns Frame synchronous clock and data clock high level width t WHSC 100 ns D R setup time t DSR Note 65 ns D R hold time t DHR Note 120 ns SP DATA clock frequency f SPCLK 2048 kHz SP DATA setup time t GSR Note 100 ns SP DATA hold time t GHR Note 100 ns Float in SP synchronous timing t FSD 40 ns Note Set the rise time and fall time of the digital input waveform and clock signal used for measuring timings to 5 ns. 15 µPD9611 DC CHARACTERISTICS (TA = –20 to +85 °C, VDD = 5 ± 0.25 V, GND = 0 V, fDCLK = 2048 kHz, and all output pins are unloaded.) (1) Power consumption Item Circuit current Symbol I DD Power-down circuit current I DDPD Condition MIN. TYP. MAX. Unit All channels in normal operation 23 30 mA All channels in power-down mode 5 6 TYP. MAX. Unit µA (2) Digital interface Item Symbol Condition MIN. Digital input current I ID D R, DCLK, FSC, LAW, PD1, PD2, PD3, PD4, SP CLK , SP SYNC, SP DATA, RST Each pin 0 ≤ V DIN ≤ V DD –10 +10 3-state leakage current IL D X pin 0 ≤ V DIN ≤ V DD –10 +10 High level output voltage V OH D X pin I OH = –150 µ A VDD –0.3 Low level output voltage V OL D X pin I OL = 0.8 mA Digital output pin output capacitance C OD f = 1 MHz, 0 V other than unmeasured pins 15 Digital input pin input capacitance CID f = 1 MHz, 0 V other than unmeasured pins 10 V 0.4 pF (3) Transmit amplifier (AIN1, AIN2, AIN3, AIN4 pins) Item Input bias current Symbol Condition MIN. IB –10 Input resistance RIN 1 Input capacitance CIN TYP. MAX. Unit +10 µA MΩ 10 pF MAX. Unit +50 mV (4) Receive power amplifier (AOUT1, AOUT2, AOUT3, AOUT4 pins) Item Output offset voltage Symbol Condition MIN. V OA D R = +0 code ACOM as reference –50 Maximum output voltage V OM ACOM as reference –1.02 Output resistance R OUT TYP. +1.02 V Ω 1 (5) Signal reference voltage output (ACOMOUT1, ACOMOUT2, ACOMOUT3, ACOMOUT4 pins) Item Output voltage 16 Symbol V ACOM Condition MIN. TYP. MAX. Unit 2.35 2.4 2.45 V µPD9611 AC CHARACTERISTICS (TA = –20 to +85 °C, VDD = 5 ± 0.25 V, GND = 0 V, fDCLK = 2048 kHz) Item Data enable delay time Symbol Condition MIN. TYP. MAX. Unit t DZX1 D X when FSC is behind DCLK 100 ns t DZX2 D X when FSC is ahead of DCLK 100 ns Data delay time t DDX D X pin 100 ns Data hold time t HZX D X pin 25 ns 17 µPD9611 TIMING CHARTS (1) Transmit timing (a) When FSC is ahead of DCLK tR tWHS tF tWLS FSC tWHSC tCSD2 tCY tR 1 DCLK tCLK tF 2 8 tCLK tDZX2 tDDX tHZX Hi-Z Hi-Z DX 2nd MSB 7th LSB (b) When FSC is behind DCLK FSC tCSD1 tWHSC DCLK 1 2 8 tDZX1 Hi-Z DX 18 Hi-Z MSB 2nd 7th LSB µPD9611 (2) Receive timing (a) When FSC is ahead of DCLK tR tWHS tF tWLS FSC tWHSC tCSD2 tCY tR tCLK 1 DCLK tF 2 tDSR 8 tR, tF tCLK 9 tR, tF tDHR DR Don’t care MSB Don’t care 2nd 7th Don’t care 8th (b) When FSC is behind DCLK FSC tCSD1 tWHSC DCLK 19 µPD9611 (3) Gain setting timing SPSYNC tFSD SPCLK 1 2 3 8 9 tGSR tGHR SPDATA Don’t care Don’t care D7 Don’t care D6 D5 Don’t care D1 Don’t care D0 Don’t care Remark The relationship between SP SYNC and SP CLK is the same as in the receive timing. D X output measuring circuit Timing test waveform All inputs/outputs other than DX pin VDD 2.0 V 2 kΩ 0.8 V DX Test points 2.0 V Test points 2.4 V 0.8 V Output 165 pF DX pin output 2.4 V 0.4 V 0.4 V (4) Transmit, receive PCM data input/output timing charts 1 2 3 4 5 6 7 8 9 10 11 12 13 28 29 30 31 32 33 256 1 2 3 4 DCLK (2.048 MHz) FSC (8.0 kHz) Channel 1 data DX Hi-Z D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 MSB Channel 1 data DR Don’t care LSB MSB Channel 2 data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 MSB 20 Channel 2 data LSB MSB Channel 4 data D4 D3 D2 D1 D0 Channel 1 data Hi-Z LSB SB Channel 4 data D4 D3 D2 D1 D0 LSB D7 D6 D5 D4 Channel 1 data Don’t care D7 D6 D5 D4 MSB µPD9611 (5) Setting data input timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 SPCLK SPSYNC Setting data Setting data Don’t care SPDATA D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Don’t care D7 D6 D5 D4 MSB 21 µPD9611 TRANSMISSION CHARACTERISTICS (TA = –20 to +85 °C, VDD = 5 ± 0.25 V, GND = 0 V, fDCLK = 2048 kHz) Setting Value Unit Zero transmission level point (transmit) Item OTLP X Referenced to 600 Ω –3.8 dBm Zero transmission level point (receive) OTLP X Referenced to 600 Ω –3.8 dBm Item Insertion loss Transmission loss frequency Symbol Condition Symbol IL F RX characteristics Condition MIN. dB +0.3 D/A input signal 0 dBm0 1 kHz –0.3 +0.3 60 Hz 24.0 – 200 Hz 0 2.0 300 to 3000 Hz –0.15 +0.15 3200 Hz –0.15 +0.65 3400 Hz 0 0.8 3780 Hz +6.5 A/D 0 dBm0 D/A 0 to 3000 Hz –0.15 +0.15 3200 Hz –0.15 +0.65 3400 Hz 0 +0.8 3780 Hz +6.5 Reference input signal 1015 Hz GT X Unit –0.3 1015 Hz Gain tracking (tone method) MAX. A/D input signal 0 dBm0 1 kHz Reference input signal F RR TYP. 0 dBm0 A/D +3 to –40 dBm0 –0.2 +0.2 Reference input signal –50 dBm0 –0.5 +0.5 –10 dBm0 –55 dBm0 –1.0 +1.0 dB dB f = 700 to 1100 Hz GT R D/A +3 to –40 dBm0 –0.2 +0.2 Reference input signal –50 dBm0 –0.5 +0.5 –10 dBm0 –55 dBm0 –1.0 +1.0 f = 700 to 1100 Hz Transmit/receive channel SD X overall power distortion ratio (tone method) SD R A/D +3 to –30 dBm0 36 Input signal –40 dBm0 30 f = 700 to 1100 Hz –45 dBm0 25 +3 to –30 dBm0 36 D/A Input signal –40 dBm0 30 f = 700 to 1100 Hz –45 dBm0 25 Absolute delay characteristic DA A/A Input signal = 0 dBm0 Absolute delay distortion DO A/A frequency characteristics Idle channel noise 22 dB 540 µs 500 Hz 1400 µs 600 Hz 700 1000 to 2600 Hz 200 2800 Hz 1400 ICN ADA A/D A-law Psophometric weighted –72 ICN DAA D/A A-law Psophometric weighted –80 ICN ADµ A/D µ -law C-message weighted 18 ICN DAµ D/A µ -law C-message weighted 10 dBm0p dBrnc0 µPD9611 Item Symbol Cross talk between channels CT Power supply rejection ratio PSRR Coder offset Mutual modulation (2 tones) MAX. Unit A/A Input signal = 0 dBm0 Condition –70 dB AV DD 1, AV DD 2, AV DD 3, AV DD 4, DV DD = 5 V ± 100 mV P-P –25 dB +5 – A/D Input signal 0 V IMD MIN. –5 TYP. A/D Input signal: f1, f2; 300 to 3400 Hz, –4 to –21 dBm0 Measuring signal: 2 × f1 – f2 level (2 × f1 – f2) vs level (f1, f2) 44.0 dB D/A Input signal: f1, f2; 300 to 3400Hz, –4 to –21 dBm0 Measuring signal: 2 × f1 – f2 level (2 × f1 – f2) vs level (f1, f2) 44.0 dB Discrimination A/D Input signal: f; 4396 to 7796 Hz 0 dBm0 Measuring signal: 8000 – fHz –27 dB Out-of-band spurious D/A Input signal: f; 204 to 3604 Hz 0 dBm0 Measuring signal: 8000 – fHz –27 dB In-band spurious A/D Input signal: f; 700 to 1100 Hz 0 dBm0 Measuring signal: Any frequency –45 dB D/A Input signal: f; 700 to 1100 Hz 0 dBm0 Measuring signal: Any frequency –45 dB D/A Gain setting = 0 dB Measuring signal: f = up to 256 kHz –54 dBm0 dB Single frequency noise N SF Transmit gain setting ∆DGS X A/D difference from reference setting value –0.15 +0.15 Receive gain setting ∆DGS R D/A difference from reference setting value –0.15 +0.15 23 µPD9611 5. APPLICATION CIRCUIT EXAMPLE VDD 0.1 µF AVDD1 0.1 µF AVDD2 AVDD4 A/D AOUT1 D/A ACOMIN1 APD1 100 kΩ 0.1 µF DVDD CH1 AIN1 100 kΩ AVDD3 DSP Channel FiIter ACOMIN1 AIN2 CH2 AOUT2 ACOMOUT1 APD2 ACOMIN2 AIN3 AOUT3 VDD CH3 2 kΩ DX ACOMOUT1 APD3 DR RST ACOMIN3 SPSYNC AIN4 AOUT4 CH4 I/O Linear ↔ A, µ DGS MUX, DEMUX ACOMOUT1 APD4 ACOMIN4 APD1 0.1 µ F 0.1 µ F 0.1 µ F PD1 PD3 PD4 APD4 DR RST SPDATA LAW PD1 PD2 PD3 PD4 SPCLK SPSYNC ACOMIN2 ACOMOUT2 FSC ACOMIN3 Clock Generator Voltage Reference ACOMOUT3 DCLK DCLK FSC ACOMIN4 ACOMOUT4 0.1 µ F AGND1 24 LAW PD2 APD2 APD3 ACOMIN1 ACOMOUT1 SPCLK SPDATA DX AGND2 AGND3 AGND4 DGND SUBGND µPD9611 6. PACKAGE DRAWINGS 48 PIN PLASTIC SHRINK SOP (375 mil) 48 25 3°+7° –3° detail of lead end 1 24 A G H I K F J N E C D M M L B P48GT-65-375B-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 16.21 MAX. 0.639 MAX. B 0.63 MAX. 0.025 MAX. C 0.65 (T.P.) 0.026 (T.P.) D 0.30 ± 0.10 0.012+0.004 –0.005 E 0.125 ± 0.075 0.005 ± 0.003 F 2.0 MAX. 0.079 MAX. G 1.7 ± 0.1 0.067 ± 0.004 H 10.0 ± 0.3 0.394 +0.012 –0.013 I 8.0 ± 0.2 0.315 ± 0.008 J 1.0 ± 0.2 0.039+0.009 –0.008 K 0.15+0.10 –0.05 0.006+0.004 –0.002 L 0.5 ± 0.2 0.020+0.008 –0.009 M 0.10 0.004 N 0.10 0.004 25 µPD9611 7. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, please contact your NEC sales representative. SURFACE MOUNT TYPE µPD9611GT: 48-pin shrink SOP (375 mil) Soldering Method Soldering Conditions Infrared reflow Package peak temperature: 235 °C Duration: 30 sec. max. (210 °C or above) Number of times: 2 max. Time limit: 3 days Note (thereafter, 10-hour prebaking at 125 °C required.) <Cautions> (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. Pin heating Pin temperature: 300 °C max. Duration: 3 sec. max. (per side of device) Note 26 Recommended Condition Symbol IR-35-103-2 — For the storage period after unpacking from the dry-pack, storage conditions are max. 25 °C, 65 % RH. µPD9611 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 27 µPD9611 [MEMO] The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5