USB97C202 USB 2.0 ATA/ ATAPI Controller Datasheet Product Features 2.5 Volt, Low Power Core Operation 3.3 Volt I/O with 5V input tolerance Complete USB Specification 2.0 Compatibility − Includes USB 2.0 Transceiver − A Bi-directional Control and a Bi-directional Bulk Endpoint are provided. Internal or External Program Memory Interface − 48K Byte Internal ROM or optional 64K Byte External Code Space using Flash, SRAM, or EPROM Memory Complete System Solution for interfacing ATA or ATAPI devices to USB 2.0 bus − Supports USB Mass Storage Compliant Bootable BIOS − Supports ATA6 Drive capacities up to 2048GB − True UDMA Mode 4 transfer rates − Support for ATAPI Devices: - CD-ROM - CD-R - CD-RW - DVD Double Buffered Bulk Endpoint − Bi-directional 512 Byte Buffer for Bulk Endpoint − 64 Byte RX Control Endpoint Buffer − 64 Byte TX Control Endpoint Buffer On Board 12Mhz Crystal Driver Circuit Internal PLL for 480Mhz USB2.0 Sampling, 30Mhz MCU clock, and 60Mhz ATA clock Supports firmware upgrade via USB bus if “boot block” Flash program memory is used for optional external program memory 7 GPIOs for special function use: LED indicators, button inputs, etc. − Inputs capable of generating interrupts with either edge sensitivity − USB High Speed LED − Serial EEPROM interface for VID/PID/Serial Number Customization - DVD/R/W 8051 8 bit microprocessor − Provides low speed control functions − 30 Mhz execution speed at 4 cycles per instruction average − 768 Bytes of internal SRAM for general purpose scratchpad or program execution while re-flashing external ROM 100 Pin STQFP (12x12x1.4 body, 2mm footprint) package ORDERING INFORMATION Order Number(s): USB97C202-MN-02 for 100 pin STQFP package SMSC USB97C202 Page 1 DATASHEET Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © SMSC 2004. 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SMSC USB97C202 Page 2 DATASHEET Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................................................................................4 CHAPTER 2 PIN TABLE........................................................................................................................................5 CHAPTER 3 PIN CONFIGURATION .....................................................................................................................6 CHAPTER 4 BLOCK DIAGRAM............................................................................................................................7 CHAPTER 5 PIN DESCRIPTIONS.........................................................................................................................8 5.1 Buffer Type Descriptions................................................................................................................ 11 CHAPTER 6 TYPICAL APPLICATION ................................................................................................................12 CHAPTER 7 DC PARAMETERS .........................................................................................................................13 7.1 Maximum Guaranteed Ratings ...................................................................................................... 13 7.1.1 Capacitance TA = 25°C; FC = 1MHz; VDD = 2.5V ...................................................................... 15 CHAPTER 8 8.1 8.2 AC SPECIFICATIONS ....................................................................................................................16 ATA/ATAPI..................................................................................................................................... 16 USB2.0 Timing ............................................................................................................................... 16 CHAPTER 9 PACKAGE OUTLINE ......................................................................................................................17 LIST OF FIGURES Figure 3.1 – 100 PIN STQFP .........................................................................................................................................6 Figure 9.1 - 100 Pin STQFP Package Outline, 12x12x1.4 Body, 2MM Footprint (Rev A) ............................................17 LIST OF TABLES Table 5.1 – USB97C202 Pin Descriptions......................................................................................................................8 Table 5.2 - USB97C202 Buffer Type Descriptions .......................................................................................................11 Table 7.1 - DC Electrical Characteristics .......................................................................................................................13 Table 9.1 – 100 Pin STQFP Package Parameters (Rev A)..........................................................................................17 SMSC USB97C202 Page 3 DATASHEET Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet Chapter 1 General Description The USB97C202 is a USB2.0 Mass Storage Class Peripheral Controller intended for use with standard ATA-5 and -6 hard drives and standard ATAPI-5 devices. The device consists of a USB 2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded scratchpad and 768 of program SRAM, internal 48 KB program ROM, and an ATA-66 compatible interface. Provisions for optional external Flash Memory up to 64K bytes for program storage is provided. A serial EEPROM which can be modified via USB from the host provides unique VID/PID/Serial numbers, as well as optional configuration information. Internal 768 Bytes of scratchpad SRAM are also provided.. This internal SRAM can also be used for program storage to implement program upgrade via USB download to external “boot block” Flash program memory, if desired. Seven GPIO pins are provided for controlling external power control elements and sensing specialized drive functions. Provisions are made to allow dynamic attach and re-attach to the USB bus to allow hot swap of drives to be implemented. ATA-6 HDD or ATAPI-5 Optical drive USB2.0 BUS USB97C202 ATA-66 HS Indicator Serial EEPROM (VID/PID/options) SMSC USB97C202 Page 4 DATASHEET Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet Chapter 2 Pin Table DISK DRIVE INTERFACE (27 Pins) IDE_D0 IDE_D1 IDE_D2 IDE_D4 IDE_D5 IDE_D6 IDE_D8 IDE_D9 IDE_D10 IDE_D12 IDE_D13 IDE_D14 IDE_nIOR IDE_nIOW IDE_IRQ IDE_DRQ IDE_nCS0 IDE_nCS1 IDE_SA1 IDE_SA2 IORDY USB INTERFACE (7 Pins) USBD+ USBDLOOPFLTR RTERM FS+ FSMEMORY/IO INTERFACE (28 Pins) MD0 MD1 MD2 MD4 MD5 MD6 MA0 MA1 MA2 MA4 MA5 MA6 MA8 MA9 MA10 MA12 MA13 MA14 nMRD nIOR nMWR MISC (15 Pins) ROMEN GPIO1/HS GPIO2/EE_CS GPIO4/EE_DIO GPIO5/ATA RESET GPIO6/A16 XTAL1/CLKIN XTAL2 nRESET TST_OUT/DBGOUT nTESTEN CLKOUT POWER, GROUNDS, and NO CONNECTS (23 Pins) SMSC USB97C202 Page 5 DATASHEET IDE_D3 IDE_D7 IDE_D11 IDE_D15 IDE_DACK IDE_SA0 RBIAS MD3 MD7 MA3 MA7 MA11 MA15 nIOW GPIO3/VBUS GPIO7/EE_CLK nTEST/nDBGSTR Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet Pin Configuration ROMEN GPIO1 GPIO2 GPIO3 GND GPIO4 GPIO5 GPIO6 GPIO7 nTEST0 nTEST1 nTEST2 VDDIO IDE_D8 IDE_D7 IDE_D9 VDD IDE_D6 IDE_D10 GND IDE_D5 IDE_D11 IDE_D4 VDDIO IDE_D12 Chapter 3 75 IDE_D3 IDE_D13 IDE_D2 GND IDE_D14 IDE_D1 IDE_D15 IDE_D0 VDDIO IDE_DRQ IDE_nIOW IDE_nIOR IORDY GND IDE_DACK IDE_IRQ IDE_SA1 IDE_SA0 VDD IDE_SA2 IDE_nCS0 IDE_nCS1 VDDIO nMWR nMRD USB97C202 1 25 nIOR nIOW VDDIO CLKOUT MA15 MA14 GND MA13 MA12 VDD MA11 MA10 MA9 MA8 VDDIO MA7 MA6 MA5 MA4 N.C. MA3 MA2 MA1 MA0 GND RBIAS VDDA FS+ USB+ USBFSRTERM VSSA XTAL1/CLKIN XTAL2 VSSP LOOPFLTR VDDP N.C. N.C. MD7 MD6 MD5 MD4 GND MD3 MD2 MD1 MD0 nRESET 51 Figure 3.1 – 100 PIN STQFP SMSC USB97C202 Page 6 DATASHEET Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet Chapter 4 Block Diagram Auto address generators 512 Bytes EP2 TX/RX Buffer B EP0TX_BC Address EP0RX_BC Address 1.25KB SRAM 512 Bytes EP2 TX/RX Buffer A Address 64 Bytes EP1RX 64 Bytes EP1TX 64 Bytes EP0RX Address RAMWR_A/B Address RAMRD_A/B Address Address MUX Address Data Buss EP1TX_BC EP1RX_BC 64 Bytes EP0TX 32 Bit 60MHz Latch phase 1 Latch phase 0 Latch phase 2 Future phase 3 Clocked byPhase 0 Clock SIE ( Serial Interface Engine ) 32 bit 15MHz Data Buss Data @ 32 bit 15MHz ATA/ATAPI Drive ATA-66 Interface XDATA 8 bits ( Address and Data busses ) Address Register Clocked byPhase 2 Clock SIE Control Regs USB 2.0 PHY ( Transciever ) GPIO Configuration and Control 768 Byte Program/Scratchpad SRAM Clock Generation Interrupt Controller 7 pins 7 pins 48KB ROM Osc MEM/IO Bus XTAL OPTIONAL External PHY Program Memory/ IO Bus 29pins FAST 8051 CPU CORE CLOCKOUT 12 MHz Debug Serial 2 wire ( Data/Strobe) Clocked byPhase 1 Clock SMSC USB97C202 ROMEN Page 7 Revision 1.2 (02-04-04) DATASHEET 2 pins USB 2.0 ATA/ATAPI Controller Datasheet Chapter 5 Pin Descriptions Table 5.1 – USB97C202 Pin Descriptions DISK DRIVE INTERFACE IS This pin is the active high DMA request from the ATA/ATAPI interface. IDE DMA Request IDE_DRQ IDE IO Read Strobe IDE_nIOR O20 This pin is the active low read signal for the interface. IDE Register Address 1 IDE_SA1 O20 This pin is the register select address bit 1 signal for the ATA/ATAPI interface. IDE Register Address 0 IDE_SA0 O20 This pin is the register select address bit 0 signal for the ATA/ATAPI interface. IDE Register Address 2 IDE_SA2 O20 This pin is the register select address bit 2 signal for the ATA/ATAPI interface. IDE Data IDE_D15 IO20 This pin is the bi-directional data bus bit 15 signal for the ATA/ATAPI interface. IDE IO Write Strobe IDE_nIOW O20 This pin is active low write signal for the ATA/ATAPI interface. O20 This pin is the active low DMA acknowledge signal for the ATA/ATAPI interface. IDE DMA IDE_nDACK Acknowledge IDE Interrupt Request IDE_IRQ IS This pin is the active high interrupt request signal for the ATA/ATAPI interface. IDE Data IDE_D13 IO20 This pin is the bi-directional data bus bit 13 signal for the ATA/ATAPI interface. IDE Data IDE_D14 IO20 IDE Chip Select 0 IDE_nCS0 O20 This pin is the bi-directional data bus bit 14 signal for the ATA/ATAPI interface. . This pin is the active low chip select 0 signal for the ATA/ATAPI interface. IDE Chip Select 1 0 IDE_nCS1 O20 This pin is the active low select 1 signal for the ATA/ATAPI interface. IDE Data IDE_D[0:12] IO20 IO Ready IORDY These pins are bits 0-12 of the ATA/ATAPI bidirectional data bus. This pin is the active high IORDY signal from the IDE drive. SMSC USB97C202 I Page 8 DATASHEET Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet USB Bus Data USB Transceiver Filter USB Transceiver Bias Termination Resistor Full Speed USB Data USBUSB+ LOOPFLTR RBIAS RTERM FSFS+ Memory Data MD[7:0] Bus Memory Address Bus Memory Write Strobe Memory Read Strobe IO Read Strobe IO Write Strobe USB INTERFACE IO-U These pins connect to the USB bus data signals. MA[15:0] nMWR IO-U MEMORY/IO INTERFACE IO12PU When ROMEN=0, these signals are used to transfer data between the internal CPU and the external program memory. When ROMEN=1, a weak internal pull up is activated to prevent these pins from floating. O12 These signals address memory locations within the external memory. O12 Program Memory Write; active low nMRD O12 Program Memory Read; active low nIOR O12 XDATA space Read; active low nIOW O12 XDATA space Write; active low XTAL1/ Crystal Input/External CLKIN Clock Input ICLKx Crystal Output XTAL2 OCLKx Clock Output CLKOUT O8 Internal ROM ROMEN Enable IP SMSC USB97C202 This pin provides the ability to supplement the internal filtering of the transceiver with an external network, if required. A 9.09 Kohm precision resistor is attached from ground to this pin to set the transceiver’s internal bias currents. A precision 1.5Kohm precision resistor is attached to this pin from a 3.3V supply. These pins connect to the USB- and USB+ pins through 31.6 ohm series resistors. MISC 12Mhz Crystal or external clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 12Mhz clock when a crystal is not used. 12Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit. This pin produces a 30Mhz clock signal independent of the processor clock divider. It is held inactive and low whenever the internal processor clock is stopped or is being obtained from the ring oscillator. When left unconnected or tied high, the USB97C202 uses the internal ROM for program execution. When tied low, an external program memory should be connected to the memory/data bus. The state of this pin latched internally on the rising edge of nRESET. Page 9 DATASHEET Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet MISC These general purpose pins may be used either as inputs, edge sensitive interrupt inputs, or outputs. When using internal ROM mode, these pins have the following assignments: GPIO1: USB HS Indicator; active high GPIO2: Serial EEPROM (93LC66 type) Chip Select GPIO3: USB VBUS Detect Input GPIO4: Serial EEPROM Data In/Out GPIO5: ATA Drive Reset GPIO6: A16 control line for external program Flash memory when using firmware upgrade capability (external ROM operation only) GPIO7: Serial EEPROM Clock output RESET input nRESET IS This active low signal is used by the system to reset the chip. The active low pulse should be at least 100ns wide. Test input nTest[0:2] IP These signals are used for testing the chip. User should normally leave them unconnected. For board testing, all pads except these test inputs are included in an XNOR chain, such that by tying nTEST2 low, nIOR will reflect the toggling of a signal on each pin. Circuit board continuity of the pin solder connections after assembly can be checked in this manner POWER, GROUNDS, and NO CONNECTS VDD +2.5V Core power VDDIO +3.3V I/O power VDDP +2.5 Analog power VSSP Analog Ground Reference VDDA +3.3V Analog power VSSA Analog Ground Reference GND Ground Reference NC No Connect. These pins should not be connected externally. General Purpose I/O SMSC USB97C202 GPIO[1:7] IO20 Page 10 DATASHEET Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet 5.1 Buffer Type Descriptions Table 5.2 - USB97C202 Buffer Type Descriptions BUFFER I IS IP IO8 O8 O12 IO12PU IO12 IO20 O20 O20PU ICLKx OCLKx I/O-U SMSC USB97C202 DESCRIPTION Input Input with Schmitt trigger Input with weak pull-up Input/Output with 8 mA drive Output with 8mA drive Output with 12mA drive Input/Output with 12 ma drive and controlled weak pull up Input/Output with 12 ma drive Input/output with 20mA drive Output with 20mA drive Output with 20mA drive and weak pullup XTAL clock input XTAL clock output Defined in USB specification Page 11 DATASHEET Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet Chapter 6 Typical Application IDE_D[0:15] P1 IDE_DRQ IDE_nIOW IDE_nIOR IORDY IDE_DACK IDE_IRQ IDE_SA1 IDE_SA0 IDE_nCS0 IDE_D3 IDE_D12 IDE_D2 IDE_D13 IDE_SA2 IDE_nCS1 1 IDE_D1 IDE_D14 IDE_D0 IDE_D15 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 C1 0.047uF 25V 10% 2 DVDD R8 4.75K 1/8W 1% 2 2 R7 1.0K 1/8W 1% DVDD R6 2.21K 1/8W 1% 2 1 R7 1.0K 1/8W 1% R9 332 1/8W 1% 12 2 DVDD 1 2 R2 5.62K 1/8W 1% 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 IDE_D7 IDE_D6 IDE_D5 IDE_D4 IDE_D3 IDE_D2 IDE_D1 IDE_D0 1% 1 1/8W IDE_D5 IDE_D10 IDE_D4 IDE_D11 IDE supports : Mode 1, Mode 2, Mode 3, Mode 4 Ultra DMA 33/66 Primary IDE 100 1 R1 nRESET 1 IDE_D7 IDE_D8 IDE_D6 IDE_D9 LED1 T1 GREEN 2 GPIO3 R13 10K 1M R14 VDD VCCEXT P2 DVDD FS- FS+ C2 .1uF C3 .1uF C4 .1uF C5 .1uF C6 .1uF C7 .1uF C8 .1uF C9 .1uF C10 .1uF 1 R11 31.6 2 USB- 1 R12 31.6 2 USB+ 1 2 3 4 VCC DD+ GND USB TYPE B 3.3V Regulator VCCEXT R15 9.09K 1/10W 1% 3 + 2 IDE_nIOW VIN GND 1 VR1 C11 10uF R16 USB+ MA15 IDE_IRQ IDE_D14 IDE_DRQ IDE_D15 7 6 5 VSS DO 82 N.C. MD5 MD6 59 8 9 7 11 12 13 14 16 15 17 18 19 21 95 22 23 24 32 99 98 97 96 94 88 MA11 MA10 MA9 MA8 MA7 C18 10uF 13 14 15 17 18 19 20 21 MA2 MA1 MA0 2 30 VDDIO 32 16 3 VOUT 2 C14 .1uF C15 .1uF C16 .1uF C17 .1uF VDD + C19 10uF MA[0:15] MA6 MA5 MA4 MA3 nRESET 2 VIN MA13 MA12 89 93 92 MD7 VDDIO N.C. 91 20 28 nMRD 26 GND nMWR 25 nIOW 27 nIOR 2 nTEST2 1 CLKOUT VSSP VDD XTAL2 XTAL1/CLKIN nTEST1 nTEST0 GND + U1 VDD MA13 MA12 GND MA11 MA10 MA9 MA8 MA7 VDDIO MA6 MA5 MA4 MA3 GND MA2 MA1 MA0 VDD MD0 MD1 MD2 MD3 MD4 VDDP C13 .1uF VR2 1 5 6 MA14 MA15 RTERM 79 80 81 FS- USB- USB+ 87 77 78 47 40 30 29 76 RBIAS VDDA LOOPFLTR FS+ GND IDE_nIOW 37 GND IDE_SA0 IDE_nCS0 IDE_nCS1 33 39 31 IDE_SA2 IDE_nIOR IDE_DACK 36 49 46 35 41 34 IDE_SA1 IDE_D13 44 IDE_D15 IDE_D14 IDE_DRQ IDE_IRQ GPIO7 GPIO6 GPIO5 VDDIO nRESET 64 100 10 4 DI 86 CLK N.C. 85 N.C. 1 84 CS 65 VCC 66 8 69 U3 71 GPIO3 VDDIO,VDDA 2.5V Regulator VCCEXT USB97C202 68 IORDY GPIO2 VDDIO IDE_D12 IDE_D11 GND IDE_D10 IDE_D9 VDDIO IDE_D8 IDE_D7 IDE_D6 IDE_D5 IDE_D4 VSSA IDE_D3 IDE_D2 IDE_D1 IDE_D0 VDDIO IORDY ROMEN GPIO1 GPIO2 GPIO3 GPIO4 N.C. 67 IDE_D3 IDE_D2 IDE_D1 IDE_D0 3 51 54 56 57 60 52 62 61 58 55 53 83 50 48 45 43 42 38 75 74 73 72 70 90 63 VDD IDE_D8 IDE_D7 IDE_D6 IDE_D5 IDE_D4 C12 10uF VDDIO 3 IDE_D10 IDE_D9 + 1.5K 1/10W 5% MA14 USB- FS+ FS- VDDA GND IDE_nCS1 IDE_SA0 IDE_SA2 IDE_nIOR IDE_DACK IDE_SA1 IDE_D13 VDDIO IDE_D12 IDE_D11 VDDIO 2 1 IDE_nCS0 VOUT U2 D0 D1 D2 D3 D4 D5 D6 D7 NC NC VCC GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE WE VPP 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 22 24 31 1 VDDIO 4 93LC66A Serial EEPROM R18 1K Q1 Y1 R17 R3 120 12.00Mhz C21 22pf 39VF512-70 or e quiv OTP/EPROM 10K C22 22pf C20 OPTIONAL for test purposes only, if used tie ROMEN low;otherwise do not populate 1µf D1 Title LED Size C Date: SMSC USB97C202 Page 12 Revision 1.2 (02-04-04) DATASHEET USB97C202 T ypical Application Document Number Friday , June 07, 2002 Rev A Sheet 1 of 1 USB 2.0 ATA/ATAPI Controller Datasheet Chapter 7 7.1 DC Parameters Maximum Guaranteed Ratings Operating Temperature Range........................................................................................................................... 0oC to +70oC Storage Temperature Range ............................................................................................................................-55o to +150oC Lead Temperature Range (soldering, 10 seconds) ..................................................................................................... +325oC Positive Voltage on any pin, with respect to Ground ........................................................................................................ 5.5V Negative Voltage on any pin, with respect to Ground......................................................................................................-0.3V Maximum VDDA, VDDIO ......................................................................................................................................................+4.0V Maximum VDD, VDDP .........................................................................................................................................................+3.0V *Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used. Table 7.1 - DC Electrical Characteristics (TA = 0°C - 70°C, VDDIO, VDDA = +3.3 V ± 10%, VDD, VDDP = +2.5 V ± 10%,) PARAMETER SYMBOL MIN TYP MAX UNITS 0.8 V COMMENTS I Type Input Buffer Low Input Level VILI High Input Level ICLK Input Buffer VIHI 2.0 TTL Levels V 0.4 V Low Input Level VILCK High Input Level Input Leakage (All I and IS buffers) VIHCK 2.2 Low Input Leakage IIL -10 +10 uA VIN = 0 High Input Leakage IIH -10 +10 uA VIN = VDDIO SMSC USB97C202 Page 13 DATASHEET V Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet PARAMETER O8 Type Buffer SYMBOL MIN Low Output Level VOL High Output Level VOH 2.4 Output Leakage IOL -10 TYP MAX UNITS COMMENTS 0.4 V IOL = 8 mA @ VDDIO = 3.3V V IOH = -4mA @ VDDIO = 3.3V +10 uA 0.4 V IOL = 8 mA @ VDDIO = 3.3V V IOH = -4 mA @ VDDIO = 3.3V VIN = 0 to VDDIO (Note 7.1) I/O8 Type Buffer Low Output Level VOL High Output Level VOH 2.4 Output Leakage IOL -10 +10 µA 0.4 V IOL = 12 mA @ VDDIO = 3.3V V IOH = -6mA @ VDDIO = 3.3V +10 µA VIN = 0 to VDDIO (Note 7.1, Note 7.3) 0.4 V IOL = 20 mA @ VDDIO = 3.3V V IOH = -5 mA @ VDDIO = 3.3V µA VIN = 0 to VDDIO (Note 7.1, Note 7.3) VIN = 0 to VDDIO (Note 7.1, Note 7.3) I/O12 Type Buffer Low Output Level VOL High Output Level VOH 2.4 Output Leakage IOL -10 I/O20 Type Buffer Low Output Level VOL High Output Level VOH 2.4 Output Leakage IOL -10 SMSC USB97C202 Page 14 DATASHEET +10 Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet PARAMETER IO-U Note 7.2 Supply Current Unconfigured Supply Current Active SYMBOL MIN ICCINIT TYP MAX 65 85 ICC UNITS mA mA 85 120 mA mA Note 7.1 Output leakage is measured with the current pins in high impedance. Note 7.2 See appendix A for USB DC electrical characteristics. Note 7.3 Output leakage is valid only on pins without internal weak pull ups or pull downs. 7.1.1 Capacitance TA = 25°C; FC = 1MHz; VDD = 2.5V PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SMSC USB97C202 SYMBOL CIN CIN COUT MIN LIMITS TYP MAX 20 10 20 Page 15 DATASHEET COMMENTS VDDIO, VDDA VDD, VDDP VDDIO, VDDA VDD, VDDP UNIT TEST CONDITION pF All pins except USB pins (and pins under test tied pF to AC ground) pF Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet Chapter 8 8.1 AC Specifications ATA/ATAPI The USB97C202 conforms to all timing diagrams and specifications for ATAPI-5 as set forth in the T13/1321D Revision 3 NCITS specification. Please refer to this specification for more information. 8.2 USB2.0 Timing The USB97C202 conforms to all timing diagrams and specifications for USB peripheral silicon building blocks as set forth in the USB-IF USB 2.0 specification. Please refer to this specification for more information. SMSC USB97C202 Page 16 DATASHEET Revision 1.2 (02-04-04) USB 2.0 ATA/ATAPI Controller Datasheet Chapter 9 Package Outline Figure 9.1 - 100 Pin STQFP Package Outline, 12x12x1.4 Body, 2MM Footprint (Rev A) A A1 A2 D D1 E E1 H L L1 e θ W R1 R2 ccc MIN ~ 0.05 1.35 13.80 11.80 13.80 11.80 0.09 0.45 ~ o 0 0.13 0.08 0.08 ~ Table 9.1 – 100 Pin STQFP Package Parameters (Rev A) NOMINAL MAX REMARKS ~ 1.60 Overall Package Height ~ 0.15 Standoff ~ 1.45 Body Thickness ~ 14.20 X Span ~ 12.20 X body Size ~ 14.20 Y Span ~ 12.20 Y body Size ~ 0.20 Lead Frame Thickness 0.60 0.75 Lead Foot Length 1.00 ~ Lead Length 0.40 Basic Lead Pitch ~ 7o Lead Foot Angle 0.16 0.23 Lead Width ~ ~ Lead Shoulder Radius ~ 0.20 Lead Foot Radius ~ 0.08 Coplanarity Notes: 1 Controlling Unit: millimeter. 2 Tolerance on the true position of the leads is ± 0.035 mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC USB97C202 Page 17 DATASHEET Revision 1.2 (02-04-04)