ETC UT54ACTS374

UT54ACS374/UT54ACTS374
Radiation-Hardened
Octal D-Type Flip-Flops with Three-State Outputs
PINOUTS
FEATURES
20-Pin DIP
Top View
8 latches in a single package
Three-state bus-driving true outputs
Full parallel access for loading
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
OC
1Q
1
2
20
19
VDD
8Q
1D
2D
3
18
8D
4
17
7D
2Q
5
16
7Q
3Q
3D
6
7
15
14
6Q
6D
4D
4Q
8
9
13
12
5D
5Q
10
11
CLK
VSS
DESCRIPTION
20-Lead Flatpack
Top View
The UT54ACS374 and the UT54ACTS374 are non-inverting
octal D type flip-flops with three-state outputs designed for driving highly capacitive or relatively low-impedance loads. The
device is suitable for buffer registers, I/O ports, and bidirectional
bus drivers.
The eight flip-flops are edge triggered D-type flip-flops. On the
positive transition of the clock the Q outputs will follow the data
(D) inputs.
An output-control input (OC) places the eight outputs in either
a normal logic state (high or low logic level) or a high-impedance state. The high-impedance third state and increased drive
provide the capability to drive the bus line in a bus-organized
system without the need for interface or pull-up components.
The output control OC does not affect the internal operations of
the flip-flops. Old data can be retained or new data can be
entered while the outputs are off.
OC
1
20
VDD
1Q
2
19
8Q
1D
3
18
8D
2D
2Q
4
5
17
16
7D
7Q
3Q
6
15
6Q
3D
7
14
6D
4D
4Q
VSS
8
9
10
13
12
11
5D
5Q
CLK
LOGIC SYMBOL
OC
CLK
(1)
(11)
EN
C1
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
INPUTS
OC
223
CLK
OUTPUT
nD
nQ
L
H
H
L
L
L
L
L
X
nQ0
H
X
X
Z
1D (3)
(4)
2D
3D (7)
(8)
4D
5D (13)
6D (14)
7D (17)
8D (18)
1D
(2)
1Q
(5)
2Q
(6)
3Q
(9)
4Q
(12) 5Q
(15) 6Q
(16) 7Q
(19) 8Q
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
RadHard MSI Logic
UT54ACS374/UT54ACTS374
LOGIC DIAGRAM
8D
7D
(18)
6D
(17)
5D
(14)
4D
(13)
3D
(8)
2D
CLK OC
1D
(7)
(4)
(3)
DC
D C
DC
D C
D C
D C
D C
D C
Q
Q
Q
Q
Q
Q
Q
Q
(19)
8Q
(16)
7Q
(15)
6Q
(12)
5Q
(9)
4Q
(6)
3Q
(5)
2Q
(11) (1)
(2)
1Q
RADIATION HARDNESS SPECIFICATIONS 1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E6
rads(Si)
SEU Threshold 2
80
MeV-cm2/mg
SEL Threshold
120
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATING
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 7.0
V
VI/O
Voltage any pin
-.3 to VDD +.3
V
TSTG
Storage Temperature range
-65 to +150
C
TJ
Maximum junction temperature
+175
C
TLS
Lead temperature (soldering 5 seconds)
+300
C
Thermal resistance junction to case
20
C/W
II
DC input current
10
mA
PD
Maximum power dissipation
1
W
JC
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RadHard MSI Logic
224
UT54ACS374/UT54ACTS374
RECOMMENDED OPERATING CONDITIONS
225
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
4.5 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
×C
RadHard MSI Logic
UT54ACS374/UT54ACTS374
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C)
SYMBOL
VIL
VIH
IIN
PARAMETER
CONDITION
MIN
Low-level input voltage 1
ACTS
ACS
High-level input voltage 1
ACTS
ACS
MAX
UNIT
0.8
.3VDD
V
.5VDD
.7VDD
V
Input leakage current
ACTS/ACS
VIN = VDD or VSS
Low-level output voltage 3
ACTS
ACS
IOL = 8.0mA
IOL = 100 A
High-level output voltage 3
ACTS
ACS
IOH = -8.0mA
IOH = -100 A
IOZ
Three-state output leakage current
VO = VDD and VSS
-20
20
A
IOS
Short-circuit output current 2 ,4
ACTS/ACS
VO = VDD and VSS
-200
200
mA
Output current10
VIN = VDD or VSS
8
mA
(Sink)
VOL = 0.4V
Output current10
VIN = VDD or VSS
-8
mA
(Source)
VOH = VDD - 0.4V
Ptotal
Power dissipation 2, 8, 9
CL = 50pF
1.9
mW/
MHz
IDDQ
Quiescent Supply Current
VDD = 5.5V
10
A
Quiescent Supply Current Delta
For input under test
1.6
mA
VOL
VOH
IOL
IOH
IDDQ
ACTS
-1
1
A
0.40
0.25
V
.7VDD
VDD - 0.25
V
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
CIN
COUT
Input capacitance 5
= 1MHz @ 0V
15
pF
Output capacitance 5
= 1MHz @ 0V
15
pF
RadHard MSI Logic
226
UT54ACS374/UT54ACTS374
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
227
RadHard MSI Logic
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