UT54ACS00/UT54ACTS00 Radiation-Hardened Quadruple 2-Input NAND Gates FEATURES PINOUTS • 1.2µ radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 14-pin DIP - 14-lead flatpack 14-Pin DIP Top View A1 1 14 VDD B1 2 13 B4 Y1 3 12 A4 A2 B2 4 11 5 10 Y4 B3 Y2 VSS 6 9 7 8 A3 Y3 DESCRIPTION The UT54ACS00 and the UT54ACTS00 are quadruple, twoinput NAND gates. The circuits perform the Boolean functions Y = A⋅B or Y = A + B in positive logic. 14-Lead Flatpack Top View The devices are characterized over full military temperature range of -55°C to +125°C. A1 1 14 VDD B1 2 13 B4 FUNCTION TABLE Y1 3 12 A4 11 OUTPUT A2 B2 4 5 10 Y4 B3 Y Y2 6 9 A3 VSS 7 8 Y3 INPUTS A B H H L L X H X L H LOGIC DIAGRAM A1 B1 LOGIC SYMBOL A1 B1 A2 B2 A3 B3 A4 B4 (1) (2) A2 & (3) Y1 (9) (6) (8) (10) (12) (13) Y2 A3 (4) (5) B2 Y1 (11) Y2 B3 Y3 A4 Y3 B4 Y4 Y4 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 1 RadHard MSI Logic UT54ACS00/UT54ACTS00 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to V DD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C RadHard MSI Logic 2 UT54ACS00/UT54ACTS00 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; V SS = 0V 6, -55°C < T C < +125°C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100µA High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100µA Short-circuit output current 2 ,4 ACTS/ACS VO = V DD and VSS -200 Output current 10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current 10 VIN = VDD or VSS -8 mA (Source) VOH = V DD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.8 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 µA Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH ∆IDDQ ACTS -1 1 µA 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 3 Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS00/UT54ACTS00 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH(min) + 20%, - 0%; V IL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH (min) and V IL (max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm 2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; V SS = 0V 1, -55°C < T C < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 1 14 ns tPLH Input to Yn 1 11 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose ≤ 1E6 rads(Si). RadHard MSI Logic 4 UT54ACS02/UT54ACTS02 Radiation-Hardened Quadruple 2-Input NOR Gates FEATURES PINOUTS radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack 14-Pin DIP Top View DESCRIPTION Y1 A1 1 14 VDD 2 13 Y4 B1 3 12 B4 Y2 4 A2 5 11 10 A4 Y3 B2 VSS 6 7 9 8 B3 A3 The UT54ACS02 and the UT54ACTS02 are quadruple, twoinput NOR gates. The circuits perform the Boolean functions Y = A + B or Y = A B in positive logic. The devices are characterized over full military temperature range of -55 C to +125 C. A VDD Y1 1 14 A1 2 13 Y4 B1 3 12 B4 OUTPUT Y2 Y 4 5 11 10 A4 A2 B2 VSS 6 7 9 8 B3 A3 FUNCTION TABLE INPUTS 14-Lead Flatpack Top View B H X L X H L L L H Y3 LOGIC DIAGRAM LOGIC SYMBOL A1 B1 A1 (2) B1 (3) (5) A2 (6) B2 (8) A3 (9) B3 (11) A4 (12) B4 1 (1) Y1 A2 Y1 Y2 B2 (4) Y2 A3 Y3 B3 (10) (13) Y3 A4 Y4 B4 Y4 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 5 RadHard MSI Logic UT54ACS02/UT54ACTS02 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W JC II DC input current PD Maximum power dissipation mA 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 6 UT54ACS02/UT54ACTS02 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, ,9 CL = 50pF 1.8 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 7 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS02/UT54ACTS02 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 1 13 ns tPLH Input to Yn 1 11 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 8 UT54ACS04/UT54ACTS04 Radiation-Hardened Hex Inverters FEATURES PINOUTS 14-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack A1 1 14 VDD Y1 2 13 A6 A2 3 12 Y6 Y2 A3 4 11 5 10 A5 Y5 Y3 VSS 6 9 7 8 A4 Y4 DESCRIPTION The UT54ACS04 and the UT54ACTS04 are hex inverters. The circuits perform the Boolean function Y = A. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE 14-Lead Flatpack Top View A1 1 14 Y1 VDD 2 13 A6 A2 3 12 Y6 INPUT OUTPUT Y2 4 11 A Y A3 5 10 A5 Y5 H L Y3 6 9 A4 7 8 H VSS Y4 L LOGIC DIAGRAM LOGIC SYMBOL A1 A2 A3 A4 A5 A6 (1) (2) Y1 Y2 (5) (4) (6) (9) (8) (11) (10) (13) (12) (3) 1 Y3 Y1 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 Y4 Y5 Y6 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 IEC Publication 617-12. 9 A1 and RadHard MSI Logic UT54ACS04/UT54ACTS04 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 10 UT54ACS04/UT54ACTS04 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.8 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 11 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS04/UT54ACTS04 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSSsat frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 1 19 ns tPLH Input to Yn 1 11 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) RadHard MSI Logic 12 UT54ACS08/UT54ACTS08 Radiation-Hardened Quadruple 2-Input AND Gates FEATURES PINOUTS • 1.2m radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 14-pin DIP - 14-lead flatpack 14-Pin DIP Top View DESCRIPTION A1 1 14 VDD B1 2 13 B4 Y1 3 12 A4 A2 B2 4 11 Y4 5 10 B3 Y2 VSS 6 9 7 8 A3 Y3 The UT54ACS08 and the UT54ACTS08 are quadruple twoinput AND gates. The circuits perform the Boolean functions Y= A B or Y = A + B 14-Pin Flatpack Top View in positive logic. The devices are characterized over full military temperature range of -55 C to +125 C. A1 1 14 VDD B1 2 13 B4 FUNCTION TABLE Y1 3 12 A4 A2 4 11 Y4 B2 5 10 B3 Y2 6 9 A3 VSS 7 8 Y3 INPUT OUTPUT A B Y H H H L X L X L L LOGIC DIAGRAM LOGIC SYMBOL A1 B1 A2 B2 A3 B3 A4 B4 (1) (2) (4) (5) (9) (3) (6) (8) (10) (12) (13) (11) Y1 A1 B1 A2 Y2 Y3 Y4 B2 Y1 Y2 A3 B3 Y3 A4 B4 Y4 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 13 RadHard MSI Logic UT54ACS08/UT54ACTS08 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 14 UT54ACS08/UT54ACTS08 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = V DD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.8 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 15 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS08/UT54ACTS08 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; V IL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 1 13 ns tPLH Input to Yn 1 10 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 16 UT54ACS10/UT54ACTS10 Radiation-Hardened Triple 3-Input NAND Gates FEATURES • • • • • • PINOUTS 14-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed A1 1 14 Low power consumption VDD B1 2 13 C1 Single 5 volt supply A2 3 12 Y1 Available QML Q or V processes B2 C2 4 5 11 10 C3 B3 Y2 VSS 6 7 9 8 A3 Y3 Flexible package - 14-pin DIP - 14-lead flatpack DESCRIPTION The UT54ACS10 and the UT54ACTS10 are triple three-input NAND gates. The circuits perform the Boolean functions Y = A B C or Y = A + B + C in positive logic. A1 1 14 VDD B1 2 13 C1 A2 3 12 Y1 B2 4 11 C3 C2 5 10 B3 OUTPUT Y2 6 9 A3 VSS 7 8 Y3 The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS A B C Y H H H L L X X H X L X H X X L H LOGIC DIAGRAM LOGIC SYMBOL A1 B1 C1 A2 B2 C2 A3 B3 C3 (1) (2) (12) Y1 (13) (3) (4) 14-Lead Flatpack Top View (6) A1 B1 C1 Y1 A2 B2 C2 Y2 A3 B3 C3 Y3 Y2 (5) (9) (10) (11) (8) Y3 Note:. 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 17 RadHard MSI Logic UT54ACS10/UT54ACTS10 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 18 UT54ACS10/UT54ACTS10 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = V DD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.8 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 19 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS10/UT54ACTS10 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 1 16 ns tPLH Input to Yn 1 12 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 20 UT54ACS11/UT54ACTS11 Radiation-Hardened Triple 3-Input AND Gates FEATURES • • • • • • PINOUTS 14-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack DESCRIPTION A1 1 14 VDD B1 2 13 C1 A2 3 12 Y1 B2 C2 4 5 11 10 C3 B3 Y2 VSS 6 7 9 8 A3 Y3 The UT54ACS11 and the UT54ACTS11 are triple three-input AND gates. The circuits perform the Boolean functions 14-Lead Flatpack Top View Y = A B C or Y = A + B + C in positive logic. The devices are characterized over full military temperature range of -55 C to +125 C. A1 1 14 VDD B1 2 13 C1 FUNCTION TABLE A2 3 12 Y1 INPUTS B2 4 11 C3 C2 5 10 B3 Y2 6 9 A3 VSS 7 8 Y3 A B OUTPUT C Y H H H H L X X L X L X L X X L L LOGIC DIAGRAM LOGIC SYMBOL A1 B1 C1 A2 B2 C2 A3 B3 C3 (1) (2) & (12) Y1 (13) (3) (4) (6) Y2 (5) (9) (10) (11) (8) A1 B1 C1 Y1 A2 B2 C2 Y2 A3 B3 C3 Y3 Y3 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 21 RadHard MSI Logic UT54ACS11/UT54ACTS11 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 22 UT54ACS11/UT54ACTS11 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN VOL PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS Input leakage current ACTS/ACS Low-level output voltage ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD VIN = VDD or VSS -1 V 1 A 0.40 0.25 V 3 IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.8 IDDQ Quiescent Supply Current VDD = 5.5V 10 mW/ MHz A Quiescent Supply Current Delta For input under test 1.6 mA = 1MHz @ 0V 15 pF = 1MHz @ 0V 15 pF VOH IOS IOL IOH IDDQ ACTS .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 23 Input capacitance 5 Output capacitance 5 RadHard MSI Logic UT54ACS11/UT54ACTS11 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 1 13 ns tPLH Input to Yn 1 10 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 24 UT54ACS14/UT54ACTS14 Radiation-Hardened Hex Inverting Schmitt Triggers Dec. 1, 2003 FEATURES PINOUTS • 1.2µ radiation-hardened CMOS (ACTS14) and 0.6µ CRH 14-Pin DIP Top View CMOS process (ACS14) - Latchup immune High speed A1 1 14 VDD Y1 2 13 A6 A2 3 12 Y6 Y2 A3 4 11 5 10 A5 Y5 Y3 VSS 6 9 7 8 • • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 14-pin DIP (not available for the ACS14) - 14-lead flatpack DESCRIPTION The UT54ACS14 and the UT54ACTS14 are hex inverters. The circuits perform the Boolean function Y = A. The devices are characterized over full military temperature range of -55°C to +125°C. FUNCTION TABLE INPUT OUTPUT A Y H L L H A2 A3 A4 A5 A6 (1) (3) 1 (2) (4) (5) (6) (9) (8) (11) (10) (13) (12) Y1 Y2 A1 1 14 Y1 VDD 2 13 A6 A2 3 12 Y6 Y2 4 11 A3 5 10 A5 Y5 Y3 6 9 A4 VSS 7 8 Y4 A1 Y1 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 Y3 Y4 Y5 Y6 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 25 14-Lead Flatpack Top View LOGIC DIAGRAM LOGIC SYMBOL A1 A4 Y4 RadHard MSI Logic UT54ACS14/UT54ACTS14 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 (ACTS14) 5.0E5 (ACS14) rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C RadHard MSI Logic 26 UT54ACS14/UT54ACTS14 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL VT+ VT- VH IIN PARAMETER CONDITION MIN Schmitt Trigger, positive going1 threshold ACTS ACS Schmitt Trigger, negative going1 threshold ACTS ACS MAX UNIT 2.25 .7VDD V V 0.5 .3VDD Schmitt Trigger, typical range of hysteresis 2 ACTS ACS 0.3 0.6 0.9 1.5 V -1 1 µA 0.40 0.25 V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100µA High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100µA Short-circuit output current 2,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.8 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 µA Quiescent Supply Current Delta For input under test 3.1 mA VOL VOH IOS IOL IOH ∆IDDQ ACTS .7VDD VDD-0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 27 Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS14/UT54ACTS14 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All ACTS specifications are valid for radiation dose <1E6 rads(Si), and all ACS specifications are valid for radiation dose <5E5 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 2 14 ns tPLH Input to Yn 2 13 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. For the ACTS version, all specifications are valid for radiation dose <1E6 rads(Si). For the ACS version, all specifications are valid for radiation dose <5E5 rads(Si). RadHard MSI Logic 28 UT54ACS20/UT54ACTS20 Radiation-Hardened Dual 4-Input NAND Gates FEATURES • • • • • • PINOUTS 14-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack A1 1 14 VDD B1 2 13 D2 NC 3 12 C2 C1 D1 4 5 11 10 NC B2 Y1 VSS 6 7 9 8 A2 Y2 DESCRIPTION The UT54ACS20 and the UT54ACTS20 are dual 4-input NAND gates. The circuits perform the Boolean functions Y = A B C D or Y = A + B + C + D in positive logic. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS A B C D NC B2 Y Y1 6 9 A2 VSS 7 8 Y2 X X H X L X X H X X L X H X X X L H C2 D2 LOGIC DIAGRAM A1 B1 C1 D1 LOGIC SYMBOL B2 C2 11 X A2 NC 12 10 L D1 D2 3 5 L & (2) (4) VDD 13 4 H C1 14 2 D1 H B1 1 B1 C1 H (1) A1 OUTPUT H A1 14-Lead Flatpack Top View (6) Y1 (5) A2 B2 C2 Y1 Y2 D2 (9) (10) (12) (8) Y2 (13) Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 29 RadHard MSI Logic UT54ACS20/UT54ACTS20 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 30 UT54ACS20/UT54ACTS20 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = V DD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 31 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS20/UT54ACTS20 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 1 15 ns tPLH Input to Yn 1 11 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 32 UT54ACS27/UT54ACTS27 Radiation-Hardened Triple 3-Input NOR Gates FEATURES • • • • • • PINOUTS 14-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed A1 1 14 VDD B1 2 13 C1 A2 3 12 Y1 B2 C2 4 5 11 10 C3 B3 Y2 VSS 6 7 9 8 A3 Y3 Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack DESCRIPTION The UT54ACS27 and the UT54ACTS27 are triple, three-input NOR gates. The circuits perform the Boolean functions Y = A+B+C or Y = A B C in positive logic. A1 1 14 VDD B1 2 13 C1 A2 3 12 Y1 B2 4 11 C3 C2 5 10 B3 Y Y2 6 9 A3 X L VSS 7 8 Y3 The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS A B 14-Lead Flatpack Top View OUTPUT C H X X H X L X X H L L L L H LOGIC DIAGRAM LOGIC SYMBOL A1 B1 C1 A2 B2 C2 A3 B3 C3 (1) (2) 1 (12) Y1 (13) (3) (4) (6) Y2 (5) (9) (10) (11) (8) A1 B1 C1 Y1 A2 B2 C2 Y2 A3 B3 C3 Y3 Y3 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 33 RadHard MSI Logic UT54ACS27/UT54ACTS27 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W JC II DC input current PD Maximum power dissipation mA 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 34 UT54ACS27/UT54ACTS27 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = V DD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS Ptotal Power dissipation 2, 8, 9 CL = 50pF IOL Output current10 VIN = VDD or VSS (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS (Source) VOH = VDD - 0.4V Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOH IDDQ IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 -200 V 200 mA 1.8 mW/ MHz 8 mA -8 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 35 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS27/UT54ACTS27 Notes: 1.Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 1 15 ns tPLH Input to Yn 1 13 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 36 UT54ACS34/UT54ACTS34 Radiation-Hardened Hex Noninverting Buffers FEATURES • • • • • • PINOUTS 14-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed A1 1 14 VDD Y1 2 13 A6 A2 3 12 Y6 Y2 A3 4 5 11 10 A5 Y5 Y3 VSS 6 7 9 8 A4 Y4 Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack DESCRIPTION The UT54ACS34 and the UT54ACTS34 are hex noninvertering buffers. The circuits perform the Boolean functions Y = A. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUT OUTPUT A Y H H L L LOGIC SYMBOL A1 A2 A3 A4 A5 A6 (5) (9) (11) (13) 1 (2) Y1 (4) Y2 (6) Y3 (8) Y4 (10) Y5 (12) Y6 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 37 A1 1 14 VDD Y1 2 13 A6 A2 3 12 Y6 Y2 A3 4 11 A5 5 10 Y5 Y3 6 9 A4 VSS 7 8 Y4 LOGIC DIAGRAM (1) (3) 14-Lead Flatpack Top View A1 Y1 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 RadHard MSI Logic UT54ACS34/UT54ACTS34 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 38 UT54ACS34/UT54ACTS34 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = V DD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.8 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 39 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS34/UT54ACTS34 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 1 11 ns tPLH Input to Yn 1 11 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 40 UT54ACS54/UT54ACTS54 Radiation-Hardened 4-Wide AND-OR-INVERT Gates FEATURES PINOUTS • 1.2μ radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 14-pin DIP - 14-lead flatpack 14-Pin DIP Top View A 1 14 VDD C 2 13 B D 3 12 NC E F 4 5 11 10 NC NC VSS 6 7 9 8 H G Y DESCRIPTION The UT54ACS54 and the UT54ACTS54 are 4-wide AND-ORINVERT gates. The devices perform the Boolean function: 14-Lead Flatpack Top View Y = AB+CD+EF+GH The devices are characterized over full military temperature range of -55°C to +125°C. FUNCTION TABLE INPUT OUTPUT A B C D E F G H Y H H X X X X X X L X X H H X X X X L X X X X H H X X L X X X X X X H H L L X L X L X L X H X L X L X L X L H A 1 14 VDD C 2 13 B D 3 12 NC E 4 11 NC F 5 10 H NC 6 9 G VSS 7 8 Y LOGIC DIAGRAM A LOGIC SYMBOL A B C D E F G H (1) B C & D >1 (13) (2) (3) (4) Y E & F & (8) Y (5) (9) G H & (10) Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 41 RadHard MSI Logic UT54ACS54/UT54ACTS54 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 15.5 °C/W II DC input current ±10 mA PD Maximum power dissipation 3.2 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. PD = TS-TC/ΘJC. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C RadHard MSI Logic 42 UT54ACS54/UT54ACTS54 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100μA High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100μA Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS Ptotal Power dissipation 2, 8, 9 CL = 50pF IOL Output current10 VIN = VDD or VSS (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS (Source) VOH = VDD - 0.4V Quiescent Supply Current VDD = 5.5V 10 μA Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOH IDDQ ΔIDDQ ACTS -1 1 μA 0.40 0.25 V .7VDD VDD - 0.25 -200 V 200 mA 2.0 mW/ MHz 8 mA -8 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 43 Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS54/UT54ACTS54 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL From any input to Y output 1 16 ns tPLH From any input to Y output 1 13 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose ≤ 1E6 rads(Si). RadHard MSI Logic 44 UT54ACS74/UT54ACTS74 Radiation-Hardened Dual D Flip-Flops with Clear & Preset FEATURES PINOUTS • 1.2μ radiation-hardened CMOS (ACS74) and 0.6μm CRH CMOS process (ACTS74) - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 14-pin DIP (not available for the ACTS74) - 14-lead flatpack 14-Pin DIP Top View CLR1 1 14 VDD D1 2 13 CLR2 CLK1 3 12 D2 PRE1 4 11 Q1 5 10 CLK2 PRE2 Q1 VSS 6 7 9 8 Q2 Q2 DESCRIPTION The UT54ACS74 and the UT54ACTS74 contain two independent D-type positive triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. When Preset and Clear are inactive (high), data at the D input meeting the setup time requirement is transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The devices are characterized over full military temperature range of -55°C to +125°C. 14-Lead Flatpack Top View CLR1 1 14 VDD D1 2 13 CLR2 CLK1 3 12 D2 PRE1 4 11 CLK2 Q1 5 10 PRE2 Q1 6 9 Q2 VSS 7 8 Q2 FUNCTION TABLE INPUTS OUTPUT PRE CLR CLK D Q Q L H X X H L H L X X L H LOGIC SYMBOL PRE1 CLK1 L L X X H1 H1 D1 H H ↑ H H L CLR1 H H ↑ L L H PRE2 H H L X Qo Qo CLK2 D2 Note: 1. The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are near VIL maximum. In addition, this configuration is nonstable; that is, it will not persist when either preset or clear returns to its inactive (high) level. 45 CLR2 (4) (3) (2) (1) S (5) C1 D1 (6) Q1 Q1 R (10) (11) (12) (13) (9) (8) Q2 Q2 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. RadHard MSI Logic UT54ACS74/UT54ACTS74 LOGIC DIAGRAM PRE CLR Q CLK Q D RadHard MSI Logic 46 UT54ACS74/UT54ACTS74 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -0.3 to VDD +0.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 ° C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 47 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C RadHard MSI Logic UT54ACS74/UT54ACTS74 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 0.3VDD V 0.5VDD 0.7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100μA High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100μA Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 μA Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH ΔIDDQ ACTS -1 1 μA 0.40 0.25 V 0.7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic 48 UT54ACS74/UT54ACTS74 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at a frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 49 RadHard MSI Logic UT54ACS74/UT54ACTS74 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL CLK to Q, Q 3 21 ns tPLH CLK to Q, Q 1 20 ns tPLH PRE to Q 1 15 ns tPHL PRE to Q 3 19 ns tPHL CLR to Q 3 19 ns tPLH CLR to Q 1 15 ns fMAX Maximum clock frequency 71 MHz tSU1 PRE or CLR inactive Setup time before CLK ↑ 5 ns tSU2 Data setup time before CLK ↑ 5 ns tH3 Data hold time after CLK ↑ 2 ns tW Minimum pulse width PRE or CLR low CLK high CLK low 7 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose ≤ 1E6 rads(Si). 3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested. RadHard MSI Logic 50 UT54ACS85/UT54ACTS85 Radiation-Hardened 4-Bit Comparators FEATURES radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack LOGIC SYMBOL A0 A1 A2 A3 (A<B)IN (A=B)IN (A>B)IN B0 B1 DESCRIPTION The UT54ACS85 and the UT54ACTS85 are 4-bit magnitude comparators that perform comparison of straight binary and straight BCD (8-4-2-1) codes. Three fully decoded decisions about two 4-bit words (A, B) are made and are externally available at three outputs. Devices are fully expandable to any number of bits without external gates. The cascading paths of the devices are implemented with only a two-gate-level delay to reduce overall comparison times for long words. An alternate method of cascading which further reduces the comparison time is shown in the typical application data. B2 B3 COMP (10) 0 (12) A (13) (15) (2) (3) (4) 3 < < = > (7) (6) = (5) (A<B)OUT (A=B)OUT (A>B)OUT > (9) 0 (11) B (14) (1) 3 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. PINOUTS 16-Pin DIP Top View B3 1 16 VDD (A<B)IN 2 15 A3 (A=B)IN 3 14 B2 (A>B)IN (A>B)OUT 4 5 13 12 A2 A1 (A=B)OUT (A<B)OUT 6 7 11 10 B1 A0 VSS 8 9 B0 The devices are characterized over full military temperature range of -55 C to +125 C. 16-Lead Flatpack Top View B3 51 1 16 VDD A3 (A<B)IN 2 15 (A=B)IN 3 14 B2 (A>B)IN 4 13 A2 (A>B)OUT 5 12 A1 (A=B)OUT 6 11 B1 (A<B)OUT VSS 7 8 10 9 A0 B0 RadHard MSI Logic UT54ACS85/UT54ACTS85 FUNCTION TABLE COMPARING INPUTS CASCADING INPUTS OUTPUTS A3, B3 A2, B2 A1, B1 A0, B0 A>B A<B A=B A>B A<B A=B A3>B3 X X X X X X H L L A3<B3 X X X X X X L H L A3=B3 A2>B2 X X X X X H L L A3=B3 A2<B2 X X X X X L H L A3=B3 A2=B2 A1>B1 X X X X H L L A3=B3 A2=B2 A1<B1 X X X X L H L A3=B3 A2=B2 A1=B1 A0>B0 X X X H L L A3=B3 A2=B2 A1=B1 A0<B0 X X X L H L A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L A3=B3 A2=B2 A1=B1 A0=B0 X X H L L H A3=B3 A2=B2 A1=B1 A0=B0 H H L L L L A3=B3 A2=B2 A1=B1 A0=B0 L L L H H L LOGIC DIAGRAM (15) A3 (1) B3 (5) A>B A2 (13) B2 (14) A<B (2) (3) A=B (4) A>B (6) A=B (12) A1 B1 (11) (7) A<B (10) A0 (9) B0 RadHard MSI Logic 52 UT54ACS85/UT54ACTS85 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 53 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS85/UT54ACTS85 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = V DD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.3 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 54 UT54ACS85/UT54ACTS85 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum 7. All specifications valid for radiation dose 1E6 rads(Si). 6. Maximum allowable relative shift equals 50mV. 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 55 RadHard MSI Logic UT54ACS85/UT54ACTS85 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL An, Bn to (A<B)OUT 2 22 ns tPLH An, Bn to (A<B)OUT 2 16 ns tPHL An, Bn to (A=B)OUT 2 17 ns tPLH An, Bn to (A=B)OUT 2 16 ns tPHL An, Bn to (A>B)OUT 2 18 ns tPLH An, Bn to (A>B)OUT 2 16 ns tPHL (A<B)IN, (A=B) IN to (A>B)OUT 2 17 ns tPLH (A<B)IN, (A=B) IN to (A>B)OUT 2 15 ns tPHL (A=B)IN to (A=B) OUT 2 13 ns tPLH (A=B)IN to (A=B) OUT 1 15 ns tPHL (A>B)IN, (A=B) IN to (A<B)OUT 2 17 ns tPLH (A>B)IN, (A=B) IN to (A<B)OUT 2 15 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) RadHard MSI Logic 56 UT54ACS86/UT54ACTS86 Radiation-Hardened Quadruple 2-Input Exclusive OR Gates FEATURES • • • • • • PINOUTS 14-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack DESCRIPTION A1 1 14 VDD B1 2 13 B4 Y1 3 12 A4 A2 B2 4 11 5 10 Y4 B3 Y2 VSS 6 9 7 8 The UT54ACS86 and the UT54ACTS86 are quadruple 2-input exclusive OR gates. The devices perform the Boolean function Y = A B = AB + AB in positive logic. An application is as a true/complement element. If one of the inputs is low, the other input will be reproduced in true form at the output. If one of the inputs is high, the signal on the other input will be reproduced inverted at the output. The devices are characterized over full military temperature range of -55 C to +125 C. A3 Y3 14-Lead Flatpack Top View A1 B1 Y1 A2 B2 Y2 VSS 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VDD B4 A4 Y4 B3 A3 Y3 FUNCTION TABLE INPUTS OUTPUT A B Y L L L L H H H L H H H L LOGIC DIAGRAM LOGIC SYMBOL A1 B1 A2 B2 A3 B3 A4 B4 (1) (2) (4) (5) (9) =1 (3) (6) (8) (10) (12) (13) (11) Y1 Y2 A1 B1 Y1 A2 B2 Y2 A3 B3 Y3 A4 B4 Y4 Y3 Y4 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 57 RadHard MSI Logic UT54ACS86/UT54ACTS86 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C Rad-ard MSI Logic 58 UT54ACS86/UT54ACTS86 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = V DD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.8 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 59 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS86/UT54ACTS86 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Data to input 1 14 ns tPLH Data to input 1 13 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). Rad-ard MSI Logic 60 UT54ACS109/UT54ACTS109 Radiation-Hardened Dual J-K Flip-Flops Dec. 1, 2003 FEATURES • 1.2µ radiation-hardened CMOS (ACTS109) and 0.6µ CRH CMOS process (ACS109) - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 16-pin DIP (not available for ACS109) - 16-lead flatpack addition, this configuration is nonstable; that is, it will not persist when either preset or clear returns to its inactive (high) level. PINOUTS 16-Pin DIP Top View DESCRIPTION The UT54ACS109 and the UT54ACTS109 are dual J-K positive triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the other input levels. When preset and clear are inactive (high), data at the J and K input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the J and K input can be changed without affecting the levels at the outputs. The flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D flip-flops if J and K are tied together. The devices are characterized over full military temperature range of -55°C to +125°C. CLR1 1 16 VDD J 2 15 CLR2 K1 3 14 J2 CLK1 PRE1 4 5 13 12 K2 CLK2 Q1 Q1 VSS 6 7 8 11 10 9 PRE2 Q2 Q2 16-Lead Flatpack Top View CLR1 1 16 VDD J1 2 15 CLR2 K1 3 14 J2 CLK1 PRE1 4 5 13 12 K2 Q1 6 11 PRE2 Q1 7 8 10 9 Q2 VSS CLK2 Q2 FUNCTION TABLE INPUTS OUTPUT PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H1 H1 H H ↑ L L L H H H ↑ H L Toggle H H ↑ L H No Change H H ↑ H H H H L X X H PRE1 J1 CLK1 K1 CLR1 PRE2 L No Change Note: 1. The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are near VIL maximum. In 61 LOGIC SYMBOL J2 CLK2 (5) (2) (4) (3) (1) S J1 C1 K1 R (6) (7) Q1 Q1 (11) (14) (10) Q2 (12) (13) K2 (15) CLR2 (9) Q2 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. RadHard MSI Logic UT54ACS109/UT54ACTS109 LOGIC DIAGRAM PRE Q CLK J Q K CLR RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 (ACTS109) 5.0E5 (ACS109) rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 62 UT54ACS109/UT54ACTS109 RECOMMENDED OPERATING CONDITIONS 63 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C RadHard MSI Logic UT54ACS109/UT54ACTS109 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100µA High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100µA Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8 ,9 CL = 50pF 2.0 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 µA Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH ∆IDDQ ACTS -1 1 µA 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic 64 UT54ACS109/UT54ACTS109 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All ACTS specifications are valid for radiation dose <1E6 rads(Si), and all ACS specifications are valid for radiation dose <5E5 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 65 RadHard MSI Logic UT54ACS109/UT54ACTS109 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL CLK to Q, Q 5 27 ns tPLH CLK to Q, Q 4 23 ns tPLH PRE to Q 1 16 ns tPHL PRE to Q 1 19 ns tPHL CLR to Q 2 19 ns tPLH CLR to Q 2 16 ns fMAX Maximum clock frequency 62 MHz tSU1 PRE or CLR inactive Setup time before CLK ↑ 5 ns tSU2 Data setup time before CLK↑ 5 ns tH3 Data hold time after CLK ↑ 3 ns tW Minimum pulse width PRE or CLR low CLK high CLK low 8 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. For the ACTS version, all specifications are valid for radiation dose <1E6 rads(Si). For the ACS version, all specifications are valid for radiation dose <5E5 rads(Si). 3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested. RadHard MSI Logic 66 UT54ACS132/UT54ACTS132 Radiation-Hardened Quadruple 2-Input NAND Schmitt Triggers Dec. 1, 2003 PINOUTS FEATURES 14-Pin DIP Top View • 1.2µ radiation-hardened CMOS (ACTS 132) and 0.6µ CRH CMOS process (ACS132) - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 14-pin DIP (not available for the ACS132) - 14-lead flatpack A1 1 14 VDD B1 2 13 B4 Y1 3 12 A4 A2 B2 4 11 5 10 Y4 B3 Y2 VSS 6 9 7 8 A3 Y3 DESCRIPTION The UT54ACS132 and the UT54ACTS132 are 2-input NAND gates with Schmitt Trigger input levels. A high applied on both the inputs forces the output to a low state. The devices are characterized over full military temperature range of -55°C to +125°C. A1 B1 Y1 A2 B2 FUNCTION TABLE INPUTS 14-Lead Flatpack Top View OUTPUT An Bn Yn L L H L H H H L H H H L Y2 VSS A1 B1 A2 B1 A2 B2 A3 B3 A4 B4 (1) (2) B2 (9) (3) (13) 3 12 4 11 5 10 Y4 B3 6 9 A3 7 8 VDD B4 A4 Y3 Y1 Y2 Y1 B3 Y3 A4 (6) (8) (10) (12) 13 A3 & (4) (5) 14 2 LOGIC DIAGRAM LOGIC SYMBOL A1 1 (11) Y2 B4 Y4 Y3 Y4 Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 67 RadHard MSI Logic UT54ACS132/UT54ACTS132 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 (ACTS132) 5.0E5 (ACS132) rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C RadHard MSI Logic 68 UT54ACS132/UT54ACTS132 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL PARAMETER CONDITION MIN MAX UNIT 2.25 .7VDD V VT + Schmitt Trigger, positive going 1 threshold ACTS ACS VT- Schmitt Trigger, negative going 1 threshold ACTS ACS 0.5 .3VDD VH Schmitt Trigger, typical range of hysteresis 2 ACTS ACS 0.3 0.6 0.9 1.5 IIN Input leakage current ACTS/ACS -1 1 µA 0.40 0.25 V V VIN = VDD or VSS VOL Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100µA VOH High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100µA .7VDD VDD - 0.25 IOS Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 IOL Output current10 VIN = VDD or VSS (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS (Source) VOH = VDD - 0.4V IOH Ptotal Power dissipation 2, 8, 9 IDDQ Quiescent Supply Current ∆IDDQ Quiescent Supply Current Delta ACTS V V 200 mA 8 mA -8 mA CL = 50pF 1.9 mW/ MHz VDD = 5.5V 10 µA 3.1 mA For input under test VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 69 Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS132/UT54ACTS132 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All ACTS specifications are valid for radiation dose <1E6 rads(Si), and all ACS specifications are valid for radiation dose <5E5 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Yn 2 15 ns tPLH Input to Yn 2 12 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. For the ACTS version, all specifications are valid for radiation dose <1E6 rads(Si). For the ACS version, all specifications are valid for radiation dose <5E5 rads(Si). RadHard MSI Logic 70 UT54ACS138/UT54ACTS138 Radiation-Hardened 3-Line to 8-Line Decoders/Demultiplexers FEATURES • • • • • • PINOUTS 16-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION A 1 16 VDD B 2 15 Y0 C 3 14 Y1 G2A G2B 4 5 13 12 Y2 Y3 G1 Y7 6 7 11 10 Y4 Y5 VSS 8 9 Y6 The UT54ACS138 and the UT54ACTS138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. 16-Lead Flatpack Top View The conditions at the binary select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates of inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The devices are characterized over full military temperature range of -55 C to +125 C. A 1 16 VDD B 2 15 Y0 C 3 14 Y1 G2A 4 13 Y2 G2B 5 12 Y3 G1 6 11 Y4 Y7 VSS 7 8 10 9 Y5 Y6 FUNCTION TABLE ENABLE INPUTS 71 SELECT INPUTS OUTPUT G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H L X X X X X H H H H H H H H X H X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L RadHard MSI Logic UT54ACS138/UT54ACTS138 LOGIC SYMBOL A BIN/OCT (1) 1 B (2) (3) C 0 2 1 4 2 3 4 G1 G2A G2B (6) & (4) 5 EN 6 7 (5) (15) (14) (13) (12) (11) (10) (9) (7) Y0 Y1 Y2 A B C (1) (2) (3) DMUX 1 0 7 G --- 2 4 0 1 2 Y3 3 Y4 4 Y5 Y6 G1 G2A Y7 G2B (6) & (4) 5 EN (15) (14) (13) (12) (11) (10) 6 7 (5) (9) (7) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Note: 1. Logic symbols in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM (15) (14) G1 ENABLE (6) (13) G2A (4) G2B (5) (12) Y0 Y1 Y2 Y3 DATA (11) A SELECT B (1) (10) (2) (9) C (3) RadHard MSI Logic (7) Y4 Y5 Y6 Y7 72 UT54ACS138/UT54ACTS138 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 73 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS138/UT54ACTS138 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 74 UT54ACS138/UT54ACTS138 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 75 RadHard MSI Logic UT54ACS138/UT54ACTS138 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Binary Select to output Yn 2 15 ns tPLH Binary Select to output Yn 2 15 ns tPHL Enable to output Yn 2 17 ns tPLH Enable to output Yn 2 14 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 76 UT54ACS139/UT54ACTS139 Radiation-Hardened Dual 2-Line to 4-Line Decoders/Demultiplexers PINOUTS FEATURES 16-Pin DIP Top View • Incorporates two enable inputs to simplify cascading and/or data reception • 1.2μ radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 16-pin DIP - 16-lead flatpack IG 1 16 VDD 1A 2 15 2G 1B 3 14 2A 1Y0 1Y1 4 5 13 12 2B 2Y0 1Y2 1Y3 6 7 11 10 2Y1 2Y2 VSS 8 9 2Y3 DESCRIPTION The UT54ACS139 and the UT54ACTS139 are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. The devices consist of two individual two-line to four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. The devices are characterized over full military temperature range of -55°C to +125°C. FUNCTION TABLE SELECT INPUTS A Y0 Y1 Y2 Y3 H X X H H H H L L L L H H H L L H H L H H L H L H H L H H 16 VDD 1A 2 15 2G 1B 3 14 2A 1Y0 1Y1 4 5 13 12 2B 1Y2 6 11 2Y1 1Y3 VSS 7 8 10 9 2Y2 2Y3 2Y0 LOGIC DIAGRAM B H 1 OUTPUT G L 1G H H H L (4) 1G (1) (5) (6) SELECT 1A 1B (3) (7) (15) (11) (10) SELECT 2A 2B 77 1Y1 1Y2 (2) (12) 2G 1Y0 1Y3 DATA ENABLE INPUTS 16-Lead Flatpack Top View 2Y0 2Y1 2Y2 (14) (13) (9) 2Y3 RadHard MSI Logic UT54ACS139/UT54ACTS139 LOGIC SYMBOL (2) 1A (3) 1B (1) 1G X/Y 1 (4) 0 2 1 EN 2 (5) (6) (7) 3 (12) (11) (14) 2A (10) (13) 2B (9) (15) 2G 1A 1Y0 1Y1 1B 1Y2 1G DMUX (2) 0 (3) 0 0 G --- 1 3 (1) 1 2 3 1Y3 (4) (5) (6) (7) (12) 2Y0 2Y1 2A 2Y2 2B 2Y3 2G (11) (14) (10) (13) (9) (15) 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 Note: 1. Logic symbols in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 78 UT54ACS139/UT54ACTS139 RECOMMENDED OPERATING CONDITIONS 79 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C RadHard MSI Logic UT54ACS139/UT54ACTS139 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL PARAMETER CONDITION VIL Low-level input voltage 1 ACTS ACS VIH High-level input voltage 1 ACTS ACS IIN Input leakage current ACTS/ACS VIN = VDD or VSS VOL Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100μA VOH High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100μA IOL Output current10 VIN = VDD or VSS (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS (Source) VOH = VDD - 0.4V Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS Ptotal Power dissipation 2, 8, ,9 IDDQ IOH IOS ΔIDDQ MIN MAX UNIT 0.8 .3VDD V .5VDD .7VDD -1 V 1 μA 0.40 0.25 V .7VDD VDD - 0.25 V 8 mA -8 mA 200 mA CL = 50pF 1.8 mW/ MHz Quiescent Supply Current VDD = 5.5V 10 μA Quiescent Supply Current Delta For input under test 1.6 ACTS -200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic 80 UT54ACS139/UT54ACTS139 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 81 RadHard MSI Logic UT54ACS139/UT54ACTS139 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Select to output Yn 2 14 ns tPLH Select to output Yn 2 15 ns tPHL Enable to output Yn 2 14 ns tPLH Enable to output Yn 2 12 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose ≤ 1E6 rads(Si). RadHard MSI Logic 82 UT54ACS151/UT54ACTS151 Radiation-Hardened 1 of 8 Data Selectors/Multiplexers FEATURES PINOUTS • 8-line to 1-line multiplexers can perform as Boolean function generators, parallel-to-serial converters, and data source selectors • radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 16-pin DIP - 16-lead flatpack 16-Pin DIP Top View D3 1 16 D2 2 15 D1 3 14 D0 4 13 Y 5 12 Y 6 11 G 7 10 A B Vss 8 9 C DESCRIPTION The UT54ACS151 and the UT54ACTS151 are data multiplexers that provide full binary decoding to select one of eight data sources. The strobe input, G, must be at a low logic level to enable the inputs. A high level at the strobe terminal forces the Y output high and the Y output low. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS SELECT OUTPUT VDD D4 D5 D6 D7 16-Lead Flatpack Top View D3 1 16 VDD D2 2 15 D4 D1 3 14 D5 D0 4 13 D6 Y 5 12 D7 Y 6 11 A G 7 10 Vss 8 9 B C STROBE C B A G Y Y X X X H L H L L L L D0 D0 L L H L D1 D1 L H L L D2 D2 L H H L D3 D3 H L L L D4 D4 H L H L D5 D5 H H L L D6 D6 H H H L D7 D7 H= high level, L = low level, X = irrelevant D0, D1... D7 = the level of the D respective input LOGIC SYMBOL (7) G (11) A (10) B (9) C (4) D0 (3) D1 (2) D2 (1) D3 (15) D4 (14) D5 (13) D6 (12) D7 MUX E N 0 0 G --3 1 2 0 1 (5) (6) Y Y 2 3 4 5 6 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 83 RadHard MSI Logic UT54ACS151/UT54ACTS151 LOGIC DIAGRAM STROBE G (7) D0 (4) D1 (3) D2 D3 (2) (1) (5) DATA (6) D4 (15) D5 (14) D6 (13) D7 (12) DATA SELECT RadHard MSI Logic A (11) B (10) C (9) Y OUTPUTS Y 84 UT54ACS151/UT54ACTS151 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 85 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS151/UT54ACTS151 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.3 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 86 UT54ACS151/UT54ACTS151 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 87 RadHard MSI Logic UT54ACS151/UT54ACTS151 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to Y 1 22 ns tPLH Input to Y 1 23 ns tPHL Input to Y 1 25 ns tPLH Input to Y 1 19 ns tPHL Select to Y 1 21 ns tPLH Select to Y 1 22 ns tPHL Select to Y 1 24 ns tPLH Select to Y 1 21 ns tPHL G to Y 1 14 ns tPLH G to Y 1 11 ns tPHL G to Y 1 14 ns tPLH G to Y 1 10 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 88 UT54ACS153/UT54ACTS153 Radiation-Hardened Dual 4 to 1 Multiplexers FEATURES PINOUTS 16-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UT54ACS153 and the UT54ACTS153 are dual four to one line selectors/multiplexers. Common inputs A and B select a value from one of four sources for each section and routes the value from each section to their respective outputs. Separate strobe inputs, G are provided for each of the two four-line sections. 1G 1 16 VDD B 1C3 1C2 1C1 1C0 1Y VSS 2 3 4 5 6 7 8 15 14 13 12 11 10 9 2G A 2C3 2C2 2C1 2C0 2Y 16-Lead Flatpack Top View 1G 1 16 VDD B 2 15 2G The devices are characterized over full military temperature range of -55 C to +125 C. 1C3 3 14 A 1C2 4 2C3 FUNCTION TABLE 1C1 5 13 12 1C0 6 11 2C1 1Y VSS 7 8 10 9 2C0 2Y SELECT INPUTS DATA INPUTS OUTPUT CONTROL OUTPUT B A C0 C1 C2 C3 G Y X X X X X X H L L L L X X X L L L L H X X X L H L H X L X X L L L H X H X X L H H L X X L X L L H L X X H X L H H H X X X L L L H H X X X H L H 2C2 LOGIC SYMBOL A B 1G 1C0 1C1 1C2 1C3 2G 2C0 2C1 (14) (2) 0 1 0 G --3- (1) (6) (5) (4) (3) (15) EN 0 1 2 MUX (7) 1Y 3 (10) (11) (12) 2C2 (13) 2C3 (9) 2Y Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 89 RadHard MSI Logic UT54ACS153/UT54ACTS153 LOGIC DIAGRAM OUTPUT CONTROL 1G (1) 1C0 (6) 1C1 DATA 1 1C2 1C3 B SELECT (5) (7) 1Y (4) (3) (2) A (14) 2C0 (10) 2C1 (11) DATA 2 2C2 2C3 OUTPUT CONTROL RadHard MSI Logic 2G (12) (9) 2Y (13) (15) 90 UT54ACS153/UT54ACTS153 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 91 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS153/UT54ACTS153 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.1 mW/ MHz IDDQ Quiescent Supply Current Delta For input under test 1.6 mA 10 A VOL VOH IOS IOL IOH ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V IDDQ Quiescent Supply Current CIN Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF COUT RadHard MSI Logic VDD = 5.5V 92 UT54ACS153/UT54ACTS153 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 93 RadHard MSI Logic UT54ACS153/UT54ACTS153 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1 , -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Data to output Yn 2 16 ns tPLH Data to output Yn 2 12 ns tPHL Strobe to output Yn 1 15 ns tPLH Strobe to output Yn 1 14 ns tPHL Select to output Yn 2 16 ns tPLH Select to output Yn 2 14 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 94 UT54ACS157/UT54ACTS157 Radiation-Hardened Quadruple 2 to 1 Multiplexers FEATURES • • • • • • PINOUTS 16-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UT54ACS157 and the UT54ACTS157 are monolithic data selectors/multiplexers. A 4-bit word is selected from one of two sources and is routed to the four outputs. A separate strobe input, G, is provided. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS OUTPUT STROBE G SELECT A/B DATA A B Y H X X X L L L L X L L L H X H L H X L L L H X H H A/B 1 16 VDD A1 2 15 G B1 3 14 A4 Y1 4 13 B4 A2 5 12 Y4 B2 6 11 A3 Y2 7 10 B3 VSS 8 9 Y3 16-Lead Flatpack Top View A/B 1 16 VDD A1 2 15 G B1 3 14 A4 Y1 4 13 B4 A2 5 12 Y4 B2 6 11 A3 Y2 VSS 7 8 10 B3 9 Y3 LOGIC SYMBOL (15) G (1) A/B A1 B1 A2 B2 A3 B3 A4 B4 EN G1 (2) (3) (5) (6) (11) (10) (14) (13) 1 1 MUX (4) (7) (9) (12) Y1 Y2 Y3 Y4 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 95 RadHard MSI Logic UT54ACS157/UT54ACTS157 LOGIC DIAGRAM 1A (2) (4) 1B 2A (3) 1Y (5) (7) 2B (6) 3A (11) 2Y (9) 3B 4A (10) (14) (12) 4B STROBE G SELECT A/B RadHard MSI Logic 3Y (13) 4Y (15) (1) 96 UT54ACS157/UT54ACTS157 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 97 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS157/UT54ACTS157 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 98 UT54ACS157/UT54ACTS157 Notes: 1.Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltag within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 99 RadHard MSI Logic UT54ACS157/UT54ACTS157 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Data to output Yn 2 15 ns tPLH Data to output Yn 2 13 ns tPHL Strobe to output Yn 2 15 ns tPLH Strobe to output Yn 2 12 ns tPHL Select to output Yn 2 16 ns tPLH Select to output Yn 2 14 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 100 UT54ACS163/UT54ACTS163 Radiation-Hardened 4-Bit Synchronous Counters FEATURES PINOUTS 16-Pin DIP Top View Internal look-ahead for fast counting Carry output for n-bit cascading Synchronous counting Synchronously programmable radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack CLR 1 16 VDD CLK 2 15 RCO A 3 14 QA B 4 13 QB C 5 12 QC D ENP 6 7 11 10 QD ENT VSS 8 9 16-Lead Flatpack Top View DESCRIPTION The UT54ACS163 and the UT54ACTS163 are synchronous presettable 4-bit binary counters that feature internal carry lookahead logic for high-speed counting designs. Synchronous operation occurs by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable inputs and internal gating. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. The counters are fully programmable (i.e., they may be preset to any number between 0 and 15). Presetting is synchronous; applying a low level at the load input disables the counter and causes the outputs to agree with the load data after the next clock pulse. The clear function is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse. This synchronous clear allows the count length to be modified by decoding the Q outputs for the maximum count desired. The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. The devices are characterized over full military temperature range of -55 C to +125 C. 101 LOAD CLR 1 16 VDD CLK 2 15 RCO A 3 14 QA B 4 13 QB C 5 12 QC D 6 11 QD ENP VSS 7 8 10 9 ENT LOAD LOGIC SYMBOL (1) CLR (9) LOAD ENT ENP CLK A B C D (10) (7) (2) (3) (4) (5) (6) CTRDIV 16 5CT=0 M1 M2 3CT = 15 G3 G4 (15) RCO C5/2,3,4+ 1,5D (1) (2) (4) (8) (14) (13) (12) (11) QA QB QC QD Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. RadHard MSI Logic UT54ACS163/UT54ACTS163 FUNCTION TABLE Operating Mode CLR Reset (Clear) l Parallel Load h3 ENP ENT LOAD DATA A,B,C,D QN RCO X X X X L L X X X X l l l h L H L 3 Count h3 h h h X Count 1 Inhibit h3 h3 l2 X X l2 h3 X X QN QN 1 h CLK X X h3 1 L H = High voltage level h = High voltage level one setup time prior to the low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to the low-to-high clock transition Notes: 1. The RCO output is high when ENT is high and the counter is at terminal count HHHH. 2. The high-to-low transition of ENP or ENT should only occur while CLK is high for conventional operations. 3. The low-to-high transition of LOAD or CLR should only occur while CLK is high for conventional operations. LOGIC DIAGRAM CLK CLR (2) (1) D (9) LOAD (7) ENP (10) ENT (3) DATA A Q (14) QA C Q D Q (13) QB C Q DATA B (4) D Q (12) QC C Q DATA C (5) D Q (11) Q D C DATA D (6) Q (15) RadHard MSI Logic RCO 102 UT54ACS163/UT54ACTS163 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 103 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS163/UT54ACTS163 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 104 UT54ACS163/UT54ACTS163 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 105 RadHard MSI Logic UT54ACS163/UT54ACTS163 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL CLK to Qn 4 24 ns tPLH CLK to Qn 4 22 ns tPHL CLK to RCO 4 22 ns tPLH CLK to RCO 4 24 ns tPHL ENT to RCO 1 13 ns tPLH ENT to RCO 1 14 ns fMAX Maximum clock frequency 77 MHz tSU1 A, B, C, D Setup time before CLK 6 ns tSU2 LOAD, ENP, ENT, CLR low or high Setup time before CLK 6 ns tH13 Data hold time after CLK 1 ns tH2 All synchronous inputs hold time after CLK 1 ns tW Minimum pulse width CLR low CLK high CLK low 7 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). 3. Based on characterization, hold time (t H1) of 0ns can be assumed if data setup time (tSU1) is >10ns. This is guaranteed, but not tested. RadHard MSI Logic 106 UT54ACS164/UT54ACTS164 Radiation-Hardened 8-Bit Shift Registers FEATURES PINOUTS AND-gated (enable/disable) serial inputs Fully buffered clock and serial inputs Direct clear radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack 14-Pin DIP Top View A 1 14 VDD B 2 13 QH QA 3 12 QG QB QC 4 5 11 10 QF QE QD VSS 6 7 9 8 14-Lead Flatpack Top View DESCRIPTION The UT54ACS164 and the UT54ACTS164 are 8-bit shift registers which feature AND-gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data. A low at either input inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high-level at both serial inputs sets the first flip-flop to the high level at the next clock pulse. Data at the serial inputs may be changed while the clock is high or low, providing the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock input. The devices are characterized over full military temperature range of -55 C to +125 C. CLR CLK A 1 14 VDD B 2 13 QH QA 3 12 QG QB QC 4 11 5 10 QF QE QD 6 9 CLR VSS 7 8 CLK LOGIC SYMBOL FUNCTION TABLE INPUTS OUTPUTS CLR CLK A B QA L X X X L H L QB L ... QH L A B X X QA0 QB0 QH0 H H H H QAn QGn H L X L QAn QGn H X L L QAn QGn Notes: 1. QA0, QB0, QH0 = the level of QA , QB or QH, respectively, before the indicated steady-state input conditions were established. 2. Q An and QGn = the level of Q A or QG before the most recent transition of the clock; indicates a one-bit shift. 107 (9) CLR (8) CLK (1) (2) SRG8 R C1/ & 1D (3) QA (4) QB (5) Q (6) C QD (10) Q (11) E Q (12) F Q (13) G QH Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. RadHard MSI Logic UT54ACS164/UT54ACTS164 LOGIC DIAGRAM CLR CLK SERIAL (9) (8) (1) A B (2) C R K S C R K S C R K S (4) (3) QA C R K S QB (5) QC C R K S C R K S (6) QD (10) QE C R K S C R K S (11) (12) QF QG (13) QH RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 108 UT54ACS164/UT54ACTS164 RECOMMENDED OPERATING CONDITIONS 109 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS164/UT54ACTS164 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 110 UT54ACS164/UT54ACTS164 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 111 RadHard MSI Logic UT54ACS164/UT54ACTS164 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL CLK to Qn 4 21 ns tPLH CLK to Qn 2 18 ns tPHL CLR to Qn 5 21 ns fMAX Maximum clock frequency 83 MHz tSU1 CLR inactive Setup time before CLK 4 ns tSU2 Data setup time before CLK 4 ns tH3 Data hold time after CLK 2 ns tW Minimum pulse width CLR low CLK high CLK low 6 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). 3. Based on characterization, hold time (t H) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested. RadHard MSI Logic 112 UT54ACS165/UT54ACTS165 Radiation-Hardened 8-Bit Parallel Shift Registers FEATURES PINOUTS 16-Pin DIP Top View Complementary outputs Direct overriding load (data) inputs Gated clock inputs Parallel-to-serial data conversions radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack SH/LD 1 16 VDD CLK 2 15 CLK INH E 3 14 D F 4 13 C G 5 12 B H QH 6 7 11 10 A VSS 8 9 The UT54ACS165 and the UT54ACTS165 are 8-bit serial shift registers that, when clocked, shift the data toward serial output QH. Parallelin access to each stage is provided by eight individual data inputs that are enabled by a low level at the SH/LD input. The devices feature a clock inhibit function and a complemented serial output QH . Clocking is accomplished by a low-to-high transition of the CLK input while SH/LD is held high and CLK INH is held low. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a low CLK input and a low-to-high transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is high. Parallel loading is disabled when SH/LD is held high. Parallel inputs to the registers are enabled while SH/LD is low independently of the levels of CLK, CLK INH or SER inputs. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INTERNAL OUTPUTS OUTPUTS SH/ CLK CLK SER PARALLEL LD INH A ... H L H X L H H H QA QB QH QH h X X a ... h X a QA b QB h QH QH L H X H QA QG QG L L X L QA QG QG H X L X X X QA QB QH QH Note: 1. Qn = The state of the referenced output one setup time prior to the Low-toHigh clock transition. 113 QH 16-Lead Flatpack Top View DESCRIPTION INPUTS SER SH/LD 1 16 VDD CLK 2 15 CLK INH E 3 14 D F G 4 13 C 5 12 B H QH 6 11 A 7 8 10 9 SER QH VSS LOGIC SYMBOL (1) SH/LD (15) CLK INH (2) CLK (10) SER (11) A (12) B (13) C (14) D (3) E (4) F (5) G (6) H SRG8 C1 (LOAD) 1 C2/ 2D 1D 1D 1D (9) Q (7) H QH Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. RadHard MSI Logic UT54ACS165/UT54ACTS165 LOGIC DIAGRAM A B (11) SH/LD CLK INH CLK SER C (12) D (13) E (14) F (1) G (4) (3) H (5) (6) (15) (2) (10 ) S S S S S S S S C C C C C C C C (9) D QA D QB DQ C D QD DQ E D QF D QG (7) D QH R R R R R R R R QH QH RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. RadHard MSI Logic 114 UT54ACS165/UT54ACTS165 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 115 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS165/UT54ACTS165 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.9 mW/MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 116 UT54ACS165/UT54ACTS165 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 117 RadHard MSI Logic UT54ACS165/UT54ACTS165 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL CLK or CLK INH to QH or QH 2 21 ns tPLH CLK or CLK INH to QH or QH 2 18 ns tPHL SH/LD to QH or QH 2 21 ns tPLH SH/LD to QH or QH 2 18 ns tPHL H to Q H 2 21 ns tPLH H to Q H 2 17 ns tPHL H to Q H 2 20 ns tPLH H to Q H 2 18 ns fMAX Maximum clock frequency 71 MHz tSU1 SER, SH/LD, CLKINH or CLK Setup time before CLK or CLK INH 7 ns tSU2 Data setup time before SH/LD 7 ns tH1 SER hold time after CLK or CLK INH 2 ns tH2 CLK INH hold time after CLK 2 ns tH33 Hold time for any input after SH/LD 2 ns Minimum pulse width CLK or CLK INH high CLK or CLK INH low SH/LD 7 ns tW Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). 3. Based on characterization, hold time (t H3) of 0ns for data pins A-H, can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested. RadHard MSI Logic 118 UT54ACS169/UT54ACTS169 Radiation-Hardened 4-Bit Up-Down Binary Counters FEATURES • Fully synchronous operation for counting and programming • Internal look-ahead for fast counting • Carry output for n-bit cascading • Fully independent clock circuit • 1.2μ radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 16-pin DIP - 16-lead flatpack PINOUTS 16-Pin DIP Top View DESCRIPTION The UT54ACS169 and the UT54ACTS169 are synchronous 4bit binary counters that feature an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable inputs and internal gating. Synchronous operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple clock) counters. The clock input triggers the four flip-flops on the rising (positive-going) edge of the clock. The counters are fully programmable (i.e., the outputs may each be preset high or low). The load input circuitry allows loading with the carry-enable output of cascaded counters. Loading is synchronous; applying a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry provides for cascaded counters for n-bit synchronous application without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output. Assert both count enable inputs (ENP and ENT) to count. The direction of the count is determined by the level of the U/D input. When U/D is high, the counter counts up; when low, it counts down. Input ENT is fed forward to enable the carry output. The ripple carry output 16 VDD 2 15 RCO 3 14 B C 4 5 13 12 QA QB D ENP 6 7 11 10 VSS 8 9 U/D 1 CLK A QC QD ENT LOAD 16-Lead Flatpack Top View U/D 1 16 VDD CLK 2 15 RCO A 3 14 QA B 4 13 QB C 5 12 QC D 6 11 QD ENP 7 10 ENT VSS 8 9 LOAD Transitions at ENP or ENT are allowed regardless of the level of the clock input. The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, U/D) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. The devices are characterized over full military temperature range of -55°C to +125°C. RCO enables a low-level pulse while the count is zero (all inputs low) counting down or maximum (15) counting up. The lowlevel overflow carry pulse can be used to enable successive cascaded stages. 119 RadHard MSI Logic UT54ACS169/UT54ACTS169 LOGIC SYMBOL LOAD U/D ENT (9) (1) (10) (7) ENP (2) CLK A (3) (4) B (5) C (6) D FUNCTION TABLE CTRDIV 16 M1 (LOAD) M2 (COUNT) M3 (UP) M4 (DOWN) 3,5CT = 15 G5 4,5CT = 0 G6 (15) RCO OUTPUT LOAD ENP ENT U/D CLK Count Up H L L H ↑ Count Down H L L L ↑ Load Preset L X X X ↑ Inhibit H H H X X H X X X X 2,3,5,6+/C7 2,3,5,61,7D (1) (2) (4) (8) (14) (13) (12) (11) QA QB QC QD Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. RadHard MSI Logic 120 UT54ACS169/UT54ACTS169 LOGIC DIAGRAM CLK U/D (2) (1) DQ C Q LOAD (9) ENP ENT (14) Q0 (7) (10) DQ C Q A (13) Q 1 (3) (4) DQ C B Q (12) C (5) Q2 DQ C Q (11) D 121 (6) Q3 (15) RCO RadHard MSI Logic UT54ACS169/UT54ACTS169 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C RadHard MSI Logic 122 UT54ACS169/UT54ACTS169 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100μA High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100μA Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.3 mW/MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 μA Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH ΔIDDQ ACTS -1 1 μA 0.40 0.25 V .7VDD VDD-0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 123 Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS169/UT54ACTS169 Notes: 1.Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH CLK to RCO 2 23 ns tPHL CLK to RCO 4 28 ns tPLH CLK to any Q 4 24 ns tPHL CLK to any Q 4 24 ns tPLH ENT to RCO 1 15 ns tPHL ENT to RCO 2 16 ns tPLH U/D to RCO 2 16 ns tPHL U/D to RCO 2 16 ns fMAX Maximum clock frequency 71 MHz tSU1 A, B, C, D setup time before CLK ↑ 9 ns tSU2 LOAD , ENP, ENT, U/D Setup time before CLK ↑ 9 ns tH1 Data hold time after CLK ↑ 2 ns tH2 All synchronous inputs hold time after CLK ↑ 2 ns tW Minimum pulse width CLK high CLK low 7 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose ≤ 1E6 rads(Si). 3. Based on characterization, hold time (tH1) of 0ns can be assumed if data setup time (tSU1) is >10ns. This is guaranteed, but not tested. RadHard MSI Logic 124 UT54ACS190/UT54ACTS190 Radiation-Hardened Synchronous 4-Bit Up-Down BCD Counters FEATURES PINOUTS Single down/up count control line Look-ahead circuitry enhances speed of cascaded counters Fully synchronous in count modes Asynchronously presettable with load control radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack 16-Pin DIP Top View The outputs of the four flip-flops are triggered on a low-to-highlevel transition of the clock input if the enable input (CTEN) is low. A logic one applied to CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down. The counters feature a fully independent clock circuit. Changes at control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The counters are fully programmable. The outputs may be preset to either logic level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. The asynchronous load allows counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. If preset to an illegal state, the counter returns to a normal sequence in one or two counts. 125 1 16 VDD QB 2 15 A QA 3 14 CLK CTEN D/U 4 5 13 12 RCO MAX/MIN QC QD 6 7 11 10 LOAD C VSS 8 9 D 16-Lead Flatpack Top View DESCRIPTION The UT54ACS190 and the UT54ACTS190 are synchronous 4bit reversible up-down BCD decade counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed. Synchronous operation eliminates the output counting spikes associated with asynchronous counters. B B 1 16 VDD QB 2 15 A QA 3 14 CLK CTEN D/U 4 5 13 12 RCO MAX/MIN QC 6 11 LOAD QD VSS 7 8 10 9 C D Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum (MAX/MIN) count. The MAX/MIN output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (9) counting up. The ripple clock output (RCO) produces a low-level output pulse under those same conditions but only while the clock input is low. The counters easily cascade by feeding the RCO to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. Use the MAX/MIN count output to accomplish look-ahead for highspeed operation. The devices are characterized over full military temperature range of -55 C to +125 C. RadHard MSI Logic UT54ACS190/UT54ACTS190 FUNCTION TABLE LOGIC SYMBOL Function LOAD CTEN D/U Count up H L L Count down H L H Asynchronous L X CLK CTRDIV 10 G M2 (DOWN) (4) CTEN D/U X CLK H X (13) G4 (11) No change (12) MAX/MIN RCO LOAD (15) 5D (1) B C (1) 7 (2) (6) (9) QA Q (4) Q (8) QD Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM (14) CLK (13) (5) D/U RCO (12) MAX/MIN (15) A CTEN B (4) J S Q (3) Q A C K Q R (1) J S Q (2) Q B C KR Q C (10) J S Q (6) Q C C K Q R D (9) J S Q (7) Q D C K Q R LOAD RadHard MSI Logic (11) 126 UT54ACS190/UT54ACTS190 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 127 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS190/UT54ACTS190 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.2 mW/MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 128 UT54ACS190/UT54ACTS190 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 129 RadHard MSI Logic UT54ACS190/UT54ACTS190 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH LOAD to Qn 2 19 ns tPHL LOAD to Qn 2 22 ns tPLH Data In to Qn 2 19 ns tPHL Data In to Qn 2 21 ns tPLH CLK to Qn 2 18 ns tPHL CLK to Qn 2 20 ns tPLH CLK to RCO 2 16 ns tPHL CLK to RCO 2 16 ns tPLH CLK to MAX/MIN 2 18 ns tPHL CLK to MAX/MIN 2 23 ns tPLH D/U to RCO 2 16 ns tPHL D/U to RCO 2 18 ns tPLH D/U to MAX/MIN 1 14 ns tPHL D/U to MAX/MIN 2 18 ns tPLH CTEN to RCO 2 12 ns tPHL CTEN to RCO 2 16 ns fMAX Maximum clock frequency 71 MHz tSU1 CTEN, D/U Setup time before CLK 13 ns tSU2 LOAD Setup time before CLK 2 ns tSU3 A, B, C, D setup time before LOAD 7 ns tH1 CTEN and D/U hold time after CLK 2 ns tH23 A, B, C, D hold time after LOAD 2 ns Minimum pulse width CLK high CLK low LOAD low 7 ns tW Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). 3. Based on characterization, hold time (t H2) of 0ns can be assumed if data setup time (tSU3) is >10ns. This is guaranteed, but not tested. RadHard MSI Logic 130 UT54ACS191/UT54ACTS191 Radiation-Hardened Synchronous 4-Bit Up-Down Binary Counters FEATURES PINOUTS 16-Pin DIP Top View • Single down/up count control line • Look-ahead circuitry enhances speed of cascade counters • Fully synchronous in count modes • Asynchronously presetable with load control • 1.2μ radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 16-pin DIP - 16-lead flatpack The outputs of the four flip-flops are triggered on a low-to-highlevel transition of the clock input if the enable input (CTEN) is low. A logic one applied to CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down. The counters feature a fully independent clock circuit. Changes at control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The counters are fully programmable. The outputs may be preset to either logic level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. The asynchronous load allows counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. 1 16 VDD QB 2 15 A QA 3 14 CLK CTEN D/U 4 5 13 12 QC QD 6 7 11 10 RCO MAX/MIN LOAD VSS 8 9 C D 16-Lead Flatpack Top View DESCRIPTION The UT54ACS191 and the UT54ACTS191 are synchronous 4bit reversible up-down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed. Synchronous operation eliminates the output counting spikes associated with asynchronous counters. B B 1 16 VDD QB 2 15 A QA 3 14 CLK CTEN 13 12 RCO D/U 4 5 QC 6 11 LOAD QD VSS 7 8 10 9 C D MAX/MIN The ripple clock output (RCO) produces a low-level output pulse under those same conditions but only while the clock input is low. The counters easily cascade by feeding the RCO to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. Use the MAX/MIN count output to accomplish look-ahead for highspeed operation. The devices are characterized over full military temperature range of -55°C to +125°C. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum (MAX/MIN) count. The MAX/MIN output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (15) counting up. 131 Rad-Hard MSI Logic UT54ACS191/UT54ACTS191 FUNCTION TABLE LOGIC SYMBOL FUNCTION LOAD CTEN D/U CLK Count Up H L L ↑ Count Down H L H ↑ Asynchronous Reset L X X X No Change H CTEN D/U (4) (5) (14) CLK (11) H X X LOAD CTRDIV 16 G1 M2 (DWN) 2(CT=0)Z6 M3 (UP) 3(CT=9)Z6 1,2 -/1,3+ G4 6,1,4 C5 (15) A B C (1) (10) (1) 5D ±7 (2) (4) (9) D (8) (12) (13) (3) (2) (6) (7) MAX/MIN RCO QA QB QC QD Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM (14) CLK (13) RCO D/U (5) (12) MAX/MIN A (15) 1J CTEN (4) (3) S Q 1K R B QA C1 Q (1) 1J (2) S Q QB C1 Q 1K R C (10) 1J (6) S Q QC C1 Q 1K R D (9) 1J S Q (7) Q D C1 Q 1K R LOAD Rad-Hard MSI Logic (11) 132 UT54ACS191/UT54ACTS191 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 133 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C Rad-Hard MSI Logic UT54ACS191/UT54ACTS191 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100μA High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100μA Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.1 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 μA Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH ΔIDDQ ACTS -1 1 μA 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF Rad-Hard MSI Logic 134 UT54ACS191/UT54ACTS191 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 135 Rad-Hard MSI Logic UT54ACS191/UT54ACTS191 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH LOAD to Qn 2 20 ns tPHL LOAD to Qn 2 22 ns tPLH Data In to Qn 2 23 ns tPHL Data In to Qn 2 19 ns tPLH CLK to Qn 2 17 ns tPHL CLK to Qn 2 22 ns tPLH CLK to RCO 2 12 ns tPHL CLK to RCO 2 15 ns tPLH CLK to MAX/MIN 2 22 ns tPHL CLK to MAX/MIN 2 23 ns tPLH D/U to RCO 2 16 ns tPHL D/U to RCO 2 18 ns tPLH D/U to MAX/MIN 2 15 ns tPHL D/U to MAX/MIN 2 17 ns tPLH CTEN to RCO 2 12 ns tPHL CTEN to RCO 2 16 ns fMAX Maximum clock frequency 63 MHz tSU1 LOAD , CTEN, D/U 12 ns Setup time before CLK ↑ tSU2 A, B, C, D setup time before LOAD ↑ 5 ns tH1 CTEN and D/U hold time after CLK ↑ 2 ns tH23 A, B, C, D hold time after LOAD ↑ 2 ns Minimum pulse width CLK high CLK low LOAD low 8 ns tW Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose ≤ 1E6 rads(Si). 3. Based on characterization, hold time (tH2) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested. Rad-Hard MSI Logic 136 UT54ACS193/UT54ACTS193 Radiation-Hardened Synchronous 4-Bit Up-Down Dual Clock Counters FEATURES • • • • • • • • • • PINOUTS 16-Pin DIP Top View Look-ahead circuitry enhances cascaded counters Fully synchronous in count modes Parallel asynchronous load for modulo-N count lengths Asynchronous clear 1.2μm radiation-hardened CMOS (ACTS193) and .6μm CRH CMOS process (ACS193) - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack B 1 16 VDD QB 2 15 A QA 3 14 CLR DOWN UP 4 5 13 12 BO CO QC QD 6 7 11 10 LOAD C VSS 8 9 D 16-Lead Flatpack Top View DESCRIPTION The UT54ACS193 and the UT54ACTS193 are synchronous 4bit, binary reversible up-down binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed. Synchronous operation eliminates the output counting spikes normally associated with asynchronous counters. The outputs of the four flip-flops are triggered on a low-to-highlevel transition of either count input (Up or Down). The direction of the counting is determined by which count input is pulsed while the other count input is high. The counters are fully programmable. The outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the count pulses. Asynchronous loading allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. B 1 16 VDD QB 2 15 A QA 3 14 CLR DOWN UP 4 5 13 12 BO CO QC 6 11 LOAD QD VSS 7 8 10 9 C D FUNCTION TABLE FUNCTION CLOCK UP CLOCK DOWN CLR LOAD Count Up ↑ H L H Count Down H ↑ L H Reset X X H X Load Preset Input X X L L A clear input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and the load inputs. The counter is designed for efficient cascading without the need for external circuitry. The borrow output (BO) produces a lowlevel pulse while the count is zero and the down input is low. Similarly, the carry output (CO) produces a low-level pulse while the count is maximum 137 RadHard MSI Logic UT54ACS193/UT54ACTS193 LOGIC SYMBOL (14) CLR (5) UP DOWN LOAD A (4) (11) (15) (1) B (10) C (9) D CTRDIV 16 CT=0 1CT=15 2+ G1 1G2 C3 3D 2CT=0 (1) (2) (4) (8) (12) (13) (3) (2) CO BO QA QB (6) QC (7) QD Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. RadHard MSI Logic 138 UT54ACS193/UT54ACTS193 LOGIC DIAGRAM (13) (12) A BO CO (15) DOWN (4) UP (5) SQ C RQ (3) Q A B (1) SQ C RQ C (2) Q B (10) SQ C RQ D (9) CLR (14) SQ C RQ (6) Q (7) Q C D LOAD (11) 139 RadHard MSI Logic UT54ACS193/UT54ACTS193 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 140 UT54ACS193/UT54ACTS193 RECOMMENDED OPERATING CONDITIONS 141 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C RadHard MSI Logic UT54ACS193/UT54ACTS193 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100μA High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100μA Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.1 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 μA Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH ΔIDDQ ACTS -1 1 μA 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic 142 UT54ACS193/UT54ACTS193 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All ACTS specifications are valid for radiation dose ≤ 1E6 rads(Si) and all ACS specifications are valid for radiation dose ≤ 5E5 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 143 RadHard MSI Logic UT54ACS193/UT54ACTS193 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH UP to Qn 2 20 ns tPHL UP to Qn 2 24 ns tPLH UP to CO 2 13 ns tPHL UP to CO 2 16 ns tPLH DOWN to BO 2 13 ns tPHL DOWN to BO 2 16 ns tPLH DOWN to Qn 2 20 ns tPHL DOWN to Qn 2 24 ns tPLH LOAD to Qn 2 22 ns tPHL LOAD to Qn 2 23 ns tPHL CLR to Qn 2 22 ns fMAX Maximum clock frequency 56 MHz tSU1 LOAD inactive setup time before UP or DOWN ↑ 3 ns tSU2 CLR inactive setup time before UP or DOWN↑ 3 ns tSU3 A, B, C, D setup time before LOAD ↑ 6 ns tH1 UP high hold time after DOWN ↑ 20 ns tH2 DOWN high hold time after UP ↑ 20 ns tH33 A, B, C, D hold time after LOAD ↑ 2 ns Minimum pulse width UP high or low DOWN high or low LOAD low CLR high 9 ns tW Notes: 1. Maximum allowable relative shift equals 50mV. 2. All ACTS specifications are valid for radiation dose ≤ 1E6 rads(Si) and all ACS specifications are valid for radiation dose ≤ 5E5 rads(Si). 3. Based on characterization, data hold time (tH3) of 0ns can be assumed if data setup time (tSU3) is >10ns. This is guaranteed, but not tested. RadHard MSI Logic 144 UT54ACTS220 Clock and Wait-State Generation Circuit FEATURES • 1.2μ radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5-volt supply • Available QML Q or V processes • Flexible package - 14-pin DIP - 14-lead flatpack PINOUTS 14-Pin DIP Top View DESCRIPTION The UT54ACTS220 is designed to be a companion chip to UTMC’s UT69151 SμMMIT family for the purpose of generating clock and wait-state signals. The device contains a divide by two circuit that accepts TTL input levels and drives CMOS output buffers. The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by ± 20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle variation. The wait-state circuit generates a single wait-state by delaying the falling edge of DTACK into the SμMMIT. The clock/timing device generates DTACK from the falling edge of input RCS which is synchronized by the falling edge of 24MHz. The SμMMIT drives inputs RCS and DMACK. The devices are characterized over full military temperature range of -55°C to +125°C. NC 1 14 VDD CLKOUT 2 13 24MHz CLKOUT 3 12 CLKIN NC 4 11 DTACK TEST 5 10 MRST 48MHz VSS 6 9 7 8 RCS DMACK 14-Lead Flatpack Top View NC 1 14 VDD CLKOUT 2 13 24MHz CLKOUT 3 12 CLKIN NC 4 11 DTACK TEST 5 10 MRST 48MHz VSS 6 9 7 8 RCS DMACK LOGIC SYMBOL MRST 48MHz RCS DMACK (10) S (6) (9) (8) CTR1 (13) SRG2 1D (12) DTACK S (11) (2) CLKIN 24MHz (4) (3) TEST CLKOUT CLKOUT Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 145 RadHard MSI Logic UT54ACTS220 PIN DESCRIPTION Pin Number Pin Name Description 2 CLKOUT Buffered version of CLKIN. 3 CLKOUT Inverted version of CLKIN. 4 CLKIN Clock Input. This signal can be any arbitrary signal that the user wishes to buffer. 6 48MHz 48MHz Clock. The 24MHz clock is created by dividing this signal by two. 8 DMACK 9 RCS 10 MRST Master Reset. This input can be used to preset 24MHz, DTACK and TEST. For normal operation tie MRST to VDD through a resistor. 11 TEST Test output signal. 12 DTACK Data Transfer Acknowledge. This signal can be used to drive the DTACK signal of the SμMMIT if the user requires one wait state during the memory transfer. 13 24MHz 24MHz Clock. This output runs at half the frequency of the 48MHz input. The falling edge of 24MHz is the signal that latches the DTACK outputs. 24MHz is forced high whenever MRST is low. Properly loaded, 24MHz will have a 50% duty cycle ± 5%. DMA Acknowledge. This input is generated by the SμMMIT. When high, this signal will cause DTACK output to be forced high. RAM Chip Select. This input is generated by the SμMMIT. FUNCTIONAL TIMING: Single SμMMIT Wait-State For both read and write memory cycles, DTACK is an input to the SμMMIT E and SμMMIT LXE/DXE. A non-wait state memory requires two clock cycles, T1 and T2 of figure 1. For accessing slower memory devices, the UT54ACTS220 holds DTACK to a logical “1”. This results in the stretching of memory cycles by one clock to three clock cycles, TW of figure 1. The SμMMIT E and SμMMIT LXE/DXE samples the DTACK on the rising edge of the 24 MHz clock. If DTACK is not generated before the rising edge of the clock, the SμMMIT E and SμMMIT LXE/DXE extends the memory cycle. 48MHz 24MHz T1 TW T2 DMACK RCS DTACK Figure 1. Functional Timing RadHard MSI Logic 146 UT54ACTS220 LOGIC DIAGRAM 24MHz D 48MHz MRST RCS Q CK Q RST D DTACK Q CK Q PRE D Q TEST CK Q PRE DMACK CLKIN CLKOUT CLKOUT 147 RadHard MSI Logic UT54ACTS220 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C 48MHz Duty Cycle 50 ± 20% MHz RadHard MSI Logic 148 UT54ACTS220 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL PARAMETER VIL Low-level input voltage 1 TTL VIH High-level input voltage 1 TTL IIN Input leakage current TTL CONDITION MIN MAX UNIT 0.8 V .5VDD VIN = VDD or VSS -1 V 1 μA 0.4 0.25 V VOL1 Low-level output voltage 3 IOL = 8mA IOL = 100μA VOH1 High-level output voltage 3 IOH = -8mA, VDD = 4.5V IOH = -100μA VOL2 CLKOUT/CLKOUT Low-level output voltage 3 IOL = 12mA, VDD = 4.5V IOL = 100μA VOH2 CLKOUT/CLKOUT High-level output voltage 3 IOH = -12mA, VDD = 4.5V IOH = -100μA IOS Short-circuit output current 2 ,4 VO = VDD and VSS -300 IOL1 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Output current10 VIN = VDD or VSS 12 mA (Sink) CLKOUT/CLKOUT VOL = 0.4V Output current10 VIN = VDD or VSS -12 mA (Source) CLKOUT/CLKOUT VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.0 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 μA Quiescent Supply Current Delta For input under test 1.6 mA IOH1 IOL2 IOH2 ΔIDDQ .7VDD VDD-0.25 V 0.4 0.25 V .7VDD VDD-0.25 V 300 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 149 Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACTS220 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. RadHard MSI Logic 150 UT54ACTS220 AC ELECTRICAL DIAGRAM 48MHz 24MHz RCS T1 TW TW T2 tSUR DTACK tSU tH CLKIN CLKOUT or CLKOUT 151 tPHL or tPLH RadHard MSI Logic UT54ACTS220 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL 48MHz ↑ to 24MHz ↓ 0 15 ns tPLH 48MHz ↑ to 24MHz ↑ 0 15 ns tPHL 24MHz ↓ to DTACK ↓ 0 7 ns tPLH 24MHz ↓ to DTACK ↑ 0 6 ns tPLH DMACK ↑ to DTACK ↑ 3 16 ns tPLH MRST ↓ to 24MHz, DTACK ↑ 3 16 ns tPHL CLKIN ↓ to CLKOUT ↓ 0 11 ns tPLH CLKIN ↑ to CLKOUT ↑ 0 11 ns tPHL CLKIN ↑ to CLKOUT ↓ 0 11 ns tPLH CLKIN ↓ to CLKOUT ↑ 0 11 ns tSU3 DTACK ↓ to 24MHz ↑ 12 ns tH3 24MHz ↑ to DTACK ↑ 20 ns tSUR Setup time from RCS ↓ to 24MHz ↓ 16 ns tWM MRST pulse width 5 ns tWC CLKIN pulse width 12 ns fMAX CLKIN 40 MHz Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose ≤ 1E6 rads(Si). 3. Guaranteed by design but not tested. RadHard MSI Logic 152 UT54ACS240/UT54ACTS240 Radiation-Hardened Octal Buffers & Line Drivers, Inverted Three-State Outputs FEATURES PINOUTS 20-Pin DIP Top View Three-state outputs drive bus lines or buffer memory address registers radiation-hardened CMOS - Latchup immune High speed 1G 1A1 1 20 2 19 VDD 2G 2Y4 3 18 1Y1 Low power consumption 1A2 4 17 Single 5 volt supply 2Y3 5 16 2A4 1Y2 Available QML Q or V processes 1A3 2Y2 6 15 7 14 1A4 2Y1 8 13 9 12 2A2 1Y4 VSS 10 11 2A1 Flexible package - 20-pin DIP - 20-lead flatpack DESCRIPTION The UT54ACS240 and the UT54ACTS240 are inverting octal buffer and line drivers which improve the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. 2A3 1Y3 20-Lead Flatpack Top View 1G 1 20 The devices are characterized over full military temperature range of -55 C to +125 C. 1A1 2 19 2G 2Y4 3 18 1Y1 FUNCTION TABLE 1A2 2Y3 4 17 5 16 2A4 1Y2 INPUTS OUTPUT VDD 1A3 6 15 2A3 1G, 2G A Y 2Y2 7 14 1Y3 L L H 1A4 2Y1 VSS 8 13 9 12 10 11 2A2 1Y4 2A1 L H L H X Z LOGIC SYMBOL 1G (1) EN (2) (18) (4) 1A2 (6) 1A3 (8) 1A4 (16) 1A1 2G (19) (14) (12) 1Y2 1Y3 1Y4 EN (11) (9) (13) 2A2 (15) 2A3 (17) 2A4 (7) 2A1 1Y1 (5) (3) 2Y1 2Y2 2Y3 2Y4 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 153 RadHard MSI Logic UT54ACS240/UT54ACTS240 LOGIC DIAGRAM 2G (19) 1G (1) 1A1 1A2 1A3 1A4 (2) (18) (4) (16) (6) (14) (8) (12) 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 (11) (9) (13) (7) (15) (5) (17) (3) 2Y1 2Y2 2Y3 2Y4 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 154 UT54ACS240/UT54ACTS240 RECOMMENDED OPERATING CONDITIONS 155 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS240/UT54ACTS240 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 12.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -12.0mA IOH = -100 A IOZ Three-state output leakage current VO = VDD and VSS -30 30 A IOS Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -300 300 mA Output current10 VIN = VDD or VSS 12 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -12 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.1 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 156 UT54ACS240/UT54ACTS240 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 157 RadHard MSI Logic UT54ACS240/UT54ACTS240 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Input to Yn 1 10 ns tPHL Input to Yn 1 13 ns tPZL G low to Yn active 1 11 ns tPZH G low to Yn active 2 13 ns tPLZ G high to Yn three-state 2 11 ns tPHZ G high to Yn three-state 2 14 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 158 UT54ACS244/UT54ACTS244 Radiation-Hardened Octal Buffers & Line Drivers, Three-State Outputs FEATURES PINOUTS 20-Pin DIP Top View Three-state outputs drive bus lines or buffer memory address registers radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack DESCRIPTION The UT54ACS244 and the UT54ACTS244 are non-inverting octal buffer and line drivers which improve the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. 1 20 2 19 VDD 2G 2Y4 3 18 1Y1 1A2 4 17 2A4 2Y3 5 16 1Y2 1A3 2Y2 6 15 7 14 2A3 1Y3 1A4 2Y1 8 13 9 12 2A2 1Y4 VSS 10 11 2A1 20-Lead Flatpack Top View 1G 1 20 1A1 2 19 2G 2Y4 3 18 1Y1 1A2 2Y3 4 17 OUTPUT 5 16 2A4 1Y2 The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS 1G 1A1 VDD 1G, 2G A Y 1A3 6 15 2A3 L L L 2Y2 7 14 1Y3 L H H 1A4 2Y1 VSS 8 13 9 12 10 11 2A2 1Y4 2A1 H X Z LOGIC SYMBOL 1G (1) EN (2) (18) (4) 1A2 (6) 1A3 (8) 1A4 (16) 1A1 2G (19) (14) (12) 1Y2 1Y3 1Y4 EN (11) (9) (13) 2A2 (15) 2A3 (17) 2A4 (7) 2A1 1Y1 (5) (3) 2Y1 2Y2 2Y3 2Y4 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 159 RadHard MSI Logic UT54ACS244/UT54ACTS244 LOGIC DIAGRAM 1G (1) 1A1 1A2 1A3 1A4 2G (19) (2) (18) (4) (16) (6) (14) (8) (12) 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 (11) (9) (13) (7) (15) (5) (17) (3) 2Y1 2Y2 2Y3 2Y4 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 160 UT54ACS244/UT54ACTS244 RECOMMENDED OPERATING CONDITIONS 161 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS244/UT54ACTS244 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 12.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -12.0mA IOH = -100 A Output current10 VIN = VDD or VSS (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS (Source) VOH = VDD - 0.4V IOZ Three-state output leakage current VO = VDD and VSS -30 30 A IOS Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -300 300 mA Ptotal Power dissipation 2,8,9 CL = 50pF 2.0 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 12 mA -12 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 162 UT54ACS244/UT54ACTS244 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 163 RadHard MSI Logic UT54ACS244/UT54ACTS244 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Input to Yn 1 11 ns tPHL Input to Yn 1 11 ns tPZL G low to Yn active 2 12 ns tPZH G low to Yn active 2 12 ns tPLZ G high to Yn three-state 2 12 ns tPHZ G high to Yn three-state 2 12 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 164 UT54ACS245/UT54ACTS245 Radiation-Hardened Octal Bus Transceiver with Three-State Outputs FEATURES PINOUTS 20-Pin DIP Top View Three-state outputs drive bus line directly radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack DIR A1 1 2 20 19 VDD G A2 3 18 B1 A3 4 17 B2 A4 5 16 B3 A5 A6 6 7 15 14 B4 B5 A7 A8 8 9 13 12 B6 B7 VSS 10 11 B8 DESCRIPTION The UT54ACS245 and the UT54ACTS245 are non-inverting octal bus transceivers designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction control (DIR) input. The enable input (G) disables the device so that the buses are effectively isolated. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE ENABLE G DIRECTION CONTROL DIR OPERATION L L B Data To A Bus L H A Data To B Bus H X Isolation 20-Lead Flatpack Top View DIR 1 20 VDD A1 2 19 G A2 3 18 B1 A3 A4 4 5 17 16 B2 B3 A5 6 15 B4 A6 7 14 B5 A7 A8 VSS 8 9 10 13 12 11 B6 B7 B8 LOGIC SYMBOL G DIR A1 A2 A3 A4 A5 A6 A7 A8 (19) (1) (2) (3) G3 3 EN1 (BA) 3 EN2 (AB) (18) 1 B1 2 (17) (4) (16) (5) (6) (15) (7) (8) (9) (14) B2 B3 B4 B5 (13) B6 (12) B7 (11) B8 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 165 RadHard MSI Logic UT54ACS245/UT54ACTS245 LOGIC DIAGRAM DIR (1) (19) A1 (18) A2 B7 (9) (11) RadHard MSI Logic B6 (8) (12) A8 B5 (7) (13) A7 B4 (6) (14) A6 B3 (5) (15) A5 B2 (4) (16) A4 B1 (3) (17) A3 G (2) B8 166 UT54ACS245/UT54ACTS245 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 167 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS245/UT54ACTS245 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 12.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -12.0mA IOH = -100 A IOZ Three-state output leakage current VO = VDD and VSS -30 30 A IOS Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -300 300 mA Output current10 VIN = VDD or VSS 12 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -12 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.0 mW/MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 168 UT54ACS245/UT54ACTS245 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 169 RadHard MSI Logic UT54ACS245/UT54ACTS245 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Data to bus 1 11 ns tPHL Data to bus 1 15 ns tPZL G low to bus active 2 12 ns tPZH G low to bus active 2 12 ns tPLZ G high to bus three-state 2 12 ns tPHZ G high to bus three-state 2 12 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) RadHard MSI Logic 170 UT54ACS253/UT54ACTS253 Radiation-Hardened Dual 4-Input Multiplexers, Three-State Outputs FEATURES PINOUTS 16-Pin DIP Top View Permits multiplexing from N lines to 1 line Performs parallel-to-serial conversion radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package -16-pin DIP -16-lead flatpack 1G 1 16 VDD B 1C3 1C2 1C1 1C0 1Y VSS 2 3 4 5 6 7 8 15 14 13 12 11 10 9 2G A 2C3 2C2 2C1 2C0 2Y DESCRIPTION The UT54ACS253 and the UT54ACTS253 are 1-line to 4-line multiplexers that contain drivers to supply full binary decoding. Separate output control inputs are provided for each of the two four-line sections. Use the three-state outputs to drive data lines in bus-organized systems. With all but one of the common outputs disabled the low-impedance of the single enable output will drive the bus line to a high or low logic level. Each output has its own strobe (G). The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE SELECT INPUTS 1G 1 16 VDD B 2 15 2G 1C3 3 14 A 1C2 4 2C3 1C1 5 13 12 1C0 6 11 2C1 1Y VSS 7 8 10 9 2C0 2Y 2C2 LOGIC SYMBOL DATA INPUTS OUTPUT CONTROL OUTPUT B A C0 C1 C2 C3 G Y X X X X X X H Z L L L X X X L L L L H X X X L H L H X L X X L L L H X H X X L H H L X X L X L L H L X X H X L H H H X X X L L L H H X X X H L H 177 16-Lead Flatpack Top View A B 1G 1C0 1C1 1C2 1C3 (14) (2) 0 1 0 3 G --- (1) (6) (5) (4) (3) (15) 2G (10) 2C0 (11) 2C1 (12) 2C2 (13) 2C3 EN 0 1 2 MUX (7) 1Y 3 (9) 2Y Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. RadHard MSI Logic UT54ACS253/UT54ACTS253 LOGIC DIAGRAM OUTPUT CONTROL (1) 1G 1C0 (6) 1C1 DATA 1 1C2 1C3 B SELECT (5) (7) 1Y (4) (3) (2) A (14) 2C0 (10) 2C1 (11) DATA 2 (9) 2C2 2C3 2G (12) 2Y (13) (15) OUTPUT CONTROL RadHard MSI Logic 178 UT54ACS253/UT54ACTS253 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 179 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS253/UT54ACTS253 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 200 mA Three-state output leakage current VO = VDD and VSS -20 20 A Quiescent Supply Current VDD = 5.5V 10 A Output current10 VIN = VDD or VSS (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.1 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOZ IDDQ IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 8 mA -8 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 180 UT54ACS253/UT54ACTS253 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 181 RadHard MSI Logic UT54ACS253/UT54ACTS253 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Select to output Yn 2 12 ns tPHL Select to output Yn 2 16 ns tPLH Data to output Yn 2 14 ns tPHL Data to output Yn 2 16 ns tPZH G low to Yn active 2 12 ns tPZL G low to Yn active 1 12 ns tPHZ G high to Yn three-state 2 11 ns tPLZ G high to Yn three-state 2 10 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 182 UT54ACS264/UT54ACTS264 Radiation-Hardened Look-Ahead Carry Generators for Counters FEATURES PINOUTS 16-Pin DIP Top View Performs look-ahead carry across n-bit counters Accommodates active-high or active-low carry Improves cascaded counters system performance radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack A1 1 16 VDD B1 2 15 B2 A0 3 14 A2 B0 4 CE A3 5 13 12 B3 RCOB 6 7 11 10 C1 RCOA VSS 8 9 C0 C2 DESCRIPTION The UT54ACS264 and the UT54ACTS264 are look-ahead generators designed specifically to perform a carry-anticipate across any number of n-bit counters, thus increasing system clock frequency. A carry enable CE, and carry outputs RCOA and RCOB are provided for n-bit cascading. Use the counter with either active-high-carry or active-low-carry counters. For active-high-carry counters, CE is active high, the A set of inputs and output RCOA are used. The B set of inputs are connected to a low logic level. For active-low-carry counters, CE is active low, the B set of inputs and output RCOB are used. The A set of inputs are connected to a high logic level. 16-Lead Flatpack Top View A1 1 16 VDD B1 2 15 B2 A0 3 14 A2 B0 4 13 CE A3 5 12 C0 B3 6 11 C1 RCOB VSS 7 8 10 9 RCOA C2 The devices are characterized over full military temperature range of -55 C to +125 C. 183 RadHard MSI Logic UT54ACS264/UT54ACTS264 LOGIC SYMBOL ACTIVE-LOW INPUTS ACTIVE-HIGH INPUTS CE B0 A0 B1 A1 B2 A2 B3 A3 (13) 1,3 2,3 1 1,3,5 2,3,5 4,5 1 1,3,5,7 2,3,5,7 4,5,7 6,7 1 Z1 (4) Z2 (3) G3 (12) CE C1 A0 B1 (2) Z4 (1) G5 (15) Z6 (14) G7 (6) (9) C2 1,3,5,7, 4,5,7,9 6,7,9 8,9 1 2 4 6 8 1 A2 (10) RCOA Z8 (5) A1 B2 1 B3 A3 G9 (7) Z1 1,2 3 1 G2 5 3,4 1,2,4 1 7 5,6 3,4,6 1,2,4,6 1 C0 B0 (11) (13) (4) (3) Z3 (2) G4 (1) Z5 (15) (6) G8 (5) A0 B0 CE C0 H H X H H X H H L X X X L L L L FUNCTION TABLE FOR C1 OUTPUT INPUTS OUTPUT A1 A0 B1 B0 CE C1 H X H X X H H H X H X H H H X X H H L X X X X L X X L L X X L X L (7) RCOB FUNCTION TABLE FOR C2 OUTPUT INPUTS OUTPUT A2 A1 A0 B2 B1 B0 CE C2 H X X H X X X H H H X X H X X H H H H X X H X H H H H X X X H H L X X X X X X L X L X L X X X L X X L L L X X L X X X L L L L L INPUTS FUNCTION TABLE FOR RCOB OUTPUT OUTPUT B3 B2 B1 B0 CE RCOB H X X X X H X H X X X H X X H X X H X X X H X H X X X X H H L L L L L L RadHard MSI Logic RCOA RCOB A3 L INPUTS C2 FUNCTION TABLE FOR RCOA OUTPUT L L C1 Z9 FUNCTION TABLE FOR C0 OUTPUT OUTPUT (10) 1,2,4,6,8 Notes: 1. Logic symbols in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. INPUTS C0 1 9 7,8 5,6,8 3,4,6,8 1,4,6,8 Z7 (11) (9) G6 (14) (12) A2 A1 A0 B3 H X X X H H X X H H H H H L X X L X X X OUTPUT B2 B1 CE RCOA H X X X H X H X X H X X X H X H H H X X X H H X X X X X X L X X L X X X L X L X L L X X L X X L L L L X L X X X L L L L L 184 UT54ACS264/UT54ACTS264 LOGIC DIAGRAM (7) RCOB (13) CE (10) RCOA B3 A3 (6) (5) (9) C2 B2 A2 (15) (14) (11) C1 B1 A1 (2) (1) (12) B0 A0 185 (4) C0 (3) RadHard MSI Logic UT54ACS264/UT54ACTS264 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 186 UT54ACS264/UT54ACTS264 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.2 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 187 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS264/UT54ACTS264 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH CE to C0, C1, C2 1 17 ns tPHL CE to C0, C1, C2 1 16 ns tPLH An or Bn to C0, C1, C2 1 15 ns tPHL An or Bn to C0, C1, C2 1 17 ns tPLH An, Bn or CE to RCOA 1 15 ns tPHL An, Bn or CE to RCOA 1 15 ns tPLH Bn or CE to RCOB 1 12 ns tPHL Bn or CE to RCOB 1 15 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 188 UT54ACS273/UT54ACTS273 Radiation-Hardened Octal D-Flip-Flops with Clear FEATURES PINOUTS 20-Pin DIP Top View Contains eight flip-flops with single-rail outputs Buffered clock and direct clear inputs Individual data input to each flip-flop Applications include: - Buffer/storage registers, shift registers, and pattern generators radiation-hardened CMOS - Latchup immune High speed CLR 1Q 1 2 20 19 VDD 8Q 1D 3 18 8D 2D 4 17 7D 2Q 5 16 7Q 3Q 3D 6 7 15 14 6Q 6D 4D 4Q 8 9 13 12 5D 5Q VSS 10 11 CLK Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack 20-Lead Flatpack Top View DESCRIPTION The UT54ACS273 and the UT54ACTS273 are positive-edgetriggered D-type flip-flops with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE CLR 1 20 VDD 1Q 2 19 8Q 1D 3 18 8D 2D 2Q 4 5 17 16 7D 7Q 3Q 6 15 6Q 3D 7 14 6D 4D 4Q VSS 8 9 10 13 12 11 5D 5Q CLK LOGIC SYMBOL INPUTS OUTPUTS CLR CLK Dx Qx L X X L CLR CLK H H 1D H H H L L L X No change 2D 3D 4D 5D 6D 7D 8D (1) (11) R C1 (2) (3) (4) (7) (8) (13) (14) (17) (18) 1D (5) (6) 1Q 2Q 3Q (9) 4Q (12) 5Q (15) 6Q (16) 7Q (19) 8Q Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 189 RadHard MSI Logic UT54ACS273/UT54ACTS273 LOGIC DIAGRAM 1D (3) (11) CLK 2D (4) D C 4D (8) 5D (13) 6D (14) D D D C D C D C R CLR 3D (7) C C R R R R 7D (17) 8D (18) D D C C R R R (1) (2) (5) 1Q 2Q (6) (9) 3Q RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER 4Q (12) 5Q (16) (15) 7Q 6Q LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 (19) 8Q Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 190 UT54ACS273/UT54ACTS273 RECOMMENDED OPERATING CONDITIONS 191 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS273/UT54ACTS273 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 192 UT54ACS273/UT54ACTS273 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 193 RadHard MSI Logic UT54ACS273/UT54ACTS273 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH CLK to Q 4 17 ns tPHL CLK to Q 4 19 ns tPHL CLR to Q 5 19 ns fMAX Maximum clock frequency 63 MHz tSU1 CLR inactive setup time before CLK 5 ns tSU2 Data setup time before CLK 5 ns tH Data hold time after CLK 3 ns tW Minimum pulse width CLR low CLK high CLK low 8 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 194 UT54ACS279/UT54ACTS279 Radiation-Hardened Quadruple S-R Latches FEATURES PINOUTS 16-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply 1R 1 16 VDD 1S1 2 15 4S 1S2 3 14 4R 1Q 2R 4 5 13 12 4Q 3S2 2S 2Q 6 7 11 10 3S1 3R VSS 8 9 3Q Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UT54ACS279 and the UT54ACTS279 contain four basic S-R flip-flop latches. Under conventional operation, the S-R inputs are normally held high. When the S input is pulsed low, the Q output will be set high. When R is pulsed low, the Q output will be reset low. If the S-R inputs are taken low simultaneously, the Q output is unpredictable. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS OUTPUT S R Q H H Q0 L H H H L L L L H1 LOGIC DIAGRAM (LATCHES 1 & 3) S1 S2 195 1R 1 16 VDD 1S1 2 15 4S 1S2 3 14 4R 1Q 4 13 4Q 2R 5 12 3S2 2S 6 11 3S1 2Q VSS 7 8 10 9 3R 3Q LOGIC SYMBOL Note: 1. This configuration is nonstable. It may not persist when the S and R inputs return to their inactive (high) level. (LATCHES 2 & 4) R 16-Lead Flatpack Top View R (1) 1R (2) 1S1 (3) 1S2 (5) 2R (6) 2S (10) 3R (11) 3S1 (12) 3S2 (14) 4R (15) 4S R S1 S1 R S2 R S3 S3 R S4 (4) (7) (9) (13) 1Q 2Q 3Q 4Q Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. Q S Q RadHard MSI Logic UT54ACS279/UT54ACTS279 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 196 UT54ACS279/UT54ACTS279 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 12.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -12.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -300 Output current10 VIN = VDD or VSS 12 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -12 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.1 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 300 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 197 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS279/UT54ACTS279 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH S to Q 1 15 ns tPHL S to Q 1 18 ns tPHL R to Q 1 17 ns Minimum pulse width S low R low 8 tW ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 198 UT54ACS280/UT54ACTS280 Radiation-Hardened 9-Bit Parity Generators/Checkers FEATURES PINOUTS 14-Pin DIP Top View Generates either odd or even parity for nine data lines Cascadable for n-bits parity radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack DESCRIPTION The UT54ACS280 and the UT54ACTS280 are 9-bit parity generators/checkers that use high-performance circuitry and features odd and even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE NUMBER OF INPUTS A THRU I THAT ARE HIGH G 1 14 VDD H 2 13 F NC 3 12 E I EVEN 4 5 11 10 D C ODD VSS 6 7 9 8 B A 14-Lead Flatpack Top View G 1 14 VDD H 2 13 F NC 3 12 E I 4 11 EVEN 5 10 D C ODD VSS 6 9 B 7 8 A OUTPUT EVEN ODD 0,2,4,6,8 H L 1,3,5,7,9 L H LOGIC SYMBOL A B C D E F G H I (8) 2k (9) (10) (11) (12) (5) EVEN (13) (1) (2) (6) ODD (4) Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 199 RadHard MSI Logic UT54ACS280/UT54ACTS280 LOGIC DIAGRAM A (8) ( B (9) C (10) (5) EVEN D E F (11) (12) (13) (6) ODD (1) G (2) H (4) I RadHard MSI Logic 200 UT54ACS280/UT54ACTS280 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Input voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 201 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS280/UT54ACTS280 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.2 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 202 UT54ACS280/UT54ACTS280 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 203 RadHard MSI Logic UT54ACS280/UT54ACTS280 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Any input to even 1 20 ns tPHL Any input to even 1 20 ns tPHL Any input to odd 1 22 ns tPLH Any input to odd 1 20 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 204 UT54ACS283/UT54ACTS283 Radiation-Hardened 4-Bit Binary Full Adders FEATURES PINOUTS 16-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UT54ACS283 and the UT54ACTS283 are 4-bit binary adders. The adders perform addition of two 4-bit binary words. The sum ( ) outputs are provided for each bit and the resultant carry (C4) is obtained as the fifth bit. The adders feature full internal look-ahead across all four bits for fast carry generation. The devices are characterized over full military temperature range of -55 C to +125 C. LOGIC SYMBOL A1 A2 A3 A4 B1 B2 B3 B4 C0 (5) (3) (14) (12) (6) (2) P (7) Q 3 3 C1 (1) (13) 0 (15) (11) 16 VDD B2 2 15 B3 A2 3 14 A3 1 A1 4 13 5 12 3 A4 B1 6 11 B4 C0 7 10 4 VSS 8 9 C4 1 16 VDD 2 15 B3 A2 3 14 A3 1 A1 4 5 13 12 3 A4 B1 C0 6 11 B4 7 8 10 9 4 C4 2 B2 (4) 0 3 1 16-Lead Flatpack Top View VSS 0 2 C0 (10) 1 2 3 4 (9) C4 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 205 RadHard MSI Logic UT54ACS283/UT54ACTS283 FUNCTION TABLE INPUT OUTPUT When C0 = L A1 A3 B1 B3 A2 A4 B2 B4 1 3 When C2 = L 2 4 C2 C4 When C0 = H 1 3 When C2 = H 2 4 C2 C4 L L L L L L L H L L H L L L H L L L H L L H L L H L L L H L H H L L L H L H H L L L H L L H L H H L H L H L H H L L L H L H H L H H L L L H H H H L L L H H L H L L L H L H L H H L H L L H H H L L L H L H L H H H L L L H H H L H L L H H L H L L H H L L H H L H H L H H H L H L H H L H H H H L H L H H H H H H L H H H H H H = high level, L = low level Note: Input conditions at A1, A2, B1, B2, and C0 are used to determine outputs 1 and 2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and B4 are then used to determine outputs 3, 4, and C4. RadHard MSI Logic 206 UT54ACS283/UT54ACTS283 LOGIC DIAGRAM (9) C4 B4 (11) A4 (12) B3 (15) A3 (14) B2 (2) A2 (3) B1 (6) A1 (5) C0 (7) (10) (13) (1) 207 (4) RadHard MSI Logic UT54ACS283/UT54ACTS283 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 208 UT54ACS283/UT54ACTS283 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 209 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS283/UT54ACTS283 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay C0 to n 2 16 ns tPHL Propagation delay C0 to n 2 19 ns tPLH Propagation delay C0 to C4 2 16 ns tPHL Propagation delay C0 to C4 2 17 ns tPLH Propagation delay An, Bn to C4 2 16 ns tPHL Propagation delay An, Bn to C4 2 15 ns tPLH Propagation delay An, Bn to n 2 14 ns tPHL Propagation delay An, Bn to n 2 16 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 210 UT54ACS365/UT54ACTS365 Radiation-Hardened Hex Buffers/Line Drivers with Three-State Outputs FEATURES PINOUTS 16-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UT54ACS365 and UT54ACTS365 are non-inverting hex buffer and line driver with three-state outputs. The output enables (OE1 and OE2) control the three-state outputs. If OE1 or OE2 is high, the outputs will be in a high impedance state. For data, both OE1 and OE2 must be low. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS OE1 OE2 A OE1 1 16 VDD A1 2 15 OE2 Y1 3 14 A6 A2 4 13 Y6 Y2 5 12 A5 A3 Y3 6 11 7 10 Y5 A4 VSS 8 9 Y4 16-Lead Flatpack Top View OE1 1 16 VDD A1 2 15 OE2 Y1 3 14 A6 A2 Y2 4 5 13 12 Y6 OUTPUT Y A3 6 11 Y5 Y3 VSS 7 8 10 9 A4 Y4 L L L L L L H H X H X Z H X X Z A5 LOGIC SYMBOL OE1 OE2 A1 A2 A3 A4 A5 A6 (1) (15) & EN (2) (3) (4) (5) (6) (7) (10) (9) (12) (11) (14) (13) Y1 Y2 Y3 Y4 Y5 Y6 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 211 RadHard MSI Logic UT54ACS365/UT54ACTS365 LOGIC DIAGRAM OE2 (15) A6 A5 A4 A3 A2 (12) (10) (6) (4) (2) (13) (11) (9) (7) (5) (3) Y5 Y4 Y3 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER (1) A1 (14) Y6 OE1 Y2 Y1 LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 212 UT54ACS365/UT54ACTS365 RECOMMENDED OPERATING CONDITIONS 213 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS365/UT54ACTS365 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 12.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -12.0mA IOH = -100 A IOZ Three-state output leakage current VO = VDD and VSS -30 30 A IOS Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -300 300 mA Output current10 VIN = VDD or VSS 12 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -12 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.8 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 214 UT54ACS365/UT54ACTS365 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 215 RadHard MSI Logic UT54ACS365/UT54ACTS365 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Data to output 2 11 ns tPHL Data to output 2 13 ns tPZL OE low to output active 2 14 ns tPZH OE low to output active 2 15 ns tPLZ OE high to output three-state 2 12 ns tPHZ OE high to output three-state 2 14 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 216 UT54ACS365/UT54ACTS365 Radiation-Hardened Hex Buffers/Line Drivers with Three-State Outputs FEATURES PINOUTS 16-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UT54ACS365 and UT54ACTS365 are non-inverting hex buffer and line driver with three-state outputs. The output enables (OE1 and OE2) control the three-state outputs. If OE1 or OE2 is high, the outputs will be in a high impedance state. For data, both OE1 and OE2 must be low. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS OE1 OE2 A OE1 1 16 VDD A1 2 15 OE2 Y1 3 14 A6 A2 4 13 Y6 Y2 5 12 A5 A3 Y3 6 11 7 10 Y5 A4 VSS 8 9 Y4 16-Lead Flatpack Top View OE1 1 16 VDD A1 2 15 OE2 Y1 3 14 A6 A2 Y2 4 5 13 12 Y6 OUTPUT Y A3 6 11 Y5 Y3 VSS 7 8 10 9 A4 Y4 L L L L L L H H X H X Z H X X Z A5 LOGIC SYMBOL OE1 OE2 A1 A2 A3 A4 A5 A6 (1) (15) & EN (2) (3) (4) (5) (6) (7) (10) (9) (12) (11) (14) (13) Y1 Y2 Y3 Y4 Y5 Y6 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 211 RadHard MSI Logic UT54ACS365/UT54ACTS365 LOGIC DIAGRAM OE2 (15) A6 A5 A4 A3 A2 (12) (10) (6) (4) (2) (13) (11) (9) (7) (5) (3) Y5 Y4 Y3 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER (1) A1 (14) Y6 OE1 Y2 Y1 LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 212 UT54ACS365/UT54ACTS365 RECOMMENDED OPERATING CONDITIONS 213 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS365/UT54ACTS365 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 12.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -12.0mA IOH = -100 A IOZ Three-state output leakage current VO = VDD and VSS -30 30 A IOS Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -300 300 mA Output current10 VIN = VDD or VSS 12 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -12 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.8 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 214 UT54ACS365/UT54ACTS365 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 215 RadHard MSI Logic UT54ACS365/UT54ACTS365 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Data to output 2 11 ns tPHL Data to output 2 13 ns tPZL OE low to output active 2 14 ns tPZH OE low to output active 2 15 ns tPLZ OE high to output three-state 2 12 ns tPHZ OE high to output three-state 2 14 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 216 UT54ACS373/UT54ACTS373 Radiation-Hardened Octal Transparent Latches with Three-State Outputs FEATURES PINOUTS 20-Pin DIP Top View 8 latches in a single package Three-state bus-driving true outputs Full parallel access for loading radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack OC 1Q 1 2 20 19 VDD 8Q 1D 2D 3 18 8D 4 17 7D 2Q 5 16 7Q 3Q 3D 6 7 15 14 6Q 6D 4D 4Q 8 9 13 12 5D 5Q 10 11 C VSS DESCRIPTION 20-Lead Flatpack Top View The UT54ACS373 and the UT54ACTS373 are 8-bit latches with three-state outputs designed for driving highly capacitive or relatively low-impedance loads. The device is suitable for buffer registers, I/O ports, and bidirectional bus drivers. The eight latches are transparent D latches. While the enable (C) is high the Q outputs will follow the data (D) inputs. When the enable is taken low, the Q outputs will be latched at the levels that were set up at the D inputs. An output-control input (OC) places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The high-impedance third state and increased drive provide the capability to drive the bus line in a bus-organized system without need for interface or pull-up components. The output control OC does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS OC C nD nQ L H H H L H L L L L X nQ0 H X X Z1 Note: 1. Data may be latched internally. 217 OUTPUT OC 1 20 VDD 1Q 2 19 8Q 1D 3 18 8D 2D 2Q 4 5 17 16 7D 7Q 3Q 6 15 6Q 3D 7 14 6D 4D 4Q VSS 8 9 10 13 12 11 5D 5Q C LOGIC SYMBOL OC C (1) (11) 1D (3) (4) 2D 3D (7) (8) 4D 5D (13) 6D (14) 7D (17) 8D (18) EN C1 1D (2) 1Q (5) 2Q (6) 3Q (9) (12) (15) (16) (19) 4Q 5Q 6Q 7Q 8Q Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. RadHard MSI Logic UT54ACS373/UT54ACTS373 LOGIC DIAGRAM 8D 7D (18) 6D (17) 5D (14) 4D (13) 3D (8) 2D 1D C (7) (4) (3) DC DC DC DC D C D C D C DC Q Q Q Q Q Q Q Q (19) 8Q (16) 7Q (15) 6Q (12) 5Q (9) 4Q (6) 3Q (5) 2Q OC (11) (1) (2) 1Q RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATING SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 218 UT54ACS373/UT54ACTS373 RECOMMENDED OPERATING CONDITIONS 219 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 ×C RadHard MSI Logic UT54ACS373/UT54ACTS373 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A IOZ Three-state output leakage current VO = VDD and VSS -20 20 A IOS Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 200 mA Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 220 UT54ACS373/UT54ACTS373 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 221 RadHard MSI Logic UT54ACS373/UT54ACTS373 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Data to Qn 1 14 ns tPHL Data to Qn 1 16 ns tPLH C to Qn 1 16 ns tPHL C to Qn 1 18 ns tPZL OC low to Qn 1 14 ns tPZH OC low to Qn 1 14 ns tPLZ OC high to Qn three-state 1 14 ns tPHZ OC high to Qn three-state 1 14 ns fMAX Maximum clock frequency 71 MHz tSU Data setup time before C 5 ns tH Data hold time after C 4 ns tW Minimum pulse width C high 7 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 222 UT54ACS374/UT54ACTS374 Radiation-Hardened Octal D-Type Flip-Flops with Three-State Outputs PINOUTS FEATURES 20-Pin DIP Top View 8 latches in a single package Three-state bus-driving true outputs Full parallel access for loading radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack OC 1Q 1 2 20 19 VDD 8Q 1D 2D 3 18 8D 4 17 7D 2Q 5 16 7Q 3Q 3D 6 7 15 14 6Q 6D 4D 4Q 8 9 13 12 5D 5Q 10 11 CLK VSS DESCRIPTION 20-Lead Flatpack Top View The UT54ACS374 and the UT54ACTS374 are non-inverting octal D type flip-flops with three-state outputs designed for driving highly capacitive or relatively low-impedance loads. The device is suitable for buffer registers, I/O ports, and bidirectional bus drivers. The eight flip-flops are edge triggered D-type flip-flops. On the positive transition of the clock the Q outputs will follow the data (D) inputs. An output-control input (OC) places the eight outputs in either a normal logic state (high or low logic level) or a high-impedance state. The high-impedance third state and increased drive provide the capability to drive the bus line in a bus-organized system without the need for interface or pull-up components. The output control OC does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off. OC 1 20 VDD 1Q 2 19 8Q 1D 3 18 8D 2D 2Q 4 5 17 16 7D 7Q 3Q 6 15 6Q 3D 7 14 6D 4D 4Q VSS 8 9 10 13 12 11 5D 5Q CLK LOGIC SYMBOL OC CLK (1) (11) EN C1 The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS OC 223 CLK OUTPUT nD nQ L H H L L L L L X nQ0 H X X Z 1D (3) (4) 2D 3D (7) (8) 4D 5D (13) 6D (14) 7D (17) 8D (18) 1D (2) 1Q (5) 2Q (6) 3Q (9) 4Q (12) 5Q (15) 6Q (16) 7Q (19) 8Q Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. RadHard MSI Logic UT54ACS374/UT54ACTS374 LOGIC DIAGRAM 8D 7D (18) 6D (17) 5D (14) 4D (13) 3D (8) 2D CLK OC 1D (7) (4) (3) DC D C DC D C D C D C D C D C Q Q Q Q Q Q Q Q (19) 8Q (16) 7Q (15) 6Q (12) 5Q (9) 4Q (6) 3Q (5) 2Q (11) (1) (2) 1Q RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATING SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 224 UT54ACS374/UT54ACTS374 RECOMMENDED OPERATING CONDITIONS 225 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 ×C RadHard MSI Logic UT54ACS374/UT54ACTS374 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A IOZ Three-state output leakage current VO = VDD and VSS -20 20 A IOS Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 200 mA Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 226 UT54ACS374/UT54ACTS374 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 227 RadHard MSI Logic UT54ACS374/UT54ACTS374 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH CLK to Qn 1 15 ns tPHL CLK to Qn 1 18 ns tPZL OC low to Qn active 1 13 ns tPZH OC low to Qn active 1 13 ns tPLZ OC high to Qn three-state 1 11 ns tPHZ OC high to Qn three-state 1 12 ns fMAX Maximum clock frequency 71 MHz tSU Data setup time before CLK 5 ns tH Data hold time after CLK 2 ns tW Minimum pulse width CLK high, CLK low 7 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 228 UT54ACS540/UT54ACTS540 Radiation-Hardened Octal Buffers & Line Drivers, Inverted Three-State Outputs FEATURES PINOUTS Three-state outputs drive bus lines or buffer memory address registers radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack DESCRIPTION The UT54ACS540 and the UT54ACTS540 are inverting octal buffers and line drivers which improve the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS OUTPUT 20-Pin DIP Top View 1G A1 1 20 2 19 VDD 2G A2 3 18 Y1 A3 4 17 Y2 A4 5 16 Y3 A5 A6 6 15 7 14 Y4 Y5 A7 A8 8 13 9 12 Y6 Y7 VSS 10 11 Y8 20-Lead Flatpack Top View 1G 1 20 VDD A1 2 19 2G A2 3 18 Y1 A3 A4 4 17 5 16 Y2 Y3 A5 6 15 Y4 1G 2G An Yn A6 7 14 Y5 L L L H A7 A8 VSS 8 13 9 12 10 11 Y6 Y7 Y8 L L H L H X X Z X H X Z LOGIC SYMBOL 1G 2G (1) (19) A1 (2) (3) A2 A3 (4) (5) A4 (6) A5 A6 (7) A7 (8) A8 (9) & EN (18) Y1 (17) Y2 (16) Y3 (15) Y4 (14) Y5 (13) Y6 (12) Y7 (11) Y8 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 229 RadHard MSI Logic UT54ACS540/UT54ACTS540 LOGIC DIAGRAM A8 (9) (11) Y8 A6 A7 (7) (8) (13) (12) Y6 Y7 A5 A4 (6) (5) (14) Y5 (15) Y4 A3 (4) (16) Y3 A2 A1 (3) 2G 1G (2) (19) (17) (1) (18) Y2 Y1 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table .2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 230 UT54ACS540/UT54ACTS540 RECOMMENDED OPERATING CONDITIONS 231 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic UT54ACS540/UT54ACTS540 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 12.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -12.0mA IOH = -100 A IOZ Three-state output leakage current VO = VDD and VSS -30 30 A IOS Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -300 300 mA Output current10 VIN = VDD or VSS 12 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -12 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.1 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic 232 UT54ACS540/UT54ACTS540 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 233 RadHard MSI Logic UT54ACS540/UT54ACTS540 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH An to Yn 1 12 ns tPHL An to Yn 1 13 ns tPZL G low to Yn active 2 14 ns tPZH G low to Yn active 2 15 ns tPLZ G high to Yn three-state 2 13 ns tPHZ G high to Yn three-state 2 14 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 234 UT54ACS541/UT54ACTS541 Radiation-Hardened Octal Buffers & Line Drivers, Three-State Outputs Dec. 1, 2003 PINOUTS FEATURES • Three-state outputs drive bus lines or buffer memory address registers • 1.2µ radiation-hardened CMOS (ACS541) and 0.6µ CRH CMOS process (ACTS541) - Latchup immune • High speed • Low power consumption • Single 5 volt supply • Available QML Q or V processes • Flexible package - 20-pin DIP (not available for the ACTS541) - 20-lead flatpack 20-Pin DIP Top View DESCRIPTION The UT54ACS541 and the UT54ACTS541 are non-inverting octal buffers and line drivers which improve the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The devices are characterized over full military temperature range of -55°C to +125°C. FUNCTION TABLE INPUTS OUTPUT 1G 2G An Yn L L L L L L H H H X X Z X H X Z 1G A1 1 20 2 19 VDD 2G A2 3 18 Y1 A3 4 17 Y2 A4 5 16 Y3 A5 A6 6 15 7 14 Y4 Y5 A7 A8 8 13 9 12 Y6 Y7 VSS 10 11 Y8 20-Lead Flatpack Top View 1G 1 20 VDD A1 2 19 2G A2 3 18 Y1 A3 A4 4 17 5 16 Y2 Y3 A5 6 15 Y4 A6 7 14 Y5 A7 A8 VSS 8 13 9 12 10 11 Y6 Y7 Y8 LOGIC SYMBOL 1G 2G (1) (19) A1 (2) (3) A2 A3 (4) (5) A4 A5 (6) A6 (7) A7 (8) A8 (9) & EN (18) Y1 (17) Y2 (16) Y3 (15) (14) (13) (12) (11) Y4 Y5 Y6 Y7 Y8 Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 235 RadHard MSI Logic UT54ACS541/UT54ACTS541 LOGIC DIAGRAM A8 (9) (11) Y8 A6 A7 (7) (8) (13) (12) Y6 Y7 A5 A4 (6) (5) (14) Y5 (15) Y4 A3 (4) (16) Y3 A2 A1 (3) 2G 1G (2) (19) (17) (1) (18) Y2 Y1 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 (ACS541) 5.0E5 (ACTS541) rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C TLS Lead temperature (soldering 5 seconds) +300 °C ΘJC Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RadHard MSI Logic 236 UT54ACS541/UT54ACTS541 RECOMMENDED OPERATING CONDITIONS 237 SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 °C RadHard MSI Logic UT54ACS541/UT54ACTS541 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 12.0mA IOL = 100µA High-level output voltage 3 ACTS ACS IOH = -12.0mA IOH = -100µA IOZ Three-state output leakage current VO = VDD and VSS -30 30 µA IOS Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -300 300 mA Output current10 VIN = VDD or VSS 12 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -12 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 2.1 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 µA Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOL IOH ∆IDDQ ACTS -1 1 µA 0.40 0.25 V .7VDD VDD - 0.25 V VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 ƒ = 1MHz @ 0V 15 pF Output capacitance 5 ƒ = 1MHz @ 0V 15 pF RadHard MSI Logic 238 UT54ACS541/UT54ACTS541 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All ACS specifications are valid for radiation dose <1E6 rads(Si), and all ACTS specifications are valid for radiation dose <5E5 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 239 RadHard MSI Logic UT54ACS541/UT54ACTS541 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH An to Yn 1 11 ns tPHL An to Yn 1 14 ns tPZL G low to Yn active 2 14 ns tPZH G low to Yn active 2 15 ns tPLZ G high to Yn three-state 2 12 ns tPHZ G high to Yn three-state 2 13 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. For the ACTS version, all specifications are valid for radiation dose <1E6 rads(Si). For the ACTS version, all specifications are valid for radiation dose <5E5 rads(Si). RadHard MSI Logic 240 UT54ACS4002/UT54ACTS4002 Radiation-Hardened Dual 4-Input NOR Gates FEATURES PINOUTS 14-Pin DIP Top View radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack DESCRIPTION Y1 1 14 VDD A1 2 13 Y2 B1 3 12 D2 C1 D1 4 5 11 10 C2 B2 NC VSS 6 7 9 8 A2 NC The UT54ACS4002 and the UT54ACTS4002 are dual 4-input NOR gates. A high on any input forces the output to a low state. The circuits perform the Boolean functions: Y = A + B + C + D = A B C D. The devices are characterized over full military temperature range of -55 C to +125 C. FUNCTION TABLE INPUTS An Bn OUTPUT Cn Dn Yn L L L L H H X X X L X H X X L X X H X L X X X H L LOGIC SYMBOL A1 B1 C1 D1 A2 B2 C2 D2 (2) (3) (4) 1 (1) 14-Lead Flatpack Top View Y1 1 14 VDD A1 2 13 Y2 B1 3 12 D2 C1 4 11 C2 D1 5 10 B2 NC 6 9 A2 VSS 7 8 NC LOGIC DIAGRAM A1 B1 C1 D1 Y1 A2 B2 C2 D2 Y2 Y1 (5) (9) (10) (11) (13) Y2 (12) Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. 241 RadHard MSI Logic UT54ACS4002/UT54ACTS4002 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W JC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C RadHard MSI Logic 242 UT54ACS4002/UT54ACTS4002 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; V SS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = V DD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100 A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100 A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT 243 Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF RadHard MSI Logic UT54ACS4002/UT54ACTS4002 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH (min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; V SS = 0V 1, -55 C < TC < +125 C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPHL Input to output 1 12 ns tPLH Input to output 2 14 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). RadHard MSI Logic 244 2.0 RADHARD MSI PACKAGES Side-Brazed Packages 245 RadHard MSI Logic Flatpack Packages RadHard MSI Logic 246 3.0 ORDERING INFORMATION RadHard MSI - 14-Lead Packages: Military Temperature Range UT54 *** *** - * * * * Lead Finish: (See Notes 1 and 2) (A) = Solder (C) = Gold (X) = Optional Screening: (See Note 3) (C) = Mil Temp Package Type: (P) = 14-lead ceramic side-brazed DIP (U) = 14-lead ceramic bottom-brazed dual-in-line Flatpack Part Number: (See Note 4) (00) = Quadruple 2-input NAND (02) = Quadruple 2-input NOR (04) = Hex Inverter (08) = Quadruple 2-input AND (10) = Triple 3-input NAND (11) = Triple 3-input AND (14) = Hex inverter with Schmitt trigger (20) = Dual 4-input NAND (27) = Triple 3-input NOR (34) = Hex noninverting buffer (54) = 4-wide AND-OR Invert (74) = Dual D flip-flop with Clear and Preset (86) = Quadruple 2-input Exclusive OR (132) = Quadruple 2-input NAND Schmitt trigger (164) = 8-bit shift register (220) = Clock and wait-state (280) = 9-bit parity generator/checker (4002) = Dual 4-input NOR counter I/O Type: (ACS) = CMOS compatible I/O level (ACTS) = TTL compatible I/O level Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices have 48 hours of burn-in and are tested at -55C, room temperature, and 125C. Radiation characteristics are neither tested nor guaranteed and may not be specified. 4. The following devices are not available in a DIP package: UT54ACS14 and UT54ACS132. 247 RadHard MSI Logic ORDERING INFORMATION RadHard MSI - 16-Lead Packages: Military Temperature Range UT54 *** *** - * * * * Lead Finish: (See Notes 1 and 2) (A) = Solder (C) = Gold (X) = Optional Screening: (See Note 3) (C) = Mil Temp Package Type: (P) = 16-lead ceramic side-brazed DIP (U) = 16-lead ceramic bottom-brazed dual-in-line Flatpack Part Number: (See Note 4) (85) = 4-bit Comparator (109) = Dual J-K flip-flop (138) = 3-line to 8-line Decoder/demultiplexer (139) = Dual 2-line to 4-line Decoder/demultiplexer (151) = 1 of 8 data selector/multiplexer (153) = Dual 4 to 1 multiplexer (157) = Quadruple 2 to 1 multiplexer (163) = 4-bit synchronous counter (165) = 8-bit parallel shift register (169) = 4-bit up/down binary counter (190) = Synchronous 4-bit up/down BCD counter (191) = Synchronous 4-bit up/down Binary counter (193) = Synchronous 4-bit up/down Dual Clock counter (253) = Dual 4-input multiplexer (264) = Look-ahead carry genrator for counter (279) = Quadruple S-R latch (283) = 4-bit binary full adder (365) = Hex buffer/line driver with 3-sate outputs I/O Type: (ACS) = CMOS compatible I/O level (ACTS) = TTL compatible I/O level Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices have 48 hours of burn-in and are tested at -55C, room temperature, and 125C. Radiation characteristics are neither tested nor guaranteed and may not be specified. 4. The following devices are not available in a DIP package: UT54ACS109. RadHard MSI Logic 248 ORDERING INFORMATION RadHard MSI - 20-Lead Packages: Military Temperature Range UT54 *** *** - * * * * Lead Finish: (See Notes 1 and 2) (A) = Solder (C) = Gold (X) = Optional Screening: (See Note 3) (C) = Mil Temp Package Type: (P) = 20-lead ceramic side-brazed DIP (U) = 20-lead ceramic bottom-brazed dual-in-line Flatpack Part Number: (See Note 4) (240) = Octal buffer & line driver with inverted 3-state outputs (244) = Octal buffer & line driver with 3-state outputs (245) = Octal bus transceiver with 3-state outputs (245S) = Schmitt octal bus transceiver with 3-state outputs (273) = Octal D flip-flop with clear (373) = Octal transparent latch with 3-state outputs (374) = Octal DFF with 3-state outputs (540) = Octal buffer & line driver with inverted 3-state outputs (541) = Octal buffer & line driver with 3-state outputs I/O Type: (ACS) = CMOS compatible I/O level (ACTS) = TTL compatible I/O level Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices have 48 hours of burn-in and are tested at -55C, room temperature, and 125C. Radiation characteristics are neither tested nor guaranteed and may not be specified. 4. The following devices are not available in a DIP package: UT54ACTS541. 249 RadHard MSI Logic RadHard MSI: SMD, Class Q & Class V 5962 * ***** 01 * * * Lead Finish: (Notes 1 & 2) (A) = Solder (C) = Gold (X) = Optional Case Outline: (Note 3) (C) = 14-lead ceramic side-brazed DIP (X) = 14-lead ceramic bottom-brazed dual-in-line flatpack (E) = 16-lead ceramic side-brazed DIP (X) = 16-lead ceramic bottom-brazed dual-in-line flatpack (R) = 20-lead ceramic side-brazed DIP (X) = 20-lead ceramic bottom-brazed dual-in-line flatpack Class Designator: (V) = Class V, QML qualified to MIL-PRF-38535 (Q) = Class Q, QML qualified to MIL-PRF-38535 Device Type: No options Part Number: Please see SMD cross reference Total Dose: (Note 4) (H) = 1E6 rads(Si) (G) = 5E5 rads(Si) (F) = 3E5 rads(Si) (R) = 1E5 rads(Si) (-) = Total dose characteristics neither tested nor guaranteed Federal Stock Class Designator Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Products listed in the SMD Cross Reference with a ♣ mark can only be procurred in a bottom-brazed dual-in-line flatpack. 4. Products listed in the SMD Cross Reference with a ♣ mark can only be procurred with a total dose guarantee of -, R, F, and G. RadHard MSI Logic 249A