ETC 403GCX

PowerPC 403GCX
32-Bit RISC
Data
Sheet
Embedded Controller
Features
• PowerPC RISC CPU and instruction set
architecture
• Glueless interfaces to DRAM, SRAM,
ROM, and peripherals, including byte and
half-word devices
• 16KB instruction cache and 8KB writeback data cache, two-way set-associative
• Memory management unit
–64-entry, fully associative TLB array
–Variable page size (1KB-16MB)
–Flexible TLB management
• Individually programmable on-chip controllers for:
–Four DMA channels
–DRAM, SRAM, and ROM banks
–External interrupts
• DRAM controller supports EDO DRAM
• Flexible interface to external bus masters
• CPU core can run at 2X the external bus
speed
Applications
• Set-top boxes and network computers
• Consumer electronics and video games
• Telecommunications and networking
• Office automation (printers, copiers, fax)
Specifications
• CPU core frequency of 76 MHz, I/Os to
38 MHz
• Interfaces to both 3V and 5V technologies
• Low-power 3.3V operation with built-in
power management and stand-by mode
• Low-cost 160 lead PQFP package
• 0.45 µm triple-level-metal CMOS
Overview
The PowerPC 403GCX 32-bit RISC embedded
controller offers high performance and functional
integration with low power consumption. The
403GCX RISC CPU executes at sustained
speeds approaching one cycle per instruction.
On-chip caches and integrated DRAM and
SRAM control functions reduce chip count and
design complexity in systems, while improving
system throughput.
External I/O devices or SRAM/DRAM memory
banks can be directly attached to the 403GCX
bus interface unit (BIU). Interfaces for up to eight
memory banks and I/O devices, including a maximum of four DRAM banks, can be configured
individually, allowing the BIU to manage devices
or memory banks with differing control, timing, or
bus width requirements.
Interrupt
Controller
Timers
RISC Execution Unit
JTAG
Port
Memory Management Unit
Instruction
Cache Unit
Serial
Port
4-Channel
DMA
Controller
Data
Cache Unit
On-chip
Peripheral
Bus
(Address
and
Control)
Bus Interface Unit
DRAM Controller
I/O Controller
DRAM
Controls
SRAM, ROM, I/O
Controls
Data Address
Bus Bus
IBM PowerPC 403GCX
The 403GCX RISC controller consists of a pipelined RISC processor core and several peripheral
interface units: BIU, DMA controller, asynchronous interrupt controller, serial port, and JTAG
debug port.
the address for the data read or write to the
BIU.When noncacheable operands are being
transferred, data can pass directly between the
EXU and the BIU, which interfaces to the external
memory being accessed.
The RISC processor core includes the internal
16KB instruction cache and 8KB data cache,
reducing overhead for data transfers to or from
external memory. The instruction queue logic
manages branch prediction, folding of branch
and condition register logical instructions, and
instruction prefetching to minimize pipeline
stalls.The integrated memory management unit
provides robust memory management and protection functions, optimized for embedded environments.
Special Purpose Registers
RISC CPU
The RISC core comprises four tightly coupled
functional units: the execution unit (EXU), the
memory management unit (MMU), the data
cache unit (DCU), and the instruction cache unit
(ICU). Each cache unit consists of a data array,
tag array, and control logic for cache management and addressing. The execution unit consists of general purpose registers (GPR), special
purpose registers (SPR), ALU, multiplier, divider,
barrel shifter, and the control logic required to
manage data flow and instruction execution
within the EXU. The 403GCX core can operate at
either 1X or 2X the speed of the external buses,
which run at the SysClk input rate.
The EXU handles instruction decoding and execution, queue management, branch prediction,
and branch folding. The instruction cache unit
passes instructions to the queue in the EXU or, in
the event of a cache miss, requests a fetch from
external memory through the bus interface unit.
The MMU provides translation and memory protection for instruction and data accesses, using a
unified 64-entry, fully associative TLB array.
General Purpose Registers
Data transfers to and from the EXU are handled
through the bank of 32 GPRs, each 32 bits wide.
Load and store instructions move data operands
between the GPRs and the data cache unit,
except in the cases of noncacheable data or
cache misses. In such cases the DCU passes
2
Special purpose registers are used to control
debug facilities, timers, interrupts, the protection
mechanism, memory cacheability, and other
architected processor resources. SPRs are
accessed using move to/from special purpose
register (mtspr/mfspr) instructions, which move
operands between GPRs and SPRs.
Supervisory programs can write the appropriate
SPRs to configure the operating and interface
modes of the execution unit. The condition register (CR) and machine state register (MSR) are
written by internal control logic with program execution status and machine state, respectively.
Status of external interrupts is maintained in the
external interrupt status register (EXISR). Fixedpoint arithmetic exception status is available from
the exception register (XER).
Device Control Registers
Device control registers (DCR) are used to manage I/O interfaces, DMA channels, SRAM and
DRAM memory configurations and timing, and
status/address information regarding bus errors.
DCRs are accessed using move to/from device
control register (mtdcr/mfdcr) instructions, which
move operands between GPRs and DCRs.
Instruction Set
Table 1 summarizes the 403GCX instruction set
by categories of operations. Most instructions
execute in a single cycle, with the exceptions of
load/store multiple, load/store string, multiply,
and divide instructions.
Bus Interface Unit
The bus interface unit integrates the functional
controls for data transfers and address operations other than those which the DMA controller
handles. DMA transfers use the address logic in
the BIU to output the memory addresses being
accessed.
IBM PowerPC 403GCX
Control functions for direct-connect I/O devices
and for DRAM, SRAM, or ROM banks are provided by the BIU. Burst access for SRAM, ROM,
and page-mode DRAM devices is supported for
cache fill and flush operations.
The BIU controls the transfer of data between the
external bus and the instruction cache, the data
cache, or registers internal to the processor core.
The BIU also arbitrates among external bus master and DMA transfers, the internal buses to the
cache units and the register banks, and the serial
port on the on-chip peripheral bus (OPB).
Memory Addressing Regions
The 403GCX can address an effective range of
4GB, mapped to 3.5GB (256MB for SRAM/ROM
or other I/O, 256MB DRAM, and 3GB OPB/
reserved) of physical address space containing
twenty-eight 128MB regions. Cacheability with
respect to the instruction or data cache is programmed via the instruction and data cache control registers, respectively.
Within the DRAM and SRAM/ROM regions, a
total of eight banks of devices are supported.
Each bank can be configured for 8-, 16-, or 32-bit
devices.
For individual DRAM banks, the number of wait
states, bank size, RAS-to-CAS timing, use of an
external address multiplexer (for external bus
masters), and refresh rate are user-programma-
ble. For each SRAM/ROM bank, the bank size,
bank location, number of wait states, and timings
of chip selects, byte enables, and output enables
are all user-programmable.
Memory Management Unit
The memory management unit (MMU) supports
address translation and protection functions for
embedded applications. When used with appropriate system level software, the MMU provides
the following functions: translation of 4GB logical
address space into physical addresses, independent enabling of instruction and data translation/
protection, page level cacheability and access
control via the translation mechanism, software
control of page replacement strategy, and additional control over protection via zones.
The fully associative 64-entry TLB array handles
both instruction and data accesses. The translation for any virtual address can be placed in any
one of the 64 entries, allowing maximum flexibility by TLB management software. Each TLB
entry contains a translation for a page that can
be any one of eight sizes from 1KB to 16MB,
incrementing by powers of 4.
The TLB can simultaneously contain any mix of
page sizes. This feature enables the use of small
pages when maximum granularity is required,
reducing the amount of wasted memory when
compared to the more common fixed 4KB page
size.
Table 1. 403GCX Instructions by Category
Category
Base Instructions
Data Movement
load, store
Arithmetic / Logical
add, subtract, negate, multiply, divide, and, or, xor, nand, nor, xnor, sign
extension, count leading zeros
Comparison
compare, compare logical, compare immediate
Branch
branch, branch conditional
Condition
condition register logical
Rotate/Shift
rotate, rotate and mask, shift left, shift right
Cache Control
invalidate, touch, zero, flush, store
Interrupt Control
write to external interrupt enable bit, move to/from machine state register,
return from interrupt, return from critical interrupt
Processor Management
system call, synchronize, move to/from device control registers, move to/
from special purpose registers
3
IBM PowerPC 403GCX
Instruction Cache Unit
The instruction cache unit (ICU) is a two-way setassociative 16KB cache memory unit with
enhancements to support branch prediction and
folding. The ICU is organized as 512 sets of 2
lines, each line containing 16 bytes. A separate
bypass path is available to handle cache-inhibited instructions and to improve performance during line fill operations.
the block and then wrapping around to fill the
remaining fullwords at the beginning of the block.
DMA Controller
The four-channel DMA controller manages block
data transfers in buffered, fly-by and memory-tomemory transfer modes with options for burstmode operation. In fly-by and buffered modes,
the DMA controller supports transactions
between memory and peripheral devices.
The cache can send two cached instructions per
cycle to the execution unit, allowing instructions
to be folded out of the queue without interrupting
normal instruction flow. When a branch instruction is folded and executed in parallel with
another instruction, the ICU provides two more
instructions to replace both of the instructions
just executed so that bandwidth is balanced
between the ICU and the execution unit.
Each DMA channel provides a control register, a
source address register, a destination address
register, a transfer count register, and a chained
count register. Peripheral set-up cycles, wait
cycles, and hold cycles can be programmed into
each DMA channel control register. Each channel supports chaining operations. The DMA status register holds the status of all four channels.
Data Cache Unit
Exception Handling
The data cache unit is provided to minimize the
access time of frequently used data items in
main store. The 8KB cache is organized as a
two-way set associative cache. There are 256
sets of 2 lines, each line containing 16 bytes of
data. The cache features byte-writeability to
improve the performance of byte and halfword
store operations.
Cache operations are performed using a writeback strategy. A write-back cache only updates
locations in main storage that corresponds to
changed locations in the cache. Data is flushed
from the cache to main storage whenever
changed data needs to be removed from the
cache to make room for other data.
The data cache may be disabled for a 128MB
memory region via control bits in the data cache
control register or on a per-page basis if the
MMU is enabled for data translation. A separate
bypass path is available to handle cache-inhibited data operations and to improve performance
during line fill operations.
Cache flushing and filling are triggered by load,
store, and cache control instructions executed by
the processor. Cache blocks are loaded starting
at the requested fullword, continuing to the end of
4
Table 2 summarizes the 403GCX exception priorities, types, and classes. Exceptions are generated by interrupts from internal and external
peripherals, instructions, the internal timer facility,
debug events or error conditions. Six external
interrupt signals are provided on the 403GCX:
one critical and five general-purpose, all individually maskable.
All exceptions fall into three basic classes: asynchronous imprecise exceptions, synchronous
precise exceptions, and asynchronous precise
exceptions. Asynchronous exceptions are
caused by events external to processor execution, while synchronous exceptions are caused
by instructions.
Except for a system reset or machine check, all
403GCX exceptions are handled precisely. Precise handling implies that the address of the
excepting instruction (synchronous exceptions
other than system call) or the address of the next
sequential instruction (asynchronous exceptions
and system call) is passed to the exception handling routine. Precise handling also implies that
all instructions prior to the excepting instruction
have completed execution and have written back
their results.
IBM PowerPC 403GCX
Asynchronous imprecise exceptions include system resets and machine checks. Synchronous
precise exceptions include most debug exceptions, program exceptions, data storage violations, TLB misses, system calls, and alignment
error exceptions. Asynchronous precise exceptions include the critical interrupt exception,
external interrupts, and internal timer facility
exceptions and some debug events.
Only one exception is handled at a time. If multiple exceptions occur simultaneously, they are
handled in priority order.
The 403GCX processes exceptions as reset, critical, or noncritical. Four exceptions are defined
as critical: machine check exceptions, debug
exceptions, exceptions caused by an active level
on the critical interrupt pin, and the first time-out
from the watchdog timer.
When a noncritical exception is taken, special
purpose register Save/Restore 0 (SRR0) is
loaded with the address of the excepting instruction (synchronous exceptions other than system
call) or the next sequential instruction to be processed (asynchronous exceptions and system
call). If the 403GCX is executing a multicycle
instruction (load/store multiple, load/store string,
multiply or divide), the instruction is terminated
and its address stored in SRR0. Save/Restore
Register 1 (SRR1) is loaded with the contents of
the machine state register. The MSR is then
updated to reflect the new context of the
machine. The new MSR contents take effect
beginning with the first instruction of the exception handling routine.
At the end of the exception handling routine, execution of a return from interrupt (rfi) instruction
forces the contents of SRR0 and SRR1 to be
loaded into the program counter and the MSR,
respectively. Execution then begins at the
address in the program counter.
The four critical exceptions are processed in a
similar manner. When a critical exception is
taken, SRR2 and SRR3 hold the next sequential
address to be processed when returning from the
exception and the contents of the machine state
register, respectively. After the critical exception
handling routine, return from critical interrupt
(rfci) forces the contents of SRR2 and SRR3 to
be loaded into the program counter and the
MSR, respectively.
Timers
The 403GCX contains four timer functions: a
time base, a programmable interval timer (PIT), a
fixed interval timer (FIT), and a watchdog timer.
The time base is a 64-bit counter incremented at
the timer clock rate. The timer clock may be
driven by either an internal signal equal to the
processor clock rate or by a separate external
timer clock pin. No interrupts are generated when
the time base rolls over.
Table 2. 403GCX Exception Priorities, Types and Classes
Priority
1
2
3
4
5
6
7
8
9
10
Exception Type
Exception Class
System Reset
Machine Check
Asynchronous imprecise
Asynchronous imprecise
Synchronous precise
Debug
(except UDE and EXC)
Critical Interrupt
Asynchronous precise
WatchdogTimer Time-out
Asynchronous precise
Program Exception, Data Storage Exception,TLB Miss, and Synchronous precise
System Calls
Alignment Exceptions
Synchronous precise
External Interrupts
Asynchronous precise
Fixed Interval Timer
Asynchronous precise
Programmable Interval Timer
Asynchronous precise
5
IBM PowerPC 403GCX
The programmable interval timer is a 32-bit register that is decremented at the same rate as the
time base is incremented. The user preloads the
PIT register with a value to create the desired
delay. When the register is decremented to zeros,
the timer stops decrementing, a bit is set in the
timer status register (TSR), and a PIT interrupt is
generated. Optionally, the PIT can be programmed to reload automatically the last value
written to the PIT register, after which the PIT
begins decrementing again.The timer control
register (TCR) contains the interrupt enable for
the PIT interrupt.
The fixed interval timer generates periodic interrupts based on selected bits in the time base.
Users may select one of four intervals for the
timer period by setting the correct bits in the
TCR. When the selected bit in the time base
changes from 0 to 1, a bit is set in the TSR and a
FIT interrupt is generated. The FIT interrupt
enable is contained in the TCR.
The watchdog timer generates a periodic interrupt based on selected bits in the time base.
Users may select one of four time periods for the
interval and the type of reset generated if the
watchdog timer expires twice without an intervening clear from software. If enabled, the watchdog
timer generates a system reset unless an exception handler updates the watchdog timer status
bit before the timer has completed two of the
selected timer intervals.
Serial Port
The 403GCX serial port is capable of supporting
RS232 standard serial communication, as well as
high-speed execution (bit speed at a maximum of
one-sixteenth of the SysClk processor clock
rate). The serial clock which drives the serial port
can come from the internal SysClk or an external
clock source at the external serial clock pin (maximum of one-half the SysClk rate).
The 403GCX serial port contains many features
found only on advanced communications controllers, including the capability of being a peripheral
for DMA transfers. An internal loopback mode
supports diagnostic testing without requiring
external hardware. An auto echo mode is
included to retransmit received bits to the external device. Auto-resynchronization after a line
6
break and false start bit detection are also provided, as well as operating modes that allow the
serial port to react to handshaking line inputs or
control handshaking line outputs without software interaction. Program generation mode
allows the serial port transmitter to be used for
pulse width modulation with duty cycle variation
controlled by frame size, baud rate, and data pattern.
JTAG Port
The JTAG port has been enhanced to allow it to
be used as a debug port. Through the JTAG test
access port, debug software on a workstation or
PC can single-step the processor and interrogate
internal processor state to facilitate software
debugging. The standard JTAG boundary-scan
register allows testing of circuitry external to the
chip, primarily the board interconnect. Alternatively, the JTAG bypass register can be selected
when no other test data register needs to be
accessed during a board-level test operation.
Real-Time Debug Port
The real-time debug port supports tracing the
instruction stream being executed out of the
instruction cache in real time. The trace status
signals provide trace information while in realtime trace debug mode. This mode does not alter
the performance of the processor.
P/N Code
Table 3. PPC403GCX Part Number
MHz
Part Number
Package
76
403GCX-3JC76C2
PQFP
Note: The characters following the dash indicate reliability grade (3), package type (J), revision level (C),
maximum internal CPU core clock rate (76), commercial version (C), and the ratio of internal CPU core clock
rate to external bus speed (2 times the maximum external bus clock rate).
IBM PowerPC 403GCX
Logic Symbol
Signals in brackets are multiplexed.
PPC403GCX
RISC Controller
SYSCLK
DMAR0
•
•
•
SERCLK
DSR[CTS]
DTR[RTS]
RECVD
XMITD
DMAR3[XREQ]
DMAA0
Serial
Port
DMA
•
•
•
Controls
DMAA3[XACK]
EOT0[TC0]
•
•
•
EOT3[TC3][XSIZE0]
HOLDREQ
HOLDACK
BUSREQ/
[DMADXFER]
External
Master
SRAM
Controls
OE[XSIZE1][BLast]
TIMERCLK
CINT
INT0
WBE0[A4][BE0]
WBE1[A5][BE1]
WBE2[A30][BE2]
WBE3[A31][BE3]
R/W
CS0
Interrupts
•
•
•
SRAM/DRAM
INT4
Controls
READY
BUSERROR
•
•
•
CS3
CS4[RAS3]
•
•
•
CS7[RAS0]
ERROR
CAS0
•
•
•
RESET
BOOTW
TESTC/
[HOLDPRI]
DRAM
CAS3
Controls
AMUXCAS
DRAMOE
DRAMWE
TS0
TCK
TS1
TS2
TS3[DP3]
TS4[DP2]
Trace
Status
JTAG
TMS
TDI
TDO
HALT
TS5[DP1]
TS6[DP0]
A6
•
•
•
A29
Address
Data
Bus
Bus
D0
•
•
•
D31
7
IBM PowerPC 403GCX
Pin/Ball Functional Descriptions
Active-low signals are shown with overbars: DMAR0. Multiplexed signals are alphabetized under the first
(unmultiplexed) signal names on the same pins/balls. The logic symbol on the preceding page shows all
403GCX signals arranged by functional groups.
Table 4. 403GCX Signal Descriptions
Signal
Name
I/O
Type
Pin
Ball
A6
92
K12
I/O
Address Bus Bit 6. When the 403GCX is bus master, this is an
address output from the 403GCX. When the 403GCX is not bus
master, this is an address input from the external bus master, to
determine bank register usage.
A7
93
K11
I/O
Address Bus Bit 7. See description of A6.
A8
94
J13
I/O
Address Bus Bit 8. See description of A6.
A9
95
J14
I/O
Address Bus Bit 9. See description of A6.
A10
96
J12
I/O
Address Bus Bit 10. See description of A6.
A11
97
J11
I/O
Address Bus Bit 11. See description of A6.
A12
98
H13
O
Address Bus Bit 12. When the 403GCX is bus master, this is an
address output from the 403GCX.
A13
99
H14
O
Address Bus Bit 13. See description of A12.
A14
103
G14
O
Address Bus Bit 14. See description of A12.
A15
104
G13
O
Address Bus Bit 15. See description of A12.
A16
105
G11
O
Address Bus Bit 16. See description of A12.
A17
106
F14
O
Address Bus Bit 17. See description of A12.
A18
107
F12
O
Address Bus Bit 18. See description of A12.
A19
108
F13
O
Address Bus Bit 19. See description of A12.
A20
109
F11
O
Address Bus Bit 20. See description of A12.
A21
110
E14
O
Address Bus Bit 21. See description of A12.
A22
112
E13
I/O
Address Bus Bit 22. When the 403GCX is bus master, this is an
address output from the 403GCX. When the 403GCX is not bus
master, this is an address input from the external bus master, to
determine page crossings.
A23
113
E11
I/O
Address Bus Bit 23. See description of A22.
A24
114
D14
I/O
Address Bus Bit 24. See description of A22.
A25
115
D12
I/O
Address Bus Bit 25. See description of A22.
A26
116
D13
I/O
Address Bus Bit 26. See description of A22.
A27
117
C14
I/O
Address Bus Bit 27. See description of A22.
A28
118
C12
I/O
Address Bus Bit 28. See description of A22.
8
Function
IBM PowerPC 403GCX
Table 4. 403GCX Signal Descriptions
Signal
Name
I/O
Type
Pin
Ball
Function
A29
119
C13
I/O
Address Bus Bit 29. See description of A22.
AMuxCAS
139
A8
O
DRAM External Address Multiplexer Select. AMuxCAS controls the
select logic on an external multiplexer. If AMuxCAS is low, the multiplexer should select the row address for the DRAM and when
AMuxCAS is 1, the multiplexer should select the column address.
BootW
11
E1
I
Boot-up ROM Width Select. BootW is sampled while the Reset pin
is active and again after Reset becomes inactive to determine the
width of the boot-up ROM. If this pin is tied to logic 0 when sampled
on reset, an 8-bit boot width is assumed. If BootW is tied to 1, a 32bit boot width is assumed. For 16-bit boot widths, this pin should be
tied to the RESET pin.
BusError
12
E3
I
Bus Error Input. A logic 0 input to the BusError pin by an external
device signals to the 403GCX that an error occurred on the bus
transaction. BusError is only sampled during the data transfer cycle
or the last wait cycle of the transfer.
135
BusReq/
DMADXFER
A9
O
Bus Request. While HoldAck is active, BusReq is active when the
403GCX has a bus operation pending and needs to regain control
of the bus.
DMA Data Transfer. When HoldAck is not active, DMADXFER indicates a valid data transfer cycle. For DMA use, DMADXFER controls burst-mode fly-by DMA transfers between memory and
peripherals. DMADXFER is not meaningful unless a DMA Acknowledge signal (DMAA0:3) is active. For transfer rates slower than one
transfer per cycle, DMADXFER is active for one cycle when one
transfer is complete and the next one starts. For transfer rates of
one transfer per cycle, DMADXFER remains active throughout the
transfer.
CAS0
142
C8
O
DRAM Column Address Select 0. CAS0 is used with byte 0 of all
DRAM banks.
CAS1
143
A7
O
DRAM Column Address Select 1. CAS1 is used with byte 1 of all
DRAM banks.
CAS2
144
B7
O
DRAM Column Address Select 2. CAS2 is used with byte 2 of all
DRAM banks.
CAS3
145
D7
O
DRAM Column Address Select 3. CAS3 is used with byte 3 of all
DRAM banks.
CINT
36
L2
I
Critical Interrupt. To initiate a critical interrupt, the user must maintain a logic 0 on the CINT pin for a minimum of one SysClk clock
cycle followed by a logic 1 on the CINT pin for at least one SysClk
cycle.
CS0
155
C4
O
SRAM Chip Select 0. Bank register 0 controls an SRAM bank, CS0
is the chip select for that bank.
CS1
154
A4
O
SRAM Chip Select 1. See description of CS0 but controls bank 1.
9
IBM PowerPC 403GCX
Table 4. 403GCX Signal Descriptions
Signal
Name
I/O
Type
Pin
Ball
CS2
153
D5
O
SRAM Chip Select 2. See description of CS0 but controls bank 2.
CS3
152
B5
O
SRAM Chip Select 3. See description of CS0 but controls bank 3.
CS4/RAS3
151
C5
O
Chip Select 4/ DRAM Row Address Select 3. When bank register 4
is configured to control an SRAM bank, CS4/RAS3 functions as a
chip select. When bank register 4 is configured to control a DRAM
bank, CS4/RAS3 is the row address select for that bank.
CS5/RAS2
148
B6
O
Chip Select 5/ DRAM Row Address Select 2. See description of
CS4/RAS3 but controls bank 5.
CS6/RAS1
147
C6
O
Chip Select 6/ DRAM Row Address Select 1. See description of
CS4/RAS3 but controls bank 6.
CS7/RAS0
146
A6
O
Chip Select 7/ DRAM Row Address Select 0. See description of
CS4/RAS3 but controls bank 7.
D0
42
N2
I/O
Data bus bit 0 (most significant bit).
D1
43
P2
I/O
Data bus bit 1.
D2
44
N3
I/O
Data bus bit 2.
D3
45
P3
I/O
Data bus bit 3.
D4
46
N4
I/O
Data bus bit 4.
D5
47
M4
I/O
Data bus bit 5.
D6
48
P4
I/O
Data bus bit 6.
D7
51
P5
I/O
Data bus bit 7.
D8
52
M5
I/O
Data bus bit 8.
D9
53
L5
I/O
Data bus bit 9.
D10
54
N6
I/O
Data bus bit 10.
D11
55
P6
I/O
Data bus bit 11.
D12
56
M6
I/O
Data bus bit 12.
D13
57
L6
I/O
Data bus bit 13.
D14
58
N7
I/O
Data bus bit 14.
D15
62
M7
I/O
Data bus bit 15.
D16
63
P8
I/O
Data bus bit 16.
D17
64
N8
I/O
Data bus bit 17.
D18
65
L8
I/O
Data bus bit 18.
D19
66
P9
I/O
Data bus bit 19.
D20
67
M9
I/O
Data bus bit 20.
D21
68
N9
I/O
Data bus bit 21.
10
Function
IBM PowerPC 403GCX
Table 4. 403GCX Signal Descriptions
Signal
Name
I/O
Type
Pin
Ball
Function
D22
71
M10 I/O
Data bus bit 22.
D23
72
N10
I/O
Data bus bit 23.
D24
73
L10
I/O
Data bus bit 24.
D25
74
P11
I/O
Data bus bit 25.
D26
75
M11 I/O
Data bus bit 26.
D27
76
N11
I/O
Data bus bit 27.
D28
77
P12
I/O
Data bus bit 28.
D29
78
M12 I/O
Data bus bit 29.
D30
79
N12
I/O
Data bus bit 30.
D31
82
N13
I/O
Data bus bit 31.
DMAA0
156
B4
O
DMA Channel 0 Acknowledge. DMAA0 has an active level when a
transaction is taking place between the 403GCX and a peripheral.
DMAA1
157
A3
O
DMA Channel 1 Acknowledge. See description of DMAA0.
DMAA2
158
C3
O
DMA Channel 2 Acknowledge. See description of DMAA0.
DMAA3/
XACK
159
B3
O
DMA Channel 3 Acknowledge / External Master Transfer Acknowledge. When the 403GCX is bus master, this signal is DMAA3; see
description of DMAA0. When the 403GCX is not the bus master,
this signal is XACK, an output from the 403GCX which has an
active level when data is valid during an external bus master transaction.
DMAR0
2
B2
I
DMA Channel 0 Request. External devices request a DMA transfer
on channel 0 by putting a logic 0 on DMAR0.
DMAR1
3
B1
I
DMA Channel 1 Request. See description of DMAR0.
DMAR2
4
C2
I
DMA Channel 2 Request. See description of DMAR0.
DMAR3/
XREQ
5
C1
I
DMA Channel 3 Request. When the 403GCX is the bus master,
external devices request a DMA transfer on channel 3 by putting a
logic 0 on DMAR3. See description of DMAR0.
When the 403GCX is not the bus master, DMAR3 is used as the
XREQ input. The external bus master places a logic 0 on XREQ to
initiate a transfer to the DRAM controlled by the 403GCX DRAM
controller.
DRAMOE
137
D9
O
DRAM Output Enable. DRAMOE has an active level when either
the 403GCX or an external bus master is reading from a DRAM
bank. This signal enables the selected DRAM bank to drive the data
bus.
DRAMWE
138
B8
O
DRAM Write Enable. DRAMWE has an active level when either the
403GCX or an external bus master is writing to a DRAM bank.
11
IBM PowerPC 403GCX
Table 4. 403GCX Signal Descriptions
Signal
Name
I/O
Type
Pin
Ball
DSR/CTS
28
J2
I
Data Set Ready / Clear to Send. The function of this pin as either
DSR or CTS is selectable via the Serial Port Configuration bit in the
IOCR.
DTR/RTS
88
L14
O
Data Terminal Ready / Request to Send. The function of this pin as
either DTR or RTS is selectable via the Serial Port Configuration bit
in the IOCR.
EOT0/TC0
128
A11
I/O
End of Transfer 0 / Terminal Count 0. The function of the EOT0/TC0
is controlled via the EOT/TC bit in the DMA Channel 0 Control Register. When EOT0/TC0 is configured as an End of Transfer pin,
external users may stop a DMA transfer by placing a logic 0 on this
input pin. When configured as a Terminal Count pin, the 403GCX
signals the completion of a DMA transfer by placing a logic 0 on this
pin.
EOT1/TC1
131
A10
I/O
End of Transfer 1 / Terminal Count 1. See description of EOT0/TC0.
EOT2/TC2
132
C10
I/O
End of Transfer 2 / Terminal Count 2. See description of EOT0/TC0.
EOT3/TC3/
XSize0
133
D10
I/O
End of Transfer 3 / Terminal Count 3 / External Master Transfer Size
0. When the 403GCX is bus master, this pin has the same function
as EOT0/TC0.
When the 403GCX is not bus master, EOT3/TC3/XSize0 is used as
one of two external transfer size input bits, XSize0:1.
Error
136
C9
O
System Error. Error goes to a logic 1 whenever a machine check
error is detected in the 403GCX. The Error pin then remains a logic
1 until the machine check error is cleared in the Exception Syndrome Register and/or Bus Error Syndrome Register.
1
G7
Ground. All ground pins must be used.
10
E2
Ground. All ground pins must be used.
15
F1
Ground. All ground pins must be used.
29
J4
Ground. All ground pins must be used.
30
K1
Ground. All ground pins must be used.
41
H7
Ground. All ground pins must be used.
50
N5
Ground. All ground pins must be used.
59
P7
Ground. All ground pins must be used.
60
L7
Ground. All ground pins must be used.
70
P10
Ground. All ground pins must be used.
81
H8
Ground. All ground pins must be used.
GND
12
Function
IBM PowerPC 403GCX
Table 4. 403GCX Signal Descriptions
Signal
Name
I/O
Type
Pin
Ball
90
K13
Ground. All ground pins must be used.
101
G12
Ground. All ground pins must be used.
102
H12
Ground. All ground pins must be used.
111
E12
Ground. All ground pins must be used.
121
G8
Ground. All ground pins must be used.
130
B10
Ground. All ground pins must be used.
141
C7
Ground. All ground pins must be used.
150
A5
Ground. All ground pins must be used.
Halt
9
D4
I
Halt from external debugger, active low.
HoldAck
134
B9
O
Hold Acknowledge. HoldAck outputs a logic 1 when the 403GCX
relinquishes its external buses to an external bus master. HoldAck
outputs a logic 0 when the 403GCX regains control of the bus.
HoldReq
14
F2
I
Hold Request. External bus masters can request the 403GCX bus
by placing a logic1 on this pin. The external bus master relinquishes
the bus to the 403GCX by deasserting HoldReq.
INT0
31
K3
I
Interrupt 0. INT0 is an interrupt input to the 403GCX and users may
program the pin to be either edge-triggered or level-triggered and
may also program the polarity to be active high or active low. The
IOCR contains the bits necessary to program the trigger type and
polarity.
INT1
32
K2
I
Interrupt 1. See description of INT0.
INT2
33
K4
I
Interrupt 2. See description of INT0.
INT3
34
L1
I
Interrupt 3. See description of INT0.
INT4
35
L3
I
Interrupt 4. See description of INT0.
IVR
39
M2
I
Reserved for manufacturing test. Tied high for normal operation.
OE/XSize1/
BLast
126
B11
O/I/O
Output Enable / External Master Transfer Size 1. When the 403GCX
is bus master, OE enables the selected SRAMs to drive the data
bus. The timing parameters of OE relative to the chip select, CS,
are programmable via bits in the 403GCX bank registers.
When the 403GCX is not bus master, OE/XSize1 is used as one of
two external transfer size input bits, XSize0:1.
In Byte Enable mode, Burst Last (BLast) goes active to indicate the
last transfer of a memory access, whether burst or nonburst.
Ready
13
E4
I
Ready. Ready is used to insert externally generated (device-paced)
wait states into bus transactions. The Ready pin is enabled via the
Ready Enable bit in 403GCX bank registers.
RecvD
27
J3
I
Serial Port Receive Data.
GND
Function
13
IBM PowerPC 403GCX
Table 4. 403GCX Signal Descriptions
Signal
Name
I/O
Type
Pin
Ball
Reset
91
K14
I/O
Reset. A logic 0 input placed on this pin for one SysClk cycle
causes the 403GCX to begin a system reset. When a system reset
is invoked, the Reset pin becomes a logic 0 output for 2048 SysClk
cycles.
R/W
127
C11
I/O
Read / Write. When the 403GCX is bus master, R/W is an output
which is high when data is read from memory and low when data is
written to memory.
When the 403GCX is not bus master, R/W is an input from the
external bus master which indicates the direction of data transfer.
SerClk
26
J1
I
Serial Port Clock. Through the Serial Port Clock Source bit in the
Input/Output Configuration register (IOCR), users may choose the
serial port clock source from either the input on the SerClk pin or
processor SysClk. The maximum allowable input frequency into
SerClk is half the SysClk frequency.
SysClk
22
G3
I
SysClk is the processor system clock input. The 403GCX can also
be programmed to operate at a 2X internal clock rate while the
external bus interface runs at the SysClk input rate.
TCK
6
D2
I
JTAG Test Clock Input. TCK is the clock source for the 403GCX test
access port (TAP). The maximum clock rate into the TCK pin is one
half of the processor SysClk clock rate.
TDI
8
D1
I
Test Data In. The TDI is used to input serial data into the TAP. When
the TAP enables the use of the TDI pin, the TDI pin is sampled on
the rising edge of TCK and this data is input to the selected TAP
shift register.
TDO
16
F3
O
Test Data Output. TDO is used to transmit data from the 403GCX
TAP. Data from the selected TAP shift register is shifted out on TDO.
TestA
23
H1
I
Reserved for manufacturing test. Tied low for normal operation.
TestB
24
H2
I
Reserved for manufacturing test. Tied high for normal operation.
TestC/HoldPri
37
M1
I
TestC. Reserved for manufacturing test during the reset interval.
While Reset is active, this signal should be tied low for normal operation.
HoldReq Priority. When Reset is not active, this signal is sampled to
determine the priority of the external bus master signal HoldReq. If
HoldPri = 0 then the HoldReq signal is considered high priority, otherwise HoldReq is considered low priority.
TestD
38
M3
I
Reserved for manufacturing test. Tied low for normal operation.
TimerClk
25
H4
I
Timer Facility Clock. Through the Timer Clock Source bit in the
Input/Output Configuration register (IOCR), users may choose the
clock source for the Timer facility from either the input on the TimerClk pin or processor CoreClk. The maximum input frequency into
TimerClk is half the CoreClk frequency.
14
Function
IBM PowerPC 403GCX
Table 4. 403GCX Signal Descriptions
Signal
Name
I/O
Type
Pin
Ball
TMS
7
D3
I
Test Mode Select. The TMS pin is sampled by the TAP on the rising
edge of TCK. The TAP state machine uses the TMS pin to determine the mode in which the TAP operates.
TS0
17
F4
O
Trace Status 0.
TS1
18
G2
O
Trace Status 1.
TS2
19
G1
O
Trace Status 2.
TS3/DP3
86
L13
O/I/O
Trace Status 3 / Data Parity 3. When parity checking and generation
are enabled, this signal represents odd parity for read/write operations using byte 3 (D24:31) of the data bus. The Parity Error status
bit is set in the BESR when a parity error is detected.
TS4/DP2
85
M14 O/I/O
Trace Status 4 / Data Parity 2 for byte 2 (D16:23). See TS3/DP3
description above.
TS5/DP1
84
M13 O/I/O
Trace Status 5 / Data Parity 1 for byte 1 (D8:15). See TS3/DP3
description above.
TS6/DP0
83
N14
Trace Status 6 / Data Parity 0 for byte 0 (D0:7). See TS3/DP3
description above.
20
G4
Power. All power pins must be connected to 3.3V supply.
21
H3
Power. All power pins must be connected to 3.3V supply.
40
N1
Power. All power pins must be connected to 3.3V supply.
49
L4
Power. All power pins must be connected to 3.3V supply.
61
M8
Power. All power pins must be connected to 3.3V supply.
69
L9
Power. All power pins must be connected to 3.3V supply.
80
P13
Power. All power pins must be connected to 3.3V supply.
89
L11
Power. All power pins must be connected to 3.3V supply.
100
H11
Power. All power pins must be connected to 3.3V supply.
120
B14
Power. All power pins must be connected to 3.3V supply.
129
D11
Power. All power pins must be connected to 3.3V supply.
140
D8
Power. All power pins must be connected to 3.3V supply.
149
D6
Power. All power pins must be connected to 3.3V supply.
160
A2
Power. All power pins must be connected to 3.3V supply.
VDD
O/I/O
Function
15
IBM PowerPC 403GCX
Table 4. 403GCX Signal Descriptions
Signal
Name
Pin
Ball
I/O
Type
WBE0/A4/
BE0
122
B13
O/I/O
Write Byte Enable 0 / Address Bus Bit 4 / Byte Enable 0. When the
403GCX is bus master, the write byte enable outputs, WBE0:3,
select the active byte(s) in a memory write access to SRAM.
The byte enables can also be programmed as read/write byte
enables, depending on the mode set in the IOCR. Note 5 on page
35 summarizes the functional and timing differences in these signals when programmed as read/write byte enables.
For 8-bit memory regions, WBE2 and WBE3 become address bits
30 and 31 and WBE0 is the byte-enable line. For 16-bit memory
regions, WBE2 and WBE3 become address bits 30 and 31 and
WBE0 and WBE1 are the high byte and low byte enables, respectively. For 32-bit memory regions, WBE0:3 are byte enables for
bytes 0-3 on the data bus, respectively. When the 403GCX is not
bus master, WBE0:1 are used as the A4:5 inputs (for bank register
selection) and WBE2:3 are used as the A30:31 inputs (for byte
selection and page crossing detection).
WBE1/A5/
BE1
123
A13
O/I/O
Write Byte Enable 1 / Address Bus Bit 5 / Byte Enable 1. See
description of WBE0 / A4 above.
WBE2/A30/
BE2
124
B12
O/I/O
Write Byte Enable 2 / Address Bus Bit 30 / Byte Enable 2. See
description of WBE0 / A4 above.
WBE3/A31/
BE3
125
A12
O/I/O
Write Byte Enable 3 / Address Bus Bit 31 / Byte Enable 3. See
description of WBE0 / A4 above.
XmitD
87
L12
O
Serial port transmit data.
16
Function
IBM PowerPC 403GCX
Table 5. PQFP Package Signals Ordered by Pin Number
Pin
Signal Name
Pin Signal Name Pin Signal Name Pin
Signal Name
Pin
Signal Name
1
GND
33 INT2
65 D18
97
A11
129 VDD
2
DMAR0
34 INT3
66 D19
98
A12
130 GND
3
DMAR1
35 INT4
67 D20
99
A13
131 EOT1/TC1
4
DMAR2
36 CINT
68 D21
132 EOT2/TC2
5
DMAR3/XREQ
37 TestC/HoldPri 69 VDD
100 VDD
101 GND
6
TCK
38 TestD
70 GND
102 GND
134 HoldAck
7
TMS
39 IVR
71 D22
103 A14
135 BusReq/
DMADXFER
8
TDI
40 VDD
72 D23
104 A15
136 Error
9
Halt
41 GND
73 D24
105 A16
137 DRAMOE
10 GND
42 D0
74 D25
106 A17
138 DRAMWE
11 BootW
43 D1
75 D26
107 A18
139 AMuxCAS
12 BusError
44 D2
76 D27
108 A19
140 VDD
13 Ready
45 D3
77 D28
109 A20
141 GND
14 HoldReq
46 D4
78 D29
110 A21
142 CAS0
15 GND
47 D5
79 D30
111 GND
143 CAS1
16 TDO
48 D6
80 VDD
112 A22
144 CAS2
17 TS0
81 GND
113 A23
145 CAS3
18 TS1
49 VDD
50 GND
82 D31
114 A24
146 CS7/RAS0
19 TS2
51 D7
83 TS6/DP0
115 A25
147 CS6/RAS1
20 VDD
52 D8
84 TS5/DP1
116 A26
148 CS5/RAS2
21 VDD
22 SysClk
53 D9
85 TS4/DP2
117 A27
54 D10
86 TS3/DP3
118 A28
149 VDD
150 GND
23 TestA
55 D11
87 XmitD
119 A29
151 CS4/RAS3
24 TestB
56 D12
88 DTR/RTS
120 VDD
152 CS3
25 TimerClk
57 D13
121 GND
153 CS2
133 EOT3/TC3/XSize0
26 SerClk
58 D14
89 VDD
90 GND
122 WBE0/A4/BE0
154 CS1
27 RecvD
59 GND
91 Reset
123 WBE1/A5/BE1
155 CS0
28 DSR/CTS
60 GND
92 A6
124 WBE2/A30/BE2 156 DMAA0
29 GND
93 A7
125 WBE3/A31/BE3 157 DMAA1
30 GND
61 VDD
62 D15
94 A8
126 OE/XSize1/
BLast
158 DMAA2
31 INT0
63 D16
95 A9
127 R/W
159 DMAA3/XACK
32 INT1
64 D17
96 A10
128 EOT0/TC0
160 VDD
17
IBM PowerPC 403GCX
PQFP Mechanical Drawing (Top View)
120
81
See
detail
121
80
mm
Dimensions:
inches
31.2 ± 0.25
1.228 ± 0.01
Note: English dimensions
are for reference only.
28 ± 0.2
1.102 ± 0.008
Index Mark
41
160
1
40
0.015 ± 0.05
0.006 ± 0.002
0.25 Min
0.01
0° - 7°
0.65 Basic
0.0256
0.3 ± 0.1
0.012 ± 0.004
18
3.95 Max
0.155
0.8 ± 0.15
0.032 ± 0.006
IBM PowerPC 403GCX
Package Thermal Specifications
The 403GCX is designed to operate within the case temperature range from -40˚C to 120˚C. Thermal
resistance values are shown in Table 6:
Table 6. Thermal Resistance (˚C/Watt)
Airflow-ft/min (m/sec)
Parameter
θJC Junction to case
0
(0)
100
(0.51)
200
(1.02)
2
2
2
37.2
31.6
29.8
θCA Case to ambient
PQFP (no heatsink)
Notes:
1. Case temperature TmC is measured at top center of case surface with device soldered to circuit board.
2. TmA = TmC – P×θ CA, where TmA is ambient temperature.
3. TmCMax = TmJMax – P×θJC, where TmJMax is maximum junction temperature and P is power consumption.
4. The above assumes that the chip is mounted on a card with at least one signal and two power planes.
Electrical Specifications
Absolute Maximum Ratings
The absolute maximum ratings in Table 7 below are stress ratings only. Operation at or beyond these
maximum ratings may cause permanent damage to the device.
Table 7. 403GCX Maximum Ratings
Parameter
Maximum Rating
Supply voltage with respect to GND
-0.5V to +3.8V
Voltage on other pins with respect to GND
-0.5V to +5.5V
Case temperature under bias
-40˚C to +120˚C
Storage temperature
-65˚C to +150˚C
19
IBM PowerPC 403GCX
Operating Conditions
The 403GCX can interface to either 3V or 5V technologies. The range for supply voltages is specified for
five-percent margins relative to a nominal 3.3V power supply.
Device operation beyond the conditions specified in Table 8 is not recommended. Extended operation
beyond the recommended conditions may affect device reliability:
Table 8. Operating Conditions
Symbol
VDD
FC
TmC
Parameter
Min
Max
Unit
3.14
3.47
V
Clock
403GCX-3JC76
24
38
MHz
Case temperature under bias:
403GCX-3JC76
-40
85
°C
Supply voltage:
403GCX-3JC76
frequency1:
Note:
These frequencies do not account for TCS. See Table 11.
Power Considerations
Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as
external source/sink current requirements. Typical power dissipation is 0.49 W at 38/76 MHz, with an
average 50pF capacitive load.
Derating curves are provided in the section, "Output Derating for Capacitance and Voltage," on page 29.
Recommended Connections
Power and ground pins should all be connected to separate power and ground planes in the circuit board
to which the 403GCX is mounted. Unused input pins must be tied inactive, either high or low.
The IVR pin should be tied to VDD for normal operation.
20
IBM PowerPC 403GCX
DC Specifications
Table 9. 403GCX DC Characteristics
Symbol
Parameter
Min
Max
Units
VIL
Input low voltage (except for SysClk)
GND - 0.1
0.8
V
VILC
Input low voltage for SysClk
GND - 0.1
0.8
V
VIH
Input high voltage (except for SysClk)
2.0
5.1
V
VIHC
Input high voltage for SysClk
2.0
5.1
V
VOL
Output low voltage
0.4
V
VOH
Output high voltage
VDD
V
IOH
Output high current
2
mA
IOL
Output low current
4
mA
ILI
Input leakage current3
150
µA
ILO
Output leakage current
10
µA
ICC
Supply current (ICC Max at FCore of 76MHz)
305
mA
2.4
Notes:
1. The 403GCX drives its outputs to the level of VDD and, when not driving, the 403GCX outputs can be pulled up to
5V by other devices in a system.
2. ICC Max is measured at worst-case recommended operating conditions for temperature, frequency and voltage as
specified in Table 8 on page 20, and a capacitive load of 50 pF.
3. The Input leakage current is dependent on the applied. See "Input Leakage Current," on page 32 for details.
.
Table 10. 403GCX I/O Capacitance
Symbol
Max
Units
Input capacitance (except for SysClk)
5
pF
CINC
Input capacitance for SysClk
15
pF
COUT
Output
capacitance1
7
pF
CI/O
I/O pin capacitance
8
pF
CIN
Parameter
Min
Note:
1. COut is specified as the load capacitance of a floating output in high impedance.
21
IBM PowerPC 403GCX
AC Specifications
Output
Pin
Clock timing and switching characteristics are specified in accordance with
recommended operating conditions in Table 8 on page 20. AC specifications
are characterized at VDD = 3.14V and TJ = 85˚C with the 50pF test load
shown in the figure at right. Derating of outputs for capacitive loading is
shown in the figure "Output Derating for Capacitance and Voltage," on page
29.
CL
CL = 50 pf for all signals
SysClk Timing
TCF
TCR
2.0V
1.5V
0.8V
TCH
TCL
TC
Table 11. 403GCX System Clock Timing
38 MHz
Symbol
Parameter
Units
Min
Max
24
38
MHz
27.8
41.7
ns
0.2
ns
FC
SysClk clock input frequency1
TC
SysClk clock period1
TCS
Clock edge
stability2
TCH
Clock input high time
11
ns
TCL
Clock input low time
11
ns
TCR
Clock input rise time3
0.5
2.5
ns
0.5
2.5
ns
TCF
Clock input fall
time3
Notes:
1. These values do not include the allowable tolerance for clock edge instability represented by TCS.
2. Cycle-to-cycle jitter allowed between any two edges.
3. Rise and fall times measured between 0.8V and 2.0V.
22
IBM PowerPC 403GCX
Serial Clock Timing Characteristics
Table 12. 403GCX Serial Clock Timings
Symbol
Parameter
Min
Max
Units
0.5 FC
MHz
FSC
SerClk input frequency
TSC
SerClk period
2TC
ns
TSCH
SerClk input high time
TC
ns
TSCL
SerClk input low time
TC
ns
Timer Clock Timing Characteristics
Table 13. 403GCX Timer Clock Timings
Symbol
IOCR[2xC] = 1
CoreClk
Doubled Mode
Parameter
Min
FTC
TimerClk input frequency
TTC
TimerClk period
TTCH
TTCL
Max
IOCR[2xC] = 0
CoreClk
Non-Doubled Mode
Min
Units
Max
FC
0.5 FC
MHz
TC
2 TC
ns
TimerClk input high time
0.5 TC
TC
ns
TimerClk input low time
0.5 TC
TC
ns
Table 14. 403GCX Serial Port Output Timings
38 MHz
Symbol
Parameter
Units
TOHMin
TOH, TOV
Output hold, output valid
TOHSP1, TOVSP1
TOHSP2, TOVSP2
TOVMax
DTR/RTS
XmitD
12
10
ns
Note:
1. Output times are measured with a standard 50 pF capacitive load, unless otherwise noted.
23
IBM PowerPC 403GCX
Input Setup and Hold Waveform
SysClk
1.5V+
Inputs
TIS
TIH
MIN
MIN
1.5V
+
TISCAS
TISEDO MIN
Data Bus
D0:31
(Inputs)
1.5V
+
VALID
MIN
TIHCAS
MIN
VALID
VALID
VALID
TISCAS
TIHEDO MIN
CAS0:3
Outputs
MIN
TIHCAS
MIN
1.5V+
TCAS2CLK
MIN
TCAS2CLK
MIN
Notes:
1. The 403GCX may be programmed to latch data from the data bus with respect to SysClk, or with respect to CAS.
When IOCR[DRC] = 1, the 403GCX is programmed to latch data on the rise of CAS. When IOCR[EDO] = 1, the
403GCX is programmed to latch data on either the fall of CAS or the fall of the internal duty cycle corrected
SysClk, depending on the parameters set in the bank register and the type of transfer. When neither of these special modes are set, the 403GCX will latch data on the rise of SysClk. Note that it is invalid to concurrently set
IOCR[DRC] = 1 and IOCR[EDO] = 1.
2. TCAS2CLK ≥ 13.5 ns. When IOCR[DRC] = 1 or IOCR[EDO] = 1, the capacitive load on the CAS outputs must not
delay the CAS transition such that the period from the CAS data latching edge to the next SysClk rising edge
becomes less than 13.5 ns. The maximum value of CAS capacitive loading can be determined by using the output
time for CAS from Table 17 on page 27, and applying the appropriate derating factor for your application. See the
figure, "Output Derating for Capacitance and Voltage," on page 29.
24
IBM PowerPC 403GCX
All TIS and TIH timings in Table 15 are specified with respect to the rise of the external SysClk signal.
Internal system clocks are duty-cycle corrected so the falling edge of the external SysClk signal may not
be the same as the falling edge of the internally corrected system clock.
Table 15. 403GCX Synchronous Input Timings
38 MHz
Symbol
Parameter
Units
Min
TIS
TIH
TR,TF
Input setup:
TIS1
TIS2
TIS3
TISEDO
TISCAS
TIS4
TIS5
TIS6
TIS7
TIS8
TIS9
TIS10
Input hold:
TIH1
TIH2
TIH3
TIHEDO
TIHCAS
TIH4
TIH5
TIH6
TIH7
TIH8
TIH9
TIH10
Input rise/fall time
A4:11,A22:31
BusError
D0:31 (to SysClk)3
D0:31 (to SysClk)4,5
D0:31 (to CAS)5
HoldPri
HoldReq
R/W
Ready
Ready(SOR mode)
XReq
XSize0:1
3
5
4
16.2
3
3
3
3
5
10
4
3
A4:11,A22:31
BusError
D0:31 (after SysClk)3
D0:31 (after SysClk)4,5
D0:31 (after CAS)5
HoldPri
HoldReq
R/W
Ready
Ready(SOR mode)
XReq
XSize0:1
2
2
3
-10.2
3
2
2
2
2
2
2
2
0.5
Max
ns
ns
2.5
ns
Notes:
1. Parity setup and hold times are the same as for the data bus.
2. For detailed EDO DRAM timing waveforms, refer to "EDO DRAM 2-1-1-1 Burst Read Followed by Single Transfer
Read," on page 42 and "EDO DRAM 3-1-1-1 Burst Read Followed by Single Transfer Read," on page 44.
3. Data bus input setup and hold times TIS3 and TIH3 are the specifications to use for all modes except DRAM Read
on CAS and EDO DRAM read modes (controlled via IOCR[DRC] and IOCR[EDO], respectively).
4. In EDO mode, the data bus input setup and hold times with respect to SysClk. Use the following equations to
determine the minimum input setup and hold times for this signal: TISEDOMin = Tc/2 + 3; TIHEDOMin = -Tc/2 + 3.
Valid for Tc greater than 25ns and less than 41.7 ns.
5. Guaranteed by design and not tested.
25
IBM PowerPC 403GCX
Table 16. 403GCX Asynchronous Input Timings
38 MHz
Symbol
Parameter
Units
Min
TIS
TIH
Input setup time
TIS11
TIS12
TIS13
TIS14
TIS15
TIS16
TIS17
3
3
3
3
4
8
5
CINT
DMAR0:3
EOT0:3
HALT
INT0:4
Reset
Ready
Input hold time
TIH11
TIH12
TIH13
TIH14
TIH15
TIH16
TIH17
CINT
DMAR0:3
EOT0:3
HALT
INT0:4
Reset
Ready
Max
ns
TC
TC
TC
TC
TC
Note 1,2
TC
Notes:
1. During a system-initiated reset, Reset must be taken low for a minimum of 2048 SysClk cycles.
2. The BootW input has a maximum rise time requirement of 10 ns when it is tied to Reset.
3. Input hold times are measured at 3.47V and TJ = 0°C.
Output Delay and Float Timing Waveform
1.5V
SysClk
TOV
TOH
Max
Outputs
1.5V
TOF
26
Valid
Max
Min
Outputs
Min
1.5V
IBM PowerPC 403GCX
All TOH and TOV timings in Table 17 are specified with respect to the rise of the SysClk input signal. Internal system clocks are duty-cycle corrected so the falling edge of the external SysClk signal may not be
the same as the falling edge of the internally corrected system clock. TOHxr/TOVxr specifications are for
signals which transition relative to the rising edge of SysClk, while TOHxf/TOVxf apply to falling edge transitions. Refer to the appropriate timing diagram to determine the appropriate clock edge for signal transitions.
Table 17. 403GCX Synchronous Output Timings
TOH, TOV
TOF
38 MHz
Parameter
Symbol
Output hold, output
TOH1r, TOV1r
TOH1f, TOV1f
TOH2, TOV2
TOH3, TOV3
TOH4r, TOV4r
TOH4f, TOV4f
TOH5, TOV5
TOH6, TOV6
TOH7, TOV7
TOH8, TOV8
TOH9r, TOV9r
TOH9f, TOV9f
TOH10, TOV10
TOH11, TOV11
TOH12, TOV12
TOH13, TOV13
TOH14r, TOV14r
TOH14f, TOV14f
TOH15, TOV15
TOH16, TOV16
TOH17, TOV17
TOH18, TOV18
TOH19, TOV19
TOH20, TOV20
TOH21, TOV21
TOH22, TOV22
Output float time
TOF1
TOF4
TOF5
TOF6
TOF9
TOF10
TOF13
TOF14
TOF16
TOF17
TOF20
TOHMin
TOVMax
3
16.2
3
3
3
16.2
3
3
3
3
3
16.2
3
3
3
3
3
16.2
10
2
3
3
4
3
3
4
10
23.2
9
9
9
22.3
9
12
9
10
9
23.2
9
10
9
10
9
23.2
16.9
10
9
10
13
9
10
14
Min
2
3
3
3
3
3
3
3
2
3
3
Max
8
10
10
10
9
9
9
10
9
9
9
Units
valid
A6:31
A6:312,3,8
AMuxCAS
BusReq
CAS0:38
CAS0:32,3
CS0:7
D0:31
DMAA0:3
DMADXFER
DRAMOE
DRAMOE2,3,8
DRAMWE
Error
HoldAck
OE
RAS0:3(turn-off)8
RAS0:3(turn-on)3
RAS0:3(Early, turn-on)4
Reset
R/W
TC0:3
Parity(DMA)5,8
WBE0:3[BE0:3]
XAck
BLast8
A6:31
CAS0:3
CS0:7
D0:31
DRAMOE
DRAMWE
OE
RAS0:3
Reset
R/W
WBE0:3[BE0:3]
ns
ns
27
IBM PowerPC 403GCX
Notes:
1. For all output timing, TOH and TOV are relative to the rising edge of SysClk.
2. For detailed EDO DRAM timing waveforms, refer to "EDO DRAM 2-1-1-1 Burst Read Followed by Single Transfer
Read," on page 42 and "EDO DRAM 3-1-1-1 Burst Read Followed by Single Transfer Read," on page 44.
3. The Address bus, RAS, CAS and DRAMOE output timings (with respect to the falling edge of the internal duty
cycle corrected SysClk) vary with the 403GCX operating frequency. Use the following equations to determine the
worst-case output delay and hold times for these signals: TOVfMax = Tc/2 + TOVrMax; TOHfMin = Tc/2 + TOHrMin,
where TOVrMax and TOHrMin correspond to the specifications for the speed grade of the part. Valid for Tc greater
than 25 ns and less than 41.7 ns.
4. In early RAS mode, the RAS output delay varies with the 403GCX operating frequency. Use the following equation
to determine the worst-case output delay for this signal: TOV15Max = Tc/4 + TOH15Min, where TOH15Min corresponds to the specification for the speed grade of the part. TOHMin remains unchanged. Valid for Tc greater than
25 ns and less than 41.7 ns.
5. Parity timings are for DMA buffered mode. For normal memory accesses, use the data bus timings for parity.
6. Output times are measured with a standard 50 pF capacitive load, unless otherwise noted. Output hold times are
measured as TOVmin at 3.47V and Tj=0°C.
7. All output hold and float times are guaranteed by design and not tested.
8. Noted output valid times guaranteed by design and not tested.
Table 18. 403GCX DRAM Interface Timing Relationships
Parameter
Symbol
38 MHz
Units
Min
TASR
Row Address Setup Time to RAS:
BRn[ERM] = 0
BRn[ERM] = 1
0.5TC -4.0
0.25TC -2.5
ns
TRAH
Row Address Hold Time:
BRn[ERM] = 0
BRn[ERM] = 1
0.5TC -1.5
0.67TC -0.5
ns
TASC
Column Address Setup Time to CAS
0.5TC -4.0
ns
TCAH
Column Address Hold Time
0.5TC -2.0
ns
TCAS
Available CAS Access Time:
2-1-1-1 access
3-2-2-2 access
3-1-1-1 access
0.5TC -2.5
1.5TC -2.5
0.5TC -2.5
TCP
CAS Precharge Time
0.5TC -2.5
ns
TDS
Write Data Setup Time to CAS
0.5TC -4.0
ns
TRP
RAS Precharge Time:
BRn[ERM] = 0 and BRn[PCC] = 0
BRn[ERM] = 0 and BRn[PCC] = 1
BRn[ERM] = 1 and BRn[PCC] = 0
BRn[ERM] = 1 and BRn[PCC] = 1
1.5TC -2.5
2.5TC -2.5
1.25TC -1.0
2.25TC -1.0
TRAS
RAS Active During Refresh:
BR[RAR] = 0
BR[RAR] = 1
1.5TC -1.5
2.5TC -1.5
ns
ns
ns
Note:
1. Relationships are guaranteed by design and are not tested. Relationships also assume 50 pF capacitive loading
on interface signals.
2. For detailed DRAM interface timing waveforms, refer to "DRAM Interface Timing Diagram," on page 29.
28
IBM PowerPC 403GCX
DRAM Interface Timing Diagram
ADDRESS
TRAS
TASR
TRP
TRAH
TASC
TCAH
RAS
TCAS
1.5V
TCP
CAS
TDS
WRITE DATA
Output Derating for Capacitance and Voltage
Output Propagation Delay Derating
Note: Test Conditions
Derating Equations for Output Delays:
1. ∆tpLH(CL, V) = tpLH∆C + tpLH∆V
Vt = 1.5V at TJ = 85˚C
+20
tpZL∆C = 0.14 CL - 1.2ns
(from 5.5V)
3. ∆tpZL5V(CL, V) = tpZL∆C + tpHL∆V
∆ Output Delay (ns)
2. ∆tpHL(CL, V) = tpHL∆C + tpHL∆V
+10
tpHL∆C = 0.06 CL - 2.3ns
tpLH∆C = 0.04 CL - 1.9ns
0
-10
0
50
100
150
CL (pF)
29
IBM PowerPC 403GCX
Output Propagation Delay Derating vs Output Voltage Level
+6
Note: Test condition TJ = 85˚C
tpHL∆V (CL = 100 pF)
tpLH∆V (CL = 100 pF)
∆ Output Delay (ns)
+4
tpHL∆V (CL = 50pF)
tpLH∆V (CL = 50pF)
+2
tpLH∆V (CL = 25 pF)
tpHL∆V (CL = 25 pF)
0
0
1.5
3
VOut (V)
Output Rise and Fall Time Derating
Output Transition Time Derating
Note: Test Conditions
Vt = 0.8V to 2V at TJ = 85˚C
+6
Derating Equations for Output
Rise and Fall Times:
4. tR(CL) = 2ns + tpr∆C
5. tF(CL) = 2.5ns + tpf∆C
∆ Output Transition (ns)
tpr∆C
+4
tpf∆C
+2
0
-2
0
50
100
CL (pF)
30
150
IBM PowerPC 403GCX
Output Voltage vs Output Current
3.5
VOH Min (V)
VOL Max (V)
0.6
0.3
3
2.5
0
2
0
4
3
2
1
1
0
2
3
IOH (mA)
IOL (mA)
Note: Test conditions 3.14V at TJ = 85˚C
Supply Current vs Operating Frequency
Test Conditions: 3.47V at TJ = 85˚C
(Worst Case)
320 mA
ICC (mA)
260 mA
200 mA
103 mA
127 mA
155 mA
Test Conditions:
3.3V at TJ = 55˚C (Typical)
0
0
FC (MHz)
25
33
40
31
IBM PowerPC 403GCX
Input Leakage Current
+200
Leakage Current (µa)
+100
0
-100
-200
0
0.5
1.0
1.5
2.0
Input Voltage (v)
See Note 3 in "403GCX DC Characteristics," on page 21.
32
2.5
3.0
IBM PowerPC 403GCX
Reset and HoldAck
The following table summarizes the states of signals on output pins when Reset or HoldAck is active.
Table 19. Signal States During Reset or Hold Acknowledge
Signal Names
State When Reset Active
State When HoldAck Active
A6:29
AMuxCAS
BusReq
CAS0:3
Floating
Inactive (low)
Inactive (low)
Inactive (high)
Floating (set to input mode)
Operable (see note 1)
Operable (see note 1)
Operable (see notes 1 and 2)
CS0:3
CS4:7/RAS3:0
D0:31
DMAA0:3
Floating
Floating
Floating
Inactive (high)
Floating
CS floating, RAS operable (notes 1 and 2)
Floating (external master drives bus)
Inactive (high)
XAck
DRAMOE
DRAMWE
Inactive (high)
Inactive (high)
Inactive (high)
Operable (see note 1)
Operable (see notes 1 and 2)
Operable (see notes 1 and 2)
Inactive (low)
Inactive (low)
Floating
Floating unless initiating system reset
Operable (see note 1)
Active
Floating (input for XSize1)
Floating unless initiating system reset
Floating
Floating (set to input)
Floating (set to input)
Floating
Floating (set to input)
Inactive (high)
Floating (input for XSize0)
Operable (see note 1)
TS0:2
TS3:6[DP3:0]
Inactive (low)
Floating
WBE0:3[BE0:3]
XmitD
Floating
Inactive (high)
Operable (see note 1)
Operable (see note 1)[floating when
parity mode is enabled]
Operable (inputs for A4:5, A30:31)
Operable (see note 1)
Error
HoldAck
OE
Reset
R/W
TC0:2
TC3
TDO
Note:
1. Signal may be active while HoldAck is asserted, depending on the operation being performed by the 403GCX.
2. Signal may be placed in high impedance, depending on DRAM 3-state control setting in IOCR.
Bus Waveforms
The waveforms in this section represent external bus operations, including SRAM and DRAM accesses,
DMA transfers, and external master operations.
Write Byte Enable Encoding
The 403GCX provides four write byte enable signals (WBE0:3) to support 8-, 16-, and 32-bit devices, as
shown in Table 20. For an eight-bit memory region, WBE2:3 are encoded as A30:31 and WBE0 is the
byte-enable line. For a 16-bit region, WBE0 is the high-byte enable, WBE1 is the low-byte enable and
WBE2:3 are encoded as A30:31. For a 32-bit region, address bits 6:29 select the word address and
WBE0:3 select data bytes 0:3, respectively.
33
IBM PowerPC 403GCX
Table 20. Write Byte Enable Encoding
Transfer Size
Address
WBE0 = WE
WBE1 = 1
WBE2 = A30
WBE3 = A31
Byte
0
0
1
0
0
Byte
1
0
1
0
1
Byte
2
0
1
1
0
Byte
3
0
1
1
1
Transfer Size
Address
WBE0 = BHE
WBE1 = BLE
WBE2 = A30
WBE3 =A31
Half-word
0
0
0
0
0
Half-word
2
0
0
1
0
Byte
0
0
1
0
0
Byte
1
1
0
0
1
Byte
2
0
1
1
0
Byte
3
1
0
1
1
Transfer Size
Address
WBE0
WBE1
WBE2
WBE3
Word
0
0
0
0
0
8-Bit Bus
Width
16-Bit Bus
Width
32-Bit Bus
Width
Half-word
0
0
0
1
1
Half-word
2
1
1
0
0
Byte
0
0
1
1
1
Byte
1
1
0
1
1
Byte
2
1
1
0
1
Byte
3
1
1
1
0
Address Bus Multiplexing
To support DRAM memories with differing configurations and bus widths, the 403GCX provides an internally multiplexed address bus controlled by the BIU. Table 21 shows the multiplexed address outputs referenced by waveforms later in this section.
Table 21. Multiplexed Address Outputs
Address
Pins
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29
Addr Bits Out
in RAS Cycle
a6
a7
a8
a9 a10 a11 a12 a13 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22
Addr Bits Out
in CAS Cycle
xx
a6
a7
a8
a9 a10 a11 a12 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31
When the 403GCX is bus master and there are no bus operations in progress, the states of the address
bus outputs are determined by the setting of IOCR[ATC]. If this bit is set to zero, the address bus will be
placed in high impedance. If this bit is set to one, the last address held in the BIU address register will be
driven out on the address bus until bus operations resume.
34
IBM PowerPC 403GCX
SRAM Read-Write-Read with Zero Wait and One Hold
1
2
3
4
5
6
7
8
SysClk
A6:29,1
WBE2[A30],
WBE3[A31]
Read Address
Write Address
Read Address
Valid – BE
Valid – BE
Valid – BE
R/W
CSx
OE4
BLast5
WBE0:32,4
BE0:35
Data Out
Data In
D0:31
Error?
BusError
Data In
Error?
Error?
Bank Register Bit Settings
SLF
Burst
Mode
Bus Width
Ready
Enable
Wait
States
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits 15:16
Bit 17
Bits 18:23
Bit 24
Bit 25
Bit 26
Bit 27
Bits 28:30
0 or 1
0
xx
0
00 0000
0
0
0
0
001
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 20 on page 34 for WBE signal definitions based on bus width.
3. Byte Enable Mode IOCR[BEM] = 1. WBE0:3/BE0:3 are byte enables and BLast is the signal which appears on the
multiplexed OE[XSize1][BLast] output.
4. When in Byte Enable Mode IOCR[BEM] = 1, the BLast signal appears on the multiplexed OE[XSize1][BLast] output, as described in Table 4 on page 8.
5. Not Byte Enable Mode IOCR[BEM] = 0. WBE0:3/BE0:3 are write byte enables and OE is the signal which appears
on the multiplexed OE[XSize1][BLast] output.
35
IBM PowerPC 403GCX
SRAM, ROM, or I/O Write Request with Wait and Hold
1
2
3
4
5
6
Address
Valid
7
8
SysClk
A6:29,1
WBE2[A30],
WBE3[A31]
R/W
CSon=0
CSon=1
CSon=0
WEon=0
CSon=1,0
WEon=0,1
CSon=1
WEon=1
CSon=0
OEon=0
CSon=1,0
OEon=0,1
CSon=1
OEon=1
CSx5
OE4,5
WEoff=1
WEoff=0
WBE0:32,3,5
Data Out
D0:31
Wait + 1 Cycle
Hold
Error?
BusError
Bank Register Bit Settings
SLF
Burst
Mode
Bus Width
Ready
Enable
Wait
States
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits 15:16
Bit 17
Bits 18:23
Bit 24
Bit 25
Bit 26
Bit 27
Bits 28:30
0 or 1
0
xx
0
00 0011
0 or 1
0 or 1
0 or 1
0 or 1
001
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 20 for WBE signal definitions based on bus width.
3. WBE signals can be read/write byte enables based on the setting of IOCR[BEM]. See waveform and note 3 on
page 35.
4. When in Byte Enable Mode IOCR[BEM] = 1, the BLast signal appears on the multiplexed OE[XSize1][BLast] output, as described in Table 4 on page 8.
5. Wait must be programmed to a value ≥ (CSon + WEon + WEoff) and ≥ (CSon + OEon + WEoff).
If Wait > (CSon + WEon) and > (CSon + OEon), then all signals retain the values shown in cycle 4 until the Wait
time expires.
6. If Hold is programmed > 001, all signals retain the values shown in cycle 6 until the Hold timer expires.
36
IBM PowerPC 403GCX
SRAM, ROM, or I/O Read Request, Wait Extended with Ready
1
2
3
4
5
6
7
8
SysClk
A6:29,1
WBE2[A30],
WBE3[A31]
Address Valid
R/W
CSon=0
CSon=1
CSon=0
OEon=0
CSon=0,1
OEon=1,0
CSx5
CSon=1
OEon=1
OE4,5
WBE0:32,3
Sample Data
Data In
D0:31
Wait
Not
Ready
Ready7
Not
Ready
Sample Ready
Ready
Hold
Error?
BusError
Bank Register Bit Settings
SLF
Burst
Mode
Bus Width
Ready
Enable
Wait
States
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits 15:16
Bit 17
Bits 18:23
Bit 24
Bit 25
Bit 26
Bit 27
Bits 28:30
0 or 1
0
xx
1
00 0010
0 or 1
0 or 1
0 or 1
x
001
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 20 on page 34 for WBE signal definitions based on bus width.
3. WBE signals can be read/write byte enables based on the setting of IOCR[BEM]. See waveform and note 3 on
page 35.
4. When in Byte Enable Mode IOCR[BEM] = 1, the BLast signal appears on the multiplexed OE[XSize1][BLast] output, as described in Table 4 on page 8.
5. Wait must be programmed to a value ≥ (CSon + OEon). If Wait > (CSon + OEon), then all signals will retain the
values shown in cycle 4 until the Wait timer expires.
6. If Hold is programmed > 001, all output signals retain the values shown in cycle 7 until the Hold timer expires.
7. If Wait = 00 0000, the Ready input is ignored and single-cycle transfers occur. If Wait > 00 0000, Ready is sampled
starting after the Wait cycles have expired.
8. IOCR[SOR] = 0.
37
IBM PowerPC 403GCX
SRAM Read Extended with Ready (Asynchronous Ready Mode)
Cycle
1
2
3
4
5
6
7
8
9
SysClk
A6:291
WBE2/A30
WBE3/A31
Wait=000010
Sample
Ready
Hold=01
Valid
R/W
CSon=0
CSon=1
CSx
CSon=0
OEon=0
CSon=1, OEon=0 or
CSon=0, OEon=1
CSon=0
OEon=0
CSon=1, OEon=0 or
CSon=0, OEon=1
OE2
BLAST3
WBE0:32
BE0:33
Latch Data
Data In
D0:D31
4
READY
Bank Register Settings
SLF
Burst
Mode
Bus Width
Ready
Enable
Wait
States
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits 15:16
Bit 17
Bits 18:23
Bit 24
Bit 25
Bit 26
Bit 27
Bits 28:30
x
o
xx
1
000010
0 or 1
0 or 1
x
0
001
Notes:
1. WBE2:3 are address bits A30:31 if the bus width is programmed as byte or halfword.
2. Not Byte Enable Mode (IOCR[BEM] = 0). WBE0:3/BE0:3 are write byte enables and OE/BLAST is OE.
3. Byte Enable Mode (IOCR[BEM] = 1). WBE0:3/BE0:3 are byte enables and OE/BLAST is BLAST
4. Arrows indicate when READY is sampled.
5. IOCR[ARE] is set.
38
IBM PowerPC 403GCX
SRAM, ROM or I/O Burst Read with Wait and Hold
1
2
3
4
5
6
7
8
Addr2
Addr3
Address4
BE
BE
Valid BE
SysClk
A6:29,1
WBE2[A30],
WBE3[A31]
Address1
R/W
CSon=0
CSon=1
CSon=0
OEon=0
CSon=0,1
OEon=1,0
CSx5
OE4,5
BLast4
WBE0:32,3
BE0:33
Valid BE
D0:31
D1
BusError
Error?
D4
Error?
Error?
Burst + 1
Cycles
Burst + 1
Cycles
Error?
Burst + 1
Cycles
Wait + 1 Cycles5
D3
D2
Hold 6
Bank Register Bit Settings
SLF
Burst
Mode
Bus
Width
Ready
Enable
Bit 13
Bit 14
Bits 15:16
Bit 17
0 or 1
1
xx
0
Wait
States
Burst
Wait
Bits 18:21 Bits 22:23
0001
00
CSon
OEon
WEon
WEoff
Hold
Bit 24
Bit 25
Bit 26
Bit 27
Bits 28:30
0 or 1
0 or 1
x
x
001
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 20 on page 34 for WBE signal definitions based on bus width.
3. WBE signals can be read/write byte enables based on the setting of IOCR[BEM].
4. When in Byte Enable Mode (IOCR[BEM] = 1), the BLast signal appears on the multiplexed OE[XSize1][BLast] output, as described in Table 4 on page 8.
5. Wait must be programmed to a value ≥ (CSon + OEon). If Wait > (CSon + OEon), then all signals will retain the
values shown in cycle 3 until the Wait timer expires.
6. If Hold is programmed > 001, all output signals retain the values shown in cycle 7 until the Hold timer expires.
7. Data parity is only checked when IOCR[RDM] = 11 and BRHx[PCE] is set.
39
IBM PowerPC 403GCX
SRAM, ROM or I/O Burst Write with Wait, Burst Wait, and Hold
1
2
3
4
5
6
7
8
9 10 11 12 13 14
SysClk
A6:29,1
WBE2[A30],
WBE3[A31]
Address1
Addr2
Address4
Addr3
R/W
CSon=0
CSon=1
CSx5
OE4,5
BLast4
CSon=0 CSon=1,0 CSon=1
WEon=0 WEon=0,1 WEon=1
WEoff=1
WEoff=1
WEoff=1
WEoff=1 WEoff=0
BE
BE
Valid BE
Data2
Data3
Data4
WBE0:32,3
BE0:33
Valid BE
CSon=0 CSon=1,0 CSon=1
OEon=0 OEon=0,1 OEon=1
Data1
D0:31
Error
?
BusError
Error
?
Burst + 1
Cycles
Wait + 1 Cycles
Error
?
Burst + 1
Cycles
Error
?
Burst + 1
Cycles Hold
Bank Register Bit Settings
SLF
Burst
Mode
Bus
Width
Ready
Enable
Bit 13
Bit 14
Bits 15:16
Bit 17
0 or 1
1
xx
0
Wait
States
Burst
Wait
Bits 18:21 Bits 22:23
0100
01
CSon
OEon
WEon
WEoff
Hold
Bit 24
Bit 25
Bit 26
Bit 27
Bits 28:30
0 or 1
0 or 1
0 or 1
0 or 1
001
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 20 on page 34 for WBE signal definitions based on bus width.
3. WBE signals can be read/write byte enables based on the setting of a control bit in the IOCR.
4. When in Byte Enable Mode (IOCR bit 20 = 0), the BLast signal appears on the multiplexed OE[XSize1][BLast] output, as described in Table 4 on page 8.
5. Wait must be programmed to a value ≥ (CSon + WEon + WEoff) and ≥ (CSon + OEon + WEoff).
If Wait > (CSon + WEon) and > (CSon + OEon), then all signals retain the values shown in cycle 3 until the Wait
timer expires.
6. If Hold is programmed > 001, all output signals retain the values shown in cycle 12 until the Hold timer expires.
7. Data parity is only generated when IOCR[RDM] = 11.
40
IBM PowerPC 403GCX
DRAM 2-1-1-1 Page Mode Read
1
2
3
4
5
CAS
CAS
CAS
CAS
6
7
8
SysClk
A11:29,
WBE2[A30],
WBE3[A31]
RAS
Row
Pre-Charge
Column4
Column1 Column2 Column3
AMuxCAS
R/W
RAS
CAS0:3
DRAMOE
DRAMWE
Note 8
Data1
D0:31
Data2
Data3
Data4
Note 7
Error
?
Error
?
Error
?
BusError
Error
?
Bank Register Bit Settings
SLF
ERM
Bus
Width
Ext
Mux
Bit 13 Bit 14 Bits 15:16 Bit 17
0 or 1
0
xx
x
RAS-to- Refresh
CAS
Mode
Bit 18
Bit 19
0
0
Page
Mode
First
Access
Burst
Access
Bit 20 Bits 21:22 Bits 23:24
1
00
00
Prechg Refresh Refresh
Cycles
RAS
Rate
Bit 25
Bit 26
Bits 27:30
0
x
xxxx
Notes:
1. For burst access, the addresses represented by Columns 1 to 4 does not necessarily indicate that they are in
incremental address order. Typically, burst access is target word first.
2. If internal mux mode is used, address bits A11:29 represent address bits described in Table 21 on page 34.
3. During internal mux mode access, A6:10 retain their unmultiplexed values.
4. If external mux mode is used, A11:29 are unaffected and do not change between CAS and RAS cycles.
5. If bus width is programmed as byte or half-word, WBE2:3 represent address bits A30:31 regardless of mux mode.
6. WBE0:1 are always ones during DRAM transfers.
7. Data is latched on the rising edge of SysClk when IOCR[DRC] = 0 (default setting).
8. Data is latched later (on the rising edge of CAS) if IOCR[DRC] = 1.
41
IBM PowerPC 403GCX
EDO DRAM 2-1-1-1 Burst Read Followed by Single Transfer Read
1
Cycle
2
3
RAS
CAS0
4
5
CAS1
CAS2
6
CAS3
7
8
9
Pre-Charge
10
11
12
RAS
CAS0
Pre-Chg
13
SysClk
A6:291
WBE2/A30
WBE3/A31
Row
Addr
Col 1
Col 2
Col 3
Row
Addr
Col 4
Column
Addr
AMuxCAS
R/W
RAS
CAS
DramOE
DramWE
D0:31, DP0:3
D0
D1
D2
D3
?
?
?
?
D4
Note 2
BusError
Error?
Error?
Bank Register Bit Settings
SLF
ERM Bus Width
Ext RAS-to- Refresh Page
Mux
CAS
Mode Mode
Bit 13 Bit 14 Bits 15:16 Bit 17
x
0
10
0
Bit 18
Bit 19
0
0
First
Access
Burst
Access
Bit 20 Bits 21:22 Bits 23:24
1
00
00
Prechg Refresh Refresh
Cycles
RAS
Rate
Bit 25
Bit 26
Bits 27:30
0
1
xxxx
Notes:
1. IOCR[EDO] is set and IOCR[DRC] is cleared.
2. Data is latched with respect to the fall of the internal system clock (duty-cycle corrected).
3. Data parity, if enabled, matches the timing of data bus transfers.
42
IBM PowerPC 403GCX
DRAM 3-2-2-2 Page Mode Write
1
2
3
4
5
6
7
8
9
RAS
CAS
CAS
CAS
CAS
CAS
CAS
CAS
CAS
10
11
12
SysClk
A11:29
Row
Column1
Column2
Column3
Data1
Data2
Data3
Pre-Chg
Column4
AMuxCAS
R/W
RAS
CAS0:3
DRAMOE
DRAMWE
D0:31
Error?
BusError
Error?
Data4
Error?
Error?
Bank Register Bit Settings
SLF
ERM
Bus
Width
Ext
Mux
Bit 13 Bit 14 Bits 15:16 Bit 17
0 or 1
0
xx
x
RAS-to- Refresh
CAS
Mode
Bit 18
Bit 19
0
0
Page
Mode
First
Access
Burst
Access
Bit 20 Bits 21:22 Bits 23:24
1
01
01
Prechg Refresh Refresh
Cycles
RAS
Rate
Bit 25
Bit 26
Bits 27:30
0
x
xxxx
Notes:
1. For burst access, the addresses represented by Columns 1 to 4 do not necessarily indicate that they are in incremental address order. Typically, burst access is target word first.
2. If internal mux mode is used, address bits A11:29 represent address bits described in Table 21 on page 34.
3. During internal mux mode access, A6:10 retain their unmultiplexed values.
4. If external mux mode is used, A11:29 are unaffected and do not change between CAS and RAS cycles.
5. If bus width is programmed as byte or half-word, WBE2:3 represent address bits A30:31 regardless of mux mode.
6. WBE0:1 are always ones during DRAM transfers.
7. DRAM read on CAS, IOCR[DRC], and EDO DRAM, IOCR[EDO], modes do not affect writes.
43
IBM PowerPC 403GCX
EDO DRAM 3-1-1-1 Burst Read Followed by Single Transfer Read
Cycle
1
2
3
4
5
6
7
8
RAS
CAS0
CAS0
CAS1
CAS2
CAS3
Pre-Chg
9
10 11 12 13 14 15 16
RAS
CAS
CAS
Pre-Chg
SysClk
A6:291
WBE2/A30
WBE3/A31
Row
Addr
Col 1
Col 2
Row
Addr
Col 4
Col 3
Column
Addr
AMuxCAS
R/W
RAS
CAS
DramOE
DramWE
D0:31
D0
D1
D2
D3
D4
Note 2
Latch data with fall of CAS
?
BusError
?
?
Error?
?
Error?
Bank Register Bit Settings
SLF
ERM
Bus
Width
Ext
Mux
Bit 13 Bit 14 Bits 15:16 Bit 17
x
0/1
10
0
RAS-to- Refresh
CAS
Mode
Bit 18
Bit 19
0
0
Page
Mode
First
Access
Burst
Access
Bit 20 Bits 21:22 Bits 23:24
1
01
00
Prechg Refresh Refresh
Cycles
RAS
Rate
Bit 25
Bit 26
Bits 27:30
0
x
xxxx
Notes:
1. IOCR[EDO] is set and IOCR[DRC] is cleared.
2. Data is latched with respect to the fall of the internal system clock (duty-cycle corrected).
3. Data parity, if enabled, matches the timing of data bus transfers.
44
IBM PowerPC 403GCX
DRAM Read-Write-Read, One Wait
1
2
3
4
RAS
CAS
CAS
5
6
7
PreCharge RAS
CAS
8
9 10 11 12 13 14 15 16
SysClk
A11:29
Row1
Column1
PreCAS Charge RAS
Column2
Row2
CAS
Row3
CAS
PreCharge
Column3
AMuxCAS
R/W
RAS
CAS0:3
DRAMOE
DRAMWE
Data2
Data1
D0:31
Error
?
BusError
Data3
Error
?
Error
?
Bank Register Bit Settings
SLF
ERM
Bus
Width
Ext
Mux
Bit 13 Bit 14 Bits 15:16 Bit 17
0 or 1
0
xx
x
RAS-to- Refresh
CAS
Mode
Bit 18
Bit 19
0
0
Page
Mode
First
Access
Burst
Access
Bit 20 Bits 21:22 Bits 23:24
0
01
xx
Prechg Refresh Refresh
Cycles
RAS
Rate
Bit 25
Bit 26
Bits 27:30
0
x
xxxx
Notes:
1. If internal mux mode is used, address bits A11:29 represent address bits described in Table 21 on page 34.
2. During internal mux mode access, A6:10 retain their unmultiplexed values.
3. If external mux mode is used, A11:29 are unaffected and do not change between CAS and RAS cycles.
4. If bus width is programmed as byte or half-word, WBE2:3 represent address bits A30:31 regardless of mux mode.
5. WBE0:1 are always ones during DRAM transfers.
45
IBM PowerPC 403GCX
DRAM Three-state - Refresh request before and after HoldAck
1
Cycle
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SysClk
A6:29
WBE2/A30
WBE3/A31
HoldReq
HoldAck
RAS0:3
E
F
CAS0:3
F
0
F
F
F
F
D
0
F
F
DramWE,
DramOE,
R/W,
OE/XSize1,
EOT3/TC3/XSize0,
WBE0:3
Bank 4 refresh request
gets in just before
HoldAck
External master has
control of bus;
refreshes held off until
out of HoldAck
Bank 5 refresh counter
expired while in
HoldAck. Refresh of
bank as soon as out of
HoldAck
Bank Register Bit Settings
SLF
ERM
x
x
Bus
Ext
Width Mux
10
Note:
1. IOCR[EDT] is set.
46
0
RAS-to- Refresh
CAS
Mode
x
0
Page
Mode
x
First
Burst
Access Access
x
x
Prechg Refresh Refresh
Cycles
RAS
Rate
x
0
xxxx
IBM PowerPC 403GCX
DMA Buffered Single Transfer from Peripheral to 3-Cycle DRAM
1
2
3
Sync
Sync
4
5
6
7
8
9
10
11
12
SysClk
DMA
Ack
BIU
Req
RAS
CAS
CAS
Pre-Chg
DMAR
DMAA
Row
A11:29
Column
R/W
RAS
CAS0:3
DRAMOE
DRAMWE
Data
D0:31
Data
OE
WBE0:3
Bank Register Bit Settings
SLF
ERM
Bus
Width
Ext
Mux
Bit 13 Bit 14 Bits 15:16 Bit 17
0 or 1
0
10
RAS-to- Refresh
CAS
Mode
Bit 18
Bit 19
0
0
0
Page
Mode
First
Access
Burst
Access
Prechg Refresh Refresh
Cycles
RAS
Rate
Bit 20 Bits 21:22 Bits 23:24
0
01
Bit 25
Bit 26
Bits 27:30
0
x
xxxx
xx
DMA Control Register Bit Settings
Transfer Direction Transfer Width Transfer Mode PeripheralSetup Peripheral Wait Peripheral Hold
Bit 2
Bits 4:5
Bits 9:10
Bits 11:12
Bits 13:18
Bits 19-21
1
10
00
00
00 0000
000
Notes:
1. DMAR must be inactive inactive at the start of cycle 9 to guarantee a single transfer.
2. This waveform assumes that the internal address mux is used.
3. CAS0 is used for byte accesses, CAS0:1 for halfwords, and CAS0:3 for fullwords.
47
IBM PowerPC 403GCX
DMA Fly-By Single Transfer, Write to 3-Cycle DRAM
1
2
3
Sync
Sync
4
5
6
7
BIU Req RAS
CAS
CAS
8
9
10
11
12
SysClk
Pre-Chg
DMAR
S=0
S=1
S=2
(S = peripheral setup time)
DMAA
DMADXFER
A11:29
Row
Column
R/W
RAS
CAS0:3
DRAMOE
DRAMWE
D0:31
Data
Bank Register Bit Settings
SLF
ERM Bus Width
Ext
Mux
RAS-to- Refresh Page
CAS
Mode Mode
Bit 13 Bit 14 Bits 15:16 Bit 17
0 or 1
0
10
0
Bit 18
Bit 19
0
0
First
Access
Burst
Access
Bit 20 Bits 21:22 Bits 23:24
0
01
Prechg Refresh Refresh
Cycles
RAS
Rate
Bit 25
Bit 26
Bits 27:30
0
x
xxxx
xx
DMA Control Register Bit Settings
Transfer Direction Transfer Width Transfer Mode PeripheralSetup Peripheral Wait Peripheral Hold
Bit 2
Bits 4:5
Bits 9:10
Bits 11:12
Bits 13:18
1
10
01
Note 3
xx xxxx
Notes:
1. DMAR must be inactive in cycle 7 (last DMAA cycle) to guarantee a single transfer.
2. Peripheral data bus width must match DRAM bus width.
3. See diagram for settings.
4. This waveform assumes that the internal address mux is used.
5. CAS0 is used for byte accesses, CAS0:1 for halfwords, and CAS0:3 for fullwords.
48
Bits 19-21
xxx
IBM PowerPC 403GCX
DMA Fly-By Continuous Burst to 3-Cycle DRAM
1
2
3
4
5
6
7
8
9
10
Sync
BIU
Req
RAS
CAS
CAS
CAS
CAS
CAS
CAS
SysClk
Sync
1
DMAR
2
S=0
DMAA
12
Pre-Chg
3
S=1
(S = peripheral setup time)
1
1
11
1
2
2
3
3
DMADXFER
Row
A11:29
Column1
Column2
Data1
Data2
Column3
R/W
RAS
CAS0:3
DRAMOE
DRAMWE
D0:31
Data3
Bank Register Bit Settings
SLF
ERM
Bus
Width
Ext
Mux
Bit 13 Bit 14 Bits 15:16 Bit 17
0 or 1
0
10
0
RAS-to- Refresh Page
CAS
Mode Mode
Bit 18
Bit 19
0
0
First
Access
Burst
Access
Bit 20 Bits 21:22 Bits 23:24
1
01
01
Prechg Refresh Refresh
Cycles
RAS
Rate
Bit 25
Bit 26
Bits 27:30
0
x
xxxx
DMA Control Register Bit Settings
Transfer
Direction
Transfer
Width
Transfer
Mode
Peripheral
Setup
Peripheral
Wait
Peripheral
Hold
Burst Mode
Bit 2
Bits 4:5
Bits 9:10
Bits 11:12
Bits 13:18
Bits 19-21
Bit 25
1
10
01
Note 3
xx xxxx
xxx
1
Notes:
1. DMAR must be inactive at the end of cycle 10 (last DMAA cycle) to guarantee three transfers.
2. Peripheral data bus width must match DRAM bus width.
3. See diagram for settings.
4. This waveform assumes that the internal address mux is used.
5. CAS0 is used for byte accesses, CAS0:1 for halfwords, and CAS0:3 for fullwords.
6. Numbers (1,2,3,...) in the DMAR signal represent when DMAR is sampled and accepted. Numbers (1,2,3,...) in the
DMAA signal represent the transfers associated with the accepted DMAR.
49
IBM PowerPC 403GCX
External Master Nonburst DRAM Read with HoldReq/HoldAck
1
2
3
4
5
6
7
8
RAS
CAS
CAS
9
10
11
12
SysClk
Ext Bus Master
XReq
BSel
PreCharge
HoldReq
HoldAck
XReq1
R/W
XSize0:11
10
XAck1
A4:312
403 Master
D0:31
403 Master
HiZ
Valid Address - Ext Master
403 Address
HiZ
DRAM
drives bus
403 Data
DRAM Control
AMuxCAS
RASx
CAS0:3
DRAMOE
DRAMWE
Bank Register Bit Settings
SLF
ERM
Bus
Width
Ext
Mux
Bit 13 Bit 14 Bits 15:16 Bit 17
0 or 1
0
10
1
RAS-to- Refresh
CAS
Mode
Bit 18
Bit 19
0
0
Page
Mode
First
Access
Burst
Access
Bit 20 Bits 21:22 Bits 23:24
0
01
xx
Prechg Refresh Refresh
Cycles
RAS
Rate
Bit 25
Bit 26
Bits 27:30
0
x
xxxx
Notes:
1. XReq, XSize0, XSize1, and XAck are multiplexed with DMAR3, EOT3/TC3, OE, and DMAA3, respectively.
2. A4, A5, A30, and A31 are multiplexed with WBE0, WBE1, WBE2, and WBE3, respectively.
50
IBM PowerPC 403GCX
External Master DRAM Burst Write, 3-2-2-2 Page Mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SysClk
PreXReq BSel RAS CAS CAS CAS CAS CAS CAS CAS CAS Chg
Ext Bus Master
HoldReq
HoldAck
XReq3
R/W
XSize0:11,2,3
11
11
11
XAck
A4:314
D0:31
Valid Address1 - Ext Master
Address2
Address3
Address4
Valid Data1 - Ext Master
Data2
Data3
Data4
DRAM Control
AMuxCAS
RASx
CAS0:3
DRAMOE
DRAMWE
Bank Register Bit Settings
SLF
ERM
Bus
Width
Ext
Mux
Bit 13 Bit 14 Bits 15:16 Bit 17
0 or 1
0
10
1
RAS-to- Refresh
CAS
Mode
Bit 18
Bit 19
0
0
Page
Mode
First
Access
Bit 20 Bits 21:22
1
01
Burst
Access
Prechg Refresh Refresh
Cycles
RAS
Rate
Bits
23:24
Bit 25
Bit 26
Bits 27:30
01
0
x
xxxx
Notes:
1. XReq, XSize0, XSize1, and XAck are multiplexed with DMAR3, EOT3/TC3, OE, and DMAA3, respectively.
2. XSize0:1 = 11 indicates a burst transfer at the width of the DRAM device.
3. The burst is terminated in cycle 12 by deasserting the XReq input signal. A burst may also be terminated by deasserting either XSize0 or XSize1.
4. A4, A5, A30, and A31 are multiplexed with WBE0, WBE1, WBE2, and WBE3, respectively.
51
IBM PowerPC 403GCX
Ordering Information
This section provides the part numbering nomenclature for the 403GCX. For availability, contact your
local IBM sales office.
Table 22. PPC403GCX Part Number
IBM Part Number
06K6173
OEMLS Part Number
IBM25403GCX-3JC76C2
Processor Bus
Frequency
Package
Revision Level
76 MHz
PQFP
C
IBM Part Number Key for 403GCX
IBM25403GCX-3JC76C2
403 Family
Grade:
3 = 100 FITS
2 = 25 FITS
Package:
J - PQFP
B - PBGA
Revision Level
52
Clock Doubler
Commercial
CPU speed: 50, 66, 80
IBM PowerPC 403GCX
53
© Copyright IBM Corporation 1996,2000. All rights reserved.
Printed in the USA on recycled paper.
8-00
IBM Microelectronics, PowerPC, PowerPC Architecture, and 403GCX
are trademarks, IBM and the IBM logo are registered trademarks of IBM
Corporation.
This document may contain preliminary information and is subject to
change by IBM without notice. IBM assumes no responsibility of liability
for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under
the intellectual property rights of IBM or third parties. The products
described in this document are not intended for use in implantation or
other direct life support applications where malfunction may result in
direct physical harm or injury to persons. NO WARRANTIES OF ANY
KIND, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
PURPOSE, ARE OFFERED IN THIS DOCUMENT.
IBM Microelectronics Division
1580 Route 52, Bldg. 502
Hopewell Junction, NY 12533-6531
Tel: (800) PowerPC
SC09-3033-SP
08.16.00