. CPC700 Memory Controller and PCI Bridge Features map essential to making it appear like a device but does not preclude it from being a host. • PowerPC 60x/7xx bus. • 66.66 MHz (IBM25CPC700BB3B66). • 83.33 MHz (IBM25CPC700BB3B83). • Synchronous DRAM interface operates at the processor bus speed with support for ECC. • PCI Revision 2.1 Compliant Interface. • ROM/SRAM/External peripheral controller. • Interrupt Controller supports interrupts from a variety of sources. • Programmable Timers. • Two 2-wire, 8-bit, 16550 compatible UARTs. • Two independent IIC interfaces. • Byte swapping supported for bi-endian operation. • Internal PCI Bus Arbiter for PCI bus speeds up to 33.33 MHz (may be disabled for use with an external arbiter). • Supports independent primary and secondary resource management mapping. This feature enables the CPC700 to effectively isolate local processing resources from host side memory and I/O allocations. Through the use of three independent translation decodes, the PowerPC operating environment access to PCI is managed solely by the PowerPC. • Dual address capabilities enhance the CPC700’s capabilities by allowing it to manage, control, or test beyond 4GB limitations. • Support for shared memory is locally mapped to the processor’s ROM or SDRAM through PCI standard Base Address Registers. Two Memory I/O BARs are available for requesting host memory or I/O resources and managing PCI to PowerPC access. • Provides a special interface enabling the CPC700 to generate any PCI command, including Type 1 configuration cycles. • Fully buffers PCI writes and supports PCI read pre-fetching from local memory. • 32-bit PCI bus operates at frequencies from 25MHz to 66.66 Mhz. • Hardware enforces cache coherency. • Uses standard type 0 PCI configuration register • Implemented in CMOS5SE. cpc700_ds2.fm 05/04/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CPC700 Memory Controller and PCI Bridge Contents Section 1. “Description” ....................................................................................................... 3 Section 2. “Electrical Characteristics” .................................................................................. 4 Section 3. “Signal Lists” ..................................................................................................... 12 Section 4. “Package Information”....................................................................................... 18 Section 5. “Ordering Information” ...................................................................................... 19 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 cpc700_ds2.fm 05/04/00 CPC700 Memory Controller and PCI Bridge 1. Description The CPC700 contains a bridge from the PowerPC processor to the PCI bus, as well as a high-speed memory controller, internal peripherals, and control for external ROM and external peripherals. The CPC700 is a general purpose solution for interfacing the high performance, superscalar, PowerPC 603e, 740, and 750 families of RISC microprocessors to a PCI bus and system memory. CPC700 Embedded Bridge Functional Block Diagram 66.66 or 83.33 MHz Processor Bus 5 104 CPC700 ASIC SDRAM ROM Peripherals Processor Interface Data Parity System & PLL 1/2X OPB Bridge ECC 66.66 or 83.33 MHz Processor Local Bus (PLB) 8 Parity or Arbiter DCR Bus PCI Arb PCI Interface JTAG Misc. 33.33 MHz On Chip Peripheral Bus (OPB) 119 UART 2 UART 2 IIC 2 IIC 2 GPT (Timers) UIC (interrupts) 52 25 to 66.66 MHz PCI Bus cpc700_ds2.fm 05/04/00 9 1 12 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CPC700 Memory Controller and PCI Bridge 2. Electrical Characteristics Absolute Maximum Ratings Characteristic Symbol Value Unit VDD 0 to 3.6 V PLL0 Supply Voltage AVDD0 0 to 3.6 V PLL1 Supply Voltage AVDD1 0 to 3.6 V VIN 0 to 3.6 V TSTG -65 to 150 °C Supply Voltage Input Voltage Storage Temperature Range Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage VDD 3.135 3.3 3.465 V PLL0 Supply Voltage VDD 3.135 3.3 3.465 V PLL1 Supply Voltage VDD 3.135 3.3 3.465 V Input Logic High (3.3V receivers) VIH 2.0 VDD V Input Logic High (5.0V receivers) VIH 2.0 5.50 V Input Logic Low VIL 0.0 0.8 V Output Logic High VOH 2.4 VDD V Output Logic Low VOL 0.0 0.4 V Input Leakage Current Group 1 IIL1 — <1 10 µA 2 Input Leakage Current Group 2 IIL2 — — 400 µA 3 Input Leakage Current Group 3 IIL3 — — -250 µA 4 Input Max Allowable Overshoot (3.3V receivers) VIMAO3 VDD + 0.6 V Input Max Allowable Overshoot (5.0V receivers) VIMAO5 5.50 V Input Max Allowable Undershoot (3.3V receivers) VIMAU3 -0.60 V Input Max Allowable Undershoot (5.0V receivers) VIMAU5 -0.60 V Output Max Allowable Overshoot (3.3V receivers) VOMAO3 VDD + 0.6 V Output Max Allowable Overshoot (5.0V receivers) VOMAO5 5.50 V Output Max Allowable Undershoot (3.3V receivers) VOMAU3 -0.60 V 105 °C Die Junction Temperature 1. 2. 3. 4. 5. TJ -40 Notes Refer to the Output Signal Power Ranges Table for power information. Input leakage currents for all inputs except those indicated in Notes 3 and 4. Input leakage current for signals TEST_ENABLE, GBL_N, TSIZ[0], TSIZ[1], TT[0], AND TT[4]. Input leakage current for signals TSIZ[2], TT[1], TRST_N, TDI, TMS, TCK, DI1, AND DI2. In addition to any other specification herein, all CPC700 PCI bus I/Os meet or exceed the PCI v2.1 requirements for 3.3V and 5.0V signalling environments. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 cpc700_ds2.fm 05/04/00 CPC700 Memory Controller and PCI Bridge Capacitance Parameter Symbol Min Max Unit Notes Input Capacitance Group 1 CIN1 — 5 pF 1, 3 Input Capacitance Group 1 CIN2 — 8 pF 2, 3 1. Group 1 includes all signals except those indicated in note 2. 2. Group 2 includes GBL_N, TSIZ[0], TSIZ[1], TT[4], and TT[0]. 3. Excludes test signals TEST_ENABLE, DI1_N, DI2_N, RI_N, and JTAG signals. DC Electrical Characteristics Parameter Symbol Max Unit Notes Thermal Resistance, Junction to Ambient 15 °C/W 1 Thermal Resistance, Junction to Balls 5.9 °C/W 1,2 420 (66.66 MHz) 500 (83.33 MHz) mA 3 3.465 V 14 mA 3.465 V 14 mA Active Operating Current Min Typ IDD PLL0 Voltage VPLL0 PLL0 VDD Input current IPLL0 PLL1 Voltage VPLL1 PLL1 VDD Input current IPLL1 3.135 3.3 3.135 3.3 1. Under normal operating conditions, the CPC700 does not require a heat sink. 2. Measured from junction to outside corner ball. 3. IDD Max is measured at Tc = 105 °C, worst case operating conditions for frequency and voltage, and a capacitive load of 50 pF. Power Processor/Memory Frequency Units Notes Power 66.66 83.33 MHz Typical 1.1 1.2 W 1, 2 Maximum 1.6 1.9 W 2, 3, 4 1. Typical power is measured at VDD=3.3V, 27 °C in a system executing typical sequences. 2. Guaranteed by design and characterization and is not tested. 3. Maximum power is measured at VDD=3.6V, 120 °C in a system executing worse case sequences with the CPU caches disabled 4. Maximum power at – 40 °C can be derived by subtracting 0.05 W from the maximum power number at 120 °C. cpc700_ds2.fm 05/04/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CPC700 Memory Controller and PCI Bridge Common I/O Specifications for 66.66MHz and 83.33MHz Signal I/O Input (ns) Setup Time Hold Time (min) (min) Output (ns) Valid Delay Hold Time (max) (min) PCI Bus Asynchronous Operation1, 2, 3, 5, 7 AD[0:31] I/O 1.6 0.0 C/BE_N[0:3] I/O 2.6 0.0 DEVSEL_N I/O 2.9 0.0 FRAME_N I/O 2.9 0.0 IDSEL I 1.8 0.0 IRDY_N I/O 2.8 0.0 PAR I/O 2.3 0.0 PERR_N I/O 1.8 0.0 RST_N O STOP_N I/O 2.7 0.0 TRDY_N I/O 2.6 0.0 SERR_N O PCI Bus 2:1 Synchronous Operation1, 2, 4, 5, 7 AD[0:31] I/O 3.8 0.0 C/BE_N[0:3] I/O 5.5 0.0 DEVSEL_N I/O 4.8 0.0 FRAME_N I/O 5.2 0.0 IDSEL I 2.5 0.0 IRDY_N I/O 5.2 0.0 PAR I/O 4.7 0.0 PERR_N I/O 4.1 0.0 STOP_N I/O 3.6 0.0 TRDY_N I/O 4.6 0.0 SERR_N O (Part 1 of 3) Output Current (mA) I/O H I/O L (max) (min) 5.6 5.7 5.8 5.6 1.6 1.7 1.6 1.8 16.8 16.8 16.8 16.8 14 14 14 14 5.3 5.3 5.4 n/a 5.8 5.8 5.8 1.7 1.8 1.7 n/a 1.7 1.7 1.7 16.8 16.8 16.8 13.4 16.8 16.8 16.8 14 14 14 9 14 14 14 8.7 8.6 8.4 8.3 2.9 2.8 2.8 2.8 7.9 8.5 8.8 8.5 8.5 8.3 2.8 2.8 3.1 2.9 2.9 2.3 16.8 16.8 16.8 16.8 16.8 16.8 14 14 14 14 14 14 16.8 16.8 16.8 16.8 14 14 14 14 Clock Notes PCI (A) PCI (A) PCI (A) PCI (A) PCI (A) PCI (A) PCI (A) PCI (A) PCI (A) PCI (A) PCI (A) PCI (S) PCI (S) PCI (S) PCI (S) PCI (S) PCI (S) PCI (S) PCI (S) PCI (S) PCI (S) PCI (S) 1. Timing is guaranteed by design and characterization and is not tested. 2. All I/O timing (CPU, PCI, and other) is specified into a 50pf load. All timings include errors (if any) induced by internal PLLs, given a clock input with no jitter. Sys (2X): Timings shown are referenced to the rising edge of the output of PLL0, operating at twice the frequency of the SYS_CLK input. PLL0 locks to the rising edge of SYS_CLK. Sys (1X): Timing is referenced to SYS_CLK. PCI (A): PCI interface in asynchronous mode. Timings are referenced to the PCI_CLK input. Logic is clocked by the output of PLL1, which repeats PCI_CLK. PCI (S): PCI interface in synchronous mode. Timings are referenced to the SYS_CLK, which is assumed to be exactly equal to the PCI clock. 3. Asynchronous PCI timings reflect 66.66 MHz PCI operation. Output timings are specified into a 50pF load. 4. PCI in 2:1 (CPU @ 66.66MHz, PCI @ 33.33 MHz). 5. All PCI timings meet or exceed PCI v2.1 specifications. System designers should design using the PCI timing budgets of the PCI version 2.1 specifications. Output delays are specified into a 50pF lumped load model. 6. IIC output timing specified into a 250pF load. 7. This is a 5.0V receiver. Other receivers are 3.3V receivers. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 cpc700_ds2.fm 05/04/00 CPC700 Memory Controller and PCI Bridge Common I/O Specifications for 66.66MHz and 83.33MHz Signal I/O Input (ns) Setup Time Hold Time (min) (min) Output (ns) Valid Delay Hold Time (max) (min) (Part 2 of 3) Output Current (mA) I/O H I/O L (max) (min) Clock Notes PCI Arbitration1, 2, 5 GNT0_N/REQ_N REQ0_N/GNT_N REQ[1:5]_N GNT[1:5]_N 8.8 2.7 16.8 14 PCI (A) 9.3 2.9 16.8 14 PCI (S) 5.3 1.7 16.8 14 PCI (A) 7.6 2.6 16.8 14 PCI (S) O 4.7 0.0 PCI (A) 4.7 0.0 Sys (S) 2.7 0.0 PCI (A) 5.1 0.0 PCI (S) 4.4 0.0 PCI (A) 4.4 0.0 PCI (S) I I 8.8 2.7 16.8 14 PCI (A) 9.3 2.9 16.8 14 PCI (S) O Async Internal Arbiter Sync Internal Arbiter Async External Arbiter Sync External Arbiter Async Internal Arbiter Sync Internal Arbiter Async External Arbiter Sync External Arbiter Async Internal Arbiter Sync Internal Arbiter Async Internal Arbiter Sync Internal Arbiter 1. Timing is guaranteed by design and characterization and is not tested. 2. All I/O timing (CPU, PCI, and other) is specified into a 50pf load. All timings include errors (if any) induced by internal PLLs, given a clock input with no jitter. Sys (2X): Timings shown are referenced to the rising edge of the output of PLL0, operating at twice the frequency of the SYS_CLK input. PLL0 locks to the rising edge of SYS_CLK. Sys (1X): Timing is referenced to SYS_CLK. PCI (A): PCI interface in asynchronous mode. Timings are referenced to the PCI_CLK input. Logic is clocked by the output of PLL1, which repeats PCI_CLK. PCI (S): PCI interface in synchronous mode. Timings are referenced to the SYS_CLK, which is assumed to be exactly equal to the PCI clock. 3. Asynchronous PCI timings reflect 66.66 MHz PCI operation. Output timings are specified into a 50pF load. 4. PCI in 2:1 (CPU @ 66.66MHz, PCI @ 33.33 MHz). 5. All PCI timings meet or exceed PCI v2.1 specifications. System designers should design using the PCI timing budgets of the PCI version 2.1 specifications. Output delays are specified into a 50pF lumped load model. 6. IIC output timing specified into a 250pF load. 7. This is a 5.0V receiver. Other receivers are 3.3V receivers. cpc700_ds2.fm 05/04/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CPC700 Memory Controller and PCI Bridge Common I/O Specifications for 66.66MHz and 83.33MHz Signal ROM Interface ROM_ALE ROM_OE_N ROM_RD_N ROM_READY ROM_RNW ROM_WE_N ROM_WR_N IIC Port IIC_SCL IIC_SDA UART Ports UART_RX UART_TX Miscellaneous RESET_OUT_N IRQ_OUT_N TDO I/O Input (ns) Setup Time Hold Time (min) (min) O O O I O O O 3.5 I/O I/O 3.0 2.0 1.0 1.0 I O 2.5 1.0 Output (ns) Valid Delay Hold Time (max) (min) (Part 3 of 3) Output Current (mA) I/O H I/O L (max) (min) 12.1 8.1 9.0 4.5 2.8 3.3 10.2 19 13.4 6.8 16 9 8.6 7.8 9.0 3.1 2.8 3.3 13.4 19 13.4 9 16 9 Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) 22.7 21.6 4.3 4.3 13.4 13.4 9 9 Sys (1X) Sys (1X) 11.1 3.9 10.2 6.8 Sys (1X) Sys (1X) 19 10.2 10.2 16 6.8 6.8 1.0 O O O Clock Notes 7 6, 7 6, 7 Sys (2X) 1. Timing is guaranteed by design and characterization and is not tested. 2. All I/O timing (CPU, PCI, and other) is specified into a 50pf load. All timings include errors (if any) induced by internal PLLs, given a clock input with no jitter. Sys (2X): Timings shown are referenced to the rising edge of the output of PLL0, operating at twice the frequency of the SYS_CLK input. PLL0 locks to the rising edge of SYS_CLK. Sys (1X): Timing is referenced to SYS_CLK. PCI (A): PCI interface in asynchronous mode. Timings are referenced to the PCI_CLK input. Logic is clocked by the output of PLL1, which repeats PCI_CLK. PCI (S): PCI interface in synchronous mode. Timings are referenced to the SYS_CLK, which is assumed to be exactly equal to the PCI clock. 3. Asynchronous PCI timings reflect 66.66 MHz PCI operation. Output timings are specified into a 50pF load. 4. PCI in 2:1 (CPU @ 66.66MHz, PCI @ 33.33 MHz). 5. All PCI timings meet or exceed PCI v2.1 specifications. System designers should design using the PCI timing budgets of the PCI version 2.1 specifications. Output delays are specified into a 50pF lumped load model. 6. IIC output timing specified into a 250pF load. 7. This is a 5.0V receiver. Other receivers are 3.3V receivers. IRQ [0:11], RESET_N, and PCI_66_STRAP are asynchronous inputs that use 5.0V receivers. Timing to the clock and output characteristics are not specified for these pins. There is an internal 13KΩ pull-down resistor connected to pin TEST_ENABLE. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 cpc700_ds2.fm 05/04/00 CPC700 Memory Controller and PCI Bridge CPU and Memory Interface I/O Specifications for 66.66 MHz Signal I/O CPU Bus Interface1, 2 A[0:31] I/O AACK_N O AP[0:3] I/O ARTRY_N I/O BG_N O BR_N I DBG_N O DH[0:31] I/O DL[0:31] I/O DP[0:7] I/O GBL_N O MCP_N O MCP_REQ I TA_N O TBST_N I/O TS_N I/O TSIZ[0:2] I/O TT[0:4] I/O Input (ns) Setup Time Hold Time (min) (min) 3.0 1.0 2.5 2.5 1.0 1.0 3.0 1.0 3.0 3.0 2.5 1.0 1.0 1.0 2.5 1.0 2.5 3.0 2.5 2.5 1.0 1.0 1.0 1.0 Memory Controller Interface1, 2 BA0 O BA1 O BANK_SEL_N[0:4] O CAS_N O CKE O M_DATA[0:63] I/O 3.0 DQM[0] O ECC[0] I/O 3.0 ECC[1:7]/DQM[1:7] I/O 3.0 MA[0:12] O RAS_N O WE_N O 1.0 1.0 1.0 Output (ns) Valid Delay Hold Time (max) (min) Output Current (mA) I/O H I/O L (max) (min) Clock Notes 10.3 9.3 9.4 8.5 8.5 3.5 3.5 3.4 3.2 3.2 10.2 16.8 10.2 10.2 6.8 14 6.8 6.8 9.5 9.6 9.8 6.1 9.5 10.3 3.5 3.4 3.5 1.8 3.5 3.9 10.2 10.2 10.2 16.8 10.2 10.2 6.8 6.8 6.8 14 6.8 6.8 9.1 10.1 8.6 9.8 9.3 3.2 3.6 2.9 3.5 3.5 10.2 10.2 10.2 10.2 10.2 6.8 6.8 6.8 6.8 6.8 Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) 11.1 10.6 8.1 6.6 6.8 7.8 6.9 8.0 8.0 11.1 6.9 6.7 2.8 2.8 2.8 2.4 2.4 2.8 2.5 2.9 2.9 3.0 2.4 2.4 19 19 13.4 19 19 13.4 19 13.4 13.4 19 19 19 16 16 9 16 16 9 16 9 9 16 16 16 Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) 3 4 3 5 1. Timing is guaranteed by design and characterization and is not tested. 2. All I/O timing (CPU, PCI, and other) is specified into a 50pf load. All timings include errors (if any) induced by internal PLLs, given a clock input with no jitter. Sys (2X): Timings shown are referenced to the rising edge of the output of PLL0, operating at twice the frequency of the SYS_CLK input. PLL0 locks to the rising edge of SYS_CLK. Sys (1X): Timing is referenced to SYS_CLK. PCI (A): PCI interface in asynchronous mode. Timings are referenced to the PCI_CLK input. Logic is clocked by the output of PLL1, which repeats PCI_CLK. PCI (S): PCI interface in synchronous mode. Timings are referenced to the SYS_CLK, which is assumed to be exactly equal to the PCI clock... 3. This is a 5.0V receiver. Other receivers are 3.3V receivers 4. This output mimics an open collector gate and requires a pull-up resistor. 5. The CPC700 never drivesTBST_N low. The CPC700 drivesTBST_N high on snoops. There are internal 13KΩ pull-down resistors connected to pins GBL_N, TSIZ [0:1], TT [0], and TT [4]. There are internal 20KΩ pull-up resistors connected to pins TSIZ [2] and TT [1]. cpc700_ds2.fm 05/04/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CPC700 Memory Controller and PCI Bridge CPU and Memory Interface I/O Specifications for 83.33 MHz Signal I/O CPU Bus Interface1, 2 A[0:31] I/O AACK_N O AP[0:3] I/O ARTRY_N I/O BG_N O BR_N I DBG_N O DH[0:31] I/O DL[0:31] I/O DP[0:7] I/O GBL_N O MCP_N O MCP_REQ I TA_N O TBST_N I/O TS_N I/O TSIZ[0:2] I/O TT[0:4] I/O Input (ns) Setup Time Hold Time (min) (min) 2.5 1.0 2.5 2.5 1.0 1.0 2.5 1.0 3.0 3.0 2.5 1.0 1.0 1.0 2.5 1.0 2.5 2.5 2.5 2.1 1.0 1.0 1.0 1.0 Memory Controller Interface1, 2 BA0 O BA1 O BANK_SEL_N[0:4] O CAS_N O CKE O M_DATA[0:63] I/O 2.5 DQM[0] O ECC[0] I/O 2.5 ECC[1:7]/DQM[1:7] I/O 2.5 MA[0:12] O RAS_N O WE_N O Output (ns) Valid Delay Hold Time (max) (min) 1.0 1.0 1.0 Output Current (mA) I/O H I/O L (max) (min) Clock 6.6 6.5 6.6 6.0 6.0 3.5 3.5 3.4 3.2 3.2 10.2 16.8 10.2 10.2 6.8 14 6.8 6.8 6.7 7.1 7.1 6.1 7.2 7.8 3.5 3.4 3.5 1.8 3.5 3.9 10.2 10.2 10.2 16.8 10.2 10.2 6.8 6.8 6.8 14 6.8 6.8 6.0 7.6 6.0 6.7 7.0 3.2 3.6 2.9 3.5 3.5 10.2 10.2 10.2 10.2 10.2 6.8 6.8 6.8 6.8 6.8 Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) 9.0 8.5 6.0 5.9 5.8 6.0 5.7 6.0 6.0 8.9 5.8 5.7 2.8 2.8 2.8 2.4 2.4 2.8 2.5 2.9 2.9 3.0 2.4 2.4 19 19 13.4 19 19 13.4 19 13.4 13.4 19 19 19 16 16 9 16 16 9 16 9 9 16 16 16 Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Sys (2X) Notes 3 4 3 5 1. Timing is guaranteed by design and characterization and is not tested. 2. All I/O timing (CPU, PCI, and other) is specified into a 50pf load. All timings include errors (if any) induced by internal PLLs, given a clock input with no jitter. Sys (2X): Timings shown are referenced to the rising edge of the output of PLL0, operating at twice the frequency of the SYS_CLK input. PLL0 locks to the rising edge of SYS_CLK. Sys (1X): Timing is referenced to SYS_CLK. PCI (A): PCI interface in asynchronous mode. Timings are referenced to the PCI_CLK input. Logic is clocked by the output of PLL1, which repeats PCI_CLK. PCI (S): PCI interface in synchronous mode. Timings are referenced to the SYS_CLK, which is assumed to be exactly equal to the PCI clock. 3. This is a 5.0V receiver. Other receivers are 3.3V receivers. 4. This output mimics an open collector gate and requires a pull-up resistor. 5. The CPC700 never drivesTBST_N low. The CPC700 drivesTBST_N high on snoops. There are internal 13KΩ pull-down resistors connected to pins GBL_N, TSIZ [0:1], TT [0], and TT [4]. There are internal 20KΩ pull-up resistors connected to pins TSIZ [2] and TT [1]. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 cpc700_ds2.fm 05/04/00 CPC700 Memory Controller and PCI Bridge Clock DC Specifications Signal Name Minimum Vih Maximum Vil Cin SYS_CLK 2.0V 0.8V 5pf PCI_CLK 2.0V 0.8V 5pf CPC700 - 66 Clock AC Specifications Input Jitter Duty Cycle Signal Name Fmin Fmax Short Long Min Max SYS_CLK 10 MHz 33.33MHz ±150ps ±250ps 40% 60% PCI_CLK 25 MHz 66.66MHz ±150ps ±250ps 40% 60% Notes 1. In the clock tables, 25 MHz represents 1/(40ns), 33.33MHz represents 1/(30ns), 41.66MHz represents 1/(24ns), 66.66MHz represents 1/(15ns), and 83.33MHz represents 1/(12ns). 2. For information on CPC700 operation with a spread spectrum clock, please contact your IBM technical representative. CPC700 - 83 Clock AC Specifications Input Jitter Duty Cycle Signal Name Fmin Fmax Short Long Min Max SYS_CLK 10MHz 41.66MHz ±150ps ±250ps 40% 60% PCI_CLK 25MHz 66.66MHz ±150ps ±250ps 40% 60% Notes 1. In the clock tables, 25MHz represents 1/(40ns), 33.33MHz represents 1/(30ns), 41.66MHz represents 1/(24ns), 66.66MHz represents 1/(15ns), and 83.33MHz represents 1/(12ns). 2. For information on CPC700 operation with a spread spectrum clock, please contact your IBM technical representative. cpc700_ds2.fm 05/04/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CPC700 Memory Controller and PCI Bridge 3. Signal Lists Pin Number List Pin Number List (Part 1 of 9) (Part 2 of 9) (Part 3 of 9) Pin Pin Signal Pin Signal AB16 AB17 AB18 AB19 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 DH29 A27 DL25 AP0 A00 A08 A04 VDD DL04 DL07 DH02 VDD DL17 DP1/REQ3_N DH07 VDD RI DH18 DH24 VDD DL29 DL23 DL28 A14 A12 A20 A28 DP3/REQ5_N GND DH03 DL10 DH00 GND DH14 DP2/REQ4_N DP5/GNT3_N GND DH26 DH28 DL31 DL24 DL27 GND A22 A26 A30 DL02 UNUSED DH09 UNUSED DH10 UNUSED DH11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D01 D02 D03 D04 D05 D06 D07 UNUSED DH27 UNUSED DH30 DH31 DL30 DL26 GND UART0_TX ECC6/DQM6 ECC4/DQM4 M_DATA62 M_DATA60 GND M_DATA47 M_DATA42 M_DATA39 GND M_DATA25 M_DATA21 M_DATA23 GND M_DATA00 M_DATA02 BANK_SEL_N3 BANK_SEL_N0 CKE UART0_RX UART1_TX ECC1/DQM1 VDD M_DATA54 M_DATA55 M_DATA45 VDD M_DATA35 VDD M_DATA27 VDD M_DATA13 M_DATA09 M_DATA03 VDD BANK_SEL_N4 CAS_N RAS_N IRQ0 UART1_RX ECC0 ECC2/DQM2 M_DATA58 M_DATA46 M_DATA44 Pin Number List A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 Signal NO BALL ECC7/DQM7 ECC5/DQM5 M_DATA63 M_DATA61 UNUSED M_DATA59 UNUSED M_DATA41 UNUSED M_DATA26 UNUSED M_DATA22 UNUSED M_DATA08 M_DATA01 BANK_SEL_N2 BANK_SEL_N1 GND AD03 GND VDD A02 A16 VDD DL06 GND DL22 VDD DH08 GND DH13 VDD DP7/GNT5_N DH25 AP3 GND A31 AD00 AD01 A06 A10 A24 DL01 DL08 DL18 DL11 DH05 DH06 DH19 DH12 DH17 DH21 ©IBM Corporation. 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Page 12 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 cpc700_ds2.fm 05/04/00 CPC700 Memory Controller and PCI Bridge Pin Number List Pin Number List Pin Number List (Part 4 of 9) (Part 5 of 9) (Part 6 of 9) Pin Signal Pin Signal Pin Signal D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 G01 G02 G03 G04 G05 M_DATA40 M_DATA36 M_DATA31 M_DATA17 M_DATA19 M_DATA12 M_DATA11 M_DATA04 UNUSED MA11 WE_N DQM0 IRQ02 GND IIC0_SCL ECC3/DQM3 M_DATA57 VDD M_DATA43 GND M_DATA34 VDD M_DATA18 GND M_DATA15 VDD M_DATA05 M_DATA06 MA06 GND MA09 UNUSED IIC1_SCL IIC1_SDA IIC0_SDA M_DATA56 UNUSED GND M_DATA32 M_DATA33 M_DATA30 M_DATA24 M_DATA20 M_DATA14 M_DATA10 M_DATA07 MA03 MA05 MA07 UNUSED IRQ05 GND IRQ01 VDD IRQ04 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 K01 K02 K03 GND UNUSED VDD UNUSED GND UNUSED VDD UNUSED GND ROM_RD_N VDD MA04 MA10/AP MA08 PCIPLL_VDDA IRQ06 PCI_CLK VDD IRQ03 UNUSED UNUSED UNUSED M_DATA53 M_DATA38 M_DATA16 UNUSED UNUSED ROM_ALE UNUSED MA02 MA01 MA00 MA12 UNUSED VDD IRQ08 GND IRQ10 VDD UNUSED GND M_DATA52 VDD M_DATA29 GND UNUSED VDD UNUSED GND BA1 VDD UNUSED RST_N IRQ11 TMS K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 N01 REQ0_N/GNT_N GNT1_N IRQ09 UNUSED M_DATA49 M_DATA51 M_DATA37 M_DATA28 ROM_OE_N UNUSED UNUSED ROM_WR_N ROM_RNW TDO BA0 SYS_RESET_N UNUSED DEVSEL_N PAR VDD IRQ07 GND IDSEL VDD M_DATA50 GND GND VDD ROM_READY GND ROM_WE_N VDD RESET_OUT_N PCI_66_STRAP UNUSED AD28 AD20 REQ1_N AD30 AD31 SERR_N GNT0_N/REQ_N PERR_N VDD M_DATA48 VDD DBG_N TA_N AACK_N TEST_ENABLE MCP_N SYS_CLK GND SYSPLL_VDDA AD19 cpc700_ds2.fm 05/04/00 ©IBM Corporation. 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Page 13 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CPC700 Memory Controller and PCI Bridge Pin Number List Pin Number List Pin Number List (Part 7 of 9) (Part 8 of 9) (Part 9 of 9) Pin Signal Pin Signal Pin Signal N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 VDD AD27 GND AD26 VDD FRAME_N GND AD29 GND TSIZ2 GND TSIZ1 VDD BR_N GND GBL_N VDD MCP_REQ C/BE_N0 AD21 TCK IRDY_N AD23 TRDY_N AD24 AD11 VDD AD25 VDD ARTRY_N IRQ_OUT_N TS_N TT3 TSIZ0 TDI VDD TRST_N AD15 AD17 AD18 VDD AD14 GND UNUSED VDD DL03 GND DL12 VDD A23 GND TT0 VDD BG_N TT4 R19 T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 TBST_N AD13 C/BE_N1 AD16 STOP_N AD12 UNUSED UNUSED C/BE_N3 DL14 DL13 DL09 DL19 UNUSED A01 A21 AP1 A07 TT1 TT2 UNUSED VDD AD22 GND UNUSED VDD UNUSED GND UNUSED VDD DL05 GND UNUSED VDD UNUSED GND A03 VDD UNUSED DI1_N AD09 DI2_N AD10 C/BE_N2 UNUSED UNUSED UNUSED DL16 DH04 DL00 DH16 UNUSED UNUSED A09 AP2 V17 V18 V19 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 A11 A13 A05 AD08 AD07 AD06 VDD UNUSED GND UNUSED VDD DP0/REQ2_N GND DH15 VDD UNUSED GND UNUSED VDD A15 A25 A17 UNUSED AD04 AD05 AD02 A18 UNUSED DP6/GNT4_N DH01 DL15 DL20 DL21 DH20 DH23 UNUSED DH22 DP4/GNT2_N A19 A29 UNUSED ©IBM Corporation. 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Page 14 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 cpc700_ds2.fm 05/04/00 CPC700 Memory Controller and PCI Bridge Signal Name List Signal Name List Signal Name List (Part 1 of 9) (Part 2 of 9) (Part 3 of 9) Pin Signal Pin Signal Pin Signal A00 A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 AACK_N AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 U03 P05 P07 P10 N05 N03 M01 N09 M04 M05 AB19 T16 V16 AA17 P12 K18 J17 B18 A18 A17 B17 C17 R17 N15 P01 T02 V05 T08 C18 B19 M12 L02 AD09 Y08 AC07 AD07 V10 AB10 AB11 AC11 AA11 AE07 AE09 AE11 AB13 AA13 AD11 W11 V12 AB14 AC14 AB12 Y12 AB15 Y15 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AP0 AP1 AP2 AP3 ARTRY_N BA0 BA1 BANK_SEL_N0 BANK_SEL_N1 BANK_SEL_N2 BANK_SEL_N3 BANK_SEL_N4 BG_N BR_N C/BE_N0 C/BE_N1 C/BE_N2 C/BE_N3 CAS_N CKE DBG_N DEVSEL_N DH00 DH01 DH02 DH03 DH04 DH05 DH06 DH07 DH08 DH09 DH10 DH11 DH12 DH13 DH14 DH15 DH16 DH17 DH18 DH19 DH20 DH21 DH22 Y13 AC15 AA16 AD15 AE13 AD16 AB16 AE15 AE16 V01 V03 V11 AB06 AE05 R09 AC05 U11 AA07 AC06 AB07 T11 AD08 AB09 R11 T10 T09 Y09 V09 AC09 AB08 T12 Y10 Y11 AA09 AC18 AD18 AB18 AE18 AD19 AC19 AC17 AE17 AD17 W09 AC10 AD12 AD05 Y16 AD13 Y07 AA15 D19 D03 C03 D04 DH23 DH24 DH25 DH26 DH27 DH28 DH29 DH30 DH31 DI1_N DI2_N DL00 DL01 DL02 DL03 DL04 DL05 DL06 DL07 DL08 DL09 DL10 DL11 DL12 DL13 DL14 DL15 DL16 DL17 DL18 DL19 DL20 DL21 DL22 DL23 DL24 DL25 DL26 DL27 DL28 DL29 DL30 DL31 DP0/REQ2_N DP1/REQ3_N DP2/REQ4_N DP3/REQ5_N DP4/GNT4_N DP5/GNT3_N DP6/GNT4_N DP7/GNT5_N DQM0 ECC0 ECC1/DQM1 ECC2/DQM2 AC01 T14 AA04 U17 AC03 V19 AB03 T17 AC02 V15 AB04 V17 AD02 V18 AD01 W17 AA05 W19 Y05 Y17 AD03 T15 AE02 R13 AB05 W18 AE03 AB17 AD04 Y18 AE04 AA19 M14 AB01 AB02 Y04 AA01 Y02 Y03 W03 W02 W01 V02 V04 P08 T05 T01 R05 R01 T03 R02 R03 N01 M02 P02 cpc700_ds2.fm 05/04/00 ©IBM Corporation. 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Page 15 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CPC700 Memory Controller and PCI Bridge Signal Name List Signal Name List Signal Name List (Part 4 of 9) (Part 5 of 9) (Part 6 of 9) Pin Signal Pin Signal Pin Signal E04 B03 A03 B02 A02 N07 N17 A19 AA02 AA08 AA12 AA18 AD06 AD10 AD14 AE01 AE19 B06 B10 B14 E02 E08 E12 E18 F07 G02 G06 G10 G14 J04 J08 J12 J16 L06 L10 L11 L14 M18 N04 N08 N10 N12 N16 R06 R10 R14 U04 U08 U12 U16 W06 W10 W14 M07 K05 ECC3/DQM3 ECC4/DQM4 ECC5/DQM5 ECC6/DQM6 ECC7/DQM7 FRAME_N GBL_N GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNT0_N/REQ_N GNT1_N L07 E03 F04 F02 F03 P04 D01 G03 E01 H05 G05 G01 H02 L05 J03 K06 J05 K02 P13 B15 A16 B16 C15 D15 E15 E16 F15 A15 C14 F14 D14 D13 C13 F13 E13 H11 D11 E11 D12 F12 B12 A13 B13 F11 B11 A11 C11 K11 J11 F10 D10 F08 F09 E09 C09 IDSEL IIC0_SCL IIC0_SDA IIC1_SCL IIC1_SDA IRDY_N IRQ0 IRQ01 IRQ02 IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 IRQ08 IRQ09 IRQ10 IRQ11 IRQ_OUT_N M_DATA00 M_DATA01 M_DATA02 M_DATA03 M_DATA04 M_DATA05 M_DATA06 M_DATA07 M_DATA08 M_DATA09 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15 M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23 M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 D09 K10 H10 B09 D08 A09 B08 E07 D07 C07 D06 B07 M10 K08 L09 K09 J09 H09 C05 C06 F05 E05 D05 A07 B05 A05 B04 A04 H18 H17 H16 F16 G17 F17 E17 F18 G19 E19 G18 D17 H19 M16 N19 L03 L18 H03 H01 M08 C19 K04 M03 L17 AC13 H14 K12 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47 M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55 M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63 MA00 MA01 MA02 MA03 MA04 MA05 MA06 MA07 MA08 MA09 MA10/AP MA11 MA12 MCP_N MCP_REQ PAR PCI_66_STRAP PCI_CLK PCIPLL_VDDA PERR_N RAS_N REQ0_N/GNT_N REQ1_N RESET_OUT_N RI_N ROM_ALE ROM_OE_N ©IBM Corporation. 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Page 16 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 cpc700_ds2.fm 05/04/00 CPC700 Memory Controller and PCI Bridge Signal Name List Signal Name List Signal Name List (Part 7 of 9) (Part 8 of 9) (Part 9 of 9) Pin Signal Pin Signal Pin Signal G15 L13 K16 L15 K15 K01 M06 T04 M17 K19 M19 M13 R19 P03 P17 K17 M15 K03 P06 P19 P14 P16 N13 N11 R15 T18 T19 P15 R18 C01 B01 D02 C02 A06 A08 A10 A12 A14 AE06 AE08 AE10 AE12 AE14 D16 F01 F06 F19 G07 G09 G11 G13 H06 H07 H08 H12 ROM_RD_N ROM_READY ROM_RNW ROM_WE_N ROM_WR_N RST_N SERR_N STOP_N SYS_CLK SYS_RESET_N SYSPLL_VDDA TA_N TBST_N TCK TDI TDO TEST_ENABLE TMS TRDY_N TRST_N TS_N TSIZ0 TSIZ1 TSIZ2 TT0 TT1 TT2 TT3 TT4 UART0_RX UART0_TX UART1_RX UART1_TX UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED H13 H15 J01 J07 J13 J15 J19 K07 K13 K14 L01 L19 R07 T06 T07 T13 U01 U05 U07 U09 U13 U15 U19 V06 V07 V08 V13 V14 W05 W07 W13 W15 Y01 Y06 Y14 Y19 AA03 AA06 AA10 AA14 AC04 AC08 AC12 AC16 C04 C08 C10 C12 C16 E06 E10 E14 G04 G08 G12 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD G16 H04 J02 J06 J10 J14 J18 L04 L08 L12 L16 M09 M11 N02 N06 N14 N18 P09 P11 P18 R04 R08 R12 R16 U02 U06 U10 U14 U18 W04 W08 W12 W16 D18 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD WE_N cpc700_ds2.fm 05/04/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CPC700 Memory Controller and PCI Bridge 4. Package Information 474-Pin CBGA Top View 12.902 11.980 3.15 13.363 Screening Fiducials x 12 (∅ 0.1) 1.5 10.598 0.925 10.598 11.059 0.65 Center line Fiducials x 4 A01 Index Mark 1.843 0.15 C (474x) (∅ 0.89 +0.04 ) −0.07 ∅ 0.3 m c A s B s ∅ 0.1 m C Solder ball x 474 C Chip Placement Fiducials x 2 1.01± 0.1 1.07± 0.1 7.142 13.363 13.594 13.824 3.05 Max 2.5 Min 1.27 Typ 25 ± 0.2 01 19 B A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 0.9 ± 0.1 32.5 ± 0.2 A Bottom View ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 cpc700_ds2.fm 05/04/00 . CPC700 Memory Controller and PCI Bridge 5. Ordering Information Product Name IBM Part Number OEMLS Part Number Processor Bus Frequency Package Rev Level CPC700 45L7531 IBM25CPC700BB3B66 66.66 25x32MM (474) CBGA dd 1.1 CPC700 45L7530 IBM25CPC700BB3B83 83.33 25x32MM (474) CBGA dd 1.1 CPC700 09K4299 IBM25CPC700CB3B66 66.66 25x32MM (474) CBGA dd 1.2 CPC700 09K4298 IBM25CPC700CB3B83 83.33 25x32MM (474) CBGA dd 1.2 This section provides the part numbering nomenclature for the CPC700. For availability, contact your local IBM sales office. IBM Part Number Key IBM25CPC700BB3B66 Marketing Part Number Processor Bus Frequency 66 - 66.66 MHz 83 - 83.33 MHz Revision Revision PCI Rev Reg Code Level A dd 1.0 0000 0000 B dd 1.1 0000 0001 C dd 1.2 0000 0010 cpc700_ds2.fm 05/04/00 Application Conditions B - Full Specification Grade 3 Reliability Package (CBGA) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 CPC700 Memory Controller and PCI Bridge Copyright Trademarks The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM IBM Logo PowerPC AIX CPC700 Other company, product, and service names may be trademarks or service marks of others. IBM reserves the right to change or discontinue this product without notice. © International Business Machines Corporation 2000. Portions hereof ©International Business Machines Corporation, 1991-2000. All rights reserved. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 cpc700_ds2.fm 05/04/00