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VIA TECHNOLOGIES, INC.
Title
Document Number
Date:
Tuesday, August 27, 2002
C
5
4
3
2
USB port& power switch
Size
Rev
0.1
VT5642D
Sheet
1
1
of
2
5
4
3
2
1
VIA TECHNOLOGIES ASSUMES NO RESPONSIBILITY FOR ANY ERRORS IN DRAWING THESE SCHEMATICS.
D
-INTB
CLK
-REQ
AD31
AD29
AD27
AD25
-CBE3
AD23
AD21
AD19
C
AD17
-CBE2
-IRDY
-DEVSEL
-CBE1
AD14
AD12
AD10
AD8
AD7
52
53
54
55
56
57
58
59
60
61
62
AD5
AD3
AD1
B
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
PCI3V3
-INTA
-INTC
VCC3_SB
-RST
-GNT
-PME
AD30
AD28
AD26
AD24
IDSEL
AD22
AD20
AD18
AD16
-FRAME
-TRDY
-STOP
116
117
118
121
122
123
124
125
126
1
2
7
8
11
12
13
14
15
16
29
30
31
32
37
38
39
40
42
45
46
47
48
-CBE0
-CBE1
-CBE2
-CBE3
41
28
19
3
-FRAME
IDSEL
-IRDY
-TRDY
-DEVSEL
-STOP
PAR
-REQ
-GNT
-RST
CLK
-INTA
-INTB
-INTC
PAR
AD15
AD13
AD11
AD9
-CBE0
52
53
54
55
56
57
58
59
60
61
62
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD6
AD4
20
6
21
22
23
24
27
113
112
111
109
105
106
107
64
67
-PME
AD2
AD0
9
127
17
25
33
43
51
61
100
108
119
5
36
54
114
PCI
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C10
CT11
10u
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10u
C11
V_IN
ADJ
V_OUT
C44
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70
4
35
53
115
REXT
88
R9
5.1K 1%
GNDUSB
GNDUSB
GNDUSB
GNDUSB
87
83
79
75
R10
1.02K 1%
EECS
EESK
EEDO/TEST0
EEDI
49
50
55
56
AGND
EECS
EESK
EEDO R70
EEDI
63
60
97
104
103
102
R73
R74
R75
R76
R77
R78
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
65
66
57
58
59
99
R11
R12
R13
R14
R65
R63
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
NC
NC
NC
NC
NC
NC
ATPGEN
TESTMODE
TEST1
TEST2
TEST3
TEST4
-OC0
-OC1
2
2
WAKEUP_EN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
.01u .1u .1u .1u .1u .01u .01u .01u
4.7K
98 R15
4.7K
VCCPLLA
89
GNDPLLA
90
VCCOSC
96
GNDOSC
93
VCCPLL
91
GNDPLL
92
GNDSUS
69
XOUT
VCC2_5
U10
3V3
8
6
7
5
C42
.1u
3V3
VCC DO
NC
DI
NC
SK
GND CS
AVCC3
2
FB12
USB DEVICE WAKE-UP
3V3
1
J2&J3 1-2 : ENABLE
3
2-3 : DISABLE
B
AVCC2_5
AVCC3
C37 C36 C38
C35
.1u .1u .1u
.1u
95
AGND
AGND
2
XTAL1 24M
C13
20p
20p
PCI3V3
AGND
VCC3
J5
1
3
FB23 VCC3
3V3
J5 : 1-2 PCI support 3.3v to chip
2-3 Regulator support 3.3v
2
O
A
R71
CT15
C45
10u
.1u
AVCC3
FB2
C23 C22 C20 C21
FB4
.1u .1u .1u .1u
modify 2002,02,05
VIA TECHNOLOGIES, INC.
G
510
CT14 10u
R72
Title
AGND
820
AGND
modify 2002,02,05
5
.1u .01u .1u .01u
J3
1
3
VT6202/VT6202A
1
C14 C17 C16 C15
IS93LC46
VCC3_SB
2
C
EEDO
EEDI
EESK
EECS
4
3
2
1
3V3
AVCC2_5
XIN
C12
2
2
2
2
2
2
2
2
C25 C26 C34 C32 C28 C31 C29 C33
J2
AGND
U12
AMS1117-ADJ
I
VCCUSB
VCCUSB
VCCUSB
VCCUSB
84
80
76
72
-OC0
-OC1
USB1N
USB1P
USB2N
USB2P
USB3N
USB3P
USB4N
USB4P
3V3
-FRAME
IDSEL
-IRDY
-TRDY
-DEVSEL
-STOP
PAR
-REQ
-GNT
PCIRST
PCICLK
-INTA
-INTB
-INTC
-SMI
-PME
.1u
AGND
A
85
86
81
82
77
78
73
74
71
68
AVCC3
-CBE0
-CBE1
-CBE2
-CBE3
G
CT1
D
USB1N
USB1P
USB2N
USB2P
USB3N
USB3P
USB4N
USB4P
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
-USBOC0
-USBOC1
AGND
94
GND
C9
COPYRIGHT 2001 VIA TECHNOLOGIES INCORPORATED.
AVCC2_5
O
V_OUT
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VSUS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
THESE SCHEMATICS ARE SUBJECT TO CHANGE AT ANY TIME WITHOUT NOTICE.
VCC2_5
VCC25
VCC25
VCC25
VCC25
U1
PCIA1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
VCC33
PCIB1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
AVCC3
10
18
26
34
44
52
62
101
110
120
128
3V3
4
3
2
VT6202 PCI to USB 2.0 Host Controller
Size
C
Document Number
Date:
Tuesday, August 27, 2002
Rev
0.1
VT5642D
Sheet
1
2
of
2