S1R72U01
Data Sheet
Rev. 1.20
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material is
applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any
intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that
anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. This material or portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license
from the Ministry of Economy, Trade and Industry or other approval from another government agency.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
©SEIKO EPSON CORPORATION 2009, All rights reserved.
Table of Contents
1. Overview ....................................................................................................................... 1
2. Features ........................................................................................................................ 2
3. Block Diagram .............................................................................................................. 3
4. Functions ...................................................................................................................... 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
Serial I/F (UART) ....................................................................................................................... 4
USB Host SIE ............................................................................................................................ 4
USB Device SIE......................................................................................................................... 4
Transceiver Macro .................................................................................................................... 4
FIFO ........................................................................................................................................... 4
Bridge Sequencer..................................................................................................................... 4
SIO ............................................................................................................................................. 4
Debug I/F ................................................................................................................................... 5
1.8-V Regulator ......................................................................................................................... 5
3.3-V Regulator ......................................................................................................................... 5
VBUS SW................................................................................................................................... 5
Test Circuit ................................................................................................................................ 5
5. Pin Layout Diagram...................................................................................................... 6
6. Pin Functions................................................................................................................ 7
7. Commands...................................................................................................................11
8. Electrical Characteristics .......................................................................................... 12
8.1 Absolute Maximum Ratings................................................................................................... 12
8.2 Recommended Operating Conditions .................................................................................. 12
8.3 DC Characteristics ................................................................................................................. 13
8.3.1
Current consumption ....................................................................................................... 13
8.3.2
Input characteristics ........................................................................................................ 14
8.3.3
Output characteristics...................................................................................................... 15
8.3.4
Pin capacitance ............................................................................................................... 17
8.3.5
VBUS supply function characteristics .............................................................................. 18
8.3.6
Fail-safe cell .................................................................................................................... 19
8.4 AC Characteristics ................................................................................................................. 20
8.4.1
Power supply input/cutoff timing ...................................................................................... 20
8.4.2
Reset timing .................................................................................................................... 21
8.4.3
Clock timing..................................................................................................................... 21
8.4.4
USB I/F timing ................................................................................................................. 21
8.4.5
Serial I/F (main CPU) timing (SPI not supported by S1R72U01)..................................... 22
8.4.6
Serial I/F (history display) timing ..................................................................................... 22
9. Connection Examples................................................................................................ 23
ii
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
10. External Dimensions Diagrams............................................................................... 24
10.1 QFP12-48 ................................................................................................................................. 24
10.2 QFN7-48................................................................................................................................... 25
11. Product Codes .......................................................................................................... 26
Revision History ............................................................................................................. 27
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
iii
1. Overview
1. Overview
The S1R72U01 is a serial (UART) - USB 2.0 host/device bridge LSI supporting USB 2.0 FS/LS. The main CPU
controls the LSI’s USB functions using simplified commands. No USB driver is required. The USB class
supported is the Human Interface Device class.
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
1
2. Features
2. Features
Ease of use and easy connections (serial connections)
Uses simplified commands to control USB functions
The main CPU controls this LSI’s USB functions using simplified commands. No USB driver needs to
be installed.
The UART (2-wire asynchronous) serial interface permits the easy connection of various CPU types.
Built-in regulator
USB regulator
Core voltage regulator
The S1R72U01 has two regulators: one (input range: 3.3 to 5.0 V) to generate 3.3 V for the USB and
another (input voltage: 3.3 to 5.0 V) to generate the internal core voltage of 1.8 V. This allows the
S1R72U01 to operate from a single power source as long as the supplied voltage is at least 3.3 V.
Built-in VBUS supply function
No external VBUS power SW required
The S1R72U01 features a built-in VBUS supply function for USB host operations, eliminating the need
for the external VBUS power SW previously required by the USB host controller. The S1R72U01
features an interface that controls the external VBUS power SW if the built-in VBUS supply function
cannot supply adequate current. If necessary, connect an external VBUS power SW to ensure sufficient
current capacity for bus-powered devices.
Product (system) development support function
History display
The S1R72U01 uses a serial interface (asynchronous type) to display the history of internal LSI
processing, etc. This function provides useful information during product (system) development.
2
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
3. Block Diagram
3. Block Diagram
ManyHub
VBUS_Cur
TPL
ManyDev
XIRQ_EVENT
XIRQ_STATUS
SIO_READY
SCK
SS
MISO
MOSI
SPIxUART
Serial I/F
HOSTxDEVICE
WAKEUP
INIT_BAUD
Bridge
Sequencer
SIN0
1.8V
Reg.
SIO
FIFO
SOUT0
debug i/f*
VROUT_Enb
DBGDCLK, DBGDT,
DBGST
VRIN
XRESET
3.3V
Reg.
VBUS_5V_IN
VBUS_OUT
VBUS
SW
USB
Device SIE
test
circuit*
USB Host
SIE
Macro
CLKSEL
CLK_Source
CLKIN
CLKOUT
XI
XO
VBUSEN
(Rev. 1.20)
VBUSFLG
DP
DM
VBUS
S1R72U01 Data Sheet
TSTEN
OSC PLL
CLK
Transceiver
Fig. 3.1
ATPGEN
Block diagram
Seiko Epson Corporation
3
4. Functions
4. Functions
4.1 Serial I/F (UART)
The S1R72U01 is connected to the main CPU via UART (2-wire asynchronous system). Set the SPIxUART
mode setting pin to Low.
The interface voltage (CVDD) can be used across a broad range, from 1.8 to 5.0 V.
•
UART connection (asynchronous serial I/F)
Initial baud rate: 300/9600 bps (set by mode setting pin INIT_BAUD)
Baud rate: Settable (max. 3 Mbps)
lsb first
8-bit data
1/2 stop bit
Odd/Even/No parity
4.2 USB Host SIE
The USB host function complies with the USB 2.0 (Universal Serial Bus Specification Revision 2.0) standard. It
supports FS (12 Mbps) and LS (1.5 Mbps) speed modes. The USB functions are controlled by the Bridge
Sequencer block inside the LSI. The USB class supported is the Human Interface Device Class.
4.3 USB Device SIE
The USB device function complies with the USB 2.0 (Universal Serial Bus Specification Revision 2.0) standard.
It supports FS (12 Mbps) and LS (1.5 Mbps) speed modes. The USB function is controlled by the Bridge
Sequencer block inside the LSI. The USB class supported is the Human Interface Device Class.
4.4 Transceiver Macro
This is a USB analog macro block shared by host and device.
4.5 FIFO
This FIFO block serves as a buffer for data between the serial interface and the USB.
4.6 Bridge Sequencer
This controls the USB functions based on commands from the serial interface.
4.7 SIO
This block is used to display the history of the product (system) development support functions and for analog
tests.
4
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
4. Functions
4.8 Debug I/F
This is a debugging pin for the built-in Bridge Sequencer. It is not intended for use by the user and should be
disregarded.
4.9 1.8-V Regulator
This regulator generates 1.8-V internal core voltage. The range of input voltages is from 3.3 to 5.0 V.
4.10 3.3-V Regulator
This regulator generates 3.3 V for the USB. The range of input voltages is from 3.3 to 5.0 V.
4.11 VBUS SW
This is a VBUS output block built into the LSI.
4.12 Test Circuit
This is a circuit for IC tests. It is not intended for use by the user and should be disregarded.
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
5
5. Pin Layout Diagram
5. Pin Layout Diagram
36 35 34 33 32 31 30 29 28 27 26 25
SIO_READY
XIRQ_EVENT
XIRQ_STATUS
MOSI
XRESET
MISO
SS
CVDD
SCK
SPIxUART
HOSTxDEV
WAKEUP
37
ATPGEN
TPL
24
38
INIT_BAUD
ManyDev
23
39
CLKSEL
ManyHub
22
VBUS_Cur
21
VSS
（NC）
20
40
CLKIN
41
CLK_Source
42
CLKOUT
43
VSS
DBGDT
18
44
TSTEN
DBGST
17
45
VROUT_Enb
DBGDCLK
16
46
LVDD
SIN0
15
47
VRIN
SOUT0
14
48
VSS
VBUSEN
13
19
VBUSFLG
XO
XI
VBUS
DP
DM
VSS
UVDD3
VRIN
VSS
VBUS_5V_IN
VBUS_OUT
1 2 3 4 5 6 7 8 9 10 11 12
Fig. 5.1 Package pin layout diagram (common to QFP and QFN)
6
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
6. Pin Functions
6. Pin Functions
GENERAL (CVDD system)
BGA
QFP
-
29
-
39
Name
XRESET
CLKSEL
I/O
RESET
IN
IN
Pin description
-
Reset signal
-
Clock frequency selection
Set the frequency input from the clock source (CLKIN
or XI pin).
1: 24 MHz 0: 12 MHz
-
41
CLK_Source
IN
-
Clock source selection
Set whether the clock source is input from the CLKIN
or XI pin.
1: CLKIN 0: XI
-
40
CLKIN
IN
-
Clock input
12 MHz / 24MHz
If the clock input is from the XI pin, set this pin to Low.
Low
Clock output
Refer to the S1R72U01 Technical Manual for
information on how to change the clock output.
48 MHz / 24 MHz / 12 MHz / 6 MHz / 3 MHz / STOP
-
42
CLKOUT
OUT
OSC (LVDD system)
BGA
QFP
Name
I/O
RESET
Pin description
-
10
XI
IN
-
Internal oscillator circuit input
If the clock input is from the CLKIN pin, set this pin to
Low.
12 MHz / 24 MHz
-
11
XO
OUT
-
Internal oscillator circuit output
If the clock input is from the CLKIN pin, leave this pin
open.
TEST (LVDD, CVDD systems)
BGA
QFP
Name
I/O
RESET
Pin description
-
44
TSTEN
IN(PD)
-
Test pin (*1); not intended for use by user
-
37
ATPGEN
IN(PD)
-
Test pin (*1); not intended for use by user
PD: Pull-down I/Os are used.
*1 This is pulled down inside the LSI. However, we recommend fixing it at Low on the circuit board.
USB (UVDD3 system)
BGA
QFP
Name
I/O
RESET
Pin description
-
9
VBUS
IN
-
VBUS input pin
VBUS input pin when S1R72U01 is used as USB
device. Leave this pin open when using S1R72U01
as a USB host.
-
8
DP
BI
Hi-Z
USB data line
Data+
-
7
DM
BI
Hi-Z
USB data line
Data-
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
7
6. Pin Functions
VBUS (UVDD3 system)
BGA
QFP
Name
I/O
RESET
Pin description
-
12
VBUSFLG
IN(PU)
-
USB power switch fault detection signal
1: Normal, 0: Error
CMOS Schmitt input
Use when external USB power switch is added.
Leave open when not used.
-
13
VBUSEN
OUT
Low
USB power switch control signal
Use when external USB power switch is added.
Leave open when not used.
PU: Pull-up I/Os are used.
Serial I/F (CVDD system): Main CPU
BGA
QFP
-
30
MISO
Tri
High
Serial data output
(Hi-z is output when the SS pin is set to High.)
-
28
MOSI
IN
-
Serial data input
-
31
SS
IN
-
Slave selection
(Can be used to control output from the MISO pin. If
Hi-z output is not required, fix this pin at Low.)
-
33
SCK
IN
-
Serial clock (not used: fix at Low)
Low
Communication ready notification pin
Refer to the S1R72U01 Technical Manual for detailed
instructions on using this pin. Leave open when not
used.
High
Status notification
Refer to the S1R72U01 Technical Manual for detailed
instructions on using this pin. Leave open when not
used.
High
Event read request
Refer to the S1R72U01 Technical Manual for detailed
instructions on using this pin. Leave open when not
used.
-
-
-
25
27
26
Name
SIO_READY
XIRQ_STATUS
XIRQ_EVENT
I/O
RESET
OUT
OUT
OUT
Pin description
Serial I/F (UVDD3 system): History Display
BGA
-
-
8
QFP
15
14
Name
SIN0
SOUT0
I/O
IN
OUT
RESET
Pin description
-
Asynchronous serial data IN
Serial data IN pin for history display. Refer to the
S1R72U01 Development Support Manual for
specifics of history display. Fix at High when not used.
High
Asynchronous serial data OUT
Serial data OUT pin for history display. Refer to the
S1R72U01 Development Support Manual for
specifics of history display. Leave open when not
used.
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
6. Pin Functions
DEBUG I/F (UVDD3 system)
BGA
QFP
Name
I/O
-
RESET
Pin description
16
DBGDCLK
OUT
High
Not used (*1)
18
DBGDT
BI(PU)
-
Not used (*2)
17
DBGST
OUT
Low
Not used (*1)
PU: Pull-up I/Os are used.
*1 Leave open.
*2 This is pulled up in the LSI. However, an external pull-up of about 10 kΩ is recommended.
GPI (CVDD system)
BGA
QFP
-
34
SPIxUART
IN
-
Setting pin (fix at Low)
0: UART mode
-
35
HOSTxDEVICE
IN
-
Setting pin
1: HOST mode, 0: DEVICE mode
Switching modes resets the LSI.
-
36
WAKEUP
IN
-
Wake-up pin
Used to resume from SLEEP state.
Rising edge activates the wake-up trigger.
-
Initial baud rate setting pin
1: 9600bps 0: 300bps
UART baud rate can be set to between 300 bps and 3
Mbps using the serial port setting. Refer to the
S1R72U01 Technical Manual for detailed instructions
on making serial port settings.
-
38
Name
INIT_BAUD
I/O
IN
RESET
Pin description
GPO (CVDD system)
BGA
QFP
-
-
-
-
24
23
22
21
Name
TPL
ManyDev
ManyHub
VBUS_Cur
S1R72U01 Data Sheet
(Rev. 1.20)
I/O
OUT
OUT
OUT
OUT
RESET
Pin description
Low
Unsupported Device
1: Error, 0: Used for USB Compliance Testing. Leave open when
not used.
Low
Too Many Devices
1: Error, 0: Used for USB Compliance Testing. Leave open when
not used.
Low
Too Many Hubs
1: Error, 0: Used for USB Compliance Testing. Leave open when
not used.
Low
VBUS Over Current
1: Error, 0: Used for USB Compliance Testing. Leave open when
not used.
Seiko Epson Corporation
9
6. Pin Functions
Regulator (VRIN system)
BGA
QFP
-
4, 47
-
45
Name
I/O
VRIN
RESET
Power
VROUT_Enb
IN
Pin description
-
Regulator input
Connect Cin = 1.0 μF to each pin.
Make sure to keep this open when not using the
regulator.
-
Enables the regulator
Set this to the same level as VRIN when using the
regulator.
Make sure to set this to Low when not using the
regulator.
VBUS SW (VBUS_5V_IN system)
BGA
QFP
Name
I/O
RESET
Pin description
-
2
VBUS_5V_IN
Power
-
VBUS generation input
Voltage input pin for built-in VBUS supply function.
The power supply (VSWIN in 8.3.5) should be
provided even when this function is not used.
-
1
VBUS_OUT
Power
-
VBUS output
VBUS output pin for built-in VBUS supply function.
Leave open when this function will not be used.
POWER
BGA
-
10
QFP
5
Name
UVDD3
Voltage
Pin description
3.3V
Power supply for USB
When using regulator: Connect Cout = 1.0 μF.
When not using regulator: Apply the voltage indicated
to the left.
-
46
LVDD
1.8V
Internal power supply, test power supply, OSC power
supply
When using regulator: Connect Cout = 1.0 μF.
When not using regulator: Apply the voltage indicated
to the left.
-
32
CVDD
1.8 to 5.0V
Power supply for main CPU I/F
-
3, 6, 20, 43,
48
VSS
0V
GND
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
7. Commands
7. Commands
Communication with the main CPU is implemented via commands. For detailed information on commands, refer
to the S1R72U01 Technical Manual.
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
11
8. Electrical Characteristics
8. Electrical Characteristics
8.1 Absolute Maximum Ratings
Item
Code
Rating
Unit
CVDD
VRIN (*1)
-0.3 to 7.0
V
UVDD3
-0.3 to 4.0
V
LVDD (*2)
-0.3 to 2.5
V
VI (*3)
-0.3 to CVDD+0.5
-0.3 to UVDD3+0.5
-0.3 to LVDD+0.5
V
VBUS_5V_IN
-0.3 to 7.0
V
VO (*3)
-0.3 to CVDD+0.5
-0.3 to UVDD3+0.5
-0.3 to LVDD+0.5
V
VBUS_OUT
VBUS_5V_IN+0.3
V
Output current/pin
Iout
±10
mA
Storage temperature
Tstg
-65 to 150
°C
Power supply voltage
Input voltage
Output voltage
*1 VRIN≥UVDD3, VRIN≥LVDD
*2 CVDD, UVDD3≥LVDD
*3 Power supply voltages
8.2 Recommended Operating Conditions
Item
Min.
Typ.
Max.
Uni
CVDD
1.65
1.80 to 5.00
5.50
V
VRIN
3.00
3.30 to 5.00
5.50
V
UVDD3
3.00
3.30
3.60
V
LVDD
1.65
1.80
1.95
V
Input voltage
VI (*)
-0.3
-
CVDD+0.3
UVDD3+0.3
LVDD+0.3
V
Ambient temperature
Ta
-40
25
85
°C
Power supply voltage
Code
* Power supply voltages for each pin
[Precautions for power ON sequence]
Be careful of the power supply timing when providing an external power supply without using a built-in regulator.
Refer to “8.4.1 Power supply input/cutoff timing” for more information.
12
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
8. Electrical Characteristics
8.3 DC Characteristics
8.3.1
Current consumption
Item
Code
Condition
Min.
Typ.
Max.
Unit
-
5
-
mA
Power supply current (*1)
Power supply current
IDDH0
CVDD = 5.5V
IDDH1
UVDD3 = 3.6V
-
5 *2
-
mA
IDDL
LVDD = 1.95V
-
25 *2
-
mA
IDDR
VRIN = 5.5V
-
30 *3
-
mA
IDDS
Max. condition of each power
supply
Fixed to power supply or GND
-
50
-
μA
Max. condition of each power
supply
-5
-
5
μA
Power supply current
(Static current) (*4)
Power supply current
Input leak
Input leakage current
IL
*1 At recommended operating conditions (Ta = 25°C). Operating current for Seiko Epson evaluation board configuration.
*2 Operating current for Seiko Epson evaluation board configuration with external power supply and no built-in regulator.
*3 Operating current for Seiko Epson evaluation board configuration with built-in regulator.
*4 Static current when Ta = 25°C and when using regulator.
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
13
8. Electrical Characteristics
8.3.2
Input characteristics
Item
Input characteristics
Code
Condition
Min.
Typ.
Max.
Unit
Pin:
LVDD-system pin
“H” level input voltage
VIH1
LVDD = 1.95V
1.27
-
-
V
“L” level input voltage
VIL1
LVDD = 1.65V
-
-
0.57
V
Input characteristics (Schmitt)
Pin:
CVDD- and UVDD3-system pin
VT1+
CVDD = 5.5V
CVDD = 3.6V
CVDD = 1.95V
UVDD3 = 3.6V
-
-
4.00
2.52
1.36
2.52
V
VT1-
CVDD = 4.5V
CVDD = 3.0V
CVDD = 1.65V
UVDD3 = 3.0V
0.80
0.75
0.42
0.75
-
-
V
Hysteresis voltage
ΔV1
CVDD = 4.5V
CVDD = 3.0V
CVDD = 1.65V
UVDD3 = 3.0V
0.30
0.30
0.17
0.30
-
-
V
Schmitt input characteristics
(USB: FS)
Pin:
DP, DM
“H” level trigger voltage
VTU+
UVDD3 = 3.6V
-
-
2.0
V
“L” level trigger voltage
VTU-
UVDD3 = 3.0V
0.8
-
-
V
Pin:
DP, DM pair
VDSU
UVDD3 = 3.0V
Differential input voltage:
0.8 to 2.5 V
0.2
-
-
V
Pin:
VBUSFLG, DBGDT
RPLU
VI = 0V (ＵVDD3 = 3.0V)
52
160
384
kΩ
Pin:
ATPGEN
RPLD
VI = CVDD（CVDD = 4.5V）
VI = CVDD（CVDD = 3.0V）
VI = CVDD（CVDD = 1.65V）
32
52
200
100
160
600
240
384
1440
kΩ
Pin:
TSTEN
RPLDL
VI = LVDD (LVDD = 1.65V)
40
120
288
kΩ
Pin name:
VBUS
RPLDB
VI = 5.0V
100
125
165
kΩ
“H” level trigger voltage
“L” level trigger voltage
Input characteristics
(USB: FS differential input)
Differential input
sensitivity
Input characteristics
Pull-up resistance
Input characteristics
Pull-down resistance
Input characteristics
Pull-down resistance
Input characteristics
Pull-down resistance
14
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
8. Electrical Characteristics
8.3.3
Output characteristics
(VSS=0V)
Item
Output characteristics
Code
Pin:
Condition
VOH1
VOL1
CVDD = 4.5V (IOH = 2.0mA)
CVDD = 3.0V (IOH = 1.4mA)
CVDD = 1.65V (IOH = 0.6mA)
UVDD3 = 3.0V (IOH = 1.4mA)
Pin:
MISO, SOUT0, CLKOUT
VOH2
CVDD = 4.5V (IOH = -4.0mA)
CVDD = 3.0V (IOH = -2.8mA)
CVDD = 1.65V (IOH = -1.2mA)
UVDD3 = 3.0V (IOH = -2.8mA)
VOL2
CVDD = 4.5V (IOH = 4.0mA)
CVDD = 3.0V (IOH = 2.8mA)
CVDD = 1.65V (IOH = 1.2mA)
UVDD3 = 3.0V (IOH = 2.8mA)
Pin:
DP, DM
“H” level output
voltage
VOHUF
“L” level output
voltage
“L” level output
voltage
Output characteristics
“H” level output
voltage
“L” level output
voltage
Output characteristics
(USB: FS)
Output characteristics
OFF-STATE
leakage current
S1R72U01 Data Sheet
(Rev. 1.20)
Typ.
Max.
Unit
SIO_READY, XIRQ_EVENT, XIRQ_STATUS, TPL, ManyDev, ManyHUB,
VBUS_Cur, VBUSEN
CVDD = 4.5V (IOH = -2.0mA)
CVDD = 3.0V (IOH = -1.4mA)
CVDD = 1.65V (IOH = -0.6mA)
UVDD3 = 3.0V (IOH = -1.4mA)
“H” level output
voltage
Min.
CVDD – 0.4
CVDD – 0.4
CVDD – 0.4
UVDD3 –
0.4
-
-
V
-
-
0.4
0.4
0.4
0.4
V
CVDD – 0.4
CVDD – 0.4
CVDD – 0.4
UVDD3 –
0.4
-
-
V
-
-
0.4
0.4
0.4
0.4
V
UVDD3 = 3.0V
2.8
-
-
V
VOLUF
UVDD3 = 3.6V
-
-
0.3
V
Pin:
CVDD-system pin
IOZ
CVDD = 5.5V
VOH = CVDD
VOL = VSS
-5
-
5
μA
Seiko Epson Corporation
15
8. Electrical Characteristics
{ Fmax-Cl
<Output buffer types>
Type1A: SIO_READY, XIRQ_EVENT, XIRQ_STATUS, TPL, ManyDev, ManyHUB, VBUS_Cur, VBUSEN
Type2A: MISO, SOUT0, CLKOUT
Using 5.0 V IO voltage
I/O 出力最大周波数
Maximum
I/O output frequency
I/O 出力最大周波数
Maximum
I/O output frequency
(CVDD=5.0V , 25℃ , Model Typ)
(CVDD=4.5V , 125℃ , Model Slow )
1000
fmax (MHz)
100
Type1A
Type2A
10
fmax (MHz)
1000
1
100
Type1A
Type2A
10
1
0
50
100
150
200
250
0
50
100
150
200
250
Load
capacity
(pF)(pF)
負荷容量
Load
capacity(pF)
(pF)
負荷容量
Using 3.3 V IO voltage
I/O 出力最大周波数
Maximum
I/O output frequency
(CVDD/UVDD3=3.0V , 125℃ , Model Slow )
出 力output
最大周波
数
Maximum
frequency
I/O I/O
(CVDD/UVDD3=3.3V , 25℃ , Model Typ)
1000
100
Type1A
Type2A
10
fmax (MHz)
fmax (MHz)
1000
100
Type1A
Type2A
10
1
0
50
100
150
200
1
250
0
Load
(pF)
負 荷capacity
容 量 (pF)
50
100
150
200
250
(pF)(pF)
負荷容量
Load
capacity
Using 1.8 V IO voltage
Maximum
I/O output frequency
I/O 出力最大周波数
I/O 出力最大周波数
Maximum
I/O output frequency
(CVDD=1.65V , 125℃ , Model Slow )
(CVDD=1.8V , 25℃ , Model Typ)
1000
Type1A
10
Type2A
1
fmax (MHz)
fmax (MHz)
100
100
Type1A
Type2A
10
1
0
50
100
150
200
250
Load
capacity(pF)
(pF)
負荷容量
16
0
50
100
150
200
250
(pF)(pF)
Load
capacity
負荷容量
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
8. Electrical Characteristics
8.3.4
Pin capacitance
Item
Pin capacitance
Input pin capacitance
Pin capacitance
Output pin
capacitance
Pin capacitance
Input/output pin
capacitance
Pin capacitance
Input/output pin
capacitance (USB)
S1R72U01 Data Sheet
(Rev. 1.20)
Code
Condition
Min.
Typ.
Max.
Unit
-
-
8
pF
-
-
8
pF
-
-
8
pF
-
-
15
pF
Pin name:
All input pins
CI
f = 1MHz
Pin name:
All output pins
CO
f = 1MHz
Pin name:
All output pins except DP and DM
CB
f = 1MHz
Pin name:
DP, DM
CBU
f = 1MHz
Seiko Epson Corporation
17
8. Electrical Characteristics
8.3.5
VBUS supply function characteristics
Item
Code
Condition
Min.
Typ.
Max.
Unit
3.0
5.0
5.5
V
Input voltage
VSWIN
On resistance
RSWON
VBUS_5V_IN = 5.0V
VBUS_5V_IN = 3.0V
-
2.4
3.5
4.0
Off leakage current
ISWOFF
VBUS_5V_IN = 5.0V
VBUS_5V_IN = 3.0V
-
10
10
100
100
Overcurrent detection
ISWLMT
VBUS_5V_IN = 5.0V
VBUS_5V_IN = 3.0V
21
26
17
35
Overcurrent response time
TSWOFF
Overcurrent → VBUS Off
300
18
Seiko Epson Corporation
Ω
nA
mA
μs
S1R72U01 Data Sheet
(Rev. 1.20)
8. Electrical Characteristics
8.3.6
Fail-safe cell
The S1R72U01 uses fail-safe cells for certain pins. Fail-safe cells have the following advantages:
• They prevent input leakage currents when a power supply is applied to input pins or input/output pins in the
input state, even if the signal input exceeds the power supply voltage. (Note that a leakage current of
approximately 30 µA will occur for pins with pull-up resistance.)
• No input leakage current occurs when the power supply is cut off, even when an external input signal is
applied.
Note that while signals with a voltage level exceeding the operating voltage can be received, the signal voltage
that can be applied to the fail-safe cell cannot exceed the absolute maximum rating.
<Fail-safe fitted pins>
MISO, MOSI, SCK, SS, SIO_READY, XIRQ_EVENT, XIRQ_STATUS, SPIxUART, HOSTxDEVICE,
WAKEUP, INIT_BAUD, TPL, ManyDev, ManyHUB, VBUS_Cur, SIN0, SOUT0, VBUSFLG, VBUSEN,
CLKOUT, CLKIN, CLK_Source, CLKSEL, DBGDCLK, DBGDT, DBGST, XRESET, ATPGEN
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
19
8. Electrical Characteristics
8.4 AC Characteristics
8.4.1
Power supply input/cutoff timing
A. Power supply input/cutoff timing (for LVDD ⇒ HVDD / HVDD ⇒LVDD: recommended conditions)
→
Timing parameters
Item
Code
Min.
Typ.
Max.
Unit
HVDD power supply input timing
Tlhh
0
-
10
sec
HVDD cutoff timing
Thll
0
-
10
sec
Voltage parameters
Item
Code
LVDD initial voltage
HVDD initial voltage
Voltage conditions
Unit
Input
Cutoff
V_lvdd
LVDD_min
LVDD_min
V
V_hvdd
HVDD_min
HVDD_min
V
Timing diagram
V_lvdd
LVDD
Tlhh
Thll
V_hvdd
HVDD (*)
B. Power supply input/cutoff timing (for HVDD
LVDD / LVDD ⇒HVDD)
Timing parameters
Item
Code
Min.
Typ.
Max.
Unit
LVDD power supply input timing
Tlhh
0
-
1
sec
LVDD cutoff timing
Thll
0
-
1
sec
Voltage parameters
Item
Code
LVDD initial voltage
HVDD initial voltage
Voltage conditions
Unit
Input
Cutoff
V_lvdd
LVDD_min
LVDD_min
V
V_hvdd
0.1
0.1
V
Timing diagram
HVDD (*)
Tlhh
V_hvdd
Thll
V_lvdd
LVDD
* HVDD refers to USB UVDD3 or interface CVDD.
* For LVDD ⇒ HVDD timing, refer to A for input and B for cutoff.
For HVDD ⇒ LVDD timing, refer to B for input and A for cutoff.
20
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
8. Electrical Characteristics
8.4.2
Reset timing
tRESET
XRESET
Code
tRESET
8.4.3
Description
Reset pulse width
min
typ
max
Unit
40
-
-
ns
Min.
Typ.
Max.
Unit
Clock timing
tCYC
tCYCL
tCYCH
XI, CLKIN
Code
Description
tCYC
Clock cycle (CLKSEL = "L")
-
12.000
-
MHz
tCYC
Clock cycle (CLKSEL = "H")
-
24.000
-
MHz
45
50
55
%
tCYCL
tCYCH
Clock duty
* The clock source selected must satisfy the accuracy requirements under USB standards. FS: 2,500 ppm, LS:
15,000 ppm
8.4.4
USB I/F timing
Complies with USB 2.0 (Universal Serial Bus Specification Revision 2.0) standard.
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
21
8. Electrical Characteristics
8.4.5
Serial I/F (main CPU) timing (SPI not supported by S1R72U01)
In UART operation
tBRm
MOSI/MISO
b0
Code
tBRm
8.4.6
b1
b2
Description
Baud rate
b3
b4
b5
b6
b7
Min.
Typ.
Max.
Unit
300
-
3M
bps
Serial I/F (history display) timing
tBRh
SIN0/SOUT0
Code
tBRh
22
b0
Description
Baud rate
b1
b2
b3
b4
b5
b6
b7
Min.
Typ.
Max.
Unit
-
38400
-
bps
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
9. Connection Examples
9. Connection Examples
Refer to the S1R72U01 Evaluation Board Manual.
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
23
10. External Dimensions Diagrams
10. External Dimensions Diagrams
10.1 QFP12-48
24
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
10. External Dimensions Diagrams
10.2 QFN7-48
S1R72U01 Data Sheet
(Rev. 1.20)
Seiko Epson Corporation
25
11. Product Codes
11. Product Codes
26
Product code
Description
S1R72U01F12E300
QFP12-48 package
S1R72U01F07E300
QFN7-48 package
Seiko Epson Corporation
S1R72U01 Data Sheet
(Rev. 1.20)
Revision History
Revision History
Attachment-1
Rev. No.
Rev.1.00
Date
02/25/2008
Page
All pages
Category
New
Rev.1.10
06/06/2009
P10
Amend
P13
Add
P14
Revise
Revise
Delete
Revise
Revise
Revise
Revise
P15
Amend
P18
Revise
Revise
Revise
Rev.1.10
09/07/2009
S1R72U01 Data Sheet
(Rev. 1.20)
P19
Add
P8
Amend
P14
Remove
Contents
Newly established
Processing method amended for when function is not used
Before : Open
After : Provide power supply
Power supply current (static current) conditions
After : Condition *4 added
Delete VTU+ Min characteristics
Revise VTU- Min characteristics and delete Max
characteristics
Before : 0.9 [V] (min)
After : 0.8 [V] (min)
Delete ΔV entry
Revise RPLU Min characteristics and amend conditions
Before : 64 [kΩ] (min)
After : 52 [kΩ] (min)
Revise RPLD Min characteristics and amend conditions
Before : 40/64/240 [kΩ] (min)
After : 32/52/200 [kΩ] (min)
Revise RPLDL Min characteristics and amend conditions
Before : 48 [kΩ] (min)
After : 40 [kΩ] (min)
Revise RPLDB Min/Max characteristics
Before : 105 [kΩ] (min) 155 [kΩ] (max)
Before : 100 [kΩ] (min) 165 [kΩ] (max)
Amend IOZ conditions
Revise RSWON Max characteristics
Before : 3.0/4.5 [Ω] (max)
After : 4.0 [Ω] (max)
Revise ISWOFF Max characteristics
Before : 10 [nA] (max)
After : 100 [nA] (max)
Revise ISWLMT Min/Max characteristics
Before : 21/14 [mA] (min) 30/20 [mA] (max)
After : 21 [mA] (min) 35 [mA] (max)
Add “Fail-safe fitted pins”
After : Add XRESET, ATPGEN
Amend I/O and processing method when function is not used
Before : IN(PU) Leave Open
After : IN
Fix at High
Remove SIN0 Pin from the object of RPLU
Seiko Epson Corporation
27
International Sales Operations
AMERICA
ASIA
EPSON ELECTRONICS AMERICA, INC.
EPSON (CHINA) CO., LTD.
2580 Orchard Parkway,
San Jose, CA 95131, USA
Phone: +1-800-228-3964
7F, Jinbao Bldg., No.89 Jinbao St.,
Dongcheng District,
Beijing 100005, CHINA
Phone: +86-10-6410-6655
FAX: +86-10-6410-7320
FAX: +1-408-922-0238
SHANGHAI BRANCH
EUROPE
EPSON EUROPE ELECTRONICS GmbH
Riesstrasse 15, 80992 Munich,
GERMANY
Phone: +49-89-14005-0
FAX: +49-89-14005-110
7F, Block B, Hi-Tech Bldg., 900 Yishan Road,
Shanghai 200233, CHINA
Phone: +86-21-5423-5522
FAX: +86-21-5423-5512
SHENZHEN BRANCH
12F, Dawning Mansion, Keji South 12th Road,
Hi-Tech Park, Shenzhen 518057, CHINA
Phone: +86-755-2699-3828
FAX: +86-755-2699-3838
EPSON HONG KONG LTD.
20/F, Harbour Centre, 25 Harbour Road,
Wanchai, Hong Kong
Phone: +852-2585-4600
FAX: +852-2827-4346
Telex: 65542 EPSCO HX
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
14F, No. 7, Song Ren Road,
Taipei 110, TAIWAN
Phone: +886-2-8786-6688
FAX: +886-2-8786-6660
EPSON SINGAPORE PTE., LTD.
1 HarbourFront Place,
#03-02 HarbourFront Tower One, Singapore 098633
Phone: +65-6586-5500
FAX: +65-6271-3182
SEIKO EPSON CORP.
KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong,
Youngdeungpo-Ku, Seoul 150-763, KOREA
Phone: +82-2-784-6027
FAX: +82-2-767-3677
SEIKO EPSON CORP.
SEMICONDUCTOR OPERATIONS DIVISION
IC Sales Dept.
IC International Sales Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-42-587-5814
FAX: +81-42-587-5117
Document Code: 411544505
First Issue September 2008
D
Revised September 2009 in JAPAN ○