W181 Peak Reducing EMI Solution Features Table 1. Modulation Width Selection • Cypress PREMIS™ family offering • Generates an EMI optimized clocking signal at the output • Selectable input to output frequency • Single 1.25% or 3.75% down or center spread output • Integrated loop filter components • Operates with a 3.3V or 5V supply • Low power CMOS design • Available in 8-pin SOIC (Small Outline Integrated Circuit) or 14-pin TSSOP (Thin Shrink Small Outline Package select options only) Key Specifications W181-01, 02, 03 Output SS% W181-51, 52, 53 Output 0 Fin ≥ Fout ≥ Fin – 1.25% Fin + 0.625% ≥ Fin≥ – 0.625% 1 Fin ≥ Fout ≥ Fin – 3.75% Fin + 1.875% ≥ Fin≥ –1.875% Table 2. Frequency Range Selection W181 Option# FS2 FS1 -01, 51 (MHz) -02, 52 (MHz) -03, 53 (MHz) N/A Supply Voltages: ...........................................VDD = 3.3V±5% or VDD = 5V±10% 0 0 28 ≤ FIN ≤ 38 28 ≤ FIN ≤ 38 0 1 38 ≤ FIN ≤ 48 38 ≤ FIN ≤ 48 N/A Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz 1 0 46 ≤ FIN ≤ 60 N/A 46 ≤ FIN ≤ 60 1 1 58 ≤ FIN ≤ 75 N/A 58 ≤ FIN ≤ 75 Crystal Reference Range.................. 28 MHz ≤ Fin ≤ 40 MHz Cycle to Cycle Jitter: ....................................... 300 ps (max.) Selectable Spread Percentage: ....................1.25% or 3.75% Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time: .................................. 5 ns (max.) Simplified Block Diagram Pin Configurations 3.3 or 5.0V SOIC X2 W181 Spread Spectrum Output (EMI suppressed) 3.3 or 5.0V CLKIN or X1 1 NC or X2 2 GND 3 SS% 4 8 7 6 5 FS2 FS1 VDD CLKOUT W181-02/03 W181-52/53 40 MHz Max. 1 2 3 4 W181-01/51 X1 XTAL Input CLKIN or X1 NC or X2 GND SS% 8 SSON# 7 FS1 6 VDD 5 CLKOUT 14 NC NC FS1 NC VDD NC CLKOUT TSSOP Oscillator or Reference Input W181 NC or X2 GND NC SS% NC Spread Spectrum Output (EMI suppressed) 1 2 3 4 5 6 7 W181-01 FS2 CLKIN or X1 13 12 11 10 9 8 PREMIS is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation Document #: 38-07152 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 25, 2001 W181 Pin Definitions Pin No. (SOIC) Pin No. (TSSOP)(-01) Pin Type CLKOUT 5 8 O Output Modulated Frequency: Frequency modulated copy of the unmodulated input clock (SSON# asserted). CLKIN or X1 1 2 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. NC or X2 2 3 I Crystal Connection: If using an external reference, this pin must be left unconnected. SSON# 8(02/03/52/ 53) -- I Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. FS1:2 7, 8 (01/51) 12, 1 I Frequency Selection Bit(s) 1 and 2: These pins select the frequency range of operation. Refer to Table 2. These pins have internal pull-up resistors. SS% 4 6 I Modulation Width Selection: When Spread Spectrum feature is turned on, this pin is used to select the amount of variation and peak EMI reduction that is desired on the output signal. This pin has an internal pull-up resistor. VDD 6 10 P Power Connection: Connected to 3.3V or 5V power supply. GND 3 4 G Ground Connection: Connect all ground pins to the common system ground plane. 5, 7, 9, 11, 13, 14 NC Pin Name NC Document #: 38-07152 Rev. ** Pin Description No Connection. Page 2 of 10 W181 Overview The W181 products are one series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a lowfrequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram on page 1 shows a simple implementation. Functional Description The W181 uses a Phase-Locked Loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. (Note: For the W181 the output frequency is equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (FS1:2 pins), the frequency range can be set. Spreading percentage is set to be 1.25% or 3.75% (see Table 1). A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between 0.5% and 2.5% are most common. VDD Clock Input Reference Input Freq. Divider Q Phase Detector Charge Pump Σ VCO Post Dividers CLKOUT (EMI suppressed) Modulating Waveform Feedback Divider P PLL GND Figure 1. Functional Block Diagram Document #: 38-07152 Rev. ** Page 3 of 10 W181 Spread Spectrum Frequency Timing Generation Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 3. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. Figure 3 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 2. As shown in Figure 2, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) EMI Reduction Typical Clock Amplitude (dB) Amplitude (dB) SSFTG Spread Spectrum Enabled NonSpread Spectrum Frequency Span (MHz) Down Spread Frequency Span (MHz) Center Spread Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX. MIN. Figure 3. Typical Modulation Profile Document #: 38-07152 Rev. ** Page 4 of 10 W181 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5% Parameter Description IDD Supply Current tON Power-Up Time Test Condition Min. Typ. Max. Unit 18 32 mA 5 ms First locked clock cycle after Power Good VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 1 –100 µA IIH Input High Current Note 1 10 µA IOL Output Low Current @ 0.4V, VDD = 3.3V 15 mA IOH Output High Current @ 2.4V, VDD = 3.3V 15 mA 0.8 2.4 V V 0.4 2.4 V V CI Input Capacitance All pins except CLKIN CI Input Capacitance CLKIN pin only RP Input Pull-Up Resistor 500 kΩ ZOUT Clock Output Impedance 25 Ω 6 7 pF 10 pF Note: 1. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor. Document #: 38-07152 Rev. ** Page 5 of 10 W181 DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10% Parameter Description Test Condition Min. Typ. Max. Unit 30 50 mA 5 ms 0.15VDD V IDD Supply Current tON Power-Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 1 –100 µA IIH Input High Current Note 1 10 µA IOL Output Low Current @ 0.4V, VDD = 5V 24 mA IOH Output High Current @ 2.4V, VDD = 5V 24 mA CI Input Capacitance All pins except CLKIN CI Input Capacitance CLKIN pin only RP Input Pull-Up Resistor 500 kΩ ZOUT Clock Output Impedance 25 Ω First locked clock cycle after Power Good 0.7VDD V 0.4 2.4 V V 6 7 pF 10 pF AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10% Parameter Description Test Condition Min. Typ. Max. Unit fIN Input Frequency Input Clock 28 75 MHz fOUT Output Frequency Spread Off 28 75 MHz tR Output Rise Time VDD, 15-pF load 0.8V–2.4V 2 5 ns tF Output Fall Time VDD, 15-pF load 2.4V–0.8V 2 5 ns tOD Output Duty Cycle 15-pF load 40 60 % tID Input Duty Cycle 40 60 % tJCYC Jitter, Cycle-to-Cycle 300 ps Harmonic Reduction Document #: 38-07152 Rev. ** 250 fout = 40 MHz, third harmonic measured, reference board, 15-pF load 8 dB Page 6 of 10 W181 Application Information creased trace inductance will negate its decoupling capability. The 10-µF decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. Recommended Circuit Configuration For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. Recommended Board Layout VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-µF decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the in1 NC 2 GND 3 8 W181 Reference Input Figure 5 shows a recommended 2-layer board layout. 4 7 6 5 Clock Output R1 C1 0.1 µF 3.3 or 5V System Supply FB C2 10 µF Tantalum Figure 4. Recommended Circuit Configuration C1 = High frequency supply decoupling capacitor (0.1-µF recommended). C2 = Common supply low frequency decoupling capacitor (10-µF tantalum recommended). R1 = Match value to line impedance FB G = = Ferrite Bead Via To GND Plane Reference Input NC C1 G G Clock Output R1 G Power Supply Input (3.3 or 5V) C2 FB Figure 5. Recommended Board Layout (2-Layer Board) Ordering Information Freq. Mask Code Package Name Package Type W181 01, 02, 03 51, 52, 53 G 8-pin Plastic SOIC (150-mil) W181 01 X 14-pin Plastic TSSOP Ordering Code Document #: 38-07152 Rev. ** Page 7 of 10 W181 Package Diagram 14-pin Thin Shrink Small Outline Package Document #: 38-07152 Rev. ** Page 8 of 10 W181 Package Diagram (continued) 8-Pin Small Outline Integrated Circuit (SOIC, 150 mils) Document #: 38-07152 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W181 Document Title: W181 Peak Reducing EMI Solution Document Number: 38-07152 REV. ECN NO. Issue Date Orig. of Change ** 110262 12/15/01 SZV Document #: 38-07152 Rev. ** Description of Change Change from Spec number: 38-00790 to 38-07152 Page 10 of 10