W42C31-09 Spread Spectrum Frequency Timing Generator Features to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. • Maximized EMI suppression using Cypress’s Spread Spectrum technology • Generates a spread spectrum copy of the provided input • Integrated loop filter components • Operates with a 3.3V or 5V supply • Low-power CMOS design • Available in 8-pin SOIC (Small Outline Integrated Circuit) In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. Table 1. Frequency Spread Selection W42C31-09 FS1 Overview The W42C31-09 incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, EMI is greatly reduced. Use of this technology allows systems FS0 Input Frequency (MHz) 0 0 30 to 55 fIN ±0.625% 0 1 30 to 55 fIN ±1.25% 1 0 30 to 55 fIN ±2.5% 1 1 30 to 55 fIN –3.75% Simplified Block Diagram Pin Configuration VDD SOIC CLKIN NC GND FS1 W42C31-09 Cypress Semiconductor Corporation 1 2 3 4 W42C31-09 Oscillator or Reference Input Output Frequency (MHz) 8 7 6 5 SSON# CLKOUT FS0 VDD Spread Spectrum Output (EMI suppressed) • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 January 25, 2000, rev. *B W42C31-09 Pin Definitions Pin No. Pin Type CLKOUT 7 O Output Modulated Frequency: Frequency modulated copy of the unmodulated input clock. CLKIN 1 I External Reference Frequency Input NC 2 I No Connect: This pin must be left unconnected. SSON# 8 I Spread Spectrum Control (Active LOW): Pulling this input signal LOW turns the internal modulation waveform on. This pin has an internal pull-down resistor. FS0:1 6, 4 I Frequency Selection Bit 0: These pins select the frequency spreading characteristics. Refer to Table 1. These pins have internal pull-up resistors. VDD 5 P Power Connection: Connected to 3.3V or 5V power supply. GND 3 G Ground Connection: This should be connected to the common ground plane. Pin Name Pin Description Frequency Selection With SSFTG Functional Description In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed, the modulation percentage may be varied. The W42C31-09 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. (Note: For the W42C31-09 the output frequency is equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Using frequency select bits (FS1:0 pins), various spreading percentages can be chosen (see Table 1). A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between ±0.5% and ±2.5% are most common. The W42C31 features the ability to select from various spread spectrum characteristics. Selections specific to the W42C31-09 are shown in Table 1. Other spreading characteristics are available (see separate data sheets) or can be created with a custom mask. Also, other devices in the W42C31 family offer frequency multiplication in addition to the spread spectrum function. This will allow the use of less expensive fundamental mode crystals. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. VDD Clock Input Reference Input Freq. Divider Q Phase Detector Σ Charge Pump VCO Post Dividers Modulating Waveform Feedback Divider P PLL GND Figure 1. System Block Diagram (Concept, not actual implementation) 2 CLKOUT (EMI suppressed) W42C31-09 Cypress frequency selection tables express the modulation percentage in two ways. The first method displays the spreading frequency band as a percent of the programmed average output frequency, symmetric about the programmed average frequency. This method is always shown using the expression fCenter ± XMOD% in the frequency spread selection table. Spread Spectrum Frequency Timing Generation The benefits of using Spread Spectrum Frequency Timing Generation are depicted in Figure 2. An EMI emission profile of a clock harmonic is shown. The second approach is to specify the maximum operating frequency and the spreading band as a percentage of this frequency. The output signal is swept from the lower edge of the band to the maximum frequency. The expression for this approach is fMAX – XMOD%. Whenever this expression is used, Cypress has taken care to ensure that fMAX will never be exceeded. This is important in applications where the clock drives components with tight maximum clock speed specifications. Contrast the typical clock EMI with the Cypress Spread Spectrum Frequency Timing Generation EMI. Notice the spike in the typical clock. This spike can make systems fail quasi-peak EMI testing. The FCC and other regulatory agencies test for peak emissions. With spread spectrum enabled, the peak energy is much lower (at least 8 dB) because the energy is spread out across a wider bandwidth. Modulating Waveform The shape of the modulating waveform is critical to EMI reduction. The modulation scheme used to accomplish the maximum reduction in EMI is shown in Figure 3. The period of the modulation is shown as a percentage of the period length along the X axis. The amount that the frequency is varied is shown along the Y axis, also shown as a percentage of the total frequency spread. SSON# Pin An internal pull-down resistor defaults the chip into a spread spectrum mode. The SSON# pin enables the spreading feature when set LOW. The SSON# pin disables the spreading feature when set HIGH (VDD). 5 dB /div EMI Reduction Typ ical C lo ck Amplitude (dB ) S S FT G Spread Spectrum Enabled -S S % F req uen cy S p an (M Hz ) NonSpread Spectrum +SS% Time Figure 3. Modulation Waveform Profile 3 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 100% 80% 60% 40% 20% 0% –20% –40% –60% –80% –100% 10% Frequency Shift Figure 2. Typical Clock and SSFTG Comparison W42C31-09 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±10% Parameter Description IDD Supply Current tON Power Up Time VIL (Logic Inputs) Input Low Voltage VIL (CLKIN) Input Low Voltage VIH (Logic Inputs) Input High Voltage VIH (CLKIN) Input High Voltage VOL Output Low Voltage Test Condition Min Typ Max Unit 18 32 mA 5 ms 0.8 V .4 V First locked clock cycle after Power Good 2.4 V 2.8 V [1] IOL = 21.6 mA [1] 0.4 V VOH Output High Voltage IOH = 31.5 mA IIL Input Low Current Note 2 –100 µA IIH Input High Current Note 2 10 µA IOL Output Low Current @ 0.4V, VDD = 3.3V 15 IOH Output High Current @ 2.4V, VDD = 3.3V 15 CI Input Capacitance All pins except CLKIN CI Input Capacitance CLKIN pin only RP Input Pull-Up Resistor 500 kΩ ZOUT Clock Output Impedance 25 Ω Notes: 1. Output driver is full CMOS. 2. Inputs FS1:0 have a pull-up resistor, Input SSON# has a pull-down resistor. 4 2.5 V 6 mA mA 7 pF 10 pF W42C31-09 DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10% Parameter Description Test Condition Min Typ Max Unit 30 45 mA 5 ms IDD Supply Current tON Power Up Time VIL (Logic Inputs) Input Low Voltage 0.15VDD V VIL (CLKIN) Input Low Voltage 0.4 V VIH (Logic Inputs) Input High Voltage 0.7VDD V VIH (CLKIN) Input High Voltage 4.2 V VOL Output Low Voltage IOL = 25.7mA VOH Output High Voltage IOH = 118.mA IIL Input Low Current Note 2 –100 µA IIH Input High Current Note 2 10 µA First locked clock cycle after Power Good 0.4 2.5 V V IOL Output Low Current @ 0.4V, VDD = 5V 24 mA IOH Output High Current @ 2.4V, VDD = 5V 24 mA CI Input Capacitance All pins except CLKIN CI Input Capacitance CLKIN pin only RP Input Pull-Up Resistor 500 kΩ ZOUT Clock Output Impedance 25 Ω 6 7 pF 10 pF AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±10% Symbol Parameter Test Condition Min Typ Max Unit fIN Input Frequency Input Clock 30 40 55 MHz fOUT Output Frequency Spread Off 30 40 55 MHz tR Output Rise Time V, 15-pF load 0.8 – 2.4 2 5 ns tF Output Fall Time V, 15-pF load 2.4 – 0.8 2 5 ns tOD Output Duty Cycle 15-pF load 40 60 % tID Input Duty Cycle 40 60 % tJCYC Jitter, Cycle-to-Cycle 300 ps Harmonic Reduction 250 fout = 40 MHz, third harmonic measured, reference board, 15-pF load 8 dB AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 5V±10% Symbol Parameter Test Condition Min Typ Max Unit fIN Input Frequency Input Clock 30 40 55 MHz fOUT Output Frequency Spread Off 30 40 55 MHz tR Output Rise Time V, 15-pF load 0.8 – 2.4 2 5 ns tF Output Fall Time V, 15-pF load 2.4 – 0.8 2 5 ns tOD Output Duty Cycle 15-pF load 40 60 % tID Input Duty Cycle 40 60 % tJCYC Jitter, Cycle-to-Cycle Harmonic Reduction 250 fout = 40 MHz, third harmonic measured, reference board, 15-pF load 5 8 300 ps dB W42C31-09 creased trace inductance will negate its decoupling capability. The 10-µF decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. Application Information Recommended Circuit Configuration For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. Recommended Board Layout VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-µF decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the in1 NC 2 GND 3 4 W42C31-09 Reference Input Figure 5 shows a recommended 2-layer board layout. 8 Clock Output 7 6 R1 VDD 5 C1 0.1 µF 5V or 3.3V System Supply FB C2 10 µF Tantalum Figure 4. Recommended Circuit Configuration C1 = High frequency supply decoupling capacitor (0.1-µF recommended). C2 = Common supply low frequency decoupling capacitor (10-µF tantalum recommended). R1 = Match value to line impedance FB = G = Ferrite Bead Via To GND Plane Reference Input R1 NC Clock Output G C1 G C2 G Power Supply Input (3.3V or 5V) FB Figure 5. Recommended Board Layout (2-Layer Board) Ordering Information Ordering Code W42C31 Freq. Mask Code Package Name Package Type 09 G 8-pin Plastic SOIC (150-mil) Document #: 38-00799-B 6 W42C31-09 Package Diagram 8-Pin Small Outline Integrated Circuit (SOIC, 150-mil) © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.