W530-02 Frequency-multiplying, Peak-reducing EMI Solution Features Table 1. Output Frequency Range Selection • Cypress PREMIS™ SMARTSPREAD™ family offering • Generates an electromagnetic-interference (EMI)-optimized clocking signal at the output • Selectable frequency range and multiplication factor • Single 1.25%, 2.5%, 5%, or 10%, down or center spread output • Integrated loop filter components • Operates with a 3.3V or 5V supply • Low-power CMOS design • Higher drive strength, higher frequency support than W530 • Available in 20-pin SSOP Key Specifications Supply Voltages:....................................... VDD = 3.3V ± 0.3V or VDD = 5V ± 10% Frequency Range:......................... 13 MHz ≤ Fout ≤ 166 MHz Cycle to Cycle Jitter: ........................................250 ps (max.) Output Duty Cycle: ............................... 40/60% (worst case) OR 2 OR 1 Output Range (Multiplication Factor Selection) 0 0 reserved 0 1 13 MHz ≤ FOUT ≤ 30 MHz 1 0 25 MHz ≤ FOUT ≤ 60 MHz 1 1 50 MHz ≤ FOUT ≤ 166 MHz Table 2. Modulation Width Selection MW2 MW1 MW0 Output 0 0 0 Fin ≥ Fout ≥ Fin –1.25% 0 0 1 Favg + 0.625% ≥ Fout ≥ Favg – 0.625% 0 1 0 Fin ≥ Fout ≥ Fin – 2.5% 0 1 1 Favg + 1.25% ≥ Fout ≥ Favg – 1.25% 1 0 0 Fin ≥ Fout ≥ Fin – 5% 1 0 1 Favg + 2.5% ≥ Fout ≥ Favg – 2.5% 1 1 0 Fin ≥ Fout ≥ Fin – 10% 1 1 1 Favg + 5% ≥ Fout ≥ Favg – 5% Table 3. Input Frequency Range Selection Cypress Semiconductor Corporation Document #: 38-07190 Rev. *A • IR2 IR1 Input Range 0 0 reserved 0 1 13 MHz ≤ FIN ≤ 30 MHz 1 0 25 MHz ≤ FIN ≤ 60 MHz 1 1 50 MHz ≤ FIN ≤ 166 MHz 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 7, 2003 W530-02 Pin Configuration[1] Simplified Block Diagram 3.3V or 5.0V SSOP X1 XTAL Input X2 W530-02 3.3V or 5.0V Oscillator or Reference Input X1 W530-02 REFOUT VDD GND IR1* IR2* 15 SSOUT 8 14 13 MW1* GND 9 12 VDD 10 11 MW2^ 1 2 3 4 5 OR1^ NC GND 6 OR2* SSON# 7 W530-02 Spread Spectrum Output (EMI suppressed) 20 19 18 17 16 X1 X2 AVDD MW0^ STOP^ Spread Spectrum Output (EMI suppressed) Pin Definitions Pin Name Pin No. Pin Type Pin Description SSOUT 15 O Output Modulated Frequency. Frequency modulated signal. Frequency of the output is selected as shown in Table 1. REFOUT 20 O Non-modulated Output. This pin provides a copy of the reference frequency. This output will not have the Spread Spectrum feature regardless of the state of logic input SSON#. CLKIN or X1 1 I Crystal Connection or External Reference Frequency Input. This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. NC or X2 2 I Crystal Connection: Input connection for an external crystal. If using an external reference signal, this pin must be left unconnected. SSON# 10 I Spread Spectrum Control (Active LOW). Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. MW0:2 4, 14, 11 I Modulation Width Selection. When the Spread Spectrum feature is turned on, these pins are used to select the amount of variation and peak EMI reduction that is desired on the output signal (see Table 2). MW0: DOWN, MW1: UP, MW2: DOWN. 17,16 I Reference Frequency Selector. The logic level provided at this input indicates to the internal logic what range the reference frequency is in and determines the factor by which the device multiplies the input frequency. Refer to Table 3. These pins have internal pull-up resistors. NC 7 NC STOP 5 I Output Disable. When pulled HIGH, stops all outputs at logic low voltage level. This pin has an internal pull-down. OR1:2 6,9 I Output Frequency Selection Bits. These pins select the frequency of operation for the output. Refer to Table 1. OR1: DOWN, OR2: UP. IR1:2 No Connection. Leave this pin unconnected. VDD 3, 12, 19 P Power Connection. Connected to 3.3V or 5V power supply. GND 8, 13, 18 G Ground Connection. Connect all ground pins to the common ground plane. Overview The W530-02 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in phase-locked loop (PLL) spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram on page 1 shows a simple implementation. Note: 1. Pins that are marked with [*] have internal pull-up resistors. Pins that are marked with [^] have internal pull-down resistors. Document #: 38-07190 Rev. *A Page 2 of 8 W530-02 The W530-02 also allows for frequency multiplication in order to determine the relationship between the input and output frequencies. Simply compare the min. frequency of the input and output ranges selected (use 12.5 instead of 13 for this calculation, though). The multiplication options are: 0.25, 0.5,1.0, 2.0, and 4.0. causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG Functional Description The W530-02 uses a PLL to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (IR1:2, OR1:2 pins), the frequency range can be set (see Table 1 and Table 3). Spreading percentage is set with pins MW0:2, as shown in Table 2. A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between 0.5% and 2.5% are most common. VDD Clock Input Reference Input Freq. Divider Q Phase Detector Charge Pump Σ VCO Post Dividers CLKOUT (EMI suppressed) Modulating Waveform Feedback Divider P PLL GND Figure 1. Conceptual Block Diagram Spread Spectrum Frequency Timing Generation The benefits of using Spread Spectrum Frequency Timing Generation are depicted in Figure 2. An EMI emission profile of a clock harmonic is shown. Contrast the typical clock EMI with the Cypress Spread Spectrum Frequency Timing Generation EMI. Notice the spike in the typical clock. This spike can make systems fail quasi-peak EMI testing. The FCC and other regulatory agencies test for peak emissions. With spread spectrum enabled, the peak energy is much lower (at least 8 dB) because the energy is spread out across a wider bandwidth. Modulating Waveform The shape of the modulating waveform is critical to EMI reduction. The modulation scheme used to accomplish the maximum reduction in EMI is shown in Figure 3. The period of the modulation is shown as a percentage of the period length along the X axis. The amount that the frequency is varied is Document #: 38-07190 Rev. *A shown along the Y axis, also shown as a percentage of the total frequency spread. Cypress frequency selection tables express the modulation percentage in two ways. The first method displays the spreading frequency band as a percent of the programmed average output frequency, symmetric about the programmed average frequency. This method is always shown using the expression fCenter ± XMOD% in the frequency spread selection table. The second approach is to specify the maximum operating frequency and the spreading band as a percentage of this frequency. The output signal is swept from the lower edge of the band to the maximum frequency. The expression for this approach is fMAX – XMOD%. Whenever this expression is used, Cypress has taken care to ensure that fMAX will never be exceeded. This is important in applications where the clock drives components with tight maximum clock speed specifications. Page 3 of 8 W530-02 SSON# Pin An internal pull-down resistor defaults the chip into spread spectrum mode. When the SSON# pin is asserted (active LOW) the spreading feature is enabled. Spreading feature is disabled when SSON# is set HIGH (VDD). Frequency Span (MHz) Center Spread 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 100% 80% 60% 40% 20% 0% –20% –40% –60% –80% –100% 10% Frequency Shift Figure 2. Typical Clock and SSFTG Comparison Time Figure 3. Modulation Waveform Profile Document #: 38-07190 Rev. *A Page 4 of 8 W530-02 Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condiParameter Description tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating Unit VDD, VIN Voltage on any Pin with Respect to GND –0.5 to +7.0 V –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±0.3V Parameter Description IDD Supply Current tON Power-Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage Test Condition Min. Typ. Max. Unit 18 32 mA 5 ms 0.8 V 0.4 V –100 µA First locked clock cycle after Power Good 2.4 V VOH Output High Voltage IIL Input Low Current Note 2 2.4 V IIH Input High Current Note 2 IOL Output Low Current @ 0.4V, VDD = 3.3V 15 IOH Output High Current @ 2.4V, VDD = 3.3V 15 CI Input Capacitance RP Input Pull-Up Resistor 80 kΩ ZOUT Clock Output Impedance 25 Ω µA 10 mA mA 7 pF DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10% Parameter Description IDD Supply Current tON Power-Up Time VIL Input Low Voltage VIH Input High Voltage Test Condition Min. Typ. Max. Unit 30 50 mA 5 ms 0.15VDD V First locked clock cycle after Power Good 0.7VDD V VOL Output Low Voltage VOH Output High Voltage 0.4 IIL Input Low Current Note 2 –100 µA IIH Input High Current Note 2 10 µA IOL Output Low Current @ 0.4V, VDD = 5V 24 mA IOH Output High Current @ 2.4V, VDD = 5V 24 mA 2.4 V V CI Input Capacitance RP Input Pull-Up Resistor 80 7 kΩ pF ZOUT Clock Output Impedance 25 Ω Note: 2. Inputs OR1:2 and IR1:2 have a pull-up resistor, Input SSON# has a pull-down resistor. Document #: 38-07190 Rev. *A Page 5 of 8 W530-02 AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±0.3V Parameter Description Test Condition Min. Typ. Max. Unit fIN Input Frequency Input Clock 14 166 MHz fOUT Output Frequency Spread Off 13 166 MHz tR Output Rise Time VDD, 15-pF load, 0.8V–2.4V 2 5 ns tF Output Fall Time VDD, 15-pF load, 2.4V–0.8V 2 5 ns 15-pF load tOD Output Duty Cycle tID Input Duty Cycle tJCYC Jitter, Cycle-to-Cycle 40 60 % 40 60 % 250 300 ps Typ. Max. Unit 166 MHz 166 MHz 5 ns 5 ns 55 % AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 5V±10% Parameter Description Test Condition Min. fIN Input Frequency Input Clock 14 fOUT Output Frequency Spread Off 13 tR Output Rise Time VDD, 15-pF load, 0.8V–2.4V tF Output Fall Time VDD, 15-pF load, 2.4V–0.8V tOD Output Duty Cycle 15-pF load tID Input Duty Cycle tJCYC Jitter, Cycle-to-Cycle 2 2 45 40 100 60 % 200 ps Ordering Information Ordering Code Package Type Product Flow W530-02H 20-pin Plastic SSOP (209-mil) Commercial, 0°C to 70°C W530-02HT 20-pin Plastic SSOP (209-mil) - Tape and Reel Commercial, 0°C to 70°C Document #: 38-07190 Rev. *A Page 6 of 8 W530-02 Package Drawing and Dimension 20-pin (5.3 mm) Shrunk Small Outline Package O20 51-85077-*C PREMIS and SMARTSPREAD are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07190 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W530-02 Document History Page Document Title: W530-02 Frequency-multiplying, Peak-reducing EMI Solution Document Number: 38-07190 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110591 01/07/02 DSG Changed from Spec number: 38-01062 to 38-07190 *A 122549 01/08/03 RGL Added a SMARTSPREAD™ in the features area. Document #: 38-07190 Rev. *A Page 8 of 8