Preliminary W25S243A 64K × 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W25S243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 × 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduces power dissipation. This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle. FEATURES • Synchronous operation • Pipelined/non-pipelined data output capability • High-speed access time: 12 nS • Supports snooze mode (low-power state) • Single +3.3V power supply • • Individual byte write capability Internal burst counter supports Intel burst (Interleaved) mode & linear burst mode • 3.3V LVTTL compatible I/O • Supports 2T/1T mode • Clock-controlled and registered input • Packaged in 128-pin QFP and TQFP • Asynchronous output enable BLOCK DIAGRAM A(15:0) INPUT REGISTER 64K X 64 CORE ARRAY CLK CE(3:1) GW BWE CONTROL LOGIC BW(8:1) DATA I/O REGISTER REGISTER OE I/O(64:1) ADSC ADSP ADV LBO FT ZZ -1- Publication Release Date: November 1998 Revision A1 Preliminary W25S243A PIN CONFIGURATION V D C D NEN Q C2 C VSSQ I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 VDDQ VSSQ I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 VDDQ VSSQ I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 VDDQ 1 1 2 2 8 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 3 9 / / / / / CV V/ B BB B/ C E S D C W W W WO L 3 S DE8 7 6 5 EK / / / / / AA/ V / / B / BBVV B BDDAS W G WWS D W WS S D S E W4 3 S D 2 1 C P V Q 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 102 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 65 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 V/ SF ST Q / AA AV VAA A AA RAA AAA VVAA A Z V L 1 1 1 DS1 1 1 9 8 S 7 6 5 4 3 DS 2 1 0 Z D V D B54 3 DS2 1 0 DS Q O -2- VDDQ I/O32 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 VSSQ VDDQ I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 VSSQ VDDQ I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 VSSQ Preliminary W25S243A PIN DESCRIPTION SYMBOL TYPE DESCRIPTION Input, Synchronous Host address I/O, Synchronous Data Inputs/Outputs Input, Clock Processor host bus clock CE1, CE2, CE3 Input, Synchronous Chip enables GW Input, Synchronous Global write BWE Input, Synchronous Byte write enable from cache controller BW1− BW8 Input, Synchronous Host bus byte enables used with BWE OE Input, Asynchronous Output enable input ADV Input, Synchronous Internal burst address counter advance ADSC Input, Synchronous Address status from Chip Set ADSP Input, Synchronous Address status from CPU ZZ Input, Asynchronous Snooze pin for low-power state, internal pull low FT Input, Static Connected to VSSQ: Device operates in flowthrough (non-pipelined) mode. A0−A15 I/O1−I/O64 CLK Connected to VDDQ or unconnected: Device operates in pipelined mode. LBO Input, Static Lower address burst order Connected to VSSQ: Device is in linear mode. Connected to VDDQ or unconnected: Device is in non-linear mode. VDDQ I/O power supply VSSQ I/O ground VDD Power supply VSS Ground RSV Reserved pin, don't use these pins NC No connection -3- Publication Release Date: November 1998 Revision A1 Preliminary W25S243A FUNCTIONAL DESCRIPTION The W25S243A is a synchronous-burst pipelined SRAM designed for use in high-end personal computers. It supports two burst address sequences for Intel systems (Interleaved mode) and linear mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC and the burst counter is incremented whenever ADV is sampled low. The device can also be switched to non-pipelined mode if necessary. BURST ADDRESS SEQUENCE INTEL SYSTEM ( LBO = VDDQ) LINEAR MODE ( LBO = VSSQ) A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] External Start Address 00 01 10 11 00 01 10 11 Second Address 01 00 11 10 01 10 11 00 Third Address 10 11 00 01 10 11 00 01 Fourth Address 11 10 01 00 11 00 01 10 The device supports several types of write mode operations. BWE and BW [8:1] support individual byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is used to override the byte enable signals and allows the cache controller to write all bytes to the SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM latches both data and valid byte enable signals from the processor. TRUTH TABLE ADDRESS USED CE1 CE2 CE3 ADSP Unselected No 1 X X Unselected No 0 X 1 Unselected No 0 0 Unselected No 0 X Unselected No 0 Begin Read External 0 Begin Read CYCLE ADSC ADV OE DATA WRITE* X 0 X X Hi-Z X 0 X X X Hi-Z X X 0 X X X Hi-Z X 1 1 0 X X Hi-Z X 0 X 1 0 X X Hi-Z X 1 0 0 X X X Hi-Z X External 0 1 0 1 0 X X Hi-Z Read Continue Read Next X X X 1 1 0 1 Hi-Z Read Continue Read Next X X X 1 1 0 0 D-Out Read Continue Read Next 1 X X X 1 0 1 Hi-Z Read Continue Read Next 1 X X X 1 0 0 D-Out Read Suspend Read Current X X X 1 1 1 1 Hi-Z Read Suspend Read Current X X X 1 1 1 0 D-Out Read Suspend Read Current 1 X X X 1 1 1 Hi-Z Read Suspend Read Current 1 X X X 1 1 0 D-Out Read -4- Preliminary W25S243A Truth Table, continued ADDRESS USED CE1 CE2 CE3 Begin Write Current X X Begin Write Current 1 X Begin Write External 0 Next X CYCLE Continue Write ADSP ADSC ADV OE DATA WRITE* X 1 1 1 X Hi-Z Write X X 1 1 X Hi-Z Write 1 0 1 0 X X Hi-Z Write X X 1 1 0 X Hi-Z Write Continue Write Next 1 X X X 1 0 X Hi-Z Write Suspend Write Current X X X 1 1 1 X Hi-Z Write Suspend Write Current 1 X X X 1 1 X Hi-Z Write Notes: 1. For a detailed definition of read/write, see the Write Table below. 2. An "X" means don't care, "1" means logic high, and "0" means logic low. 3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled synchronous to the bus clock except for the OE pin. 4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timings are met. WRITE TABLE READ/WRITE FUNCTION GW BWE BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1 Read 1 1 X X X X X X X X Read 1 0 1 1 1 1 1 1 1 1 Write byte 1 I/O1−I/O8 1 0 1 1 1 1 1 1 1 0 Write byte 2 I/O9−I/O16 1 0 1 1 1 1 1 1 0 1 Write byte 2, byte 1 1 0 1 1 1 1 1 1 0 0 Write byte 3 I/O17−I/O24 1 0 1 1 1 1 1 0 1 1 Write byte 3, byte 1 1 0 1 1 1 1 1 0 1 0 Write byte 3, byte 2 1 0 1 1 1 1 1 0 0 1 Write byte 3, byte 2, byte 1 1 0 1 1 1 1 1 0 0 0 Write byte 4, I/O25−I/O32 1 0 1 1 1 1 0 1 1 1 Write byte 4, byte 1 1 0 1 1 1 1 0 1 1 0 Write byte 4, byte 2 1 0 1 1 1 1 0 1 0 1 Write byte 4, byte 2, byte 1 1 0 1 1 1 1 0 1 0 0 Write byte 4, byte 3 1 0 1 1 1 1 0 0 1 1 Write byte 4, byte 3, byte 1 1 0 1 1 1 1 0 0 1 0 Write byte 4, byte 3, byte 2 1 0 1 1 1 1 0 0 0 1 Write byte 4, byte 3, byte 2, byte 1 1 0 1 1 1 1 0 0 0 0 Write byte 5, I/O33−I/O40 1 0 1 1 1 0 1 1 1 1 Write byte 5, byte 1 1 0 1 1 1 0 1 1 1 0 -5- Publication Release Date: November 1998 Revision A1 Preliminary W25S243A Write Table, continued READ/WRITE FUNCTION GW BWE BW8 BW7 BW6 BW5 BW4 BW3 BW2 BW1 Write byte 5, byte 2 1 0 1 1 1 0 1 1 0 1 Write byte 5, byte 2, byte 1 1 0 1 1 1 0 1 1 0 0 Write byte 5, byte 3 1 0 1 1 1 0 1 0 1 1 Write byte 5, byte 3, byte 1 1 0 1 1 1 0 1 0 1 0 Write byte 5, byte 3, byte 2 1 0 1 1 1 0 1 0 0 1 Write byte 5, byte 3, byte 2, byte 1 1 0 1 1 1 0 1 0 0 0 Write byte 5, byte 4 1 0 1 1 1 0 0 1 1 1 Write byte 5, byte 4, byte 1 1 0 1 1 1 0 0 1 1 0 Write byte 5, byte 4, byte 2 1 0 1 1 1 0 0 1 0 1 Write byte 5, byte 4, byte 2, byte 1 1 0 1 1 1 0 0 1 0 0 Write byte 5, byte 4, byte 3 1 0 1 1 0 0 0 1 1 Write byte 5, byte 4, byte 3, byte 1 1 0 1 1 1 0 0 0 1 0 Write byte 5, byte 4, byte 3, byte 2 1 0 1 1 1 0 0 0 0 1 Write byte 5, byte 4, byte 3, byte 2, byte 1 1 0 1 1 1 0 0 0 0 0 Write byte 6 1 0 1 1 0 1 1 1 1 1 Write byte 6, byte 1 1 0 1 1 0 1 1 1 1 0 Write byte 6, byte 2 1 0 1 1 0 1 1 1 0 1 Write byte 6, byte 2, byte 1 1 0 1 1 0 1 1 1 0 0 ..... and so on ..... ... ... ... ... ... ... ... ... ... ... Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 2, byte 1 1 0 0 0 0 0 0 1 0 0 Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3 1 0 0 0 0 0 0 0 1 1 Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3, byte 1 1 0 0 0 0 0 0 0 1 0 Write byte 8, byte 7, byte 6, byte 5, byte 4, byte 3, byte 2 1 0 0 0 0 0 0 0 0 1 Write all bytes 1 0 0 0 0 0 0 0 0 0 Write all bytes 0 x x x x x x x x x 1 The ZZ state is a low-power state in which the device consumes less power than in the unselected mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the ZZ pin low for a set period of time will wake up the SRAM again. While the SRAM is in ZZ mode, data retention is guaranteed, but the chip will not monitor any input signal except for the ZZ pin. In the unselected mode, on the other hand, all the input signals are monitored. -6- Preliminary W25S243A DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to 4.6 V -0.5 to 4.6 VSSQ -0.5 to VDDQ +0.5 1.0 -65 to 150 V V W °C 0 to +70 °C Core Supply Voltage to Vss I/O Supply Voltage to Vss Input/Output to VSSQ Potential Allowable Power Dissipation Storage Temperature Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C) SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Input Low Voltage Input High Voltage PARAMETER VIL VIH - -0.5 +2.0 - +0.8 VDD +0.3 V V Input Leakage Current ILI VIN = VSSQ to VDDQ -10 - +10 µA Output Leakage Current ILO VI/O = VSSQ to VDDQ, and data I/O pins in high-Z state defined in truth table -10 - + 10 µA Output Low Voltage Output High Voltage Operating Current VOL VOH IDD IOL = +8.0 mA IOH = -4.0 mA 2.4 - - 0.4 350 V V mA Standby Current ISB Unselected mode defined in truth table, VIN, VIO = VIH (min.) /VIL (max.) TCYC ≥ min. - - 80 mA ZZ Mode Current IZZ ZZ mode, TCYC ≥ min. - - 5 mA TCYC ≥ min. , I/O = 0 mA Note: Typical characteristics are measured at VDD = 3.3V, TA = 25° C. CAPACITANCE (VDD = 3.3V, TA = 25° C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/Output Capacitance CI/O VOUT = 0V 8 pF Note: These parameters are sampled but not 100% tested. -7- Publication Release Date: November 1998 Revision A1 Preliminary W25S243A AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3V Input Rise and Fall Times 2 nS Input and Output Timing Reference Level 1.5V Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA AC Test Loads and Waveform R1 320 ohm RL = 50 ohm 3.3V VL = 1.5V OUTPUT 5 pF OUTPUT 30 pF Including Jig and Scope Zo = 50 ohm 3.0V Including Jig and Scope R2 350 ohm (For T KHZ, TKLZ, TOHZ, TOLZ, measurement) 90% 90% 10% 10% 0V 2 nS 2 nS AC Timing Characteristics (VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C, all timings measured in pipelined mode) PARAMETER SYMBOL W25S243A-12 UNIT MIN. MAX. Add. Setup Time TAS 2.5 - nS Add. Hold Time TAH 0.5 - nS Write Data Setup Time TDS 2.5 - nS Write Data Hold Time TDH 0.5 - nS ADV Setup Time TADVS 2.5 - nS ADV Hold Time TADVH 0.5 - nS -8- NOTES Preliminary W25S243A AC Timing Characteristics, continued PARAMETER SYMBOL W25S243A-12 UNIT MIN. MAX. NOTES ADSP Setup Time TADSS 2.5 - nS ADSP Hold Time TADSH 0.5 - nS ADSC Setup Time TADCS 2.5 - nS ADSC Hold Time TADCH 0.5 - nS CE1 , CE2, CE3 Setup Time TCES 2.5 - nS CE1 , CE2, CE3 Hold Time TCEH 0.5 - nS GW , BWE X Setup Time TWS 2.5 - nS GW , BWE X Hold Time TWH 0.5 - nS Clock Cycle Time TCYC 15 - nS Clock High Pulse Width TKO 6 - nS Clock Low Pulse Width TKL 6 - nS Clock to Output Valid TKQ - 12 nS Clock to Output High-Z TKHZ 2 15 nS 1 Clock to Output Low-Z TKLZ 0 - nS 1 Clock to Output Invalid TKX 2 - nS 1 Output Enable to Output Valid TOE - 7 nS Output Enable to Output High-Z TOHZ - 7 nS 1 Output Enable to Output Low-Z TOLZ 0 - nS 1 Output Enable to Output Invalid TOX 0 - nS ZZ Standby Time TZZS - 100 nS 2 ZZ Recover Time TZZR 100 - nS 3 Notes: 1. These parameters are sampled but not 100% tested 2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active. 3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode. 4. Configuration signals LBO and FT are static and should not be changed during operation. -9- Publication Release Date: November 1998 Revision A1 Preliminary W25S243A TIMING WAVEFORMS Read Cycle Timing Single Read Unselected Burst Read TCYC CLK TADSS T KH TKL TADSH ADSP is blocked by CE1 inactive ADSP TADCS TADCH ADSC initiated read ADSC T ADVS TADVH Suspend Burst ADV TAS A[15:0] TAH RD1 RD3 RD2 T WS TWH T WS TWH GW BWE BW[4:1] T CES TCEH TCES TCEH TCES TCEH CE1 masks ADSP CE1 CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 CE2 CE3 TOE T OHZ OE T OX TOLZ Data-Out High-Z T KLZ 1a T KX 2a T KX 2b 2d 3a TKHZ T KQ Data-In 2c High-Z DON'T CARE UNDEFINED - 10 - Preliminary W25S243A Timing Waveforms, continued Write Cycle Timing Single Write TCYC Burst Write Write Unselected CLK T KH TKL TADSS T ADSH ADSP is blocked by CE1 inactive ADSP TADCS TADCH TADVS TADVH ADSC initiated write ADSC ADV ADV must be inactive for ADSP write T AS T AH A[15:0] WR2 WR1 TWS T WH TWS T WH TWS TWH WR3 GWE allows processor address (and BE=BW) to be pipelined during a writeback GW BWE WR1 BW[4:1] TCES T CEH TCES TCEH TCES TCEH WR2 WR3 CE1 masks ADSP CE1 CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 CE2 CE3 OE Data-Out High-Z T DS TDH Data-In High-Z 1a BW[4:1] are applied only to first cycle of WR2 2a 2b 2c 2d 3a DON'T CARE UNDEFINED - 11 - Publication Release Date: November 1998 Revision A1 Preliminary W25S243A Timing Waveforms, continued Read/Write Cycle Timing Single Write TCYC Single Read Burst Read Unselected CLK TADSS TKH TKL TADSH ADSP is blocked by CE1 inactive ADSP TADCS TADCH ADSC initiated read ADSC TADVS T ADVH Suspend Burst ADV TAS A[15:0] TAH RD1 RD2 WR1 T WS TWH T WS TWH GW BWE T WS TWH WR1 BW[4:1] T CES TCEH TCES T CEH TCES T CEH CE1 masks ADSP CE1 CE2 and CE3 only sampled with ADSP or ADSC CE2 Unselected with CE3 CE3 T OE TOHZ OE TOH TOLZ Data-Out High-Z T KLZ 2a 1a T KHZ High-Z 2b 2c 2d TKHZ TDSTDH TKQ Data-In TKX 1a DON'T CARE UNDEFINED - 12 - Preliminary W25S243A Timing Waveforms, continued ZZ and RD Timing Single Read Read Snooze -with Data Retention TCYC CLK TADSS TKH TKL TADSH ADSP ADSC TADVS TADVH ADV TAS A[15:0] TAH RD1 RD2 TWS TWH TWS TWH TWS TWH GW BWE BW[4:1] RD TCES TCEH TCES TCEH TCES TCEH RD RD CE1 CE2 CE3 TOE TOHZ OE TOH TOLZ Data-Out High-Z TKLZ 1a TKQ Data-In TKX TKHZ High-Z TZZS TZZR ZZ DON'T CARE UNDEFINED - 13 - Publication Release Date: November 1998 Revision A1 Preliminary W25S243A ORDERING INFORMATION PART NO. ACCESS TIME (nS) OPERATING CURRENT MAX. (mA) STANDBY CURRENT MAX. (mA) PACKAGE W25S243AF-12 12 350 80 128-pin QFP W25S243AD-12 12 350 80 128-pin TQFP Notes 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 14 - Preliminary W25S243A PACKAGE DIMENSIONS 128-pin QFP HD D 128 103 1 102 E E H 38 65 39 e 64 b c A θ A2 A1 See Detail F Seating Plane L y L1 Dimension in inches Symbol A A1 A2 b c D E e HD HE L L1 y θ Min. Nom. Max. Dimension in mm Min. Nom. Max. 0.134 0.004 3.40 0.10 0.107 0.113 2.57 2.72 2.87 0.006 0.008 0.010 0.15 0.20 0.25 0.004 0.006 0.010 0.10 0.15 0.25 0.547 0.551 0.555 13.90 14.00 14.10 0.783 0.787 0.791 19.90 20.00 20.10 0.101 0.50 0.020 0.669 0.677 0.685 17.00 17.20 17.40 0.905 0.913 0.921 23.00 23.20 23.40 0.023 0.031 0.039 0.60 0.80 1.00 0.055 0.063 0.071 1.40 1.60 1.80 0.004 0 Detail F 12 - 15 - 0.10 0 12 Publication Release Date: November 1998 Revision A1 Preliminary W25S243A Package Dimensions, continued 128-pin TQFP HD D 128 103 1 102 E E H 38 65 39 e 64 b c A 2 θ A L 1 See Detail F Seating Plane A y Dimension in inches Symbol A A1 A2 b c D E e HD HE L L1 y θ Min. Nom. Max. L1 Dimension in mm Min. Nom. 0.063 0.002 0.053 Max. 1.60 0.05 0.055 0.057 1.35 1.40 1.45 0.006 0.008 0.011 0.15 0.20 0.27 0.004 0.006 0.010 0.10 0.15 0.25 0.547 0.551 0.555 13.90 14.00 14.10 0.783 0.787 0.791 19.90 20.00 20.10 0.50 0.020 0.626 0.630 0.634 15.90 16.00 16.10 0.862 0.866 0.870 21.90 22.00 22.10 0.018 0.024 0.030 0.45 0.60 0.75 0.039 1.00 0.004 0 12 - 16 - 0.10 0 12 Detail F Preliminary W25S243A VERSION HISTORY VERSION DATE A1 Nov. 1998 Headquarters PAGE DESCRIPTION Initial Issued Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 17 - Publication Release Date: November 1998 Revision A1