M62382FP 5 V Type 12-bit 4ch Composite Multiplying D/A Converter REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Description The M62382FP is a semiconductor integrated circuit of 5 V CMOS structure with 12-bit 4 channels of built-in multiplying D/A converters and 8-bit 8 channels of built-in multiplying D/A converters. 8-bit D/A converters, when used in combination with 12-bit D/A converters, can operate in a wider range. Parallel data input under the 2 modes (A, B) of channel assignment allows for easier usage. Features • • • • Built-in low power 12-bit 4 channels D/A converters 8-bit D/A converter with buffer making full swing between VCC and GND. 2 modes (A, B) of channel assignment Zero level function Built-in function of retaining arbitrary assigned data in 12-bit D/A converter. In normal use, output voltage can be switched to the voltage corresponding to the formerly assigned data by the setting of Z01, making it possible to calibrate the data (output voltage value). Application High precision measurement equipments such as memory testers, industrial measurement equipments, medical equipments, standard equipments in general REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Page 1 of 10 M62382FP Block Diagram 0-level 12-bit D/A register Z00 Z01 12 12 12 12 VrefU (12DA) 1 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 for 12-bit D/A DA-selector 24 8 LD A04 A03 A01 A00 12-bit D/A C 12-bit register VrefL (12DA) 1 8-bit register VrefU (8DA1) 1 for offset 8-bit D/A 2-4 A08 A07 A06 A05 DAout (12DA) 1 8-bit D/A C for offset 0 dB 8 VrefL (8DA1) 1 VrefU (8DA2) 1 8-bit register for gain 8-bit D/A A02 3 3 8-bit D/A C for gain DAout (8DA1) 1 0 dB DAout (8DA2) 1 3 VrefL (8DA2) 1 24 CH1 D/A C 28 CH2 D/A C VrefU (12DA) 2 DAout (12DA) 2 VrefL (12DA) 2 VrefU (8DA1) 2 DAout (8DA1) 2 VrefL (8DA1) 2 VrefU (8DA2) 2 DAout (8DA2) 2 VrefL (8DA2) 2 CH3 D/A C VrefU (12DA) 3 DAout (12DA) 3 VrefL (12DA) 3 VrefU (8DA1) 3 DAout (8DA1) 3 VrefL (8DA1) 3 VrefU (8DA2) 3 DAout (8DA2) 3 VrefL (8DA2) 3 CH4 D/A C VrefU (12DA) 4 DAout (12DA) 4 VrefL (12DA) 4 VrefU (8DA1) 4 DAout (8DA1) 4 VrefL (8DA1) 4 VrefU (8DA2) 4 DAout (8DA2) 4 VrefL (8DA2) 4 24 28 VDD 24 VDD VSS VSS VCC VCC GND GND REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Page 2 of 10 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VrefL (12DA) 1 DAout (12DA) 1 VrefU (12DA) 1 NC VrefL (8DA2) 1 DAout (8DA2) 1 VrefU (8DA2) 1 NC REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Page 3 of 10 VrefL (8DA1 )1 DAout (8DA1) 1 VrefU (8DA1) 1 GND NC GND VrefU (8DA1) 2 DAout (8DA1) 2 VrefL (8DA1) 2 NC VrefU (8DA2) 2 DAout (8DA2) 2 VrefL (8DA2) 2 NC (Top view) Outline: PLQP0100KB-A (100P6Q-A) VrefU (12DA) 2 DAout (12DA) 2 VrefL (12DA) 2 NC VrefU (12DA) 3 DAout (12DA) 3 VrefL (12DA) 3 52 51 VrefL (8DA2) 3 55 53 DAout (8DA2) 3 56 54 NC 59 VrefU (8DA2) 3 VrefL (8DA1) 3 60 57 DAout (8DA1) 3 61 58 GND VrefU (8DA1) 3 62 GND NC VrefU (8DA1) 4 65 63 DAout (8DA1) 4 66 64 NC VrefL (8DA1) 4 VrefU (8DA2) 4 69 67 DAout (8DA2) 4 70 68 NC VrefL (8DA2) 4 73 71 VrefU (12DA) 4 74 72 VrefL (12DA) 4 DAout (12DA) 4 75 M62382FP Pin Arrangement M62382FP NC 76 50 NC NC 77 49 VCC GND 78 48 VSS D11 79 47 VDD NC 80 46 Z00 D10 81 45 Z01 D09 82 44 NC NC 83 43 LD D08 84 42 A08 D07 85 41 NC NC 86 40 A07 D06 87 39 A06 NC 88 38 NC D05 89 37 A05 NC 90 36 A04 D04 91 35 NC D03 92 34 A03 NC 93 33 A02 D02 94 32 NC D01 95 31 A01 NC 96 30 A00 D00 97 29 NC VSS 98 28 VSS NC 99 27 VCC NC 100 26 NC M62382FP Pin Description Pin No. 1, 25, 51, 75 2, 24, 52, 74 3, 23, 53, 73 Pin Name VrefL (12) DAout (12) VrefU (12) Function 12-bit D/A converter lower reference voltage input terminal 12-bit D/A converter output terminal 12-bit D/A converter upper reference voltage input terminal 5, 9, 17, 21, 55, 59, 67, 71 VrefL (8) 8-bit D/A converter lower reference voltage input terminal 6, 10, 16, 20, 56, 60, 66, 70 DAout (8) 8-bit D/A converter output terminal 7, 11, 15, 19, 57, 61, 65, 69 27, 49 12, 14, 62, 64, 78 47 28, 48, 98 30, 31, 33, 34, 36, 37, 39, 40, 42 VrefU (8) 8-bit D/A converter upper reference voltage input terminal VCC GND VDD VSS A00 to A08 Analog power supply terminal Analog GND terminal Digital power supply terminal Digital GND terminal Address terminal D00 to D11 D/A data terminal LD D/A LD terminal Z00 Z01 NC Zero level data assignment terminal Zero level data load terminal Non-connection 79, 81, 82, 84, 85, 87, 89, 91, 92, 94, 95, 97 43 46 45 4, 8, 13, 18, 22, 29, 32, 35, 38, 41, 44, 50, 54, 58, 63, 68, 72, 76, 77, 80, 83, 86, 88, 90, 93, 96, 99, 100 Absolute Maximum Ratings Item Digital supply voltage Analog supply voltage Digital input voltage D/A reference voltage D/A output voltage Operating temperature Storage temperature Symbol VDD VCC VDIN Vref VDAout Topr Tstr REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Page 4 of 10 Ratings –0.3 to +7.0 –0.3 to +7.0 –0.3 to VDD + 0.3 ≤ 7.0 –0.3 to VDD + 0.3 ≤ 7.0 –0.3 to VDD + 0.3 ≤ 7.0 –20 to +85 –40 to +125 Unit V V V V V °C °C M62382FP Electrical Characteristics <Digital Part> (VDD = VCC = 5 V, VSS = GND (= 0 V), VrefU = VCC, VrefL = GND, Ta = –20 to +85°C, unless otherwise noted.) Item Digital supply current Input leak current Input capacitive load Symbol IDD IILK CIN Min Limits Typ Max Unit — –10 — — — — 3.0 +10 1.2 mA µA pF Conditions fLD = 1 MHz, VDIN = VSS, or VDD VDIN = VSS to VDD <Analog Part> (VDD = VCC = 5 V, VSS = GND (= 0 V), VrefU = VCC, VrefL = GND, Ta = –20 to +85°C, unless otherwise noted.) Item Symbol Analog supply current ICC Reference current for D/A converter (U to L) Iref Min Limits Typ Max Unit — — 1.6 0.7 6.0 2.0 mA mA — 0.1 0.4 mA Buffer amplifier output drive range IOA ±1.5 — — mA Output resistance RO Differential nonlinearity error SDL SNL Zero code error SZERO 2.2 10 — — — — — — — +1.5 +1.0 +2.0 +1.0 +3.0 kΩ Ω LSB Nonlinearity error — — –1.5 –1.0 –2.0 –1.0 –3.0 Full code error SFULL –3.0 — +3.0 LSB Temperature coefficient of nonlinearity error ∆NL/t — — 0.05 LSB/°C Cross talk between the channels CT — 75 — dB Power supply rejection ratio PSRR — — — 65 65 55 — — — dB Temperature coefficient of D/A output Settling time of 12-bit D/A Settling time of 8-bit D/A TCo — 20 — ppm/°C tSTDA tstDA — — 1.4 70 — — µs µs REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Page 5 of 10 LSB LSB Conditions D/A output = 1/2 MSB 12-bit D/A D/A data for maximum current of D/A reference, each circuit current from 8-bit D/A VrefU to VrefL Upper side saturation voltage = 0.3 V Lower side saturation voltage = 0.3 V 12-bit D/A: R-2R ladder output 8-bit D/A: Buffer amplifier output 12-bit D/A VrefU = 5.0 V, VrefL = 0.0 V Ta = 25°C 8-bit D/A 12-bit D/A VrefU = 5.0 V, VrefL = 0.0 V Ta = 25°C 8-bit D/A VrefU = 5.0 V, VrefL = 0.0 V Ta = 25°C VrefU = 5.0 V, VrefL = 0.0 V Ta = 25°C VrefU = 5.0 V, VrefL = 0.0 V SNL 12-bit D/A / 60°C (Ta = 25 to 85°C) 12-bit D/A Vin = –10 dBm f = 100 Hz to 1 kHz 8-bit D/A 12-bit D/A 8-bit D/A VCCin = VCC – 10 dBm f = 100 Hz to 1 kHz Without load (IOA = 0 mA) Until output takes 1/2 LSB of the final value M62382FP Recommended Operating Condition (Ta = 25 to 75°C) Min Limits Typ Max Unit Analog power supply voltage Digital power supply voltage H side D/A reference voltage L side D/A reference voltage H level digital input voltage L level digital input voltage D/A data set up time VCC VDD VrefH VrefL VIH VIL tDDCH 4.5 4.5 VCC – 0.5 GND 2 GND 10 5.0 5.0 — — — — — 5.5 5.5 VCC 0.5 VDD 0.8 — V V V V V V ns Address data set up time tADCH 150 — — ns Driving 12-bit and 8-bit D/A converters at same time D/A data hold time tDCHD tLDH + 35 — — ns Driving 12-bit and 8-bit D/A converters at same time Address data hold time tACHD tLDH + 10 — — ns Driving 12-bit and 8-bit D/A converters at same time Load signal H level hold time tLDH 100 — — ns Driving 12-bit and 8-bit D/A converters at same time Z00 signal H level hold time tZSH 15 — — ns Item Symbol Conditions Driving 12-bit and 8-bit D/A converters at same time Timing Chart tDDCH D/A data (12-bit: D00 to D11) D0 tDCHD D1 D2 D1 D/A data (D0) tADCH Address data (9-bit: A00 to A08) A0 D2 tACHD A1 Address data (A0) A2 A1 A2 tLDH Load signal (LD) tSTDA DAout (12DA) n (CHn 12-bit DAout) DAout (Old data) DAout (D0 data) DAout (D2) tstDA DAout (8DA) m (CHm 8-bit DAout) REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Page 6 of 10 DAout (Old data) DAout (D1 data) M62382FP Zero Level Setting (input/output): Z00, Z01 tDDCH tDCHD Data for D/A converter (D00 to D11: 12-bit data) Zero level output value is set by 12-bit data. Data for zero level setting tZSH Zero level setting signal (Z00) Data sampling when signal rises, data retained when signal falls. Set data to be memorized Zero level output and normal mode output can be swiched with each other. Zero level load signal (Z01) D/A output zero level at signal rise, D/A output recovered at signal fall. tSTDA Back to original output value after recovery. DAout (12DA) (12-bit DAout) 12-bit DAC output DAout (normal output) tSTDA DAout (zero level output) DAout (normal output) Digital Format 1. Channel Select Setting (A01, A02) Setting Select CH1 select CH2 select CH3 select CH4 select 2. Channel Assign Mode Setting (A02) A01 0 0 1 1 A00 0 1 0 1 Channel Assign Mode Setting A channel assign mode B channel assign mode 3. 8-bit D/A Converter Select Setting (A03) 4. D/A Converter Select Setting (A04) 8-bit D/A Converter Select Setting D/A select for offset D/A select for gain D/A Converter Select Setting 12-bit D/A converter select 8-bit D/A converter select A03 0 1 A02 0 1 A04 0 1 5. Channel Select Setting B (A05, A06, A07, A08) Setting Select CH1 select CH2 select CH3 select CH4 select A05 1 0 0 0 A06 0 1 0 0 A07 0 0 1 0 A08 0 0 0 1 12-bit D/A D00 0 1 0 1 : 0 1 0 1 D01 0 0 1 1 : 0 0 1 1 D02 0 0 0 0 : 1 1 1 1 D03 0 0 0 0 : 1 1 1 1 D04 0 0 0 0 : 1 1 1 1 D05 0 0 0 0 : 1 1 1 1 D06 0 0 0 0 : 1 1 1 1 REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Page 7 of 10 D07 0 0 0 0 : 1 1 1 1 D08 0 0 0 0 : 1 1 1 1 D09 0 0 0 0 : 1 1 1 1 D10 0 0 0 0 : 1 1 1 1 D11 0 0 0 0 : 1 1 1 1 D/A Output VrefL12 (VrefU12 – VrefL12) / 4096 × 1 (VrefU12 – VrefL12) / 4096 × 2 (VrefU12 – VrefL12) / 4096 × 3 : (VrefU12 – VrefL12) / 4096 × 4092 (VrefU12 – VrefL12) / 4096 × 4093 (VrefU12 – VrefL12) / 4096 × 4094 (VrefU12 – VrefL12) / 4096 × 4095 M62382FP 8-bit D/A D00 0 1 0 1 : 0 1 0 1 D01 0 0 1 1 : 0 0 1 1 D02 0 0 0 0 : 1 1 1 1 D03 0 0 0 0 : 1 1 1 1 D04 0 0 0 0 : 1 1 1 1 D05 0 0 0 0 : 1 1 1 1 D06 0 0 0 0 : 1 1 1 1 D07 0 0 0 0 : 1 1 1 1 D08 — — — — : — — — — D09 — — — — : — — — — D10 — — — — : — — — — D11 — — — — : — — — — D/A Output VrefL8 (VrefU8 – VrefL8) / 256 × 1 (VrefU8 – VrefL8) / 256 × 2 (VrefU8 – VrefL8) / 256 × 3 : (VrefU8 – VrefL8) / 256 × 252 (VrefU8 – VrefL8) / 256 × 253 (VrefU8 – VrefL8) / 256 × 254 (VrefU8 – VrefL8) / 256 × 255 8-bit D/A Converter for Reference Voltage Power Supply VrefU 8-bit DAC Vout VrefU VrefL 12-bit DAC Vout VrefU VrefL 8-bit DAC Vout VrefL Note: Arbitrary voltage can be set without the connection to power supply by connecting the output terminal of 8-bit D/A converter with upper reference voltage and lower reference voltage of 12-bit D/A converter. Ultra High Precision D/A Converter VrefU 8-bit DAC Vout VrefU VrefL 12-bit DAC Vout VrefL Note: By connecting the output terminal of 8-bit D/A converter with the upper reference voltage of 12-bit D/A converter, D/A converter equivalent to 20-bit is configurated to have higher precision configuration. If more minute output variation is needed, 8-bit D/A converter can be utilized for compensation like this. REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Page 8 of 10 M62382FP Application Circuit 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 + 71 + 72 + 73 + 74 + 75 + 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 86 40 87 38 + + + + 25 24 23 22 21 20 19 18 17 16 15 9 + 14 26 13 27 100 12 28 99 11 29 98 10 30 97 8 31 96 7 32 95 6 33 94 5 34 93 4 35 92 3 36 91 2 37 90 1 89 + + 39 M62382FP 88 + + Caution This IC has four different kinds of terminals, which are to be applied by constant voltage when used. (VCC, VDD, VrefU, VrefL) D/A converter precision may be worsened when ripple voltage or spike is duplicated on these four terminals. So please be sure to put capacitor between each terminal and GND for stabilized D/A converter operation. REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Page 9 of 10 M62382FP Package Dimensions JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 50 76 bp c1 Reference Dimension in Millimeters Symbol c E *2 HE b1 D E A2 HD HE A A1 bp b1 c c1 26 1 ZE Terminal cross section 100 25 Index mark ZD y e *3 bp A1 c A A2 F L x L1 Detail F REJ03D0882-0300 Rev.3.00 Mar 25, 2008 Page 10 of 10 e x y ZD ZE L L1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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