ETC W65C832PL-10

THE WESTERN DESIGN CENTER, INC.
WDC W65C832 .,
') ~
W65CB32
SPECIFlCA~ION AND DA~A S ~~~
INFORMATION,
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A
M
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R
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Q
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R R
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VDD
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A1
VSS
A2
A3
A4
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AS
A6
6
7
8
9
10
3
2
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43
M
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X
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2
41
B
E
12
13
14
15
16
17 18 19
20
21
22
23
24
25
26
27
A
8
A
9
A
1
0
A
1
1
V
S
S
V
S
S
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1
2
A
1
3
A
1
4
A
1
S
5
44
V
D
A
40
39
38
37
36
35
34
33
32
31
30
29
28
11
~
7
MARCH 1991 4
V
S
S
W65C832
E8/E16
R/W­
VDD
DO/A16 D1/A17 D2/A18 D3/A19 D4/A20 D5/A21 D6/A22
D7/A23
WOC
THE WESTERN DESIGN CENTER, INC.
WOC reserves the right to make changes at any
time without notice in order to improve design
and supply the best possible product.
Information
contained
herein
is
provided
gratuitously and without liability, to any user.
Reasonable efforts have been made to verify the
accuracy of the information but no guarantee
whatsoever is given as to the accuracy or as to
its applicability to particular uses. In every
instance, i t must be the responsibility of the
user to determine the suitability of the
products for each application. WOC products are
not authorized for use as critical components in
life support devices or systems.
Nothing
contained herein shall be construed as a
recommendation to use any product in violation
of existing patents or other rights of third
parties. The sale of any WOC product is subject
to all WDC Terms and Conditions of. Sales and
Sales Policies, copies of which are available
upon request.
Copyright (C) 1981-1990 by The Western Design
Center, Inc. All rights reserved, including the
right of reproduction in whole or in part in any
form.
MARCH 1990 W65C832 THE WESTERN DESIGN CENTER, INC.
WOC
W6SC832 tABLE OF CONTENTS
INTRODUCTION
1
SECTION 1:
2
W65C832 FUNCTION DESCRIPTION
1.1 Instruction Register and Decode
1.2 Timing Control Unit . . .
1.3 Arithmetic and Logic Unit
1.4 Internal Registers . . .
1.5 Accumulators . . . . .
1.6 Data Bank Register.
1.7 Direct . . . . . . .
1.8 Index . . . . . . . .
1.9 Processor Status . .
1.10 Program Bank Register
1.11 Program Counter .
1.12 Stack Pointer . . . .
SECTION 2:
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
Abort . . . .
Address Bus . . . .
Bus Enable . . . .
Data/Address Bus.
Emulation Status.
Interrupt Request
Memory Lock . . .
Memory/Index Select Status.
Non-Maskable Interrupt.
Phase 2 In . . . . .
Read/Write . . • . .
Ready . . . . . . .
Reset . . . . . . .
Valid Data Address, Valid Program Address
VDD and VSS
Vector Pull . . . .
SECTION 3:
3.1
3.2
3.3
3.4
3.5
PIN FUNCTION DESCRIPTION
ADDRESSING MODES
Reset and Interrupt Vectors
Stack . . . . . . . . .
Direct. . . . . . . .'.
Program Address Space
Data Address Space . . . .
MARCH 1990 2
2
2
2
3
3
3
3
. 3
4
4
4
10 .11 .11 . . .11 .11 .12 . . 12 .12 .12 .12 .12 .13 .13 .13 .14 .14 .14 15 .15 .15 .15 .15 .15 WOC
THE WESTERN DESIGN CENTER, INC.
SECTION 4:
4.1
4.2
4.3
4.4
TIMING, AC AND DC CHARACTERISTICS
Absolute Maximum Ratings.
DC Characteristics.
AC Characteristics, 5V. .
AC Characteristics, 1.2V.
W65C832
24 .24 .25 .26 . .27 SECTION 5:
ORDERING INFORMATION
29
SECTION 6:
APPLICATION INFORMATION
30
SECTION 7:
ASSEMBLER SYNTAX STANDARDS
43 7.1
7.2
7.3
Directives . . . •
Comments . . . .
The Source Line
SECTION 8:
<
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
8.22
8 .23
CAVEATS
Stack Addressing . . . . . . .
Direct Addressing . . . . . .
Absolute Indexed Addressing.
ABORT. . . . . . . . . . .
VDA and VPA . . . . . . . .
Apple II, IIc, IIc and 11+ Disk Systems
DB/BA Operation . . . . . . . .
M/X Output. . . . . . . . . . . .
. ...
All Opcodes Function in All Modes of Operation.
Indirect Jumps . . . . . . . . . . . . . . . . .
Switching Modes . . . . . . . . . . . . . . . .
Hardware Interrupts, BRK, and COP Instructions.
Binary Mode. .
. ...
WAI Instruction
STP Instruction
COP Signatures.
WDM Opcode Use.
ROY Pulled During Write
MVN and MVP . . . . . . .
Interrupt Priorities. . . . . . . . . . .
Transfers from differing sized registers.
Stack Transfers.
. . .
. ...
REP / SEP . . . . . . . . . . . . . . . . .
MARCH 1991 .43 .43 .43 46 .47 .47 .48 .48 .48 .48 .49 .49 .49 .49 .49 .50 .50 .50 .50 .50 .50 . . 51 .51 .51 .51 .51 .51 THE WESTERN DESIGN CENTER, INC.
WOC
w65C832
TABLE OF CONTENTS
TABLES
SECTION 1:
1-1
FUNCTION DESCRIPTION
W65C832 Emulation and Register Width Control.
SECTION 2:
2-1
PIN FUNCTION DESCRIPTION
Pin Function Table. . . . . .
SECTION 3:
3-1
3-2
ADDRESSING MODES
Address Mode Formats.
Addressing Mode Summary
SECTION 4:
4-1
4-2
4-3A
4-3B
4-4A
SECTION
6-1
6-2
6-3
6-4
6-5
TIMING, AC AND DC CHARACTERISTICS
Absolute Maximum Ratings . . . .
DC Characteristics . . . . . . . .
AC Characteristics-5V, 4-7MHz .
AC Characteristics-5V, 8-10MHz.
AC Characteristics-1.2V, 40 KHz
6:
APPLICATION INFORMATION
Instruction Set . . . . . . . . . . .
Vector Locations . . . . . . . . . . .
Opcode Matrix . . . . . . . . . . . .
Operation, Operation Codes and Status Register.
Instruction Operation . . . . .
SECTION 7:
7-3-1
7-3-2
SECTION
8-1
ASSEMBLER SYNTAX STANDARDS
Alternate Mnemonics . .
Byte Selection Operator
8:
CAVEATS
2
9
10 .11 15 · .22 .23 24 .24 .25 .26 .26 .27 30 · .30 .31 .32 .33 34-42 43 .44 · .45 46 Compatibility Issues . . . . . • . . . . . . . . . . . . . 46-47 MARCH 1990 THE WESTERN DESIGN CENTER, INC.
WDC
W65C832
TABLE OF CONTENTS
FIGURES
SECTION 1:
1-1
1-2
1-3
1-4
1-5
Internal Architecture Block Diagram. . . .
W65C832 Native Mode Programming Model . . . .
W65C816 16-bit Emulation Programming Model.
W65C02 8-bit Emulation Programming Model.
W65C832 Status Register Coding. . . . . . .
SECTION 2:
2-1
PIN FUNCTION DESCRIPTION
W65C832 44 PLCC Pinout. . . .
2
. 5
. 6
7
8
9
10 .10 TIMING, AC AND DC CHARACTERISTICS
24 Timing Diagram. . . . . . . . . . . .
.28 SECTION 4:
4-1
FUNCTION DESCRIPTION
MARCH 1990 WDC THE WESTERN DESIGN CENTER, INC.
W65C832 INTRODUCTION The WDC W65C832 is a CMOS 32-bit microprocessor featuring total software
compatibility with their 8-bit NMOS and 8-bit and 16-bit CMOS 6500-series
predecessors. The W65C832 is pin-to-pin compatible with 16-bit devices currently
available. These devices offer the many advantages of CMOS technology I including
increased noise immunity,
higher reliability,
and greatly reduced power
requirements. A software switch determines whether the processor is in the 8-bit or
16-bit "emulation" mode, or in the native mode, thus allowing existing systems to
use the expanded features.
As shown in the processor programming model, the Accumulator, ALU, X and Y Index
registers have been extended to 32 bits. A 16-bit Program Counter, Stack Pointer
and Direct Page register augments the Direct Page addressing mode (formerly Zero
Page addressing). Separate Program Bank and Data Bank registers allow 24-bit memory
addressing with segmented or linear addressing for program space and 32-bit 4GByte
data space for ASIC use although only 24 bits of address are available in the
standard pin-out.
Four signals provide the system designer with many options.
The ABORT input can
interrupt the currently executing instruction without modifying internal register,
thus allowing virtual memory system design.
Valid Data Address (VDA) and Valid
Program Address (VPA) outputs facilitate dual cache memory by indicating w.hether a
data segment or program segment is accessed.
Modifying a vector is made easy by
monitoring the Vector Pull (VP) output.
\ KEY FEATURES OF THE W65C832
* Advanced CMOS design for low power * Separate program and data bank
power consumption and increased
registers allow program
noise immunity segmentation or full 16-MByte
linear addressing * Single 1.2-5.25V power supply,
* New Direct Register and stack as specified
relative addressing provides
* Emulation mode allows complete
hardware and software
capability for re-entrant, compatibility with W65C816 designs
re-cursive and re-Iocatable 24-bit
address
bus
allows
access
programming
*
to 16 MBytes of memory space
* 24 addressing modes-13 original
6502 modes, plus 11 new addressing
* Full 32-bit ALU, Accumulator,
and Index Registers
modes with 91 instructions using 255 opcodes * Valid Data Address (VDA) and
Valid Program Address (VPA)
* Wait-for-Interrupt (WAI) and output allows dual cache and
Stop-the Clock (STP) instructions cycle steal DMA implementation
further reduce power consumption, decrease interrupt latency and * Vector Pull (VP) output indicates
when interrupt vectors are being
allows synchronization with addressed. May be used to
external events implement vectored interrupt
* Co-Processor (COP) instruction design
with associated vector supports Abort
(ABORT)
input
and
associated
co-processor configurations, i.e.,
*
vector supports virtual memory
floating point processors
system design * Block move ability
MARCH 1990
1
WDC
THE WESTERN DESIGN CENTER, INC.
W65C832 SECTION 1
W65C832 FUNCTION DESCRIPTION
The W65C832 provides the design engineer with upward mobility and software
compatibility in applications where a 32-bit system configuration is desired. The
W65C832's 32-bit hardware configuration, coupled with current software allows a wide
selection of system applications.
In the Emulation mode, the W65C832 offers many
advantages, including full software compatibility with 6502, W65C02 or W65C816
coding. In addition, the W65C832' s powerful instruction set and addressing modes
make it an excellent choice for new 32-bit designs.
Internal organization of the W65C832 can be divided into two parts:
1)
The
Register Section and 2) The Control Section.
Instructions (or opcodes) obtained
from program memory are executed by implementing a series of data transfers within
the Register Section.
Signals that cause data transfers to be executed are
generated within the Control Section.
The W65C832 has a 32-bit internal
architecture with an 8-bit external data bus.
1.1
Instruction Register and Decode
An opcode enters the processor on the Data Bus, and is latched into the Instruction
Register during the instruction fetch cycle.
This instruction is then decoded,
along with timing and interrupt signals, to generate the various Instruction
Register control signals.
1.2
Timing Control Unit (TCU)
The Timing Control Unit keeps track of each instruction cycle as it is executed.
The TCU is set to zero each time an instruction fetch is executed, and is advanced
at the beginning of each cycle for as many cycles as is required to complete the
instruction.
Each data transfer between registers depends upon decoding the
contents of both the Instruction Register and the Timing Control Unit.
1.3
Arithmetic and Logic Unit (ALU)
All arithmetic and logic operations take place within the 32-bit ALU. In addition
to data operations, the ALU also calculates the effective address for relative and
indexed addressing modes. The result of a data operation is stored in either memory
or an internal register. Carry, Negative, OVerflow and Zero flags may be updated
following the ALU data operation.
1.4
Internal Registers (Refer to Programming Model)
MARCH 1990
2
WOC
THE WESTERN DESIGN CENTER, INC.
W65C832 1.5 Accumulator
The Accumulator is a general purpose register which stores one of the operands, or
the result of most arithmetic and logical operations.
In the Native mode the
Accumulator can be 8-, 16- or 32-bits wide.
1.6 Data Bank Register (DBR)
During modes of operation, the 8-bit Data Bank Register holds the default bank
address for memory transfers.
The 24-bit address is composed of the 16-bit
instruction effective address and the 8-bit Data Bank address. The register value
is multiplexed with the data value and is present on the Data/Address lines during
the first half of a data transfer memory cycle for the W65C832.
The Data Bank
Register is initialized to zero during Reset.
1.7 . Direct (D)
The 16-bit Direct Register provides an address offset for all instructions using
direct addressing.
The effective bank zero address is formed by adding the 8-bit
instruction operand address to the Direct Register.
The Direct Register is
initialized to zero during Reset.
1.8
Index (X and Y)
There are two Index Registers (X and Y) which may be used as general purpose
registers or to provide an index value for calculation of the effective address.
When executing an instruction with indexed addressing, the microprocessor fetches
the opcode and the base address, and then modifies the address by adding the Index
Register contents to the address prior to performing the desired operation.
Pre-indexing or post-indexing of indirect addresses may be selected. In the Native
mode, both Index Registers are 32 bits wide (providing the Index Select Bit (X)
equals zero). If the Index Select Bit (X) equals one, both registers will be 8 bits
wide, and the high bytes if forced to zero.
1.9
Processor Status (P)
The 8-bit Processor Status Register contains status flags and mode select bits. The
Carry (C), Negative (N), Overflow (V), and Zero (Z) status flags serve to report the
status of most ALU operations. These status flags are tested by use of Conditional
Branch instructions. The Decimal (D), IRQ Disable (I), Memory/Accumulator (M), and
Index (X) bits are used as mode select flags. These flags are set by the program to
change microprocessor operations.
The Emulation (E8 and E16) select and the Break (B) flags are accessible only
through the Processor Status Register.
The Emulation (E8) mode select flag is
selected by the Exchange Carry and Emulation Bits (XCE) instruction.
The XFE
instruction exchanges the Emulation (E8 and E16) mode select flags with the Overflow
Table 1, Emulation and Register Width Control, illustrates the
and Carry Flags.
features of the Native and Emulation modes. The M and X flags are always equal to
one in the 8-bit Emulation mode.
When an interrupt occurs during the Emulation
mode, the Break flag is written to stack memory as bit 4 of the Processor Status
Register.
MARCH 1990
3
WDC
1.10
THE WESTERN DESIGN CENTER, INC.
W65C832 Program Bank Register (PBR)
The 8-bit Program Bank Register holds the bank address for all instruction fetches.
The 24-bit address consists of the 16-bit instruction effective address and the
8-bit Program Bank address. The register value is multiplexed with the data value
and presented on the Data/Address lines during the first half of a program memory
read cycle. The Program Bank Register is initialized to zero during Reset. The PHK
instruction pushes the PBR register onto the Stack.
1.11
Program Counter (PC)
The 16-bit Program Counter Register provides the addresses which are used to step
the microprocessor through sequential program instructions.
The register is
incremented each time an instruction or operand is fetched from program memory.
1.12
Stack Pointer (S)
The Stack Pointer is a 16-bit register which is used to indicate the next available
location in the stack memory area.
It serves as the effective address in stack
addressing modes as well as subroutine and interrupt processing. The Stack Pointer
allows simple implementation of nested subroutines and multiple-level interrupts.
During the Emulation mode, the Stack Pointer high-order byte (SH) is always equal to
one. The bank address for all stack operations is Bank zero.
MARCH 1990
4
WDC
THE WESTERN DESIGN CENTER, INC.
Figure 1-1
W65C832 W65C832 Internal Architecture Simplified Block Diagram INDEX x
(3l. III TS)
i
a
::
a:
INDEX
v
(32. BITS)
....
....,:::>
II.
AO-A7
INTERRUPT
lOGIC
<II
-
ABOR1' (816)
....­
....
'"II:
..
o
Q
fll\f.lNG
CurlT,
TRANSI'ER
SWITCHES
<1>2 lIN)
A8-A15
CLOCK
GEN­
ERATon
<1>1 (OUT}
l~n2)
<l>2101IT) (R02)
Mll~l&)
00-07 (602)
n.n1AO-07/BA7181S)
VP (H'~)
E (816)
'so (e021
MARCH 1990
5
THE WESTERN DESIGN CENTER, INC.
WDC
8 Bits
8 Bits
W65C832
8 Bits
Index and Data Registers
X Register
x
Y Register
Y
ACCUMULATOR
A
Address Registers
Program Counter
IProgram Bank I
o
____________ IRegister (PBR) 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
o
PC
o
Direct Register
D
o
Stack Pointer
S
IData Banko
Register_______________________________
DBR
____________ 1
Status Register
Status
Figure 1-2
MARCH 1990
P
W65C832 Native Mode Programming Model
6
WDC
THE WESTERN DESIGN CENTER, INC.
8 Bits
8 Bits
8 Bits
W65C832 8 Bits
Index and Data Registers
X Register
x
Y Register
Y
ACCUMULATOR
A
Address Registers
o
1
______ 1
o
Program Bank
Register (PBR)
1
Program Counter
PC
1_ _ _ _ _ _ _ _ _ _ _ __
o
Direct Register
D
o
Stack Pointer
S
IData Bank
o
Register_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
DBR
______ 1
Status Register
Status
Figure 1-3
MARCH 1990
P
W65C816 16-bit Emulation Programming Model
7
WOC
W65C832 THE WESTERN DESIGN CENTER, INC.
8 Bits
8 Bits
8 Bits
Index and Data Registers
X Register
X
Y Register
Y
ACCUMULATOR
A
Address Registers
o
1Program Bank
_ _ _ _ _ _ 1 Register
(PBR)
1
Program Counter
o
Direct Register
o
IIIStack Pointer
- - - - - - - - - - - - _ - ­ ___--1_1_---------­
IData Bank
o
o
__________ 1
PC
1_ _ _ _ _ _ _ _ _ _ _ __
Register___________________
D
S
DBR
Status Register
Status
Figure 1-4
/'
P
W65C02 8-bit Emulation Programming Model
'\
MARCH 1990
8
WOC
THE WESTERN DESIGN CENTER, INC.
I Status Reg. (P) I
I lEI
I-I
I 111
lEI
181
I 1611181
INIVIMIXIDIIIZICI
I I I I I I I I
I I I I I I I I
I I I I I I I -I
I
I
I
I I
I I I I
I
I
I
I
I
I
I
I
I I
I
W65C832 E16 - W65C816 Emulation
E8 - w65C02 Emulation
Carry 1 = true
Zero 1 = result zero
IRQ- disable 1 = disable
Decimal mode 1 = true
Index Reg. Select
Memory Width Select
Overflow 1 = true
Negative 1 = neg.
Figure 1-5 W65C832 Status Register Coding
Table 1-1
W65C832 Emulation and Register Width Control
I
A and
Memory
Loads,
Stores,
Pushes,
and
Pulls
E16
E8
M
X
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
0
1
0
1
BRK
16
16
8
8
32
32
8
8
16
16
8
8
8
X,Y
Loads,
Stores,
Pushes,
Pulls,
and
Address Generation
32
8
32
8
32
8
32
8
16
8
16
8
8
W65C832
W65C832
W65C832
W65C832
W65C832
W65C832
W65C832
W65C832
W65C816
W65C816
W65C816
W65C816
W65C02
Native
Native
Native
Native
Native
Native
Native
Native
Emulation
Emulation
Emulation
Emulation
Emulation
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
MARCH 1990
9
THE WESTERN DESIGN CENTER, INC.
WOC
W65C832 SECTION 2
PIN FUNCTION DESCRIPTION
A
B
M
L
NMI­
VPA
VDD
AO
A1
VSS
A2
A3
A4
AS
A6
6
7
8
9
10
11
12
13
14
15
16
17
18
A
7
P
R
V E V M H
I
B
S S D /
Q T
A X 2
Y
E
S
4 3 2 1 44 43 42 41 40
5
39
38
37
36
35
W65C832
34
33
32
31
30
29
19 20 21 22 23 24 25 26 27 28
A A A A V V A A A A
8
1
1 1
9 1
S S 1
1
1
4 5
S S 2
3
0
I
R
0
R
Figure 2-1
MARCH 1990
R
D
V
P
E8/E16
R/W­
VDD
DO/A16
D1/A17
D2/A18
D3/A19
D4/A20
D5/A21
D6/A22
D7/A23
W65C832 44 Pin PLCC Pinout
10
WDC
THE WESTERN DESIGN CENTER, INC.
Table 2-1
Description
Address Bus
ABORT-
Abort Input
BE
PHI2(IN)
DO/A16-D7/A23
E8/El6
IRQMLM/X
NMI-
Bus Enable
Phase 2 In Clock
Data Bus/Address Bus
Emulation Select
Interrupt Request
Memory Lock
Mode Select (Pm or Px)
Non-Maskable Interrupt
Ready
Reset
Read/Write
Valid Data Address
Vector Pull
Valid Program Address
Positive Power Supply (+5 volts)
Internal Logic Ground
RESR/WVDA
VPVPA
VDD
VSS
2.1
Pin Function Table
Pin
AO-A15
ROY
W65C832
Abort (ABORT-)
The Abort input is used to abort instructions (usually due to an Address Bus
condition).
A negative transition will inhibit modification of any internal
register during the current instruction.
Upon completion of this instruction, an
interrupt sequence is initiated. The location of the aborted opcode is stored as
the return address in stack memory. The Abort vector address is 00FFF8,9 (Emulation
mode) or 00FFE8,9 (Native mode).
Note that ABORT- is a pulse-sensitive signal;
i.e., an abort will occur whenever there is a negative pulse (or level) on the
ABORT- pin during a PHI2 clock.
2.2
Address Bus (AO-A15)
These sixteen output lines form the low 16 bits of the Address Bus for memory and
I/O exchange on the Data Bus. The address lines may be set to the high impedance
state by the Bus Enable (BE) signal.
2.3
Bus Enable (BE)
The Bus Enable input signal allows external control of the Address and Data Buffers,
as well as the R/W- signal. With Bus Enable high, the R/W- and Address Buffers are
active. The Data/Address Buffers are active during the first half of every cycle
and the second half of a write cycle. When BE is low, these buffers are disabled.
Bus Enable is an asynchronous signal.
2.4
Data/Address Bus (DO/A16-D7/A23)
These eight lines multiplex address bits Al6-A23 with the data value DO-D7.
The
address is present during the first half of a memory cycle, and the data value is
read or written during the second half of the memory cycle. Four memory cycles are
required to transfer 32-bit values. These lines may be set to the high impedance
state by the Bus Enable (BE) signal.
MARCH 1990
11
WDC
2.5
THE WESTERN DESIGN CENTER, INC.
W65CS32 Emulation Status (ES/E16)
The Emulation Status output ES/E16 reflects the state of the Emulation ES and E16
mode flags in the Processor Status (P) Register. This signal may be thought of as
an opcode extension and used for memory and system management.
2.6
Interrupt Request (IRQ-)
The Interrupt Request input signal is used to request that an interrupt sequence be
initiated.
When the IRQ Disable (I) flag is cleared, a low- input logic level
initiates an interrupt sequence after the current instruction is completed.
The
Wait-for-Interrupt (WAI) instruction may be executed to ensure the interrupt will be
recognized immediately. The Interrupt Request vector address is OOFFFE,F (Emulation
mode) or OOFFEE, F (Native mode).
Since IRQ- is a level-sensitive input, an
interrupt will occur if the interrupt source was not cleared since the last
interrupt. Also, no interrupt will occur if the interrupt source is cleared prior
to interrupt recognition.
2.7
Memory Lock (ML-)
The Memory Lock output may be used to ensure the integrity of Read-Modify-Write
instructions in a multiprocessor system. Memory Lock indicates the need to defer
arbitration of the next bus cycle. Memory Lock is low during the last three, five
or nine cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory referencing
instructions, depending on the state of the M and ES flags.
2.S
Memory/Index Select Status (M/X)
This multiplexed output reflects the state of the AcctJInu-lator (M) and Index (X)
select flags (bits 5 and 4 of the Processor Status (P) Register. Flag M is valid
during the Phase 2 clock negative transition and Flag X is valid during the Phase 2
clock positive transition. These bits may be thought of as opcode extensions and
may be used for memory and system management.
2.9
Non-Maskable Interrupt (NMI-)
A negative transition on the NMI- input initiates an interrupt sequence.
A
high-to-Iow transition initiates an interrupt sequence after the current instruction
is completed. The Wait for Interrupt (WAI) instruction may be executed to ensure
that the interrupt will be recognized immediately.
The Non-Maskable Interrupt
vector address is OOFFFA,B (S-bit Emulation mode), OOFFEA,B (16-bit Emulation mode)
or OOFFDA,B (Native mode). Since NMI- is an edge-sensitive input, an interrupt will
occur if there is a negative transition while servicing a previous interrupt. Also,
no interrupt will occur if NMI- remains low.
2.10
phase 2 In (PHI2)
This is the system clock input to the microprocessor internal clock generator.
During the low power Standby Mode, PHI2 may held in the high or low state to
preserve the contents of internal registers.
However, usually it is held in the
high state.
MARCH 1990
12
WDC
2.11
THE WESTERN DESIGN CENTER, INC.
W65C832
Read/Write (R/W-)
When the R/W- output signal is in the high state, the microprocessor is reading data
from memory or I/O. When in the low state, the Data Bus contains valid data from
the microprocessor which is to be stored at the addressed memory location. The R/W­
signal may be set to the high impedance state by Bus Enable (BE).
2.12
Ready (RDY)
This bidirectional signal indicates that a Wait for Interrupt (WAI) instruction has
A low
been executed allowing the user to halt operation of the microprocessor.
input logic level will halt the microprocessor in its current state. Returning RDY
to the active high state allows the microprocessor to continue following the next
PHI2 Clock negative transition. The RDY signal is internally pulled low following
the execution of a Wait for Interrupt (WAI) instruction, and then returned to the
high state when a RES-, ABORT-I NMI- 1 or IRQ- external interrupt is provided. This
feature may be used to eliminate interrupt latency by placing the WAI instruction at
the beginning of the IRQ- servicing routine. If the IRQ- Disable flag has been set l
the next instruction will be executed when the IRQ- occurs. The processor will not
stop after a WAI instruction if RDY has been forced to a high state. However I this
feature should only be used on ASIC's and the RDY buffer modified. The Stop (STP)
instruction has no effect on RDY.
2.13
Reset (RES-)
The Reset input is used to initialize the microprocessor and start program
execution.
The Reset input buffer has hysteresis such that a simple R-C timing
circuit may be used with the internal pullup device. The RES- signal must be held
low for at least two clock cycles after VDD reaches operating voltage. Ready (RDY)
has no effect while RES- is being held low. During the Reset conditioning period l
the following period l the following processor initialization takes place:
Registers
D
DBR
PBR
0000
00
00
=
SH
XH
YH
N
V/E16
M
X
D
I
z
01
00
00
=
=
C/E8
I
P
1
*/1
1
o 1 * */1
I *
*
_______________________________________ 1
=
not
initialized
STP and WAI instructions are cleared.
Signals
E8
E16
M/X
R/WSYNC
=
=
=
=
1
1
1
1
0
VDA
VPVPA
=
0
=
1
0
When Reset is brought highl an interrupt sequence is initiated:
o R/W- remains in the high state during the stack address cycles.
o The Reset vector address is OOFFFC/D.
MARCH 1990
13
THE WESTERN DESIGN CENTER, INC.
WDC 2.14
W65C832
Valid Data Address (VDA) and Valid Program Address (VPA)
These two output signals indicate valid memory addresses when high logic 1, and are
used for memory or IIO address qualification.
VDA
o
o
VPA
0
1
1
0
1
1
2.15
Internal Operation-Address and Data Bus available. The Address Bus may be invalid. Valid program address-may be used for program cache
control. Valid data address-may be used for data cache control. Opcode fetch-may be used for program cache control and single step control
VDD and VSS
VDD is the positive supply voltage and VSS is system logic ground.
2.16
Vector Pull (VP-)
The Vector Pull output indicates that a vector location is being addressed during an
interrupt sequence.
VP- is low during the last two interrupt sequence cycles,
during which time the processor reads the interrupt vector. The VP- signal may be
used to select and prioritize interrupts from several sources by modifying the
vector addresses.
MARCH 1990
14
WDC
THE WESTERN DESIGN CENTER, INC.
W65C832
SECTION 3
ADDRESSING MODES
The W65C832 is capable of directly addressing 16 MBytes of memory for program space
and 4GBytes for data space although only 24 bits (16MBytes) of address space are
available on the standard product.
This address space has special significance
within certain addressing modes, as follows:
3.1
Reset and Interrupt Vectors
The Reset and Interrupt Vectors use the majority of the fixed addresses between
OOFFDO and OOFFFF.
3.2
Stack
The Stack may use memory from 000000 to OOFFFF. The effective address of Stack and
Stack Relative addressing modes will be always be within this range.
3.3
Direct
The Direct addressing modes are usually used to store memory registers and pointers.
The effective address generated by Direct, Direct,X and Direct,Y addressing modes is
always in Bank 0 (OOOOOO-OOFFFF).
3.4
Program Address Space
The Program Bank register is not affected by the Relative, Relative Long, Absolute,
Absolute Indirect, and Absolute Indexed Indirect addressing modes or by incrementing
the Program Counter from FFFF. The only instructions that affect the Program Bank
register are: RTI, RTL, JML, JSL, and JMP Absolute Long. Program code may exceed
64K bytes although code segments may not span bank boundaries.
3.5
Data Address Space
The Data Address space is contiguous throughout the 16 MByte address space. Words,
arrays, records, or any data structures may span 64 KByte bank boundaries with no
compromise in code efficiency.
The following addressing modes generate 24-bit
effective addresses in W65C816 Emulation mode and some, where noted by (*), generate
32-bit effective address in W65C832 native mode.
o Direct Indexed Indirect (d,x)
* Direct Indirect Indexed (d),y
o Direct Indirect (d)
o Direct Indirect Long [dl
* Direct Indirect Long Indexed [dl,y
o Absolute a
* Absolute a,x
* Absolute a,y
o Absolute Long al
* Absolute Long Indexed al,x
* Stack Relative Indirect Indexed (d,x),y
MARCH 1990
15
WDC THE WESTERN DESIGN CENTER, INC.
W65C832
The following addressing mode descriptions provide additional detail as to how
effective addresses are calculated.
Twenty-four addressing modes are available for the W65C832. The 32-bit indexed
addressing modes are used with the W65C832i however, the high byte of the address is
not available to the hardware on the standard W65C832 but is available on the core
for ASIC's. Detailed descriptions of the 24 addressing modes are as follows:
3.5.1 Immediate Addressing-f
The operand is the second byte in 8-bit mode, second and third bytes
when in the 16-bit mode, or 2nd thru 5th bytes in 32-bit mode of the
instruction.
3.5.2 Absolute-a
With Absolute addressing the second and third bytes of the instruction
form the low-order 16 bits of the effective address.
The Data Bank
Register contains the high-order 8 bits of the operand address.
Instruction:
Operand
Address:
3.5.3 Absolute 1ong-al
opcode
addrl
addrh
DBR
addrh
addrl
Instruction:
opcode
addrl
addrh
baddr I
Operand
Address:
baddr
addrh
addrl
3.5.4 Direct-d
The second byte of the instruction is added to the Direct Register (D)
to form the effective address. An additional cycle is required when the
Direct Register is not page aligned (01 not equal 0). The Bank register
is always O.
Instruction:
opcode I offset I
I Direct Register
+
I offset I
00
leffective address I
Operand
Address:
3.5.5 Accumulator-A
The
This form of addressing always uses a single byte instruction.
operand is the Accumulator.
3.5.6 Implied-i
Implied addressing uses a single byte instruction.
The operand is
implicitly defined by the instruction.
MARCH 1990
16
THE WESTERN DESIGN CENTER I INC.
VIDC W65C832
* 3.5.7 Direct Indirect Indexed-(d)/Y
This address mode is often referred to as IndirectlY' The second byte
of the instruction is added to the Direct Register (D).
The 16-bit
contents of this memory location is then combined with the Data Bank
register to form a 24-bit base address. The Y Index Register is added
to the base address to form the effective address. In native mode this
creates 32-bit effective addresses.
Instruction:
opcode I offset I 1 Direct Register +
I offset
00
I direct address then: 1 (direct address)
1
1
base address Operand
+
1
I
Y Reg Address:
I
effective address Direct Indirect Long Indexed-[d]/Y
with this addressing model the 24-bit base address is pointed to by the
sum of the second byte of the instruction and the Direct Register. The
effective address is this 24-bit base address plus the Y Index Register.
In native mode this creates 32-bit effective addresses.
1
+1
* 3.5.8
Instruction:
00
DBR
oEcode 1 offset
1 Direct
+
00
I . direct
then: 1
Register I offset address (direct address) I
base address Operand
I
1 Y Reg Address:
1
effective address Direct Indexed Indirect-(d,x)
This address mode is often referred to as Indirect, X. The second byte
of the instruction is added to the sum of the Direct Register and the X
Index Register.
The result points to the low-order 16 bits of the
effective address.
The Data Bank Register contains the high-order 8
bits of the effective address.
1
+1
I
+
3.5.9
Instruction:
oEcode 1 offset 1 I Direct Register +
I offset I direct address +1
1 X Reg
00
address I
then: 1
Operand
Address:
MARCH 1990
DBR
+1
I
00
1
(address) DBR
1
effective address 17
WOC THE WESTERN DESIGN CENTER, INC.
W65C832
3.5.10 Direct Indexed With X-d,x
The second byte of the instruction is added to the sum of the Direct
Register and the X Index Register to form the 16-bit effective address.
The operand is always in Bank O.
Instruction:
opcode 1 offset 1
1 Direct Register
+
1 offset
1 direct address
Operand
+1
1 X Reg 1
Address:
1
00
leffective address 1
3.5.11 Direct Indexed With Y-d,y
The second byte of the instruction is added to the sum of the Direct
Register and the Y Index Register to form the 16-bit effective address.
The operand is always in Bank O.
Instruction:
opcode 1 offset I
I Direct Register
+
I offset
1 direct address
Operand
+1
1
Y Reg 1
Address:
1
00
leffective address 1
* 3.5.12 Absolute Indexed With X-a,x
The second and third bytes of the instruction are added to the X Index
Register to form the low-order 16-bits of the effective address.
The
Data Bank Register contains the high-order 8 bits of the effective
address. In native mode this creates 32-bit effective addresses.
opcode r addrl I addrh
DBR I addrh 1 addrl Operand
+1
1 X Reg Address:
1
effective address * 3.5.13 Absolute Long Indexed With X-al,x
The second, third and fourth bytes of the instruction form a 24-bit base
address.
The effective address is the sum of this 24-bit address and
the X Index Register.
In native mode this creates 32-bit effective
addresses.
Instruction:
Instruction:
opcode I addrl 1 addrh
baddr 1
baddr 1 addrh I addrl Operand
+I
I X Reg Address:
1
effective address
* 3.5.14 Absolute Indexed With Y-a,y
The second and third bytes of the instruction are added to the Y Index
Register to form the low-order 16 bits of the effective address. The
Data Bank Register contains the high-order 8 bits of the effective
address. In native mode this creates 32-bit effective addresses.
Instruction:
Operand
Address:
MARCH 1990
opcode 1 addrl
DBR I addrh
addrh
addrl +1
1 Y Reg effective address 1
1
18
THE WESTERN DESIGN CENTER, INC.
WDC W65C832 3.5.15 Program Counter Relative-r
This address mode, referred to as Relative Addressing, is used only with
the Branch instructions.
If the condition being tested is met, the
second byte of the instruction is added to the Program Counter, which
has been updated to point to the opcode of the next instruction. The
offset is a signed a-bit quantity in the range from -128 to 127. The
Program Bank Register is not affected.
3.5.16 Program Counter Relative Long-rl
This address mode, referred to as Relative Long Addressing, is usd only
with the Unconditional Branch Long instruction (BRL) and the Push
Effective Relative instruction (PER). The second and third bytes of the
instruction are added to the Program Counter, which has been updated to
point to the opcode of the next instruction.
With the branch
instruction, the Program Counter is loaded with the result. With the
Push Effective Relative instruction, the result is stored on the stack.
The offset is a signed 16-bit quantity in the range from -32768 to
32767. The Program Bank Register is not affected.
3.5.17 Absolute Indirect-{a)
The second and third bytes of the instruction form an address to a
pointer in Bank O.
The Program Counter is loaded with the first and
second bytes at this pointer. With the Jump Long (JML) instruction, the
Program Bank Register is loaded with the third byte of the pointer.
Instruction: 1 opcode 1 addrl 1 addrh 1
Indirect Address = 1 00 I addrh I addrl
New PC = (indirect address)
with JML:
New PC = (indirect address)
New PBR = (indirect address +2)
3.5.18 Direct Indirect-(d)
The second byte of the instruction is added to the Direct Register to
form a pointer to the low-order 16 bits of the effective address. The
Data Bank Register contains the high-order 8 bits of the effective
address.
Instruction:
then:
opcode 1 offset I
I Direct Register
+
1 offset
00
I direct address
I
00
I (direct address)
Operand
+1 DBR
1
Address:
I ----~~~----~-------effective address
3.5.19 Direct Indirect Long-[d]
The second byte of the instruction is added to the Direct Register to
form a pointer to the 24-bit effective address.
Instruction:
then:
Operand
Address:
MARCH 1990
opcode I offset I
I Direct Register
+
I offset
00
I direct address
(direct address)
19
WDC THE WESTERN DESIGN CENTER, INC.
W65C832 3.5.20 Absolute Indexed Indirect-(a,x)
The second and third bytes of the instruction are added to the X Index
Register to form a 16-::bit pointer in Bank O.
The contents of this
pointer are loaded in the Program Counter. The Program Bank Register is
not changed.
Instruction:
opcode
PBR
addrl I addrh addrh I addrl I X Reg address then: PC = (address) 3.5.21 Stack-s
Stack addressing refers to all instructions that push or pull data from
the stack, such as Push, Pull, Jump to Subroutine, Return from
Subroutine, Interrupts, and Return from Interrupt. The bank address is
always O. Interrupt Vectors are always fetched from Bank O.
3.5.22 Stack Relative-d,s
The low-order 16 bits of the effective address is formed from the sum of
the second byte of the instruction and the stack pointer.
The
high-order 8 bits of the effective address is always zero. The relative
offset is an unsigned 8-bit quantity in the range of 0 to 255.
opcode I offset I
I Stack Pointer
Operand
+
I offset I
Address:
I
00
leffective address I
* 3.5.23 Stack Relative Indirect Indexed-(d,s),y
The second byte of the instruction is added to the Stack Pointer to form
a pointer to the low-order 16-bit base address in Bank O. The Data Bank
Register contains the high-order 8 bits of the base address.
The
effective address is the sum of the 24-bit base address and the Y Index
Register. In the native mode this creates 32-bit effective addresses.
Instruction:
opcode I offset
1 Stack
+
00
I
S +
Instruction:
I
Pointer I offset
offset
then:
Operand
Address:
MARCH 1990
+1
I
+
I
I
S + offset
I
base address
I
I Y Reg
effective address
DBR
20
WDC THE WESTERN DESIGN CENTER, INC.
W65C832 3.5.24 Block Source Bank, Destination Bank-xya
This addressing mode is used by the Block Move instructions. The second
byte of the instruction contains the high-order 8 bits of the
destination address.
The Y Index Register contains the low-order 16
bits of the destination address.
The third byte of the instruction
contains the high-order 8 bits of the source address.
The X Index
Register contains the low-order bits of the source address.
The
Accumulator contains one less than the number of bytes to move. When
the Accumulator is zero it will move one byte. The second byte of the
block move instructions is also loaded into the Data Bank Register. In
W65C832 native mode this X Index Register contains the entire source
address and the X Index Register contains the entire destination
address; therefore, the instruction is shorter by two bytes and two
cycles per byte moved.
Instruction: I opcode
dstbnk I srcbnk I
Source dstbnk -> DBR
srcbnk I
Address: X Reg
DBR I
Destination Y Reg
Address:
Increment (MVN) or decrement (MVP) X and Y.
Decrement C (if greater than zero), then PC+3->PC.
*
In W65C832 native mode these addressing modes creates 32-bit effective data
space addresses.
MARCH 1990
21
WDC
THE WESTERN DESIGN CENTER 1 INC.
Table 3-1
Addressing Mode
Immediate
Absolute
Absolute Long
Direct Page
Accumulator
Implied Addressing
Direct Indirect
Indexed
Direct Indirect
Indexed Long
Direct Indexed
Indirect
Direct Indexed by X
Direct Indexed by Y
Absolute Indexed by X
Note:
MARCH 1990
Address Mode Formats
Format
#d
#a
tal
#EXT
#<d
#<a
#<al
#<EXT
#>d
:/f>a
:/f>al
:/f>EXT
:/f"d
#Aa
:/fAal
:/fAEXT
!d
!a
a
!al
!EXT
EXT
>d
>a
>al
al
>EXT
d
<d
<a
<al
<EXT
Addressing Mode
Absolute Indexed by Y
Format
!d,y
d,y
a,y
!a y
!ai,y
!EXT,y
EXT,y
>d,x
Absolute Long Indexed
>a x
by X
>ai,x
al,x
>EXT,x
Program Counter Relative d
and Program Counter
a
al
Relative Long
(EXT)
(d)
Absolute Indirect
(! d)
(a) (! a)
( tal)
Direct Indirect
Direct Indirect Long
Absolute Indexed
A
l~~l)~y
[d] , y
~~l:~
<a 1 y
<EXTi,y
(d, x)
«d,x)
«ai, x)
«EXT, x)
d,x
<d,x
<a x
<ai,x
<EXT, x
d,y
<d,y
<a y
<ai,y
<EXT,y
d,x
!d,x
a,x
!a x
!ai,x
!EXT,x
EXT,x
«a x)
«a)
«al)
«EXT)
~gll
[>a ]
[>EXT]
(d, x)
( ! d, x)
(!a,x)
(! aI, x)
~~~~~y
«EXT),y
(EXT)
(d)
(a, x)
(no operand)
~
W65C832
Stack Addressing
Stack Relative
Indirect Indexed
(EXT, x)
(!EXT,x)
(no
oQerand)
(a,s),y
«d,s),y «a, s) ,y
«al, s) y
Block Move
«EXT, s), y
d,d
d,a
d,al
d,EXT
a,d
a,a
a,al
aiEXT
a ,d
al,a
al,al
al,EXT
EXT,d
EXT, a
EXTral
EXT,EXT
The alternate ! (exclamation point) is used in place of the
I (vertical bar) .
22
WOC THE WESTERN DESIGN CENTER, INC.
Table 3-2
Address Mode
l.
2.
3.
4.
5.
6.
7.
8.
I
I 9.
I
110.
Ill.
112.
113.
114.
115.
116.
117.
118.
119.
120.
1
12l.
122.
123.
I
124.
I
I
Immediate Absolute Absolute Long Direct Accumulator Implied Direct Indirect Indexed
(d) , y Direct Indirect Indexed
Long (d],y
Direct Indexed Indirect
(d, x)
Direct,X
Direct,Y
Absolute, X Absolute Long,X Absolute,Y Relative Relative LonSl Absolute Indirect (Jump)
Direct Indirect Direct Indirect Long Absolute Indexed Indirect
(Jump)
Stack
Stack Relative Stack Relative Indirect
Indexed
Block Move X,Y,C (Source,
Destination, Block
w65C832
Addressing Mode Summary
I Instruction Times IMemory Utilization I
lIn Number of Program I
I In Memory Cycles
Sequence Bytes
I
I
I Original I New
I Original I New
18-bit NMOS I W65C832 18-bit NMOS I W65C832
6502
6502
I
I
2 (3)
2 (3) I
2
2
I
4 (5)
4 (3,5) I
3
3
I
5 (3) I
4
I
3 (5)
3(3,4,5)1
2
2
I
2
1
1
2
I
I
2
1
1
2
I
I
5 (1)
5(1,3,4) I
2
2
I
I
I
2
6(3,4) I
I
I
I
6(3,4) I
2
2
6
I
1
I
4 (5)
4(3,4,5) I
2
2
I
4 (3, 4) I
2
4
2
I
4(1,5)
4(1,3,5)1
3
3
I
5 (3) I
4
I
4 (1)
4(1,3) 1
3
3
I
2(1,2)
2(2) 1
2
2
1
3(2) I
3
1
5
5
3
3
I
I
5(3,4) I
2
I
6(3,4) I
2
1
6
3
I
I
I
1
3-7
3-11 I
1-3
1-4
I
4 (3) I
2
I
7 (3) I
2
I
I
I
7 (6) I
3 (6)
I
I
I
Notes (these are indicated in parentheses) :
1. Page boundary, add 1 cycle if page boundary is crossed when forming
address.
2. Branch taken, add 1 cycle if branch is taken.
3. 16 bit operation, add 1 cycle, add 1 byte for immediate.
32 bit operation, add 3 cycles, add 3 bytes for immediate.
4. Direct register low (DL) not equal zero, add 1 cycle.
5. Read-Modify-Write, add 2 cycles for 8-bit, add 4 cycles for 16-bit, add 8
cycles for 32-bit operation.
6. For W6SC832 native mode, subtract 2 cycles and 2 bytes.
MARCH 1990
23
, WOC THE WESTERN DESIGN CENTER, INC.
w65C832
SECTION 4
TIMING, AC AND DC CHARACTERISTICS
4.1
Absolute Maximum Ratings:
(Note 1)
Table 4-1
Absolute Maximum Ratings
Rating
Symbol 1
Value
_____________________ ------_1--------------­
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
VDD
VIN
TA
TS
1
1 -0.3 to +7.0V
1-0.3 to VDD +0.3V
1 0 OC to +70 oC
1
1
-55 0 C to +150 oC 1
________________ I 1
This device contains input protection against damage due to high static voltages or
electric fields; however, precautions should be taken to avoid application of
voltages higher than the maximum rating.
Notes:
1. Exceeding these ratings may result in permanent damage.
Functional operation under these conditions is not implied.
MARCH 1990
24
WDC
4.2
DC Characteristics:
THE WESTERN DESIGN CENTER, INC.
W65C832
VDD = 5.0V +/- 5%,
VSS = OV,
TA = OoC to +70oC
Table 4-2
DC Characteristics
I
Parameter
'Symbol' Min , Max ,Unit'
,Input High Voltage
,Vih , - - , - - , -,
I RES-, RDY, IRQ-, Data, BE
I ' 2.0 IVDD+0.3' V
,
, PHI2, NMI-, ABORTI
10.9*VDDIVDD+0.31 V I
I
,
I
I
I
[Input Low Voltage
I Vil
I
I
I
RES-, RDY, IRQ-, Data, BE
I ' -0.3
I
0.8 , V I
I
I PHI2, NMI-, ABORTI ' -0.3 10.1*VDD, V I
,
,
I
I
[
I
,Input Leakage Current (Vin = 0.4 to 2.4) I lin [
I
I
I
I RES-, NMI-, IRQ-, BE, ABORT"
-100'
1
I uA I
,
(Internal Pullup)
I'
I
I
,
I RDY (Internal Pullup, Open Drain)
I
,-100 I 10.. , uA ,
,lin , -1
,
1
, uA ,
, PHI2
I Address, Data, R/W-, (Off State, BE=O) I
,-10 I 10
, uA ,
I
I
,
,
,_ _
IOutput High Voltage (Ioh=-100uA)
I Voh,
,
,
, Data,Address,R/W-,ML-,VP-,M/X,E8/E16'
,
I
,
, VDA, VPA
I
'0.7 VDD I
'V
I
I
,
,
,_ _
[Output Low Voltage (101 = 1.6rnA)
,Vol,
,
,
, Data,Address,R/W-,ML-,VP-,M/X,E8/E16 I
,
,
,
I VDA,VPA
I
[
[0.4 [ V
,
I
,
[
[
[
'Supply Current (No Load)
' [ '
[rnA/MHz [
,
I
,
,
,
,
,Standby Current (No Load, Data Bus = VSSI Isb,
I
I
,
I orVDD
I
,
,
,
,
, RES-,NMI-,IRQ-,SO-,BE,ABORT-,PHI2=VDD),
,
I 1
I uA ,
I
I
,
[
I
I
'Capacitance (Vin=OV, TA=250C, f=2MHz),
I
,
,
[
I Cin,
, 1 0 , pF I
I Logic,PHI2
I Address, Data, R/W-(Off State)
I Cts'
I 15
I pF I
,
,
,
I
[
[
MARCH 1990
25
THE WESTERN DESIGN CENTER, INC.
WOC 4.3 General AC Characteristics:
VDD= 5.0V +/- 5%, VSS=
Ta= OoC to +70oC
W65C832
ov,
Table 4-3A W65C832 General AC Characteristics, 4-7MHz
I
I
I 4 MHz I 5 MHz I 6 MHz I 7 MHz I
I
Parameter
ISymbo~IMin MaxlMinlMaxlMin Maxi MiniMax IUnit
ICycle Time
1 tCYC 1250 DC 1200lDC 1165 DC 1140 DC 1 nS
IClock Pulse Width Low
I tPWL .125 10 1.10110 .082 10 1.07 10 I uS
IClock Pulse Width High
I tPWH 1125
11001 - 182
170
- I nS
IFall Time! Rise Time
ItF,tR I - 10 I - 110 I 5 I 5 I nS
IAO-A15 Hold Time
I tAH 110
- 110 I - 110
- 110
- I nS
IAO-A15 Setup Time
I tADS I - 75 I - 167 I - 60 I - 60 I nS
IA16-A23 Hold Time
I tBH 110
- 110 I - 110
- 110
- 1 nS
IA16-A23 Setup Time
I tBAS 1 - 90 I - 177 I - 65 I - 55 I nS
IAccess Time
I tACC 1130 - 11151 - 187
- 160
- I nS
IRead Data Hold Time
I tDHR 110
- 110 I - 110
- 110
- I nS
IRead Data Setup Time
1 tDSR 130
- 125 I - 120
- 125
- I nS
IWrite Data Delay Time
1 tMDS I - 70 I - 165 1 - 160 I - 55 I nS
IWrite Data Hold Time
I tDHW 110
- 110 I - 110 1 - 110 I - I nS
IProcessor Control Setup Time 1 tPCS 130 I - 125 I - 120 1 - 120 I - I nS
IProcessor Control Hold Time I tPCH 110 I - 110 I - 110 I - 110 I - I nS
IE8/E16!MX Output Hold Time I tEH 110 I - 110 I - I 5 I - I 5 I - I nS
IE8/E16!MX Output Setup Time 1 tES 150 1 - 137 I - 125 I - 125 I - I nS
ICapacitive Load *1
1 CEXT I - 11001 - 11001 - 135 I - 135 1 pF
IBE to Valid Data *2
I tBVD I - 130 I - 130 1 - 130 I - 130 I nS
Table 4-3B
W65C832 General AC Characteristics, 8-10MHz
Parameter
C:icle Time
Clock Pulse Width Low
Clock Pulse width High
Fall Time, Rise Time
AO-A15 Hold Time
AO-A15 SetuE Time
A16-A23 Hold Time
A16-A23 Setup Time
Access Time
Read Data Hold Time
Read Data SetuE Time
Write Data Dela:i Time
Write Data Hold Time
Processor Control Setup Time
Processor Control Hold Time
ES/E16!MX Output Hold Time
ES/E16,MX Output SetuE Time
CaEacitive Load *1
BE to Valid Data
*1
*2
I tCYC
I tPWL
I tPWH
ItF,tR
1 tAH
I tADS
I tBH
I tBAS
I tACC
I tDHR
I tDSR
I tMDS
I tDHW
I tPCS
I tPCH
I tEH
I tES
I CEXT
I tBVD
162
I 110
I 110
I 170
110
115
I 110
115
110
I 5
115
I I -
I I 5
I 140
I 145
I I -
1140
I I
-
I
I
-
I
-
135
130
I 9 MHz 110 MHz I
I
IMinlMaxlMinlMaxlUnitl
nS
1110 DC 1100lDC
.055 10 1.05110
uS
- 50 I - nS
55
5
5 nS
- 10
10
nS
- 40 - 40 nS
- 10 - nS
10
- 45 - 45 nS
70
- 70 - nS
10
- 10 - nS
15
- 15 - nS
- 40 - 40 nS
10
- 10 - nS
15
- 15 - nS
10
- 10 - nS
5 I nS
5
15 I - 15
- nS
pF
- 135 I - 35
nS
- 130 I - 30
Applies to Address! Data, R/W
BE to High Impedence State is not testable but should be the same amount of time
as BE to Valid Data
MARCH 1990
26
WDC THE WESTERN DESIGN CENTER, INC.
4.4 General AC Characteristics:
W65C832
VDD= 1.2V, VSS= OV,
Ta= OoC to +70oC
Table 4-4A W65C832 General AC Characteristics, 40 KHz
I
I
I 40 KHz I
I
I
Parameter
ISymbollMin IMaxlUnit/
ICycle Time
/ tCYC 1 ­ 125 I uS
IClock Pulse Width Low
I tPWL 112.5113 I uS
IClock Pulse Width High
I tPWH 112.51 - I uS
IFal1 Time, Rise Time
ItF,tR I - 110 1 nS
IAO-A15 Hold Time
I tAR 110 I - I nS
IAO-A15 Setup Time
I tAOS I - I 2 I uS
IAAO-A23 Hold Time
I tBH 110 I - I nS
IA16-A23 Setup Time
I tBAS 1 - 1 2 I uS
IAccess Time
I tACC 135 , - , uS
'Read Data Hold Time
I tDRR 1100 I - 1 nS
IRead Data Setup Time
I tDSR 11.5 I - I uS
IWrite Data Delay Time
I tMDS , ­
I 2 I uS
IWrite Data Hold Time
I tDRW 110 I - I nS
IProcessor Control Setup Time I tPCS 11.5 I - I uS
jProcessor Control Hold Time I tPCH 1100 I - I nS
IES/E16,MX Output Hold Time I tEH 110 I - 1 nS
IE8/E16,MX Output Setup Time I tES 1100 I - I nS
ICapacitive Load *1
1 CEXT I - 11001 pF
IBE to Valid Data *2
1 tBVD I 130 1 nS
*1
*2
Applied to Address, Data, R/W
BE to High Impedance State is not testable but should be the same amount of time
as BE to Valid Data
MARCH 1990
27
THE WESTERN DESIGN CENTER, INC.
WOC W65CS32
1<----------------tCYC2----------------> , ,<--tF
PHI 2_ _ _."
,
II
I
1\
/
\1
1\
/
tF-> II <------tPWL------>, <------tPWH------> 1 ' - - - - ­
tAH-> , ,<->, <tR
->1
1<-tAH
I
,
,
R/W-,ML-,VP----,
\
/
AO-A15,VDA,VPA ,/--\
I <----tADS----> I <--- -----tACC-----> I
I
Read D a t a , - - - I - \ / - - \ / A16-A23
A16-A23
I /\
/\
tDHR-> I-I <--I <-tBAS--> I
->
/
/\
I <-tBH
1
1-\/
1 /\
I <-tD'"""SR:----­
I
\/-,-\/
/ \ , /\
-> I-I <·--t:-::D=H=-R­
->1
'<-tDSR
,
I
Write Data,---,-\/--\/A16-A23
- \ / - \ / Write Data\
A16-A23
,/\
/\
/\
/\
1 /\
tDHW-> I-I <---> I
,<-tMDS--> I '<·-'-t:-::D=H=W­
,
I
tPCS->,
,<­
,
,
IRQ-,NMI-,RES-,---,
I
/-,-\/ ,
,
\
I
,
,
ROY
\
I
,
/\ 1/
/
\_, tPCS-> I
,
- > - , <--:-t-=P=CH:::--­
I
,<­
1
M/X ---
->
:M\/
_/\
1<-tEH
I
,
ES/E16
\/X-,:x\/
\/M: :M\/
/\ I /\_ _ _ _/\
/\
- - - - - 1-'-1
-> - I <--t-=E=H-­
1->1
1<-tEH
tES->1
1<-1
,
1
->1
I
ES\/-----:-\/E16-\/
/\
/\_,_/\
I
<-tES
I
I
1
\/E81-\/
/\_,_/\_-­
Timing Notes:
1.
2.
Voltage levels are Vl<O.4V, Vh>2.4V.
Timing measurement points are 0.8V and 2.0v.
Figure 4-1 General Timing Diagram
MARCH 1990
28
WDC W65C832 THE WESTERN DESIGN CENTER, INC.
SECTION 5
ORDERING INFORMATION
65C832
I
W-Standard
I
I
_P_r_od_u_c_t__I_d_e_n_t_i_f_i_c_a_t_i_o_n__N_umbe_r
__ _________ I
W
=D~e7sc~r~1~'p~t~1~'o7n~___________________ 1
PL
I
I
I
I
I
-8
~p~ac~k7a~g~e~~~~~~__7 0_ _ _ _ _ _. -_ _ _ _ _ _ _ _ _ 1
PL-44 leaded plastic chip carrier
Temperature/Processing
Blank- OoC to +70oC
Performance Designator
Designators selected for speed and power. -4 4MHz -6 6MHz -8 8MHz -10 10MHz -E Experimental General sales or technical assistance, and information about devices supplied to a
custom specification may be requested from:
The Western Design Center, Inc. 2166 East Brown Road Mesa, Arizona 85213 Phone: 602-962-4545
Fax: 602-835-6442
WARNING:
MOS CIRCUITS ARE SUBJECT TO DAMAGE FROM STATIC DISCHARGE
Internal static discharge circuits are provided to minimize part damage due to
environmental
static
electrical
charge
build-ups.
Industry
established
recommendations for handling MOS circuits include:
1. Ship and store product in conductive shipping tubes or conductive foam plastic.
Never ship or store product in non-conductive plastic containers or
non-conductive plastic foam material.
2. Handle MOS parts only at conductive work stations.
3. Ground all assembly and repair tools.
MARCH 1990
29
THE WESTERN DESIGN CENTER, INC.
WDC
w65C832
SECTION 6
APPLICATION INFORMATION Table 6-1
w65C832 Instruction Set-Alphabetical Sequence ADC
Add Memory to Accumulator with
AND
ASL
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
"AND Memor¥ with Accumulator
Shift One B~t
Branch on Carry Clear (Pc=O)
Branch on Carry Set (Pc=l)
Branch if Equal (Pz=l)
Bit Test
Branch if Result Minus (Pn=l)
Branch if Not Equal (Pz=O)
Branch if Result Plus (Pn=O)
Branch Always
Force Break
Branch Always Long
Branch on Overflow Clear (Pv=O)
Branch on Overflow Set (Pv=l)
Clear Carry Flag
Clear Decimal Mode
Clear Interrupt Disable Bit
Clear Overflow Flag
Compare Memory and Accumulator
Coprocessor
Compare Memory and Index X
Compare Memory and Index Y
Decrement Memory or Accumulator
by One
Decrement Index X by One
Decrement Index Y by One
"Exclusive OR" Memory with
Accumulator
Increment Memory or Accumulator
by One
Increment Index X by One
Increment Index Y by One
Jump Long
Jump to New Location
Jump Subroutine Long
Jump' to New Location Saving Return
Loaa Accumulator with Memory
Load Index X with Memory
Load Index Y with Memory
Shift One Bit Right (Memory or
Accumulator)
Block Move Negative
Block Move Positive
No Operation
"OR" Memory with Accumulator
Push Effective Absolute Address
on Stack
Push Effective Absolute Address
on stack
Push Effective Program Counter
Relative Address on Stack
BRA
BRK
BRL
BVC
BVS
CLC
CLD
CLI
CLV
CMF
COP
CPX
CPY
DEC DEX DEY
EOR
INC
INX
INY
JML
JMP
JSL
JSR
LDA
LDX
LDY
LSR
MVN
MVP
NOP
ORA
PEA
PEl
PER
Carr~
PHA
PHB
PHD
PHK
PHP
PHX
PHY
PLA
PLB
PLD
PLP
PLX
PLY
REP
ROL
ROR
RTI
RTL
RTS
SBC
SEP
STA
STP
STX
STY
STZ
TAX
TAY
TCD
TCS
TDC
TRB
TSB
TSC
TSX
TXA
TXS
TXY
TYA
TYX
WAI
WDM
XBA
XCE
XFE
Push Accumulator on Stack
Push Data Bank Register on Stack
Push Direct Register on Stack
Push Program Bank Register on
Stack
Push Processor Status on Stack
Push Index X on Stack
Push Index Y on Stack
Pull Accumulator from Stack
Pull Data Bank Register from
Pull Direct Register from Stack
Pull Processor Status from Stack
Pull Index X from Stack
Pull Index Y from Stack
Reset Status Bits
Rotate One Bit Left (Memory or
Accumulator)
Rotate One Bit Right (Memory or
Accumulator)
Return from Interrupt
Return from Subrout~ne Long
Return from Subroutine
Subtract Memory from Accumulator
with Borrow
Set Processor Status Bite
Store Accumulator In Memory
Stop the Clock
Store Index X in Memory
Store Index Y in Memory
Store Zero in Memory
Transfer Accumulator to Index X
Transfer Accumulator to Index Y
Transfer C Accumulator to Direct
Register
Transfer C Accumulator to Stack
Pointer Register
Transfer D~rect Register to C
Accumulator
Test and Reset Bit
Test and Set Bit
Transfer Stack Pointer Register
to C Accumulator
Transfer Stack Pointer Register
to Index X
Transfer Index X to Accumulator
Transfer Index X to Stack
Pointer Register
Transfer Index X to Index Y
Transfer Index Y to Accumulator
Transfer Index Y to Index X
Wait for Interrupt
Reserved for Future Use
Exchange B and A Accumulator
Exchange Carry and Emulation E8
Exchange Carry and Emulation E8
and Exchange Overflow and
Emulation E16
For alternate mnemonics, see Table 7-3-1.
MARCH 1990
30
WDC
THE WESTERN DESIGN CENTER, INC.
Table 6-2
W6SC02 8- Emulation
OOFFFE,F-IRQ-/BRK
Hardware/Software
Hardware
Hardware
Hardware
OOFFFC,D-RESETOOFFFA,C-NMIOOFFF8,9-ABORTOOFFF6,7-(Reserved)
OOFFF4,S-COP
Software
W65C832
Vector Locations
W6SC816 16-bit Emulation
OOFFEE,F-IRQ- Hardware
OOFFEC,D-(Reserved)
OOFFEA,B-NMI- Hardware
OOFFE8,9-ABORT-Hardware
OOFFE6,7-BRK Software
OOFFE4,5-COP
Software
W6SC832 Native
OOFFDE,F-IRQHardware
OOFFDC,D-(Reserved)
OOFFDA,B-NMIHardware
OOFFD8,9-ABORTHardware
OOFFD6,7-BRK
Software
OOFFD4,S-COP
Software
The VP output is low during the two cycles used
for vector location access. When an interrupt
is executed, D=O and 1=1 in Status Register P.
MARCH 1990
31
W65C832 THE WESTERN DESIGN CENTER, INC.
WDC
Table 6-3
Opcode Matrix -~--
I~
M
S
LSD
0
C
0
E
F
ASLA PHDs
1 2 1* 4
TSBa
3-6
ORAa
3 4
ASLa
3 6
ORAal
4 *5
0
CLCi ORAa.y INCA TCSi
1-2 1*2
1 2
3 4
TRBa
3-6
ORAa.x ASL a.x ORAal.
4*5
3 4
3 7
1
AND[d]
2* 6
PLPs
1 4
BIT a
3 4
ANDJdl.y
2 6
SECi
1 2
EOR [dl
2*6
PHAs
1 3
1
2
3
4
5
6
7
8
9
BRKs
0
2 8
ORA (d.x)
2 6
COPs
2*8
ORAd.s
2*4
TSBd
2-5
ORAd
2 3
ASLd
2 5
ORA[d]
2*6
PHPs
•1 3
ORA II
2 2
1 BPL r
I 2 2
ORA (d).Y ORA (d) ORA~d.S).Y
2 7
2 5
i 2 - 5
TRBd
2-5
.JS"l a
3 6
AND (d,xl
2 6
BITd
2 3
8MI r
AND (d).y
2 5
0
-­
2
-.­
3
2 2
-­
JSL al
4 *8
---_.
AND n.s
2*4
AND (d) AND td.sl.y
2-5
f--.­
W~M
2
7
MVP xyc
3*7
RTI s
1 7
EOR (d.x)
2 6
BVe r
2 2
EOR (d).y
6
RTS s
1 6
ADC (d,x)
2 6
7
BVS r
2 2
ADC (d),y
2 5
8
BRAr
2-2
STA (d.x)
2 6
BRL rl
3*3
STAd.s
2*4
STYd
2 3
9
BCCr
2 2
STA (d).y
2 6
STA (d)
2-5
STA ~.s}.y
2 7
STY d.x
2 4
A
LOY II
2 2
LDA (d,x)
2 6
LDX 1/
2 2
LDA d.s
2*4
LOYd
2 3
B
8GS r
2 2
LOA (d).y
2 5
.\
---- --­
5
2 5
--­ ,---­
r-
.c'
--.,-.--­
CPY
~
2
--_._­
~
.. ­
IIE I"~?~ __._._, -­
0
CP;( II
I:~EQ~
,
,L_ i
ROLd
2 5
-­
!ANDd.X ROL d.x
2
6
2
4
---­
EORd
2 3
'-­
LSRd
2 5
EOn (til EOR ~d$).y MVN xyc EOR d.x LSR d.x EOR [d].y
2 -5 _. 2 7
3*7
2 -I
2*6
.. 2 6
PER 5
3*6
ADCd.S
2*4
STZd
2-3
LOA (01) LOA ~d,S).y
2-5
2 7
ROAd
2 5
ADC [dJ
2 *6
REP #
2*3
-.--~-
eMP (1.5
2*4
C:I'Y d
,23
-----1-­
SSC «I) SOC ~d,s).y
2-5
2 7
PEA s
3*5
-----­
2
'--------­
PEl $
2* 6
3
symbol
#
A
r
rl
i
s
d
d,x
cI,y
(d)
(tl,x)
(d).y
STAd
2 3
STXd
2 3
CLI i
1 2
AND II
2 2
ROLA PLDs
1 2 1 *5
ANDa:y DEC A TSC i
1 -2 1 * 2
3 4
--.- f--.
EORn
2 2
ANDa
3 4
BIT a.x
3 -4
LSRA PHKs
1 2 1*3
JMPa
EOR a.y PHYs TCDi
1-3 1 *2
3 4
JMPal
4*4
4
PLAs
1 4
SEIi
1 2
AOcn
2 2
3 3
DEYi
1 2
BIT II
2-2
STAJdl.y
2 6
TYAi
1 2
STA a.y
3 5
LOA [dl
2*6
TAYi
1 2
LOA II
2 2
LDAJdJ,v
2 6
CLVi
1 2
l.DA a.y
3 4
LO~
LOXd
2
2 3
RORA RTL 5
1 2 1*6
,..."_
SBCd
2 3
SBC d.x l!-led.x
2 6
2 4
INXi
1 2
SBC #
2 2
SBC IdLy
2 *6
seol
SBCa,y
3 4
7
8
6
5
2
STAa.x
3 5
TAXi PLBs
1 2 1*4
LOY a
3 4
LDAa
3 4
LDYa.x
3 4
LOA a,X
3 4
TSXi
2
TYX i
1* 2
CPVa
:; 4
RORa
3 6
9
,
NOPi XBAi
2 1*3
CPX a
3 4
PLX S XCEi JSR (a,~)
3*6
, - 4 1*2
B
A
STXa
3 4
LDXa
3 4
(d]
[d],y
a
direct indirect long
diwct indirect long indexed
absolule
absolute indexed (with x)
absolule indexed (wilh V)
absolute long
absolute long indexed
stack relati",
stack relative indirect indexed
absolute indirect
absolute indeXed indirect
block move
C
CMPa
3 4
DECa
3
MARCH 1990
• = New W65C02 Opcodes
Blank = NMOS 6502 Opcodes
LOAal
4*5
CMPal
5
7
8
9
A
B
4
*5
-- c--'
SBCa
:\ 4
SSC a,x
3 4
0
INCa
3 6
SBCal
4*5
INC a,X SBC al,x
4*5
3 7
E
AC'DRESSING
MODE
BASE NO, CYCLES 32
C
-.--­
CMPa,x DECa,x eMP al,>
3 4
:3 7
4*5
Op Code Matrix Legend
BASE
NO, BYTES
STA al
4*5
LOX a.y LDAal,x
4*5
3 4
------
* = New W65C816/802 OpcQdes
4
AOCal! 6
4 *5 i
STZa.x STAal.x
3-5
4*5
-- '---­ ,,--­ - -"­
JML la)
3*6
immediate
accumulator
prO'l'am ('ou"t~r relatiYe
prograr., COunler relative long
unpiled
stack
direct
direct indexed (with x)
direct indexed (with V)
direct indirect
direct indexed indirect
direct indirect indexed
!INSTRUCTION
MNEMONIC
EORal
4*5
f--'
addressing mode
xyc
ADCa
3 4
STZa
3-4
symbol
a,y
al
al,x
d,S
(d,s).y
(a)
(a,x)
LSR a
3 6
EOR a,x LSR a.x EOR al..
3 4
4*5
3 7
TXYi
1 *2
TXS i
1 2
addressing mode
a.x
:1
STAa
3 4
-_.1
SBC [dJ
2 * 6
1
ANDa.x ROLa.x ANDal.
4 *5
3 4
3 7
STY a
3 4
~~-----
INCd
2 5
2
TXA i PHBs
1 2 1* 3
CMP[dj
INY i
CMP~
DECd
DEX i WAil
2 *6
1 2 1- 3
1 2
2 2
2 5
..­
f---- - ' - - ­
eMP d,x DECd,x CMP[qi,y CLO i CMPa,y PHXs STP i
2*6
2 4
2 6
1 2
3 4
1 - 3 1-3
CMP<l
2 3
JMP (a)
3 5
ANOal
4*5
EORa
:.I 4
ROLa
3 6
ADCa.y PLYs TDCi JMP (a.x) ADCa.x ROR a.x ADCal.
3-6
4*5
3 4
3 4
3 7
1- 4 1* 2
STA [d]
2*6
STAd.x STX d.y
2 4
2 4
LOYd.x LDAd,x LOX d' 1
2 4
2 4
:1 4
CPXd
2 3
2
AOCd
2 3
ADC(d) ADC ~d.S).y STZd.x ADC d.x RCR d.x ADC IdLy
2-4
2-5
2 7
2 *6
2 4
2 6
CMP IdLy CMP(d) CMP t<1.S),y
2-5
:1 7
. 2 5
r---"---­
SEP :I
SBC d,S
SSC l<l,x)
2 f)
2*4
2*:3
SBC (dLy
2 5
'--_.­
-0­
1
;~
2*2
ANDd
2 3
OR'\Idl.y
2 6
B
~--
eMf' (d,X)
~
6
~.--.---"-
!
EOR n.s
2*4
BIT d.l<
2 -4
ORAd.x ASld.x
2 4
2 6
A
F
D
e
F
l
Operation, Operation Codes and Status Register Table 6-4
. ..
MNE­
MONIC
I
AOC
AND
ASL
BCC
BCS
OPERATION
A+M+C A
AAIIII-A
C-· ll~-O
BRANCH IF =0
BRANCH IFC =1
BEQ
BIT
BMI
BNE
BPl
BRANCH IF Z = 1
AAM(NOTE 1)
BRANCH IF N =1
BRANCH IF Z =0
BRANCH IF N =0
BRA
BRK
BRL
BVC
BVS
BRANCH ALWAYS
BREAK (NOTE 2)
BRANCH LONG ALWAYS
BRANCH IF V =0
BRANCH IF V = 1
CLC
CLO
CLI
CLV
CMP
0 C
0-0
0-1
O-V
A-M
4
1 2 3
5
69 60 6F 65 i
29 20 2F 25
010
06 OA
10
75
35
16
8
9
77 61
37 21
to­
ftII
..
~
~ :!. ~ !!.
19 20 21
67
32 27
14 1
79
39
III
'tI
~
24
63 73
23 33
eo
34
BEQ
BIT
BMI
BNE
BPL
Z
M,M,
10
80
50
70
EO EC
CO CC
CE
•
00
182
0
C3 03
02 C7
OOIOF 09
05
88
0
DE
51
57 41
55
F6
50 5F 59
FE
152 47
DC
6C
85
A6
A4
46 4A
NO OPERATION
09 00 OF 05
AVM
A
Mp<:'1. Mpc.2 - MS-l.Ms
S- 2 - S
M(d). Mid' 1) - Ms 1. Ms
S 2-S
Mpc + rl, Mpc ...
1 Ms -1. Ms
S- 2­ S
84
BO BF B9
B6
8C
510
15
10 IF 19
54
44
M - M NEGATIVE
M ­ M POSITIVE
EA
11
17 01
03 13
12 07
r' .
PHA
PHB
PHD
PHK
PHP
A-Ms.S-l
S
OBR - Ms. S 1 S
O-MS.Ms I,S-2-S
PBR - Ms. S - 1 - S
p-Ms.S-l-S
PHX
PHY
PLA
PL8
PLO
X - Ms. S 1 ­ S
Y-MS.S-l-S
S. MS- A
S'1
S .1
S.Ms- OBR
S + 2 ­ S. Ms -1. Ms ­ 0
S+ 1 ­ S. Ms P
S+I-S.Ms X
Y
~+I-S.MS
MIIP- P
,
C"c
RTRN
RTRN FROM SUB. LONG
RTRN SUBROUTINE
A-M-<;-A
SEC
SED
SEI
SEP
STA
1 C
1 0
1-1
MVP-P
A-M
STP
STX
STY
STZ
TAX
STOP ( 1-¢2)
X-M
V­ M
OO-M
A-X
TAY
TCO
TCS
TOC
TRB
A-Y
C-O
C-S
O-C
TSB
TSC
TSX
TXA
TXS
TXY
TYA
TYX
WAI
WOM
AVM-M
S-C
S-X
X-A
X-S
X-V
V-A
V-X
O-ROY
NO OPERATION (RESERVED)
X8A
XCE
8--A
C-E
I
I
I
2E
26 2A
66 SA
i
36
3E
76
7E
E5
Fl
F71 El
Z
*
04
*
62
*
*
*
Ie
68
AB
2B
i
N
,N
'N
128
FA
7A
I
1*
Z
Z
Z
I Z
:1·
Z CI
IN
N
N V M X 0
i
Z C
Z C
*
60
I F5
FO FF F9
F2 E7
E3 F3
Z C
1
N V
38'
'ez
',*
Z
Z
X
I
•
Z
N V M X 0
N
N
N V M
0
40
6B
E9 ED EF
N
1
F8
78
80 8F 85
91
97 81
90 9F 99
95
92 87,
N V MX0
83 93
1
I Z
c*
'.
DB
8E
8C
9C
96
88
84
64
84
AA
74
1
910
A8
5B
lB
7B
lC
14
OC
04
N
i.
IN
N
Z
•
Z
*
N
i.
•*
N
N
N
Z
Z
N
N
N
Z
Z
Z
N
Z
*
Z
•
Z
3B
BA
SA
9A
*
Z
I
9B
96
8B
C6
42
lOB
FB
!
E
3.
i teN and V fla snotalfected. When M
*
*
F4
~~
!
6E
Z
Z
Z
Z C
06
4B
08
I
-c...l
ROR
RTI
RTL
RTS
SBC
I
I
N
N
0
I:
I
i
I
C2
N
A3 B3
BE
56
Z
Z
Z
*
.82 A7
0.M1
-NandM
-V.
*
= New W65C6161802 Instructions
• = New W65C02 Instructions
+ Add
- Subtract.
BRA
BRK
8RL
8VC
8VS
CLC
CLO
CLI
ClV
CMP
I
COP
CPX
CPY
DEC
OEX
I
DEY
EOR
INC
INX
INY
Z
7C
FC
Bl B7 A1
Z
Z C
Z
Z
Z
N
N
N
N
N
43 53
C *
I
N
N
N
N
06
E8
C8
NOP
ORA
PEA
C
Z C
N
02
CA
A2 AE
AO AC
410
*
0
I
4C 5C
22
20
A9 AD AF AS
•
I
0
~~ I01 ,01 ICI
49 40 4F 45
EE
E6 1A
0
0
18
08,
E4
C4
C6 3A
M-X
M-Y
Notes:
1. Bitimm
MNE­
MONIC
7 6 5 4 3 2 1 0
N V M X 0 I Z C E= 0
N V 1 B D I Z CE 1
Z C
AOC
N V
N
Z
AND
AS..
N
Z C
BCC
BCS
~
JC
90
C9 CO CF C5
41
PROCESSOR
STATUS CODE
'":
IE
i
LOX
LOY
LSR
MVN
MVP
ROL
'om'
..
...
DO
Y-1
Y
A"tM ­ A
INCREMENTS
X+ I-X
Y+ 1- Y
JUMP LONG TO NEW LOC.
JUMP TO NEW LOC.
JUMP LONG TO SU8.
JUMP TO SUB.
M-A
PLP
PLX
PLY
REP
I~~
1
o ­ l1ikLQJ -
1
6
."
..
FO
DEY
EOR
INC
INX
INY
PER
I
I
'tI
.
...
~~
i
'"
30
CO-PROCESSOR
X-M
Y-M
DECREMENT
X-l-X
PEl
I
ii
89 2C
COP
CPX
CPY
DEC
OEX
JML
JMP
JSL
JSR
LOA
W65C832 THE WESTERN DESIGN CENTER, INC.
WDC
*
*
•*
*
*
!
JML
JMP
JSL
JSR
LOA
LOX
LOY
LSR
MVN
MVP
NOP,
ORA
PEA
PEl
PER
PHA
PHB
PHD
PHK
PHP
PHX
PHY
PLA
PLB
PLO
PLP
PLX
PLY
REP
ROL
ROR
RTI
RTL
RTS
SBC
SEC
SED
SEI
SEP
STA
STP
STX
STY
STZ
TAX
TAY
TCO
TCS
TOC
TRB
TSB
TSC
TSX
TXA
TXS
TXY
TVA
TYX
WAI
WOM
XBA
XCE
VOR
-V- Exclusive OR
!
I
WOC THE WESTERN DESIGN CENTER, INC.
Table 6-5
ADDRESS MODE
Instruction Operation
(14) (14)
(15 )
CYCLE VP,ML,VDA,VPA ADDRESS BUS
1. 1 1
2. 1 1
(LDY,CPY,CPX,LDX,ORAI
AND,EOR/ADC,BIT/LDA 1 (1) 2a. 1 1
CMP,SBC/REP,SEP) (14 OpCodes) (2, 3 and bytes) (2 1 3 and 5 cycles) 1. 1 1
2a. Absolute-a 2. 1 1
(BIT,STY,STZ/LDY,
3. 1 1
CPY,CPX,STX/LDX,
ORA, AND, EOR,ADC 1
4. 1 1
(1) 4a. 1 1
STA,LDA/CMP/SBC)
(18 OpCodes) (3 bytes) (4, 5 and 7 cycles 2b. Absolute-(R-M-W)-a
1. 1 1
2. 1 1
(ASL,ROL, LSR, ROR
DEC, INC, TSB, TRB)
3. 1 1
4. 1 0
(6 OpCodes)
(1) 4a. 1 0
(3 bytes)
(6 for 8-bit data,
(3) 5. 1 0
8 for 16-bit data,
(1) 6a. 1 0
12 for 32-bit data)
6. 1 0
2c. Absolute (JUMP)-a
1. 1 1
(JMP) (4C)
2. 1 1
(1 OpCode)
3. 1 1
(3 bytes)
1. 1 1
(3 cycles) 2d. Absolute (Jump to
1. 1 1
subroutine)-a
2. 1 1
(JSR)
3. 1 1
(1 OpCode)
4. 1 1
(3 bytes)
5. 1 1
(6 cycles)
6. 1 1
(different order from
1. 1 1
N6502) *3a. Absolute Long-al
1. 1 1
(ORA, AND, EOR,ADC
2. 1 1
STA,LDA,CMP,SBC)
3. 1 1
(8 OpCodes)
4. 1 1
(4 bytes)
5. 1 1
(1) Sa. 1 1
(5, 6 and 8 cycles)
1. 1 1
*3b. Absolute Long (JUMP)-al
(JMP)
2. 1 1
(1 OpCode)
3. 1 1
(4 bytes)
4. 1 1
(4 cycles)
1. 1 1
1. Immediate-I MARCH 1990 W65C832
DATA BUS
R/W
1
0
0
1 PBR/PC
1 PBR,PC+l
1 PBR,PC+2-4
OpCode
IDO
IDl-3
1
0
0
1
1
1
1
1
0
0
PBR/PC
PBR / PC+l
PBR / PC+2
DBR,AA
DBR,AA+1-3
OpCode
1
AAL
1
AAH
1
Byte 0 1/0 Bytesl-3 1/0 1
0
0
1
1
0
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
PBR,PC
OpCode
PBR,PC+1
AAL
PBR,PC+2
AAH
DBR,AA
Byte 0
DBR,AA+-3
Bytes 1-3
DBR,AA+1 or 3 10
DBR,AA+3-1
Bytes 3-1
DBR,AA
Byte 0
PBR,PC
OpCode
PBR,PC+1
New PCL
PBR,PC+2
New PCH
PBR,NEW PC
New OpCode
1
0
0
0
1
1
1
1
1
1
0
0
0
1
PBR,PC
PBR,PC+l
PBR,PC+2
PBR,PC+2
O,S
O,S-l
PBR,NEW PC
1
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
1
0
1
PBR,PC
PBR, PC+1
PBR,PC+2
PBR,PC+3
AAB,AA
AAB,AA+1
PBR,PC
PBR,PC+1
PBR,PC+2
1 PBR,PC+3
1 NEW PBR,PC
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
OpCode
New PCL
New PCH
1
1
1
10
1
PCH
0
PCL
0
New OpCode 1 OpCode
1
AAL
1
AAH
1
AAB
1
Byte 0 1/0 Bytesl-3 1/0 OpCode
1
New PCL
1
New PCH
1
New'BR
1
OpCode
1
34
WDC
THE WESTERN DESIGN
ADDRESS MODE
OpCode
New PCL
1
1
1
0
1
New PCH
1
1
1
1
1
1
1
3.
1
(1 OpCode)
(4 bytes)
(7 cycles)
4.
5.
6.
7.
8.
1
1
1
1
1
1.
1.
1
1
1
1
a
0
1
1
1
1
1
1
2.
(2) 2a.
1
3. 1 1
(1) 3a. 1 1
1
0
1 1
1 1
1 1
1 0
1 0
1 0
1 0
1 0
1 1
1 1
1
1.
(2)
(1)
(3)
(1)
5. Accumulator-A
(ASL,INC,ROL,DEC,LSR,ROR)
(6 OpCodes)
(1 byte)
( 2 cycles)
6a. Implied i
(DEY,INY,INX,DEX,NOP,
XCE,TYA,TAY,TXA,TXS,
TAX,TSX,TCS,TSC,TCD,
TDC,TXY,TYX,CLC,SEC,
CLI,SEI,CLV,CLD,SED)
(25 OpCodes)
(1 byte)
(2 cycles)
*6b. Implied i
(XBA)
(1 OpCode)
(1 byte)
(3 cycles)
f6c. Wait-for-Interrupt
(WAI)
(1 OpCode)
(9)
(1 byte)
(3 cycles)
IRQ, NMI
1.
2.
1.
2.
1.
2.
3.
1.
2.
3.
1.
R/W
1 PBR,PC
1 PBR,PC+1
(JSL)
2.
2a.
3.
3a.
4.
Sa.
5.
DATA BUS
a
1 1
1 1
1.
W65C832
1
2.
MARCH 1990
INC.
CYCLE VP,ML,VDA,VPA ADDRESS BUS
*3c. Absolute Long (JUMP to
Subroutine Long)-al
4a. Direct-d
(BIT,STZ,STY,LDY,
CPY,CPX,STX,LDX,
ORA, AND, EOR,ADC,
STA,LDA,CMP,SBC)
(18 OpCodes)
(2 bytes)
(3, 4, 5 and 7 cycles)
4b. Direct (R-M-W)-d
(ASL, ROL, LSR, ROR
DEC,INC,TSB,TRB)
(6 OpCodes)
(2 bytes)
(5,6,7,8,11 and
12 cycles)
~ENTER,
a
1
1
PBR,PC+2
a a,s
a O,S
1 PBR,PC+3
0 O,S-l
0 O,S-2
1 NEW PBR,PC
1 PBR,PC
1 PBR,PC+1
0 PBR,PC+1
0 O,D+DO
0 o,D+DO+1-3
PBR
a
1
IO
New PBR
1
PCH
a
PCL
0
New OpCode 1
OpCode
1
1
DO
IO
1
Byte a 1/0
Bytesl-3 1/0
1
1
1
1
1
1
0
0
1
0
OpCode
1 PBR,PC
1 PBR, PC+1
DO
0 PBR,PC+l
IO
Byte 0
0 O,D+DO
Bytes 1-3
0 O,D+DO+1-3
0 O,D+DO+1 or 3 IO
Bytes 3-1
0 O,D+DO+3-1
Byte 0
0 O,D+DO
OpCode
1 PBR, PC
IO
0 PBR,PC+l
1 1
1 1
1
0
1 PBR,PC
0 PBR,PC+1
OpCode
IO
1
1 1
1 1
1 1
1
0
0
1 PBR,PC
0 PBR,PC+1
0 PBR,PC+1
OpCode
1
1
1
1
1
1
1
1
0
0
1
ROY
1 1
0 1
0 0
1 1
1
1
1
1
a
a
1
1
0
1
1
PBR, PC
PBR,PC+1
PBR,PC+1
PBR,PC+1
IO
10
OpCode
10
10
IRQ (BRK)
1
1
1
1
1
1
1
35
WOC
THE WESTERN DESIGN CENTER, INC.
ADDRESS MODE
#6d. Stop-the-Clock
(STP)
(1 OpCode)
RES-=l
(1 byte)
RES-=O
(3 cycles)
RES-=O
RES-=l
(See 21a. Stack
Hardware Interrupt)
7. Direct Indirect
Indexed-(d),y
(ORA,AND,EOR,ADC,
STA,LDA,CMP,SBC)
(8 OpCodes)
(2 bytes)
(5,6,7,8,9 and 10
cycles)
8. Direct Indirect
Indexed Long-(d],y
(ORA, AND, EOR, ADC,
STA, LDA, CMP, SBC)
(8 OpCodes)
(2 bytes)
(6,7,8,9 and 10
cycles)
CYCLE VP,ML,VDA,VPA ADDRESS BUS
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1 1
2. 1 1
(2) 2a. 1 1
3. 1 1
4. 1 1
(4) 4a. 1 1
5. 1 1
(1) Sa. 1 1
1. 1 1
2. 1 1
(2) 2a. 1 1
3. 1 1
4. 1 1
5. 1 1
(17) Sa. 1 1
6. 1 1
(1) 6a. 1 1
9. Direct Indexed
1. 1 1
Indirect-(d,x)
2. 1 1
(ORA,AND,EOR,ADC,
(2) 2a. 1 1
STA,LDA,CMP,SBC)
3. 1 1
(8 OpCodes)
4. 1 1
(2 bytes)
5. 1 1
(6,7,8,9 and 10 cycles)
6. 1 1
(1) 6a. 1 1
10a.Direct,X-d,x
1. 1 1
(BIT,STZ,STY,LDY,
2. 1 1
ORA, AND, EOR,ADC,
(2 ) 2a. 1 1
STA,LDA,CMP,SBC)
3. 1 1
(11 OpCodes)
4. 1 1
(2 bytes)
(1) 4a. 1 1
(4,5,6,7 and 8 cycles)
10b.Direct,X(R-M-W)-d,x
1. 1 1
(ASL,ROL,LSR,ROR,
2. 1 1
DEC,INC)
(2) 2a. 1 1
(6 OpCodes)
3. 1 1
(2 bytes)
4. 1 0
(6,7,8,9,12 and
(1) 4a. 1 0
13 cycles)
(3) 5. 1 0
(1), 6a. 1 0
6. 1 0
1
0
0
1
1
0
1
1
1
0
0
1
1
1
0
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
1
0
1
1
1
1
0
0
0
0
0
MARCH 1990
1
2. 1
3. 1
1c. 1
lb. 1
1a. 1
1. 1
1.
1.
ROY
1
1
1
1
1
1
1
W65C832
DATA BUS
PBR,PC
PBR,PC+1
PBR,PC+1
PBR,PC+1
PBR,PC+1
PBR,PC+1
PBR,PC+1
OpCode
PBR,PC
PBR,PC+1
PBR,PC+1
O,D+DO
0,D+DO+1
DBR,AAJ,AAL+YL
DBR,AA+Y
DBR,AA+Y+1-3
PBR,PC
PBR,PC+1
PBR,PC+1
O,D+DO
0,D+DO+1
0,D+DO+2
0,0+DO+2
AAB,AA+Y
AAB,AA+Y+1-3
PBR,PC
PBR,PC+1
PBR,PC+1
PBR,PC+1
O,D+DO+X
O,D+DO+X+1
DBR,AA
DBR,AA+1-3
PBR,PC
PBR,PC+1
PBR,PC+1
PBR,PC+1
O,D+DO+X
0,D+DO+X+1
OpCode
DO
PBR,PC
PBR,PC+1
PBR,PC+1
PBR,PC+1
O,D+DO+X
O,D+DO+X+1
0,D+DO+X+1
0 O,D+DO+X+1
0 O,D+DO+X
10
10
RES (BRK)
RES (BRK)
RES (BRK)
BEGIN
IO
AAL
AAH
10
Byte 0
Bytesl-3
OpCode
DO
10
AAL
AAH
AAB
10
Byte 0
Bytesl-3
OpCode
DO
10
10
AAL
AAH
Byte 0
Bytesl-3
OpCode
DO
IO
10
Byte 0
Bytesl-3
OpCode
DO
R/N
1
1
1
1
1
1
1
1
1
1
1
1
1
1/0
1/0
1
1
1
1
1
1
1
1/0
1/0
1
1
1
1
1
1
1/0
1/0
1
1
1
1
1/0
1/0
10
1
1
1
1
1
1
1
Bytes 3-1
Byte 0
0
10
10
Byte 0
Bytesl-3
0
36
WDC
TaE WESTERN DESIGN CENTER, INC.
ADDRESS MODE
11. Direct,Y-d,y
(STX, LDX)
(2 OpCodes)
(2 bytes)
(4, 5, 6, 7 and 8 cycles)
CYCLE VP,ML,VDA,VPA ADDRESS BUS
1 1
1 1
1
0
1
0
3. 1 1
4. 1 1
(1) 4a. 1 1
l. 1 1
2. 1 1
3. 1 1
(4) 3a. 1 1
4. 1 1
(1) 4a. 1 1
1.
2.
(2)
12a.Absolute,X-a,x
(BIT,.LDY, STZ,
ORA,AND, EOR,ADC,
STA,LDA,CMP,SBC)
(11 OpCodes)
(3 bytes)
(4,5,6, 7 and 8 cycles)
12b.Absolute,X(R-M-W)-a,x
(ASL,ROL,LSR,ROR,
DEC, INC)
(6 OpCodes)
(3 bytes)
(7,9 and 13 cycles)
(1)
(3)
(1)
*13. Absolute Long,X-al,x
(ORA, AND, EOR, ADC,
STA,LDA,CMP,SBC)
(8 OpCodes)
(4 bytes)
(5,6,7 and 8 cycles)
14. Absolute,Y-a,y
(LDX,ORA/AND,EOR/ADC,
STA,LDA/CMP/SBC)
(9 OpCodes)
(3 bytes)
(4,5 / 6,7 and 8 cycles)
15. Relative-r
(BPL,BMI,BVC,BVS/BCC,
BCS,BNE,BEQ,BRA)
(9 OpCodes)
(2 bytes)
(2,3 and 4 cycles)
*16. Relative Long-rl
(BRL)
(1 OpCode)
(3 bytes)
(4 cycles)
17a.Absolute Indirect-(a)
(JMP)
(1 OpCode)
(3 bytes)
(5 cycles)
2a. 1
l.
2.
3.
4.
5.
Sa.
6.
7a.
7.
l.
2.
3.
4.
(17) 4a.
5.
(1) Sa.
l.
2.
3.
(4) 3a.
4.
(1) 4a.
l.
2.
(5) 2a.
(6) 2b.
l.
l.
2.
3.
4.
- l.
l.
2.
3.
4.
5.
l.
MARCH 1990
W65C832
DATA BUS
R/W
OpCode
DO
1
1
10
10
1
0
1
1
1
0
0
0
1
1
1 PBR,PC
1 PBR,PC+1
0 PBR,PC+l
0 PBR,PC+1
0 O,D+DO+Y
0 O,D+DO+Y+1-3
1 PBR,PC
1 PBR, PC+l
1 PBR,PC+2
0 DBR,AAH,AAL+XL
0 DBR,AA+X
0 DBR,AA+X+l-3
1
Byte 0 1/0
Bytesl-3 1/0
1
OpCode
AAL
1
AAH
1
10
1
Byte 0 1/0
Bytesl-3 1/0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
PBR,PC
PBR,PC+1
PBR,PC+2
DBR,AAH,AAL+XL
DBR,AA+X
DBR,AA+X+1-3
DBR,AA+X+1or3
DBR,AA+X+3-1
DBR,AA+X
PBR,PC
PBR,PC+1
PBR,PC+2
PBR,PC+3
PBR,PC+3
AAB,AA+X
AAB,AA+X+1-3
PBR,PC
PBR / PC+1
PBR,PC+2
DBR, AAH, AAL+Y
DBR,AA+Y
DBR / AA+Y+1-3
PBR,PC
PBR,PC+1
PBR,PC+1
PBR,PC+1
PBR,PC+Offset
OpCode
AAL
AAH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
1
PBR,PC
PBR / PC+1
PBR / PC+2
PBR,PC+2
PBR,PC+Offset
PBR,PC
PBR,PC+1
PBR, PC+2
O,AA
OpCode
OFF Low
OFF High
O/AA+1
PBR/NEW PC
1
1
1
10
1
1
Byte 0
Bytes 1-3 1
IO
1
Bytes 3-1 0
Byte 0
0
1
OpCode
AAL
1
AAH
1
1
AAB
1
10
1/0
Byte 0
Bytesl-3 1/0
OpCode
1
AAL
1
AAH
1
10
1
Byte 0
110
Bytesl-3 1/0
OpCode
1
OFF
1
10
1
1
10
1
OpCode
10
OpCode
OpCode
AAL
AAH
New PCL
New PCH
OpCode
1
1
1
1
1
1
1
1
1
1
1
37
WOC
ADDRESS MODE
THE WESTERN DESIGN CENTER, INC.
CYCLE VP,ML,VDA,VPA ADORESS BUS
*17b.Absolute Indirect-(a)
(JML)
(1 OpCode)
(3 bytes)
(6 cycles
U8. Oirect Indirect-(d)
(ORA, AND, EOR,ADC,
(2 )
STA,LOA,CMP,SBC)
(8 OpCodes)
(2 bytes)
(5,6,7,8 and 9 cycles)
(1)
*19. Direct Indirect Long-[d]
(ORA,ANO,EOR,AOC
(2)
STA, LOA, CMP, SBC
(8 OpCodes)
(2 bytes)
(6,7,8,9 and 10 cycles)
1.
2.
3.
4.
5.
6.
1.
1.
2.
2a.
3.
4.
5.
Sa.
1.
2.
2a.
3.
4.
5.
6.
(1) 6a.
20a.Absolute Indexed Indirect­
(a, xl
1.
(JMP)
2.
(1 OpCode)
3.
(3 bytes)
4.
(6 cycles)
5.
6.
1.
*20b.Absolute Indexed Indirect- 1.
(a, x)
2.
(JSR)
3.
(1 OpCode)
4.
(3 bytes)
5.
(8 cycles)
6.
7.
8.
1.
1.
21a.Stack (Hardware
Interrupts)-s
(3) 2.
(IRQ,NMI,ABORT,RES)
(7) 3.
(4 hardware interrupts) (10)4.
(0 bytes)
(10) 5.
(7 and 8 cycles)
(10) (11) 6.
7.
8.
l.
MARCH 1990
W65C832 OATA BUS
R/W
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
PBR,PC
PBR,PC+1
PBR,PC+2
O,AA
O,AA+l
O,AA+2
NEW PBR,PC
PBR,PC
PBR,PC+1
PBR,PC+1
0,0+00
0,0+00+1
OBR,AA
PBR,AA+l-3
PBR,PC
PBR, PC+l
PBR,PC+1
0,0+00
0,0+00+1
0,0+00+2
AAB,AA
AAB,AA+l-3
1
1
1
1
1
1
1
1
1
1
10
AAL
1
AAH
1
Byte 0 1/0
Bytesl-3 1/0
OpCode
1
DO
1
10
1
AAL
1
AAH
1
AAB
1
Byte 0 1/0
Bytesl-3 1/0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
0
1
1
1
1
0
0
PBR,PC
PBR-PC+l
PBR-PC+2
PBR,PC+2
PBR,AA+X
PBR,AA+X+1
PBR,NEW PC
PBR,PC
PBR,PC+1
O,S
O,S-l
PBR,PC+2
PBR,PC+2
PBR,AA+X
PBR,AA+X+l
PBR,NEW PC
PBR,PC
PBR,PC
O,S
O,S-l
0,S-2
O,S-3
O,VA
O,VA+1
O,AAV
OpCode
AAL
AAH
0
0
0
0
0
1
OpCode
AAL
AAH
New PCL
New PCH
New PBR
OpCode
OpCode
00
1
1
1
10
1
New PCL
1
New PCH
1
OpCode
1
OpCode
1
AAL
1
PCH
0
PCL
0
AAH
1
10
1
New PCL
1
New PCH
1
New OpCode 1
10
1
10
1
PBR
0
PCH
0
PCL
0
p
0
AAVL
1
AAVH
1
New OpCode 1
38
WDC THE WESTERN DESIGN CENTER, INC.
ADDRESS MODE 21b.Stack (Software
Interrupts)-s
(BRK,COP)
(2 OpCodes)
(2 bytes)
(7 and 8 cycles)
CYCLE VP,ML,VDA,VPA ADDRESS BUS
(16) 1.
(16) (3) 2.
21c.Stack (Return from
Interrupt)-s
(RTI)
(1 Op Code)
(1 byte)
(6 and 7 cycles)
(different order from
N6502) 21d.Stack (Return from
Subroutine)-s
(RTS)
(1 Op Code)
(1 byte)
(6 cycles)
(7) 3.
4.
5.
6.
7. 8. 1. 1.
2.
(3) 3.
4.
5.
6.
(7) 7.
*21e.Stack (Return from
Subroutine Long)-s
(RTL)
(1 Op Code)
(1 byte)
(6 cycles)
21f.Stack (Push)-s
(PHP/PHA,PHY,PHX,
PHD,PHK,PHB)
(1) (11)
(7 Op Codes)
(1 byte)
(3,4, and 6 cycles) 21g.Stack (Pull)-s
(PLP/PLA,PLY,PLX,PLD,PLB)
(Different than N6502)
(6 Op Codes)
(1 byte)
(1)
(4,5 and 7 cycles) *21h.Stack (Push Effective
Indirect Address)-s
(PEl)
(2)
(1 Op Code)
(2 bytes)
(6 and 7 cycles)
MARCH 1990
1.
1.
2.
3.
4.
5.
6.
1. 1.
2.
3.
4.
5.
6.
1. 1.
2.
3a.
3.
1.
2.
3.
4.
4a.
1.
2.
2a.
3.
4.
5.
6. 1 1
1 1
1 1
1 1
1 1
1 1
0 1
0 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
W65C832 DATA BUS
R/W
OpCode
Signature
PBR
PCH
PCL
P
AAVL
AAVH
New OpCode
OpCode
10
10
P
PCL
PCH
PBR
New OpCode
OpCode
10
10
PCL
PCH
10
OpCode
OpCode
0
PBR,PC
PBR,PC+1
O,S
O,S-1
O,S-2
O,S-3 (16)
O,VA
O,VA+1
O,AAV
PBR,PC
PBR,PC+1
PBR,PC+1
0, S+1
O,S+2
O,S+3
O,S+4
PBR,PC
PBR/PC
PBR,PC+1
PBR,PC+1
0,S+1
0,S+2
NEW PC-1
PBR,PC
PBR, PC
PBR,PC+1
PBR,PC+1
0, S+1
0,S+2
0/S+3
NEW PBR,PC
PBR/PC
PBR / PC+1
O,S
0,S-1-3
PBR,PC
PBR,PC+1
PBR,PC+1
0, S+1
0,S+2-4
OpCode
10
10
Byte 0
Bytes1-3
1
1
1
1
1
OpCode
DO
10
AAL
AAH
1
1
1
1
1
AAH
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1 PBR,PC
1 PBR,PC+1
0 PBR,PC+1
0 0,0+00
0 0,0+00+1
0 O,S-1
0 0,S-1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO
10
1
New PCL
1
New PCH
1
New PBR
1
New OpCode 1 OpCode
1
10
1
Bytes3-1
1
ByteO
1
1
AAL
39
WDC ADDRESS MODE THE WESTERN DESIGN CENTER, INC.
CYCLE VP,ML,VDA,VPA ADDRESS BUS
*21i.Stack (Push Effective
Absolute Address)-s
(PEA)
(lOp Code)
(3 bytes)
(5 cycles) *21j.Stack (Push Effective
Program Counter Relative
Address)-s
(PER)
(1 Op Code)
(3 bytes)
(6 cycles)
*22. Stack Relative-d,s
(ORA, AND, EOR, ADL,
STA,LDA,CMP,SBC)
(8 Op Codes)
(1)
(2 bytes)
(4,5 and 7 cycles) *23. Stack Relative Indirect
Indexed-(d,s),y
(ORA,AND,EOR,ADC,STA,LDA,
CMP, SBC)
(8 Op Codes)
(2 bytes)
(7,8 and 10 cycles)
(1)
*24a.Block Move Positive
(forward)-xyc
(MVP)
(lOp Code)
(3 bytes)
(5 and 7 cycles)
R/W
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
PBR,PC
PBR,PC+l
PBR,PC+2
O,S
O,S-l
OpCode
AAL
AAH
AAH
AAL
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
PBR, PC
PBR,PC+1
PBR,PC+2
PBR,PC+2
O,S
1
1. 1
2. 1
3. 1
4. 1
4a. 1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
0
O,S-1
PBR,PC
PBR,PC+1
PBR,PC+1
O,S+SO
0,S+SO+1-3
OpCode
1
OFF Low
1
OFF High
1
IO
1
PCH+OFF+
0
Carry PCL+OFF
0
OpCode
1
1
SO
IO
1
Byte 0 1/0 Bytesl-3 1/0 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
0
0
0
0
0
0
PBR,PC
PBR,PC+1
PBR+PC+1
O,S+SO
O,S+SO+l
O,S+SO+1
DBR,AA+Y
DBR,AA+Y+1-3
1
OpCode
1
SO
IO
1
AAL
1
AAH
1
IO
1
Byte 0 1/0 Bytesl-3 1/0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
0
PBR,PC
PBR,PC+1
PBR,PC+2
SBA,X
DBA,Y
DBA,Y
DBA,Y
OpCode
DBA
SBA
SRC Data
DEST Data
IO
IO
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
0
PBR,PC
PBR,PC+1
PBR, PC+2
SBA,X-1
DBA,Y-1
DBA,Y-1
DBA,Y-1
OpCode
DBA
SBA
SRC Data
DEST Data
IO
IO
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
PBR,PC
PBR,PC+1
PBR,PC+2
SBA,X-2
DBA,Y-2
DBA,Y-2
DBA,Y-2
PBR,PC+3
Op Code
DBA
SBA
SRC Data
DEST Data
IO
IO
New OpCode
1
1
1
1
1
1
1
0
0
1
1
0
0
2.
3.
4.
5.
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
6.
7.
7a.
- 1.
2.
3.
4.
5.
6.
7.
x=Source Address y=Destination
I 1.
c=iof bytes to move-1(18) I 2.
x,y Decrement
(18) I 3.
MVP is used when the N-11 4.
dest. start address Bytel 5.
is higher (more
C=l, 6.
positive) than the source I 7.
start address. I 1.
FFFFFF
(18) I 2.
"Dest Start
(18) I 3.
Bytel 4.
, Source StartN Last'
5.
6.
-':=Dest
End
C=OI
I
I 7.
I ,
Source End
000000
I 1.
MARCH 1990
DATA BUS
1
1
1
1
1
1.
I
(18) I
(18) I
N-2!
Bytel
C=21
I
W65C832
1.
1
1
1
1
0
0
0
1
1
1
40
WDC ADDRESS MODE
*24b.Block Move Negative
(backward)-xyc
(MVN)
(lOp Code)
(3 bytes)
(7 cycles)
THE WESTERN DESIGN CENTER, INC.
CYCLE VP,ML,VDA,VPA ADDRESS BUS
- l.
DATA BUS
R!W
OpCode
DBA
SBA
SRC Data
DEST Data
IO
1
1
IO
1
0
1
1
3.
1
1
0
4.
5.
6.
7.
I
1
1
1
1
1
1
1
1
1
1
0
0
1 PBR,PC
1 PBR,PC+1
1 PBR,PC+2
0 SBA,X
0 DBA,Y
0 DBA,Y
0 DBA,Y
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
0
0
PBR,PC
PBR,PC+l
PBR,PC+2
SBA,X+l
DBA, Y+l
DBA,Y+l
DBA,Y+l
OpCode
DBA
SBA
SRC Data
DEST Data
IO
IO
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
PBR,PC
PBR,PC+l
PBR,PC+2
SBA,X+2
DBA,Y+2
DBA,Y+2
DBA,Y+2
PBR,PC+3
OpCode
DBA
SBA
SRC Data
DEST Data
IO
IO
New OpCode
1
1
1
1
0
1
1
1
I
(18) I
(1S) I
N-21
Bytel
C=21
2.
x=Source Address
y=Destination
I
c=tof bytes to move-l(18) I 2.
x,y Increment
(18) I 3.
MVN is used when the N-ll 4.
dest. start address Bytel 5.
is lower (more
C=ll 6.
negative) than the source I 7.
start address.
I l.
FFFFF
(18) I 2.
Source End
(18) I 3.
I
N Bytel 4.
I
I
I Dest.End
C=OI 5.
I
1 I-1-Source Start
I 6.
V I -Dest.Start
I 7.
000000
I l.
1 1
1 1
W65C832 1
0
0
0
1
1
1. Add 1 byte (for immediate only) for 16-bit data, add 3 bytes for 32-bit data,
add 1 cycle for 16-bit data and 3 cycles for 32-bit data.
2. Add 1 cycle for direct register low (DL) not equal O.
3. Special case for aborting instruction. This is the last cycle which may be aborted or the Status, PBR or DBR registers will be updated. 4. Add 1 cycle for indexing across page boundaries, or write, or 16-bit or 32-bit
Index Registers.
When 8-bit Index Registers or in the emulation mode, this
cycle contains invalid addresses.
5. Add 1 cycle if branch is taken.
6. Add 1 cycle if branch is taken across page boundaries in 6502 emulation mode.
7. Subtract 1 cycle for 6502 emulation mode.
8. Add 1 cycle for REP, SEP.
9. Wait at cycle 2 for 2 cycles after NMI- or IRQ- active input.
10. R/W- remains high during Reset.
11. BRK bit 4 equals "0" in Emulation mode.
12. PHP and PLP.
13. Some OpCodes shown are not on the W65C02.
14. VDA and VPA are not valid outputs on the W65C02 but are valid on the W65C832.
The two signals, VDA and VPA, are included to point out the upward
compatibility to the W65C832. When VDA and VPA are both a one level, this is
equivalent to SYNC being a one level.
15. The PBR is not on the W65C02.
16. Co-processors may monitor the signature byte to aid in processor to
co-processor communications.
17. Add 1 cycle for 32-bit Index Register mode.
18. Subtract 2 bytes and 2 cycles when in W65C832 Native mode for MVN and MVP.
MARCH 1990
41
WDC
THE WESTERN DESIGN CENTER, INC.
AAB
AAH
AAL
AAVH
AAVL
Byte 0
Bytes 1-3
C
D
DBA
DBR
DEST
DO
IDO
IDl-3
Absolute Address Bank
Absolute Address High
Absolute Address Low
Absolute Address Vector High
Absolute Address Vector Low
Data Byte 0
Data Bytes 1-3
Accumulator
Direct Register
Destination Bank Address
Data Bank Register
Destination
Direct Offset
Immediate Data Byte 0
Immediate Data Bytes 1-3
10 Internal Operation
OFF
P
PBR
PC
PCH
PCL
R-M-W
S
SBA
SRC
SO
VA
x,y
W65C832 Offset
Status Register
Program Bank Register
Program Counter
Program Counter High
Program Counter Low
Read-Modify-Write
Stack Address
Source Bank Address
Source
Stack Offset
Vector Address
Index Register
* = New W65C816/802 Addressing Modes
*
= New W65C02 Addressing Modes
Blank = NMOS 6502 Addressing Modes
MARCH 1990
42
I
I
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I
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I
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WOC THE WESTERN DESIGN CENTER, INC.
W65C832 SECTION 7
RECOMMENDED ASSEMBLER SYNTAX STANDARDS
7.1
Directives
Assembler directives are those parts of the assembly language source program which
give directions to the assembler; this includes the definition of data area and
constants within a program.
This standard excludes any definitions of assembler
directives.
7.2
Comments
An assembler should provide a way to use any line of the source program as a
comment. The recommended way of doing this is to treat any blank line, or any line
that starts with s semi-colon or an asterisk as a comment. Other special characters
may be used as well.
7.3
The Source Line
Any line which causes the generation of a single machine language instruction should
be divided into four fields:
a label field, the operation code, the operand, the
comment field.
7.3.1 The Label Field--The label field begins in column one of the line.
A
label must start with an alphabetic character, and may be followed by
zero or more alphanumeric characters. An assembler may define an upper
limit on the number of characters that can be in a label, so long as
that upper limit is greater than or equal to six characters.
An
assembler may limit the alphabetic characters to upper-case characters
if desired.
If lower-case characters are allowed, they should be
treated as identical to their upper-case equivalents. Other characters
may be allowed in the label, so long as their use does not conflict with
the coding of operand fields.
7.3.2 The Operation Code Field--The operation code shall consist of a three
character sequence (mnemonic) from Table 6-2. It shall start no sooner
than column 2 of the line, or one space after the label if a label is
coded.
7.3.2.1
Many of the operation codes in Table 6-2 have duplicate
mnemonics; when two or more machine language instruction have the same
mnemonic, the assembler resolves the difference based on the operand.
7.3.2.2
If an assembler allows lower-case letters in labels, it must
also allow lower-case letters in the mnemonic. When lower-case letters
are used in the mnemonic, they shall be treated as equivalent to the
upper-case counterpart. Thus, the mnemonics LDA, Ida and LdA must all
be recognized, and are equivalent.
7.3.2.3 In addition to the mnemonics shown in Table 6-2, an assembler
may provide the alternate mnemonics show in Table 7-3-1.
MARCH 1990
43
WDC THE WESTERN DESIGN CENTER, INC.
w65C832
Table 7-3-1 Alternate Mnemonics
Standard
BCC
Alias
BLT
BCS
CMP A
BGE
CMA
DEC A
INC A
JSL
JML
TCD
TCS
TDC
TSC
XBA
DEA
INA
JSR
JMP
TAD
TAS
TDA
TSA
SWA
7.3.2.4
JSL should be recognized as equivalent to JSR when it is
specified with a long absolute address. JML is equivalent to JMP with
long addressing forced.
7.3.3 The Operand Field--The operand field may start no sooner than one space
after the operation code field.
The assembler must be capable of at
least twenty-four bit address calculations.
The assembler should be
capable of specifying addresses as labels, integer constants, and
The assembler must allow addition and
hexadecimal constants.
subtraction in the operand field.
Labels shall be recognized by the
:eact that they start alphabetic characters. Decimal numbers shall be
recognized as containing only the decimal digits 0 ... 9.
Hexadecimal
constants shall be recognized by prefixing the constant with a "$"
character, followed by zero or more of either the decimal digits or the
hexadecimal digits "A" ... "F". If lower-case letters are allowed in the
label field, then they shall also be allowed as hexadecimal digits.
7.3.3.1 All constants, no matter what their format, shall provide at
least enough precision to specify all values that can be represented by
a twenty-four bit signed or unsigned integer represented in two's
complement notation.
7.3.3.2 Table 7-3-2 shows the operand formats which shall be recognized
by the assembler. The symbol d is a label or value which the assembler
can recognize as being less than $100. The symbol a is a label or value
which the assembler can recognize as greater than $FF but less than
$10000; the symbol al is a label or value that the assembler can
recognize as being greater than $FFF. The symbol EXT is a label which
cannot be located by the assembler at the time the instruction is
assembled. Unless instructed otherwise, an assembler shall assume that
EXT labels are two bytes long. The symbols rand rl are 8 and 16 bit
signed displacements calculated by the assembler.
-­
7.3.3.3
Note that the operand does not determine whether or not
immediate address loads one or two bytes, this is determined by the
setting of the status register.
This forces the requirement for a
directive or directives that tell the assembler to generate one or two
bytes of space for immediate loads. The directives provided shall allow
separate settings for the accumulator and index registers.
MARCH 1990
44
w65C832
THE WESTERN DESIGN CENTER, INC.
WDC
7.3.3.4 The assembler shall use the <, >, and A characters after the #:
character in immediate address to specify which byte or bytes will be
selected from the value of the operand. Any calculations in the operand
must be performed before the byte selection takes place. Table 7-3-2
defines the action taken by each operand by showing the effect of the
operator on an address.
The column that shows a two byte immediate
value show the bytes in the order in which they appear in memory. The
coding of the operand is for an assembler which uses 32 bit address
calculations, showing the way that the address should be reduced to a 24
bit value.
Table 7-3-2
Operand
#$01020304
#<$01020304
#>$01020304
1"$01020304
Byte Selection Operator
One Byte Result
04
04
03
02
Two Byte Result
03
03
02
01
04
04
03
01
Four Byte Result
01
02
03
04
7.3.3.5 In any location in an operand where an address, or expression
resulting in an address, can be coded, the assembler shall recognize the
prefix characters <, I, and >, which force one byte (direct page), two
byte (absolute) or three byte (long absolute) addressing.
In cases
where the addressing modes is not forced, the assembler shall assume
that the address is two bytes unless the assembler is able to determine
the type of addressing required by context, in which case that
addressing mode will be used.
Addresses shall be truncated without
error in an addressing mode is forced which does not require the entire
value of the address. For example,
LDA $0203
LDA \$010203­
are completely equivalent. If the addressing mode is not forced, and
the type of addressing cannot be determined from context,t he assembler
shall assume that a two byte address is to be used. If an instruction
does not have a short addressing mode (as in LDA< which ahs no direct
page indexed by Y) and a short address is used in the operand, the
assembler shall automatically extend the address by padding the most
significant bytes with zeroes in order to extend the address to the
length needed.
As with immediate address, any expression evaluation
shall take place before the address is selected; thus, the address
selection character is only used once, before the address of expression.
7.3.3.6 The! (exclamation point) character should be supported as an
alternative to the I (vertical bar).
7.3.3.7 A long indirect address is indicated in the operand field of an
instruction field of an instruction by surrounding the direct page
address where the indirect address is found by square brackets; direct
page addresses which contain sixteen-bit addresses are indicated by
being surrounded by parentheses.
7.3.3.8
The operands of a block move instruction are specified as
source bank, destination bank-the opposite order of tzz object bytes
generated.
7.3.4
~
Comment Field--The comment field may start no sooner than one space
after the operation code field or operand field depending on instruction
type.
/'
MARCH 1990
45
WDC
THE WESTERN DESIGN CENTER, INC.
W65C832 SECTION 8 CAVEATS
Table 8-1
I
11. S (Stack)
I
I
12. X (X Index Reg)
I
I
I
13. Y (Y Index Reg)
I
I
I
14. A (Accumulator)
I
15. (Flag Reg)
I
I
I
I
I
I
I6. Timing
I
A. ABS,X ASL, LSR,
I
ROL, ROR With No
I
Page Crossing
lB. Jump Indirect
I
Operand=XXFF
I
I
1 C. Branch Across
I
Page
I
D. Decimal Mode
17. BRK Vector
I
I
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I
I
18. Interrupt or Break
I Bank Address
I
I
I
1
19. Memory Lock (ML-)
I
W65C816 Compatibility Issues
I W65C816/802
I
W65C02
I
NMOS 6502 IAlways page 1 (E=IAlways page l,81Always page 1,8 11), 8 bits; 16
Ibits
Ibits Ibits when (E=O) I
I
IIndexed page zerolAlways page 0 IAlways page 0 Ialways in page 0 I
I
I (E=l), Cross page I
I
I
I
I (E=O)
IIndexed page zerolAlways page 0 IAlways page 0 Ialways in page 0 I
I
I (E=l), Cross page I
I
I (E=O)
I
I
18 bits (M=l), 16 18 bits
18 bits Ibits (M=O)
I
I
IN,V, and Z flags IN,V, and ZflagslN,V, and Z flags I valid in decimal Ivalid in dec. Iinvalid in I
I
Idecimal Imode. D=O after Imode. D=O after Imode. D=unknown Ireset/interrupt. Ireset/interruptlafter reset. D I
I
Inot modified I
I
I after interrupt I
I
I
17 cycles
16 cycles
17 cycles I
I
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I
15 cycles
16 cycles
15 cycles and I
I
Iinvalid page I
Icrossing I
14 cycles (E=l)
14 cycles
14 cycles 13 cycles (E=O)
I
I
INa add. cycle
IAdd 1 cycle
INa add. cycle 100FFFE,F (E=l)
IFFFE,F BRK bit=IFFFE,F BRK bit=O 1 IBRK bit=O on
10 on stack if Ion stack if IRQ-, I Istack if IRQ-,
IIRQ-, NMI-.
INMI-.
I
INMI-,ABORT-.
I
I
I
100FFE6,7 (E=O) x=1
I
I
IX on Stack always I
I
I
IPBR not pushed
INot available INot available
I
I (E=l), RTI PBR
I
I
I
I not pulled (E=l) , I
I
I
IPBR pushed (E=O), I
I
I
1RTI PBR pulled
I
I
I
I (E=O)
I
I
I
IML-=O during ReadIML-=O during
INot available
I
IModify and Write IModify and
I
I
I________________~~----------~--~~----~------------I
MARCH 1990
46
THE WESTERN DESIGN CENTER, INC.
WDC
W65C832 I
W65C8l6/802
I
W65C02
NMOS 6502 IExtra read of
IExtra read of
I10. Indexed Across Page IExtra read of
Boundary (d),Yia,x; I invalid address. Ilast instructionlinvalid address. I
a,y
I (Note 1)
Ifetch.
I
Ill.ROY Pulled During IIgnored (E-l) forlProcessor stops. IIgnored. I
Write Cycle
IW65C816 only.
I
I
I
IProcessor stops I
I
I
I (E=O) .
I
I
or. 1:1,2:. WAI & STP instruct. IAvailable
IAvailable
INot available r- 113.Unused OP Codes
lOne reserved OP INo operation.
IUnknown and some '" · I
I Code specified as I
I"hang up" -,. f
I WDM will be used I
I processor. I
Iin future systems I
,I I
I The W65C816
I
I
I
Iperforms a noI
I
J
I operation.
I
I
LPBR=OO after re- INot available
INot available '(:':-114.Bank Address
:r:r ';cf '':;Handling
I set or interrupts I
I
;:'?':;l15~; R/W';' During ReadI E=l, R/W-=O during IR/W-=O only dur-I R/W-=O during ",,,:,cY::,')M6dify-Write
IModify and Write Iing Write cycle. IModify and Write PC.l''''P,;, Instructions
I cycles. E=O, R/W-= I
Icycles. , I
I 0 only during
I
I
~,[ f';;:'c~/
IWrite cycle.
I
I
. 116.Pin 7
IW65C802=SYNC.
ISYNC
ISYNC ':-~1
..
IW65C816=VPA
I
I
.. 117.COP Instruction
IAvailable
INot available
INot available .. I . ,,: Signatures 00-7F
I
I
I
--'r=' defined. Signatures I I
I
I--~~~~~~~--~------------~------------~-------------8.1
Stack Addressing
When in the Native mode, the Stack may use memory locations 000000 to OOFFFFF.
The effective address of Stack, Stack Relative, and Stack Relative Indirect
Indexed- addressing modes will always be within this range.
In the Emulation
mode, the Stack address range is 000100 to OOOlFF.
The following opcodes and
addressing modes will increment or decrement beyond this range when accessing
two or three bytes.
JSL; JSR(a, x); PEA, PEl, PER, PHD, PLD, RTL; d, Si (d, s), y
8.2
Direct Addressing
8.2.1 The Direct Addressing modes are often used to access memory registers
and pointers.
The effective address generated by Direct; Direct,X and
Direct,Y addressing modes will always be in the Native mode range 000000
to OOFFFF. When in the Emulation mode, the direct addressing range is
000000 to OOOOFF, except for [Direct] and [Direct], Y addressing modes
and the PEl instruction which will increment from OOOOFE or OOOOFF into
the Stack area.
MARCH 1990
47
WOC THE WESTERN DESIGN CENTER, INC.
8.2.2 When in the Emulation mode and DH is not
addressing range is OODHOO to OODHFF, except
addressing modes and the PEI instruction
OODHFE or OODHFF into the next higher page.
8.2.3 When in the Emulation mode and DL in not
addressing range is 000000 to OOFFFF.
8.3
W65C832 equal to zero, the direct
for [Direct] and [Direct],Y
which will increment from
equal to zero, the direct
Absolute Indexed Addressing
The Absolute Indexed addressing modes are used to address data outside the
direct addressing range.
The W65C02 and W65C832 addressing range is OO(}:O to
FFFF. Indexing from page FFXX may result in a OOYY data fetch when using the
W65C02 or w65C832.
In contrast, indexing from page ZZFFXX may result in
ZZ+l,OOYY when using the W65C832.
8.4
ABORT- Input
:-
I
I
8.4.1 ABORT- should be held low for a period no~to exceed one cyp 1e!; "Also I
i f ABORT- is held low during the Abort Interrupt sequencer: the Abort
Interrupt will be aborted.
It is not recommended to. abort.:;the:_~bort
Interrupt. The ABORT- internal latch is cleared during the sel?9~d cycle
of the Abort Interrupt. Asserting the ABORT- input after ~1!e ·~ollqwing
instruction cycles will cause registers to be modified:
.
8.4.1.1
Read-Modify-Write:
Processor status modified if ABORTT is
asserted after a modify cycle.
.
8.4.1.2
RTI:
Processor status modified if ABORT- is asserted"after
cycle 3.
8.4.1.3
IRQ-, NMI -, ABORT- BRRI COP:
When ABORT- is asserted' after
cycle 2, PBR and DBR will become 00 (Emulation mode) or PBRwill become
00 (Native mode).
8.4.2 The Abort- Interrupt has been designed for virtual memory systems. For
this reason l asynchronous ABORT/s- may cause undesirable results due to
the above conditions.
8.5
VDA and VPA Valid Memory Address Output Signals
When VDA or VPA are high and during all write cycles, the Address Bus is always
valid. VDA and VPA should be used to qualify all memory cycles. Note that
when VDA and VPA are both low l invalid addresses may be generated.
The Page
and Bank addresses could also be invalid.
This will be due to low byte
addition only.
The cycle when only low byte addition occurs is an optional
cycle for instructions which read memory when the Index Register consists of 8
bits. This optional cycle becomes a standard cycle for the Store instruction,
all instructions using the 16-bit Index Register mode, and the
Read-Modify-Write instruction when using 8- or 16-bit Index Register modes.
8.6
Apple II, IIe l IIc and II+ Disk Systems
VDA and VPA should not be used to qualify addresses during disk operation on
Apple systems.
Consult your Apple representative for hardware/software
configurations.
MARCH 1990
48
WDG THE WESTERN DESIGN CENTER, INC.
W65C832
DBIBA Qperation when ROy is Pulled Low
8.7
When RDY is low, the Data Bus is held in the data transfer state (i.e., PHI2
high) .'rhe Bank address external transparent latch should be latched when the
. PHI2clo.ek or RDY is .low.
8 !.%' M(X Output:·.
:..:1.:)
·~"'.S.
',.:
The MIX output reflects the valid of theM and X bits of the processor Status
iL ·~:Re,giS.ter{.
·The REP, SEP and PLP .instructions may change the state of the M and
X bits.
Note that the NIX output is :invalid. during the instruction cycle
following REP, SEP and PLP instruction execution.
This cycle is used as the
opcode fetch cycle of the next instruction.
::::: s:-: ,:":';
,'J::7"',~ .::.. . :
- ,:.:; ':'
8.9.1 It should be noted that all opcodes function in all modes of operation.
However, some instructions and addressing modes are intended for W65C832
24-bit addressing and are therefore less useful for the W65C832.
The
KG';:
i:oUQwing is a;; list of instructions and addressing modes which are
,!9:;8r.:'.~::..:; ~:t"t.marily intended for .W·65C832 use:
j:::od.e ~_ " .!.J JSL;RTL; Cd] i Cd] ,YiJMP aliJMLial,al,x 8L'j.r·.a;~9 .:?-.:Th~:o following .instru~tions may be used with the W65C832 even though a JX91! 5::~ ~·~nck AO,dress is not multiplexed on the Data Bus: 9dj ~~ r~L~' :.PHKiPHB;PLB
.
:-;f. ~:t9;.~,.l'Deot'01lowing instructions have "limited" use in the Emulation mode: ... ~ "..... ;.8: 9.3 .. 1 The REP and SEP instructions cannot modify the M and X bits when ""~:',l
... in Jpe Emulation mode.
In this mode the M and X bits will always be high
F
.~
.••
.• . ; , ;
•. .J.
;_~ ~ :~log~c
~' . -~.:.
1).
8.9.3.2 When in the Emulation mode, the MVP and MVN instructions use the
X and Y Index Registers for the memory address.
Also, the MVP and MVN
illstructions can only move data within the memory range 0000 (Source
Bank) to OOFF (Destination Bank) for the W65C832, and 0000 to OOFF for
the ~W65C832.
.
­
8 ..19~n~lir~.9t . J~ps
:. .,¥he JMP (a) ,and JML .(a) instructions use the direct Bank for indirect
addressing, while JMP (a, x) and JSR (a, x) use the Program Bank for indirect
address tables.
8.11 Switching Modes
-
1..:_ '
.. WhE;n switching from the Native mode to the Emulation mode, the X and M bits of
the Status Register are set high (logic 1), the high byte of the Stack is set
to 01, and the high bytes of the X and Y Index Registers are set to 00.
To
save previous values, these bytes must always be stored before changing modes.
Note that the low byte of the S, X and Y Registers and the low and high byte of
the Accumulator (A and B) are not affected by a mode change.
MARCH 1990
49
WDC THE WESTERN
DESIGN~CENTER,
W65C832,
INC.
8.12 How Hardware Interrupts, BRK, and COP Instructions Affect the Program Bank and
the Data Bank Registers
8.12.1 When in the Native mode, the Program Bank register (PBR) is cleared to
00 when a hardware interrupt, BRK or COP is executed.
Ift' the· Native
mode, previous PBR contents is automatically saved on Stack.
8.12.2 In the Emulation mode, the PBR and DBR registers are cleared to OO.when i?
a hardware interrupt, BRK or COP is executed.
In this case, previous
contents of the PBR are not automatically saved.
'.,
"
8.12.3 Note that a Ret urn from .,Interrupt (RTI) should always be executed' '~·from
the same "mode" which originally ~gEm'erated the interrupt~
~
,
8.13 Binary Mode
The Binary Mode is set whenever a :tta:tdwitre"'r~,softwate,14..nte~rupt:r-:j,s,)':zexeGuted.· 8
The D flag within the Status Register is cleared to zero.
J'~~.:":. i:.~jf):'y
::'C.-L
~":_... " __ .~:
:"'7
l ,
~'
,8
8.14 WAI Instruction
The WAI instruction pulls RDY low and 'places the p~ocessor· ,in' -the WAI "low
power" mode. NMI-, IRQ- or RESET will termina'te the' WAI~.conditiotr alld transfer
control to the interrupt handler routine: Note that an ABORT~ input will abort
the WAI instruction, but will not restart the;· processor.
When;':·the. tStatus
Register I flag is set (IRQ- disabled), the IRQ.:- interrupt will ca1fie the next
instruction (following the WAI instruction) to be executed without going to the
IRQ- interrupt handler. This method results in the highest' speedtespense~:
an
IRQ- input. When an interrupt is received after an ABORT- whic~ocaurs during
the WAI instruction, the processor will return to the 'WAI instruction. Other
than RES- (highest priority), ABORT- is the next highest priority, ~followed by ,
NMI- or IRQ- interrupts.
• ~
te
8.15 The STP instruction disables the PHI2 clock to all circuitry. When disabled,
the PHI2 clock is held in the high state.
In this case, the Dta Bus will
remain in the data transfer state and the Bank address will notb~ multiplexed
onto the Data Bus. Upon executing the STP instruction, the RES- signal is the
only input which can restart the processor.
The processor 'is . r-e'started 'by t
enabling the PHI2 clock, which occurs on the falling edge of the RES- input.
Note that the external oscillator must be--stable, and ,operating p'roperly before
RES- goes high.
..
-,. .
- ,
8.16 COP Signatures
':"
Signatures 00-7F may be user defined, while signatures 80-FF are reserved for
instructions on future microprocessors:~ ::,c:contact WDC for software-·emulation of
future microprocessor hardware functio{ls ~, .,[
8.17 WDM Opcode Use
The WDM opcode will be used on future microprocessors.
MARCH 1990
50
'.,
WDC
THE WESTERN DESIGN CENTER, INC.
W65C832
S.18 ROY Pulled During Write
The NMOS 6502 does not stop during a write operation. In contrast, both the
W65C02 and the W65C832 do stop during write operations.
The W65C832 stops
during a write when in the Native mode, but does not stop when in the Emulation
mode.
8.19 MVN and MVP Affects on the Data Bank Register
The MVN and MVP instructions change the Data Bank Register to the value of the
second byte of the instruction (destination bank address) .
8.20 Interrupt Priorities
The following interrupt priorities will be in effect should more than one
interrupt occur at the same time:
RES­
ABORT­
NMI­
IRQ-
Highest Priority Lowest Priority 8.21 Transfers from differing register sizes
All transfers from one register to another will result in a full 32-bit output
from the source register.
The destinat·ion register size will determine the
number of bits actually stored in the destination register and the values
stored in the processor Status Register.
The following are always 16-bit
transfers, regardless of the accumulator size:
TASiTSAiTADiTDA
8.22 Stack Transfers
When in the W65C02 Emulation mode, a 01 is forced into the high byte of the
16-bit stack pointer. When in the Native mode or W65C816 Emulation mode, the A
Accumulator is transferred to the 16-bit stack pointer. Note that in both the
Emulation and Native modes, the full 16 bits of the Stack Register are
transferred to the A Accumulator regardless of the state of the M bit in the
Status Register.
8.23 REP/SEP
WDC had problems using the REP and SEP instructions in early versions of the
high-speed W65C816 and W65CS02 devices and has been corrected on all W65CS32
devices.
MARCH 1990
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