ETC 7700

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER
/ 7700 SERIES
7700
Family
Software Manual
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
● These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
● Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
● Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor when considering the
use of a product contained herein for any specific purposes, such as apparatus
or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea
repeater use.
● The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
● If these products or technologies are subject to the Japanese export control
restrictions, they must be exported under a license from the Japanese government
and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of
JAPAN and/or the country of destination is prohibited.
● Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.
Preface
This manual has been prepared to enable the users of
the 7700 Family CMOS 16-bit microcomputers to better understand the instruction set and the features so
that they can utilize the capabilities of the microcomputers to the fullest. This manual presents detailed
descriptions of the instructions and addressing modes
available for the 7700 Family microcomputers.
For the hardware descriptions of the 7700 Family
microcomputers and descriptions of various development support tools (e.g., assembler, debugger, and so
on.), please refer to the user's manuals and operating
guidebooks for the respective hardware and software
products.
List of tables
Table of contents
CHAPTER 1. DESCRIPTION
1.1 Description .............................................................................................................................. 1-2
CHAPTER 2. CENTRAL PROCESSING UNIT (CPU)
2.1 Central Processing Unit (CPU) ........................................................................................... 2-2
CHAPTER 3. ADDRESSING MODES
3.1 Addressing Modes ................................................................................................................. 3-2
3.2 Explanation of addressing mode........................................................................................ 3-2
CHAPTER 4. INSTRUCTIONS
4.1 Instruction set ......................................................................................................................... 4-2
4.2 Description of instructions .................................................................................................. 4-7
4.3 Notes for programming .................................................................................................... 4-129
CHAPTER 5. INSTRUCTION EXECUTION SEQUENCE
5.1 Change of the CPU basic clock φ CPU ................................................................................................... 5-2
5.2 Instruction execution sequence .......................................................................................... 5-3
CHAPTER 6. CPU INSTRUCTION EXECUTION SEQUENCE FOR EACH ADDRESSING MODE
ii
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions ............................................................................................ 7-2
APPENDIX.2 Hexadecimal Instruction Code Table ............................................................. 7-18
7700 FAMILY SOFTWARE MANUAL
iii
CHAPTER 1
DESCRIPTION
1.1 Description
DESCRIPTION
1.1 DESCRIPTION
1.1 Description
The 7700 Family software offer the following features.
1.1.1 7700 Series, 7770 Series, and 7790 Series software features
● m and x flags are used to select between word and byte operation enabling most instructions to be
implemented with 1-byte operation code (reduces application ROM size)
● Powerful addressing modes, and fast and compact instruction set
● Direct page mapping function and memory oriented software system by direct paging
● The usual 64K bytes program memory boundary can be ignored for the practical purposes, and
programs can be written to utilize the full 16M bytes of memory space
● For data memory linear as well as bank memory accessing are supported
● Bit manipulation instructions and bit test and branch instructions can be used for memory and I/O
accessing of the entire 16M bytes space
● Block transfer instruction capable of handling blocks of up to 64K bytes each
● Decimal arithmetic instruction execution requiring no software compensation
1.1.2 7750 Series software features
The 7750 Series software is based on the Mitsubishi original 16-bit microcomputer 7700 Series and provides
enhanced signed operation instructions. The signed operation enhancement is realized by additional instructions,
instruction code and execution cycle of 7750 Series are completely compatible with those of conventional 7700
Series instructions.
In addition to the 7700 Series, 7770 Series, and 7790 Series software features, the 7750 Series software offer
the following features.
● Upward compatibility for the 7700 Series
● Signed operation enhancements through signed divide/multiply, arithmetic shift right, and sign/zero
extension instruction support
In this manual, 7700 Series software is described unless otherwise noted.
1–2
7700 FAMILY SOFTWARE MANUAL
CHAPTER 2
CENTRAL PROCESSING
UNIT (CPU)
2.1 Central processing unit (CPU)
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
2.1 Central processing unit (CPU)
The CPU of 7700 Series has the ten registers as shown in Figure 2.1.1. Each of these registers is described
below.
2.1.1 Accumulator (Acc)
Accumulators A and B are available and each can be used as 8-bit or 16-bit register as necessary.
(1) Accumulator A (A)
Accumulator A is the main register of the microcomputer. Data operations such as calculations, data
transfer, and input/output are executed mainly through accumulator A. It consists of 16 bits, and the
low-order 8 bits can be also used separately. The data length flag (m) determines whether the register
is used as a 16-bit register or as an 8-bit register. It is used as a 16-bit register when the flag m is
“0”, and as an 8-bit register when the flag m is “1”. The flag m is a part of the processor status register
(PS) which is described later. When an 8-bit register is selected, the low-order 8 bits of the accumulator A are used and the contents of the high-order 8 bits are unchanged.
(2) Accumulator B (B)
Accumulator B is a 16-bit register with the same function as accumulator A. The instructions of 7700
Series can use accumulator B instead of accumulator A, but the use of accumulator B requires more
instruction bytes and execution cycles than accumulator A. Accumulator B is also controlled by the
data length flag m just as in accumulator A.
2.1.2 Index register X (X)
Index register X consists of 16 bits and the low-order 8 bits can be also used separately. The index register
length flag (x) determines whether the register is used as a 16-bit register or as an 8-bit register. It is used
as a 16-bit register when the flag x is “0” and as an 8-bit register when the flag x is “1”. The flag x is a
part of the processor status register (PS) which is described later. When an 8-bit register is selected, the
low-order 8 bits of the index register X are used and the contents of the high-order 8 bits are unchanged.
In addressing mode in which the index register X is used as the index register, the contents of this register
is added to obtain the real address.
When executing the block transfer instruction MVP or MVN, the contents of the index register X indicate
the low-order 16 bits of the source data address. The third byte of the MVP or MVN instruction is the highorder 8 bits of the source data address.
2.1.3 Index register Y (Y)
Index register Y is a 16-bit register with the same function as index register X. Just as in index register
X, the index register length flag (x) determines whether this register is used as a 16-bit register or as an
8-bit register.
When executing the block transfer instruction MVP or MVN, the contents of the index register Y indicate
the low-order 16 bits of the destination data address. The second byte of the MVP or MVN instruction is
the high-order 8 bits of the destination data address.
2–2
7700 FAMILY SOFTWARE MANUAL
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
b15
b0
b8 b7
AH
b15
b0
b8 b7
BH
b15
Accumulator B (B)
BL
b0
b8 b7
XH
Index register X (X)
XL
b15
b0
b8 b7
YH
b15
YL
Index register Y (Y)
b0
b8 b7
SH
b7
Accumulator A (A)
AL
Stack pointer (S)
SL
b0
Data bank register (DT)
DT
b16 b15
b23
b8 b7
PG
b0
PCH
b7
Program counter (PC)
PCL
b0
Program bank register (PG)
b15
b0
b8 b7
DPRH
b15
DPRL
b0
b8 b7
PSH
b15
0
b10
0
0
0
0
Direct page register (DPR)
b9 b8 b7 b6
IPL
N V
Processor status register (PS)
PSL
b5 b4 b3 b2
b1
b0
m
Z
C
x
D
I
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level
Fig. 2.1.1 CPU registers structure
7700 FAMILY SOFTWARE MANUAL
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CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
2.1.4 Stack pointer (S)
Stack pointer S is a 16-bit register. It is used for a subroutine call or an interrupt. It is also used for
addressing modes using the stack. The contents of the stack pointer S indicate the address (stack area)
for storing registers during subroutine calls and interrupts.
When an interrupt request is accepted, the contents of the program bank register PG is stored at the
address indicated by the contents of the stack pointer S, and the contents of the stack pointer S are
decremented by 1. Then the contents of the program counter PC and the processor status register PS
(PCH, PCL , PSH, PS L) are stored. The contents of the stack pointer S after accepting an interrupt request
are equal to the contents of the stack pointer S before the accepting of the interrupt request decremented
by 5.
Figure 2.1.2 shows the stored registers before an interrupt routine.
When returning to the original routine after processing the interrupt routine by executing the RTI instruction,
the registers stored in the stack area are restored to the original registers in the reverse sequence and the
contents of the stack pointer are returned to the numerical value before the accepting of interrupt request.
The same operation is performed during a subroutine call, but the contents of the processor status register
PS are not automatically stored. (The contents of the program bank register PG may not be stored. It
depends on the addressing mode.)
The user is responsible for storing registers other than those described above with a program during
interrupts or subroutine calls.
Additionally, the stack pointer S must be initialized at the beginning of the program because its contents
are undefined at reset. The stack area changes when subroutines are nested or when multiple interrupt
requests are accepted. Therefore, make sure necessary data in the internal RAM are not destroyed when
nesting subroutines.
Stack area
Address
S–5
S–4
Processor status register’s low-order byte (PSL)
S–3 Processor status register’s high-order byte (PSH)
S–2
Program counter’s low-order byte (PCL)
S–1
Program counter’s high-order byte (PCH)
S
Program bank register (PG)
❈ “S” is the initial address that the stack pointer (S)
indicates at accepting an interrupt request.
The S’s contents become “S–5” after storing the
above registers.
Fig. 2.1.2 Stored registers before an interrupt routine
2–4
7700 FAMILY SOFTWARE MANUAL
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
2.1.5 Program counter (PC)
Program counter PC is a 16-bit counter that indicates the low-order 16 bits of the next program memory
address (24 bits) to be executed. The contents of the high-order program counter (PC H) become “FF16 ”,
and the low-order program counter (PC L) become “FE16 ” at reset. The contents of the program counter PC
become the contents of the reset vector address (addresses FFFE 16 , FFFF16 ) after removing reset status.
Figure 2.1.3 shows the program counter PC and the program bank register PG.
b23
b16 b15
PG
b8 b7
PCH
b0
PCL
Fig. 2.1.3 Program counter PC and program bank register PG
2.1.6 Program bank register (PG)
Program bank register PG is an 8-bit register that indicates the high-order 8 bits (referred to as bank) of
the next program memory address (24 bits) to be executed.
When a carry occurs after adding the contents of the program counter PC and other factors, the contents
of the program bank register PG are automatically incremented by 1. When a borrow occurs after subtracting the contents of the program counter PC, the contents of the program bank register PG are automatically
decremented by 1. Accordingly, there is no need to consider bank boundaries, usually.
This register is cleared to “0016 ” at reset.
In single-chip mode, keep the program bank register PG “0016” because the access within bank 016 is only
allowed. Be sure that prevent the program bank register PG from being set to a value other than “00 16 ”
by executing the instructions of branch and so on.
This register is cleared to “0016 ” at reset.
7700 FAMILY SOFTWARE MANUAL
2–5
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
2.1.7 Data bank register (DT)
Data bank register DT is an 8-bit register. With some addressing modes using the data bank register DT,
the contents of this register are used as the high-order 8 bits (bank) of a 24-bit address.
Use the LDT instruction to set the value in this register.
Set the only “0016 ” in single-chip mode because the access within bank 016 is only allowed.
This register is cleared to “0016 ” at reset.
2.1.8 Direct page register (DPR)
Direct page register DPR is a 16-bit register. The contents of this register indicate the direct page area
which is allocated in bank 0 16 or in the area across banks 0 16 and 1 16. This area can be accessed with
2 bytes❈ by using the direct page addressing mode.
The contents of the DPR are the base address (the lowest address) of the direct page area which extends
to 256 bytes above this address. The DPR can contain a value from 000016 to FFFF16 . However, set a
value from 000016 to FF00 16 in single-chip mode because the access within bank 0 16 is only allowed.
If it contains a value equal to or more than “FF0116 ”, the direct page area spans the area across banks
0 16 and 116. If the low-order 8 bits of the DPR is “0016 ”, the number of cycles required to generate an
address is smaller by 1 cycle than the number if its contents are not “0016”. Accordingly, the low-order 8
bits of the DPR should usually be set to “0016 ”.
This register is cleared to “000016 ” at reset. Figure 2.1.4 shows a setting example of the direct page with
the direct page register (DPR).
❈ With 3 bytes for DIV and MPY instructions, and 1 byte is added for all instructions when using accumulator B.
016
016
DPR area when DPR=0000 16
FF16
12316
Bank 016
22216
DPR area when DPR=0123 16
(Note 1)
FF1016
FFFF16
1000016
1000F16
DPR area when DPR=FF10 16
(Note 2)
Bank 116
Note 1 : The number of execution cycles is incremented by 1 when the low-order 8 bits of the
DPR are not “00 16 ”.
Note 2 : The direct page area spans the area across banks 016 and 116 when the DPR is “FF0116 ”
or more.
Fig. 2.1.4 Setting example of direct page with direct page register (DPR)
2–6
7700 FAMILY SOFTWARE MANUAL
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
2.1.9 Processor status register (PS)
Processor status register is an 11-bit register. It consists of the flags to indicate the result of operation and
the processor interrupt priority level. The flags C, Z, V, and N are tested by branch instructions.
Figure 2.1.5 shows the structure of the processor status register.
The details of the processor status register flags are described below.
b15 b14 b13 b12 b11 b10 b9
0
0
0
0
0
IPL
b8
b7
b6
b5
b4
b3
b2
b1
b0
N
V
m
x
D
I
Z
C
Note: Bits 11 to 15 are always “0” when the contents of the processor status register are read.
Fig. 2.1.5 Processor status register structure
(1) Carry flag (C)
The carry flag is assigned to bit 0 of the processor status register. It contains the carry or borrow bit
from the arithmetic and logic unit (ALU) after an arithmetic operation. This flag is also affected by shift
and rotate instructions. This flag can be set with the SEC or SEP instruction and cleared with the CLC
or CLP instruction.
(2) Zero flag (Z)
The zero flag is assigned to bit 1 of the processor status register. It is set to “1” when the result of
an arithmetic operation or data transfer is zero, and cleared to “0” when otherwise. This flag can be
set with the SEP instruction and cleared with the CLP instruction.
Note: This flag has no meaning in decimal mode addition (the ADC instruction).
(3) Interrupt disable flag (I)
The interrupt disable flag is assigned to bit 2 of the processor status register. It disables all maskable
interrupts (interrupts other than watchdog timer, the BRK instruction, and zero division). Interrupts are
disabled when this flag is “1”. When an interrupt request is accepted, this flag is automatically set to
“1” to avoid multiple interrupts. This flag can be set with the SEI or SEP instruction and cleared with
the CLI or CLP instruction. This flag is set to “1” at reset.
(4) Decimal mode flag (D)
The decimal mode flag is assigned to bit 3 of the processor status register. It determines whether
addition and subtraction are performed in binary or decimal. Binary arithmetic is performed when this
flag is “0”. When it is “1”, decimal arithmetic is performed with each word treated as two or four digits
decimal (determined by the data length flag m). Decimal adjust is performed automatically. Decimal
operation is possible only with the ADC and SBC instructions. This flag can be set with the SEP
instruction and cleared with the CLP instruction. This flag is cleared to “0” at reset.
(5) Index register length flag (x)
The index register length flag is assigned to bit 4 of the processor status register. It determines
whether the index register X and index register Y are used as a 16-bit register or an 8-bit register.
The register is used as a 16-bit register when this flag x is “0”, and as an 8-bit register when it is “1”.
This flag can be set with the SEP instruction and cleared with the CLP instruction. This flag is cleared
to “0” at reset.
❈ When transferring between different bit lengths, the data is transferred with the length of the
destination register, but except for the TXA, TYA, TXB, and TYB instructions.
7700 FAMILY SOFTWARE MANUAL
2–7
CENTRAL PROCESSING UNIT (CPU)
2.1 Central processing unit (CPU)
(6) Data length flag (m)
The data length flag is assigned to bit 5 of the processor status register. It determines whether to treat
data as a 16-bit unit or as an 8-bit unit. A data is treated as a 16-bit unit when this flag m is “0”, and
as an 8-bit unit when it is “1”.
This flag can be set with the SEM or SEP instruction and cleared with the CLM or CLP instruction.
This flag is cleared to “0” at reset.
❈ When transferring between different bit lengths, the data is transferred with the length of the
destination register, but except for the TXA, TYA, TXB, and TYB instructions.
(7) Overflow flag (V)
The overflow flag is assigned to bit 6 of the processor status register. It is used when adding or
subtracting a word as signed binary. In case the data length flag m is “0”, the overflow flag is set to
“1” when the result of addition or subtraction is outside the range between –32768 and +32767, and
cleared to “0” in all other cases. In case the data length flag m is “1”, the overflow flag is set to “1”
when the result of addition or subtraction is outside the range between –128 and +127, and cleared
to “0” in all other cases. The overflow flag can be set with the SEP instruction and cleared with the
CLV or CLP instructions.
Note : This flag has no meaning in decimal mode.
(8) Negative flag (N)
The negative flag is assigned to bit 7 of the processor status register. It is set to “1” when the result
of arithmetic operation or data transfer is negative (data bit 15 is “1” when the data length flag m is
“0”, or data bit 7 is “1” when the data length flag m is “1”). It is cleared to “0” in all other cases. This
flag can be set with the SEP instruction and cleared with the CLP instruction.
Note : This flag has no meaning in decimal mode.
(9) Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) is assigned to bits 8, 9, and 10 of the processor status
register. These three bits determine the priority level of processor interrupts from level 0 to level 7.
The interrupt is enabled when the interrupt priority level of a required interrupt (set with the interrupt
control register) is higher than IPL. When an interrupt request is accepted, the IPL is stored in the
stack and IPL is replaced by the interrupt priority level of the accepted interrupt request. This simplifies control of multiple interrupts.
There are no instructions to directly set or clear the IPL. It can be changed by placing the new IPL
on the stack and updating the processor status register with the PUL or PLP instruction.
The contents of the IPL are cleared to “0002 ” at reset.
2–8
7700 FAMILY SOFTWARE MANUAL
CHAPTER 3
ADDRESSING
MODES
3.1 Addressing modes
3.2 Explanation of addressing
modes
ADDRESSING MODES
3.1 Addressing Modes, 3.2 Explanation of Addressing Modes
3.1 Addressing Modes
When executing an instruction, the address of the memory location from which the data required for arithmetic
operation is to be retrieved or to which the result of arithmetic operation is to be stored must be specified in
advance. Address specification is also necessary when the control is to jump to a certain memory address
during program execution. Addressing refers to the method of specifying the memory address.
The 7700 Series microcomputers support 28 different addressing modes, offering extremely versatile and
powerful memory accessing capability.
3.2 Explanation of Addressing Modes
Each of the 28 addressing modes is explained on the pages indicated below:
Implied addressing mode .......................................................................... 3-3
Immediate addressing mode ..................................................................... 3-4
Accumulator addressing mode .................................................................. 3-6
Direct addressing mode ............................................................................ 3-7
Direct bit addressing mode ....................................................................... 3-9
Direct indexed X addressing mode ........................................................ 3-11
Direct indexed Y addressing mode ........................................................ 3-14
Direct indirect addressing mode ............................................................. 3-15
Direct indexed X indirect addressing mode ........................................... 3-17
Direct indirect indexed Y addressing mode ........................................... 3-20
Direct indirect long addressing mode ..................................................... 3-23
Direct indirect long indexed Y addressing mode ................................... 3-25
Absolute addressing mode ...................................................................... 3-28
Absolute bit addressing mode ................................................................ 3-31
Absolute indexed X addressing mode .................................................... 3-33
Absolute indexed Y addressing mode .................................................... 3-36
Absolute long addressing mode ............................................................. 3-39
Absolute long indexed X addressing mode............................................ 3-41
Absolute indirect addressing mode ......................................................... 3-43
Absolute indirect long addressing mode ................................................ 3-44
Absolute indexed X indirect addressing mode ....................................... 3-45
Stack addressing mode ........................................................................... 3-46
Relative addressing mode ....................................................................... 3-49
Direct bit relative addressing mode ........................................................ 3-50
Absolute bit relative addressing mode ................................................... 3-52
Stack pointer relative addressing mode ................................................. 3-54
Stack pointer relative indirect indexed Y addressing mode .................. 3-55
Block transfer addressing mode ............................................................. 3-58
Note. On the pages below, the instructions with the mark “ * ” can be used in the 7750 Series only.
3–2
7700 FAMILY SOFTWARE MANUAL
Implied
Mode
:
Implied addressing mode
Function
:
The single-instruction inherently address an internal register.
Instruction :
BRK,
RTS,
TBY,
TYX,
CLC,
SEC,
TDA,
WIT,
ex. : Mnemonic
CLC
CLI,
SEI,
TDB,
XAB
CLM,
SEM,
TSA,
CLV,
STP,
TSB,
DEX,
TAD,
TSX,
DEY,
TAS,
TXA,
INX,
TAX,
TXB,
INY,
TAY,
TXS,
NOP,
TBD,
TXY,
RTI,
TBS,
TYA,
RTL,
TBX,
TYB,
Machine Code
1816
PS
C flag
? ? ? ? ? ? ? ? ? ? ?
PS
? ? ? ? ? ? ? ? ? ? 0
ex. : Mnemonic
TXA
(m=1, x=1)
Machine Code
8A16
l l16
X
The upper-byte is
not transferred.
A
l l16
8A16
ex. : Mnemonic
TXA
(m=0, x=0)
Machine Code
8A16
X
hh16
l l16
A
hh16
l l16
7700 FAMILY SOFTWARE MANUAL
3–3
Immediate
Mode
:
Function
:
Instruction :
Immediate addressing mode
A portion of the instruction is the actual data. Such instruction code may cross over the bank
boundary.
ADC,
LDY,
AND,
MPY,
ex. : Mnemonic
ADC A, #0A5H
(m=1)
CLP, CMP,
MPYS*, ORA,
CPX,
RLA,
CPY,
SBC,
DIV,
SEP
DIVS*, EOR,
Machine Code
6916 A516
Memory
PG 000016
Op Code (6916)
A ← A+C+ A516 ←
bank PG
Operand (A516)
PG FFFF16
ex. : Mnemonic
ADC A, #0A5B7H
(m =0)
Machine Code
6916 B716 A516
Memor y
PG 000016
Op Code (69 16)
A ← A+C + A516 B716
←
bank PG
Operand (B716)
Operand (A516)
PG FFFF16
ex. : Mnemonic
LD X #0A 5H
(x=1)
Machine Code
A216 A516
Memory
PG 0000 16
Op Code (A216)
X ←
A516 ←
bank PG
Operand (A516)
PG FFFF16
3–4
7700 FAMILY SOFTWARE MANUAL
LDA,
LDT,
LDX,
Immediate
ex. : Mnemonic
LDX #0A5B7H
(x=0)
Machine Code
A216 B716 A516
Memory
PG 000016
Op Code (A216)
X ← A516 B716 ←
bank PG
Operand (B716)
Operand (A516)
PG FFFF16
7700 FAMILY SOFTWARE MANUAL
3–5
Accumulator
Mode
:
Accumulator addressing mode
Function
:
The contents of accumulator are the actual data.
Instruction :
ASL,
ASR*, DEC,
ex. : Mnemonic
EXTS*, EXTZ*, INC,
LSR,
b7
Carry flag
b0
Accumulator A
ex. : Mnemonic
ROL A
(m=0)
Machine Code
2A16
b15
3–6
ROR
Machine Code
2A16
ROL A
(m=1)
Carry flag
ROL,
b0
Accumulator A
7700 FAMILY SOFTWARE MANUAL
Direct
Mode
:
Direct addressing mode
Function
:
The contents of the bank 016 memory location specified by the result of adding the second byte
of the instruction to the contents of the direct page register become the actual data. If, however,
addition of the instruction’s second byte to the direct page register’s contents result in a value that
exceeds the bank 016 range, the specified location will be in bank 1 16.
Instruction :
ADC,
LDA,
STX,
ex. : Mnemonic
ADC A, 02H
(m=1)
AND,
LDM,
STY
ASL,
LDX,
ASR*, CMP,
LDY, LSR,
CPX,
MPY,
CPY, DEC,
MPYS*,ORA,
DIV,
ROL,
DIVS*, EOR,
ROR, SBC,
INC,
STA,
Machine Code
6516 0216
Memory
000016
A ← A+C+ DATA ←
DATA
Bank 016
123616
FFFF16
Op Code (6516)
Operand (0216)
ex. : Mnemonic
ADC A, 02H
(m=0)
Direct Page
Register
+ 123416 = 123616
Machine Code
6516 0216
Memory
000016
A ← A+C+ DATAH DATAL ←
DATAL
123616
DATAH
123716
Bank 016
FFFF16
Op Code (6516)
Operand (0216)
Direct Page
Register
+ 123416 = 123616
7700 FAMILY SOFTWARE MANUAL
3–7
Direct
ex. : Mnemonic
LDX 02H
(x=1)
Machine Code
A616 0216
Memory
000016
X ← DATA ←
DATA
Bank 016
123616
FFFF16
ex. : Mnemonic
LDX 02H
(x=0)
Op Code (A616)
Direct Page
Register
Operand (0216)
+ 123416 = 123616
Machine Code
A616 0216
Memory
000016
X←
DATAH DATAL ←
DATAL
Bank 016
123616
DATAH
FFFF16
Op Code (A616)
Operand (0216)
3–8
Direct Page
Register
+ 123416 = 123616
7700 FAMILY SOFTWARE MANUAL
Direct Bit
Mode
:
Direct bit addressing mode
Function
:
Specifies the bank 016 memory location by the value obtained by adding the instruction’s second
byte to the direct page register’s contents, and specifies the positions of multiple bits in the
memory location by the bit pattern in the third and fourth bytes of the instruction (third byte only
when the m flag is set to 1). If, however, addition of the instruction’s second byte to the direct
page register’s contents result in a value that exceeds the bank 016 range, the specified location
will be in bank 116.
Instruction :
CLB, SEB
ex. : Mnemonic
CLB #5AH, 04H
(m=1)
Machine Code
1416 0416 5A16
(Before the instruction execution )
Memory
000016
Bank 016
? ? ? ? ? ? ? ? 123816
FFFF16
Op Code (1416)
Operand (0416)
Direct Page
Register
+ 123416 = 123816
Operand (5A16)
(After the instruction execution)
Memory
000016
? 0 ? 0 0 ? 0 ? 123816
Bank 016
FFFF16
7700 FAMILY SOFTWARE MANUAL
3–9
Direct Bit
ex. : Mnemonic
Machine Code
CLB #5AA5H, 04H
(m=0)
1416 0416 A516 5A16
(Before the instruction execution)
Memory
000016
Bank 016
? ? ? ? ? ? ? ? 123816
? ? ? ? ? ? ? ? 123916
FFFF16
Op Code (1416)
Operand (0416)
Direct Page
Register
+ 123416 = 123816
Operand (A516)
Operand (5A16)
(After the instruction execution)
Memory
000016
0 ? 0 ? ? 0 ? 0 123816
Bank 016
? 0 ? 0 0 ? 0 ? 123916
FFFF16
3–10
7700 FAMILY SOFTWARE MANUAL
Direct Indexed X
Mode
:
Direct indexed X addressing mode
Function
:
The contents of the bank 016 memory location specified by the result of adding the second byte
of the instruction, the contents of the direct page register and the contents of the index register
X become the actual data. If, however, addition of the instruction’s second byte, the direct page
register’s contents and the index register X’s contents results in a value that exceeds the bank 016
or bank 116 range, the specified location will be in bank 116 or bank 216.
Instruction :
ADC,
LDY,
AND,
LSR,
ex. : Mnemonic
ADC A, 1EH, X
(m=1, x=1)
ASL,
MPY,
ASR*, CMP,
MPYS*, ORA,
Machine Code
7516 1E16
DEC,
ROL,
DIV,
ROR,
DIVS*, EOR,
SBC, STA,
LDA,
LDM,
Memory
000016
A ← A+C+ DATA ←
INC,
STY
DATA
Bank 016
133816
FFFF16
ex. : Mnemonic
ADC A, 1EH, X
(m=0, x=1)
Op Code (7516)
Direct Page
Register
Index
Register X
Operand (1E16)
+ 123416 +
E616
= 133816
Machine Code
7516 1E16
Memory
000016
A ← A+C+ DATAH DATAL ←
DATAL
133816
DATAH
133916
Bank 016
FFFF16
Op Code (7516)
Direct Page
Register
Index
Register X
Operand (1E16)
+ 123416 +
E616
7700 FAMILY SOFTWARE MANUAL
= 133816
3–11
Direct Indexed X
ex. : Mnemonic
ADC A, 1EH, X
(m=1, x=0)
Machine Code
7516 1E16
Memory
000016
A ← A+C+ DATA ←
DATA
Bank 016
433816
FFFF16
ex. : Mnemonic
ADC A, 1EH, X
(m=0, x=0)
Op Code (7516)
Index
Direct Page
Register Register X
Operand (1E16)
+ 123416 + 30E616
= 433816
Machine Code
7516 1E16
Memory
000016
A ← A+C+ DATAH DATAL ←
DATAL
433816
DATAH
433916
Bank 016
FFFF16
3–12
Op Code (7516)
Direct Page Index
Register Register X
Operand (1E16)
+ 123416 + 30E616
7700 FAMILY SOFTWARE MANUAL
= 433816
Direct Indexed X
ex. : Mnemonic
LDY 1EH, X
(x=1)
Machine Code
B416 1E16
Memory
000016
Y ← DATA ←
DATA
Bank 016
133816
FFFF16
ex. : Mnemonic
LDY 1EH, X
(x=0)
Op Code (B416)
Direct Page
Register
Index
Register X
Operand (1E16)
+ 123416 +
E616
= 133816
Machine Code
B416 1E16
Memory
000016
Y ← DATAH DATAL ←
DATAL
433816
DATAH
433916
Bank 016
FFFF16
Op Code (B416)
Operand (1E16)
Direct Page Index
Register Register X
+ 123416 + 30E616
7700 FAMILY SOFTWARE MANUAL
= 433816
3–13
Direct Indexed Y
Mode
:
Direct indexed Y addressing mode
Function
:
The contents of the bank 016 memory location specified by the result of adding the second byte
of the instruction, the contents of the direct page register and the contents of the index register
Y become the actual data. If, however, addition of the instruction’s second byte, the direct page
register’s contents and the index register Y’s contents results in a value that exceeds the bank 016
or bank 116 range, the specified location will be in bank 116 or bank 216.
Instruction :
LDX,
ex. : Mnemonic
LDX 02H, Y
(x=1)
STX
Machine Code
B616 0216
Memory
000016
X ← DATA ←
DATA
Bank 016
131C16
FFFF16
ex. : Mnemonic
LDX 02H, Y
(x=0)
Op Code (B616)
Direct Page
Register
Index
Register Y
Operand (0216)
+ 123416 +
E616
= 131C16
Machine Code
B616 0216
Memory
000016
X ← DATAH DATAL ←
DATAL
131C16
DATAH
131D16
Bank 016
FFFF16
3–14
Op Code (B616)
Index
Direct Page
Register Register Y
Operand (0216)
+ 123416 + 00E616
7700 FAMILY SOFTWARE MANUAL
= 131C16
Direct Indirect
Mode
:
Direct indirect addressing mode
Function
:
The value obtained by adding the instruction’s second byte to the contents of the direct page
register specifies 2 adjacent bytes in memory bank 016, and the contents of these bytes in memory
bank DT (DT is contents of data bank register) become the actual data. If, however, the value
obtained by adding the instruction’s second byte and the direct page register’s contents exceeds
the bank 016 range, the specified location will be in bank 116.
Instruction :
ADC,
ex. : Mnemonic
ADC A, (1EH)
(m=1)
AND,
CMP,
DIV,
DIVS*, EOR,
LDA,
MPY,
MPYS*,ORA,
SBC,
STA
Machine Code
7216 1E16
Memory
000016
125216
DATA I (0116)
125316
DATA II (1216)
Bank 016
FFFF16
Direct Page
Register
123416 +
Op Code (7216)
Operand (1E16)
=
125216
Data Bank
Register
A ← A+C+ DATA ←
DATA
DT
7700 FAMILY SOFTWARE MANUAL
120116
3–15
Direct Indirect
ex. : Mnemonic
ADC A, (1EH)
(m=0)
Machine Code
7216 1E16
Memory
000016
125216
DATA I (0116)
125316
DATA II (1216)
Bank 016
FFFF16
Direct Page
Register
Op Code (7216)
123416 +
Operand (1E16)
=
125216
Data Bank
Register
A ← A+C+ DATAH DATAL ←
3–16
DATAL
DT
120116
DATAH
DT
120216
7700 FAMILY SOFTWARE MANUAL
Direct Indexed X Indirect
Mode
:
Direct indexed X indirect addressing mode
Function
:
The value obtained by adding the instruction’s second byte, the contents of the direct page register
and the contents of the index register X specifies 2 adjacent bytes in memory bank 016, and the
contents of these bytes in memory bank 0 16, and the contents of these bytes in memory bank DT
(DT is contents of data bank register) become the actual data. If, however, the value obtained by
adding the instruction’s second byte, the direct page register’s contents and the index register X’s
contents exceeds the bank 016 or bank 116 range, the specified location will be in bank 116 or bank
216.
Instruction :
ADC,
AND,
CMP,
DIV,
DIVS*, EOR,
LDA,
MPY,
MPYS*,ORA,
SBC,
STA
Machine Code
ex. : Mnemonic
ADC A, (1EH, X)
(m=1, x=1)
6116 1E16
Memory
000016
DATA I (0016)
133816
DATA II (1416)
133916
Bank 016
FFFF16
Op Code (6116)
Direct Page
Register
Index
Register X
Operand (1E16)
+ 123416 +
E616
= 133816
Data Bank
Register
A ← A+C+ DATA ←
DATA
DT
7700 FAMILY SOFTWARE MANUAL
140016
3–17
Direct Indexed X Indirect
ex. : Mnemonic
ADC A, (1EH, X)
(m=0, X=1)
Machine Code
6116 1E16
Memory
000016
DATA I (0016)
133816
DATA II (1416)
133916
Bank 016
FFFF16
Op Code (6116)
Direct Page
Register
Index
Register X
Operand (1E16)
+ 123416 +
E616
= 133816
Data Bank
Register
A ← A+C+ DATAH DATAL ←
ex. : Mnemonic
ADC A, (1EH, X)
(m=1, x=0)
DATAL
DT
140016
DATAH
DT
140116
Machine Code
6116 1E16
Memory
1000016
DATA I (0016)
1033816
DATA II (1416)
1033916
Bank 116
1FFFF16
Op Code (6116)
Direct Page
Index
Register Register X
Operand (1E16)
+ 123416 + F0E616
Data Bank
Register
A ← A+C+ DATA ←
3–18
DATA
DT
140016
7700 FAMILY SOFTWARE MANUAL
= 1033816
Direct Indexed X Indirect
ex. : Mnemonic
ADC A, (1EH, X)
(m=0, x=0)
Machine Code
6116 1E16
Memory
1000016
DATA I (0016)
1033816
DATA II (1416)
1033916
Bank 116
1FFFF16
Op Code (6116)
Operand (1E16)
Direct Page Index
Register Register X
+ 123416 + F0E616
= 1033816
Data Bank
Register
A ← A+C+ DATAH DATAL ←
DATAL
DT
140016
DATAH
DT
140116
7700 FAMILY SOFTWARE MANUAL
3–19
Direct Indirect Indexed Y
Mode
:
Direct indirect indexed Y addressing mode
Function
:
The value obtained by adding the instruction’s second byte and the contents of the direct page
register specifies 2 adjacent bytes in memory bank 0 16.
The value obtained by adding the contents of these bytes and the contents of the index register
Y specifies address of the actual data in memory bank DT (DT is contents of data bank register).
If, however, the value obtained by adding the contents of the instruction’s second byte and the
direct page register exceeds the bank 0 16 range, the specified location will be in bank 116. Also,
if addition of the contents of memory and index register Y generate a carry, the bank number will
be 1 larger than the contents of the data bank register.
Instruction :
ADC,
AND,
ex. : Mnemonic
ADC A, (1EH), Y
(m=1, x=1)
CMP,
DIV,
DIVS*, EOR,
LDA,
MPY,
MPYS*,ORA,
SBC,
STA
Machine Code
7116 1E16
Memory
Bank 016
125216
DATA I (0116)
125316
DATA II (1216)
Direct Page
Register
Op Code (7116)
123416 +
Operand (1E16)
+
=
125216
Data Bank
Register
A ← A+C+ DATA
3–20
←
DATA
DT
7700 FAMILY SOFTWARE MANUAL
12E716
Index
Register Y
E616
= 12E716
Direct Indirect Indexed Y
ex. : Mnemonic
ADC A, (1EH), Y
(m=0, x=1)
Machine Code
7116 1E16
Memory
Bank 016
125216
DATA I (0116)
125316
DATA II (1216)
Direct Page
Register
Op Code (7116)
123416 +
Operand (1E16)
Index
Register Y
+
E616
= 12E716
=
125216
Data Bank
Register
A ← A+C+ DATAH DATAL ←
ex. : Mnemonic
ADC A, (1EH), Y
(m=1, x=0)
Machine Code
7116 1E16
DATAL
DT
12E716
DATAH
DT
12E816
Memory
125216
DATA I (0116)
125316
DATA II (1216)
Direct Page
Register
Op Code (7116)
123416 +
Operand (1E16)
Bank 016
Index
Register Y
+ F0E616
= 102E716
=
125216
Data Bank
Register
A ← A+C+ DATA ←
DATA
DT
+1
02E716
Bank
7700 FAMILY SOFTWARE MANUAL
3–21
Direct Indirect Indexed Y
ex. : Mnemonic
ADC A, (1EH), Y
(m=0, x=0)
Machine Code
7116 1E16
Memory
Bank 016
125216
DATA I (0116)
125316
DATA II (1216)
Direct Page
Register
Op Code (7116)
123416 +
Operand (1E16)
Index
Register Y
+ F0E616
=
125216
Data Bank
Register
A ← A+C+ DATAH DATAL ←
DATAL
DT
+1
02E716
DATAH
DT
+1
02E816
Bank
3–22
7700 FAMILY SOFTWARE MANUAL
= 102E716
Direct Indirect Long
Mode
:
Direct indirect long addressing mode
Function
:
The value obtained by adding the instruction’s second byte and the contents of the direct page
register specifies 3 adjacent bytes in memory bank 016 , and the contents of these bytes specify
the address of the memory location that contains the actual data. If, however, the value obtained
by adding the contents of the instruction’s second byte and the direct page register exceeds the
bank 0 16 range, the specified location will be in bank 116. The 3 adjacent bytes memory location
may be spread over two different banks.
Instruction :
ADC,
AND,
ex. : Mnemonic
ADCL A, (1EH)
(m=1)
CMP,
DIV,
DIVS*, EOR,
LDA,
MPY,
MPYS*,ORA,
SBC,
STA
Machine Code
6716 1E16
Memory
Bank 016
125216
DATA I (EF16)
125316
DATA II (0116)
125416
DATA III (1216)
Direct Page
Register
Op Code (6716)
123416 +
Operand (1E16)
=
125216
A ← A+C+ DATA ←
DATA
1201EF16
7700 FAMILY SOFTWARE MANUAL
3–23
Direct Indirect Long
ex. : Mnemonic
ADCL A, (1EH)
(m=0)
Machine Code
6716 1E16
Memory
Bank 016
125216
DATA I (EF16)
125316
DATA II (0116)
125416
DATA III (1216)
Direct Page
Register
Op Code (6716)
123416 +
Operand (1E16)
=
125216
A ← A+C+ DATAH DATAL ←
3–24
DATAL
1201EF16
DATAH
1201F016
7700 FAMILY SOFTWARE MANUAL
Direct Indirect Long Indexed Y
Mode
:
Direct indirect long indexed Y addressing mode
Function
:
The value obtained by adding the instruction’s second byte and the contents of the direct page
register specifies 3 adjacent bytes in memory bank 016, and the value obtained by adding the
contents of these bytes and the contents of the index register Y specifies the address of the
memory location where the actual data is stored. If, however, the value obtained by adding the
contents of the instruction’s second byte and the direct page register exceeds the bank 0 16 range,
the specified location will be in bank 116. The 3 adjacent bytes memory location may be spread
over two different banks.
Instruction :
ADC,
AND, CMP,
ex. : Mnemonic
ADCL A, (1EH), Y
(m=1, x=1)
DIV,
DIVS*, EOR,
LDA,
MPY,
MPYS*,ORA,
SBC,
STA
Machine Code
7716 1E16
Memory
Bank 016
125216
DATA I (EF16)
125316
DATA II (0116)
125416
DATA III (1216)
Direct Page
Register
Op Code (7716)
123416 +
Operand (1E16)
Index
Register Y
+
2116
= 12021016
=
125216
A ← A+C+ DATA ←
DATA
12021016
7700 FAMILY SOFTWARE MANUAL
3–25
Direct Indirect Long Indexed Y
ex. : Mnemonic
ADCL A, (1EH), Y
(m=0, x=1)
Machine Code
7716 1E16
Memory
Bank 016
125216
DATA I (EF16)
125316
DATA II (0116)
125416
DATA III (1216)
Direct Page
Register
Op Code (7716)
123416 +
Operand (1E16)
Index
Register Y
+
2116
= 12021016
=
125216
A ← A+C+ DATAH DATAL ←
ex. : Mnemonic
ADCL A, (1EH), Y
(m=1, x=0)
Machine Code
7716 1E16
DATAL
12021016
DATAH
12021116
Memory
Bank 016
125216
DATA I (EF16)
125316
DATA II (0116)
125416
DATA III (1216)
Direct Page
Register
Op Code (7716)
123416 +
Operand (1E16)
Index
Register Y
+ E52116 = 12E71016
=
125216
A ← A+C+ DATA ←
3–26
DATA
12E71016
7700 FAMILY SOFTWARE MANUAL
Direct Indirect Long Indexed Y
ex. : Mnemonic
ADCL A, (1EH), Y
(m=0, x=0)
Machine Code
7716 1E16
Memory
Bank 016
125216
DATA I (EF16)
125316
DATA II (0116)
125416
DATA III (1216)
Direct Page
Register
Op Code (7716)
123416 +
Operand (1E16)
Index
Register Y
+ E52116 = 12E71016
=
125216
A ← A+C+ DATAH DATAL ←
DATAL
12E71016
DATAH
12E71116
7700 FAMILY SOFTWARE MANUAL
3–27
Absolute
Mode
:
Absolute addressing mode
Function
:
The contents of the memory locations specified by the instruction’s second and third bytes and the
contents of the data bank register are the actual data. Note that, in the cases of the JMP and JSR
instructions, the instructions’ second and third byte contents are transferred to the program
counter.
Instruction :
ADC,
JMP,
SBC,
AND,
JSR,
STA,
ex.: Mnemonic
ADC A, 0AD12H
(m=1)
ASL,
LDA,
STX,
ASR*, CMP,
LDM, LDX,
STY
CPX,
LDY,
CPY,
LSR,
DEC,
MPY,
Machine Code
6D16 1216 AD16
Memory
Op Code (6D16)
Operand (1216)
Operand (AD16)
Data Bank
Register
A ← A+C+ DATA ←
ex. : Mnemonic
ADC A, 0AD12H
(m=0)
DATA
DT
AD1216
Machine Code
6D16 1216 AD16
Memory
Op Code (6D16)
Operand (1216)
Operand (AD16)
Data Bank
Register
A ← A+C+ DATAH DATAL ←
3–28
DATAL
DT AD1216
DATAH
DT AD1316
7700 FAMILY SOFTWARE MANUAL
DIV,
DIVS*, EOR,
MPYS*, ORA, ROL,
INC,
ROR,
Absolute
ex. : Mnemonic
LDX 0AC14H
(x=1)
Machine Code
AE16 1416 AC16
Memory
Op Code (AE16)
Operand (1416)
Operand (AC16)
Data Bank
Register
X ← DATA ←
ex. : Mnemonic
LDX 0AC14H
(x=0)
DATA
DT AC1416
Machine Code
AE16 1416 AC16
Memory
Op Code (AE16)
Operand (1416)
Operand (AC16)
Data Bank
Register
X ← DATAH DATAL ←
DATAL
DT AC1416
DATAH
DT AC1516
7700 FAMILY SOFTWARE MANUAL
3–29
Absolute
ex. : Mnemonic
JMP 0AC14H
Machine Code
4C16 1416 AC16
Memory
PG 000016
Op Code (4C16)
Operand (1416)
Operand (AC16)
bank PG
Program
Bank Register
Address to be
executed next.
PG
AC1416
PG
FFFF16
Program bank register contents
are not affected.
(Note) The branch destination bank must be considered carefully when a JMP
or a JSR instruction is located near a bank boundary.
→Refer the description of a JMP instruction (Page 4-50).
Refer the description of a JSR instruction (Page 4-51).
3–30
7700 FAMILY SOFTWARE MANUAL
Absolute Bit
Mode
:
Absolute bit addressing mode
Function
:
The contents of the instruction’s second and third bytes and the contents of the data bank register
specify the memory locations, and data for multiple bit positions in the memory locations are
specified by a bit pattern specified in the instruction's fourth and fifth bytes (the fourth byte only
if the m flag is set to 1).
Instruction :
CLB,
SEB
ex. : Mnemonic
CLB #5AH, 1234H
(m=1)
Machine Code
1C16 3416 1216 5A16
Memory
Op Code (1C16)
Operand (3416)
Operand (1216)
Operand (5A16)
Data Bank
Register
?
? ? ?
? ? ? ?
DT
123416
Memory
Data Bank
Register
? 0
? 0
0
? 0
?
DT
123416
7700 FAMILY SOFTWARE MANUAL
3–31
Absolute Bit
ex. : Mnemonic
CLB #5AA5H, 1234H
(m=0)
Machine Code
1C16 3416 1216 A516 5A16
Memory
Op Code (1C16)
Operand (3416)
Operand (1216)
Operand (A516)
Operand (5A16)
Data Bank
Register
?
? ? ?
? ? ? ?
DT
123416
?
? ? ?
? ? ? ?
DT
123516
Memory
Data Bank
Register
3–32
0
? 0
?
0
?
? 0
? 0 0
? 0
? 0
?
DT 123416
DT
123516
7700 FAMILY SOFTWARE MANUAL
Absolute Indexed X
Mode
:
Function
:
Instruction :
Absolute indexed X addressing mode
The contents of the memory locations specified by a value resulting from addition of a 16-bit
numeric value expressed by the instruction’s second and third bytes with the contents of the index
register X and the contents of the data bank register are the actual data. If, however, addition of
the numeric value expressed by the instruction’s second and third bytes with the contents of the
index register X generates a carry, the bank number will be 1 larger than the contents of the data
bank register.
ADC,
LDY,
AND,
LSR,
ex. : Mnemonic
ADC A, 0AD12H, X
(m=1, x=1)
ASL,
MPY,
ASR*, CMP,
MPYS*,ORA,
DEC,
ROL,
DIV,
ROR,
DIVS*, EOR,
SBC, STA
INC,
LDA,
LDM,
Machine Code
7D16 1216 AD16
Memory
Index
Register X
Op Code (7D16)
Operand (1216)
+
EE16
= AE0016
Operand (AD16)
A ← A+C+ DATA
ex. : Mnemonic
ADC A, 0AD12H, X
(m=0, x=1)
←
DATA
DT
AE0016
Machine Code
7D16 1216 AD16
Memory
Index
Register X
Op Code (7D16)
Operand (1216)
+
EE16
= AE0016
Operand (AD16)
Index
Register X
A ← A+C+
DATAH
DATAL
←
DATAL
DT
AE0016
DATAH
DT
AE0116
7700 FAMILY SOFTWARE MANUAL
3–33
Absolute Indexed X
ex. : Mnemonic
ADC A, 0AD12H, X
(m=1, x=0)
Machine Code
7D16 1216 AD16
Memory
Op Code (7D16)
Index
Register X
Operand (1216)
+ 10EE16
Operand (AD16)
= BE0016
Data Bank
Register
A ← A+C+ DATA
ex. : Mnemonic
ADC A, 0AD12H, X
(m=0, x=0)
←
DATA
DT
BE0016
Machine Code
7D16 1216 AD16
Memory
Op Code (7D16)
Index
Register X
Operand (1216)
+ 10EE16
Operand (AD16)
Data Bank
Register
A ← A+C+
3–34
DATAH
DATAL
←
DATAL
DT
BE0016
DATAH
DT
BE0116
7700 FAMILY SOFTWARE MANUAL
= BE0016
Absolute Indexed X
Machine Code
BC16 1216 BC16
ex. : Mnemonic
LDY 0BC12H, X
(x=1)
Memory
Index
Register X
Op Code (BC16)
Operand (1216)
+
EE16
= BD0016
Operand (BC16)
Data Bank
Register
Y ←
DATA
←
DATA
DT
BD0016
Machine Code
BC16 1216 BC16
ex. : Mnemonic
LDY 0BC12H, X
(x=0)
Memory
Op Code (BC16)
Index
Register X
Operand (1216)
+ 10EE16
Operand (BC16)
= CD0016
Data Bank
Register
Y ←
DATAH
DATAL
←
DATAL
DT
CD0016
DATAH
DT
CD0116
7700 FAMILY SOFTWARE MANUAL
3–35
Absolute Indexed Y
Mode
:
Absolute indexed Y addressing mode
Function
:
The contents of the memory locations specified by a value resulting from addition of a 16-bit
numeric value expressed by the instruction’s second and third bytes with the contents of the index
register Y and the contents of the data bank register are the actual data. If, however, addition of
the numeric value expressed by the instruction’s second and third bytes with the contents of the
index register Y generates a carry, the bank number will be 1 larger than the contents of the data
bank register.
Instruction :
ADC,
STA
AND,
ex. : Mnemonic
ADC A, 0AD12H, Y
(m=1, x=1)
CMP,
DIV,
DIVS*, EOR,
LDA,
LDX,
MPY,
MPYS*,ORA,
Machine Code
7916 1216 AD16
Memory
Index
Register Y
Op Code (7916)
Operand (1216)
+
EE16
= AE0016
Operand (AD16)
Data Bank
Register
A ← A+C+
ex. : Mnemonic
ADC A, 0AD12H, Y
(m=1, x=0)
DATA
←
DATA
DT
AE0016
Machine Code
7916 1216 AD16
Memory
Index
Register Y
Op Code (7916)
Operand (1216)
Operand (AD16)
+ 10EE16
Data Bank
Register
A ← A+C+
3–36
DATA
←
DATA
DT
BE0016
7700 FAMILY SOFTWARE MANUAL
= BE0016
SBC,
Absolute Indexed Y
ex. : Mnemonic
ADC A, 0AD12H, Y
(m=0, x=1)
Machine Code
7916 1216 AD16
Memory
Op Code (7916)
Index
Register Y
Operand (1216)
+
EE16
= AE0016
Operand (AD16)
Data Bank
Register
A ← A+C+ DATAH DATAL ←
ex. : Mnemonic
ADC A, 0AD12H, Y
(m=0, x=0)
DATAL
DT
AE0016
DATAH
DT
AE0116
Machine Code
7916 1216 AD16
Memory
Op Code (7916)
Index
Register Y
Operand (1216)
+ 10EE16
= BE0016
Operand (AD16)
Data Bank
Register
A ← A+C+ DATAH DATAL ←
DATAL
DT
BE0016
DATAH
DT
BE0116
7700 FAMILY SOFTWARE MANUAL
3–37
Absolute Indexed Y
ex. : Mnemonic
LDX 0BC12H, Y
(x=1)
Machine Code
BE16 1216 BC16
Memory
Index
Register Y
Op Code (BE16)
Operand (1216)
+
EE16
= BD0016
Operand (BC16)
Data Bank
Register
X ← DATA
ex. : Mnemonic
LDX 0BC12H, Y
(x=0)
←
DATA
DT
BD0016
Machine Code
BE16 1216 BC16
Memory
Op Code (BE16)
Index
Register Y
Operand (1216)
+ 10EE16
Operand (BC16)
Data Bank
Register
X ← DATAH DATAL ←
3–38
DATAL
DT
CD0016
DATAH
DT
CD0116
7700 FAMILY SOFTWARE MANUAL
= CD0016
Absolute Long
Mode
:
Absolute long addressing mode
Function
:
The contents of the memory locations specified by the instruction’s second, third and fourth bytes
become the actual data. Note that, in the cases of the JMP and JSR instructions, the instructions’
second and third byte contents are transferred to the program counter and the fourth byte contents
are transferred to the program bank register.
Instruction :
ADC,
SBC,
AND,
STA
ex. : Mnemonic
ADC A, 123456H
(m=1)
CMP,
DIV,
DIVS*, EOR,
JMP,
JSR,
LDA,
MPY,
MPYS*, ORA,
Machine Code
6F16 5616 3416 1216
Memory
Op Code (6F16)
Operand (5616)
Operand (3416)
Operand (1216)
A ← A+C+
ex. : Mnemonic
ADC A, 123456H
(m=0)
DATA
←
DATA
12345616
Machine Code
6F16 5616 3416 1216
Memory
Op Code (6F16)
Operand (5616)
Operand (3416)
Operand (1216)
A ← A+C+ DATAH DATAL ←
DATAL
12345616
DATAH
12345716
7700 FAMILY SOFTWARE MANUAL
3–39
Absolute Long
ex. : Mnemonic
JMPL 123456H
Machine Code
5C16 5616 3416 1216
Memory
Op Code (5C16)
Operand (5616)
Operand (3416)
Operand (1216)
Program Bank
Register
Address to be
executed next.
1216 345616
Program bank register contents
are replaced by the third
operand.
3–40
7700 FAMILY SOFTWARE MANUAL
Absolute Long Indexed X
Mode
:
Absolute long indexed X addressing mode
Function
:
The contents of the memory location specified by adding the numeric value expressed by the
instruction’s second, third and fourth bytes with the contents of the index register X are the actual
data.
Instruction :
ADC,
AND,
ex. : Mnemonic
ADC A, 123456H, X
(m=1, x=1)
CMP,
DIV,
DIVS*, EOR,
LDA,
MPY,
MPYS*,ORA,
SBC,
STA
Machine Code
7F16 5616 3416 1216
Memory
Op Code (7F16)
Index
Register X
Operand (5616)
Operand (3416)
+
E116
= 12353716
Operand (1216)
A ← A+C+
ex. : Mnemonic
ADC A, 123456H, X
(m=0, x=1)
DATA
←
DATA
12353716
Machine Code
7F16 5616 3416 1216
Memory
Op Code (7F16)
Index
Register X
Operand (5616)
Operand (3416)
+
E116
= 12353716
Operand (1216)
A ← A+C+ DATAH DATAL ←
DATAL
12353716
DATAH
12353816
7700 FAMILY SOFTWARE MANUAL
3–41
Absolute Long Indexed X
ex. : Mnemonic
ADC A, 123456H, X
(m=1, x=0)
Machine Code
7F16 5616 3416 1216
Memory
Op Code (7F16)
Index
Register X
Operand (5616)
+ EEE116
Operand (3416)
= 13233716
Operand (1216)
A ← A+C+
ex. : Mnemonic
ADC A, 123456H, X
(m=0, x=0)
DATA
←
DATA
13233716
Machine Code
7F16 5616 3416 1216
Memory
Op Code (7F16)
Index
Register X
Operand (5616)
+ EEE116
Operand (3416)
Operand (1216)
A ← A+C+ DATAH DATAL ←
3–42
DATAL
13233716
DATAH
13233816
7700 FAMILY SOFTWARE MANUAL
= 13233716
Absolute Indirect
Mode
:
Absolute indirect addressing mode
Function
:
The instruction’s second and third bytes specify 2 adjacent bytes in memory, and the contents of
these bytes specify the address within the same program bank to which a jump is to be made.
Instruction :
JMP
ex. : Mnemonic
JMP (1400H)
Machine Code
6C16 0016 1416
Memory
Op Code (6C16)
Operand (0016)
Operand (1416)
DATA I (FF16)
PG 140016
bank PG
DATA II (1E16)
Address to be
executed next.
(Note)
PG 1EFF16
The branch destination bank must be considered carefully when a JMP
instruction is located near a bank boundary.
→Refer the description of a JMP instruction (Page 4-50).
7700 FAMILY SOFTWARE MANUAL
3–43
Absolute Indirect Long
Mode
:
Absolute indirect long addressing mode
Function
:
The instruction’s second and third bytes specify 3 adjacent bytes in memory, and the contents of
these bytes specify the address to which a jump is to be made.
Instruction :
JMP
ex. : Mnemonic
JMPL (1234H)
Machine Code
DC16 3416 1216
Memory
Op Code (DC16)
Operand (3416)
Operand (1216)
Program Bank
Register
DATA I (1216)
PG 123416
DATA II (B416)
DATA III (A116)
Program Bank
Register
Address to be
executed next.
A116
B41216
DATA III is loaded in the
program bank register.
(Note)
3–44
The branch destination bank must be considered carefully when a JMP
instruction is located near a bank boundary.
→Refer the description of a JMP instruction (Page 4-50).
7700 FAMILY SOFTWARE MANUAL
bank PG
Absolute Indexed X Indirect
Mode
:
Absolute indexed X indirect addressing mode
Function
:
The value obtained by adding the instruction's second and third bytes and the contents of the index
register X specifies 2 adjacent bytes in memory, and the contents of these bytes specify the
address to which a jump is to be made.
Instruction :
JMP,
JSR
ex. : Mnemonic
JMP (1234H, X)
(x=1)
Machine Code
7C16 3416 1216
Memory
Index
Register X
Op Code (7C16)
Operand (3416)
+
1216
= 124616
Operand (1216)
bank PG
DATA I (1216)
124616
DATA II (BC16)
124716
Program Bank
Register
Address to be
executed next.
(Note)
PG BC1216
The branch destination bank must be considered carefully
when a JMP or a JSR instruction is located near a boundary.
→Refer the description of a JMP instruction (Page 4-50).
Refer the description of a JSR instruction (Page 4-51).
7700 FAMILY SOFTWARE MANUAL
3–45
Stack
Mode
:
Stack addressing mode
Function
:
Register contents are saved to or restored from the memory location specified by the stack pointer.
The stack pointer is set in bank-0.
Instruction :
PEA,
PLB,
ex. : Mnemonic
PHA
(m=1)
PEI,
PLD,
PER,
PLP,
PHA,
PLT,
PHB,
PLX,
PHD,
PLY,
PHG,
PSH,
PHP,
PUL
PHT,
PHX,
PHY,
Machine Code
4816
Memory
Stack Pointer
S
ex. : Mnemonic
PHA
(m=0)
SH
00
S–1
SL
Bank 016
AL
Machine Code
4816
Memory
Stack Pointer
ex. : Mnemonic
PHD
SH
00
S–2
S–1
AL
S
AH
SL
Bank 016
Machine Code
0B16
Memory
Stack Pointer
00
S–2
3–46
S–1
DPRL
S
DPRH
7700 FAMILY SOFTWARE MANUAL
SH
SL
Bank 016
PLA,
Stack
ex. : Mnemonic
PEA #1234H
Machine Code
F416 3416 1216
Memory
Stack Pointer
00
S–2
S–1
3416
S
1216
SH
SL
Bank 016
Op Code (F416)
Operand (3416)
Operand (1216)
ex. : Mnemonic
PEI #12H
Machine Code
D416 1216
Memory
DATA I
341216
DATA II
341316
Bank 016
Stack Pointer
00
S–2
S–1
DATA I
S
DATA II
Op Code (D416)
Operand (1216)
SH
SL
Direct Page
Register
+ 340016 = 341216
7700 FAMILY SOFTWARE MANUAL
3–47
Stack
ex. : Mnemonic
PER #1234H
Machine Code
6216 3416 1216
Memory
Stack Pointer
00
S–2
S–1
AC16
S
6816
SH
Bank 016
SL
Program Bank
Register
Op Code (6216)
PG
567616
bank PG
Operand (3416)
Operand (1216)
+ 567816 = 68AC16
Program Counter
3–48
7700 FAMILY SOFTWARE MANUAL
Relative
Mode
:
Relative addressing mode
Function
:
Branching occurs to the address specified by the value resulting from addition of the contents of
the program counter and the instruction’s second byte. In the case of a long branch by the BRA
instruction, a 15-bit signed numeric value formed by the contents of the instruction’s second and
third bytes is added to the program counter contents. If the addition generates a carry or borrow,
1 is added to or subtracted from the program bank register.
Instruction :
BCC,
BCS,
BEQ,
BMI,
BNE,
BPL,
BRA,
BVC,
BVS
Machine Code
ex. : Mnemonic
BCC ✽ –12
9016 F416
Memory
Address to be
executed next.
Memory
✽ –12
Op Code (9016)
Jump
Op Code (9016)
Operand (F416)
Address to be
executed next.
Operand (F416)
✽
✽
Branches to the address ✽ –12 if
the carry flag (C) has been cleared
“0”.
ex. : Mnemonic
BRAL 1234H
Advances to the address ✽ if the
carry flag (C) has been set “1”.
Machine Code
8216 3416 1216
Memory
Op Code (8216)
bank PG
Operand (3416)
Operand (1216)
PG
FF1216
PG 114616
bank PG + 1
Address to be
executed next.
7700 FAMILY SOFTWARE MANUAL
3–49
Direct Bit Relative
Mode
:
Direct bit relative addressing mode
Function
:
Specifies the bank 0 16 memory location by the value obtained by adding the instruction’s second
byte to the direct page register’s contents, and specifies the positions of multiple bits in the
memory location by the bit pattern in the third and fourth bytes (the third byte only if the m flag
is set to 1). Then, if the specified bits all satisfy the branching conditions, the instruction’s fifth byte
(or the fourth byte if the m flag is set to 1) is added to the program counter as a signed value,
generating the branching destination address. If, however, addition of the instruction’s second byte
to the direct page register’s contents result in a value that exceeds the bank 0 16 range, the
specified location will be in bank 116.
Instruction :
BBC,
BBS
ex. : Mnemonic
Machine Code
BBS #5AH, 04H, 0F6H
(m=1)
2416 0416 5A16 F616
(Branch)
(Not branch)
Memory
Memory
0 1 1 1 1 0 1 1 00123816
0 0 1 1 1 0 1 1 00123816
Program
Bank Register
Address to be
executed next.
1116 FFFD16
Op Code (2416)
Direct Page
Register
Op Code (2416)
Direct Page
Register
Jump
Operand (0416)
+ 123416 = 123816
Program
Bank Register
1216 000716
3–50
+ 123416 = 123816
Operand (5A16)
Operand (5A16)
Operand (F616)
Operand (0416)
Operand (F616)
Address to be
executed next.
7700 FAMILY SOFTWARE MANUAL
Program
Bank Register
1216 000716
Bank 016
Direct Bit Relative
Machine Code
ex. : Mnemonic
BBS #5AA5H, 04H, 0F6H
(m=0)
(Branch)
(Not branch)
Memory
Memory
1 1 1 0 0 1 1 1 00123816
0 1 1 0 0 1 1 1 00123816
0 1 0 1 1 0 1 1 00123916
0 1 0 1 1 0 1 1 00123916
Address to be
executed next.
Bank 016
1116 FFFE16
Op Code (2416)
Jump
2416 0416 A516 5A16 F616
Operand (0416)
Direct Page
Register
Op Code (2416)
Operand (0416)
+ 123416 = 123816
Operand (A516)
+ 123416 = 123816
Operand (A516)
Operand (5A16)
Operand (F616)
Direct Page
Register
Operand (5A16)
Program
Bank Register
1216 000816
Operand (F616)
Address to be
executed next.
7700 FAMILY SOFTWARE MANUAL
Program
Bank Register
1216 000816
3–51
Absolute Bit Relative
Mode
:
Absolute bit relative addressing mode
Function
:
The instruction’s second and third bytes and the contents of the data bank register specify the
memory location, and data for the memory location’s multiple bits is specified by a bit pattern in
the instruction’s fourth and fifth bytes (the fourth byte only if the m flag is set to 1). Then, if the
specified bits all satisfy the branching conditions, the instruction’s sixth byte (or the fifth byte if the
m flag is set to 1) is added to the program counter as a signed value, generating the branching
destination address.
Instruction :
BBC,
BBS
ex. : Mnemonic
BBS #5AH, 1234H, 0F6H
(m=1)
Machine Code
2C16 3416 1216 5A16 F616
(Branch)
(Not branch)
Memory
Memory
Program
Bank Register
Address to be
executed next.
Jump
1116 FFFD16
Op Code (2C16)
Op Code (2C16)
Operand (3416)
Operand (3416)
Operand (1216)
Operand (1216)
Operand (5A16)
Operand (5A16)
Operand (F616)
Program
Bank Register
1216 000716
Operand (F616)
Address
to be
executed
next.
1216 000716
Data Bank
Register
0 1 1 1 1 0 1 0
3–52
DT 123416
7700 FAMILY SOFTWARE MANUAL
Program
Bank Register
Data Bank
Register
0 0 1 1 1 0 1 0
DT 123416
Absolute Bit Relative
Machine Code
ex. : Mnemonic
BBS #5AA5H, 1234H, 0F6H 2C16 3416 1216 A516 5A16 F616
(m=0)
(Branch)
(Not branch)
Memory
Memory
Program
Bank Register
Address to be
executed next.
Jump
1116 FFFD16
Op Code (2C16)
Op Code (2C16)
Operand (3416)
Operand (3416)
Operand (1216)
Operand (1216)
Operand (A516)
Operand (A516)
Operand (5A16)
Operand (F616)
Operand (5A16)
Program
Bank Register
1216 000716
Operand (F616)
Address
to be
executed
next.
Program
Bank Register
1216 000716
Data Bank
Register
Data Bank
Register
1 0 1 1 0 1 0 1
DT 123416
0 0 1 1 0 1 0 1
DT 123416
1 1 0 1 1 1 1 0
DT 123516
1 1 0 1 1 1 1 0
DT 123516
7700 FAMILY SOFTWARE MANUAL
3–53
Stack Pointer Relative
Mode
:
Stack pointer relative addressing mode
Function
:
The contents of a bank-0 memory location specified by the value resulting from addition of the
instruction’s second byte and the contents of the stack pointer become the actual data. If,
however, the value obtained by adding the contents of the instruction’s second byte and the stack
pointer’s contents exceeds the bank-0 range, the specified location will be in bank-1.
Instruction :
ADC,
ex. : Mnemonic
ADC A, 02H, S
(m=1)
AND,
CMP,
DIV,
DIVS*, EOR,
LDA,
MPY,
MPYS*,ORA, SBC, STA
Machine Code
6316 0216
Memory
Bank 016
A ← A+C+ DATA ←
ex. : Mnemonic
ADC A, 02H, S
(m=0)
DATA
123616
Op Code (6316)
Stack Pointer
Operand (0216)
+ 123416
= 123616
Machine Code
6316 0216
Memory
Bank 016
A ← A+C+ DATAH DATAL ←
3–54
DATAL
123616
DATAH
123716
Op Code (6316)
Stack Pointer
Operand (0216)
+ 123416
7700 FAMILY SOFTWARE MANUAL
= 123616
Stack Pointer Relative Indirect Indexed Y
Mode
:
Stack pointer relative indirect indexed Y addressing mode
Function
:
The value obtained by adding the instruction’s second byte and the contents of the stack pointer
specifies 2 adjacent bytes in memory. The value obtained by adding the contents of these bytes
and the contents of the index register Y specifies address of the actual data in memory bank-DT
(DT is contents of data bank register). If addition of the 2 bytes in memory with the contents of
the index register Y generate a carry, the bank number will be 1 larger than the contents of the
data bank register.
Instruction :
ADC,
AND,
ex. : Mnemonic
ADC A, (1EH, S), Y
(m=1, x=1)
CMP,
DIV,
DIVS*, EOR,
LDA,
MPY,
MPYS*,ORA,
SBC,
STA
Machine Code
7316 1E16
Bank 016
125216
DATA I (0116)
125316
DATA II (1216)
Stack Pointer
Op Code (7316)
123416 +
Operand (1E16)
+
Index
Register Y
E616
= 12E716
=
125216
Data Bank
Register
A ← A+C+
DATA
←
DATA
DT
7700 FAMILY SOFTWARE MANUAL
12E716
3–55
Stack Pointer Relative Indirect Indexed Y
ex. : Mnemonic
ADC A, (1EH, S), Y
(m=0, x=1)
Machine Code
7316 1E16
Memory
Bank 016
125216
DATA I (0116)
125316
DATA II (1216)
Stack Pointer
Op Code (7316)
123416 +
Operand (1E16)
Index
Register Y
+
E616
= 12E716
=
125216
Data Bank
Register
DATAL
A ← A+C+ DATAH DATAL ←
DT
12E716
DATAH
ex. : Mnemonic
ADC A, (1EH, S), Y
(m=1, x=0)
Machine Code
7316 1E16
Memory
Bank 016
Index
Register Y
125216
DATA I (0116)
125316
DATA II (1216)
Stack Pointer
Op Code (7316)
123416 +
Operand (1E16)
+ F0E616
=
125216
Data Bank
Register
A ← A+C+ DATA
←
DATA
DT
+1
02E716
Bank
3–56
7700 FAMILY SOFTWARE MANUAL
= 102E716
Stack Pointer Relative Indirect Indexed Y
ex. : Mnemonic
ADC A, (1EH, S), Y
(m=0, x=0)
Machine Code
7316 1E16
Memory
Bank 016
125216
DATA I (0116)
125316
DATA II (1216)
Stack Pointer
Op Code (7316)
123416 +
Operand (1E16)
Index
Register Y
+ F0F616 = 102E716
=
125216
Data Bank
Register
A ← A+C+ DATAH DATAL ←
DATAL
DT
DATAH
Bank
7700 FAMILY SOFTWARE MANUAL
+1
02E716
3–57
Block Transfer
Mode
:
Block transfer addressing mode
Function
:
The instruction’s second byte specifies the transfer-to data bank, and the contents of the index
register Y specify the transfer-to address within the data bank. The instruction’s third byte specifies the transfer-from data bank, and the contents of the index register X specify the address in
the data bank where the data to be transferred is stored. The contents of the accumulator A
constitute the number of bytes to be transferred. Upon termination of transfer, the contents of the
data bank register will specify the transfer-to data bank. The MVN instruction is used for transfer
to lower address location. In this case, the contents of the index registers X and Y are incremented each time data is transferred. The MVP instruction is used for transfer to higher address
location. In this case, the contents of the index registers X and Y are decremented each time data
is transferred. The block of data to be transferred may cross over the bank boundary.
Instruction :
MVN,
MVP
ex. : Mnemonic
MVN 0E2H, 0E5H
(m=0, x=0)
Machine Code
5416 E216 E516
Before transfer
After transfer
Memory
Memory
Bank E216
DATA I
E2567816
DATA II
E2567916
DATA III
E2567A16
Bank E216
Op Code (5416)
A
000316
Op Code (5416)
A
FFFF16
Operand (E216)
X 123416
Operand (E216)
X
123716
Operand (E516)
Y
Operand (E516)
Y
567B16
567816
DT
?
DT E216
First
3–58
DATA I
E5123416
DATA II
E5123516
DATA III
E5123616
Bank E516
Second
7700 FAMILY SOFTWARE MANUAL
DATA I
E5123416
DATA II
E5123516
DATA III
E5123616
Bank E516
Block Transfer
ex. : Mnemonic
MVP 0E5H, 0E2H
(m=0, x=0)
Machine Code
4416 E516 E216
Before transfer
After transfer
Memory
Memory
DATA I
E2567816
DATA II
E2567916
DATA III
E2567A16
Second
Bank E216
First
DATA I
E2567816
DATA II
E2567916
DATA III
E2567A16
Bank E216
Op Code (4416)
A 000316
Op Code (4416)
A FFFF16
Operand (E516)
X 567A16
Operand (E516)
X
567716
Operand (E216)
Y 123616
Operand (E216)
Y
123316
DT
DT E516
?
Bank E516
DATA I
E5123416
DATA II
E5123516
DATA III
E5123616
Bank E516
(Note) For block transfer instruction, the transfer byte count and transfer source/destination address
range change with the status of the m and x flags, but the transfer unit is unaffected.
The transfer unit is word (16 bits), but only 1 byte is transferred when transferring the last byte
of an odd byte transfer.
7700 FAMILY SOFTWARE MANUAL
3–59
CHAPTER 4
INSTRUCTIONS
4.1 Instruction set
4.2 Description of instructions
4.3 Notes for programming
INSTRUCTIONS
4.1 Instruction set
4.1 Instruction Set
The 7700 Series, 7770 Series, and 7790 Series CPU uses the instruction set with 103 instructions. The
7750 Series CPU uses an extended instruction set (108 instructions) adding five additional instructions to
their instruction set.
«Additional instructions»
Instructions
Mnemonic
Addressing mode
Multiply with sign
MPYS
Supports addressing mode equivalent to MPY instruction
Divide with sign
DIVS
Supports addressing mode equivalent to DIV instruction
Arithmetic shift right
ASR
Supports addressing mode equivalent to ASL instruction
Extension with sign
EXTS
Extension zero
EXTZ
Supported the accumulator addressing mode
4.1.1 Data transfer instructions
The data transfer instructions move data between data and registers, between a register and the memory,
between registers or between memory devices.
Category Instruction
Load
Store
Transfer
4–2
Description
LDA
Loads the contents of memory into the accumulator.
LDM
Loads an immediate value into the memory.
LDT
Loads an immediate value into the data bank register.
LDX
Loads the contents of memory into the index register X.
LDY
Loads the contents of memory into the index register Y.
STA
Stores the contents of the accumulator in the memory.
STX
Stores the contents of the index register X in the memory.
STY
Stores the contents of the index register Y in the memory.
TAX
Transfers the contents of the accumulator A to the index register X.
TXA
Transfers the contents of the index register X to the accumulator A.
TAY
Transfers the contents of the accumulator A to the index register Y.
TYA
Transfers the contents of the index register Y to the accumulator A.
TSX
Transfers the contents of the stack pointer to the index register X.
TXS
Transfers the contents of the index register X to the stack pointer.
TAD
Transfers the contents of the accumulator A to the direct page register.
TDA
Transfers the contents of the direct page register to the accumulator A.
TAS
Transfers the contents of the accumulator A to the stack pointer.
TSA
Transfers the contents of the stack pointer to the accumulator A.
7700 FAMILY SOFTWARE MANUAL
INSTRUCTIONS
4.1 Instruction set
Category Instruction
Transfer
Description
TBD
Transfers the contents of the accumulator B to the direct page register.
TDB
Transfers the contents of the direct page register to the accumulator B.
TBS
Transfers the contents of the accumulator B to the stack pointer.
TSB
Transfers the contents of the stack pointer to the accumulator B.
TBX
Transfers the contents of the accumulator B to the index register X.
TXB
Transfers the contents of the index register X to the accumulator B.
TBY
Transfers the contents of the accumulator B to the index register Y.
TYB
Transfers the contents of the index register Y to the accumulator B.
TXY
Transfers the contents of the index register X to the index register Y.
TYX
Transfers the contents of the index register Y to the index register X.
MVN
Transfers a block of data from the lower addresses.
MVP
Transfers a block of data from the higher addresses.
PSH
Saves the contents of the specified register to the stack.
Stack
PUL
Restores the contents of stack to the specified register.
operation
PHA
Saves the contents of the accumulator A to the stack.
PLA
Restores the contents of stack to the accumulator A.
PHP
Saves the contents of the processor status register to the stack.
PLP
Restores the contents of stack to the processor status register.
PHB
Saves the contents of the accumulator B to the stack.
PLB
Restores the contents of stack to the accumulator B.
PHD
Saves the contents of the direct page register to the stack.
PLD
Restores the contents of stack to the direct page register.
PHT
Saves the contents of the data bank register to stack.
PLT
Restores the contents of stack to the data bank register.
PHX
Saves the contents of the index register X to the stack.
PLX
Restores the contents of stack to the index register X.
PHY
Saves the contents of the index register Y to the stack.
PLY
Restores the contents of stack to the index register Y.
PHG
Saves the contents of the program bank register to the stack.
PEA
Saves a the numeric of 2 bytes to the stack.
PEI
Saves the contents of 2 consecutive bytes in the direct page area to the stack.
PER
Saves the result of adding a 16-bit numeric value to the program counter contents to
the stack.
XAB
Swaps the contents of the accumulator A with the contents of the accumulator B.
Exchange
7700 FAMILY SOFTWARE MANUAL
4–3
INSTRUCTIONS
4.1 Instruction set
4.1.2 Arithmetic instructions
The arithmetic instructions perform addition, subtraction, multiplication, division, logical operation, comparison,
rotation, shifting and sign/zero extension of register and memory contents.
The following table summarizes the arithmetic instructions supported:
Note. The instructions with the mark “ * ” can be used in the 7750 Series only.
Category
Addition,
Instruction
ADC
Adds the contents of the accumulator, the contents of memory and the contents of the
carry flag.
SBC
Subtracts the contents of memory and the complement of the carry flag from the contents of the accumulator.
INC
Increments the accumulator or memory contents by 1.
DEC
Decrements the accumulator or memory contents by 1.
INX
Increments the contents of the index register X by 1.
DEX
Decrements the contents of the index register X by 1.
INY
Increments the contents of the index register Y by 1.
DEY
Decrements the contents of the index register Y by 1.
MPY
Multiples the contents of the accumulator A and the contents of memory.
Subtraction,
Multiplication,
Division
Description
MPYS*
Multiply the contents of the accumulator A and the contents of memory with sign.
DIV
Divides the numeric value whose lower byte is the contents of the accumulator A and
upper byte is the contents of the accumulator B by the contents of memory.
DIVS*
Divides the numeric value whose lower byte is the contents of the accumulator A and
upper byte is the contents of the accumulator B by the contents of memory with sign.
AND
Performs logical AND between the contents of the accumulator and the contents
of memory.
ORA
Performs logical OR between the contents of the accumulator and the contents of
memory.
EOR
Performs logical exclusive-OR between the contents of the accumulator and the contents of memory.
CMP
Compares the contents of the accumulator with the contents of memory.
CPX
Compares the contents of the index register X and the contents of memory.
CPY
Compares the contents of the index register Y and the contents of memory.
Shifting,
ASL
Shifts the contents of the accumulator or memory to the left by 1 bit.
Rotation
ASR*
Shifts the contents of the accumulator or memory holding sign to the right by 1 bit.
LSR
Shifts the contents of the accumulator or memory to the right by 1 bit.
ROL
Links the contents of accumulator or memory with the carry flag, and rotates the result
to the left by 1 bit.
ROR
Links the contents of accumulator or memory with the carry flag, and rotates the result
to the right by 1 bit.
RLA
Rotates the contents of the accumulator A to the left by the specified number of bits.
Logical operation
Comparison
Extension
with sign /
zero
4–4
EXTS*
Extend the low-order 8 bits of accumulator to 16 bits by sign extending.
EXTZ*
Extend the low-order 8 bits of accumulator to 16 bits by zero extending.
7700 FAMILY SOFTWARE MANUAL
INSTRUCTIONS
4.1 Instruction set
4.1.3 Bit manipulation instructions
The bit manipulation instructions set the specified bits of the processor status register or memory to “1” or “0”.
The following table summarizes the bit manipulation instructions supported:
Category
Instruction
Description
Bit manipulation
CLB
Clears the specified memory bit to “0”.
SEB
Sets the specified memory bit to “1”.
CLP
Clears the specified bit of the processor status register’s lower byte (PSL) to “0”.
SEP
Sets the specified bit of the processor status register’s lower byte (PSL) to “1”.
4.1.4 Flag manipulation instructions
The flag manipulation instructions set to “1” or clear to “0” the C, I, m and V flags.
The following table summarizes the flag manipulation instructions supported:
Category
Instruction
Description
Flag manipulation
CLC
Clears the contents of carry flag to “0”.
SEC
Sets the contents of carry flag to “1”.
CLM
Clears the contents of data length selection flag to “0”.
SEM
Sets the contents of data length selection flag to “1”.
CLI
Clears the contents of interrupt disable flag to “0”.
SEI
Sets the contents of interrupt disable flag to “1”.
CLV
Clears the contents of overflow flag to “0”.
4.1.5 Branching and return instructions
The branching and return instructions enable changing the program execution sequence.
The following table summarizes the branching and return instructions:
Category
Jump
Instruction
Description
JMP
Sets a new address in the program counter and jumps to the new address.
BRA
Jumps to the address obtained by adding an offset value to the contents of the program
counter.
JSR
Saves the contents of the program counter to the stack and then jumps to the new
address.
7700 FAMILY SOFTWARE MANUAL
4–5
INSTRUCTIONS
4.1 Instruction set
Category Instruction
Branch
Return
Description
BBC
Causes a branch if the specified memory bits are all “0”.
BBS
Causes a branch if the specified memory bits are all “1”.
BCC
Causes a branch if the carry flag is set to “0”.
BCS
Causes a branch if the carry flag is set to “1”.
BNE
Causes a branch if the zero flag is set to “0”.
BEQ
Causes a branch if the zero flag is set to “1”.
BPL
Causes a branch if the negative flag is set to “0”.
BMI
Causes a branch if the negative flag is set to “1”.
BVC
Causes a branch if the overflow flag is set to “0”.
BVS
Causes a branch if the overflow flag is set to “1”.
RTI
Returns from the interrupt routine to the original routine.
RTS
Returns from a subroutine to the original routine. The program bank register contents
are not restored.
RTL
Returns from a subroutine to the original routine. The program bank register contents
are restored.
4.1.6 Interrupt instruction (break instruction)
The interrupt instruction executes software interrupt.
Category Instruction
Break
BRK
Description
Executes a software interrupt.
4.1.7 Special instructions
The special instructions listed below control the clock generator circuit.
Category Instruction
Special
Description
WIT
Stops the internal clock.
STP
Stops the oscillator.
4.1.8 Other instruction
Category Instruction
Other
4–6
NOP
Description
Only advances the program counter.
7700 FAMILY SOFTWARE MANUAL
INSTRUCTIONS
4.2 Description of Instructions
4.2 Description of Instructions
This section describes the 7700 Family instructions at each instruction (Note 1). To the extent possible, each
instruction is described using one page per instruction. Each instruction description page is headed by the
instruction mnemonic, and the pages are arranged in alphabetical order of the mnemonics. For each instruction, operation and description of the instruction (Note 2, 3), status flag changes and a listing sorted by
addressing modes of the assembler coding format (Note 4), machine code, bytes-count and cycles-count (Note
5) are presented.
Note 1. The instructions with the mark “ * ” can be used in the 7750 Series only.
Note 2. In the description of instruction operation, the change in the PC (program counter) is described only
for instructions affecting the processing flow.
When an instruction is executed, the length of the instruction is added to content of the PC to form
the address of the next instruction to be executed. If a carry occurs during this addition, PG (program
bank register) is incremented by 1.
Note 3. In the description of each instruction, [Operation] indicates the contents of each register and memory
after executing the instruction. The detailed operation sequence is omitted.
Note 4. The assembler coding formats shown are general examples, and they may differ from the actual
formats for the assembler used. Please be sure to refer to the mnemonic coding description in the
manual for the assembler actually used for programming.
Note 5. The cycles-counts shown are the minimum possible, and they vary depending on the following conditions:
● Value of direct page register’s lower byte
The cycles-count shown are for when the direct page register’s lower byte (DPRL) is 0016. When
using an addressing mode that uses the direct page register with DPRL≠“00 16”, the cycles-count
will be 1 more than the value shown.
● Number of bytes that have been loaded in the instruction queue buffer
● Whether the first address of the memory read/write is even- or odd-numbered in accessing the 16bit data length.
● Accessing of an external memory are with BYTE=1 (using 8-bit external bus)
● Whether a wait is inserted in the bus cycle.
7700 FAMILY SOFTWARE MANUAL
4–7
INSTRUCTIONS
4.2 Description of Instructions
The table below lists the symbols that are used in this section:
Symbol
C
Z
I
D
x
m
V
N
IPL
+
–
×
/
V
V
∀
←
→
←
→
Acc
AccH
AccL
A
AH
AL
B
BH
BL
X
XH
XL
Y
YH
YL
S
PC
PCH
PCL
REL
PG
DT
4–8
Description
Carry flag
Zero flag
Interrupt disable flag
Decimal operation mode flag
Index register length selection flag
Data length selection flag
Overflow flag
Negative flag
Processor interrupt priority level
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
Exclusive OR
Negation
Movement to the arrow direction
Movement to the arrow direction
Movement to the arrow direction
Accumulator
Accumulator’s upper 8 bits
Accumulator’s lower 8 bits
Accumulator A
Accumulator A’s upper 8 bits
Accumulator A’s lower 8 bits
Accumulator B
Accumulator B’s upper 8 bits
Accumulator B’s lower 8 bits
Index register X
Index register X’s upper 8 bits
Index register X’s lower 8 bits
Index register Y
Index register Y’s upper 8 bits
Index register Y’s lower 8 bits
Stack pointer
Program counter
Program counter’s upper 8 bits
Program counter’s lower 8 bits
Relative address
Program bank register
Data bank register
7700 FAMILY SOFTWARE MANUAL
INSTRUCTIONS
4.2 Description of Instructions
Symbol
DPR
DPRH
DPRL
PS
PSH
PSL
PSn
M
M(n)
M(n+1,n)
M(m to n)
M(S)
Mb
ADDR
BANK
ADG
ADH
ADL
IMM
IMM16
IMM8
bn
dd
i
i1,i2
imm
immHimmL
ll
mmll
hhmmll
nn
n1,n2
rr
rr1rr 2
Description
Direct page register
Direct page register’s upper 8 bits
Direct page register’s lower 8 bits
Processor status register
Processor status register’s upper 8 bits
Processor status register’s lower 8 bits
Processor status register’s n-th bit
Memory contents
Contents of memory location specified by operand (1 byte data)
Contents of memory location specified by operand (1 word data)
Contents of memory location specified by operand (plural bytes data)
Contents of memory at address indicated by stack pointer
b-th memory location
Value of 24-bit address’ lower 16-bit (A15 to A0)
Value of 24-bit address’ upper 8-bit (A23 to A16)
Value of 24-bit address’ upper 8-bit (A23 to A16)
Value of 24-bit address’ middle 8-bit (A15 to A8)
Value of 24-bit address’ lower 8-bit (A7 to A0)
Immediate value
16-bit immediate value
8-bit immediate value
n-th bit of data
8-bit offset value
Number of transfer bytes or rotation
Number of registers pushed or pulled
8-bit immediate value
16-bit immediate value (immH specifies the upper 8-bit, and immL specifies
the lower 8-bit)
8-bit address value
16-bit address value (mm specifies the upper 8-bit and ll specifies the lower
8-bit)
24-bit address value (hh specifies the upper 8-bit, mm specifies the middle
8-bit and ll specifies the lower 8-bit)
8-bit data value
8-bit data value (Used when coding two 8-bit data side by side)
Signed 8-bit data value
Signed 16-bit data value (rr1 is the upper 8-bit value, and rr2 is the lower 8bit value)
7700 FAMILY SOFTWARE MANUAL
4–9
INSTRUCTIONS
4.1 Instruction set
4.1 Instruction Set
The 7700 Series, 7770 Series, and 7790 Series CPU uses the instruction set with 103 instructions. The
7750 Series CPU uses an extended instruction set (108 instructions) adding five additional instructions to
their instruction set.
«Additional instructions»
Instructions
Mnemonic
Addressing mode
Multiply with sign
MPYS
Supports addressing mode equivalent to MPY instruction
Divide with sign
DIVS
Supports addressing mode equivalent to DIV instruction
Arithmetic shift right
ASR
Supports addressing mode equivalent to ASL instruction
Extension with sign
EXTS
Extension zero
EXTZ
Supported the accumulator addressing mode
4.1.1 Data transfer instructions
The data transfer instructions move data between data and registers, between a register and the memory,
between registers or between memory devices.
Category Instruction
Load
Store
Transfer
4–2
Description
LDA
Loads the contents of memory into the accumulator.
LDM
Loads an immediate value into the memory.
LDT
Loads an immediate value into the data bank register.
LDX
Loads the contents of memory into the index register X.
LDY
Loads the contents of memory into the index register Y.
STA
Stores the contents of the accumulator in the memory.
STX
Stores the contents of the index register X in the memory.
STY
Stores the contents of the index register Y in the memory.
TAX
Transfers the contents of the accumulator A to the index register X.
TXA
Transfers the contents of the index register X to the accumulator A.
TAY
Transfers the contents of the accumulator A to the index register Y.
TYA
Transfers the contents of the index register Y to the accumulator A.
TSX
Transfers the contents of the stack pointer to the index register X.
TXS
Transfers the contents of the index register X to the stack pointer.
TAD
Transfers the contents of the accumulator A to the direct page register.
TDA
Transfers the contents of the direct page register to the accumulator A.
TAS
Transfers the contents of the accumulator A to the stack pointer.
TSA
Transfers the contents of the stack pointer to the accumulator A.
7700 FAMILY SOFTWARE MANUAL
INSTRUCTIONS
4.1 Instruction set
Category Instruction
Transfer
Description
TBD
Transfers the contents of the accumulator B to the direct page register.
TDB
Transfers the contents of the direct page register to the accumulator B.
TBS
Transfers the contents of the accumulator B to the stack pointer.
TSB
Transfers the contents of the stack pointer to the accumulator B.
TBX
Transfers the contents of the accumulator B to the index register X.
TXB
Transfers the contents of the index register X to the accumulator B.
TBY
Transfers the contents of the accumulator B to the index register Y.
TYB
Transfers the contents of the index register Y to the accumulator B.
TXY
Transfers the contents of the index register X to the index register Y.
TYX
Transfers the contents of the index register Y to the index register X.
MVN
Transfers a block of data from the lower addresses.
MVP
Transfers a block of data from the higher addresses.
PSH
Saves the contents of the specified register to the stack.
Stack
PUL
Restores the contents of stack to the specified register.
operation
PHA
Saves the contents of the accumulator A to the stack.
PLA
Restores the contents of stack to the accumulator A.
PHP
Saves the contents of the processor status register to the stack.
PLP
Restores the contents of stack to the processor status register.
PHB
Saves the contents of the accumulator B to the stack.
PLB
Restores the contents of stack to the accumulator B.
PHD
Saves the contents of the direct page register to the stack.
PLD
Restores the contents of stack to the direct page register.
PHT
Saves the contents of the data bank register to stack.
PLT
Restores the contents of stack to the data bank register.
PHX
Saves the contents of the index register X to the stack.
PLX
Restores the contents of stack to the index register X.
PHY
Saves the contents of the index register Y to the stack.
PLY
Restores the contents of stack to the index register Y.
PHG
Saves the contents of the program bank register to the stack.
PEA
Saves a the numeric of 2 bytes to the stack.
PEI
Saves the contents of 2 consecutive bytes in the direct page area to the stack.
PER
Saves the result of adding a 16-bit numeric value to the program counter contents to
the stack.
XAB
Swaps the contents of the accumulator A with the contents of the accumulator B.
Exchange
7700 FAMILY SOFTWARE MANUAL
4–3
INSTRUCTIONS
4.1 Instruction set
4.1.2 Arithmetic instructions
The arithmetic instructions perform addition, subtraction, multiplication, division, logical operation, comparison,
rotation, shifting and sign/zero extension of register and memory contents.
The following table summarizes the arithmetic instructions supported:
Note. The instructions with the mark “ * ” can be used in the 7750 Series only.
Category
Addition,
Instruction
ADC
Adds the contents of the accumulator, the contents of memory and the contents of the
carry flag.
SBC
Subtracts the contents of memory and the complement of the carry flag from the contents of the accumulator.
INC
Increments the accumulator or memory contents by 1.
DEC
Decrements the accumulator or memory contents by 1.
INX
Increments the contents of the index register X by 1.
DEX
Decrements the contents of the index register X by 1.
INY
Increments the contents of the index register Y by 1.
DEY
Decrements the contents of the index register Y by 1.
MPY
Multiples the contents of the accumulator A and the contents of memory.
Subtraction,
Multiplication,
Division
Description
MPYS*
Multiply the contents of the accumulator A and the contents of memory with sign.
DIV
Divides the numeric value whose lower byte is the contents of the accumulator A and
upper byte is the contents of the accumulator B by the contents of memory.
DIVS*
Divides the numeric value whose lower byte is the contents of the accumulator A and
upper byte is the contents of the accumulator B by the contents of memory with sign.
AND
Performs logical AND between the contents of the accumulator and the contents
of memory.
ORA
Performs logical OR between the contents of the accumulator and the contents of
memory.
EOR
Performs logical exclusive-OR between the contents of the accumulator and the contents of memory.
CMP
Compares the contents of the accumulator with the contents of memory.
CPX
Compares the contents of the index register X and the contents of memory.
CPY
Compares the contents of the index register Y and the contents of memory.
Shifting,
ASL
Shifts the contents of the accumulator or memory to the left by 1 bit.
Rotation
ASR*
Shifts the contents of the accumulator or memory holding sign to the right by 1 bit.
LSR
Shifts the contents of the accumulator or memory to the right by 1 bit.
ROL
Links the contents of accumulator or memory with the carry flag, and rotates the result
to the left by 1 bit.
ROR
Links the contents of accumulator or memory with the carry flag, and rotates the result
to the right by 1 bit.
RLA
Rotates the contents of the accumulator A to the left by the specified number of bits.
Logical operation
Comparison
Extension
with sign /
zero
4–4
EXTS*
Extend the low-order 8 bits of accumulator to 16 bits by sign extending.
EXTZ*
Extend the low-order 8 bits of accumulator to 16 bits by zero extending.
7700 FAMILY SOFTWARE MANUAL
INSTRUCTIONS
4.1 Instruction set
4.1.3 Bit manipulation instructions
The bit manipulation instructions set the specified bits of the processor status register or memory to “1” or “0”.
The following table summarizes the bit manipulation instructions supported:
Category
Instruction
Description
Bit manipulation
CLB
Clears the specified memory bit to “0”.
SEB
Sets the specified memory bit to “1”.
CLP
Clears the specified bit of the processor status register’s lower byte (PSL) to “0”.
SEP
Sets the specified bit of the processor status register’s lower byte (PSL) to “1”.
4.1.4 Flag manipulation instructions
The flag manipulation instructions set to “1” or clear to “0” the C, I, m and V flags.
The following table summarizes the flag manipulation instructions supported:
Category
Instruction
Description
Flag manipulation
CLC
Clears the contents of carry flag to “0”.
SEC
Sets the contents of carry flag to “1”.
CLM
Clears the contents of data length selection flag to “0”.
SEM
Sets the contents of data length selection flag to “1”.
CLI
Clears the contents of interrupt disable flag to “0”.
SEI
Sets the contents of interrupt disable flag to “1”.
CLV
Clears the contents of overflow flag to “0”.
4.1.5 Branching and return instructions
The branching and return instructions enable changing the program execution sequence.
The following table summarizes the branching and return instructions:
Category
Jump
Instruction
Description
JMP
Sets a new address in the program counter and jumps to the new address.
BRA
Jumps to the address obtained by adding an offset value to the contents of the program
counter.
JSR
Saves the contents of the program counter to the stack and then jumps to the new
address.
7700 FAMILY SOFTWARE MANUAL
4–5
INSTRUCTIONS
4.1 Instruction set
Category Instruction
Branch
Return
Description
BBC
Causes a branch if the specified memory bits are all “0”.
BBS
Causes a branch if the specified memory bits are all “1”.
BCC
Causes a branch if the carry flag is set to “0”.
BCS
Causes a branch if the carry flag is set to “1”.
BNE
Causes a branch if the zero flag is set to “0”.
BEQ
Causes a branch if the zero flag is set to “1”.
BPL
Causes a branch if the negative flag is set to “0”.
BMI
Causes a branch if the negative flag is set to “1”.
BVC
Causes a branch if the overflow flag is set to “0”.
BVS
Causes a branch if the overflow flag is set to “1”.
RTI
Returns from the interrupt routine to the original routine.
RTS
Returns from a subroutine to the original routine. The program bank register contents
are not restored.
RTL
Returns from a subroutine to the original routine. The program bank register contents
are restored.
4.1.6 Interrupt instruction (break instruction)
The interrupt instruction executes software interrupt.
Category Instruction
Break
BRK
Description
Executes a software interrupt.
4.1.7 Special instructions
The special instructions listed below control the clock generator circuit.
Category Instruction
Special
Description
WIT
Stops the internal clock.
STP
Stops the oscillator.
4.1.8 Other instruction
Category Instruction
Other
4–6
NOP
Description
Only advances the program counter.
7700 FAMILY SOFTWARE MANUAL
INSTRUCTIONS
4.2 Description of Instructions
4.2 Description of Instructions
This section describes the 7700 Family instructions at each instruction (Note 1). To the extent possible, each
instruction is described using one page per instruction. Each instruction description page is headed by the
instruction mnemonic, and the pages are arranged in alphabetical order of the mnemonics. For each instruction, operation and description of the instruction (Note 2, 3), status flag changes and a listing sorted by
addressing modes of the assembler coding format (Note 4), machine code, bytes-count and cycles-count (Note
5) are presented.
Note 1. The instructions with the mark “ * ” can be used in the 7750 Series only.
Note 2. In the description of instruction operation, the change in the PC (program counter) is described only
for instructions affecting the processing flow.
When an instruction is executed, the length of the instruction is added to content of the PC to form
the address of the next instruction to be executed. If a carry occurs during this addition, PG (program
bank register) is incremented by 1.
Note 3. In the description of each instruction, [Operation] indicates the contents of each register and memory
after executing the instruction. The detailed operation sequence is omitted.
Note 4. The assembler coding formats shown are general examples, and they may differ from the actual
formats for the assembler used. Please be sure to refer to the mnemonic coding description in the
manual for the assembler actually used for programming.
Note 5. The cycles-counts shown are the minimum possible, and they vary depending on the following conditions:
● Value of direct page register’s lower byte
The cycles-count shown are for when the direct page register’s lower byte (DPRL) is 0016. When
using an addressing mode that uses the direct page register with DPRL≠“00 16”, the cycles-count
will be 1 more than the value shown.
● Number of bytes that have been loaded in the instruction queue buffer
● Whether the first address of the memory read/write is even- or odd-numbered in accessing the 16bit data length.
● Accessing of an external memory are with BYTE=1 (using 8-bit external bus)
● Whether a wait is inserted in the bus cycle.
7700 FAMILY SOFTWARE MANUAL
4–7
INSTRUCTIONS
4.2 Description of Instructions
The table below lists the symbols that are used in this section:
Symbol
C
Z
I
D
x
m
V
N
IPL
+
–
×
/
V
V
∀
←
→
←
→
Acc
AccH
AccL
A
AH
AL
B
BH
BL
X
XH
XL
Y
YH
YL
S
PC
PCH
PCL
REL
PG
DT
4–8
Description
Carry flag
Zero flag
Interrupt disable flag
Decimal operation mode flag
Index register length selection flag
Data length selection flag
Overflow flag
Negative flag
Processor interrupt priority level
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
Exclusive OR
Negation
Movement to the arrow direction
Movement to the arrow direction
Movement to the arrow direction
Accumulator
Accumulator’s upper 8 bits
Accumulator’s lower 8 bits
Accumulator A
Accumulator A’s upper 8 bits
Accumulator A’s lower 8 bits
Accumulator B
Accumulator B’s upper 8 bits
Accumulator B’s lower 8 bits
Index register X
Index register X’s upper 8 bits
Index register X’s lower 8 bits
Index register Y
Index register Y’s upper 8 bits
Index register Y’s lower 8 bits
Stack pointer
Program counter
Program counter’s upper 8 bits
Program counter’s lower 8 bits
Relative address
Program bank register
Data bank register
7700 FAMILY SOFTWARE MANUAL
INSTRUCTIONS
4.2 Description of Instructions
Symbol
DPR
DPRH
DPRL
PS
PSH
PSL
PSn
M
M(n)
M(n+1,n)
M(m to n)
M(S)
Mb
ADDR
BANK
ADG
ADH
ADL
IMM
IMM16
IMM8
bn
dd
i
i1,i2
imm
immHimmL
ll
mmll
hhmmll
nn
n1,n2
rr
rr1rr 2
Description
Direct page register
Direct page register’s upper 8 bits
Direct page register’s lower 8 bits
Processor status register
Processor status register’s upper 8 bits
Processor status register’s lower 8 bits
Processor status register’s n-th bit
Memory contents
Contents of memory location specified by operand (1 byte data)
Contents of memory location specified by operand (1 word data)
Contents of memory location specified by operand (plural bytes data)
Contents of memory at address indicated by stack pointer
b-th memory location
Value of 24-bit address’ lower 16-bit (A15 to A0)
Value of 24-bit address’ upper 8-bit (A23 to A16)
Value of 24-bit address’ upper 8-bit (A23 to A16)
Value of 24-bit address’ middle 8-bit (A15 to A8)
Value of 24-bit address’ lower 8-bit (A7 to A0)
Immediate value
16-bit immediate value
8-bit immediate value
n-th bit of data
8-bit offset value
Number of transfer bytes or rotation
Number of registers pushed or pulled
8-bit immediate value
16-bit immediate value (immH specifies the upper 8-bit, and immL specifies
the lower 8-bit)
8-bit address value
16-bit address value (mm specifies the upper 8-bit and ll specifies the lower
8-bit)
24-bit address value (hh specifies the upper 8-bit, mm specifies the middle
8-bit and ll specifies the lower 8-bit)
8-bit data value
8-bit data value (Used when coding two 8-bit data side by side)
Signed 8-bit data value
Signed 16-bit data value (rr1 is the upper 8-bit value, and rr2 is the lower 8bit value)
7700 FAMILY SOFTWARE MANUAL
4–9
ADC
ADC
ADd with Carry
Function
:
Addition with carry
Operation
:
Acc ← Acc + M + C
When m=0
Acc
Acc
M(n+1,n)
←
+
C
+
When m=1
Acc L
Acc L
←
Description
:
M(n)
+
C
+
Adds the contents of the accumulator, memory and carry flag, and places the result in the
accumulator.
Executed as binary addition if the decimal operation mode flag D is set to 0.
Executed as decimal addition if the decimal operation mode flag D is set to 1.
Status flags
4–10
IPL:
Not affected.
N :
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0. Meaningless for decimal addition.
V :
Set to 1 when binary addition of signed data result in a value outside the range of -32768 to
+32767 (-128 to +127 if the data length selection flag m is set to 1). Otherwise, cleared to 0.
Meaningless for decimal addition.
m :
Not affected.
x
:
Not affected.
D :
Not affected.
I
Not affected.
:
Z :
Set to 1 when the result of operation is 0. Otherwise, cleared to 0. Meaningless for decimal
addition.
C :
When the data length selection flag m is set to 0, set to 1 if binary addition exceeds +65535
or if decimal addition exceeds +9999. Otherwise, cleared to 0. When the data length selection
flag m is set to 1, set to 1 if binary addition exceeds +255 or if decimal addition exceeds +99.
Otherwise, cleared to 0.
7700 FAMILY SOFTWARE MANUAL
ADC
ADC
ADd with Carry
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
Direct
ADC A, #imm
ADC A, dd
Direct indexed X
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Absolute
Absolute indexed X
Absolute indexed Y
Absolute long
ADC A, dd, X
ADC A, (dd)
ADC A, (dd, X)
ADC A, (dd), Y
ADCL A, (dd)
ADCL A, (dd), Y
ADC A, mmll
ADC A, mmll, X
ADC A, mmll, Y
ADC A, hhmmll
Absolute long indexed X
Stack pointer relative
Stack pointer relative
indirect indexed Y
ADC A, hhmmll, X
ADC A, nn,S
ADC A, (nn, S), Y
6916, imm
6516, dd
7516, dd
7216, dd
6116, dd
7116, dd
6716, dd
7716, dd
6D16, ll, mm
7D16, ll, mm
7916, ll, mm
6F16, ll, mm, hh
7F16, ll, mm, hh
6316, nn
7316, nn
2
2
2
2
2
2
2
2
3
3
3
4
4
2
2
2
4
5
6
7
8
10
11
4
6
6
6
7
5
8
(Note 1) This table applies when using the accumulator A. If using the accumulator B, replace “A” with “B”.
In this case, “4216” is added at the beginning of the machine code, the bytes-count increases by
1 and the cycles-count increases by 2.
(Note 2) When operating on 16-bit data in the immediate addressing mode with the data length selection flag
m set to 0, the bytes-count increases by 1.
7700 FAMILY SOFTWARE MANUAL
4–11
AND
logical AND
Function
:
Logical AND
Operation
:
Acc ← Acc
When m=0
AND
M
V
Acc
Acc
←
M(n+1,n)
V
When m=1
Acc L
←
Description
:
M(n)
V
Acc L
Performs logical AND between the contents of the accumulator and the contents of memory,
and places the result in the accumulator.
Status flags
4–12
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
7700 FAMILY SOFTWARE MANUAL
AND
AND
logical AND
Addressing mode
Syntax
Immediate
AND A, #imm
Direct
Direct indexed X
Direct indirect
Direct indexed X indirect
AND
AND
AND
AND
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Absolute
Absolute indexed X
Absolute indexed Y
Absolute long
Absolute long indexed X
Stack pointer relative
Stack pointer relative
AND A, (dd), Y
ANDL A, (dd)
ANDL A, (dd), Y
AND A, mmll
AND A, mmll, X
AND A, mmll, Y
AND A, hhmmll
AND A, hhmmll, X
AND A, nn, S
AND A, (nn, S), Y
A,
A,
A,
A,
dd
dd, X
(dd)
(dd, X)
Machine code
Bytes
Cycles
29 16, imm
25 16, dd
35 16, dd
32 16, dd
21 16, dd
31 16, dd
27 16, dd
3716, dd
2D 16, ll, mm
3D 16, ll, mm
39 16, ll, mm
2F 16, ll, mm, hh
3F16, ll, mm, hh
23 16, nn
33 16, nn
2
2
2
2
2
2
2
2
3
3
3
4
4
2
2
2
4
5
6
7
8
10
11
4
6
6
6
7
5
8
indirect indexed Y
(Note 1) This table applies when using the accumulator A. If using the accumulator B, replace “A” with
“B”. In this case, “4216” is added at the beginning of the machine code, the bytes-count increases
by 1 and the cycles-count increases by 2.
(Note 2) When operating on 16-bit data in the immediate addressing mode with the data length selection
flag m set to 0, the bytes-count increases by 1.
7700 FAMILY SOFTWARE MANUAL
4–13
ASL
ASL
Arithmetic Shift Left
Function
:
Arithmetic shift left
Operation
:
C
Acc or M
← 1 bit shift to left ← 0
When m=0
C
b15
Acc or M(n+1,n)
← ← ← ← ←
b0
← ← ← ← ←0
When m=1
C
b7
AccL or M(n)
b0
← ← ← ← ← ← ← ← ← 0
Description
:
Shifts all bits of the accumulator or memory one place to the left. Bit 0 is loaded with 0. The
carry flag C is loaded from bit 15 (or bit 7 when the data length selection flag m is set to 1)
of the data before the shift.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Set to 1 when bit 15 (or bit 7 when the data length selection flag m is set to 1) before the
operation is 1. Otherwise, cleared to 0.
Addressing mode
Syntax
Machine code
Bytes Cycles
Accumulator
Direct
Direct indexed X
Absolute
Absolute indexed X
ASL A
0A16
ASL
ASL
ASL
ASL
06 16, dd
16 16, dd
0E 16, ll, mm
1E 16, ll, mm
1
2
2
3
3
dd
dd, X
mmll
mmll, X
2
7
7
7
8
(Note 1)The accumulator addressing mode's specification in this table applies when using the accumulator
A. If using the accumulator B, replace “A” with “B”. In this case, “4216 ” is added at the beginning
of the machine code, the bytes-count increases by 1 and the cycles-count increases by 2.
4–14
7700 FAMILY SOFTWARE MANUAL
ASR
ASR
Arithmetic Shift Right
Function
:
Arithmetic shift right
Operation
:
Acc or M
→ 1 bit shift to Right
This instruction can be used
in the 7750 Series only.
C
→
MSB
When m=0
b15
Acc or M(n+1,n)
→ → → → →
b0
C
→ → → → →
When m=1
b7
AccL or M(n)
b0
C
→ → → → → → → → →
Description
:
Shifts all bits of the accumulator or memory one place to the right. Bit 15 (or bit 7 when the
data length selection flag m is set to 1) is loaded with the value before shift. The carry flag
C is loaded from bit 0 of the data before the shift.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Set to 1 when bit 0 before the operation is 1. Otherwise, cleared to 0.
Addressing mode
Syntax
Machine code
Bytes Cycles
8916 , 0816
4216 , 0816
8916, 0616, dd
8916 ,1616 , dd
89 16, 0E16, ll, mm
89 16, 1E16, ll, mm
2
2
3
3
4
4
Accumulator
ASR A
Accumulator
Direct
Direct indexed X
Absolute
ASR
ASR
ASR
ASR
Absolute indexed X
ASR mmll, X
B
dd
dd, X
mmll
7700 FAMILY SOFTWARE MANUAL
5
5
10
10
10
11
4–15
BBC
BBC
Branch on Bit Clear
Function
:
Branch on condition
Operation
:
Mb = 0 ? (b is the specified bits)
IMM = 0 (True)
PC ← PC + n ± REL
V
When M
V
When M
IMM ≠ 0 (False)
PC ← PC + n
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC
: PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ IMM is an immediate value indicating the bit to be tested with “1”.
❊ n is the number of instruction bytes in each addressing mode of the BBC instruction
❊ REL is relative value (–128 to +127) indicated by the last byte of the instruction
When m=0
M(n+1,n)
IMM16
V
When m=1
M(n)
IMM8
V
Description
:
The BBC instruction tests the specified bits (which may be specified simultaneously) of
memory. The instruction causes a branch to the specified address when the specified bits are
all 0. The branch address is specified by a relative address.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Direct bit relative
BBC #imm, dd, rr
Absolute bit relative
BBC #imm, mmll, rr
3416, dd, imm, rr
3C16, ll, mm, imm, rr
4
5
7
8
(Note 1) The bytes-count increases by 1 when operating on 16-bit data with the data length selection flag
m set to 0.
(Note 2) The cycles-count increases by 2 when a branch occurs.
4–16
7700 FAMILY SOFTWARE MANUAL
BBS
BBS
Branch on Bit Set
Function
:
Branch on condition
Operation
:
Mb = 1 ? (b is the specified bits)
IMM = 0 (True)
PC ← PC + n ± REL
V
When M
V
When M
IMM ≠ 0 (False)
PC ← PC + n
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC
: PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ n is the number of instruction bytes of the BBS instruction
❊ REL is relative value (–128 to +127) indicated by the last byte of the instruction
When m=0
M(n+1,n)
IMM16
V
When m=1
M(n)
IMM8
V
Description
:
The BBS instruction tests the specified bits (which may be specified simultaneously) of
memory. The instruction causes a branch to the specified address when the specified bits are
all 1. The branch address is specified by a relative address.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes Cycles
Direct bit relative
Absolute bit relative
BBS #imm, dd, rr
BBS #imm, mmll, rr
2416, dd, imm, rr
2C16, ll, mm, imm, rr
4
5
7
8
(Note 1) The bytes-count increases by 1 when operating on 16-bit data with the data length selection flag
m set to 0.
(Note 2) The cycles-count increases by 2 when a branch occurs.
7700 FAMILY SOFTWARE MANUAL
4–17
BCC
BCC
Branch on Carry Clear
Function
:
Branch on condition
Operation
:
C = 0 ?
When C = 0 (True)
PC ← PC + 2 ± REL
When C = 1 (False)
PC ← PC + 2
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC
: PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ 2 is the number of instruction bytes of the BCC instruction
❊ REL is relative value (–128 to +127) indicated by the 2nd byte of the instruction
Description
:
When the carry flag C is clear (0), the BCC instruction causes a branch to the specified
address. The branch address is specified by a relative address.
When the carry flag C is set (1), the program advances to next step without any action.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes Cycles
Relative
BCC rr
9016, rr
2
(Note 1) The cycles-count increases by 2 when a branch occurs.
4–18
7700 FAMILY SOFTWARE MANUAL
4
BCS
BCS
Branch on Carry Set
Function
:
Branch on condition
Operation
:
C = 1 ?
When C = 1 (True)
PC ← PC + 2 ± REL
When C = 0 (False)
PC ← PC + 2
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC
: PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ 2 is the number of instruction bytes of the BCS instruction
❊ REL is relative value (–128 to +127) indicated by the 2nd byte of the instruction
Description
:
When the carry flag C is set (1), the BCS instruction causes a branch to the specified address.
The branch address is specified by a relative address.
When the carry flag C is clear (0), the program advances to next step without any action.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Relative
BCS rr
B016, rr
2
4
(Note 1) The cycles-count increases by 2 when a branch occurs.
7700 FAMILY SOFTWARE MANUAL
4–19
BEQ
BEQ
Branch on Equal
Function
:
Branch on condition
Operation
:
Z = 1 ?
When Z = 1 (True)
PC ← PC + 2 ± REL
When Z = 0 (False)
PC ← PC + 2
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC
: PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ 2 is the number of instruction bytes of the BEQ instruction
❊ REL is relative value (–128 to +127) indicated by the 2nd byte of the instruction
Description
:
When the zero flag Z is set (1), the BEQ instruction causes a branch to the specified address.
The branch address is specified by a relative address.
When the zero flag Z is clear (0), the program advances to next step without any action.
Status flags
4–20
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Relative
BEQ rr
F016, rr
2
4
7700 FAMILY SOFTWARE MANUAL
BMI
BMI
Branch on Result Minus
Function
:
Branch on condition
Operation
:
N = 1 ?
When N = 1 (True)
PC ← PC + 2 ± REL
When N = 0 (False)
PC ← PC + 2
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC : PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ 2 is the number of instruction bytes of the BMI instruction
❊ REL is relative value (–128 to +127) indicated by the 2nd byte of the instruction
Description
:
When the negative flag N is set (1), the BMI instruction causes a branch to the specified
address. The branch address is specified by a relative address.
When the negative flag N is clear (0), the program advances to next step without any action.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Relative
BMI rr
3016, rr
2
4
(Note 1) The cycles-count increases by 2 when a branch occurs.
7700 FAMILY SOFTWARE MANUAL
4–21
BNE
BNE
Branch on Not Equal
Function
:
Branch on condition
Operation
:
Z = 0 ?
When Z = 0 (True)
PC ← PC + 2 ± REL
When Z = 1 (False)
PC ← PC + 2
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC : PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ 2 is the number of instruction bytes of the BNE instruction
❊ REL is relative value (–128 to +127) indicated by the 2nd byte of the instruction
Description
:
When the zero flag Z is clear (0), the BNE instruction causes a branch to the specified
address. The branch address is specified by a relative address.
When the zero flag Z is set (1), the program advances to next step without any action.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Relative
BNE rr
D016, rr
2
4
(Note 1) The cycles-count increases by 2 when a branch occurs.
4–22
7700 FAMILY SOFTWARE MANUAL
BPL
BPL
Branch on Result Plus
Function
:
Branch on condition
Operation
:
N = 0 ?
When N = 0 (True)
PC ← PC + 2 ± REL
When N = 1 (False)
PC ← PC + 2
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC : PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ 2 is the number of instruction bytes of the BPL instruction
❊ REL is relative value (–128 to +127) indicated by the 2nd byte of the instruction
Description
:
When the negative flag N is clear (0), the BPL instruction causes a branch to the specified
address. The branch address is specified by a relative address.
When the negative flag N is set (1), the program advances to next step without any action.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Relative
BPL rr
1016, rr
2
4
(Note 1) The cycles-count increases by 2 when a branch occurs.
7700 FAMILY SOFTWARE MANUAL
4–23
BRA
BRA
Branch Always
Function
:
Branch always
Operation
:
PC ← branch address (relative)
PC ← PC + n ± REL
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC : PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ n is the number of instruction bytes in each addressing mode of the BRA instruction
❊ REL is relative value (–128 to +127) indicated by the last 1-byte or last 2-byte of the
instruction
Branch area : For short relative –128 to +127
For long relative
–32768 to +32767
Description
:
The BRA instruction causes a branch to the specified address. The branch address is
specified by a relative address.
Status flags
:
Not affected.
4–24
Addressing mode
Syntax
Machine code
Bytes
Cycles
Relative
BRA rr
BRAL rr1rr 2
8016, rr
8216, rr2, rr1
2
3
4
7700 FAMILY SOFTWARE MANUAL
4
BRK
BRK
Force Break
Function
:
Software interrupt
Operation
:
Stack
← PG, PC, PS
I
←1
PG, PC ← 00, Contents of BRK interrupt vector
PC
M(S
← PC + 2
to
S–4) ← PG, PC, PS
S
←S – 5
I
←1
PG
← 0016
PC
← M(FFFB16 ,FFFA16)
Stack
(S) in just after instruction execution
(S) in just before instruction execution
PSL
PSH
PCL
PCH
PG
❊ “2” means the byte number of the BRK instruction, and “PC+2” is the address that stored
the next instruction
Description
:
When the BRK instruction is executed, the CPU first saves the address where the next
instruction is stored, and then saves the contents of the processor status register on the stack.
Then, the CPU executes a branch to the address in bank-0 the lower portion of which is
specified by the contents of FFFA16 in bank-0 and the upper portion specified by the contents
of FFFB16 in bank-0.
Status flags
IPL :
Not affected.
N
:
Not affected.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Set to 1.
Z
:
Not affected.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
BRK #nn
0016,EA16
2
15
(Note 1) The instruction's second byte is ignored, so any value impossible.
7700 FAMILY SOFTWARE MANUAL
4–25
BVC
BVC
Branch on Overflow Clear
Function
:
Branch on condition
Operation
:
V = 0 ?
When V = 0 (True)
PC ← PC + 2 ± REL
When V = 1 (False)
PC ← PC + 2
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC : PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ 2 is the number of instruction bytes of the BRA instruction
❊ REL is relative value (–128 to +127) indicated by the 2nd byte of the instruction
Description
:
When the overflow flag V is clear (0), the BVC instruction causes a branch to the specified
address. The branch address is specified by a relative address.
When the overflow flag V is set (1), the program advances to next step without any action.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Relative
BVC rr
5016, rr
2
4
(Note 1) The cycles-count increases by 2 when a branch occurs.
4–26
7700 FAMILY SOFTWARE MANUAL
BVS
BVS
Branch on Overflow Set
Function
:
Branch on condition
Operation
:
V = 1 ?
When V = 1 (True)
PC ← PC + 2 ± REL
When V = 0 (False)
PC ← PC + 2
❊ PG changes according to the result of the above PC operation
• if carry occurs in PC : PG ← PG + 1
• if borrow occurs in PC : PG ← PG – 1
❊ 2 is the number of instruction bytes of the BVS instruction
❊ REL is relative value (–128 to +127) indicated by the 2nd byte of the instruction
Description
:
When the overflow flag V is set (1), the BVS instruction causes a branch to the specified
address. The branch address is specified by a relative address.
When the overflow flag V is clear (0), the program advances to next step without any action.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Relative
BVS rr
70 16, rr
2
4
(Note 1) The cycles-count increases by 2 when a branch occurs.
7700 FAMILY SOFTWARE MANUAL
4–27
CLB
CLB
Clear Bit
Function
:
Bit manipulation
Operation
:
Mb ← 0 (b is the specified bits)
When m=0
M(n+1,n)
M(n+1,n)
←
IMM16
V
When m=1
M(n)
←
IMM8
V
M(n)
❊ IMM is immediate value indicating the bit to be cleared with a “1” and is specified by the
last 1 or 2 bytes of the instruction.
Description
:
The CLB instruction clears the specified memory bits to 0. Multiple bits to be cleared can be
specified at one time.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Direct bit
Absolute bit
CLB #imm, dd
CLB #imm, mmll
1416, dd, imm
1C16, ll, mm, imm
3
4
8
9
(Note 1) The bytes-count increases by 1 when operating on 16-bit data with the data length selection flag
m set to 0.
4–28
7700 FAMILY SOFTWARE MANUAL
CLC
CLC
Clear Carry Flag
Function
:
Flag manipulation
Operation
:
C ←0
Description
:
Clears the contents of carry flag C to 0.
Status flags
IPL :
Not affected.
N
:
Not affected.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Not affected.
C
:
Cleared to 0.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
CLC
1816
1
2
7700 FAMILY SOFTWARE MANUAL
4–29
CLI
CLI
Clear Interrupt Disable Status
Function
:
Flag manipulation
Operation
:
I ← 0
Description
:
Clears the interrupt disable flag I to 0.
Status flags
4–30
IPL :
Not affected.
N
:
Not affected.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Cleared to 0.
Z
:
Not affected.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
CLI
5816
1
2
7700 FAMILY SOFTWARE MANUAL
CLM
CLM
Clear m Flag
Function
:
Flag manipulation
Operation
:
m ← 0
Description
:
Clears the data length selection flag m to 0.
Status flags
IPL :
Not affected.
N
:
Not affected.
V
:
Not affected.
m :
Cleared to 0.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Not affected.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
CLM
D816
1
2
7700 FAMILY SOFTWARE MANUAL
4–31
CLP
CLP
Clear Processor Status
Function
:
Flag manipulation
Operation
:
PS Lb ← 0 (b is the specified flags)
V
PS L ← PSL
IMM8
❊ IMM is a 1 byte immediate value indicating the flag to be cleared with a “1” and is
specified by the second byte of the instruction.
b7 b6 b5 b4 b3 b2 b1 b0
N V m x D I Z C PSL
Description
:
Clears the processor status flags specified by the bit pattern in the second byte of the
instruction to 0.
Status flags
:
The specified status flags are cleared to “0”. IPL is not affected.
4–32
Addressing mode
Syntax
Machine code
Bytes Cycles
Immediate
CLP #imm
C2 16, imm
2
7700 FAMILY SOFTWARE MANUAL
4
CLV
CLV
Clear Overflow Flag
Function
:
Flag manipulation
Operation
:
V ←0
Description
:
Clears the overflow flag V to 0.
Status flags
IPL :
Not affected.
N
:
Not affected.
V
:
Cleared to 0.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Not affected.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
CLV
B816
1
2
7700 FAMILY SOFTWARE MANUAL
4–33
CMP
CMP
Compare
Function
:
Compare
Operation
:
Acc – M
When m=0
Acc
M(n+1,n)
–
When m=1
Acc L
M(n)
–
Description
:
Subtracts the contents of memory from the contents of the accumulator. The accumulator and
memory contents are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Set to 1 if the result of operation is 0 or larger. Otherwise, cleared to 0.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
Direct
Direct indexed X
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Absolute
Absolute indexed X
Absolute indexed Y
Absolute long
Absolute long indexed X
Stack pointer relative
Stack pointer relative
indirect indexed Y
CMP A, #imm
CMP A, dd
CMP A, dd, X
CMP A, (dd)
CMP A, (dd, X)
CMP A, (dd), Y
CMPL A, (dd)
CMPL A, (dd), Y
CMP A, mmll
CMP A, mmll, X
CMP A, mmll, Y
CMP A, hhmmll
CMP A, hhmmll, X
CMP A, nn, S
CMP A, (nn, S), Y
C916 , imm
C5 16, dd
D5 16, dd
D2 16, dd
C1 16, dd
D1 16, dd
C7 16, dd
D716, dd
CD 16, ll, mm
DD 16, ll, mm
D9 16, ll, mm
CF 16, ll, mm, hh
DF16, ll, mm, hh
C3 16, nn
D3 16, nn
2
2
2
2
2
2
2
2
3
3
3
4
4
2
2
2
4
5
6
7
8
10
11
4
6
6
6
7
5
8
(Note 1) This table applies when using the accumulator A. If using the accumulator B, replace “A” with
“B”. In this case, “4216 ” is added at the beginning of the machine code, the bytes-count increases
by 1 and the cycles-count increases by 2.
(Note 2) When operating on 16-bit data in the immediate addressing mode with the data length
selection flag m set to 0, the bytes-count increases by 1.
4–34
7700 FAMILY SOFTWARE MANUAL
CPX
CPX
Compare Memory and Index Register X
Function
:
Compare
Operation
:
X – M
When x=0
X
M(n+1,n)
–
When x=1
XL
M(n)
–
Description
:
Subtracts the contents of memory from the contents of the index register X. The index register
X and memory contents are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Set to 1 if the result of operation is 0 or larger. Otherwise, cleared to 0.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
Direct
Absolute
CPX #imm
CPX dd
CPX mmll
E016 , imm
E416, dd
EC16, ll, mm
2
2
3
2
4
4
(Note 1) When operating on 16-bit data in the immediate addressing mode with the index register length
selection flag x set to 0, the bytes-count increases by 1.
7700 FAMILY SOFTWARE MANUAL
4–35
CPY
CPY
Compare Memory and Index Register Y
Function
:
Compare
Operation
:
Y – M
When x=0
Y
M(n+1,n)
–
When x=1
YL
M(n)
–
Description
:
Subtracts the contents of memory from the contents of the index register Y. The index register
Y and memory contents are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Set to 1 if the result of operation is 0 or larger. Otherwise, cleared to 0.
Addressing mode
Syntax
Machine code
Bytes Cycles
Immediate
Direct
Absolute
CPY #imm
CPY dd
CPY mmll
C016, imm
C416,dd
CC 16, ll, mm
2
2
3
2
4
4
(Note 1) When operating on 16-bit data in the immediate addressing mode with the index register length
selection flag x set to 0, the bytes-count increases by 1.
4–36
7700 FAMILY SOFTWARE MANUAL
DEC
DEC
Decrement by One
Function
:
Decrement
Operation
:
Acc ← Acc – 1
M ←M – 1
or
When m=0
Acc
M(n+1,n)
←
– 1
or
M(n+1,n)
M(n+1,n)
←
– 1
When m=1
Acc L
AccL
←
– 1
or
M(n)
M(n)
←
Description
:
– 1
Subtracts 1 from the contents of the accumulator or memory.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Accumulator
Direct
Direct indexed X
Absolute
Absolute indexed X
DEC
DEC
DEC
DEC
DEC
1A16
C616, dd
D616, dd
CE16, ll, mm
DE16, ll, mm
1
2
2
3
3
2
7
7
7
8
A
dd
dd, X
mmll
mmll, X
(Note 1) The accumulator addressing mode's specification in this table applies when using the accumulator
A. If using the accumulator B, replace “A” with “B”. In this case, “4216 ” is added at the beginning
of the machine code, the bytes-count increases by 1 and the cycles-count increases by 2.
7700 FAMILY SOFTWARE MANUAL
4–37
DEX
DEX
Decrement Index Register X by One
Function
:
Decrement
Operation
:
X ←X – 1
When x=0
X
X
←
– 1
When x=1
XL
XL
←
Description
:
– 1
Subtracts 1 from the contents of the index register X.
Status flags
4–38
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
DEX
CA16
1
2
7700 FAMILY SOFTWARE MANUAL
DEY
DEY
Decrement Index Register Y by One
Function
:
Decrement
Operation
:
Y ←Y – 1
When x=0
Y
Y
←
– 1
When x=1
YL
YL
←
Description
:
– 1
Subtracts 1 from the contents of the index register Y.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
DEY
8816
1
2
7700 FAMILY SOFTWARE MANUAL
4–39
DIV
DIV
Divide
Function
:
Division (Unsigned)
Operation
:
A(quotient), B(remainder) ← (B, A) / M
When m=0
A
B
,
Quotient
B
Remainder
←
A
Dividend
M(n+1,n)
÷
Divisor
When m=1
AL
BL
BL
Quotient , Remainder ←
Description
:
AL
M(n)
Dividend
÷ Divisor
When the data length selection flag m is set to 0, a 32-bit data stored in the accumulators B
(upper 16 bits) and A (lower 16 bits) are divided by a 16-bit data in memory. The quotient
is placed in the accumulator A, and the remainder is placed in the accumulator B.
When the data length selection flag m is set to 1, a 16-bit data stored in the lower 8 bits of
the accumulators B (upper 8 bits) and A (lower 8 bits) are divided by an 8 bit data in memory.
The quotient is placed in the lower 8 bits of the accumulator A, and the remainder is placed
in the lower 8 bits of the accumulator B.
If an overflow occurs as a result of the operation, the V flag is set and the content of the
accumulator is unpredictable.
When divisor is 0, the zero division interrupt is generated, in which case the contents of the
program bank register, program counter, and processor status register are saved on the stack
and a branch occurs to the address in bank-0 as specified by the zero division interrupt vector.
Accumulator contents are not changed. In this case, the content of the accumulator is
unchanged.
Status flags
IPL
:
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of quotient from
the operation is 1. Otherwise, cleared to 0.
❊ When an overflow occurs as a result of the operation or divisor is 0, N flag is not affected.
V
:
Clear to 0.
❊ Set to 1 when an overflow occurs
❊ Not affected when divisor is 0
m
:
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the quotient from the operation is 0. Otherwise, cleared to 0. No changes occur
when divisor is 0.
❊ When an overflow occurs as a result of the operation or divisor is 0, Z flag is not affected.
C
:
Clear to 0.
❊ Set to 1 when an overflow occurs
❊ Not affected when divisor is 0
4–40
7700 FAMILY SOFTWARE MANUAL
DIV
DIV
Divide
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
Direct
Direct indexed X
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Absolute
Absolute indexed X
Absolute indexed Y
Absolute long
Absolute long indexed X
Stack pointer relative
Stack pointer relative
indirect indexed Y
DIV #imm
DIV dd
DIV dd, X
DIV (dd)
DIV (dd, X)
DIV (dd), Y
DIVL (dd)
DIVL (dd), Y
DIV mmll
DIV mmll, X
DIV mmll, Y
DIV hhmmll
DIV hhmmll, X
DIV nn, S
DIV (nn, S), Y
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
3
3
3
3
3
3
3
3
4
4
4
5
5
3
3
27
29
30
31
32
33
35
36
29
31
31
31
32
30
33
2916, imm
2516, dd
3516, dd
3216, dd
2116, dd
3116, dd
2716, dd
3716, dd
2D16, ll, mm
3D16, ll ,mm
3916, ll ,mm
2F16, ll, mm, hh
3F16, ll, mm, hh
2316, nn
3316, nn
(Note 1) When operating on 16-bit data in the immediate addressing mode with the data length selection
flag m set to 0, the bytes-count increases by 1.
(Note 2) The cycles-count in this table are for 16-bit ÷ 8-bit operations. For 32-bit ÷ 16-bit operations, the
cycles-count increases by 16.
(Note 3) The cycle count in this table and Note 2 are the value when the operation completes normally
(no interrupt has occurred). If a zero divide interrupt has occurred, the cycle counts in the above
table are decremented by 8 regardless of the data length.
7700 FAMILY SOFTWARE MANUAL
4–41
DIVS
DIVS
Divide with Sign
Function
:
Division (Signed)
Operation
:
A(quotient), B(remainder) ← (B, A) / M
This instruction can be used
in the 7750 Series only.
When m=0
A
B
, s Remainder
s Quotient
B
← s
A
Dividend
M(n+1,n)
÷ s Divisor
When m=1
AL
BL
BL
AL
M(n)
Quotient , Remainder ←
Dividend
s
s
s
÷ Divisor
s
❊ “s” means a sign bit that is the most significant bit of the data
Description
:
When the data length selection flag m is set to 0, a signed 32-bit data stored in the
accumulators B (upper 16 bits) and A (lower 16 bits) are divided by a signed 16-bit data in
memory. As a result of the operation, the quotient is stored in accumulator A and the
remainder is stored in accumulator B as signed 16-bit data.
When the data length selection flag m is set to 1, a signed 16-bit data stored in the lower 8
bits of the accumulators B (upper 8 bits) and A (lower 8 bits) are divided by a signed 8 bit data
in memory. As a result of the operation, the quotient is stored in low-order 8 bits of
accumulator A and the remainder is stored in low-order 8 bits of accumulator B as signed 8bit data.
The sign of remainder becomes same as dividend.
When an overflow results from this operation (the quotient exceeds the extent –32767 to
+32767 if m=0 or –127 to +127 if m=1) neglect removed out, the V flag is set. In this case,
the content of the accumulator is unpredictable.
When divisor is 0, the zero division interrupt is generated, in which case the contents of the
processor status register are saved on the stack and a branch occurs to the address in bank
0 16 as specified by the zero division interrupt vector. And accumulator contents are not
changed.
Status flags
IPL
:
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of quotient from
the operation is 1. Otherwise, cleared to 0.
❊ When an overflow occurs as a result of the operation or divisor is 0, N flag is not affected.
V
:
Clear to 0.
❊ Set to 1 when an overflow occurs
❊ Not affected when divisor is 0
m
:
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
❊ Set to 1 when divisor is 0
4–42
7700 FAMILY SOFTWARE MANUAL
DIVS
Z
DIVS
Divide with Sign
:
Set to 1 when the quotient from the operation is 0. Otherwise, cleared to 0. No changes occur
when divisor is 0.
❊ When an overflow occurs as a result of the operation or divisor is 0, Z flag is not affected.
C
:
Clear to 0.
❊ Set to 1 when an overflow occurs
❊ Not affected when divisor is 0
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
Direct
Direct indexed X
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Absolute
Absolute indexed X
Absolute indexed Y
Absolute long
Absolute long indexed X
Stack pointer relative
Stack pointer relative
indirect indexed Y
DIVS #imm
DIVS dd
DIVS dd, X
DIVS (dd)
DIVS (dd, X)
DIVS (dd), Y
DIVSL (dd)
DIVSL (dd), Y
DIVS mmll
DIVS mmll, X
DIVS mmll, Y
DIVS hhmmll
DIVS hhmmll, X
DIVS nn, S
DIVS (nn, S), Y
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
3
3
3
3
3
3
3
3
4
4
4
5
5
3
3
29
31
32
33
34
35
37
38
31
33
33
33
34
32
35
A916, imm
A516, dd
B516, dd
B216, dd
A116, dd
B116, dd
A716, dd
B716, dd
AD16, ll, mm
BD16, ll ,mm
B916, ll ,mm
AF16, ll, mm, hh
BF16, ll, mm, hh
A316, nn
B316, nn
(Note 1) When operating on 16-bit data in the immediate addressing mode with the data length selection
flag m set to 0, the bytes-count increases by 1.
(Note 2) The cycles-count in this table are for 16-bit ÷ 8-bit operations. For 32-bit ÷ 16-bit operations, the
cycles-count increases by 16.
(Note 3) The cycle count in this table and Note 2 are the value when the operation completes normally
(no interrupt has occurred). If a zero divide interrupt has occurred, the cycle counts in the above
table are decremented by 10 regardless of the data length.
7700 FAMILY SOFTWARE MANUAL
4–43
EOR
EOR
Exclusive OR Memory with Accumulator
Function
:
Logical EXCLUSIVE OR
Operation
:
Acc ← Acc ∀ M
When m=0
Acc
Acc
←
M(n+1,n)
∀
When m=1
Acc L
Acc L
←
Description
:
M(n)
∀
Performs the logical EXCLUSIVE OR between the contents of the accumulator and the
contents of memory, and places the result in the accumulator.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
Direct
Direct indexed X
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Absolute
Absolute indexed X
Absolute indexed Y
Absolute long
Absolute long indexed X
Stack pointer relative
Stack pointer relative
indirect indexed Y
EOR A, #imm
EOR A, dd
EOR A, dd, X
EOR A, (dd)
EOR A, (dd, X)
EOR A, (dd), Y
EORL A, (dd)
EORL A, (dd), Y
EOR A, mmll
EOR A, mmll, X
EOR A, mmll, Y
EOR A, hhmmll
EOR A, hhmmll, X
EOR A, nn, S
EOR A, (nn, S), Y
4916 , imm
45 16, dd
55 16, dd
52 16, dd
41 16, dd
51 16, dd
47 16, dd
5716, dd
4D 16, ll, mm
5D 16, ll, mm
59 16, ll, mm
4F 16, ll, mm, hh
5F16, ll, mm, hh
43 16, nn
53 16, nn
2
2
2
2
2
2
2
2
3
3
3
4
4
2
2
2
4
5
6
7
8
10
11
4
6
6
6
7
5
8
(Note 1) This table applies when using the accumulator A. If using the accumulator B, replace “A” with “B”.
In this case, “42 16” is added at the beginning of the machine code, the bytes-count increases by
1 and the cycles-count increases by 2.
(Note 2) When operating on 16-bit data in the immediate addressing mode with the data length selection
flag m set to 0, the bytes-count increases by 1.
4–44
7700 FAMILY SOFTWARE MANUAL
EXTS
EXTS
Extension with Sign
Function
:
Extension with sign
Operation
:
AccH ← 0016 or FF16
This instruction can be used
in the 7750 Series only.
When bit 7 of AccL=“0”
AccH ← 00 16
Acc H
AccL
00000000 0XXXXXXX
←
Acc H
AccL
?
0XXXXXXX
Acc H
AccL
?
1XXXXXXX
When bit 7 of AccL=“1”
AccH ← FF 16
Acc H
AccL
11111111 1XXXXXXX
←
❊ The high-order byte of Acc changes regardless of the m flag
Description
:
This instruction is used to extend the signed 8-bit data stored in the low-order byte of the
accumulator to a 16-bit data.
If bit 7 of the accumulator is “0”, bits 8 to 15 are set to “0”. If bit 7 of the accumulator is “1”,
bits 8 to 15 are set to “1”.
With this instruction, the high-order byte of accumulator changes regardless of the data length
selection flag m, but the content of the data length selection flag m is unchanged.
Status flags
IPL :
Not affected.
N
:
Set to 1, if bit 15 of the result of operation is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1, if the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Accumulator
Accumulator
EXTS A
EXTS B
8916 , 8B16
4216 , 8B16
2
2
8
8
7700 FAMILY SOFTWARE MANUAL
4–45
EXTZ
EXTZ
Extension Zero
Function
:
Extension zero
Operation
:
Acc H ← 0016
AccH
This instruction can be used
in the 7750 Series only.
AccL
AccH
←
0016
Acc L
?
❊ The high-order byte of Acc changes regardless of the m flag
Description
:
This instruction is used to extend the 8-bit data stored in the low-order byte of the accumulator
to a 16-bit data.
Bits 8 to 15 of the accumulator are set to “0”.
With this instruction, the high-order byte of accumulator changes regardless of the data length
selection flag m, but the content of the data length selection flag m is unchanged.
Status flags
4–46
IPL :
Not affected.
N
:
Set to “0”
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1, if the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Accumulator
Accumulator
EXTZ A
EXTZ B
8916 , AB16
4216 , AB16
2
2
5
5
7700 FAMILY SOFTWARE MANUAL
INC
INC
Increment by One
Function
:
Increment
Operation
:
Acc ← Acc + 1 or M ← M + 1
When m=0
Acc
Acc
←
+ 1
or
M(n+1,n)
M(n+1,n)
←
+ 1
When m=1
AccL
AccL
←
+1
or
M(n)
M(n)
←
Description
:
+1
Adds 1 to the contents of the accumulator or memory.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Accumulator
Direct
Direct indexed X
Absolute
Absolute indexed X
INC
INC
INC
INC
INC
3A16
E616, dd
F616, dd
EE16, ll, mm
FE16, ll, mm
1
2
2
3
3
2
7
7
7
8
A
dd
dd, X
mmll
mmll, X
(Note 1) The accumulator addressing mode's specification in this table applies when using the accumulator
A. If using the accumulator B, replace “A” with “B”. In this case, “42 16” is added at the beginning
of the machine code, the bytes-count increases by 1 and the cycles-count increases by 2.
7700 FAMILY SOFTWARE MANUAL
4–47
INX
INX
Increment Index Register X by One
Function
:
Increment
Operation
:
X ←X + 1
When x=0
X
X
←
+ 1
When x=1
XL
XL
←
Description
:
+ 1
Adds 1 to the contents of the index register X.
Status flags
4–48
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
INX
E816
1
2
7700 FAMILY SOFTWARE MANUAL
INY
INY
Increment Index Register Y by One
Function
:
Increment
Operation
:
Y ←Y + 1
When x=0
Y
Y
←
+ 1
When x=1
YL
YL
←
Description
:
+ 1
Adds 1 to the contents of the index register Y.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
INY
C816
1
2
7700 FAMILY SOFTWARE MANUAL
4–49
JMP
JMP
Jump
Function
:
Jump always
Operation
:
[PG], PC ← specified address (absolute or indirect)
When the addressing mode is ...
absolute addressing mode,
PC ← ADDR
absolute long addressing mode,
PC ← ADDR
PG ← BANK
absolute indirect addressing mode,
PC ← M(ADDR+1, ADDR)
absolute indirect long addressing mode,
PC ← M(ADDR+1, ADDR)
PG ← M(ADDR+2)
absolute indexed X indirect addressing mode,
PC ← M(ADDR+X+1, ADDR+X)
❊ ADDR indicates the low-order 16 bits of a 24-bit address and is specified by bytes 2 and
3 of the instruction.
❊ BANK is the high-order 8 bits of a 24-bit address and is specified by byte 4 of the
instruction.
Description
:
The JMP instruction causes a jump to the address specified for the addressing mode in use.
When this instruction is used in addressing mode other than absolute long, the content of PG
is incremented by 1 and the branch destination becomes the next bank if the last byte of the
instruction is at the topmost address (XXFFFF16) of a bank or if the instruction spans across
banks.
Status flags
4–50
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Absolute
Absolute
Absolute
Absolute
Absolute
JMP mmll
JMPL hhmmll
JMP (mmll)
JMPL (mmll)
JMP (mmll, X)
4C 16, ll, mm
5C16, ll, mm, hh
6C 16, ll, mm
DC 16, ll, mm
7C16, ll, mm
3
4
3
3
3
2
4
4
8
6
long
indirect
indirect long
indexed X indirect
7700 FAMILY SOFTWARE MANUAL
JSR
JSR
Jump to Subroutine
Function
:
Jump to subroutine
Operation
:
Stack ← [PG], PC
[PG], PC ← specified address (absolute or indirect)
When the addressing mode is ...
absolute addressing mode,
Stack
← PC + 3
(S) in just after instruction execution
M(S,S–1) ← PC
(S) in just before instruction execution
PC
S
←S – 2
PC
← ADDR
absolute long addressing mode,
← PC + 4
PC
M(S
to
Stack
(S) in just after instruction execution
S–2) ← PG, PC
S
←S – 3
PC
← ADDR
PG
← BANK
(S) in just before instruction execution
absolute indexed X indirect addressing mode,
PC
← PC + 3
M(S,S–1) ← PC
PCL
PCH
PCL
PCH
PG
Stack
(S) in just after instruction execution
S
←S – 2
PC
← M(ADDR+X+1,ADDR+X)
(S) in just before instruction execution
PCL
PCH
❊ ADDR indicates the low-order 16 bits of a 24-bit address and is specified by bytes 2 and
3 of the instruction.
❊ BANK is the high-order 8 bits of a 24-bit address and is specified by byte 4 of the
instruction.
Description
:
The contents of the program counter PC (or the program bank register PG and the program
counter PC if absolute long addressing mode) are first saved on the stack, then a jump occurs
to the address shown for each addressing mode.
When this instruction is used in addressing mode other than absolute long, the content of PG
is incremented by 1 and the branch destination becomes the next bank if the last byte of the
instruction is at the topmost address (XXFFFF16) of a bank or if the instruction spans across
banks.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Absolute
Absolute long
Absolute indexed X indirect
JSR mmll
JSRL hhmmll
JSR (mmll, X)
2016, ll, mm
2216, ll, mm, hh
FC16, ll, mm
3
4
3
6
8
8
7700 FAMILY SOFTWARE MANUAL
4–51
LDA
LDA
Load Accumulator from Memory
Function
:
Load
Operation
:
Acc ← M
When m=0
Acc
M(n+1, n)
←
When m=1
Acc L
M(n)
←
Description
:
Loads the contents of memory into the accumulator.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
LDA A, #imm
Direct
Direct
Direct
Direct
Direct
Direct
Direct
LDA A, dd
LDA A, dd, X
LDA A, (dd)
LDA A, (dd, X)
LDA A, (dd), Y
LDAL A, (dd)
LDAL A, (dd), Y
A916 , imm
A516, dd
B516, dd
B216, dd
A116, dd
B116, dd
A716, dd
B716, dd
AD 16, ll, mm
BD 16, ll, mm
B9 16, ll, mm
AF 16, ll, mm, hh
BF16, ll, mm, hh
A316, nn
B316, nn
2
2
2
2
2
2
2
2
3
3
3
4
4
2
2
2
4
5
6
7
8
10
11
4
6
6
6
7
5
8
indexed X
indirect
indexed X indirect
indirect indexed Y
indirect long
indirect long indexed Y
Absolute
LDA A, mmll
Absolute indexed X
LDA A, mmll, X
Absolute indexed Y
LDA A, mmll, Y
Absolute long
LDA A, hhmmll
Absolute long indexed X
LDA A, hhmmll, X
Stack pointer relative
LDA A, nn, S
Stack pointer relative
LDA A, (nn, S), Y
indirect indexed Y
(Note 1) This table applies when using the accumulator A. If using the accumulator B, replace “A” with “B”.
In this case, “4216 ” is added at the beginning of the machine code, the bytes-count increases by
1 and the cycles-count increases by 2.
(Note 2) When operating on 16-bit data in the immediate addressing mode with the data length selection
flag m set to 0, the bytes-count increases by 1.
4–52
7700 FAMILY SOFTWARE MANUAL
LDM
LDM
Load Immediate to Memory
Function
:
Load
Operation
:
M ← IMM
When m=0
M(n+1, n)
← IMM16
When m=1
M(n)
← IMM8
Description
:
Loads an immediate value into memory.
Status flags
:
Not affected.
Addressing mode
Syntax
Direct
Direct indexed X
Absolute
Absolute indexed X
LDM
LDM
LDM
LDM
#imm,
#imm,
#imm,
#imm,
dd
dd, X
mmll
mmll, X
Machine code
Bytes
Cycles
6416, dd, imm
7416, dd, imm
9C16, ll, mm, imm
9E16, ll, mm, imm
3
3
4
4
4
5
5
6
(Note 1) When operating on 16-bit data with the data length selection flag m set to 0, the bytes-count
increases by 1.
7700 FAMILY SOFTWARE MANUAL
4–53
LDT
LDT
Load Immediate to Data Bank Register
Function
:
Load
Operation
:
DT ← IMM8
DT
← IMM8
Description
:
Loads an immediate value into the data bank register DT.
Status flags
:
Not affected.
4–54
Addressing mode
Syntax
Machine code
Bytes Cycles
Immediate
LDT #imm
8916, C216, imm
3
7700 FAMILY SOFTWARE MANUAL
5
LDX
LDX
Load Index Register X from Memory
Function
:
Load
Operation
:
X ←M
When x=0
X
M(n+1, n)
←
When x=1
XL
M(n)
←
Description
:
Loads the contents of memory into the index register X.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
Direct
Direct indexed Y
Absolute
Absolute indexed Y
LDX
LDX
LDX
LDX
LDX
A216 , imm
A616, dd
B616, dd
AE16, ll, mm
BE16, ll, mm
2
2
2
3
3
2
4
5
4
6
#imm
dd
dd, Y
mmll
mmll, Y
(Note 1) When operating on 16-bit data in the immediate addressing mode with the index register length
selection flag x set to 0, the bytes-count increases by 1.
7700 FAMILY SOFTWARE MANUAL
4–55
LDY
LDY
Load Index Register Y from Memory
Function
:
Load
Operation
:
Y ←M
When x=0
Y
M(n+1, n)
←
When x=1
YL
M(n)
←
Description
:
Loads the contents of memory into the index register Y.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes Cycles
Immediate
Direct
Direct indexed X
Absolute
Absolute indexed X
LDY
LDY
LDY
LDY
LDY
A016 , imm
A416, dd
B416, dd
AC 16, ll, mm
BC 16, ll, mm
2
2
2
3
3
#imm
dd
dd, X
mmll
mmll, X
2
4
5
4
6
(Note 1) When operating on 16-bit data in the immediate addressing mode with the index register length
selection flag x set to 0, the bytes-count increases by 1.
4–56
7700 FAMILY SOFTWARE MANUAL
LSR
LSR
Logical Shift Right
Function
:
Logical shift right
Operation
:
Acc or M
0 → 1 bit shift to Right
C
→
When m=0
b15
Acc or M(n+1,n)
0→ → → → →
b0
C
→ → → → →
When m=1
b7
AccL or M(n)
b0
C
0→ → → → → → → → →
Description
:
Shifts all bits of the accumulator or memory one place to the right. Bit 15 (or bit 7 if the data
length selection flag m is set to 1) of the accumulator or memory is loaded with 0.
The carry flag C is loaded from bit 0 of the data before the shift.
Status flags
IPL :
Not affected.
N
:
Cleared to “0”.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Set to 1 when bit 0 before the operation is 1. Otherwise, cleared to 0.
Addressing mode
Syntax
Machine code
Bytes Cycles
Accumulator
Direct
Direct indexed X
LSR A
LSR dd
LSR dd, X
Absolute
Absolute indexed X
LSR mmll
LSR mmll, X
4A16
4616, dd
5616, dd
4E16, ll, mm
5E16, ll, mm
1
2
2
3
3
2
7
7
7
8
(Note 1) The accumulator addressing mode's specification in this table applies when using the accumulator
A. If using the accumulator B, replace “A” with “B”. In this case, “4216” is added at the beginning
of the machine code, the bytes-count increases by 1 and the cycles-count increases by 2.
7700 FAMILY SOFTWARE MANUAL
4–57
MPY
MPY
Multiply
Function
:
Multiplication (Unsigned)
Operation
:
B, A ← A × M
When m=0
B
A
Product
A
M(n+1,n)
← Multiplicand ×
Multiplier
When m=1
BL
AL
Product
Description
:
AL
M(n)
← Multiplicand × Multiplier
When the data length selection flag m is set to 0, the contents of the accumulator A and the
contents of memory are multiplied. Multiplication is performed as 16-bit × 16-bit, and the result
is a 32-bit data which is placed in the accumulators B (upper 16 bits of the result) and A (lower
16 bits of the result).
When the data length selection flag m is set to 1, the lower 8-bit contents of the accumulator
A and the contents of memory are multiplied. Multiplication is performed as 8-bit × 8-bit, and
the result is a 16-bit data which is placed in the lower 8 bits of the accumulators B (upper 8
bits of the result) and A (lower 8 bits of the result).
Status flags
4–58
IPL :
Not affected.
N
:
Set to 1 when bit 31 (or bit 15 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Cleared to 0.
7700 FAMILY SOFTWARE MANUAL
MPY
MPY
Multiply
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
Direct
Direct indexed X
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Absolute
Absolute indexed X
Absolute indexed Y
Absolute long
Absolute long indexed X
Stack pointer relative
Stack pointer relative
indirect indexed Y
MPY #imm
MPY dd
MPY dd, X
MPY (dd)
MPY (dd, X)
MPY (dd), Y
MPYL (dd)
MPYL (dd), Y
MPY mmll
MPY mmll, X
MPY mmll, Y
MPY hhmmll
MPY hhmmll, X
MPY nn, S
MPY (nn, S), Y
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
3
3
3
3
3
3
3
3
4
4
4
5
5
3
3
16
18
19
20
21
22
24
25
18
20
20
20
21
19
22
0916, imm
0516, dd
1516, dd
1216, dd
0116, dd
1116, dd
0716, dd
1716, dd
0D16, ll, mm
1D16, ll, mm
1916, ll, mm
0F16, ll, mm, hh
1F16, ll, mm, hh
0316, nn
1316, nn
(Note 1) When operating on 16-bit data in the immediate addressing mode with the data length selection flag
m set to 0, the bytes-count increases by 1.
(Note 2) The cycles-count in this table are for 8-bit × 8-bit multiplications. For 16-bit × 16-bit multiplications,
the cycles-count increases by 8.
7700 FAMILY SOFTWARE MANUAL
4–59
MPYS
MPYS
Multiply with Sign
Function
:
Multiplication (Signed)
Operation
:
B, A ← A × M
This instruction can be used
in the 7750 Series only.
When m=0
B
A
← Multiplicand ×
Product
s
A
s
M(n+1,n)
s
Multiplier
When m=1
BL
s
AL
Product
AL
M(n)
← Multiplicand × Multiplier
s
s
❊ s indicates the sign bit and is the topmost bit of the data to be operated on.
Description
:
When the data length selection flag m is set to 0, the content of the accumulator A is multiplied
by the content of memory as signed data. The multiplication is performed as a 16-bit × 16bit operation, and the result is a 32-bit data which is placed in the accumulators B (upper 16
bits of the result) and A (lower 16 bits of the result). Bit 15 of accumulator B becomes the
sign bit.
When the data length selection flag m is set to 1, the lower 8-bit content of the accumulator
A is multiplied by the content of memory as signed data. The multiplication is performed as
8-bit × 8-bit operation, and the result is a 16-bit data which is placed in the lower 8 bits of the
accumulators B (upper 8 bits of the result) and A (lower 8 bits of the result). Bit 7 of
accumulator B becomes the sign bit.
Status flags
4–60
IPL :
Not affected.
N
:
Set to 1 when bit 31 of the operation result which is bit 15 of accumulator B (or if the data
length selection flag m is set to 1, bit 15 of the operation result which is bit 7 of accumulator
B) is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
7700 FAMILY SOFTWARE MANUAL
MPYS
MPYS
Multiply with Sign
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
Direct
Direct indexed X
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Absolute
Absolute indexed X
Absolute indexed Y
Absolute long
Absolute long indexed X
Stack pointer relative
Stack pointer relative
indirect indexed Y
MPYS #imm
MPYS dd
MPYS dd, X
MPYS (dd)
MPYS (dd, X)
MPYS (dd), Y
MPYSL (dd)
MPYSL (dd), Y
MPYS mmll
MPYS mmll, X
MPYS mmll, Y
MPYS hhmmll
MPYS hhmmll, X
MPYS nn, S
MPYS (nn, S), Y
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
8916,
3
3
3
3
3
3
3
3
4
4
4
5
5
3
3
18
20
21
22
23
24
26
27
20
22
22
22
23
21
24
8916, imm
8516, dd
9516, dd
9216, dd
8116, dd
9116, dd
8716, dd
9716, dd
8D16, ll, mm
9D16, ll, mm
9916, ll, mm
8F16, ll, mm, hh
9F16, ll, mm, hh
8316, nn
9316, nn
(Note 1) When operating on 16-bit data in the immediate addressing mode with the data length selection flag
m set to 0, the bytes-count increases by 1.
(Note 2) The cycles-count in this table are for 8-bit × 8-bit multiplications with the same sign. If the multiplier
and multiplicand have different signs, three additional cycles are required. For 16-bit × 16-bit
multiplications, the cycles-count increases by 8.
7700 FAMILY SOFTWARE MANUAL
4–61
MVN
MVN
Move Negative
Function
:
Move
Operation
:
M(n
to
n + k) ← M(m
to
m + k)
n
Transfer
↓ Transfer direction destination
n+k
area
A = 0 ?
When A=0
Instruction execution complete
When A≠0
m
Transfer
↓ Transfer direction source
m+k
area
Repeat operation
M(DTd: Y) M(DTs: X)
X ←X + 2
Y ←Y + 2
A ←A – 2
❊ DTd indicates the transfer destination bank and is specified with the second byte of the
instruction.
❊ DTs indicates the transfer source bank and is specified with the third byte of the
instruction.
❊ Values set in register before transfer
A: Transfer byte count
When m=0
The value 0 to 65535 can be set
When m=1
The value 0 to 255 can be set
X: Transfer source area beginning (lowermost) address
When x=0
The value 0 to 65535 can be set
When x=1
The value 0 to 255 can be set (Note 1)
Y: Transfer destination area beginning (lowermost) address
When x=0
The value 0 to 65535 can be set
When x=1
The value 0 to 255 can be set (Note 1)
❊ Content of register after transfer
A: FFFF16
X: Transfer source area end (highermost) address + 1
Y: Transfer destination area beginning (highermost) address + 1
DT:Bank number of transfer destination
❊ Transfer is always performed two bytes at a time. Therefore, in the case of a 16-bit
bus, the transfer time is shorter when transfer start addresses are even compared to
when they are both odd addresses.
Note 1. This instruction is recommended to use at the x=“0”. Data in the area between
XX00 16 and XXFF 16 can be only used because the higher bytes of index
registers X and Y are not affected at x=“1”.
4–62
7700 FAMILY SOFTWARE MANUAL
MVN
MVN
Move Negative
Description
:
Normally, a block of data is transferred from upper addresses to lower addresses. The
transfer is performed in the ascending address order of the block being transferred. The target
bank is specified by the instruction’s second byte, and the address within the target bank is
specified by the contents of the index register Y. The source bank is specified by the
instruction’s third byte, and the address within the source bank is specified by the contents of
the index register X. The accumulator A is loaded with the bytes-count of the data to be
transferred. As each byte of data is transferred, the index registers X and Y are incremented
by 1, so that the index register X will become a value equal to 1 larger than the source address
of the last byte transferred and the index register Y will become a value equal to 1 larger than
the target address of the last byte received. The data bank register DT will become the target
bank number, and the accumulator A will become FFFF16.
Status flags
: Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Block transfer
MVN n 1, n 2
5416 , n1, n 2
3
7+(i/2)×7
(Note 1)The cycles-count shown above is for when the number of bytes transferred, i, is an even
number. If i is an odd number, the cycles-count is obtained as follows:
7 + (i ÷ 2) × 7 + 4.
Note that (i ÷ 2) denotes the integer part of the result of dividing i by 2.
7700 FAMILY SOFTWARE MANUAL
4–63
MVP
MVP
Move Positive
Function
:
Move
Operation
:
M(n – k
to
n) ← M(m – k
to
m)
m–k
Transfer
↑ Transfer direction source
m
area
A = 0 ?
When A=0
Instruction execution complete
When A≠0
n–k
Transfer
↑ Transfer direction destination
n
area
Repeat operation
X ←X – 1
Y ←Y – 1
M(DTd: Y) M(DTs: X)
X ←X – 1
Y ←Y – 1
A ←A – 2
❊ DTd indicates the transfer destination bank and is specified with the second byte of the
instruction.
❊ DTs indicates the transfer source bank and is specified with the third byte of the
instruction.
❊ Values set in register before transfer
A: Transfer byte count
When m=0
The value 0 to 65535 can be set
When m=1
The value 0 to 255 can be set
X: Transfer source area beginning (highermost) address
When x=0
The value 0 to 65535 can be set
When x=1
The value 0 to 255 can be set
Y: Transfer destination area beginning (highermost) address
When x=0
The value 0 to 65535 can be set
When x=1
The value 0 to 255 can be set
❊ Content of register after transfer
A: FFFF16
X: Transfer source area end (lowermost) address – 1
Y: Transfer destination area beginning (lowermost) address – 1
DT:Bank number of transfer destination
❊ Transfer is always performed two bytes at a time. Therefore, in the case of a 16-bit
bus, the transfer time is shorter when transfer start addresses are odd compared to
when they are both even addresses.
Note 1. This instruction is recommended to use at the x=“0”. Data in the area between
XX00 16 and XXFF 16 can be only used because the higher bytes of index
registers X and Y are not affected at x=“1”.
4–64
7700 FAMILY SOFTWARE MANUAL
MVP
MVP
Move Positive
Description
:
Normally, a block of data is transferred from lower addresses to upper addresses. The
transfer is performed in the descending address order of the block being transferred. The
target bank is specified by the instruction’s second byte, and the address within the
target bank is specified by the contents of the index register Y. The source bank is
specified by the instruction’s third byte, and the address within the source bank is
specified by the contents of the index register X. The accumulator A is loaded with the
bytes-count of the data to be transferred. As each byte of data is transferred, the index
registers X and Y are decremented by 1, so that the index register X will become a value
equal to 1 less than the source address of the last byte transferred and the index
register Y will become a value equal to 1 smaller than the target address of the last byte
received. The data bank register DT will become the target bank number, and the
accumulator A will become FFFF 16.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Block transfer
MVP n 1, n 2
4416, n 1, n 2
3
9+(i/2)×7
(Note 1)The cycles-count shown above is for when the number of bytes transferred, i, is an even
number. If i is an odd number, the cycles-count is obtained as follows:
9 + (i ÷ 2) × 7 + 5.
Note that (i ÷ 2) denotes the integer part of the result of dividing i by 2.
7700 FAMILY SOFTWARE MANUAL
4–65
NOP
NOP
No Operation
Function
:
No operation
Operation
:
PC ← PC + 1
❊ PG also changes depending on the result of the above operation on PC.
If a carry occurs in PC: PG ← PG + 1
Description
:
This instruction only causes the program counter to be incremented by 1 and nothing else.
Status flags
:
Not affected.
4–66
Addressing mode
Syntax
Machine code
Bytes
Implied
NOP
EA16
1
7700 FAMILY SOFTWARE MANUAL
Cycles
2
ORA
ORA
OR Memory with Accumulator
Function
:
Logical OR
Operation
:
Acc ← Acc V M
When m=0
Acc
A
←
M(n+1,n)
V
When m=1
Acc L
AccL
←
Description
:
M(n)
V
Performs the logical OR between the contents of the accumulator and the contents of memory,
and places the result in the accumulator.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Immediate
ORA A, #imm
Direct
Direct
Direct
Direct
Direct
ORA
ORA
ORA
ORA
ORA
indexed X
indirect
indexed X indirect
indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Absolute
Absolute indexed X
Absolute indexed Y
Absolute long
Absolute long indexed X
Stack pointer relative
Stack pointer relative
indirect indexed Y
A,
A,
A,
A,
A,
dd
dd, X
(dd)
(dd, X)
(dd), Y
ORAL A, (dd)
ORAL A, (dd), Y
ORA A, mmll
ORA A, mmll, X
ORA A, mmll, Y
ORA A, hhmmll
ORA A, hhmmll, X
ORA A, nn, S
ORA A, (nn, S), Y
Machine code
Bytes
Cycles
0916 , imm
0516, dd
1516, dd
1216, dd
0116, dd
1116, dd
0716, dd
1716, dd
0D16, ll, mm
1D16, ll, mm
1916, ll, mm
0F16, ll, mm, hh
1F16, ll, mm, hh
0316, nn
1316, nn
2
2
2
2
2
2
2
2
3
3
3
4
4
2
2
2
4
5
6
7
8
10
11
4
6
6
6
7
5
8
(Note 1) This table applies when using the accumulator A. If using the accumulator B, replace “A” with “B”.
In this case, “42 16” is added at the beginning of the machine code, the bytes-count increases by
1 and the cycles-count increases by 2.
(Note 2) When operating on 16-bit data in the immediate addressing mode with the data length selection flag
m set to 0, the bytes-count increases by 1.
7700 FAMILY SOFTWARE MANUAL
4–67
PEA
PEA
Push Effective Address
Function
:
Stack manipulation (push)
Operation
:
Stack ← IMM16
Stack
(S) in just after instruction execution
M(S,S – 1) ← IMM16
S← S – 2
(S) in just before instruction execution
IMML
IMMH
❊ IMM16 is an immediate value and IMM H indicates its high-order byte and IMML indicates
its low-order byte.
Description
:
Status flags
:
4–68
The instruction’s third and second bytes are saved on the stack in this order.
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PEA #imm Himm L
F4 16, immL, imm H
3
5
7700 FAMILY SOFTWARE MANUAL
PEI
PEI
Push Effective Indirect Address
Function
:
Stack manipulation (push)
Operation
:
Stack ← M(DPR + IMM8 + 1, DPR + IMM8)
M(S,S – 1) ← M(DPR + IMM8 + 1, DPR + IMM8)
S← S – 2
Stack
(S) in just after instruction execution
M(DPR+IMM8)
(S) in just before instruction execution M(DPR+IMM8+1)
❊ IMM8 is an 8-bit immediate value and is used as an offset from DPR.
Description
:
Saves the contents of the consecutive 2 bytes in the direct page as specified by the sum of
the contents of the direct page register DPR and the instruction’s second byte on the stack
in the order of upper address first and lower address second.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PEI #imm
D416 , imm
2
6
7700 FAMILY SOFTWARE MANUAL
4–69
PER
PER
Push Effective Program Counter Relative Address
Function
:
Stack manipulation (push)
Operation
:
Stack ← PC + IMM16
EAR ← PC + IMM16
Stack
(S) in just after instruction execution
EARL
EARH
(S) in just before instruction execution
M(S, S – 1) ← EAR
S← S – 2
❊ IMM16 is a 16-bit immediate value
❊ EAR is an execution address added PC and IMM16, and EARH indicates its high-order byte
and EARL indicates its low-order byte.
Description
:
Saves the result of adding a 16-bit data consisting of an upper byte specified by the
instruction’s third byte and a lower byte specified by the instruction’s second byte with the
contents of the program counter on the stack in the order of the result’s upper byte first and
lower byte second.
Status flags
:
Not affected.
4–70
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PER #imm Himm L
62 16, imm L, imm H
3
5
7700 FAMILY SOFTWARE MANUAL
PHA
PHA
Push Accumulator A on Stack
Function
:
Stack manipulation (push)
Operation
:
Stack ← A
When m=0
M(S, S – 1) ← A
S← S – 2
Stack
(S) in just after instruction execution
AL
AH
(S) in just before instruction execution
When m=1
M(S) ← AL
Stack
S← S – 1
(S) in just after instruction execution
(S) in just before instruction execution
AL
Description
:
Saves the contents of the accumulator A to the address specified by the stack pointer S. When
the data length selection flag m is set to 0, the accumulator A’s upper byte is saved on the
stack first and then the lower byte. When the data length selection flag m is set to 1, only
the accumulator A’s lower byte is saved on the stack.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PHA
4816
1
4
7700 FAMILY SOFTWARE MANUAL
4–71
PHB
PHB
Push Accumulator B on Stack
Function
:
Stack manipulation (push)
Operation
:
Stack ← B
When m=0
Stack
M(S, S – 1) ← B
S← S – 2
(S) in just after instruction execution
BL
BH
(S) in just before instruction execution
When m=1
Stack
M(S) ← BL
(S) in just after instruction execution
(S) in just before instruction execution
S← S – 1
BL
Description
:
Saves the contents of the accumulator B to the address indicated by the stack pointer S.
When the data length selection flag m is set to 0, the accumulator B’s upper byte is saved on
the stack first and then the lower byte. When the data length selection flag m is set to 1, only
the accumulator B’s lower byte is saved on the stack.
Status flags
:
Not affected.
4–72
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PHB
4216 , 4816
2
6
7700 FAMILY SOFTWARE MANUAL
PHD
PHD
Push Direct Page Register on Stack
Function
:
Stack manipulation (push)
Operation
:
Stack ← DPR
Stack
M(S, S – 1) ← DPR
S← S – 2
(S) in just after instruction execution
DPRL
DPRH
(S) in just before instruction execution
Description
:
Saves the contents of the direct page register DPR to the address indicated by the stack
pointer S in the order of upper byte first and then lower byte.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PHD
0B16
1
4
7700 FAMILY SOFTWARE MANUAL
4–73
PHG
PHG
Push Program Bank Register on Stack
Function
:
Stack manipulation (push)
Operation
:
Stack ← PG
Stack
(S) in just after instruction execution
(S) in just before instruction execution
M(S) ← PG
S← S – 1
PG
Description
:
Saves the contents of the program bank register to the address indicated by the stack pointer
S.
Status flags
:
Not affected.
4–74
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PHG
4B16
1
3
7700 FAMILY SOFTWARE MANUAL
PHP
PHP
Push Processor Status on Stack
Function
:
Stack manipulation (push)
Operation
:
Stack ← PS
Stack
M(S, S – 1) ← PS
S← S – 2
(S) in just after instruction execution
PSL
PSH
(S) in just before instruction execution
Description
:
Saves the contents of the processor status register PS to the address indicated by the stack
pointer S in the order of upper byte and then lower byte.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PHP
0816
1
4
7700 FAMILY SOFTWARE MANUAL
4–75
PHT
PHT
Push Data Bank Register on Stack
Function
:
Stack management (push)
Operation
:
Stack ← DT
Stack
(S) in just after instruction execution
(S) in just before instruction execution
M(S) ← DT
S← S – 1
DT
Description
:
Saves the contents of the data bank register DT to the address indicated by the stack pointer
S.
Status flags
:
Not affected.
4–76
Addressing mode
Syntax
Machine code
Bytes Cycles
Stack
PHT
8B16
1
7700 FAMILY SOFTWARE MANUAL
3
PHX
PHX
Push Index Register X on Stack
Function
:
Stack management (push)
Operation
:
Stack ← X
When x=0
Stack
M(S, S – 1) ← X
S← S – 2
(S) in just after instruction execution
XL
XH
(S) in just before instruction execution
When x=1
Stack
M(S) ← XL
(S) in just after instruction execution
(S) in just before instruction execution
S← S – 1
XL
Description
:
Saves the contents of the index register X to the address indicated by the stack pointer S.
When the index register length selection flag x is set to 0, the contents are saved in the order
of upper byte and then lower byte. When the index register length selection flag x is set to
1, only the lower byte is saved on the stack.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PHX
DA16
1
4
7700 FAMILY SOFTWARE MANUAL
4–77
PHY
PHY
Push Index Register Y on Stack
Function
:
Stack management (push)
Operation
:
Stack ← Y
When x=0
M(S, S – 1) ← Y
Stack
(S) in just after instruction execution
S← S – 2
YL
YH
(S) in just before instruction execution
When x=1
M(S) ← YL
Stack
(S) in just after instruction execution
(S) in just before instruction execution
S← S – 1
YL
Description
:
Saves the contents of the index register Y to the address indicated by the stack pointer S.
When the index register length selection flag x is set to 0, the contents are saved in the order
of upper byte and then lower byte. When the index register length selection flag x is set to
1, only the lower byte is saved on the stack.
Status flags
:
Not affected.
4–78
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PHY
5A16
1
4
7700 FAMILY SOFTWARE MANUAL
PLA
PLA
Pull Accumulator A from Stack
Function
:
Stack manipulation (pull)
Operation
:
A ← Stack
When m=0
AH
A ← M(S+2, S+1)
S← S + 2
AL
Stack
(S) in just before instruction execution
(S) in just after instruction execution
When m=1
AL
AL ← M(S+1)
Stack
S← S + 1
Description
:
(S) in just before instruction execution
(S) in just after instruction execution
The stack pointer S is incremented, and then restores the lower byte of the accumulator A
with the data at the address indicated by the stack pointer S. Again, increments the stack
pointer S and then restores the upper byte of the accumulator A with the data at the address
indicated by the stack pointer S. When the data length selection flag m is set to 0, 2 bytes
data are restored. When the data length selection flag m is set to 1, only 1 byte data is
restored (to the lower byte of the accumulator A).
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PLA
6816
1
5
7700 FAMILY SOFTWARE MANUAL
4–79
PLB
PLB
Pull Accumulator B from Stack
Function
:
Stack manipulation (pull)
Operation
:
B ← Stack
When m=0
BH
B ← M(S+2, S+1)
BL
Stack
(S) in just before instruction execution
S← S + 2
(S) in just after instruction execution
When m=1
BL
B L ← M(S+1)
Stack
(S) in just before instruction execution
(S) in just after instruction execution
S← S + 1
Description
:
The stack pointer S is incremented, and then restores the lower byte of the accumulator B with
the data at the address indicated by the stack pointer S. Again, increments the stack pointer
S and then restores the upper byte of the accumulator B with the data at the address indicated
by the stack pointer S. When the data length selection flag m is set to 0, 2 bytes data are
restored. When the data length selection flag m is set to 1, only 1 byte data is restored (to
the lower byte of the accumulator B).
Status flags
IPL :
Not affected.
N
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of
:
the operation result is 1. Otherwise, cleared to 0.
V
4–80
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PLB
4216 , 6816
2
7
7700 FAMILY SOFTWARE MANUAL
PLD
PLD
Pull Direct Page Register from Stack
Function
:
Stack manipulation (pull)
Operation
:
DPR ← Stack
DPR
DPR ← M(S+2, S+1)
(S) in just before instruction execution
S← S + 2
Stack
(S) in just after instruction execution
Description
:
The stack pointer S is incremented, and then the direct page register DPR is restored with the
data at the address indicated by the stack pointer .
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PLD
2B16
1
5
7700 FAMILY SOFTWARE MANUAL
4–81
PLP
PLP
Pull Processor Status from Stack
Function
:
Stack manipulation (pull)
Operation
:
PS ← Stack
PSH
PS ← M(S+2, S+1)
(S) in just before instruction execution
S ←S + 2
PSL
Stack
(S) in just after instruction execution
Description
:
The stack pointer S is incremented and then the processor status register PS is restored with
the data at the address indicated by the stack pointer S.
Status flags
:
Changes to the values restored from the stack.
4–82
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PLP
2816
1
6
7700 FAMILY SOFTWARE MANUAL
PLT
PLT
Pull DaTa Bank Register from Stack
Function
:
Stack manipulation (pull)
Operation
:
DT ← Stack
DT
Stack
DT ← M(S+1)
(S) in just before instruction execution
(S) in just after instruction execution
S← S + 1
Description
:
The stack pointer S is incremented, and then the data bank register DT is restored with the
data at the address indicated by the stack pointer S.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 7 of the operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PLT
AB16
1
6
7700 FAMILY SOFTWARE MANUAL
4–83
PLX
PLX
Pull Index Register X from Stack
Function
:
Stack manipulation (pull)
Operation
:
X ← Stack
When x=0
X ← M(S+2, S+1)
S← S + 2
XH
XL
Stack
(S) in just before instruction execution
(S) in just after instruction execution
When x=1
X L ← M(S+1)
XL
S← S + 1
Stack
(S) in just before instruction execution
(S) in just after instruction execution
Description
:
The stack pointer S is incremented, and then restores the lower byte of the index register X
with the data at the address indicated by the stack pointer S. Again, increments the stack
pointer S and then restores the upper byte of the index register X with the data at the address
indicated by the stack pointer S. When the index register length selection flag x is set to 0,
2 bytes are restored. When the index register length selection flag x is set to 1, only 1 byte
is restored (to the lower byte of the index register X).
Status flags
4–84
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PLX
FA16
1
5
7700 FAMILY SOFTWARE MANUAL
PLY
PLY
Pull Index Register Y from Stack
Function
:
Stack manipulation (pull)
Operation
:
Y ← Stack
When x=0
Y ← M(S+2, S+1)
YH
S← S + 2
YL
Stack
(S) in just before instruction execution
(S) in just after instruction execution
When x=1
YL ← M(S+1)
YL
S← S + 1
Stack
(S) in just before instruction execution
(S) in just after instruction execution
Description
:
The stack pointer S is incremented, and then restores the lower byte of the index register Y
with the data at the address indicated by the stack pointer S. Again, increments the stack
pointer S and then restores the upper byte of the index register Y with the data at the address
indicated by the stack pointer S. When the index register length selection flag x is set to 0,
2 bytes are restored. When the index register length selection flag x is set to 1, only 1 byte
is restored (to the lower byte of the index register Y).
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PLY
7A16
1
5
7700 FAMILY SOFTWARE MANUAL
4–85
PSH
PSH
Push
Function
:
Stack manipulation (push)
Operation
:
Stack ← Specified register of A, B, X, Y, DPR, DT, PG, PS
to S – n) ← A,
order to save ➀
S← S – n – 1
M(S
B,
X,
Y, DPR, DT, PG, PS
➁
➂
➃
➄
➅
➆
➇
❊ The immediate value in the second byte of the instruction is used to specify the registers
to be saved.
❊ Among the registers being saved, the following registers are affected by the flags just before
the instruction is executed.
● A, B registers
When m=0 : The high-order and low-order bytes of the register are saved.
When m=1 : The low-order bytes of the register are saved.
● X, Y registers
When x=0 : The high-order and low-order bytes of the register is saved.
When x=1 : The low-order byte of the register is saved.
❊ n indicates the number of data bytes to be saved.
Description
:
This instruction’s second byte specifies the registers to be saved. The registers corresponding
to the bits in the second byte that are 1 are saved on the stack. The bit and register
correspondence is as shown below:
b7
PS
PG
DT
DPR
Y
X
B
b0
A
← Direction to save on the stack
When saving the registers to stack, registers A and B are affected by the m flag and registers
X and Y are affected by the x flag.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PSH #nn
EB 16, nn
2
12+2xi1+i2
(Note 1) To the cycles-count shown above, the values shown below are added depending on the registers being
saved. The count is 12 cycles when no registers are saved. i 1 in above table represents the number
of registers (chosen from A, B, X, Y, DPR and PS) to be saved, and i2 represents the number of registers
(chosen from DT and PG) to be saved.
Register type
Cycles-count
4–86
PS
2
PG
1
DT
1
DPR
2
Y
2
X
2
7700 FAMILY SOFTWARE MANUAL
B
2
A
2
PSH
PSH
Push
PSH
NO
IMM8(0) = 1 ?
m=0?
NO
M(S,S-1) ← A
S ← S-2
NO
M(S) ← AL
S ← S-1
IMM8(5) = 1 ?
M(S) ← DT
S ← S-1
M(S) ← BL
S ← S-1
NO
IMM8(6) = 1 ?
M(S) ← PG
S ← S-1
IMM8(2) = 1 ?
x=0?
NO
NO
M(S,S-1) ← X
S ← S-2
NO
S ← S-2
NO
M(S,S-1) ← B
S ← S-2
IMM8(4) = 1 ?
M(S,S-1) ← DPR
NO
IMM8(1) = 1 ?
m=0?
NO
NO
M(S) ← XL
S ← S-1
IMM8(7) = 1 ?
M(S,S-1) ← PS
S ← S-2
IMM8(3) = 1 ?
x=0?
M(S,S-1) ← Y
S ← S-2
❊ IMM8 is an immediate value in 1-byte and
inside of () specifies the contents of the bit
at the value.
NO
M(S) ← YL
S ← S-1
7700 FAMILY SOFTWARE MANUAL
4–87
PUL
PUL
Pull
Function
:
Stack manipulation (pull)
Operation
:
Specified register of A, B, X, Y, DPR, DT, PG, PS ← Stack
A,
B,
X,
➀
➁
➂
S← S + n
Y, DPR, DT, PG, PS ← M(S + 1
➄ ➅ ➆ ➇ order to restore
to
S + n)
➃
❊ The immediate value in the second byte of the instruction is used to specify the registers
to be restored.
❊ Among the registers being restored, the following registers are affected by the flags in the
restored PS or the flags just before the instruction is executed.
● A, B registers
When m=0 : The high-order and low-order bytes of the register are restored.
When m=1 : The low-order bytes of the register are restored.
● X, Y registers
When x=0 : The high-order and low-order bytes of the register is restored.
When x=1 : The low-order byte of the register is restored.
❊ n indicates the number of data bytes to be restored.
Description
:
This instruction’s second byte specifies the registers to be restored. The registers corresponding to the bits in the second byte that are 1 are restored from the stack. The bit and register
correspondence is as shown below:
b7
PS
DT
DPR
Y
Direction to restore from the stack →
X
B
b0
A
When restoring from stack, registers A and B are affected by the m flag in restored PS, and
registers X and Y are affected by the x flag in restored PS. If PS is not restored, the registers
are affected by the value of these flags just before instruction execution.
Status flags
:
When bit 7 of the instruction’s second byte is 1, specifying that the program status register PS
is to be restored, the status flags are restored to the values that had been restored from the
stack. Otherwise, the status flags are not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Stack
PUL #nn
FB16, nn
2
14+3xi1+4xi2
(Note 1) To the cycles-count shown above, the values shown below are added depending on the registers
being restored. The count is 14 cycles when no registers are restored. i1 in above table represents
the number of registers (chosen from A, B, X, Y, PS and DT) to be saved. i2=1 if DPR is to be
restored, and i2=0 if DPR is not to be restored.
Register type
Cycles-count
4–88
PS
3
DT
3
DPR
4
Y
3
X
3
7700 FAMILY SOFTWARE MANUAL
B
3
A
3
PUL
PUL
Pull
PUL
NO
IMM8(7) = 1 ?
PS ← M(S+2,S+1)
NO
S ← S+2
NO
x=0?
NO
IMM8(5) = 1 ?
X ← M(S+2,S+1)
DT ← M(S+1)
S ← S+1
NO
IMM8(2) = 1 ?
XL ← M(S+1)
S ← S+1
S ← S+2
NO
IMM8(4) = 1 ?
IMM8(1) = 1 ?
DPR ← M(S+2,S+1)
S ← S+2
m=0?
NO
B ← M(S+2,S+1)
NO
BL ← M(S+1)
S ← S+1
S ← S+2
IMM8(3) = 1 ?
x=0?
Y ← M(S+2,S+1)
S ← S+2
NO
NO
IMM8(0) = 1 ?
YL ← M(S+1)
S ← S+1
m=0?
A ← M(S+2,S+1)
S ← S+2
NO
AL ← M(S+1)
S ← S+1
❊ IMM8 is an immediate value in 1-byte and
inside of () specifies the contents of the bit
at the value.
7700 FAMILY SOFTWARE MANUAL
4–89
RLA
RLA
Rotate Left Accumulator A
Function
:
Operation
:
n bits rotate to left
→
A
← n bits rotate to left ←
When m=0
→
A
b15
b0
←
n bits rotate to left
❊ n = 0 to 65535
When m=1
→
b7
AL
←
b0
n bits rotate to left
❊ n = 0 to 255
Description
:
The contents of the accumulator A are rotated to the left by n bits. The value of n is specified
by the instruction’s third byte (or third and fourth bytes when m=0).
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
RLA #imm
89 16, 4916, imm
3
6+i
i: Number of rotation
(Note 1) When the data length selection flag m is 0, the bytes-count increases by 1.
4–90
7700 FAMILY SOFTWARE MANUAL
ROL
ROL
Rotate One Bit Left
Function
:
Operation
:
Rotate to left
→
Acc or M
C
← 1 bit rotate to left ← ←
When m=0
→
b15
Acc or M(n+1,n)
← ← ← ← ←
b0
C
← ← ← ← ←
←
When m=1
→
b7
AccL or M(n)
b0
← ← ← ← ← ← ← ← ←
Description
:
C
←
The carry flag C is linked to the accumulator or memory, and the combined contents are
rotated by 1 bit to the left.
Bit 0 of the accumulator or memory is loaded with the content of the carry flag C before
execution of this instruction, and the carry flag C is loaded with the content of bit 15 (or bit
7 if the data length selection flag m is set to 1) of the accumulator or memory before execution
of this instruction.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) before execution
of the instruction is 1. Otherwise, cleared to 0
Addressing mode
Syntax
Machine code
Bytes
Cycles
Accumulator
Direct
Direct indexed X
Absolute
Absolute indexed x
ROL
ROL
ROL
ROL
ROL
2A16
2616, dd
3616, dd
2E16, ll, mm
3E16, ll, mm
1
2
2
3
3
2
7
7
7
8
A
dd
dd, X
mmll
mmll, X
(Note 1) The accumulator addressing mode's specification in this table applies when using the accumulator
A. If using the accumulator B, replace “A” with “B”. In this case, “4216” is added at the beginning
of the machine code, the bytes-count increases by 1 and the cycles-count increases by 2.
7700 FAMILY SOFTWARE MANUAL
4–91
ROR
ROR
Rotate One Bit Right
Function
:
Rotate to right
Operation
:
←
→
C
Acc or M
→ 1 bit rotate to right →
When m=0
←
C
→
Acc or M(n+1,n)
b15
→ → → → →
b0
→ → → → →
When m=1
←
C
→
Description
:
AccL or M(n)
b7
b0
→ → → → → → → → →
The carry flag C is linked to the accumulator or memory, and the combined contents are
shifted by 1 bit to the right.
Bit 15 (or bit 7 if the data length selection flag m is set to 1) of the accumulator or memory
is loaded with the content of the carry flag C, and the carry flag C is loaded with the content
of bit 0 of the accumulator or memory before execution of this instruction.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Set to 1 when bit 0 before execution of the instruction is 1. Otherwise, cleared to 0.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Accumulator
Direct
Direct indexed X
Absolute
Absolute indexed X
ROR
ROR
ROR
ROR
ROR
6A16
6616, dd
7616, dd
6E 16, ll, mm
7E 16, ll, mm
1
2
2
3
3
2
7
7
7
8
A
dd
dd, X
mmll
mmll, X
(Note 1) The accumulator addressing mode's specification in this table applies when using the accumulator
A. If using the accumulator B, replace “A” with “B”. In this case, “4216” is added at the beginning
of the machine code, the bytes-count increases by 1 and the cycles-count increases by 2.
4–92
7700 FAMILY SOFTWARE MANUAL
RTI
RTI
Return from Interrupt
Function
:
Return from subroutine
Operation
:
PG, PC, PS ← Stack (Saved content when interrupt occurred)
PS ← M(S+2, S+1)
PC ← M(S+4, S+3)
PG ← M(S+5)
S← S + 5
PSH
PSL
PCH
PCL
Stack
(S) in just before instruction execution
(S) in just after instruction execution
PG
Description
:
The contents of the processor status register PS, program counter PC, and program bank
register PG, which are saved on the stack when the last interrupt was accepted, are restored
these registers.
Status flags
:
Restored according to the values that had been on the stack.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
RTI
4016
1
11
7700 FAMILY SOFTWARE MANUAL
4–93
RTL
RTL
Return from Subroutine Long
Function
:
Return from subroutine
Operation
:
PG, PC ← Stack (Subroutine long return address)
PC ← M(S+2, S+1)
PG ← M(S+3)
S ←S + 3
(S) in just after instruction execution
Stack
(S) in just before instruction execution
PG
PCH
PCL
Description
:
The program counter PC and program bank register PG are restored according to the state
previously saved on the stack.
Status flags
:
Not affected.
4–94
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
RTL
6B16
1
8
7700 FAMILY SOFTWARE MANUAL
RTS
RTS
Return from Subroutine
Function
:
Return from subroutine
Operation
:
PC ← Stack (Subroutine return address)
PC ← M(S+2, S+1)
S← S + 2
Stack
(S) in just before instruction execution
(S) in just after instruction execution
PCH
Description
:
PCL
The program counter PC is restored according to the state previously saved on the stack.
The contents of PG is added 1 when this instruction is at topmost address (XXFFFF16) of a
bank.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
RTS
6016
1
5
7700 FAMILY SOFTWARE MANUAL
4–95
SBC
SBC
Subtract with Carry
Function
:
Subtract with carry
Operation
:
Acc ← Acc – M – C
When m=0
Acc
Acc
M(n+1,n)
←
–
C
–
When m=1
AccL
Acc L
←
Description
:
M(n)
–
C
–
Subtracts the contents of memory and the 1's complements of carry flag from the contents of
the accumulator , and places the result in the accumulator. Executed as a binary subtraction
if the decimal operation mode flag D is set to 0. Executed as a decimal subtraction if the
decimal operation mode flag D is set to 1.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0. Meaningless for decimal subtraction.
V
:
Set to 1 when binary subtraction of signed data results in a value outside the range of -32768
to +32767 (-128 to +127 if the data length selection flag m is set to 1). Otherwise, cleared
to 0. Meaningless for decimal subtraction.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Set to 1 when the result of operation is equal to or larger than 0. Otherwise,
cleared to 0, and a borrow is indicated.
4–96
7700 FAMILY SOFTWARE MANUAL
SBC
SBC
Subtract with Carry
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
SBC A, #imm
E916 , imm
2
2
Direct
SBC A, dd
E516, dd
2
4
Direct indexed X
SBC A,dd, X
F516, dd
2
5
Direct indirect
SBC A, (dd)
F216, dd
2
6
Direct indexed X indirect
SBC A,(dd, X)
E116, dd
2
7
Direct indirect indexed Y
SBC A,(dd), Y
F116, dd
2
8
Direct indirect long
SBCL A, (dd)
E716, dd
2
10
Direct indirect long indexed Y
SBCL A, (dd), Y
F716, dd
2
11
Absolute
SBC A,mmll
ED16,ll,mm
3
4
Absolute indexed X
SBC A, mmll, X
FD16, ll, mm
3
6
Absolute indexed Y
SBC A, mmll, Y
F916, ll, mm
3
6
Absolute long
SBC A, hhmmll
EF16, ll, mm, hh
4
6
Absolute long indexed X
SBC A, hhmmll, X
FF16, ll, mm, hh
4
7
Stack pointer relative
SBC A, nn, S
E316, nn
2
5
Stack pointer relative
indirect indexed Y
SBC A, (nn, S), Y
F316, nn
2
8
(Note 1) This table applies when using the accumulator A. If using the accumulator B, replace “A” with “B”.
In this case, “4216” is added at the beginning of the machine code, the bytes-count increases by
1 and the cycles-count increases by 2.
(Note 2) When operating on 16-bit data in the immediate addressing mode with the data length selection flag
m set to 0, the bytes-count increases by 1.
7700 FAMILY SOFTWARE MANUAL
4–97
SEB
SEB
Set Bit
Function
:
Bit management
Operation
:
Mb ← 1 (b is the specified bits)
When m=0
M(n+1, n)
M(n+1,n)
←
IMM16
V
When m=1
M(n)
M(n)
←
IMM8
V
❊ IMM is an immediate value indicating the bit to be set with a “1” and is specified by the last
1 or 2 bytes of the instruction.
Description
:
The SEB instruction sets the specified memory bits to 1. Multiple bits to be set can be
specified at one time.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Direct bit
Absolute bit
SEB #imm, dd
SEB #imm, mmll
04 16, dd, imm
0C 16, ll, mm, imm
3
4
8
9
(Note 1) When operating on 16-bit data with the data length selection flag m set to 0, the bytes-count
increases by 1.
4–98
7700 FAMILY SOFTWARE MANUAL
SEC
SEC
Set Carry Flag
Function
:
Flag manipulation
Operation
:
C ←1
Description
:
Sets the carry flag C to 1.
Status flags
IPL :
Not affected.
N
:
Not affected.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Not affected.
C
:
Set to 1.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
SEC
3816
1
2
7700 FAMILY SOFTWARE MANUAL
4–99
SEI
SEI
Set Interrupt Disable Status
Function
:
Flag manipulation
Operation
:
I ← 1
Description
:
Sets the interrupt disable flag I to 1.
Status flags
4–100
IPL :
Not affected.
N
:
Not affected.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Set to 1.
Z
:
Not affected.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
SEI
7816
1
2
7700 FAMILY SOFTWARE MANUAL
SEM
SEM
Set m Flag
Function
:
Flag manipulation
Operation
:
m ← 1
Description
:
Sets the data length selection flag m to 1.
Status flags
IPL :
Not affected.
N
:
Not affected.
V
:
Not affected.
m :
Set to 1.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Not affected.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
SEM
F816
1
2
7700 FAMILY SOFTWARE MANUAL
4–101
SEP
SEP
Set Processor Status
Function
:
Flag manipulation
Operation
:
PS Lb ← 1 (b is the specified flags)
PS L ← PS L V IMM8
❊ IMM8 is an immediate value indicating the bit to be set with a “1” and is specified by
the last 1 or 2 bytes of the instruction.
b7 b6 b5 b4 b3 b2 b1 b0
N V m x D I Z C PSL
Description
:
Sets the processor status flags specified by the bit pattern in the second byte of the instruction
to 1.
Status flags
:
The specified status flags are set to “1”. IPL is not affected.
4–102
Addressing mode
Syntax
Machine code
Bytes
Cycles
Immediate
SEP #imm
E216 , imm
2
3
7700 FAMILY SOFTWARE MANUAL
STA
STA
Store Accumulator in Memory
Function
:
Store
Operation
:
M ← Acc
When m=0
M(n+1,n)
Acc
←
When m=1
M(n)
Acc L
←
Description
:
Stores the contents of the accumulator in memory.
The contents of the accumulator are not changed.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Direct
Direct indexed X
STA A, dd
STA A, dd, X
Direct indirect
Direct indexed X indirect
Direct indirect indexed Y
Direct indirect long
Direct indirect long indexed Y
Absolute
Absolute indexed X
Absolute indexed Y
Absolute long
Absolute long indexed X
Stack pointer relative
STA A, (dd)
STA A, (dd, X)
STA A, (dd), Y
STAL A, (dd)
STAL A, (dd), Y
STA A, mmll
STA A, mmll, X
STA A, mmll, Y
STA A, hhmmll
STA A, hhmmll, X
STA A, nn, S
Stack pointer relative
indirect indexed Y
STA A, (nn, S), Y
8516, dd
9516, dd
9216, dd
8116, dd
9116, dd
8716, dd
9716, dd
8D16, ll, mm
9D16, ll, mm
9916, ll, mm
8F16, ll, mm, hh
9F16, ll, mm, hh
8316, nn
9316, nn
2
2
2
2
2
2
2
3
3
3
4
4
2
2
4
5
7
7
7
10
11
5
5
5
6
7
5
8
(Note 1) This table applies when using the accumulator A. If using the accumulator B, replace “A” with “B”.
In this case, “42 16” is added at the beginning of the machine code, the bytes-count increases by 1
and the cycles-count increases by 2.
7700 FAMILY SOFTWARE MANUAL
4–103
STP
STP
SToP
Function
:
Oscillation control
Operation
:
Stop the oscillation
Description
:
Resets the oscillator controlling flip-flop circuit to inhibit the oscillation of the oscillation circuit.
To restart the oscillator, either an interrupt or reset must be executed.
Status flags
:
Not affected.
4–104
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
STP
DB16
1
3
7700 FAMILY SOFTWARE MANUAL
STX
STX
Store Index Register X in Memory
Function
:
Store
Operation
:
M ← X
When x=0
M(n+1,n)
X
←
When x=1
M(n)
XL
←
Description
:
Stores the contents of the index register X in memory. The contents of the index register X
remain the same.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Direct
Direct indexed Y
Absolute
STX dd
STX dd, Y
STX mmll
8616, dd
9616, dd
8E16, ll, mm
2
2
3
4
5
5
7700 FAMILY SOFTWARE MANUAL
4–105
STY
STY
Store Index Register Y in Memory
Function
:
Store
Operation
:
M ← Y
When x=0
M(n+1,n)
Y
←
When x=1
M(n)
YL
←
Description
:
Stores the contents of the index register Y in memory. The contents of the index register Y
remain the same.
Status flags
:
Not affected.
4–106
Addressing mode
Syntax
Machine code
Bytes
Cycles
Direct
Direct indexed X
Absolute
STY dd
STY dd, X
STY mmll
8416, dd
9416, dd
8C 16, ll, mm
2
2
3
4
5
5
7700 FAMILY SOFTWARE MANUAL
TAD
TAD
Transfer Accumulator A to Direct Page Register
Function
:
Transfer
Operation
:
DPR ← A
DPR
A
←
Description
:
Loads the direct page register DPR with the contents of the accumulator A. Data is transferred
as 16-bit data regardless of the status of the data length selection flag m. The contents of
the accumulator A are not changed.
Status flags
: Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TAD
5B16
1
2
7700 FAMILY SOFTWARE MANUAL
4–107
TAS
TAS
Transfer Accumulator A to Stack Pointer
Function
:
Transfer
Operation
:
S ←A
S
A
←
Description
:
Status flags
: Not affected.
4–108
Loads the stack pointer S with the contents of the accumulator A. Data is transferred as 16bit data regardless of the status of the data length selection flag m. The contents of the
accumulator A are not changed.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TAS
1B16
1
2
7700 FAMILY SOFTWARE MANUAL
TAX
TAX
Transfer Accumulator A to Index Register X
Function
:
Transfer
Operation
:
X ←A
When x=0
X
A
←
When x=1
XL
AL
←
Description
:
Loads the index register X with the contents of the accumulator A. The contents of the
accumulator A are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TAX
AA16
1
2
7700 FAMILY SOFTWARE MANUAL
4–109
TAY
TAY
Transfer Accumulator A to Index Register Y
Function
:
Transfer
Operation
:
Y ←A
When x=0
Y
A
←
When x=1
YL
AL
←
Description
:
Loads the index register Y with the contents of the accumulator A. The contents of the
accumulator A are not changed.
Status flags
4–110
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TAY
A816
1
2
7700 FAMILY SOFTWARE MANUAL
TBD
TBD
Transfer Accumulator B to Direct Page Register
Function
:
Transfer
Operation
:
DPR ← B
DPR
B
←
Description
:
Loads the direct page register DPR with the contents of the accumulator B. Data is transferred
as 16-bit data regardless of the status of the data length selection flag m. The contents of
the accumulator B are not changed.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TBD
4216 , 5B16
2
4
7700 FAMILY SOFTWARE MANUAL
4–111
TBS
TBS
Transfer Accumulator B to Stack Pointer
Function
:
Transfer
Operation
:
S ←B
S
B
←
Description
:
Loads the stack pointer S with the contents of the accumulator B. Data is transferred as 16bit data regardless of the status of the data length selection flag m. The contents of the
accumulator B are not changed.
Status flags
:
Not affected.
4–112
Addressing mode
Syntax
Machine code
Bytes Cycles
Implied
TBS
4216 , 1B16
2
7700 FAMILY SOFTWARE MANUAL
4
TBX
TBX
Transfer Accumulator B to Index Register X
Function
:
Transfer
Operation
:
X ←B
When x=0
X
B
←
When x=1
XL
BL
←
Description
:
Loads the index register X with the contents of the accumulator B. The contents of the
accumulator B are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Implied
TBX
Machine code
4216, AA16
7700 FAMILY SOFTWARE MANUAL
Bytes
Cycles
2
4
4–113
TBY
TBY
Transfer Accumulator B to Index Register Y
Function
:
Transfer
Operation
:
Y ←B
When x=0
Y
B
←
When x=1
YL
BL
←
Description
:
Loads the index register Y with the contents of the accumulator B. The contents of the
accumulator B are not changed.
Status flags
4–114
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TBY
4216 , A816
2
4
7700 FAMILY SOFTWARE MANUAL
TDA
TDA
Transfer Direct Page Register to Accumulator A
Function
:
Transfer
Operation
:
A ← DPR
When m=0
A
DPR
←
When m=1
AL
DPRL
←
Description
:
Loads the accumulator A with the contents of the direct page register DPR. The contents of
the direct page register DPR are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TDA
7B16
1
2
7700 FAMILY SOFTWARE MANUAL
4–115
TDB
TDB
Transfer Direct Page Register to Accumulator B
Function
:
Transfer
Operation
:
B ← DPR
When m=0
B
DPR
←
When m=1
BL
DPRL
←
Description
:
Loads the accumulator B with the contents of the direct page register DPR. The contents of
the direct page register DPR are not changed.
Status flags
4–116
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TDB
4216 , 7B16
2
4
7700 FAMILY SOFTWARE MANUAL
TSA
TSA
Transfer Stack Pointer to Accumulator A
Function
:
Transfer
Operation
:
A ←S
When m=0
A
S
←
When m=1
AL
SL
←
Description
:
Loads the accumulator A with the contents of the stack pointer S. The contents of the stack
pointer S are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TSA
3B16
1
2
7700 FAMILY SOFTWARE MANUAL
4–117
TSB
TSB
Transfer Stack Pointer to Accumulator B
Function
:
Transfer
Operation
:
B ←S
When m=0
B
S
←
When m=1
BL
SL
←
Description
:
Loads the accumulator B with the contents of the stack pointer S. The contents of the stack
pointer S are not changed.
Status flags
4–118
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TSB
4216 , 3B16
2
4
7700 FAMILY SOFTWARE MANUAL
TSX
TSX
Transfer Stack Pointer to Index Register X
Function
:
Transfer
Operation
:
X ←S
When x=0
X
S
←
When x=1
XL
SL
←
Description
:
Loads the index register X with the contents of the stack pointer S. The contents of the stack
pointer S are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TSX
BA16
1
2
7700 FAMILY SOFTWARE MANUAL
4–119
TXA
TXA
Transfer Index Register X to Accumulator A
Function
:
Transfer
Operation
:
A ←X
When m=0 and x=0
A
X
←
When m=0 and x=1
A
XL
←
00
❊ Under this condition, 0016 is transferred to AH regardless of XH.
When m=1
AL
XL
←
Description
:
Loads the accumulator A with the contents of the index register X. The contents of the index
register X are not changed.
Status flags
4–120
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TXA
8A16
1
2
7700 FAMILY SOFTWARE MANUAL
TXB
TXB
Transfer Index Register X to Accumulator B
Function
:
Transfer
Operation
:
B ←X
When m=0 and x=0
B
X
←
When m=0 and x=1
B
XL
←
00
❊ Under this condition, 00 16 is transferred to A H regardless of XH.
When m=1
BL
XL
←
Description
:
Loads the accumulator B with the contents of the index register X. The contents of the index
register X are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TXB
4216 , 8A16
2
4
7700 FAMILY SOFTWARE MANUAL
4–121
TXS
TXS
Transfer Index Register X to Stack Pointer
Function
:
Transfer
Operation
:
S ←X
When x=0
S
X
←
When x=1
S
00
Description
:
Status flags
: Not affected.
4–122
XL
←
Loads the stack pointers with the contents of the index register X. The contents of the index
register X are not changed.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TXS
9A16
1
2
7700 FAMILY SOFTWARE MANUAL
TXY
TXY
Transfer Index Register X to Y
Function
:
Transfer
Operation
:
Y ←X
When x=0
Y
X
←
When x=1
YL
XL
←
Description
:
Loads the index register Y with the contents of the index register X. The contents of the index
register X are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TXY
9B16
1
2
7700 FAMILY SOFTWARE MANUAL
4–123
TYA
TYA
Transfer Index Register Y to Accumulator A
Function
:
Transfer
Operation
:
A ←Y
When m=0 and x=0
A
Y
←
When m=0 and x=1
A
YL
←
00
❊ Under this condition, 0016 is transferred to AH regardless of YH.
When m=1
AL
YL
←
Description
:
Loads the accumulator A with the contents of the index register Y. The contents of the index
register Y are not changed.
Status flags
4–124
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TYA
9816
1
2
7700 FAMILY SOFTWARE MANUAL
TYB
TYB
Transfer Index Register Y to Accumulator B
Function
:
Transfer
Operation
:
B ←Y
When m=0 and x=0
B
Y
←
When m=0 and x=1
B
YL
←
00
❊ Under this condition, 00 16 is transferred to B H regardless of YH.
When m=1
BL
YL
←
Description
:
Loads the accumulator B with the contents of the index register Y. The contents of the index
register Y are not changed.
Status flags
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the operation
result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Implied
TYB
4216 , 9816
2
7700 FAMILY SOFTWARE MANUAL
Cycles
4
4–125
TYX
TYX
Transfer Index Register Y to X
Function
:
Transfer
Operation
:
X ←Y
When x=0
X
Y
←
When x=1
XL
YL
←
Description
:
Loads the index register X with the contents of the index register Y. The contents of the index
register Y are not changed.
Status flags
4–126
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the index register length selection flag x is set to 1) of the
operation result is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Not affected.
Z
:
Set to 1 when the result of operation is 0. Otherwise, cleared to 0.
C
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
TYX
BB16
1
2
7700 FAMILY SOFTWARE MANUAL
WIT
WIT
Wait
Function
:
Clock control
Operation
:
Stop the CPU clock
Description
:
The WIT instruction stops the internal clock but not the oscillation of the oscillation circuit is
not stopped. To restart the internal clock, either an interrupt or reset must be executed.
Status flags
:
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
WIT
CB16
1
3
7700 FAMILY SOFTWARE MANUAL
4–127
XAB
XAB
Exchange Accumulator A and B
Function
:
Exchange
Operation
:
A←
→ B
When m=0
A
B
←
→
When m=1
AL
BL
←
→
Description
:
Swaps the contents of the accumulators A and B.
Status flags
4–128
IPL :
Not affected.
N
:
Set to 1 when bit 15 (or bit 7 if the data length selection flag m is set to 1) of the accumulator
A after the operation is 1. Otherwise, cleared to 0.
V
:
Not affected.
m :
Not affected.
x
:
Not affected.
D
:
Not affected.
I
:
Z
:
Set to 1 when the contents of the accumulator A is cleared to 0 by the operation. Otherwise,
cleared to 0.
C
:
Not affected.
Not affected.
Addressing mode
Syntax
Machine code
Bytes
Cycles
Implied
XAB
8916 , 2816
2
6
7700 FAMILY SOFTWARE MANUAL
INSTRUCTIONS
4.3 Notes for programming
4.3 Notes for Programming
Take care of the following when programming with the 7700 Family.
(1)
The stack pointer S is undefined immediately after the reset is commanded. Always set the initial value.
Example )
LDX
TXS
#27FH
(2)
The program bank register PG and the data bank register DT are disabled under the single chip mode. Do
not set value other than “0016” here.
(3)
When “1” is set in the D-flag for decimal operation:
The C-flag alone is effective in the ADC instruction, while the Z, N, and V flags are disabled. The C and Z
flags alone are effective in the SBC instruction, while the N and V flags are disabled. (Decimal operation can
be done in the ADC and the SBC instructions alone.)
(4)
Using the 16-bit immediate data with “1” (data length : 8 bits) in the data length selection flag m, or using
the 8- bit immediate data with “0” (data length : 16 bits) in flag m, will cause the program run-away. The same
rule is applied to the index register length selection flag x. Take care of the condition of these flags when
coding the program.
(5)
The 7700 Family can prefetch the instructions using the 3-byte instruction queue buffer. Keep in mind when
creating the timer with the software, that the number of cycles shown in the list of machine language
instructions is the minimum value. (Also see Chapter 5.)
(6)
When value other than “00 16” is set in the lower order 8 bits of the direct page register DPR (DPR L), the
processing time will become 1 machine cycle longer than when “00 16” is set.
(7)
The processing speed will deteriorate if a 16- bit data will be accessed from an odd address. Place the 16bit data from an even address if the processing speed is important.
(8)
The N and Z flags will change by execution of the PLA instruction, but the contents of the processor status
register will not change if the accumulator A alone is recovered by the PUL instruction.
(9)
The program bank register PG can be saved into the stack by setting “1” in bit 6 of the operation by the PSH
instruction. However, the PG cannot be recovered by the PUL instruction.
(10) The code in the second byte of the BRK instruction will not affect the CPU.
7700 FAMILY SOFTWARE MANUAL
4–129
INSTRUCTIONS
4.3 Notes for programming
MEMORANDUM
4–130
7700 FAMILY SOFTWARE MANUAL
CHAPTER 5
INSTRUCTION EXECUTION SEQUENCE
5.1 Change of the CPU basic
clock φCPU
5.2 Instruction execution sequence
INSTRUCTION EXECUTION SEQUENCE
5.1 Change of the CPU basic clock φ CPU
The basic clock of the 7700 Family central processing unit (CPU) is the internal clock φ (divided by 2 of the
oscillation frequency f(XIN)). The basic clock of the bus is an E derived from the internal clock φ, so data exchange
between the CPU and the internal bus is done via the bus interface unit (BIU). The frequency of E is normally
divided by 2 of the internal clock φ, but it becomes divided by 3 or 4 of φ, when accessing external memory while
the wait is enabled by the wait bit (Note).
Note : The frequency of E is depend on the product. Therefore, refer to an user's manual or a data sheet
(or a data book) to confirm it.
5.1 Change of the CPU Basic Clock φCPU
When the bus interface unit is not ready, the CPU extends the basic clock to synchronize with the bus, and
waits till it is ready. As the CPU basic clock waits owing to some conditions, this clock will be called φCPU to
be distinguished from the clock . The following are the cases in which the φ CPU waits.
Causes for the φCPU to wait
<Cause 1>
When the CPU requests operation codes and operands, but the operation codes and operands
in the instruction queue buffer did not reach the necessary number.
<Cause 2>
When the CPU tried to access data, but the bus interface unit was using the bus for fetching some
data into the instruction queue buffer or writing data.
<Cause 3>
When the bus interface unit was reading data from the internal/external memory or I/O, according
to the request of the CPU.
In addition to the above, the following are also causes for the φCPU to be extended.
•When 16-bit data is accessed from odd address.
•When external memory 16-bit data is accessed while the BYTE terminal level is “H”.
•When external memory is accessed with wait commanded by the wait bit.
The above conditions causes the execution time to differ each time, even with the same instruction and same
addressing mode. Two example instructions are given in the next section to see the variation of the number
of cycles according to the above conditions.
The “CPU execution sequence per addressing mode” of Chapter 6 is the CPU instruction execution sequences
based on the φCPU. The number of cycles shown in “4.2 Instructions” and “Appendix 1 List of machine
instructions” are the count for the shortest case, and cannot always be applied when calculating the actual
cycles or the execution time of instructions.
5–2
7700 FAMILY SOFTWARE MANUAL
INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
5.2 Instruction Execution Sequence
This section describes how the instruction execution cycles change under various conditions.
• Example 1. ASL instruction
Direct addressing mode
• Example 2. LDA instruction
Direct indirect long addressing mode
Before observing the φCPU based CPU instruction execution sequence
The following table describes the φCPU based CPU instruction execution sequence symbols. The signals
indicated in this execution sequence are all CPU internal signals, that show data exchange between the bus
interface unit and the CPU. Accordingly, these signals cannot be observed from outside.
φCPU Based CPU Instruction Execution Sequence Symbols
Symbol
Description
φCPU
CPU basic clock
AP(CPU)
Higher order 8 bits of the address (24 bits) of the program that the CPU is actually execution
AHAL(CPU)
Lower order 16 bits of the address (24 bits) of the program that the CPU is actually execution
DATA(CPU)
Data information the CPU is processing
R/W(CPU)
Data read/write request to the data buffer in the bus interface unit
PG,PC
Contents of the program bank register (PG) and the program counter (PC)
ADP
Data indicating the address (higher order 8 bits)
ADH,ADL
Data indicating the address (lower order 16 bits)
DPRH
Contents of the higher order 8 bits of the direct page register
DPRL
Contents of the lower order 8 bits of the direct page register (DPRL = 0 in the examples)
DH
Data to be fetched or written from the data buffer by the CPU (higher order 8 bits)
DL
Data to be fetched or written from the data buffer by the CPU (lower order 8 bits)
dd
Contents of the operand (DPRL = 0 in examples 1 and 2, so dd represents the lower order 8 bits
of the address)
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Before observing the φ based instruction execution sequence
The φ based instruction execution sequence symbols are shown in the following table. The signals in this
execution sequence indicates data exchange of the bus interface unit with the memory and I/O. The internal
instruction execution sequence of the CPU can be guessed from these signals.
However, the φCPU and the number of data in the instruction queue buffer shown here cannot be observed from
the outside.
φ Based Execution Sequence Symbols
Symbol
Description
φ
Basic operation clock of the microcomputer (divided by 2 of f(XIN) )
E
Basic operation clock of the bus (divided by 2 of φ )
hh
Higher order 8 bits of the address where the bus interface unit is to access to (bank)
mm
Middle order 8 bits of the address where the bus interface unit is to access to
ll
Lower order 8 bits of the address where the bus interface unit is to access to
DPR
Contents of the direct page
❊ No wait
DPR H
Contents of the higher order 8 bits of the direct page register
DPR L
Contents of the lower order 8 bits of the direct page register
OP1
Data to be fetched into the instruction queue buffer by the bus interface
OP2
OP3
(Operation code or operand)
The subscript represents the fetch sequence.
:
DL
Data to be fetched into the data buffer or data to be written into the memory by the bus interface unit
DH
dd
Data obtained as the operand (The lower order 8 bits of the address are given in examples 1 and
2, because DPRL = 0.)
ADP
Higher order 8 bits of data that indicates the address (contents of the data address register)
ADH
Middle order 8 bits of data that indicates the address (contents of the data address register)
ADL
Lower order 8 bits of data that indicates the address (contents of the data address register)
The following are the cause of the “ φCPU to queue” in the φ based instruction execution sequence.
Cause 1
When the CPU required operation codes and operands, but the number of operation codes and operands did
not reach the requested number.
Cause 2
When the CPU tried to access data, but the bus interface was using the bus for fetching data into the instruction
queue buffer or for writing data.
Cause 3
When the bus interface unit is reading data from the internal/external memory or I/O, etc., according to the
request of the CPU.
5–4
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPRL = 0016)
φCPU based CPU instruction execution sequence
φ
CPU
AP(CPU)
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
DPRH,dd
PC+2
DATA(CPU)
Op Code Operand dd
DHDL
Not Used New
DHDL
Next
Op Code
R/W(CPU)
The following examples 1-1 to 1-6 are examples of the φCPU based instruction execution sequences
under various conditions.
Example 1-1 When the instruction queue buffer is vacant
Example 1-2 When two data are in the instruction queue buffer
Example 1-3 When three data are in the instruction queue buffer
Example 1-4 When 16-bit data is accessed from odd address
Example 1-5 When external memory is accessed from the BYTE terminal using 8-bit external
bus width
Example 1-6 When external memory is accessed with wait by the wait bit
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPR L = 0016)
(Example 1-1) When the instruction queue buffer is vacant
Conditions
• Number of data in the instruction queue buffer .................................. 0
• ROM, RAM ......................................................................................... External memory is used (Note)
• Data length selection flag m ............................................................... “0” (16-bit length)
• BYTE terminal level ............................................................................ “L” (External bus width is 16 bits)
• Contents of lower order bytes (PCL) of the program counter ............. Even
• Contents of the operand (dd) ............................................................. Even
φ based execution sequence
1
φ
φ
2
3
4
5
6
7
8
9
CPU
Fetches
Op Code
Number of data in inst0
ruction queue buffer
A23—A16
/DATA(even)
hh
Fetches
Operand
2→1
0
2
OP1
hh
OP3
Op Code
A15—A8
/DATA(odd)
mm
OP2
Modifies Writes
Data
Data
Reads data
Next
Instruction
1
00
DL
00
Modified DL
DH
DPRH
Modified DH
Next Op Code
mm
OP4
DPRH
Operand (dd)
ll
A7—A0
l l+2
dd
E
BHE
“L”
R/W
Cause for φ CPU
to queue
Cause 1
Cause 2
Cause 3
Note. The operation when internal ROM and internal RAM are used, will be as shown above, regardless of the level of the BYTE terminal. However, the address/data bus, BHE, R/W signal cannot
be observed from outside, when the mode is single-chip mode.
5–6
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPRL = 0016)
Operation of the CPU and bus interface unit under various cycles
φ No.
CPU
Bus interface unit
1
(No fetching can be done, because there are no
operation codes in the instruction queue buffer.)
Fetches the instruction, because instruction
queue buffer is vacant and the CPU is not using
the bus.
2
Fetches 2-byte worth of data into the instruction
queue buffer when E becomes “L”.
Fetches the operation code.
3
Fetches the operand.
Prefetches the instruction, because the instruction queue buffer is vacant and the CPU is not
using the bus.
4
(Waits till the bus used by the bus interface unit
becomes vacant.)
Fetches 2 bytes worth of data into the instruction
queue buffer when E becomes “L”.
5
Waits for E to become “L”, to read data.
6
Reads data when E becomes “L”.
7
Modifies data.
8
Writes data into the data buffer.
9
Fetches the next operation code.
Writes the contents of the data buffer into the
original address, when E becomes “L”.
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPR L = 0016)
(Example 1-2) When two data are in the instruction queue buffer
Conditions
• Number of data in the instruction queue buffer ............................... 2
• ROM, RAM ....................................................................................... External memory is used (Note)
• Data length selection flag m ............................................................ “0” (16-bit length)
• BYTE terminal level .......................................................................... “L” (External bus width is 16 bits)
• Contents of lower order bytes (PCL) of the program counter ........ Even
• Contents of the operand (dd) .......................................................... Even
φ based execution sequence
2
1
φ
3
4
5
6
7
8
φ
CPU
Fetches Fetches
Op Code Operand
Number of data in instruction queue buffer 2
A23—A16
/DATA(even)
1
0
hh
Modifies Writes
Data
Data
Reads Data
2
OP1
Next
Instruction
1
00
DL
00
Modified DL
DH
DPRH
Modified DH
Next Op Code
A15—A8
/DATA(odd)
mm
A7—A0
OP2
DPRH
ll
dd
E
BHE
“L”
R/W
Cause for φ CPU
to queue
Cause 2
Cause 3
Note. The operation when internal ROM and internal RAM are used, will be as shown above, regardless of the level of the BYTE terminal. However, the address/data bus, BHE, R/W signal cannot
be observed from outside, when the mode is single chip mode.
5–8
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPRL = 0016)
Operation of the CPU and bus interface unit under various cycles
φ No.
CPU
Bus interface unit
1
Fetches operation code.
2
Fetches operand (dd).
Prefetches the instruction, because the instruct
queue buffer is vacant and the CPU is not using
the bus.
3
(Waits till the bus used by the bus interface unit
becomes vacant.)
Fetches 2-byte worth of data into the instruction
queue buffer when E becomes “L”.
4
Waits for E to become “L”, to read data.
5
Reads data when E becomes “L”.
6
Modifies data.
7
Writes data into the data buffer.
8
Fetches the next operation code.
Writes the contents of the data buffer into the
original address, when E becomes “L”.
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPR L = 0016)
(Example 1-3) When three data are in the instruction queue buffer
Conditions
• Number of data in the instruction queue buffer .................................. 3
• ROM, RAM ......................................................................................... External memory is used (Note)
• Data length selection flag m ............................................................... “0” (16-bit length)
• BYTE terminal level ............................................................................ “L” (External bus width is 16 bits)
• Contents of lower order bytes (PCL) of the program counter ............. Even
• Contents of the operand (dd) ............................................................. Even
φ based execution sequence
2
1
φ
3
4
5
6
7
8
φ
CPU
Fetches Fetches Reads data
Op Code Operand
Number of data in instruction queue buffer 3
2
Writes
Data
Modifies
Data
1
Next
Instruction
3
2
A23—A16
/DATA(even)
hh
00
DL
hh
OP1
00
Modified DL
A15—A8
/DATA(odd)
mm
DPRH
DH
mm
OP2
DPRH
Modified DH
A7—A0
ll
dd
ll
dd
E
BHE
“L”
R/W
Cause for φ CPU
to queue
Cause 3
Cause 2
Note. The operation when internal ROM and internal RAM are used, will be as shown above, regardless of the level of the BYTE terminal. However, the address/data bus, BHE, R/W signal cannot
be observed from outside, when the mode is single chip mode.
5–10
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPRL = 0016)
Operation of the CPU and bus interface unit under various cycles
φ No.
CPU
Bus interface unit
1
Fetches operation code .
2
Fetches operand (dd).
3
Waits for E to become “L”, to read data.
4
Reads data when E becomes “L”.
5
Modifies data.
Prefetches the instruction, because there are two
vacant instruction queue buffers and the CPU is
not using the bus.
6
(Waits till the bus used by the bus interface unit
becomes vacant.)
Fetches 2-byte worth of data into the instruction
queue buffer when E becomes “L”.
7
Writes data into the data buffer.
8
Fetches the next operation code.
Writes the contents of the data buffer into the
original address, as E becomes “L”.
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPR L = 0016)
(Example 1-4) When 16-bit data is accessed from odd address
Conditions
• Number of data in the instruction queue buffer .................................. 0
• ROM, RAM ........................................................................................ External memory is used (Note 1)
• Data length selection flag m............................................................... “0” (16-bit length)
• BYTE terminal level ........................................................................... “L” (External bus width is 16 bits)
• Contents of lower order bytes (PCL) of the program counter ............. Odd
• Contents of the operand (dd) ............................................................. Odd
φ based execution sequence
1
φ
2
3
4
5
6
7
8
9
10
11
12
13
14
φ
CPU
Fetches
Op Code
Number of data in
instruction queue
buffer
A23—A16
/DATA(even)
1→0
0
hh
OP1
mm
OP2
Op Code
A7—A0
ll
Writes
Data
Modifies
Data
2→1
hh
OP3
mm
OP4
00
D
00
DH
hh
OP5
2
00
?
Invalid
DPRH
DL
DPRH
D
mm
OP6
Invalid
dd
Modified DH
00
Invalid
Next Op Code
l l+1
Next Instruction
3
Operand (dd)
Invalid
A15—A8
/DATA(odd)
Reads Data
Fetches
Operand
d d+1
l l+3
DPRH Modified DPRH
DL
dd
?
Invalid
d d+1
E
BHE
R/W
Cause for φ CPU
to queue
Cause 1
Cause 1
Cause 3
Cause 2
Cause 2
(Note 2)
Note 1. The operation when internal ROM and internal RAM are used, will be as shown above,
regardless of the level of the BYTE terminal. However, the address/data bus, BHE, R/W
signal cannot be observed from outside, when the mode is single chip mode.
Note 2. At the
part
❊ When the CPU does not use the bus, φCPU corresponds with φ.
❊ When the CPU uses the bus, the φCPU queues till the writing in the bus interface unit completes.
(the φ14 cycle)
5–12
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPRL = 0016)
Operation of the CPU and bus interface unit under various cycles
φ No.
CPU
1
(No fetching can be done, because there are no
operation codes in the instruction queue buffer.)
2
3
Bus interface unit
Fetches the instruction, because instruction queue
buffer is vacant and the CPU is not using the bus.
Fetches 1 odd address byte worth of data into the
instruction queue buffer, when E becomes “L”.
Fetches operation code.
(No fetching can be done, because there are no
operands in the instruction queue buffer.)
4
Fetches the instruction, because instruction
queue buffer is vacant and the CPU is not using
the bus.
Fetches 2-byte worth of data into the instruction
queue buffer when E becomes “L”.
Fetches operand (dd).
5
Waits for E to become “L”, to read data.
6
Reads data in the odd addresses (DL) alone into the data buffer when E becomes “L”.
7
Waits for E to become “L”, to read data.
8
Reads data in the even addresses (DH) alone into the data buffer when E becomes “L”.
9
Modifies data.
Prefetches the instruction, because there are two
vacant positions in the instruction queue buffer,
and the CPU is not using the bus.
10
(Waits till the bus used by the bus interface unit
becomes vacant.)
Fetches 2 bytes worth of data into the instruction
queue buffer, when E becomes “L”.
11
Writes data into the data buffer.
Waits till E becomes “L” to write data.
12
Fetches the next operation code.
Writes the contents of the data buffer (DL ) into
the original address (odd address), when E becomes “L”.
13
?
14
?
Waits till E becomes “L” to write data.
Writes the contents of the data buffer (D H) into
the original address (even address), when E becomes “L”.
When internal ROM or BYTE terminal level “L” external memory is used as the program memory, the instruction is
fetched into the instruction queue buffer normally in 2-byte (word) unit of sequential even and odd addresses in this
order. However, when the instruction must be fetched from odd address like after execution of the JMP instruction,
the 1-byte of the first odd address alone is fetched into the instruction queue buffer (φ2 cycle), and the later instructions
are fetched into the instruction queue buffer in 2-byte units (φ4, φ10 cycle).
The bus interface unit automatically selects whether to fetch one word or to fetch the 1 byte of odd address alone. The
operation status can be observed from outside, according to the output of the BHE terminal and the address bus signal
A0 , as long as the mode is not single-chip mode.
• When one word is fetched
The output from both the BHE terminal and the address bus A0 are at the “L” level.
• When 1 byte of odd address alone is fetched
The output from the BHE terminal is “L”, while the output from address bus A0 is “H”.
When internal RAM and external memory at BYTE terminal level “L” are used as the data memory, with data
length selection flag m=0, both data read and write are normally done in 2-byte units of even and odd addresses,
in this sequence. However, access can also be done when the word data is defined from an odd address. In
other words, “H” is output first from address bus A0 and then “L” from the BHE terminal to access to odd address
alone. Next, “L” is output from A0, and “H” from the BHE terminal to access to the even address (φ5 to φ8, φ11
to φ14 cycle).
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPR L = 0016)
(Example 1-5) When external memory is accessed from the BYTE terminal using 8-bit
external bus width
Conditions
• Number of data in the instruction queue buffer .................................. 0
• ROM, RAM ......................................................................................... External memory is used
• Data length selection flag m ............................................................... “0” (16-bit length)
• BYTE terminal level ............................................................................ “H” (External bus width is 8 bits)
φ based execution sequence
1
φ
φ
2
3
4
5
6
7
8
9
10
11
12
13
14
CPU
Fetches
Op Code
Number of data in
instruction queue
buffer
A23—A16
/DATA(even)
1→0
0
hh
OP1
Op Code
A15—A8
/DATA(odd)
A7—A0
Fetches
Operand
Reads Data
Modifies
Data
1→0
OP2
hh
1
DL
00
DH
00
hh
mm
ll
l l+1
OP3
0
00
Next Op Code
Operand (dd)
mm
Next
Instruction
Writes
Data
DPRH
dd
Modified
DL
mm
d d+1
l l+2
00
Modified DH
DPRH
dd
d d+1
E
BHE
R/W
Cause for φ CPU
to queue
Cause 1
Cause 1
Cause 3
Cause 2
Cause 2
(Note)
Note. At the
part
❊ When the CPU does not use the bus, φCPU corresponds with φ.
❊ When the CPU uses the bus, the φCPU queues till the writing in the bus interface unit completes.
(the φ13 to φ14 cycle)
5–14
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPRL = 0016)
Operation of the CPU and bus interface unit under various cycles
φ No.
CPU
1
(No fetching can be done, because there are no
operation codes in the instruction queue buffer.)
2
Bus interface unit
Fetches the instruction, because the instruction
queue buffer is vacant and the CPU is not using
the bus.
Fetches 1 odd address byte worth of data into the
instruction queue buffer when E becomes “L”.
Fetches operation code.
3
(No fetching can be done, because there are no
operands in the instruction queue buffer.)
4
Fetches the instruction, because instruction
queue buffer is vacant and the CPU is not using
the bus.
Fetches 1-byte worth of data into the instruction
queue buffer when E becomes “L”.
Fetches operand (dd).
5
Waits for E to become “L”, to read data.
6
Reads data (DL) into the data buffer when E becomes “L”.
7
Waits for E to become “L”, to read data.
8
Reads data (DH) alone into the data buffer when E becomes “L”.
9
Modifies data.
Prefetches the instruction, because there are two
vacant positions in the instruction queue buffer,
and the CPU is not using the bus.
10
(Waits till the bus used by the bus interface unit is
vacant.)
Fetches 1 byte worth of data into the instruction
queue buffer when E becomes “L”.
11
Writes data into the data buffer.
Waits till E becomes “L” to write data.
12
Fetches the next operation code.
Writes the contents of the data buffer (DL ) into
the original address (odd address), when E becomes “L”.
13
?
Waits till E becomes “L” to write data.
14
?
Writes the contents of the data buffer (DH) into
the original address (even address), when E becomes “L”.
The external bus width becomes 8 bits when the “H” level is applied to the BYTE terminal. (The width of the internal
bus is 16 bits, regardless of the level of the BYTE terminal.) When external ROM is used under this mode, the instruction
can only be fetched byte by byte. (φ2, φ4, φ10 cycle) When external RAM is used, the data can likewise only be handled
byte by byte. Accordingly, when data length selection flag m = 0 is selected, it takes time worth 2 cycles of the enable
output E for data read and write. (φ5 to φ8, φ11 to φ14 cycle)
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPR L = 0016)
(Example 1-6) When external memory is accessed with wait by the wait bit
Conditions
• Number of data in the instruction queue buffer .................................. 0
• ROM, RAM ......................................................................................... External memory is used
• Data length selection flag m ............................................................... “0” (16-bit length)
• BYTE terminal level ............................................................................ “L” (External bus width is 16 bits)
• Contents of lower order bytes (PCL) of the program counter ............. Even
• Contents of the operand (dd) ............................................................. Even
φ based execution sequence
1
2
φ
φ
3
4
5
6
7
8
9
10
11
12
13
CPU
Fetches Op Code
Number of data
in instruction
queue buffer
A23—A16
/DATA(even)
0
hh
Fetches Operand
2→1
0
2
OP1
hh
OP3
Op Code
A15—A8
/DATA(odd)
mm
OP2
Reads Data
Modifies Writes
Data
Data
Next
Instruction
1
00
DL
00
Modified DL
DPRH
DH
DPRH
Modified DH
Next Op Code
mm
OP4
Operand (dd)
A7—A0
l l+2
ll
dd
E
Note
BHE
Note
Note
Note
“L”
R/W
Cause for φ CPU
to queue
Cause 1
Cause 2
Cause 3
Note: This figure hows the case of the bus cycle becomes as 3 cycles of φ. If the bus cycle becomes 4 cycles of φ by
wait, the “H” width of E (←→ ) becomes as 2 cycles. Therefore, the ASL instruction execution time extended
by 4 cycles from the above case.
5–16
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 1. ASL instruction / direct addressing mode (DPRL = 0016)
Operation of the CPU and bus interface unit under various cycles
φ No.
CPU
1
(No fetching can be done, because there are no
operation codes in the instruction queue buffer.)
2
3
Bus interface unit
Fetches the instruction, because instruction queue
buffer is vacant and the CPU is not using the bus.
Fetches 2 bytes worth of data into the instruction
queue buffer when E becomes “L”.
Fetches the operation code .
4
Fetches operand (dd).
Prefetches the instruction because the instruction
queue buffer is vacant and the CPU is not using the
bus.
5
6
(Waits till the bus used by the bus interface unit
becomes vacant.)
Fetches 2 bytes worth of data into the instruction
queue buffer when becomes “L”.
7
Waits till E becomes “L” to write data.
8
Reads data when E becomes “L”.
9
10
Modifies data.
11
Writes data into the data buffer.
12
Fetches the next operation code.
13
?
Writes the contents of the data buffer into the
original address (odd address), when E becomes
“L”.
The conditions are the same as the Example 1-1, except when wait is commanded by the wait bit . When accessing
to the external memory, the “L” width of enable output E is extended by 1 cycle of φ when compared to the case of no
wait. Therefore, the φCPU wait interval is also extended by 1 cycle (φ2 to φ3, φ5 to φ6, φ8 to φ9 cycle).
If the bus cycle becomes 4 cycles, the φCPU wait interval is also extended by 2 cycles of φ because the “H” and “L” width
extended by 1 cycle from the case no wait.
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
5–18
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 2. LDA instruction / Direct indirect long addressing mode (DPRL = 0016)
φCPU based CPU instruction execution sequence
φ
CPU
AP(CPU)
PG
PG
AHAL(CPU)
PC
PC+1
DATA(CPU)
00
00or01
DPRH,dd
Op Code Operand dd ADHADL
00or01
ADP
PG
DPRH +dd+2
ADHADL
PC+2
Not Used
ADP
DHDL
Next
Op Code
R/W(CPU)
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INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 2. LDA instruction / Direct indirect long addressing mode (DPRL = 0016)
(Example 2-1) When the internal as well as the external memories are used together while wait is commanded
by the wait bit.
Conditions
• Number of data in the instruction queue buffer .................................. 0
• Bank 0 ................................................................................................ Internal ROM, RAM are used
Bank 1 and after ................................................................................. External memory is used
• Data length selection flag m ............................................................... “0” (16-bit length)
• BYTE terminal level ............................................................................ “L” (External bus width is 16 bits)
• Contents of lower order bytes (PCL) of the program counter ............. Even
• Contents of the operand (dd) ............................................................. Even
• Data indicated by the address
ADL ................................................. Even
ADP ................................................ 1 or more (bank 1 and after)
φ based execution sequence
φ
2
1
φ
3
4
5
6
7
8
9
10
11
12
13
CPU
Fetches
Op code
Number of data in
instruction queue
buffer
A23—A16
/DATA(even)
Fetches
Operand
2→1
0
hh
OP1
0
mm
OP2
Calculates
Address
Reads
Data
Reads
Data
Next
Instruction
2
OP3
hh
Op Code
A15—A8
/DATA(odd)
Reads
Data
1
00
ADL
00
ADP
ADP
DL
ADH
DPRH
?
ADH
DH
Next Op Code
mm
OP4
DPRH
Operand (dd)
A7—A0
ll
l l+2
dd
d d+2
ADL
E
Note
BHE
R/W
“H”
Cause for φ CPU
to queue
Cause 1
Cause 2
Cause 3
Cause 3
Cause 3
Note: This figure hows the case of the bus cycle becomes as 3 cycles of φ. If the bus cycle becomes 4 cycles of φ by
wait, the “H” width of E (←→ ) becomes as 2 cycles.
5–20
7700 FAMILY SOFTWARE MANUAL
INSTRUCTION EXECUTION SEQUENCE
5.2 Instruction execution sequence
Example 2. LDA instruction / Direct indirect long addressing mode (DPRL = 0016)
Operation of the CPU and bus interface unit under various cycles
φ No.
CPU
Bus interface unit
1
(No fetching can be done, because there are no
operation codes in the instruction queue buffer.)
Fetches the instruction, because instruction queue
buffer is vacant and the CPU is not using the bus.
2
Fetches 2 bytes worth of data into the instruction
queue buffer when E becomes “L”.
Fetches the operation code .
3
Fetches operand (dd).
Prefetches the instruction because the instruction
queue buffer is vacant and the CPU is not using the
bus.
4
(Waits till the bus used by the bus interface unit
becomes vacant.)
Fetches 2 bytes worth of data into the instruction
queue buffer when E becomes “L”.
5
Waits for E to becomes “L”, to read data (ADH, ADL) indicated by the address obtained by adding the contents
of the operand (dd) and the DPRL.
6
Reads data when E becomes “L”.
Calculated address.
7
8
Waits for E to become “L”, to read data (ADP).
9
Reads data when E becomes “L”.
10
Waits for E to become “L”, to read the data (DH, DL) at the address specified by ADP, ADH, ADL.
11
12
Reads data when E becomes “L”.
The above is the case when bank 1 and after are used by the external memory under the memory expansion mode.
The currently executed program is in bank 0. The contents of the lower order bytes of the direct page register DPRL
is “0016”, so the direct pages are all in bank 0. The access to the outside (φ10 to φ12 cycle) alone is affected by the wait
bit, and access to the internal memory is not affected by the bit.
7700 FAMILY SOFTWARE MANUAL
5–21
CHAPTER 6
CPU INSTRUCTION EXECUTION SEQUENCE FOR
EACH ADDRESSING MODE
CPU INSTRUCTION EXECUTION SEQUENCE FOR
EACH ADDRESSING MODES
The following are the CPU instruction execution sequences for each addressing mode. The execution sequences
shown here describe the internal operation of the CPU. Therefore, the signals are all CPU internal signals, and
cannot be observed from outside. The CPU internal operation, the actual execution time, and the relation between
signals that can be externally checked are described in Chapter 4 “Instruction Execution Sequence”.
The following are the signals and the symbols indicating the contents.
Symbol
Description
φCPU
CPU basic cycle
A P(CPU)
Higher order 8 bits of the CPU internal address bus.
A HA L(CPU)
Lower order 16 bits of the CPU internal address bus.
PG
Contents of the program bank register.
PC
Contents of the program counter.
Others are data that indicates the address obtained as result of address calculation.
DATA (CPU)
The CPU internal data bus. The signal is output with a half-cycle delay from the CPU internal
address bus. The operation codes and the operands are fetched from the instruction buffer. They
are not directly fetched from the memory indicated by the PG and PC of this cycle.
R/W(CPU)
Becomes “L” when the CPU writes data into the data buffer of the bus interface unit.
The accumulator used in the above instructions in the CPU instruction execution sequence is accumulator A.
When accumulator B is used, the execution cycle will have the two cycles of a “4216 ” that indicates accumulator
B, and an internal processing cycle added at the front. (See the figure in the next page.)
The number of φCPU cycles differs in the addressing mode that uses the direct page register, according to
whether the lower order 8 bits (DPRL) are “0016”. The number of cycles when DPRL = 0016 is 1 cycle (address
calculation cycle) less than when DPR L ≠ 0016.
The number of cycles differs in the PSH and PUL instructions according to the number and type of registers
placed in (taken out of) the stack.
The number of cycles differs in the block transmission instruction (MVN, MVP), according to the number of the
data transmitted.
Note. The instructions with the mark “ * ” can be used in the 7750 Series only.
6–2
7700 FAMILY SOFTWARE MANUAL
CPU INSTRUCTION EXECUTION SEQUENCE FOR
EACH ADDRESSING MODES
Variation of the execution cycles according to the accumulator used
ADC Instruction / Immediate addressing mode
<<When accumulator A is used>>
Mnemonic : ADC A,#1234H
Machine code : 6916 3416 12 16
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+3
DATA(CPU)
6916
123416
Op Code
Operand
<<When accumulator B is used>>
Mnemonic : ADC B,#1234H
Machine code : 4216 6916 34 16 12 16
2-cycle
φ CPU
AP(CPU)
PG
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
PC+4
DATA(CPU)
Not used
4216
Op Code
6916
123416
Op Code
Operand
7700 FAMILY SOFTWARE MANUAL
6–3
Implied
Instructions
:
CLC,
SEC,
TSX,
CLI,
SEI,
TXA,
CLM,
SEM,
TXS,
CLV,
TAD,
TXY,
DEX,
TAS,
TYA,
DEY,
TAX,
TYX
INX,
TAY,
INY,
TDA,
TDB,
TSB,
TXB,
TYB
Timing :
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op Code
DATA(CPU)
Next
Op Code
Not used
“H”
R/W(CPU)
Instructions
:
TBD,
TBS,
TBX,
TBY,
Timing :
φ CPU
AP(CPU)
PG
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
PC+2
Op Code
DATA(CPU)
Not used
Op Code
Not used
“H”
R/W(CPU)
6–4
7700 FAMILY SOFTWARE MANUAL
Next
Op Code
NOP,
TSA,
Implied
Instructions
:
XAB
Timing :
φ CPU
AP(CPU)
PG
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
PC+2
Op Code
DATA(CPU)
Op Code
Not used
Not used
Not used
Not used
Next
Op Code
“H”
R/W(CPU)
Instructions
:
STP,
WIT
Timing :
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op code
DATA(CPU)
Not used
Not used
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–5
Implied
Instructions
:
Timing
:
RTS
φ CPU
AP(CPU)
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
S+1
ADHADL
DATA(CPU)
Op Code
Not used
Not used
Next
Op Code
ADHADL
“H”
R/W(CPU)
Instructions
:
Timing
:
RTL
φ CPU
AP(CPU)
PG
PG
AHAL(CPU)
PC
PC+1
Op Code
DATA(CPU)
Not used
S+1
Not used
ADHADL
“H”
R/W(CPU)
6–6
ADP
00
7700 FAMILY SOFTWARE MANUAL
ADHADL
S+3
Not used
ADP
Next
Op Code
Implied
Instructions
:
Timing
:
RTI
φ CPU
AP(CPU)
PG
PG
AHAL(CPU)
PC
PC+1
Op Code
DATA(CPU)
“H”
00
S+1
Not used Not used
PG
S+3
S+2
PSHPSL
Not used
PCHPCL
(Stack)
(Stack)
S+5
Not used
PCHPCL
PG
Next
Op Code
(Stack)
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–7
Implied
Instructions
:
Timing
:
BRK
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
Op Code
DATA(CPU)
FFFF
PC+1
Operand
Not used
00
FFFC
FFFE
Not used
Not used
Not used
“H”
R/W(CPU)
00
S–2
Not
used
6–8
S–3
PC
S–4
Not used
PS
FFFA
Not used
ADHADL
ADHADL
Next
Op Code
7700 FAMILY SOFTWARE MANUAL
S
Not used
S–1
PG
Not
used
Immediate
Instructions
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC
m=0
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+3
Operand
mmnn
Op Code
DATA(CPU)
Next
Op Code
“H”
R/W(CPU)
When m=1, fetched operand at 2-nd cycle is 1-byte (nn).
Instructions
:
Timing
:
LDX,
LDY,
CPX,
CPY
x=0
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+3
Op Code
DATA(CPU)
Operand
mmnn
Next
Op Code
“H”
R/W(CPU)
When x=1, fetched operand at 2-nd cycle is 1-byte (nn).
7700 FAMILY SOFTWARE MANUAL
6–9
Immediate
Instructions
:
Timing
:
LDT
φ CPU
AP(CPU)
PG
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
PC+3
DATA(CPU)
Op Code
Not used
Op Code
Operand
nn
Not used
Next
Op Code
“H”
R/W(CPU)
Instructions
:
Timing
:
RLA
φ CPU
AP(CPU)
PG
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
PC+4
DATA(CPU)
Op Code
Not used
Op Code
Operand
mmnn
Not used
Not used
Not used
Next
Op Code
“H”
R/W(CPU)
This Figure is shown that shifted 1 bit. If shifted more than 2 bit, the cycle “
is repeated each shift number worth. When 0 bit shift(not shifted), the cycle
“
” is nothing.
When m=1, fetched operand at 4-th cycle is 1-byte (nn).
6–10
7700 FAMILY SOFTWARE MANUAL
”
Immediate
Instructions
:
Timing
:
SEP
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+2
Op Code
DATA(CPU)
Operand
nn
Next
Op Code
Not used
“H”
R/W(CPU)
Instructions
:
Timing
:
CLP
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
PC+1
Op Code
DATA(CPU)
PG
Operand
nn
?
Not used
PC+2
Not used
Next
Op Code
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–11
Immediate
Instructions
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
m=0
✽
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
Op Code
Not Used
PG
PC+2
Op Code
Operand
mmnn
PG
PC+2
Not Used
PC+3
Next
Op Code
“H”
R/W(CPU)
When m=1, fetched operand at 4-th cycle is 1-byte(nn).
(Note) The cycle number during ✽ is shown in following table
The contents
Instruction of division
DIV
—
The number of cycles(cycle)
m=0
39
m=1
23
Plus÷Plus
DIVS
MPY
Plus÷Minus
41
25
Minus÷Minus
Minus÷Plus
42
26
—
20
12
22
14
25
17
Plus✕Plus
MPYS
Minus✕Minus
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
6–12
7700 FAMILY SOFTWARE MANUAL
Immediate
Instructions
:
Timing
:
DIV,
DIVS* ( case of zero division )
φ CPU
AP(CPU)
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
DATA(CPU)
Op Code Not used Op Code
PG
PC+2
Operand
mmnn
00
FFFF
FFFE
S
Not used Not used Not used Not used Not used Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
00
S–1
S
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
00
00
FFFC
ADHADL
Not used ADHADL
Next
Op Code
When m=1, fetched operand at 4-th cycle is 1-byte(nn).
7700 FAMILY SOFTWARE MANUAL
6–13
Accumulator
Instructions
:
Timing
:
ASL,
DEC,
INC,
LSR,
ROL,
ROR
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
Next
Op Code
Not used
Op Code
“H”
R/W(CPU)
Instruction
:
Timing
:
ASR*, EXTZ*
φ CPU
AP(CPU)
PG
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
PC+2
Op Code
DATA(CPU)
Not used
Op Code
Not used
“H”
R/W(CPU)
6–14
7700 FAMILY SOFTWARE MANUAL
Not used
Next
Op Code
Accumulator
Instruction
:
Timing
:
EXTS*
φ CPU
AP(CPU)
PG
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
PC+2
DATA(CPU)
Op Code Not used Op Code Not used Not used Not used Not used Not used
Next
Op Code
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–15
Direct
Instruction
:
Timing
:
ADC,
ORA,
AND,
SBC
CMP,
CPX,
CPY,
EOR,
LDA,
LDX,
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
PC+1
Operand
dd
Op Code
DATA(CPU)
00
00 or 01
PG
DPR+dd
PC+2
Not used
Next
Op Code
DHDL
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
Instruction
:
Timing
:
LDM
DPRL≠0
φ CPU
AP(CPU)
PG
PG
PG
00
00 or 01
PG
AHAL(CPU)
PC
PC+1
PC+2
?
DPR+dd
PC+4
DATA(CPU)
Op Code
Operand
dd
Operand
mmnn
Not used
mmnn
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
When m=1, fetched operand at 3-rd cycle and data at 5-th cycle are 1-byte(nn).
6–16
7700 FAMILY SOFTWARE MANUAL
Next
Op Code
LDY,
Direct
Instruction
:
Timing
:
STA,
STX,
STY
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PC+1
Operand
dd
Op Code
00 or 01
PG
DPR+dd
PC+2
00
PG
Not used
A
Not used
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
Instruction
:
Timing
:
ASL,
DEC,
INC,
LSR,
ROL,
ROR
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
PC+1
Op Code
Operand
dd
Not used
00 or 01
PG
DPR+dd
PC+2
DHDL
Not used
Modified
DHDL
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
7700 FAMILY SOFTWARE MANUAL
6–17
Direct
Instruction
:
Timing
:
ASR*
DPRL≠0
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
PG
00
PC+2
Op Code Not used Op Code
Operand
Not used
dd
00 or 01
PG
DPR+dd
PC+3
D HD L
Not used
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
6–18
7700 FAMILY SOFTWARE MANUAL
Modified
DHDL
Next
Op Code
Direct
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
DPRL≠0
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op
Code
DATA(CPU)
Not
used
PG
00
PC+2
Op
Code
Operand
dd
00 or 01
DPR+
dd
Not
used
PG
DPR+dd
DH D L
Not used
PC+3
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
(Note) The cycle number during ✽ is shown in following table
The contents
Instruction of division
DIV
The number of cycles(cycle)
m=0
39
m=1
23
Plus÷Minus
Minus÷Minus
41
25
Minus÷Plus
42
26
20
12
22
14
25
17
—
Plus÷Plus
DIVS
MPY
—
Plus✕Plus
Minus✕Minus
MPYS
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
7700 FAMILY SOFTWARE MANUAL
6–19
Direct
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
DPRL≠0
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op Code Not used
DATA(CPU)
00
PG
00 or 01
PC+2
Op Code
FFFF
DPR+dd
Operand
Not used
dd
D HD L
FFFE
Not used Not used Not used Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
When DPRL=0, this cycle is nothing.
00 or 01
FFFE
Not used Not used
00
S–1
S
PG
S–2
Not used
S–3
PC
S–4
S–4
Not used
PS
00
FFFC
ADHADL
Not used ADHADL
“H”
6–20
00
7700 FAMILY SOFTWARE MANUAL
Next
Op Code
Direct Bit
Instruction
:
Timing
:
CLB,
SEB
DPRL≠0, m=0
φ CPU
AP(CPU)
PG
PG
PG
00
00 or 01
PG
AHAL(CPU)
PC
PC+1
PC+2
?
DPR+dd
PC+4
Op Code
DATA(CPU)
Operand
dd
Operand
mmnn
Not used
DHDL
Not used
Modified
DHDL
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
When m=1, fetched operands at 3-rd cycle is 1-byte (nn).
7700 FAMILY SOFTWARE MANUAL
6–21
Direct Indexed X
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
LDY,
ORA,
SBC
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
00
PC+1
Operand
dd
Op Code
DATA(CPU)
00 or 01
Not used
00, 01 or 02
PG
DPR+dd+X
PC+2
Not used
DHDL
Next
Op code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
Instruction
:
Timing
:
LDM
DPRL≠0
φ CPU
AP(CPU)
PG
PG
PG
00
00 or 01
00, 01 or 02
PG
AHAL(CPU)
PC
PC+1
PC+2
?
DPR+dd
DPR+dd+X
PC+4
Op Code
DATA(CPU)
Operand
dd
Operand
mmnn
Not used
Not used
mmnn
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
When m=1, fetched operand at 3-rd cycle and data at 6-th cycle are 1-byte(nn).
6–22
7700 FAMILY SOFTWARE MANUAL
Next
Op code
Direct Indexed X
Instruction
:
Timing
:
STA,
STY
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
00 or 01
PC+1
Op Code
DATA(CPU)
00
PG
Operand
dd
Not used
00, 01 or 02
PG
DPR+dd+X
PC+2
Next
Op Code
A
Not used
Not used
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
Instruction
:
Timing
:
ASL,
DEC,
INC,
LSR,
ROL,
ROR
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
00 or 01
PC+1
Op Code
Operand
dd
Not used
Not used
00,01 or 02
PG
DPR+dd+X
PC+2
DHDL
Not used
Modified
DHDL
Next
Op code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
7700 FAMILY SOFTWARE MANUAL
6–23
Direct Indexed X
Instruction
:
Timing
:
ASR*
DPRL≠0
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
PG
00
00 or 01
PC+2
Op Code Not used Op Code
Operand
Not used Not used
dd
00, 01 or 02
PG
DPR+dd+X
PC+3
DHDL
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
6–24
7700 FAMILY SOFTWARE MANUAL
Not used
Modified
Next
DHDL Op Code
Direct Indexed X
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
DPRL≠0
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op
Code
DATA(CPU)
Not
used
PG
00
00 or 01
PC+2
Op
Code
Operand
dd
Not
used
00 , 01 or 02
DPR+
dd+X
Not
used
DHDL
DPR+dd+X
Not used
PG
PC+3
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
(Note) The cycle number during ✽ is shown in following table
The contents
Instruction of division
DIV
DIVS
MPY
—
Plus÷Plus
Plus÷Minus
39
23
41
25
Minus÷Minus
Minus÷Plus
42
26
—
20
12
22
14
25
17
Plus✕Plus
MPYS
The number of cycles(cycle)
m=0
m=1
Minus✕Minus
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
7700 FAMILY SOFTWARE MANUAL
6–25
Direct Indexed X
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
DPRL≠0
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
PG
00 or 01
00
00, 01 or 02
PC+2
Op Code Not used Op Code
Operand
dd
DPR+dd+X
Not used Not used
D HD L
FFFF
Not Used Not used Not used Not used
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
00, 01 or 02
FFFF
FFFE
Not used Not used Not used
At DIVS instruction, this cycle is nothing.
00
S
S–1
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
“H”
6–26
7700 FAMILY SOFTWARE MANUAL
00
00
FFFC
ADHADL
Next
Not used ADHADL
Op Code
Direct Indexed Y
Instruction
:
Timing
:
LDX
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
00 or 01
PC+1
Operand
dd
Op Code
Not used
00, 01 or 02
PG
DPR+dd+Y
PC+2
Not used
DHDL
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
Instruction
:
Timing
:
STX
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
00 or 01
PC+1
Op Code
Operand
dd
Not used
Not used
00, 01 or 02
PG
DPR+dd+Y
PC+2
Not used
X
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
7700 FAMILY SOFTWARE MANUAL
6–27
Direct Indirect
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
PC+1
Operand
dd
Op Code
DATA(CPU)
00
00 or 01
DT
PG
DPR+dd
ADHADL
PC+2
Not used
ADHADL
DHDL
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
Instruction
:
Timing
:
STA
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
00
PG
PC+1
Op Code
Operand
dd
00 or 01
DT
PG
DPR+dd
ADHADL
PC+2
Not used
ADHADL
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
6–28
7700 FAMILY SOFTWARE MANUAL
Not used
A
Next
Op Code
Direct Indirect
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
DPRL≠0
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op
Code
DATA(CPU)
Not
used
PG
00
00 or 01
DPR+
dd
PC+2
Op
Code
Operand
dd
Not
used
DT
ADHADL
ADHADL DHDL
PG
ADHADL
Not used
PC+3
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
(Note) The cycle number during ✽ is shown in following table
The number of cycles(cycle)
Instruction The contents
of division
m=0
m=1
39
23
DIV
—
Plus÷Plus
Plus÷Minus
DIVS
Minus÷Plus
MPY
—
Plus✕Plus
Minus✕Minus
MPYS
41
25
42
26
20
12
22
14
25
17
Minus÷Minus
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
7700 FAMILY SOFTWARE MANUAL
6–29
Direct Indirect
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
PG
00 or 01
00
00 or 01
PC+2
Op Code Not used Op Code
operand
dd
DT
ADHADL
Not used ADHADL
DHDL
FFFF
Not used Not used Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
When DPRL =0, this cycle is nothing.
DT
FFFF
00
FFFE
Not used Not used Not used
6–30
S
S–1
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
7700 FAMILY SOFTWARE MANUAL
00
00
FFFC
ADHADL
Next
Not used ADHADL
Op Code
Direct Indexed X Indirect
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
00 or 01
PC+1
Op Code
Operand
dd
Not used
00, 01 or 02
DT
PG
DPR+dd+X
ADHADL
PC+2
ADHADL
Not used
DHD L
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
Instruction
:
Timing
:
STA
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
00 or 01
PC+1
Op Code
Operand
dd
Not used
00,01 or 02
DT
PG
DPR+dd
+X
ADHADL
PC+2
Not used
ADHADL
Not used
A
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
7700 FAMILY SOFTWARE MANUAL
6–31
Direct Indexed X Indirect
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
DPRL≠0
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op
Code
DATA(CPU)
Not
used
PG
00
00 or 01
PC+2
Op
Code
Operand
dd
Not
used
00 , 01
or 02
DPR+
dd+X
Not
used
DT
ADHADL
ADHADL
DHDL
PG
ADHADL
Not used
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
(Note) The cycle number during ✻ is shown in following table
The contents
Instruction of division
DIV
The number of cycles(cycle)
m=0
39
m=1
23
Plus÷Minus
Minus÷Minus
41
25
Minus÷Plus
42
26
20
12
22
14
25
17
—
Plus÷Plus
DIVS
MPY
—
Plus✕Plus
Minus✕Minus
MPYS
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
6–32
7700 FAMILY SOFTWARE MANUAL
PC+3
Next
Op Code
Direct Indexed X Indirect
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
PG
00
00 or 01
00, 01
or 02
DPR
+dd
+X
PC+2
Op Code Not used Op Code
Operand
dd
DT
ADHADL
Not used Not used ADHADL
DHDL
Not used Not used
Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
When DPRL =0, this cycle is nothing.
DT
ADHADL
FFFF
00
S
FFFE
Not used Not used Not used Not used
S–1
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
00
00
FFFC
ADHADL
Next
Not used ADHADL
Op Code
“H”
7700 FAMILY SOFTWARE MANUAL
6–33
Direct Indirect Indexed Y
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
00 or 01
PC+1
Op Code
DATA(CPU)
00
PG
Operand
dd
DPR+dd
Not used
DT or DT+1
PG
ADHADL+Y
PC+2
DT
Not used
ADHADL
DHDL
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
Instruction
:
Timing
:
STA
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
00 or 01
DPR+dd
PC+1
Op Code
DT
Operand
dd
Not used
ADHADL
Not used
DT or DT+1
PG
ADHADL+Y
PC+2
Not used
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
6–34
7700 FAMILY SOFTWARE MANUAL
A
Next
Op Code
Direct Indirect Indexed Y
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
PG
PC+1 PC+1
Op
Code
DATA(CPU)
PG
Not
used
Op
Code
00
00 or
01
DPR+dd
PC+2
Operand
dd
Not
used
ADH
ADL
DT or DT+1
DT
ADH
ADL
+Y
Not
used
D HD L
ADHADL+Y
Not used
PG
PC+3
Next
Op
Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
(Note) The cycle number during ✽ is shown in following table
Instruction The contents
of division
DIV
The number of cycles(cycle)
m=0
m=1
39
23
Plus÷Minus
Minus÷Minus
41
25
Minus÷Plus
42
26
20
12
22
14
25
17
—
Plus÷Plus
DIVS
MPY
—
Plus✕Plus
Minus✕Minus
MPYS
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
7700 FAMILY SOFTWARE MANUAL
6–35
Direct Indirect Indexed Y
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
PG
00
00 or 01
PC+2
Op Code Not used Op Code
Operand
dd
DT or DT+1
DT
DPR+dd
ADHADL+Y
Not used ADHADL Not used
DHDL
FFFF
Not used Not used Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
When DPRL =0, this cycle is nothing.
00
DT or DT+1
FFFF
FFFE
Not used Not used Not used
S
S–1
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
“H”
6–36
7700 FAMILY SOFTWARE MANUAL
00
00
FFFC
ADHADL
Not used ADHADL
Next
Op Code
Direct Indirect Long
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
00 or 01
PC+1
DPR+dd
Operand
dd
Op Code
00 or 01
Not used
ADHADL
00 or 01
ADP
PG
DPR+dd
+2
ADHADL
PC+2
Not used
ADP
DHDL
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
Instruction
:
Timing
:
STA
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
00 or 01
DPR+dd
PC+1
Op Code
00 or 01
Operand
dd
Not used
ADHADL
00 or 01
DPR+dd
+2
Not used
PG
ADP
ADHADL
ADP
Not used
PC+2
A
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
7700 FAMILY SOFTWARE MANUAL
6–37
Direct Indirect Long
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
DPRL ≠ 0
✽
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op
Code
DATA(CPU)
Not
used
PG
Op
Code
00
00 or
01
DPR+dd
PC+2
Operand
dd
00 or
01
Not
used
ADH
ADL
00 or
01
DPR
+dd
+2
Not
used
ADP
ADH
ADL
ADP DHDL
PG
ADHADL
Not used
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
(Note) The cycle number during ✽ is shown in following table
Instruction
DIV
The contents The number of cycles(cycle)
of division
m=0
m=1
—
39
23
41
25
Plus÷Plus
Plus÷Minus
DIVS
MPY
Minus÷Minus
Minus÷Plus
42
26
—
20
12
22
14
25
17
Plus✕Plus
MPYS
Minus✕Minus
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
6–38
7700 FAMILY SOFTWARE MANUAL
PC+3
Next
Op
Code
Direct Indirect Long
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
φ C PU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op
Code
DATA(CPU)
Not
used
00
PG
00 or 01 00 or 01 00 or 01
PC+2
Op
Code
DPR
+dd
+2
DPR+dd
Operand
dd
Not
used
ADP
Not
used
ADHADL
ADHADL
ADP
Not
used
DHDL
Not
used
Not
used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
When DPRL=0, this cycle is nothing.
00
ADP
ADHADL
Not
used
FFFF
Not
used
FFFE
Not
used
S
Not
used
S–1
PG
S–2
Not
used
S–3
PC
S–4
S–4
Not
used
7700 FAMILY SOFTWARE MANUAL
PS
00
00
FFFC
ADHADL
Not
used
Next
ADHADL Op Code
6–39
Direct Indirect Long Indexed Y
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
00 or 01
00 or 01
00 or 01
DPR+dd
PC+1
Operand
dd
Op Code
DATA(CPU)
00
Not used
ADHADL
ADP
DPR+dd+2
Not used
ADP
ADP or
ADP+1
PG
ADHADL
+Y
PC+2
Not used
Next
Op Code
DHDL
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
Instruction
:
Timing
:
STA
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
00
PG
00 or 01
PC+1
Op Code
Operand
dd
00 or 01
00 or 01
DPR+dd+2
DPR+dd
Not used
ADHADL
ADP
Not used
ADP
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
6–40
7700 FAMILY SOFTWARE MANUAL
ADP or ADP+1
PG
ADHADL+Y
PC+2
Not used Not used
A
Next
Op Code
Direct Indirect Long Indexed Y
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
DPRL≠0
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
PG
PC+1 PC+1
Op
Code
DATA(CPU)
PG
Not
used
Op
Code
00 or
01
00
00 or
01
DPR+dd
PC+2
Operand
dd
00 or
01
ADH
Not
used @ ADL
Not
used
ADP or ADP+1
ADP
DPR
+dd
+2
@
ADP
Not
used
ADH
ADL
+Y
ADHADL+Y
DHDL
Not used
PG
PC+3
Next
Op
Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
(Note) The cycle number during ✽ is shown in following table
The contents The number of cycles(cycle)
Instruction of division
m=0
m=1
DIV
—
39
23
41
25
Minus÷Plus
42
26
—
20
12
22
14
25
17
Plus÷Plus
Plus÷Minus
DIVS
MPY
Minus÷Minus
Plus✕Plus
MPYS
Minus✕Minus
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
7700 FAMILY SOFTWARE MANUAL
6–41
Direct Indirect Long Indexed Y
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
00
PG
00 or 01 00 or 01 00 or 01
PC+2
Op Code Not used Op Code
DPR+dd
ADP
ADP or ADP+1
DPR+dd+2
Operand
Not used ADHADL Not used
dd
ADP
ADHADL+Y
DHDL
Not used
Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
When DPRL=0, this cycle is nothing.
00
ADP or ADP+1
ADHADL+Y
FFFF
FFFE
Not used Not used Not used Not used Not used
S
S–1
PG
S–2
Not used
S–3
PC
“H”
6–42
7700 FAMILY SOFTWARE MANUAL
S–4
S–4
Not used
PS
00
00
FFFC
ADHADL
Next
Not used ADHADL Op Code
Absolute
Instruction
:
Timing
:
ADC,
ORA,
AND,
SBC
CMP,
CPX,
CPY,
EOR,
LDA,
LDX,
LDY,
φ CPU
AP(CPU)
PG
PG
DT
PG
AHAL(CPU)
PC
PC+1
hhll
PC+3
Operand
hhll
Op Code
DATA(CPU)
Next
Op Code
DHDL
“H”
R/W(CPU)
Instruction
:
Timing
:
LDM
φ CPU
AP(CPU)
PG
PG
PG
DT
PG
AHAL(CPU)
PC
PC+1
PC+3
hhll
PC+5
Op Code
DATA(CPU)
Operand
hhll
Operand
mmnn
mmnn
Next
Operand
“H”
R/W(CPU)
When m=1, fetched operand at 3-rd cycle and data at 4-th cycle are 1-byte (nn).
7700 FAMILY SOFTWARE MANUAL
6–43
Absolute
Instruction
:
Timing
:
STA,
STX,
STY
φ CPU
AP(CPU)
PG
PG
DT
PG
AHAL(CPU)
PC
PC+1
hhll
PC+3
DATA(CPU)
Operand
hhll
Op Code
Next
Op Code
A
Not used
“H”
R/W(CPU)
Instruction
:
Timing
:
ASL,
DEC,
INC,
LSR,
ROL,
ROR
φ CPU
AP(CPU)
PG
PG
DT
PG
AHAL(CPU)
PC
PC+1
hhll
PC+3
Op Code
DATA(CPU)
Operand
hhll
DHDL
Not used
“H”
R/W(CPU)
6–44
7700 FAMILY SOFTWARE MANUAL
New DHDL
Next
Op Code
Absolute
Instruction
:
Timing
:
ASR*
φ CPU
AP(CPU)
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
Op Code
DATA(CPU)
Not used
Op Code
Operand
hhll
DT
PC+4
hhll
DHDL
PG
Not used
New
DHDL
Next
Op Code
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–45
Absolute
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
m=1
φ CPU
AP(CPU)
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
DATA(CPU)
Op Code
Not used
Op Code
DT
Operand
hhll
hhll
PG
hhll
DHDL
Not used
“H”
R/W(CPU)
(Note) The cycle number during ✽ is shown in following table
Instruction The contents
of division
DIV
—
The number of cycles(cycle)
m=0
m=1
39
23
41
25
42
26
20
12
22
14
25
17
Plus÷Plus
DIVS
Plus÷Minus
Minus÷Minus
Minus÷Plus
MPY
—
Plus✕Plus
MPYS
Minus✕Minus
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
6–46
7700 FAMILY SOFTWARE MANUAL
PC+4
Next
Op Code
Absolute
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
φ CPU
AP(CPU)
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
DATA(CPU)
Op Code Not used Op Code
DT
FFFF
hhll
Operand
hhll
DHDL
00
FFFE
S
Not used Not used Not used Not used Not used Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
00
S
S–1
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
00
00
FFFC
ADHADL
Not used ADHADL
Next
Op Code
“H”
7700 FAMILY SOFTWARE MANUAL
6–47
Absolute
Instruction
:
Timing
:
JMP
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
hhll
DATA(CPU)
Op Code
Operand
hhll
Next
Op Code
“H”
R/W(CPU)
Instruction
:
Timing
:
JSR
φ CPU
AP(CPU)
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
S–1
hhll
Op Code
DATA(CPU)
Operand
hhll
Not used
PCHPCL
“H”
R/W(CPU)
6–48
7700 FAMILY SOFTWARE MANUAL
Next
Op Code
Absolute Bit
Instruction
:
Timing
:
CLB,
SEB
m=0
φ CPU
AP(CPU)
PG
PG
PG
DT
PG
AHAL(CPU)
PC
PC+1
PC+3
hhll
PC+5
Op Code
DATA(CPU)
Operand
hhll
Operand
mmnn
DHDL
Not used
New DHDL
Next
Op Code
“H”
R/W(CPU)
When m=1, fetched operand at 3-rd cycle is 1-byte (nn).
7700 FAMILY SOFTWARE MANUAL
6–49
Absolute Indexed X
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
LDY,
ORA,
SBC
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
DT or DT+1
PG
hhll+X
PC+3
PC+1
Operand
hhll
Op Code
DATA(CPU)
DT
Not used
Next
Op Code
DHDL
“H”
R/W(CPU)
Instruction
:
Timing
:
LDM
φ CPU
AP(CPU)
PG
PG
AHAL(CPU)
PC
PC+1
Op Code
DATA(CPU)
PG
DT
PC+3
Operand
hhll
Operand
mmnn
DT or DT+1
PG
hhll+X
PC+5
Not used
“H”
R/W(CPU)
When m=1, fetched operand at 3-rd cycle and data at 5-th cycle are 1-byte (nn).
6–50
7700 FAMILY SOFTWARE MANUAL
mmnn
Next
Op Code
Absolute Indexed X
Instruction
:
Timing
:
ASL,
DEC,
INC,
LSR,
ROL,
ROR
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
DT
DT or DT+1
PG
hhll+X
PC+3
PC+1
Operand
hhll
Op Code
Not used
DHDL
Not used
New DHDL
Next
Op Code
“H”
R/W(CPU)
Instruction
:
Timing
:
ASR*
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PG
PC+2
Op Code Not used Op Code
DATA(CPU)
DT
Operand
Not used
hhll
DHDL
DT or DT+1
PG
hhll+X
PC+4
Not used
New
DHDL
Next
Op Code
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–51
Absolute Indexed X
Absolute Indexed Y
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op
Code
DATA(CPU)
Not
used
PG
DT
DT or DT+1
hhll+
X(Y)
PC+2
Op
Code
Operand
hhll
Not
used
hhll+X(Y)
DHDL
Not used
“H”
R/W(CPU)
(Note) The cycle number during ✽ is shown in following table
Instruction The contents
of division
DIV
DIVS
m=0
m=1
—
Plus÷Plus
39
23
Plus÷Minus
41
25
Minus÷Minus
Minus÷Plus
MPY
—
Plus✕Plus
MPYS
The number of cycles(cycle)
Minus✕Minus
Plus✕Minus
Minus✕Plus
42
26
20
12
22
14
25
17
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
6–52
7700 FAMILY SOFTWARE MANUAL
PG
PC+4
Next
Op Code
Absolute Indexed X
Absolute Indexed Y
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
PG
DT or DT+1
DT
PC+2
Op Code Not used Op Code
hhll+X(Y)
Operand
Not used
hhll
DHDL
FFFF
FFFE
Not used Not used Not used Not used Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
00
DT or DT+1
FFFE
Not used
S
S–1
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
00
00
FFFC
ADHADL
Not used ADHADL
7700 FAMILY SOFTWARE MANUAL
Next
Op Code
6–53
Absolute Indexed X
Absolute Indexed Y
Instruction
:
Timing
:
STA
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
DT
PC+1
Op Code
Operand
hhll
Not used
DT or DT+1
PG
hhll+X(Y)
PC+3
Not used
“H”
R/W(CPU)
6–54
7700 FAMILY SOFTWARE MANUAL
A
Next
Op Code
Absolute Indexed Y
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
LDX,
ORA,
SBC
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
DT
PC+1
Op Code
Operand
hhll
DT or DT+1
PG
hhll+Y
PC+3
Not used
DHDL
Next
Op Code
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–55
Absolute Long
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC
φ CPU
AP(CPU)
PG
PG
PG
pp
PG
AHAL(CPU)
PC
PC+1
PC+3
hhll
PC+4
DATA(CPU)
Operand
hhll
Op Code
Operand
pp
DHDL
Next
Op Code
“H”
R/W(CPU)
Instruction
:
Timing
:
STA
φ CPU
AP(CPU)
PG
PG
PG
pp
PG
AHAL(CPU)
PC
PC+1
PC+3
hhll
PC+4
Op Code
DATA(CPU)
Operand
hhll
Operand
pp
Not used
“H”
R/W(CPU)
6–56
7700 FAMILY SOFTWARE MANUAL
A
Next
Op Code
Absolute Long
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
φ CPU
AP(CPU)
PG
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
PC+4
Op
Code
DATA(CPU)
Not
used
Op
Code
pp
hhll
Operand Operand
hhll
pp
DHDL
PG
hhll
Not used
PC+5
Next
Op Code
“H”
R/W(CPU)
(Note) The cycle number during ✽ is shown in following table
Instruction The contents
of division
DIV
DIVS
MPY
m=0
m=1
—
39
23
Plus÷Plus
Plus÷Minus
41
25
Minus÷Minus
Minus÷Plus
42
26
—
20
12
22
14
25
17
Plus✕Plus
MPYS
The number of cycles(cycle)
Minus✕Minus
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
7700 FAMILY SOFTWARE MANUAL
6–57
Absolute Long
Instruction
:
Timing
:
DIV ,
DIVS*( case of 0 division )
φ CPU
AP(CPU)
PG
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
PC+4
Op Code Not used Op Code
DATA(CPU)
pp
hhll
Operand Operand
hhll
pp
DHDL
FFFF
FFFE
Not used Not used Not used Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
pp
FFFE
Not used
6–58
00
S–1
S
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
00
00
FFFC
ADHADL
Next
Not used ADHADL Op Code
7700 FAMILY SOFTWARE MANUAL
Not used
Absolute Long
Instruction
:
Timing
:
JMP
φ CPU
AP(CPU)
PG
PG
PG
pp
AHAL(CPU)
PC
PC+1
PC+3
hhll
Operand
hhll
Op Code
DATA(CPU)
Operand
pp
Next
Op Code
“H”
R/W(CPU)
Instruction
:
Timing
:
JSR
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+3
Op Code
DATA(CPU)
Operand
hhll
00
pp
S
Operand
pp
PG
S–2
Not used
hhll
PCHPCL
Next
Op Code
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–59
Absolute Long Indexed X
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC
φ CPU
AP(CPU)
PG
PG
AHAL(CPU)
PC
PC+1
pp
PC+3
Operand
hhll
Op Code
DATA(CPU)
PG
Operand
pp
pp or pp+1
PG
hhll+X
PC+4
Not used
DHDL
Next
Op Code
“H”
R/W(CPU)
Instruction
:
Timing
:
STA
φ CPU
AP(CPU)
PG
PG
AHAL(CPU)
PC
PC+1
DATA(CPU)
Op Code
PG
pp
PC+3
Operand
hhll
Operand
pp
Not used
“H”
R/W(CPU)
6–60
7700 FAMILY SOFTWARE MANUAL
pp or pp+1
PG
hhll+X
PC+4
Not used
A
Next
Op Code
Absolute Long Indexed X
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
φ CPU
AP(CPU)
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
Op
Code
DATA(CPU)
Not
used
Op
Code
PG
Operand
hhll
pp
PC+4
Operand
pp
pp or pp+1
hhll+X
Not
used
DHDL
hhll+X
Not used
PG
PC+5
Next
Op Code
“H”
R/W(CPU)
(Note) The cycle number during ✽ is shown in following table
Instruction The contents
of division
DIV
—
The number of cycles(cycle)
m=0
m=1
39
23
41
25
Plus÷Plus
DIVS
MPY
Plus÷Minus
Minus÷Minus
Minus÷Plus
42
26
—
Plus✕Plus
20
12
22
14
25
17
Minus✕Minus
MPYS
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
7700 FAMILY SOFTWARE MANUAL
6–61
Absolute Long Indexed X
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
φ CPU
AP(CPU)
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
DATA(CPU)
Op Code Not used
Op Code
PG
pp
pp or pp+1
PC+4
Operand Operand
hhll
pp
hhll+X
Not used
DHDL
FFFF
Not used Not used Not used
FFFE
Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
pp or pp+1
FFFE
Not used Not used
6–62
00
S–1
S
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
00
00
FFFC
ADHADL
Not used ADHADL
7700 FAMILY SOFTWARE MANUAL
Next
Op Code
Absolute Indirect
Instruction
:
Timing
:
JMP
φ CPU
AP(CPU)
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
hhll
ADHADL
DATA(CPU)
Op Code
operand
hhll
ADHADL
Next
Op Code
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–63
Absolute Indirect Long
Instruction
:
Timing
:
JMP
φ CPU
AP(CPU)
PG
PG
AHAL(CPU)
PC
PC+1
Op Code
DATA(CPU)
PG
PG or PG+1
hhll
Operand
hhll
ADHADL
PG or PG+1
ADP
hhll+2
ADHADL
Not used
“H”
R/W(CPU)
6–64
7700 FAMILY SOFTWARE MANUAL
ADP
Next
Op Code
Absolute Indexed X Indirect
Instruction
:
Timing
:
JMP
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
PC+1
Operand
hhll
Op Code
DATA(CPU)
PG
PG or PG+1
PG or PG+1
hhll+X
ADHADL
Not used
Next
Op Code
ADHADL
“H”
R/W(CPU)
Instruction
:
Timing
:
JSR
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
PG
PC+1
Op Code
Operand
hhll
PG or PG+1
00
PG
hhll+X
S–1
ADHADL
Not used
ADHADL
PCHPCL
Next
Op Code
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–65
Stack
Instruction
:
Timing
:
PEA
φ CPU
AP(CPU)
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
S–1
PC+3
Operand
mmnn
Op Code
DATA(CPU)
Not used
Next
Op Code
mmnn
“H”
R/W(CPU)
Instruction
:
Timing
:
PEI
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
PC+1
Op Code
DATA(CPU)
00
Operand
nn
00 or 01
00
PG
DPR+nn
S–1
PC+2
Not used
DHDL
“H”
R/W(CPU)
6–66
7700 FAMILY SOFTWARE MANUAL
DHDL
Next
Op Code
Stack
Instruction
:
Timing
:
PER
φ CPU
AP(CPU)
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
S–1
PC+3
DATA(CPU)
Op Code
Operand
mmnn
Not used
Not used
PC+mmnn
Next
Op Code
“H”
R/W(CPU)
Instruction
:
Timing
:
PHA,
PHD,
PHP,
PHX,
PHY
φ CPU
AP(CPU)
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
S–1
PC+1
Op Code
DATA(CPU)
Not used
Not used
A
Next
Op Code
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–67
Stack
Instruction
:
Timing
:
PHB
φ CPU
AP(CPU)
PG
PG
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
S–1
PC+2
DATA(CPU)
Op Code
Not used
Op Code
Not used
“H”
R/W(CPU)
Instruction
:
Timing
:
PHG,
PHT
φ CPU
AP(CPU)
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
S
PC+1
Op Code
DATA(CPU)
Not used
PG
Next
Op Code
“H”
R/W(CPU)
6–68
7700 FAMILY SOFTWARE MANUAL
Not used
B
Next
Op Code
Stack
Instruction
:
Timing
:
PLA,
PLD,
PLX,
PLY
φ CPU
AP(CPU)
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
S+1
PC+1
Not used
Op Code
DATA(CPU)
Not used
A
Next
Op Code
(Stack)
“H”
R/W(CPU)
Instruction
:
Timing
:
PLB
φ CPU
AP(CPU)
PG
PG
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
PC+1
PC+2
S+1
PC+2
DATA(CPU)
Op Code
Not used
Op Code
Not used
Not used
B
Next
Op Code
(Stack)
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–69
Stack
Instruction
:
Timing
:
PLP
φ CPU
AP(CPU)
PG
PG
00
PG
AHAL(CPU)
PC
PC+1
S+1
PC+1
Op Code
DATA(CPU)
Not used
Not used
PS
Next
Op Code
Not used
(Stack)
“H”
R/W(CPU)
Instruction
:
Timing
:
PLT
φ CPU
AP(CPU)
PG
PG
AHAL(CPU)
PC
PC+1
Op Code
DATA(CPU)
“H”
Not used
00
DL
S+1
Not used
DT
(Stack)
R/W(CPU)
6–70
PG
7700 FAMILY SOFTWARE MANUAL
PC+1
Not used
Next
Op Code
Stack
Instruction
:
Timing
:
PSH
A
B
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
PC+1
S
Op Code Operand
DATA(CPU)
00
nn
Not
used
S
Not
used
S
Not
used
S–1
00
S–2
Not
used
S–2
Not
used
A
S–3
Not
used
B
“H”
R/W(CPU)
X
Y
00
00
S–4
S–4
Not
used
B
S–5
Not
used
DT
00
S–6
S–6
Not
used
X
S–7
Not
used
PG
S–10
00
S–11
DT
S–11
Not
used
00
S–8
S–8
Not
used
Y
S–9
Not
used
S–10
DPR
Not
used
PS
00
Not
used
DPR
S–12
PG
S–12
Not
used
00
PG
S–13
PC+2
Not
used
PS
Next
Op Code
(Note) This figure is an example pushed all the registers by PSH instruction. If any register is
not pushed, its cycle “
” is nothing.
7700 FAMILY SOFTWARE MANUAL
6–71
Stack
Instruction
:
Timing
:
PUL
PS
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
PC+1
Op Code
Operand
nn
00
S+1
S+1
Not
used
Not
used
S+1
Not
used
S+1
S+2
Not
used
S+3
Not
used
PS
S+3
Not
used
Not
used
“H”
R/W(CPU)
DT
00
DT
S+3
Not
used
00
S+3
S+4
Not
used
DT
Not
used
Not
used
S+6
Not
used
S+10
Not
used
Not
used
Y
00
S+11
B
S+8
Not
used
A
00
S+10
S+7
Not
used
B
S+9
X
S+6
Not
used
DPR
00
Not
used
00
S+5
S+4
X
S+8
Y
DPR
S+12
Not
used
S+12
Not
used
PG
S+13
A
S+14
Not
used
PC+2
Not
used
Next
Op Code
(Note) This figure is an example pushed all the registers by PUL instruction. If any register is
not pushed, its cycle “
” is nothing.
6–72
7700 FAMILY SOFTWARE MANUAL
Relative
Instruction
:
Timing
:
BRA
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
PG
PG or PG+1
PC+rr
PC+1
Op Code
Operand
rr
Not used
Not used
Next
Op Code
“H”
R/W(CPU)
Instruction
:
Timing
:
BCC,
BCS,
BEQ,
BMI,
BNE,
BPL,
BVC,
BVS
Branched
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PC+1
Op Code
DATA(CPU)
PG
PG
Operand
rr
Not used
Not used
PG or PG+1
PC+rr
Not used
Not used
Next
Op Code
“H”
R/W(CPU)
When not branch, this cycle is nothing.
7700 FAMILY SOFTWARE MANUAL
6–73
Direct Bit Relative
Instruction
:
Timing
:
BBC,
BBS
DPRL≠0, m=0, Branched
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
PC+1
Op Code
DATA(CPU)
00
Operand
dd
00 or 01
PG
DPR
+dd
PC+2
Not
used
DHDL
PG
PG
PCHPCL
+rr
PC+4
Operand Operand
mmnn
rr
Not
used
PG or
PG+1
Not
used
Not
used
Next
Op Code
“H”
R/W(CPU)
When DPRL=0, this cycle is nothing.
When not branch, this cycle is nothing.
When m=1, fetched operand at 5-th cycle is 1-byte (nn).
6–74
7700 FAMILY SOFTWARE MANUAL
Absolute Bit Relative
Instruction
:
Timing
:
BBC,
BBS
m=0, Branched
φ CPU
AP(CPU)
PG
PG
PG
PG
AHAL(CPU)
PC
PC+1
hhll
PC+3
DATA(CPU)
Op Code
Operand
hhll
DHDL
PG
PG
PC+5
Operand Operand
mmnn
rr
Not
used
PG or
PG+1
PC+rr
Not
used
Not
used
Next
Op Code
“H”
R/W(CPU)
When not branch, this cycle is nothing.
When m=1, fetched operand at 4-th cycle is 1-byte (nn).
7700 FAMILY SOFTWARE MANUAL
6–75
Stack Pointer Relative
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
00 or 01
PG
S+rr
PC+2
PC+1
Operand
rr
Op Code
DATA(CPU)
00
Not used
DHDL
Next
Op Code
“H”
R/W(CPU)
Instruction
:
Timing
:
STA
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
PC+1
Op Code
Operand
rr
Not used
00 or 01
PG
S+rr
PC+2
Not used
“H”
R/W(CPU)
6–76
7700 FAMILY SOFTWARE MANUAL
A
Next
Op Code
Stack Pointer Relative
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op
Code
DATA(CPU)
Not
used
PG
00
00 or 01
PC+2
Op
Code
Operand
rr
S+rr
Not
used
PG
S+rr
DHDL
Not used
PC+3
Next
Op Code
“H”
R/W(CPU)
(Note) The cycle number during ✽ is shown in following table
The contents
Instruction of division
DIV
—
Plus÷Plus
Plus÷Minus
DIVS
—
Plus✕Plus
MPYS
m=0
39
m=1
23
41
25
42
26
20
12
22
14
25
17
Minus÷Minus
Minus÷Plus
MPY
The number of cycles(cycle)
Minus✕Minus
Plus✕Minus
Minus✕Plus
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
7700 FAMILY SOFTWARE MANUAL
6–77
Stack Pointer Relative
Instruction
:
Timing
:
DIV,
DIVS* ( case of 0 division )
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
PG
00 or 01
PC+2
Op Code Not used Op Code
DATA(CPU)
00
Operand
rr
S+rr
Not used
DHDL
FFFF
FFFE
Not used Not used Not used Not used Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
00 or 01
FFFE
S
Not used
6–78
00
S–1
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
00
00
FFFC
ADHADL
Next
Not used ADHADL
Op Code
7700 FAMILY SOFTWARE MANUAL
Stack Pointer Relative Indirect Indexed Y
Instruction
:
Timing
:
ADC,
AND,
CMP,
EOR,
LDA,
ORA,
SBC
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
00
00 or 01
DT
PC+1
Operand
rr
Op Code
S+rr
ADHADL
Not used
DT or DT+1
PG
ADHADL+Y
PC+2
Next
Op Code
Not used
DHDL
DT or DT+1
PG
ADHADL+Y
PC+2
“H”
R/W(CPU)
Instruction
:
Timing
:
STA
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
DATA(CPU)
PG
Op Code
00
00 or 01
S+rr
PC+1
Operand
rr
DT
Not used
ADHADL
Not used Not used
A
Next
Op Code
“H”
R/W(CPU)
7700 FAMILY SOFTWARE MANUAL
6–79
Stack Pointer Relative Indirect Indexed Y
Instruction
:
Timing
:
DIV,
DIVS*, MPY,
MPYS*
✽
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
Op
Code
DATA(CPU)
Not
used
PG
00
00 or 01
PC+2
Op
Code
Operand
rr
DT
DT or DT+1
ADH
ADL
+Y
S+rr
Not
used
ADHADL
Not
used
DHDL
ADHADL+Y
Not used
“H”
R/W(CPU)
(Note) The cycle number during ✽ is shown in following table
The number of cycles(cycle)
Instruction The contents
of division
m=0
m=1
DIV
—
39
23
41
25
42
26
Plus÷Plus
DIVS
Plus÷Minus
Minus÷Minus
Minus÷Plus
MPY
MPYS
—
20
12
Plus✕Plus
Minus✕Minus
22
14
Plus✕Minus
Minus✕Plus
25
17
• The contents of AHAL(CPU) during ✽ of the DIVS instruction is undefined.
• When the multiplier and the multiplicand is different sign at the MPYS instruction, the contents of
AHAL(CPU) of the last 3 cycles during ✽ is undefined.
6–80
7700 FAMILY SOFTWARE MANUAL
PG
PC+3
Next
Op Code
Stack Pointer Relative Indirect Indexed Y
Instruction
:
Timing
:
DIV ,
DIVS*( case of 0 division )
φ CPU
AP(CPU)
PG
PG
PG
AHAL(CPU)
PC
PC+1
PC+1
DATA(CPU)
00
PG
Op Code Not used Op Code
00 or 01
DT
DT or DT+1
PC+2
S+rr
ADHADL+Y
Operand
rr
Not used ADHADL Not used
DHDL
FFFF
Not used Not used Not used Not used
“H”
R/W(CPU)
At DIVS instruction, this cycle is nothing.
00
DT or DT+1
FFFF
FFFE
Not used Not used Not used
S
S–1
PG
S–2
Not used
S–3
PC
S–4
Not used
S–4
PS
7700 FAMILY SOFTWARE MANUAL
00
00
FFFC
ADHADL
Not used ADHADL
Next
Op Code
6–81
Block Transfer
Instruction
:
Timing
:
MVN
● The transfer of even byte
Repeat this cycle
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
dd
Source Bank ss
ss
PC+1
PC+2
dd
DATA(CPU)
PG
Op Code (Destination
Bank)
Not
used
ss
(Source
Bank)
Not
used
?
Not
used
X
Not
used
?
DHDL
Not
used
Not
used
“H”
R/W(CPU)
Destination Bank dd
Y
Not
used
DHDL
?
Not
used
PG
PC+3
Not
used
Next
Op Code
(Note) This figure is shown that transferred the 2-bytes data. If transferred more than 2-bytes
data, the cycle “
” is repeated each 2-bytes.
The CPU instruction execution sequence is identical regardless of whether the transfer
start address is even or odd.
6–82
7700 FAMILY SOFTWARE MANUAL
Block Transfer
Instruction
:
Timing
:
MVN
● The transfer of odd byte
Repeated this cycle
φ CPU
AP(CPU)
PG
AHAL(CPU)
PC
PG
dd
ss
PC+1
Source Bank ss
PC+2
dd
DATA(CPU)
PG
Not
used
Op Code (Destination
Bank)
ss
(Source
Bank)
X+
2(n–1)
?
Not
used
Not
used
Not
used
DHDL
?
Not
used
Not
used
“H”
R/W(CPU)
Transfer last 1-byte
Destination Bank dd
Y+2(n–1)
Not
used
DHDL
?
Not
used
Not
used
ss
dd
PG
X+2n
Y+2n
PC+3
DHDL
Not
used
DL
Next
Op Code
(Note) This figure is shown that transferred the 2-bytes. If transferred more than 2-bytes data,
the cycle “
” is repeated each 2-bytes.
The CPU instruction execution sequence is identical regardless of whether the transfer
start address is even or odd. The transfer of the last byte is performed by reading 2 byte
and writing 1 byte.
7700 FAMILY SOFTWARE MANUAL
6–83
Block Transfer
Instruction
:
Timing
:
MVP
● The transfer of even byte
Repeated this cycle
φ CPU
AP(CPU)
PG
PG
dd
PG
AHAL(CPU)
PC
PC+1
Y
PC+2
dd
DATA(CPU)
Op Code (Destination
Bank)
Not
used
ss
X
ss
?
Not
used
(Source
Bank)
Source Bank ss
Not
used
Not
used
X–1
Not
used
DHDL
Not
used
“H”
R/W(CPU)
Destination Bank dd
Y–1
Not
used
DHDL
Destination
Bank
PG
?
PC+3
?
Not
used
Not
used
Not
used
Not
used
Next
Op Code
(Note) This figure is shown that transferred the 2-bytes data. If transferred more than 2-bytes,
the cycle “
” is repeated each 2-bytes.
The CPU instruction execution sequence is identical regardless of whether the transfer
start address is even or odd.
6–84
7700 FAMILY SOFTWARE MANUAL
Block Transfer
Instruction
:
Timing
:
MVP
● The transfer of odd byte
Repeated this cycle
φ CPU
AP(CPU)
PG
PG
dd
PG
AHAL(CPU)
PC
PC+1
Y
PC+2
dd
DATA(CPU)
Op Code (Destination
Bank)
Not
used
ss
ss
X
ss
Not
used
(Source
Bank)
?
Not
used
X–2(n–1)–1
Not
used
Not
used
Not
used
DHDL
“H”
R/W(CPU)
Transfer last 1-byte
Destination Bank
Y–2(n–1)–1
Not
used
DHDL
Not
used
dd
ss
ss
dd
dd
PG
?
X–2n
–1
X–2n
Y–2n
–1
Y–2n
PC+3
Not
used
Not
used
Not
used
DL
Not
used
Not
used
DL
Next
Op Code
(Note) This figure is shown that transferred the 2-bytes data. If transferred more than 2-bytes,
the cycle “
” is repeated each 2-bytes.
The CPU instruction execution sequence is identical regardless of whether the transfer
start address is even or odd.
7700 FAMILY SOFTWARE MANUAL
6–85
CPU INSTRUCTION EXECUTION SEQUENCE FOR
EACH ADDRESSING MODES
MEMORANDUM
6–86
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX 1. Machine Instructions
APPENDIX 2. Hexadecimal Instruction Code Table
APPENDIX
APPENDIX.1 Machine Instructions
7–2
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–3
APPENDIX
APPENDIX.1 Machine Instructions
7–4
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–5
APPENDIX
APPENDIX.1 Machine Instructions
7–6
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–7
APPENDIX
APPENDIX.1 Machine Instructions
7–8
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–9
APPENDIX
APPENDIX.1 Machine Instructions
7–10
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–11
APPENDIX
APPENDIX.1 Machine Instructions
7–12
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–13
APPENDIX
APPENDIX.1 Machine Instructions
7–14
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–15
APPENDIX
APPENDIX.1 Machine Instructions
7–16
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–17
APPENDIX
APPENDIX.2 Hexadecimal Instruction Code Table
INSTRUCTION CODE TABLE - 1
D3—D0
D7—D4
0000
Hexadecimal
notation
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
SEB
ORA
ASL
ORA
ABS
A,ABL
ASL
ORA
BRK
ORA
ORA
SEB
ORA
ASL
ORA
A,(DIR,X)
A,SR
DIR,b
A,DIR
DIR
A,L(DIR)
ORA
CLB
ORA
ASL
ORA
ORA
0001
0010
1
BPL
ORA
A,(DIR),Y A,(DIR) A,(SR),Y DIR,b
JSR
AND
JSR
AND
ABS
A,(DIR,X)
ABL
A,SR
AND
AND
AND
2
0011
3
BMI
0100
4
RTI
A,(DIR,X)
EOR
5
BVC
6
RTS
EOR
7
1000
8
BVS
BRA
REL
1001
9
BCC
LDY
1010
A
IMM
1011
B
A,SR
A,(DIR,X)
ADC
D
1110
E
1111
F
DIR
A,L(DIR)
ROL
AND
BBC
AND
EOR
MVP
MVN
LDM
DIR,X A,L(DIR),Y
LSR
A,DIR
DIR
A,L(DIR)
EOR
LSR
EOR
A,DIR,X DIR,X A,L(DIR),Y
ADC
ADC
ROR
ADC
A,SR
DIR
A,DIR
DIR
A,L(DIR)
ADC
LDM
ADC
ROR
ADC
A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X DIR,X A,L(DIR),Y
STA
BRA
STA
STY
STA
STX
REL
A,SR
DIR
A,DIR
DIR
A,L(DIR)
STA
STA
STA
STY
STA
STX
STA
DIR,X
A,DIR,X
LDX
LDY
LDA
LDA
LDA
DIR,Y A,L(DIR),Y
LDX
A,(DIR,X)
IMM
A,SR
DIR
A,DIR
DIR
A,L(DIR)
LDA
LDA
LDA
LDY
LDA
LDX
LDA
A
ORA
DEC
DIR,X
A,DIR,X
CLP
CMP
CPY
CMP
DEC
CMP
IMM
A,(DIR,X)
IMM
A,SR
DIR
A,DIR
DIR
A,L(DIR)
CMP
CMP
CMP
CMP
DEC
CMP
A,(DIR),Y A,(DIR) A,(SR),Y
PEI
A,DIR,X
DIR,X A,L(DIR),Y
SBC
SEP
SBC
CPX
SBC
INC
SBC
IMM
A,(DIR,X)
IMM
A,SR
DIR
A,DIR
DIR
A,L(DIR)
SBC
SBC
SBC
SBC
INC
SBC
A,(DIR),Y A,(DIR) A,(SR),Y
A,DIR,X
ABS,b A,ABS
CLB
A
AND
ROL
A,IMM
A
SEC
PHA
AND
INC
A,ABS,Y
A
EOR
LSR
A,IMM
A
PHG
EOR
CLI
A,ABS,Y
ADC
PHY
DIR,X A,L(DIR),Y
AND
ABS
A,ABL
ROL
AND
EOR
ABS
JMP
LSR
EOR
A,ABS
ABS
A,ABL
EOR
LSR
EOR
A,ABS,X ABS,X A,ABL,X
JMP
ADC
ROR
ADC
(ABS)
JMP
A,ABS
ABS
A,ABL
ADC
ROR
ADC
RTL
A,IMM
A
ADC
SEI
JMP
ABL
PLA
AND
ROL
ABS,b,R A,ABS,X ABS,X A,ABL,X
TAD
ROR
AND
ABS,b,R A,ABS
BBC
TSA
ORA
ABS,b A,ABS,X ABS,X A,ABL,X
BBS
PLD
A,ABS,Y
DEY
PLY
TDA
Note 2
TXA
PHT
STA
TYA
A,ABS,Y
TXS
STX
STA
ABS
LDM
A,ABS
ABS
A,ABL
STA
LDM
STA
A,ABS,X ABS,X A,ABL,X
LDA
A,IMM
ABS
LDA
LDY
TAX
TSX
INY
ABS
A,ABL
LDA
LDX
LDA
CPY
CMP
DEC
CMP
ABS
A,ABS
ABS
A,ABL
JMP
CMP
DEC
CMP
WIT
CMP
PHX
STP
NOP
PSH
PLX
PUL
SBC
SBC
A,ABS,Y
A,ABS
ABS,X A,ABS,X ABS,Y A,ABL,X
DEX
A,IMM
LDA
TYX
A,IMM
A,ABS,Y
LDX
PLT
CMP
SEM
STA
ABS
A,ABS,Y
INX
STY
LDY
TAY
CLM
(ABS,X) A,ABS,X ABS,X A,ABL,X
TXY
LDA
DIR,Y A,L(DIR),Y
CPX
PEA
PHD
TAS
A,ABS,Y
CLV
CMP
BEQ
ASL
PLP
LDA
CPY
BNE
ORA
A,IMM
STA
A,(DIR,X)
A,(DIR),Y A,(DIR) A,(SR),Y
CLC
EOR
BCS
C
1101
DIR,b,R A,DIR
PER
A,(DIR),Y A,(DIR) A,(SR),Y
1100
AND
EOR
A,(DIR),Y A,(DIR) A,(SR),Y
ADC
0111
ROL
EOR
Note 1
ADC
0110
AND
A,(DIR),Y A,(DIR) A,(SR),Y DIR,b,R A,DIR,X
EOR
0101
BBS
A,DIR,X DIR,X A,L(DIR),Y
PHP
L(ABS) A,ABS,X ABS,X A,ABL,X
CPX
SBC
INC
SBC
ABS
A,ABS
ABS
A,ABL
JSR
SBC
INC
SBC
(ABS,X) A,ABS,X ABS,X A,ABL,X
Note 1. 4216 specifies the contents of the INSTRUCTION CODE TABLE-2. About the second word's codes, refer to the INSTRUCTION CODE TABLE-2.
Note 2. 8916 specifies the contents of the INSTRUCTION CODE TABLE-3. About the second word's codes, refer to the INSTRUCTION CODE TABLE-3.
7–18
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.2 Hexadecimal Instruction Code Table
INSTRUCTION CODE TABLE - 2 (The first word's code of each instruction is 4216)
D3—D0
D7—D4
Hexadecimal
notation
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ASL
ORA
ORA
B,ABL
ORA
0000
0
B,(DIR,X)
ORA
0001
0010
1
2
ORA
ORA
ORA
B,SR
B,DIR
B,L(DIR)
B,IMM
B
B,ABS
ORA
ORA
ORA
ORA
DEC
ORA
ORA
B,DIR,X
B
B,ABS,X
B,ABL,X
B,(DIR),Y B,(DIR) B,(SR),Y
B,L(DIR),Y
AND
AND
AND
AND
AND
ROL
AND
AND
B,(DIR,X)
B,SR
B,DIR
B,L(DIR)
B,IMM
B
B,ABS
B,ABL
INC
AND
AND
EOR
5
EOR
B,DIR
B,L(DIR)
B,IMM
EOR
EOR
EOR
ADC
B,ABS
B,ABL
EOR
EOR
TBD
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
ADC
ADC
ROR
ADC
ADC
B
B,ABS
B,ABL
B,SR
B,DIR
B,L(DIR)
B,IMM
ADC
ADC
ADC
ADC
B,L(DIR),Y
B,ABS,Y
STA
ADC
B,DIR,X
ADC
B,ABS,X
B,ABL,X
STA
STA
B,DIR
STA
B,L(DIR)
STA
STA
B,ABS
B,DIR,X
LDA
TXB
B,SR
STA
STA
STA
STA
B,ABL
STA
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
LDA
LDA
LDA
LDA
STA
9
B,(DIR),Y B,(DIR) B,(SR),Y
LDA
LDA
TYB
A
TBY
B,(DIR,X)
LDA
LDA
TBX
B,SR
B,DIR
B,L(DIR)
B,IMM
B,ABS
B,ABL
LDA
LDA
LDA
LDA
LDA
LDA
B
B,(DIR),Y B,(DIR) B,(SR),Y
CMP
B,DIR,X
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
CMP
CMP
CMP
CMP
CMP
CMP
B,SR
B,DIR
B,L(DIR)
B,IMM
B,ABS
B,ABL
CMP
CMP
CMP
CMP
CMP
CMP
B,DIR,X
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
C
B,(DIR,X)
CMP
CMP
D
B,(DIR),Y B,(DIR) B,(SR),Y
SBC
SBC
SBC
SBC
SBC
SBC
SBC
B,(DIR,X)
B,SR
B,DIR
B,L(DIR)
B,IMM
B,ABS
B,ABL
SBC
SBC
SBC
SBC
SBC
SBC
B,DIR,X
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
E
SBC
1111
B
ADC
8
STA
1110
EOR
TDB
B,(DIR,X)
1101
EOR
7
STA
1100
B
LSR
PLB
B,(DIR),Y B,(DIR) B,(SR),Y
1011
AND
B,ABL,X
B,DIR,X
6
ADC
1010
EOR
EOR
ADC
B,(DIR,X)
1001
EOR
B,SR
B,(DIR),Y B,(DIR) B,(SR),Y
ADC
1000
EOR
AND
B,ABS,X
PHB
EOR
0111
AND
B,ABS,Y
4
B,(DIR,X)
0110
AND
B,L(DIR),Y
TSB
EOR
0101
AND
B,DIR,X
3
B,(DIR),Y B,(DIR) B,(SR),Y
0100
TBS
B,ABS,Y
AND
0011
ORA
ORA
F
SBC
B,(DIR),Y B,(DIR) B,(SR),Y
7700 FAMILY SOFTWARE MANUAL
7–19
APPENDIX
APPENDIX.2 Hexadecimal Instruction Code Table
INSTRUCTION CODE TABLE - 3 (The first word's code of each instruction is 8916)
D3—D0
D7—D4
Hexadecimal
notation
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MPY
0000
MPY
(DIR,X)
MPY
0001
MPY
MPY
MPY
MPY
SR
DIR
L(DIR)
IMM
ABS
ABL
MPY
MPY
MPY
MPY
MPY
MPY
ABL,X
(SR),Y
DIR,X
L(DIR),Y
ABS,Y
ABS,X
DIV
DIV
DIV
DIV
DIV
DIV
DIV
(DIR),X
SR
DIR
L(DIR)
IMM
ABS
ABL
DIV
DIV
DIV
DIV
DIV
DIV
(SR),Y
DIR,X
L(DIR),Y
ABS,Y
ABS,X
ABL,X
MPYS*
MPYS*
XAB
2
DIV
0011
MPY
1
(DIR),Y (DIR)
0010
MPY
0
DIV
3
(DIR),Y (DIR)
RLA
0100
4
IMM
0101
5
0110
6
0111
7
1000
8
MPYS*
MPYS*
(DIR,X)
SR
DIVS*
EXTS*
A
DIR
L(DIR)
IMM
MPYS*
MPYS*
(SR),Y
DIR,X
L(DIR),Y
ABS,Y
DIVS*
DIVS*
DIVS*
DIVS*
EXTZ*
A
ABS,X
ABL,X
DIVS*
DIVS*
SR
DIR
L(DIR)
IMM
ABS
ABL
DIVS*
DIVS*
DIVS*
DIVS*
DIVS*
DIVS*
(DIR),Y (DIR)
(SR),Y
DIR,X
L(DIR),Y
ABS,Y
ABS,X
ABL,X
B
LDT
C
IMM
1101
D
1110
E
1111
F
Note 1. The code of each instruction first word is 8916.
Note 2. “*” shows the instructions can be used in 7750 Series.
7–20
ABL
MPYS*
DIVS*
DIVS*
1100
ABS
MPYS*
A
(DIR),X
1011
MPYS*
9
(DIR),Y (DIR)
1010
MPYS*
MPYS*
MPYS* MPYS* MPYS*
1001
MPYS*
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7–2
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–3
APPENDIX
APPENDIX.1 Machine Instructions
7–4
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–5
APPENDIX
APPENDIX.1 Machine Instructions
7–6
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–7
APPENDIX
APPENDIX.1 Machine Instructions
7–8
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–9
APPENDIX
APPENDIX.1 Machine Instructions
7–10
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–11
APPENDIX
APPENDIX.1 Machine Instructions
7–12
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–13
APPENDIX
APPENDIX.1 Machine Instructions
7–14
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–15
APPENDIX
APPENDIX.1 Machine Instructions
7–16
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.1 Machine Instructions
7700 FAMILY SOFTWARE MANUAL
7–17
APPENDIX
APPENDIX.2 Hexadecimal Instruction Code Table
INSTRUCTION CODE TABLE - 1
D3—D0
D7—D4
0000
Hexadecimal
notation
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
SEB
ORA
ASL
ORA
ABS
A,ABL
ASL
ORA
BRK
ORA
ORA
SEB
ORA
ASL
ORA
A,(DIR,X)
A,SR
DIR,b
A,DIR
DIR
A,L(DIR)
ORA
CLB
ORA
ASL
ORA
ORA
0001
0010
1
BPL
ORA
A,(DIR),Y A,(DIR) A,(SR),Y DIR,b
JSR
AND
JSR
AND
ABS
A,(DIR,X)
ABL
A,SR
AND
AND
AND
2
0011
3
BMI
0100
4
RTI
A,(DIR,X)
EOR
5
BVC
6
RTS
EOR
7
1000
8
BVS
BRA
REL
1001
9
BCC
LDY
1010
A
IMM
1011
B
A,SR
A,(DIR,X)
ADC
D
1110
E
1111
F
DIR
A,L(DIR)
ROL
AND
BBC
AND
EOR
MVP
MVN
LDM
DIR,X A,L(DIR),Y
LSR
A,DIR
DIR
A,L(DIR)
EOR
LSR
EOR
A,DIR,X DIR,X A,L(DIR),Y
ADC
ADC
ROR
ADC
A,SR
DIR
A,DIR
DIR
A,L(DIR)
ADC
LDM
ADC
ROR
ADC
A,(DIR),Y A,(DIR) A,(SR),Y DIR,X A,DIR,X DIR,X A,L(DIR),Y
STA
BRA
STA
STY
STA
STX
REL
A,SR
DIR
A,DIR
DIR
A,L(DIR)
STA
STA
STA
STY
STA
STX
STA
DIR,X
A,DIR,X
LDX
LDY
LDA
LDA
LDA
DIR,Y A,L(DIR),Y
LDX
A,(DIR,X)
IMM
A,SR
DIR
A,DIR
DIR
A,L(DIR)
LDA
LDA
LDA
LDY
LDA
LDX
LDA
A
ORA
DEC
DIR,X
A,DIR,X
CLP
CMP
CPY
CMP
DEC
CMP
IMM
A,(DIR,X)
IMM
A,SR
DIR
A,DIR
DIR
A,L(DIR)
CMP
CMP
CMP
CMP
DEC
CMP
A,(DIR),Y A,(DIR) A,(SR),Y
PEI
A,DIR,X
DIR,X A,L(DIR),Y
SBC
SEP
SBC
CPX
SBC
INC
SBC
IMM
A,(DIR,X)
IMM
A,SR
DIR
A,DIR
DIR
A,L(DIR)
SBC
SBC
SBC
SBC
INC
SBC
A,(DIR),Y A,(DIR) A,(SR),Y
A,DIR,X
ABS,b A,ABS
CLB
A
AND
ROL
A,IMM
A
SEC
PHA
AND
INC
A,ABS,Y
A
EOR
LSR
A,IMM
A
PHG
EOR
CLI
A,ABS,Y
ADC
PHY
DIR,X A,L(DIR),Y
AND
ABS
A,ABL
ROL
AND
EOR
ABS
JMP
LSR
EOR
A,ABS
ABS
A,ABL
EOR
LSR
EOR
A,ABS,X ABS,X A,ABL,X
JMP
ADC
ROR
ADC
(ABS)
JMP
A,ABS
ABS
A,ABL
ADC
ROR
ADC
RTL
A,IMM
A
ADC
SEI
JMP
ABL
PLA
AND
ROL
ABS,b,R A,ABS,X ABS,X A,ABL,X
TAD
ROR
AND
ABS,b,R A,ABS
BBC
TSA
ORA
ABS,b A,ABS,X ABS,X A,ABL,X
BBS
PLD
A,ABS,Y
DEY
PLY
TDA
Note 2
TXA
PHT
STA
TYA
A,ABS,Y
TXS
STX
STA
ABS
LDM
A,ABS
ABS
A,ABL
STA
LDM
STA
A,ABS,X ABS,X A,ABL,X
LDA
A,IMM
ABS
LDA
LDY
TAX
TSX
INY
ABS
A,ABL
LDA
LDX
LDA
CPY
CMP
DEC
CMP
ABS
A,ABS
ABS
A,ABL
JMP
CMP
DEC
CMP
WIT
CMP
PHX
STP
NOP
PSH
PLX
PUL
SBC
SBC
A,ABS,Y
A,ABS
ABS,X A,ABS,X ABS,Y A,ABL,X
DEX
A,IMM
LDA
TYX
A,IMM
A,ABS,Y
LDX
PLT
CMP
SEM
STA
ABS
A,ABS,Y
INX
STY
LDY
TAY
CLM
(ABS,X) A,ABS,X ABS,X A,ABL,X
TXY
LDA
DIR,Y A,L(DIR),Y
CPX
PEA
PHD
TAS
A,ABS,Y
CLV
CMP
BEQ
ASL
PLP
LDA
CPY
BNE
ORA
A,IMM
STA
A,(DIR,X)
A,(DIR),Y A,(DIR) A,(SR),Y
CLC
EOR
BCS
C
1101
DIR,b,R A,DIR
PER
A,(DIR),Y A,(DIR) A,(SR),Y
1100
AND
EOR
A,(DIR),Y A,(DIR) A,(SR),Y
ADC
0111
ROL
EOR
Note 1
ADC
0110
AND
A,(DIR),Y A,(DIR) A,(SR),Y DIR,b,R A,DIR,X
EOR
0101
BBS
A,DIR,X DIR,X A,L(DIR),Y
PHP
L(ABS) A,ABS,X ABS,X A,ABL,X
CPX
SBC
INC
SBC
ABS
A,ABS
ABS
A,ABL
JSR
SBC
INC
SBC
(ABS,X) A,ABS,X ABS,X A,ABL,X
Note 1. 4216 specifies the contents of the INSTRUCTION CODE TABLE-2. About the second word's codes, refer to the INSTRUCTION CODE TABLE-2.
Note 2. 8916 specifies the contents of the INSTRUCTION CODE TABLE-3. About the second word's codes, refer to the INSTRUCTION CODE TABLE-3.
7–18
7700 FAMILY SOFTWARE MANUAL
APPENDIX
APPENDIX.2 Hexadecimal Instruction Code Table
INSTRUCTION CODE TABLE - 2 (The first word's code of each instruction is 4216)
D3—D0
D7—D4
Hexadecimal
notation
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ASL
ORA
ORA
B,ABL
ORA
0000
0
B,(DIR,X)
ORA
0001
0010
1
2
ORA
ORA
ORA
B,SR
B,DIR
B,L(DIR)
B,IMM
B
B,ABS
ORA
ORA
ORA
ORA
DEC
ORA
ORA
B,DIR,X
B
B,ABS,X
B,ABL,X
B,(DIR),Y B,(DIR) B,(SR),Y
B,L(DIR),Y
AND
AND
AND
AND
AND
ROL
AND
AND
B,(DIR,X)
B,SR
B,DIR
B,L(DIR)
B,IMM
B
B,ABS
B,ABL
INC
AND
AND
EOR
5
EOR
B,DIR
B,L(DIR)
B,IMM
EOR
EOR
EOR
ADC
B,ABS
B,ABL
EOR
EOR
TBD
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
ADC
ADC
ROR
ADC
ADC
B
B,ABS
B,ABL
B,SR
B,DIR
B,L(DIR)
B,IMM
ADC
ADC
ADC
ADC
B,L(DIR),Y
B,ABS,Y
STA
ADC
B,DIR,X
ADC
B,ABS,X
B,ABL,X
STA
STA
B,DIR
STA
B,L(DIR)
STA
STA
B,ABS
B,DIR,X
LDA
TXB
B,SR
STA
STA
STA
STA
B,ABL
STA
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
LDA
LDA
LDA
LDA
STA
9
B,(DIR),Y B,(DIR) B,(SR),Y
LDA
LDA
TYB
A
TBY
B,(DIR,X)
LDA
LDA
TBX
B,SR
B,DIR
B,L(DIR)
B,IMM
B,ABS
B,ABL
LDA
LDA
LDA
LDA
LDA
LDA
B
B,(DIR),Y B,(DIR) B,(SR),Y
CMP
B,DIR,X
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
CMP
CMP
CMP
CMP
CMP
CMP
B,SR
B,DIR
B,L(DIR)
B,IMM
B,ABS
B,ABL
CMP
CMP
CMP
CMP
CMP
CMP
B,DIR,X
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
C
B,(DIR,X)
CMP
CMP
D
B,(DIR),Y B,(DIR) B,(SR),Y
SBC
SBC
SBC
SBC
SBC
SBC
SBC
B,(DIR,X)
B,SR
B,DIR
B,L(DIR)
B,IMM
B,ABS
B,ABL
SBC
SBC
SBC
SBC
SBC
SBC
B,DIR,X
B,L(DIR),Y
B,ABS,Y
B,ABS,X
B,ABL,X
E
SBC
1111
B
ADC
8
STA
1110
EOR
TDB
B,(DIR,X)
1101
EOR
7
STA
1100
B
LSR
PLB
B,(DIR),Y B,(DIR) B,(SR),Y
1011
AND
B,ABL,X
B,DIR,X
6
ADC
1010
EOR
EOR
ADC
B,(DIR,X)
1001
EOR
B,SR
B,(DIR),Y B,(DIR) B,(SR),Y
ADC
1000
EOR
AND
B,ABS,X
PHB
EOR
0111
AND
B,ABS,Y
4
B,(DIR,X)
0110
AND
B,L(DIR),Y
TSB
EOR
0101
AND
B,DIR,X
3
B,(DIR),Y B,(DIR) B,(SR),Y
0100
TBS
B,ABS,Y
AND
0011
ORA
ORA
F
SBC
B,(DIR),Y B,(DIR) B,(SR),Y
7700 FAMILY SOFTWARE MANUAL
7–19
APPENDIX
APPENDIX.2 Hexadecimal Instruction Code Table
INSTRUCTION CODE TABLE - 3 (The first word's code of each instruction is 8916)
D3—D0
D7—D4
Hexadecimal
notation
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MPY
0000
MPY
(DIR,X)
MPY
0001
MPY
MPY
MPY
MPY
SR
DIR
L(DIR)
IMM
ABS
ABL
MPY
MPY
MPY
MPY
MPY
MPY
ABL,X
(SR),Y
DIR,X
L(DIR),Y
ABS,Y
ABS,X
DIV
DIV
DIV
DIV
DIV
DIV
DIV
(DIR),X
SR
DIR
L(DIR)
IMM
ABS
ABL
DIV
DIV
DIV
DIV
DIV
DIV
(SR),Y
DIR,X
L(DIR),Y
ABS,Y
ABS,X
ABL,X
MPYS*
MPYS*
XAB
2
DIV
0011
MPY
1
(DIR),Y (DIR)
0010
MPY
0
DIV
3
(DIR),Y (DIR)
RLA
0100
4
IMM
0101
5
0110
6
0111
7
1000
8
MPYS*
MPYS*
(DIR,X)
SR
DIVS*
EXTS*
A
DIR
L(DIR)
IMM
MPYS*
MPYS*
(SR),Y
DIR,X
L(DIR),Y
ABS,Y
DIVS*
DIVS*
DIVS*
DIVS*
EXTZ*
A
ABS,X
ABL,X
DIVS*
DIVS*
SR
DIR
L(DIR)
IMM
ABS
ABL
DIVS*
DIVS*
DIVS*
DIVS*
DIVS*
DIVS*
(DIR),Y (DIR)
(SR),Y
DIR,X
L(DIR),Y
ABS,Y
ABS,X
ABL,X
B
LDT
C
IMM
1101
D
1110
E
1111
F
Note 1. The code of each instruction first word is 8916.
Note 2. “*” shows the instructions can be used in 7750 Series.
7–20
ABL
MPYS*
DIVS*
DIVS*
1100
ABS
MPYS*
A
(DIR),X
1011
MPYS*
9
(DIR),Y (DIR)
1010
MPYS*
MPYS*
MPYS* MPYS* MPYS*
1001
MPYS*
7700 FAMILY SOFTWARE MANUAL
MITSUBISHI SEMICONDUCTORS
7700 Family Software MANUAL
Sep. First Edition 1994
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1994 MITSUBISHI ELECTRIC CORPORATION
Software Manual
7700 Family
H-ED298-A KI-9409 Printed in Japan (ROD)
© 1994 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Sep. 1994.
Specifications subject to change without notice.