Final Datasheet, Version 2.08, 2004-06-07 System Basis Chip TLE 6263 Integrated LS CAN, LDO and HS Switch Automotive and Industrial N e v e r s t o p t h i n k i n g . CAN-LDO-ASIC TLE 6263 Final Datasheet 1 • • • • • • • • • • • • • • • • • • Features Standard fault tolerant differential CAN-transceiver Bus failure management Low power mode management Receive only mode for CAN CAN data transmission rate up to 125 kBaud Low-dropout voltage 5V regulator High side switch 2 wake-up inputs Power on and under-voltage reset generator Window watchdog Fail-safe output Early warning feature (VCC warning) Sense comparator input (VINT warning) Standard 8 bit SPI-interface Flash program mode Wide input voltage range Wide temperature range Enhanced power P-DSO-Package P-DSO-28-18 Enhanced Power Type Ordering Code Package TLE 6263 G Q67007-A9465 P-DSO-28-18 2 Description The TLE 6263 is a monolithic integrated circuit in an enhanced power P-DSO-28-18 package. The IC is optimized for use in advanced automotive electronic control units for body and convenience applications. To support this applications the TLE 6263 covers the main smart power functions such as failure tolerant low speed CAN-transceiver for differential mode data transmission, low dropout voltage regulator (LDO) for internal and external 5V supply as well as a SPI (serial peripheral interface) to control and monitor the IC. Further there are integrated additional features like a high side switch that can be used e.g. for cyclic supply of an external wake-up circuitry, two wake-up inputs, a window watchdog circuit with fail safe output as well as a reset and early warning feature. The IC is designed to withstand the severe conditions of automotive applications. Version 2.08 2 2004-06-07 Final Datasheet TLE 6263 3 Pin Configuration (top view) TxD 1 RxD 2 28 INT P-DSO-28-6 27 RTH (enhanced power package) RO 3 26 CANH WK2 4 25 RTL WK1 5 24 CANL GND 6 23 GND GND 7 22 GND GND 8 21 GND GND 9 20 GND 19 VCC DO 10 Figure 1: Version 2.08 CLK 11 18 V CI CSN 12 17 FSO DI 13 16 SI OUTHS 14 15 VS Pin Configuration TLE 6263 G (top view) 3 2004-06-07 Final Datasheet TLE 6263 4 Pin Definitions and Functions Pin No. Symbol Function 1 TxD Transmit data input; integrated pull up; LOW: bus becomes dominant, HIGH: bus becomes recessive 2 RxD Receive data output; push-pull output; LOW: bus becomes dominant, HIGH: bus becomes recessive 3 RO Reset output; open drain output, integrated pull up, active low 4 WK2 Wake-Up input 2; for detection of external wake-up events, edge sensitive, in sleep mode monitored by cyclic sense feature when selected; weak pull up (2µA) to avoid unwanted wake ups 5 WK1 Wake-Up input 1; for detection of external wake-up events, edge sensitive, in sleep mode monitored by cyclic sense feature when selected; weak pull up (2µA) to avoid unwanted weak ups 6, 7, 8, 9, GND 20, 21, 22, 23 Ground; to reduce thermal resistance place cooling areas on PCB close to this pins. 10 DO SPI data output; this tri-state output transfers diagnosis data to the control device. Serial data transfered from DO is a 8 bit diagnosis word with the Least Significant Bit (LSB) transmitted first. The output will remain 3-stated unless the device is selected by a LOW on Chip-Select-Not (CSN). DO will accept data on the rising edge of CLK-signal; see table 4, 5, 6 for Diagnosis protocol 11 CLK SPI clock input; clocks the shiftregister; CLK has a pull down input, active HIGH, and requires CMOS logic level inputs 12 CSN SPI chip select not input; CSN is a pull up input, active LOW, serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal active pull up and requires CMOS logic level inputs 13 DI SPI data input; receives serial data from the control device; serial data transmitted to DI is a 8 bit control word with the Least Significant Bit (LSB) being transferred first: the input has a pull down input, active HIGH, and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see table 3 for input data protocol 14 OUTHS High side switch output; controlled via SPI, in sleep mode controlled by internal cyclic sense function when selected Version 2.08 4 2004-06-07 Final Datasheet TLE 6263 4 Pin Definitions and Functions (cont’d) Pin No. Symbol Function 15 VS Power supply input; block to GND directly at the IC with ceramic capacitor 16 SI Sense comparator input; for monitoring of external voltages, to program the detection level connect external voltage divider 17 FSO Fail safe output; to supervise and control critical applications, high when watchdog is correctly served, LOW at any reset condition, open drain output, internal pull up, active LOW 18 VCI Internal voltage supply; for stabilization of internal power supply, block to GND with an external capacitor CVI ≥ 100 nF 19 VCC Voltage regulator output; for 5V supply, to stabilize block to GND with an external capacitor CQ ≥ 100 nF 24 CANL CAN-L bus line; LOW in dominant state 25 RTL CANL-Termination output; connect to CANL bus line via termination resistor 26 CANH CAN-H bus line; HIGH in dominant state 27 RTH CANH-Termination input; connect to CANH bus line via termination resistor 28 INT Interrupt output; to monitor wake-up events or valid sense input condition; integrated pull up resistor; active LOW Version 2.08 5 2004-06-07 Final Datasheet TLE 6263 5 Functional Block Diagram V BAT OUTHS Vcc CSN Drive + Protection Charge Pump CLK SPI DI DO VCC + VCI Time Base Vcc Reset Generator + Watchdog Band Gap Vcc INT SI RO Vcc FSO Early Warning / V S supervisor Vs Vcc CAN Standby / Sleep Control Vcc Vcc WK1 WK2 RTL Vcc H Output Stage CANL L Output Stage RTH Filter Receiver TxD Driver Fail Management CANH Temp Protect Vcc Input Stage RxD CAN Fail Detect GND Figure 2: Version 2.08 TLE 6263 G Functional Bloc Diagram 6 2004-06-07 Final Datasheet TLE 6263 6 Circuit Description The TLE 6263 is a monolithic IC, which incorporates a failure tolerant low speed CANtransceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5V supply as well as a SPI (serial peripheral interface) to control and monitor the IC. Further there are integrated a high side switch, two wake-up inputs, a window watchdog circuit with fail safe output as well as a reset circuit and early warning function. Figure 2 shows a schematic block diagram of the TLE 6263. Table 1 shows the status of the different chip features during the four main operation modes. Table 1: Truth table of the TLE 6263 Vbat stand-by mode receive-only mode sleep mode Feature normal mode VCC ON ON ON OFF Reset ON ON ON OFF Watchdog ON ON ON Fail safe output ON ON VINT-Fail2) ON Sense input 1) OFF ON 5) OFF ON ON ON ON ON ON OFF Wake-up 1 / 2 ON3) ON3) ON ON HS-switch4) ON ON ON OFF HS-cyclic-sense4) OFF OFF ON ON SPI ON ON ON OFF CAN transmit ON OFF OFF OFF CAN receive ON ON OFF OFF RTL output switched to Vcc switched to Vcc switched to Vs switched to Vs RxD output L = bus dominant; H = bus recessive L = bus dominant; H = bus recessive active low wake-up interrupt low INT output active low early warning active low early warning for VINT and VCC active low early warning low 1) at low VCC output current only active when watchdog undercurrent function is not activated 2) can only be monitored in Vbat-stand-by mode via SPI no wake-up interrupt generated, logic level status monitored via SPI 4) only active when selected via SPI 3) 5) if watchdog under-current function active, than FSO = low Version 2.08 7 2004-06-07 Final Datasheet TLE 6263 6.1 Operation Modes The TLE 6263 offers four different operation modes that are controlled via the SPI interface (NSTB= SPI Input Bit3, ENT=SPI Input Bit2): the normal operation mode, the receive-only mode, the Vbat stand-by mode and the sleep operation mode. Please see the state diagram (figure 3). Normal and Receive only Mode In the normal operation mode both is possible, receiving and transmitting of messages, in the receive-only mode (RxD-only mode) the output stages are disabled which doesn’t allow the CAN controller to send a message to the bus. In the state diagram (figure 3), VCC is the status of the voltage regulator. SPI Input Bits: IBit2 = ENT IBit3 = NSTB Power Down Start Up Power Up Normal Mode NSTB 1 2) ENT VCC ON ENT 1 2) 0 ENT 2) NSTB 0 NSTB 1 2) NSTB or VCC ENT 0 VCC ON 2) NSTB 2) NSTB ENT or VCC 2) NSTB NSTB 0 1 ENT 0 after 500µs HS cyclic sense NSTB 0 VCC ON RxD = LOW if a wake up occured by WK1, WK2 or CAN message 1) after 64ms ENT 1 VCC ON HS Switch = ON Vbat Stand-By Mode Wake Up = transition on WK1 or WK 2 for t > tWU or CAN message Sleep ENT 1 1) Vbat Stand-By VRT Sleep Mode NSTB 0 VRT 0 0 1 2) ENT 0 0 1 RxD-Only 2) NSTB 1 1 ENT VCC OFF 2) ENT 1 HS switch = OFF 1) after 64ms 1) after 500µs HS cyclic sense NSTB 0 ENT 1 HS Switch = ON Figure 3: 1) automatic repeated transition only if HS cycl sense feature is selected by SPI IBit 4 2) NSTB and ENT are both SPI Input Bits (IBits) VCC OFF State Diagram Vbat stand-by mode and sleep mode In the Vbat stand-by mode and sleep mode the RTL output voltage is switched to VS. Both modes are low power modes. In the sleep mode the whole application is switched Version 2.08 8 2004-06-07 Final Datasheet TLE 6263 off by disabling the voltage regulator. That allows the total current consumption to drop down to less than 100 µA. When a reset occurs, due to false watchdog triggering, the TLE6263 automatically switches from normal mode or receive-only mode respectively, to the Vbat stand-by mode. If a watchdog reset occurs in the Vbat stand-by mode the IC remains in this mode. In sleep mode a wake-up at any of the wake-up inputs as well as via the bus lines (CANH or CANL) automatically sets the TLE 6263 in Vbat stand-by mode. In the Vbat stand-by mode a wake-up is monitored by setting the output RxD low. This feature works as a flag, to indicate a wake event to the microcontroller. To send and to receive messages, the CAN-transceiver has to be set to normal operation mode by the microcontroller. In case the IC shall directly be set back to sleep mode after a wake-up, an internal wakeflip-flop has to be reseted via the SPI. Therefore IBIT1 has to be set high and then low again by a second SPI transmission. A transition from the Vbat stand-by mode to the normal mode or receive-only mode respectively, automatically resets the wake-flip-flop. 6.2 Low Dropout Voltage Regulator The integrated low dropout voltage regulator is able to drive the internal loads (e.g. CAN-circuit) as well as external 5V loads. Its output voltage tolerance is better than ± 2%. The maximum output current is limited to 110 mA. An external reverse current protection is recommended at the pin Vs to prevent the output capacitor from being discharged by negative transients or low input voltage. Stability of the output voltage is guaranteed for output capacitors CQ ≥ 100 nF, nevertheless it is recommended to use capacitors CQ ≥ 10 µF to buffer the output voltage and therefore improve the reset behavior at input voltage transients. To stabilize the internal supply a capacitor CVI ≥ 100 nF directly connected to the pin VCI is required. 6.3 CAN Transceiver The TLE 6263 is optimized for low speed data transmission up to 125 kBaud in automotive applications. Figure 4 shows the principle configuration of a CAN network.Normally a differential signal is transmitted and received respectively. When a bus wiring failure (see table 2) is detected the device automatically switches to a dedicated CANH or CANL single-wire mode to maintain the communication if necessary. Further a receive-only mode is implemented that allows a separate CAN node diagnosis. During normal and RxD-only mode, RTL is switched to VCC and RTH to GND. During Vbat stand-by and the cyclic wake mode, RTL is switched to VS and RTH to GND. Version 2.08 9 2004-06-07 Final Datasheet TLE 6263 Controller 1 RxD1 Controller 2 TxD1 RxD2 TxD2 Transceiver2 Transceiver1 BUS Line Figure 4: CAN Network Example Receive-only Mode The receive only mode is designed for a special test procedure to check the bus connections. Figure 5 shows a network consisting of 5 nodes. If the connection between node 1 and node 3 shall be tested, the nodes 2,4 and 5 are switched into receive only mode. Node 1 and node 3 are in normal mode. If node 1 sends a message, node 3 is the only node which can acknowledge the message, the other nodes can only listen but cannot send an acknowledge bit. If node 1 receives the acknowledge bit from node 3, the connection is OK. 5 4 1 3 2 Figure 5: Version 2.08 Testing the Bus Connection in Receive-only Mode 10 2004-06-07 Final Datasheet TLE 6263 Electromagnetic Emmision (EME) To reduce radiated electromagnetic emission (EME), the dynamic slopes of the CANL and CANH signals are both limited and symmetric. This allows the use of an unshielded twisted or parallel pair of wires for the bus. During single-wire transmission (one of the bus lines is affected by a bus line failure) the EME performance of the system is degraded from the differential mode. 6.4 Bus Failure Management There are 9 different CAN bus wiring failures defined by the ISO 11519-2/ISO 11898-3 standard. These failures are devided into 7 failure groups (see Table 2). The difference between ISO11898-3 and ISO 11519-2 is also shown in Table 2. When a bus wiring failure is detected the device automatically switches to a dedicated CANH or CANL single-wire mode to maintain the communication if necessary. Therefore it is equipped with one differential receiver and four single ended comparators (two for each bus line). To avoid false triggering by external RF influences, the single wire modes are activated after a certain delay time. As soon as the bus failure disappears the transceiver switches back to differential mode after another time delay. The differential receiver threshold is set to typ. -2.5V. This ensures correct reception in the normal operation mode as well as in the failure cases 1, 2, 3a(6a) and 4(5) with a noise margin as high as possible. When one of the bus failures 3(6), 5(4), 6(3), 6a(3a), and 7 is detected, the defective bus wire is disabled by switching off the affected bus termination and output stage. The failure cases in brackets() are the failure cases according to ISO 11898-3. Simultaneously the multiplexing output of the receiver circuit is switched to the unaffected single ended comparator The bus failures are monitored via the diagnosis protocoll of the SPI. A general indication of a CAN failure during normal mode at CANH or CANL is reported by OBIT 4 and 5. It is also possible to distinguish 6 CAN bus failures or failure groups on the SPI output bits 3 to 7 in the RxOnly mode(see Table 2 and 5). The failures are reported until transmission of the next CAN word begins. In case the transmission data input TxD is permanently dominant, both, the CANH and CANL transmitting stage are disabled after a certain delay time tTxD. This is necessary to prevent the bus from being blocked by a defective protocol unit or short to GND at the TxD input. In order to protect the transceiver output stages from being damaged by shorts on the bus lines, current limiting circuits are integrated. The CANL and CANH output stage respectively are protected by an additional temperature sensor, that disables them as soon as the junction temperature exceeds the maximum value. In the temperature shutdown condition of the CAN output stages receiving messages from the bus lines is still possible. Version 2.08 11 2004-06-07 Final Datasheet TLE 6263 Table 2: CAN bus line failure cases failure # failure description according to ISO 11898-3 failure description according to 11519-2 1 CANH line interrupted CANL line interrupted 2 CANL line interrupted CANH line interrupted 3 CANH shorted to Vbat CANL shorted to Vbat 3a CANH shorted to Vcc CANL shorted to Vcc 4 CANL shorted to GND CANH shorted to GND 5 CANH shorted to GND CANL shorted to GND 6 CANL shorted to Vbat CANH shorted to Vbat 6a CANL shorted to Vcc CANH shorted to Vcc 7 CANL shorted to CANH CANL shorted to CANH 6.5 SPI (serial peripheral interface) The 8-bit wide programming word (input word, see table 3) is read in via the data input DI, and this is synchronized with the clock input CLK supplied by the µC. The diagnostic information depends on the operation mode. The internal latches for the Vbat-stand-by diagnosis are reseted when leaving this mode. Table 3, Input Data Protocol all modes Table 4, Diagnosis Data Protocol normal mode IBIT OBIT 7 Watchdog Undercurrent Control 7 HS UV / Temp-Shut Down 6 Set VINT-Fail + VCC Fail Flag 6 HS Overcurrent 5 OUTHS ON 5 CANL bus fail 4 OUTHS Cyclic Sense 4 CANH bus fail 3 Not Standby 3 WK2 logic level 2 Enable Transmit 2 WK1 logic level 1 Reset Internal WK-FF 1 Window Watchdog Reset 0 Watchdog Trigger 0 Temperature Prewarning H = ON L = OFF Version 2.08 H = ON L = OFF 12 2004-06-07 Final Datasheet TLE 6263 The transmission cycle begins when the TLE6263 is selected by the chip select not input CSN (H to L). After the CSN input returns from L to H, the word that has been read in becomes the new control word. The DO output switches to tri-state status at this point, thereby releasing the DO bus circuit for other uses. For details of the SPI timing please refer to figure 6 to 9. Table 5, Diagnosis Data Protocol RxD-only mode OBIT Table 6, Diagnosis Data Protocol Vbat-Stand-by mode OBIT 7 CAN Failure 5(4) and 7 7 VCC Not-Fail 6 CAN Failure 6 (3) 6 VINT Not-Fail 5 CAN Failure 6a (3a) 5 WK1/2 Initialization Fail 4 CAN Failure 2(1) and 4(5) 4 Wake via CAN bus lines 3 CAN Failure 3(6) 3 WK2 voltage level 2 CAN Failure 1(2) and 3a(6a) 2 WK1 voltage level 1 Window Watchdog Reset 1 Window Watchdog Reset 0 Temperature Prewarning 0 Temperature Prewarning H = ON L = OFF ()... values in brackets according to ISO11898-3 see table 2 6.6 H = ON L = OFF Window Watchdog, Reset When the input voltage exceeds the reset threshold voltage the reset output RO is switched HIGH after a delay time of typ. 8ms. This is necessary for a defined start of the microcontroller when the application is switched on. As soon as an under-voltage condition of the output voltage (VCC < VRT) appears, the reset output RO is switched LOW again (power on and under-voltage reset). The LOW signal is guaranteed down to an output voltage VQ ≥ 1V. Please refer to figure 13, Reset Timing Diagram. In sleep operation mode, the watchdog circuit is automatically disabled. Long Open Window After the above described delayed reset (LOW to HIGH transition of RO) the window watchdog circuit is started by opening a long open window of typ. 65ms. The long open window allows the microcontroller to run his set-up and then to trigger the watchdog via the SPI, refer to figure 11,Watchdog Timeout Definitions. Within the long open window Version 2.08 13 2004-06-07 Final Datasheet TLE 6263 period a watchdog trigger is detected as a “rising edge” by sampling a HIGH on the IBIT 0. The trigger is accepted when the CSN input becomes HIGH after the transmission of the SPI word. After each reset as well as after a power on condition the default value of IBIT 0 is LOW. Closed and Open Window A correct watchdog trigger results in starting the window watchdog by opening a closed window of typ. 6 ms followed by a open window of typ. 10 ms. From now on the microcontroller has to service the watchdog trigger by inverting the IBIT 0 alternating. The “negative” or “positive” edge has to meet the open window time. A correct watchdog service immediately results in starting the next closed window. Please refer to figure 12, Watchdog Timing Diagram. Watchdog Reset Should the trigger signal not meet the open window a watchdog reset is created by setting the reset output RO low for a period of typ. 2 ms. Then the watchdog starts again by opening a long open window. In addition, the SPI OBIT 1 (diagnosis bit 1) is set HIGH until the next successful watchdog trigger to monitor a watchdog reset. OBIT1 is also HIGH until the watchdog is correctly triggered after power-up / start-up. For fail safe reasons the TLE6263 is automatically switched in Vbat-stand-by mode if a watchdog trigger failure occurs. So the power consumption can be minimized in case of a permanent faulty microcontroller. In case of either an undervoltage reset or a watchdog reset all SPI input registers (IBIT 0 to IBIT 7) are set low. Undercurrent Disabling Function To avoid cyclic wake-up’s of the microcontroller due to missing watchdog pulses when the microcontroller is in a low power mode, an automatic undercurrent disabling function of the watchdog circuit can be selected for the TLE 6263 Vbat-stand-by mode. For activation of this feature, the VCC output current in the Vbat-stand-by mode has to be less than the undercurrent threshold (ICC < ICCWD) and in addition the SPI IBIT 7 has to be set HIGH. When the microcontroller returns back to normal mode or the output current becomes higher than ICC > ICCWD the watchdog circuit is enabled again. A long open window is started then, to ensure a simple synchronization of the watchdog timing to the watchdog services of the microcontroller. 6.7 Flash program mode To disable the watchdog feature a flash program mode is available. This mode is selected by applying a voltage of 6.8V < VINT < 7.2V at pin INT. This is useful e.g. if the flash-memory of the micro has to be programmed and therefore a regular watchdog triggering is not possible. If the SPI is required in the flash program mode to change e.g. the mode of the TLE6263 the first input telegram has to be “00000000”. Version 2.08 14 2004-06-07 Final Datasheet TLE 6263 6.8 Fail Safe feature The output FSO becomes HIGH when the watchdog is correctly serviced by the microcontroller for the fourth time. As soon as either an under-voltage reset or watchdog reset occurs, it is set LOW again. This feature is very useful to control critical applications independent of the due function of the microcontroller e.g. to disable the power supply in case of a microcontroller failure. 6.9 Sense Comparator (pin SI) and VINT-fail The sense comparator (early warning function) compares a voltage defined by the user to an internal reference voltage. Therefore the voltage to be supervised has to be scaled down by an external voltage divider in order to compare it to the internal sense threshold VSIth. This feature can be used e.g. to supervise the battery voltage in front of the reverse protection diode. The microcontroller is given a pre-warning before an under-voltage reset due to low input voltage occurs. The pre-warning is flagged by setting the interrupt output INT low in normal mode, receive only mode and Vbat-stand-by mode. In sleep operation mode the sense function is inactive. Calculation of the voltage divider can be easily done since the sense input current can be neglected. An internal blanking time prevents from false triggering due to line transients. Further improvement is possible by the use of an external ceramic capacitor switched between SI and GND (see Application Diagram Figure 15). 6.10 VINT- and VCC-fail flag To activate the VINT supervisor feature the SPI IBIT 6 has to be set HIGH to set an internal flip-flop. This automatically sets the Vbat-stand-by OBIT 6 HIGH, too. Should the internal supply voltage become lower than the internal threshold VVINT,th (typ. 2.5V) the NOT VINT-Fail bit becomes LOW to indicate the low voltage condition. All SPI input registers are set LOW due to a low voltage condition of the internal supply voltage. Like the wake-up diagnosis the VINT-Fail diagnosis can only be monitored in the Vbatstand-by mode. The VINT-Fail feature can also be used to give an indication when the ECU has been changed and therefore a pre-setting routine of the microcontroller has to be started. Further to the reset threshold there is another supervisor threshold implemented, to monitor the output voltage VCC. This threshold is called VVCC,th (typ. 2.5V). The NOT VCC-Fail feature is monitored via OBIT 7 in the Vbat-stand-by mode and set, like the NOT VINT-Fail flag, via IBIT 6 (so both fail features are activated with the IBIT 6 but monitored via OBIT 6 and OBIT 7 during Vbat-stand-by). In the receive-only mode both fail bits cause the interrupt output INT to go low. Version 2.08 15 2004-06-07 Final Datasheet TLE 6263 6.11 Wake-Up Inputs WK1, WK2 In addition to a wake-up from sleep mode via the bus lines CANH or CANL it is also possible to wake-up the TLE6263 from low power mode via the wake-up inputs WK1 and WK2. The wake-up inputs are sensitive to a transition of the voltage level, either from high to low or the other way round. They are active in all operation modes. In the normal mode the current logic level at WK1/2 is monitored via the SPI (see table 4 and 6). A positive or negative voltage edge at WK1/2 in Vbat-stand-by mode or sleep mode immediately results in setting the output RxD low to signal a wake-up. After a wake-up via WK1/2 the transmission of the SPI diagnosis word in the Vbat-stand-by mode shows the logic level that has caused the wake-up. To get the current voltage levels at WK1/2 in the Vbat-stand-by mode the internal wake flip-flop has to be reseted by the IBIT1 for each transmission. As long as IBIT1 is set high or the internal wake flip-flop is reseted respectively, in the Vbat-stand-by mode the RxD output is blocked to signal a new wakeup event via the CAN-bus or the wake-up inputs. Further to the continues sensing at the wake-up inputs a cyclic sense feature is possible. When the OUTHS cyclic sense feature is selected via the SPI IBIT 4 the high side switch as well as the WK1/2 inputs are periodically activated by the TLE6263 in the sleep and Vbat-stand-by mode. When switching the TLE6263 into sleep mode (cyclic sense feature activated) the voltage level at the wake-inputs is sensed 2 times to initialize the reference voltage. Should this initialisation fail (2 samples are unequal) the device is automatically set in Vbat-stand-by mode and the initialisation error is shown on the OBIT 5. To enter the sleep mode now directly from the Vbat-stand-by mode, the internal wake flip-flop has to be reseted by the IBIT 1. 6.12 Interrupt output INT Like the reset output, the interrupt output is a low active output. It is used to monitor low voltage conditions at the sense input in normal mode and stand-by mode (see table 8). In the receive-only mode the VINT-fail flag and VCC supervisor are monitored. 6.13 High Side Switch The high side output OUTHS is able to switch loads up to 150 mA. Its on-resistance is 1.0 Ω typ. @ 25°C. This switch is controlled via the SPI input bits 4 and 5. In normal mode, receive-only mode and Vbat-stand-by mode the high side output is switched on and off, respectively via the SPI input bit 5. To supply external wake-up circuits in sleep mode and Vbat-stand-by mode the output OUTHS can be periodically switched on by the TLE6263 itself. In order to activate this cyclic sense feature the SPI IBIT 4 has to be set high. The auto-timing period then is typ. 65 ms, the on-time is typ. 1 ms. Should there be any over-current condition at the switch in the sleep mode (cyclic sense activated) or Vbat-stand-by mode a wake-up is flagged Version 2.08 16 2004-06-07 Final Datasheet TLE 6263 via the RxD output. The over-current condition is monitored on the SPI OBIT 6 in normal operation mode. The SPI OBIT 0 flags a thermal pre-warning of the high side switch. By this the microcontroller is able to reduce the power dissipation of the TLE6263 by switching off functions of minor priority until the temperature threshold of the thermal shutdown is reached. Further OUTHS is protected against short circuit and overload. As soon as the under-voltage condition of the supply voltage is met (VS < VUVOFF), the switch is automatically disabled by the under-voltage lockout circuit. Moreover the switch is automatically disabled when a reset or watchdog reset occurs. 6.14 Hints for unused pins SI: connect to VS OUTHS: leave open WK1/2: connect to VS or leave open INT: leave open RO: leave open FSO: leave open SI: switch to Vs Version 2.08 17 2004-06-07 Final Datasheet TLE 6263 7 Electrical Characteristics 7.1 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remarks min. max. -0.3 28 V -0.3 40 V -0.3 5.5 V -20 28 V -40 40 V VS >0 V tp< 0.5s; tp/T < 0.1 -0.3 VCC V 0 V < VS < 24 V 0 V < VCC < 5.5 V V 0 V < VS < 24 V 0 V < VCC < 5.5 V V 0 V < VS < 24 V 0 V < VCC < 5.5 V Voltages Supply voltage Supply voltage Regulator output voltage CAN bus voltage (CANH, CANL) CAN bus voltage (CANH, CANL) VS VS VCC VCANH/L VCANH/L Logic input voltages (DI, CLK, VI CSN, OSC, TxD) +0.3 Logic output voltage (DO, RO, INT, RxD, FSO) VDRI,RD Termination input voltage (RTH, RTL) VTL /TH Input voltages at WK1/2 and SI VWK/SI -40 40 V Electrostatic discharge voltage at pin CANH, CANL, GND, VS Vesd -3 3 kV human body model, C = 100 pF, R = 1.5 kΩ Electrostatic discharge voltage at any other pin Vesd -1 1 kV human body model, C = 100 pF, R = 1.5 kΩ ICC IOUTH1 – – A 1) internally limited 1) 0.2 A 1) internally limited -0.3 VCC tp< 0.5s; tp/T < 0.1 +0.3 -0.3 VS +0.3 Currents Output current; Vcc Output current; OUTHS Note 1): Not subject to production test - specified by design Version 2.08 18 2004-06-07 Final Datasheet TLE 6263 7.1 Absolute Maximum Ratings (cont’d) Parameter Symbol Limit Values Unit Remarks min. max. – 40 150 °C – – 50 150 °C – Temperatures Junction temperature Storage temperature Note: Tj Tstg Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Version 2.08 19 2004-06-07 Final Datasheet TLE 6263 7.2 Operating Range Parameter Symbol Limit Values min. Unit Remarks max. Supply voltage VS VUV OFF 20 V After VS rising above VUV ON Supply voltage VS dVS /dt VI VUV OFF 40 V thermally limited –0.5 5 V/µs – 0.3 VCC V CCC CVI fclk Tj 100 Rthj-pin Rthj-a Supply voltage slew rate Logic input voltage (DI, CLK, CSN, TxD) Output capacitor Output capacitor SPI clock frequency Junction temperature 100 nF 460 nF 1.5 MHz – 40 150 °C – 25 K/W – 65 K/W Thermal Resistances Junction pin Junction ambient Note: Calculation of the junction temperature Tj = Tamb + P x Rthj-a Version 2.08 20 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition min. typ. max. IQ – 5.5 10 mA normal mode; ICC = 30 mA; TxD recessive IQ – 8 10 mA normal mode; ICC = 30 mA; TxD dominant IQ – 300 400 µA stand-by mode; Tj=25°C; ICC = 1 mA; Ibit 7 = H Current consumption IQ – 50 80 µA sleep mode; Tj=25°C; SPI Ibit 4 = L; VCC = VCCI = 0 V Current consumption IQ 3 mA OUTHS active; SPI Ibit 4 = H; sleep mode; VCC = VCCI = 0 V Quiescent current Pin VS Current consumption IQ = IS - ICC Current consumption IQ = IS - ICC Current consumption IQ = IS - ICC Voltage Regulator; Pin VCC Output voltage VCC 4.9 5.0 5.1 V 0.1 mA< ICC< 100 mA 6 V< VI< 20 V Output voltage 4.8 5.0 5.2 V 0A < ICC < 100 µA Line regulation VCC ∆VCC 50 mV 6 V < VS < 16 V; ICC = 1mA Load regulation ∆VCC 50 mV 5mA< ICC< 100mA; VS = 6V 40 dB VS < 1 Vss; CQ ≥ 10µF 100Hz< f <100kHz 120 mA note 1) 120 mA VCC = 0 V V ICC = 80 mA; note 1) Power supply ripple rejection PSRR Output current limit Output current limit Drop voltage VDR = VS - VCC ICCmax ICCmax VDR 110 0.5 note 1) measured when the output voltage VCC has dropped 100 mV from the nominal value obtained at 13.5 V input voltage VS Version 2.08 21 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics (cont’d) VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. Unit Test Condition max. Oscillator internal oscillating frequency fOSC 125 kHz Internal cycling time (1/64 * fOSC)-1 tCYL 0.43 0.51 0.64 ms Internal cycling time (1/64 * fOSC)-1 tCYL 0.30 0.51 0.72 ms sleep mode 4.5 4.65 4.8 V VCC decreasing Reset low output voltage VRT VRO 0.2 0.4 V IRO = 1mA for VCC = VRT or IRO = 200 µA for VCC ≥ 1V Reset high output voltage VRO 4.0 Reset Generator; Pin RO Reset threshold voltage VCC+ V 0.1 Reset pull up current Reset reaction time Reset delay time (16 cyl.) IRO tRR tRD 20 200 500 µA VRO = 0V 1 2 10 µs VCC < VRT to RO = L 6.9 8.5 12 ms 7.2 10 13.6 ms 55 65 81 ms 5.1 6.1 7.7 ms 8.6 10.2 13 ms 1.7 2 3 ms 0.5 4 7 mA Watchdog Generator tWD Long open window (128 cyl.) tLW Closed window (12 cyl.) tCW tOW Open window (20 cyl.) Watchdog reset-puls time tWDR Watchdog trigger (4 cyl.) Watchdog undercurrent disable threshold Version 2.08 ICCWD 22 Tj < 85 °C; Watchdog OFF when ICC < ICCWD and SPIIbit 7= H 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics (cont’d) VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. Unit Test Condition max. Watchdog Undercurrent disable hysteresis ICCWDhys 0.5 mA Watchdog Undercurrent reaction time tLHR 8 µs Watchdog edge count difference to set HIGH nFS 4 V Fail Safe low output voltage VFS 0.2 Tj=25°C Fail Safe Output; Pin FSO Fail Safe high output voltage VFS 0.4 V VCC+ V 4.0 0.1 IFSO= 1mA for VCC = VRT or IFSO = 200 µA for VCC ≥ 1V IFSO= -1mA for VCC ≥VRT Sense Input (Early Warning) SI, VINT-Fail, Interrupt Output INT Sense In threshold voltage VSI,th Sense In threshold hysteresis VSI,hys 200 mV Sense Input Current ISI tS,r VINThigh 0.1 µA VSI ≥ 0 V Sense reaction time Interrupt Out high voltage 2.1 2.3 2.5 V VSI decreasing until INT transition to LOW 5 10 20 µs VS < VS,th to INT = low 0.7 x – VCC V I0 = – 20 µA VCC 0 – 0.9 V I0 = 1.25 mA 20 150 500 µA VINT = 0V 2.3 2.8 3.1 V VCC-Fail reaction time VINTlow IINT VVCC,th tVCC,r VINT-Fail threshold voltage VVINT,th 1.5 Interrupt Out low voltage Interrupt pull up current VCC-Fail threshold voltage Version 2.08 5 23 3.2 4.3 µs VCC < VVCC,th to Obit 6 = low; Vbatstand-by mode V proportional to VS 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics (cont’d) VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Test Condition Wake-Up Inputs WK1 / WK2 Wake-up threshold voltage VWUth 2 3 4 V sleep mode; Vbatstand-by mode Minimum time for wake-up tWU 10 15 32 µs sleep mode; Vbatstand-by mode Input current IWK µA VWK = 0 V -2 High Side Output OUTHS; (controlled by bit 4 and bit 5 of SPI input word) Static Drain-Source ON-Resistance; IOUTH3 = – 0.15 A RDSON HS – VOUTHS Clamp diode forward voltage VOUTHS Leakage current IQLHS Switch ON delay time tdONHS Switch OFF delay time tdOFFHS Overcurrent shutdown ISDHS Active zener voltage 1.0 1.5 Ω – 3.0 Ω 2.5 3.0 Ω 5.2 V ≤ VS ≤ 9 V Tj = 25 °C – 5.0 Ω 5.2 V ≤ VS ≤ 9 V V IOUTHS = – 0.15 A V IOUTHS = 0.15 A µA VOUTHS = 0 V 20 µs CSN high to OUTHS 20 µs CSN high to OUTHS –2 1 –4 – 0.8 – 0.3 – 0.2 A Tj = 25 °C – threshold Shutdown delay time Current limit UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis Cyclic sense period (128 cyl.) Version 2.08 tdSDHS IOCLHS VUV ON VUV OFF VUV HY tP CS 10 35 50 µs – 1.2 – 0.6 – 0.3 A – 5.2 6.0 V VS increasing 4.5 4.7 5.2 V VS decreasing – 0.5 – V VUV ON – VUV OFF 38 65 92 ms sleep mode SPI-bit 4 = H, 24 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics (cont’d) VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Cyclic sense period (128 cyl.) tP CS Cyclic sense ON time (1 cyl.) tCS on Limit Values min. typ. max. 55 65 80 0.5 Unit Test Condition ms Vbat-stand-by mode; SPI-bit 4 = H; watchdog undercurrent feature active ms CAN-Transceiver Receiver Output R×D HIGH level output voltage LOW level output voltage VOH VCC VCC V I0 = -250 µA VOL 0 0.9 V I0 = 1.25 mA -0.9 Transmission Input T×D 0.52× 0.7 × V HIGH level input voltage threshold VIH LOW level input voltage threshold VIL 0.3 × 0.48× VCC VCC HIGH level input current IIH IIL -150 -30 -10 µA Vi = 4 V -600 -300 -40 µA Vi = 1 V Differential receiver recessive-to-dominant threshold voltage VdRxDrd -2.8 -2.5 -2.2 V Differential receiver dominant-to-recessive threshold voltage VdRxDdr -3.1 -2.9 -2.5 V CANH recessive output voltage VCANHr 0.2 0.3 V LOW level input current VCC VCC V Bus Lines CANL, CANH Version 2.08 0.1 25 TxD = VCC; RRTH < 4 kΩ 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics (cont’d) VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. CANL recessive output voltage VCANLr CANH dominant output voltage VCANHd VCC VCC CANL dominant output voltage VCANLd CANH output current ICANH V TxD = VCC; RRTL < 4 kΩ VCC V TxD = 0 V; ICANH = – 40 mA 1.0 1.4 V TxD = 0 V; ICANL = 40 mA -80 -50 mA VCANH = 0 V; TxD = 0 V 5 µA sleep mode; VCANH = 12 V 110 mA VCANL = 5 V; TxD = 0 V 5 µA sleep mode; VCANL = 0 V -0.2 -1.4 ICANL -110 -1.0 50 80 -5 Voltage detection threshold Vdet(th) for short-circuit to battery voltage on CANH and CANL max. VCC -5 CANL output current Unit Test Condition 6.5 7.3 8.0 V CANH wake-up voltage threshold VH,wk 1.2 1.9 2.7 V low power modes CANL wake-up voltage threshold VL,wk 2.2 3.1 3.9 V low power modes CANH single-ended receiver VCANH threshold 1.6 2.1 2.6 V failure cases 3, 5, 7 recessive to dominant CANL single-ended receiver threshold VCANL 2.4 2.9 3.4 V failure case 6 and 6a recessive to dominant CANL leakage current ICANLl -5 5 µA VCC = 0 V, VS = 0 V, VCANL = 13.5 V CANH leakage current ICANHl -5 5 µA VCC = 0 V, VS = 0 V, VCANH = 5 V Version 2.08 26 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics (cont’d) VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. Unit Test Condition typ. max. 40 95 Ω Io = – 10 mA; 15 30 kΩ VBAT-stand-by or sleep mode Termination Outputs RTL, RTH RTL to VCC switch-on resistance RRTL RTL to BAT switch series resistance RoRTL RTH to ground switch-on resistance RRTH 40 95 Ω Io = 10 mA; RTH output voltage VoRTH 0.7 1.0 V Io = 1 mA; sleep mode or VBAT-stand-by RTH pull-down current 40 75 120 µA failure cases 6 and 6a RTL pull-up current IRTHpd IRTLpu -120 -75 -40 µA failure cases 3, 3a, 5 and 7 RTH leakage current IRTHl -5 5 µA VCC = 0 V, VS = 0 V, VRTH = 5 V, Tj < 85 °C RTL leakage current IRTLl -5 5 µA VCC = 0 V, VS = 0 V VRTL = 13.5 V, Tj < 85 °C 5 CAN-Transceiver Dynamic Characteristics CANH and CANL bus output trd transition time recessive-todominant 0.6 1.2 2.1 µs 10% to 90%; C1 = 10 nF; C2 = 0; R1 = 100 Ω CANH and CANL bus output tdr transition time dominant-torecessive 0.3 0.6 1.3 µs 10% to 90%; C1 = 1 nF; C2 = 0; R1 = 100 Ω 12 20 32 µs Stand-by modes Minimum dominant time for wake-up on CANL or CANH Version 2.08 twu(min) 27 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics (cont’d) VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition min. typ. max. 25 45 80 µs Failure case 6a detection time 2.0 4.8 8.0 ms Failure cases 5 and 7 detection time 1.0 2.0 4.0 ms Failure cases 5, 6, 6a and 7 recovery time 25 45 80 ms Failure cases 3 recovery time 250 500 750 µs 0.4 1.0 2.4 ms Stand-by modes Failure cases 6 and 6a detection time 0.8 4.0 8.0 ms Stand-by modes Failure cases 5, 6, 6a and 7 recovery time 0.4 1.0 2.4 ms Stand-by modes Propagation delay tPD(L) TxD-to-RxD LOW (recessive to dominant) – 1.5 2.1 µs C1 = 100 pF; C2 = 0; R1 = 100 Ω; no failures and bus failure cases 1, 2, 3a and 4 – 1.7 2.4 µs C1 = C2 = 3.3 nF; R1 = 100 Ω; no bus failure and failure cases 1, 2, 3a and 4 – 1.8 2.5 µs C1 100 pF; C2 = 0; R1 = 100 Ω; bus failure cases 3, 5, 6, 6a and 7 – 2.0 2.6 µs C1 = C2 = 3.3 nF; R1 =100 Ω; bus failure cases 3, 5, 6, 6a and 7 Failure cases 3 and 6 detection time Failure cases 5 and 7 detection time Version 2.08 tfail tfail 28 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics (cont’d) VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition min. typ. max. – 1.3 2.0 µs C1 = 100 pF; C2 = 0; R1 =100 Ω; no failures and bus failure cases 1, 2, 3a and 4 – 2.5 3.5 µs C1 = C2 = 3.3 nF; R1 = 100 Ω; no bus failure and failure cases 1, 2, 3a and 4 – 1.3 2.1 µs C1 100 pF; C2 = 0; R1 = 100 Ω; bus failure cases 3, 5, 6, 6a and 7 – 1.7 2.6 µs C1 = C2 = 3.3 nF; R1 = 100 Ω; bus failure cases 3, 5, 6, 6a and 7 Edge-count difference ne (falling edge) between CANH and CANL for failure cases 1, 2, 3a and 4 detection – 4 – – Edge-count difference (rising edge) between CANH and CANL for failure cases 1, 2, 3a and 4 recovery – 2 – – 1.3 2.0 3.5 ms VIH – – 0.7 x V – VIL 0.3 x VIHY IICSN 50 Propagation delay tPD(H) TxD-to-RxD HIGH (dominant to recessive) TxD permanent dominant disable time tTxD SPI-Interface Logic Inputs DI, CLK and CSN H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull up current at pin CSN Version 2.08 VCC – – V – 200 500 mV – – 100 – 25 –5 µA VCSN = 0.7 × VCC VCC 29 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics (cont’d) VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values min. typ. max. Unit Test Condition Pull down current at pin DI and CLK IICLK/DI 5 25 100 µA VDI = 0.2 × VCC Input capacitance at pin CSN, DI or CLK CI – 10 15 pF Not subject to production test specified by design VDOH VCC VCC – V IDOH = 1 mA Logic Output DO H-output voltage level – 1.0 – 0.7 L-output voltage level Tri-state leakage current VDOL IDOLK – 0.2 0.4 V IDOL = – 1.6 mA – 10 – 10 µA VCSN = VCC 0 V < VDO < VCC Tri-state input capacitance CDO – 10 15 pF Not subject to production test specified by design tpCLK tCLKH tCLKL tbef tlead tlag tbeh tDISU tDIHO trIN 1000 – – ns – 500 – – ns – 500 – – ns – 500 – – ns – 500 – – ns – 500 – – ns – 500 – – ns – 250 – – ns – 250 – – ns – – – 200 ns – tfIN – – 200 ns – Data Input Timing Not subject to production test - specified by design Clock period Clock high time Clock low time Clock low before CSN low CSN setup time CLK setup time Clock low after CSN high DI setup time DI hold time Input signal rise time at pin DI, CLK and CSN Input signal fall time at pin DI, CLK and CSN Version 2.08 30 2004-06-07 Final Datasheet TLE 6263 7.3 Electrical Characteristics (cont’d) VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; – 40 °C < Tj < 150 °C (max. 125°C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition min. typ. max. – 50 100 ns CL = 100 pF – 50 100 ns CL = 100 pF – – 250 ns low impedance – – 250 ns high impedance – 100 250 ns VDO < 0.1 VCC; VDO > 0.9 VCC; CL = 100 pF Data Output Timing Not subject to production test - specified by design DO rise time DO fall time DO enable time DO disable time DO valid time trDO tfDO tENDO tDISDO tVADO Thermal Prewarning and Shutdown (junction temperatures) Not subject to production test - specified by design OUTHS thermal prewarning ON temperature TjPW 120 145 170 °C bit 0 of SPI diagnosis word OUTHS thermal prewarning hyst. ∆T – 30 – K – OUTHS thermal shutdown temp. TjSD 150 175 200 °C – OUTHS thermal switch-on temp. TjSO 120 – 170 °C – OUTHS thermal shutdown hyst. ∆T – 30 – K – OUTHS ratio of SD to PW temp. TjSD / TjPW 1.20 – – – 185 200 °C hysteresis 15°K (typ.) °C hysteresis 15°K (typ.) Vcc thermal shutdown temp. TjSD OUTHS thermal shutdown temp. Version 2.08 155 TjSD 150 31 2004-06-07 Final Datasheet TLE 6263 8 Timing Diagrams CSN High to Low & rising edge of CLK: DO is enabled. Status information is transfered to Output Shift Register CSN time CSN Low to High: Data from Shift-Register is transfered to e.g. HS-Switch CLK 0 1 2 3 4 5 6 7 actual Data DI 0 1 2 3 4 5 6 0 1 new Data 0 + 7 1 + DI: Data will be accepted on the falling edge of CLK-Signal previous Status DO 0 1 2 3 4 5 actual Status 6 7 0 1 DO: State will change on the rising edge of CLK-Signal eg. OUTHS old Data Figure 6: SPI-Data Transfer Timing Figure 7: SPI-Input Timing Version 2.08 actual Data 32 2004-06-07 Final Datasheet TLE 6263 Figure 8: Turn OFF/ON Time Figure 9: DO Valid Data Delay Time and Valid Time Version 2.08 33 2004-06-07 Final Datasheet TLE 6263 Figure 10: DO Enable and Disable Time tWD tCWmax tOWmax tCWmin tOWmin closed window open window min. 5.1 max. 7.2 10.0 min. 13.6 max. 18.9 t / ms save trigger area Figure 11: Version 2.08 Watchdog Time-Out Definitions 34 2004-06-07 Final Datasheet TLE 6263 tCW WD Trigger IBIT 0 tCW tCW tOW tOW tCW+tOW tOW tLW tLW tLW tCW tCW tOW tWDR Reset Out t Watchdog timer reset t normal operation Figure 12: VCC timeout (to long) normal operation timeout (to short) normal operation Watchdog Timing Diagram VRT t < tRR VINT-Fail tRD WD Trigger IBIT 0 tLW tLW tCW tOW tRD tLW tCW t t SPI diagnosis bit 6 VINT-Fail Flag in VStbmode tRR tWDR Reset Out t Watchdog timer reset start up normal operation Version 2.08 start up HIGH LOW t activation by microcontroller Figure 13: undervoltage tSR Reset Timing Diagram 35 2004-06-07 Final Datasheet TLE 6263 RxD 5V R1 C1 C2 RTH TxD CANH CSN 20 pF DO CANL C1 R1 CLK RTL DI SI INT WK1 RO WK2 FSO OUTHS VCC 13.5 V +VS GND 100 nF Figure 14: Version 2.08 22 µF VCI 100 nF Test Circuit 36 2004-06-07 Final Datasheet TLE 6263 9 Application Vbat CAN bus TLE 6263 1 kΩ CANH 24 CANL 27 25 160 kΩ Version 2.08 TxD 1 CSN 12 CLK 11 DO 10 DI 13 RTL 16 SI 14 OUTHS INT 28 4 WK2 RO 3 5 WK1 VCC 19 15 +VS FSO 17 VCI 18 µP e.g. C505C, C164C 10 kΩ GND 100 nF Figure 15: 2 RTH 68 µF *) RxD *)10nF 100 kΩ 1 kΩ 26 6 - 9; 20 - 23 100 nF 22 µF GND 100 nF only for improvement refer to 6.9) Application Circuit 37 2004-06-07 Final Datasheet TLE 6263 10 Package Outlines GPS05123 P-DSO-28-18 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Version 2.08 38 Dimensions in mm 2004-06-07 Final Datasheet TLE 6263 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 München © Infineon Technologies AG 2001 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Version 2.08 39 2004-06-07 Infineon goes for Business Excellence “Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.” Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG