W6811 SINGLE-CHANNEL VOICEBAND CODEC (5V Analog, 3V Digital) Data Sheet -1- Publication Release Date: September, 2005 Revision A12 W6811 1. GENERAL DESCRIPTION The W6811 is a general-purpose single channel PCM CODEC with pin-selectable -Law or A-Law companding. The device is compliant with the ITU G.712 specification. It operates off of separated analog (5V) and digital (3V) power supplies and is available in 24-pin PDIP, SOG, SSOP, and TSSOP package options. Functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are compliant with ITU G.712 specification. W6811 performance is specified over the industrial temperature range of –40°C to +85°C. The W6811 includes an on-chip precision voltage reference and an additional power amplifier, capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The data transfer protocol supports both long-frame and short-frame synchronous communications for PCM applications, and IDL and GCI communications for ISDN applications. W6811 accepts seven master clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-scaler automatically determines the division ratio for the required internal clock. 2. FEATURES APPLICATIONS • • • • • • • • • • • • • Power supply: Analog 4.5 – 5.5V Digital 2.7 – 3.3V Typical power dissipation of 25 mW, power-down mode of 0.5 W Fully-differential analog circuit design On-chip precision reference of 1.575 V for a 0 dBm TLP at 600 Ω Push-pull power amplifiers with external gain adjustment with 300 Ω load capability Seven master clock rates of 256 kHz to 4.096 MHz Pin-selectable -Law and A-Law companding (compliant with ITU G.711) CODEC A/D and D/A filtering compliant with ITU G.712 Industrial temperature range (–40°C to +85°C) Four packages: 24-pin PDIP, SOG, SSOP, and TSSOP Pb-Free / RoHS package options available • • • • • • • • • -2- Digital Telephone Systems Central Office Equipment (Gateways, Switches, Routers) PBX Systems (Gateways, Switches) PABX/SOHO Systems Local Loop card SOHO Routers VoIP Terminals Enterprise Phones ISDN Terminals Analog line cards Digital Voice Recorders Publication Release Date: September, 2005 Revision A12 W6811 3. BLOCK DIAGRAM Re Int PC cei erf M ve ace Receive PCM Interface BCLKR FSR PCMR G.712 CODEC G.711 μ/A -Law Tra Int ns PC erf mitM ace Transmit PCM Interface BCLKT FST PCMT PAO+ PAOPAI RO AO AI+ AI- μ/A-Law V REF 512 kHz 256 kHz V AG 8 kHz -3- PUI VDDD VSSD Power Conditioning VDDA 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz Voltage reference Pre -scaler Saler VSSA MCLK Publication Release Date: September, 2005 Revision A12 W6811 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION ................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM............................................................................................................................... 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL DESCRIPTION............................................................................................................ 9 7.1. Transmit Path............................................................................................................................. 9 7.2. Receive Path............................................................................................................................ 10 7.3. Power Management................................................................................................................. 11 7.3.1. Analog Supply ................................................................................................................ 11 7.3.2. Digital Supply ................................................................................................................. 11 7.3.3. Analog Ground Reference Bypass................................................................................. 11 7.3.4. Analog Ground Reference Voltage Output .................................................................... 11 7.4. PCM Interface .......................................................................................................................... 11 7.4.1. Long Frame Sync ........................................................................................................... 12 7.4.2. Short Frame Sync .......................................................................................................... 12 7.4.3. GCI Interface .................................................................................................................. 12 7.4.4. IDL Interface ................................................................................................................... 13 7.4.5. System Timing................................................................................................................ 13 8. TIMING DIAGRAMS.......................................................................................................................... 14 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 21 9.1. Absolute Maximum Ratings .................................................................................................... 21 9.2. Operating Conditions .............................................................................................................. 21 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 22 10.1. General Parameters............................................................................................................... 22 10.2. Analog Signal Level and Gain Parameters............................................................................ 23 10.3. Analog Distortion and Noise Parameters............................................................................... 24 10.4. Analog Input and Output Amplifier Parameters ..................................................................... 25 10.5. Digital I/O ............................................................................................................................... 27 10.5.1. µ-Law Encode Decode Characteristics ........................................................................ 27 10.5.2. A-Law Encode Decode Characteristics........................................................................ 28 10.5.3. PCM Codes for Zero and Full Scale ............................................................................ 29 10.5.4. PCM Codes for 0dBm0 Output .................................................................................... 29 11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 30 12. PACKAGE SPECIFICATION .......................................................................................................... 32 12.1. 24L TSSOP – 4.4X7.8mm ..................................................................................................... 32 12.2. 24L SOP – 300mil.................................................................................................................. 33 12.3. 24L SSOP – 209mil ............................................................................................................... 34 12.4. 24L PDIP – 300 mil ................................................................................................................ 35 13. ORDERING INFORMATION........................................................................................................... 36 14. VERSION HISTORY ....................................................................................................................... 37 -4- Publication Release Date: September, 2005 Revision A12 W6811 5. PIN CONFIGURATION VREF 1 VREF 24 V AG VAG RO - 2 RO- AI+ 23 23 AI+ PAI 3 PAI AI 22- AI- PAO - 4 PAO - AO PAO+ VDDA 5 PAO+ AO 21 /A 20 μ 6 VDDA V 19 SSA VSSA NC VDDD 7 NC 8 VDDD NC 18 17 V SSD NC VSSD FSR 9 FSR PCMI PCMR 10 PCMI BCLKR 11 BCLKR PUI 12 PUI μ/A-Law FSX 16 16 PCMO 15 FST PCMT BCLKT 14 BCLKT MCLK 13 MCLK PDIP/SOP/SSOP/TSSOP -5- Publication Release Date: September, 2005 Revision A12 W6811 6. PIN DESCRIPTION Pin Name VREF Pin No. 1 VDD* Functionality A RO- 2 A PAI 3 A PAO- 4 A PAO+ 5 A VDDA 6 A NC VDDD 7 8 D FSR 9 D PCMR 10 D BCLKR 11 D PUI 12 D MCLK 13 D BCLKT PCMT 14 15 D D FST 16 D This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be decoupled to VSSA through a 0.1 μF ceramic decoupling capacitor. No external loads should be tied to this pin. Inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to 1.575 volt peak referenced to the analog ground level. This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage. Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced to the VAG voltage level. Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 Volt peak referenced to the VAG voltage level. Analog power supply. This pin should be decoupled to VSSA with a 0.1μF ceramic capacitor. Not Connected Digital power supply. This pin should be decoupled to VSSD with a 0.1μF ceramic capacitor. For correct operation, VDDD value should always be lower than VDDA. 8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit and receive are synchronous operations. PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins. PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is selected when this pin is tied to VSSD. The IDL mode is selected when this pin is tied to VDDD. This pin can also be tied to the BCLKT when transmit and receive are synchronous operations. Power up input signal. When this pin is tied to VDDD, the part is powered up. When tied to VSSD, the part is powered down. System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the case of 256 and 512 kHz frequencies. PCM transmit bit clock input pin. PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins. 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes. -6- Publication Release Date: September, 2005 Revision A12 W6811 Pin Name VSSD NC VSSA μ/A-Law Pin No. 17 18 19 20 VDD* Functionality D This is the digital supply ground. This pin should be connected to 0V. Not Connected A This is the analog supply ground. This pin should be connected to 0V. D Compander mode select pin. μ-Law companding is selected when this pin is tied to VDDD. A-Law companding is selected when this pin is tied to VSSD. AO 21 A Analog output of the first gain stage in the transmit path. AI22 A Inverting input of the first gain stage in the transmit path. AI+ 23 A Non-inverting input of the first gain stage in the transmit path. VAG 24 A Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal processing. This pin should be decoupled to VSSA with a 0.01μF capacitor. This pin becomes high impedance when the chip is powered down. * These columns represent whether the pin Is driven by Analog (‘A’) or Digital (‘D’) power supply. -7- Publication Release Date: September, 2005 Revision A12 W6811 7. FUNCTIONAL DESCRIPTION W6811 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a complete μLaw and A-Law compander. The μ-Law and A-Law companders are designed to comply with the specifications of the ITU-T G.711 recommendation. The block diagram in section 3 shows the main components of the W6811. The chip consists of a PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats. The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync frequency. The power conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. The main CODEC block diagram is shown in section 3. VA VAG G + - + Receive Path PAO+ PAO PAI 8 μ/Aμ/ACont Control o D/A Converter w + - fC= 3400Hz Hz Smooth Smoothing ngFilter 1 RO - Smooth Smoothing Filter ngFilter 2 Transmit Path AO 8 A/D Converter μ/Aμ/A- Control Cont ffCC == 200Hz fC== 3400Hz 3400 200 Figure 7.1 The W6811 Signal Path Hz Hz Pass High Ant --Aliasi Aliasing Ant-Aliasi High Ant --Aliasing Filt Filter Filter Pas i Filter ng ++ - AI+ AI - 7.1. TRANSMIT PATH The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain setting (see application examples in section 11). The device has an input operational amplifier whose output is the input to the encoder section. If the input amplifier is not required for operation it can be powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The input amplifier can be powered down by connecting the AI+ pin to VDDA or VSSA. The AO pin is selected as an input when AI+ is tied to VDDA and the AI- pin is selected as an input when AI+ is tied to VSSA (see Table 7.1). -8- Publication Release Date: September, 2005 Revision A12 W6811 AI+ Input Amplifier Input VDDA Powered Down AO 1.2 to VDDA-1.2 Powered Up AI+, AIVSSA Powered Down AITable 7.1 Input Amplifier Modes of operation When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the analog ground voltage VAG. The output of the input amplifier is fed through a 3.4 kHz switched capacitor low pass filter to prevent aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or A-Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression format can be selected according to Table 7.2. μ/A-Law Pin VSSA VDDA Format A-Law μ-Law Table 7.2. Pin-selectable Compression Format The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the data rate supplied by the external bit clock BCLKT. 7.2. RECEIVE PATH The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification. A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered to provide the receive output signal RO-. The RO- output can be externally connected to the PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By using external resistors (see section 11 for examples), various gain settings of this output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting PAI to VDDA. -9- Publication Release Date: September, 2005 Revision A12 W6811 7.3. POWER MANAGEMENT 7.3.1. Analog Supply The power supply for the analog part of the W6811 needs to be 5V +/- 10%. This supply voltage is connected to the VDDA pin. The VDDA pin needs to be decoupled to ground through a 0.1 μF ceramic capacitor. 7.3.2. Digital Supply The power supply for the digital part of the W6811 needs to be 3V +/- 10%. This supply voltage is connected to the VDDD pin. The VDDD pin needs to be decoupled to ground through a 0.1 μF ceramic capacitor. 7.3.3. Analog Ground Reference Bypass The system has an internal precision voltage reference which generates the 2.5V mid-supply analog ground voltage. This voltage needs to be decoupled to VSSA at the VREF pin through a 0.1 μF ceramic capacitor. 7.3.4. Analog Ground Reference Voltage Output The analog ground reference voltage is available for external reference at the VAG pin. This voltage needs to be decoupled to VSSA through a 0.01 μF ceramic capacitor. The analog ground reference voltage is generated from the voltage on the VREF pin and is also used for the internal signal processing. 7.4. PCM INTERFACE The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of operation of the interface are shown in Table 7.3. BCLKR FSR Interface Mode 64 kHz to 4.096 MHz VSSD VSSD VDDD VDDD 8 kHz Long or Short Frame Sync VSSD VDDD VSSD VDDD ISDN GCI with active channel B1 ISDN GCI with active channel B2 ISDN IDL with active channel B1 ISDN IDL with active channel B2 Table 7.3 PCM Interface mode selections 7.4.1. Long Frame Sync The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8 kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is - 10 - Publication Release Date: September, 2005 Revision A12 W6811 held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 μsec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be HIGH impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section. 7.4.2. Short Frame Sync The W6811 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the bit-clock, the W6811 starts clocking out the data on the PCMT pin, which will also change from high to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway through the LSB. The Short Frame Sync operation of the W6811 is based on an 8-bit data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section. 7.4.3. General Circuit Interface (GCI) The GCI interface mode is selected when the BCLKR pin is connected to VSSD for two or more frame sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK. The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section. - 11 - Publication Release Date: September, 2005 Revision A12 W6811 7.4.4. Interchip Digital Link (IDL) The IDL interface mode is selected when the BCLKR pin is connected to VDDD for two or more frame sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not used for data transmission and also in the time slot of the unused channels. For more timing information, see the timing section. 7.4.5. System Timing The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz master clock rates. The system clock is supplied through the master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and an 8 kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W6811 will enter the low power standby mode. Another way to power down is to set the PUI pin to LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become low impedance. - 12 - Publication Release Date: September, 2005 Revision A12 W6811 8. TIMING DIAGRAMS TFTRHM TFTRSM TMCKL TMCKH TRISE TFALL MCLK TMCK TFS TFSL FST TFTRH BCLKT 0 TFTRS 1 TFTFH 2 3 TFDTD TBCKH 4 5 6 7 TBDTD PCMT D7 D6 8 THID D5 D4 D3 D2 TBCKL 0 1 TBCK THID D1 D0 MSB LSB TFS TFSL FSR TFRRH BCLKR 0 TFRRS 1 TFRFH 2 3 TBCKH 4 5 6 7 8 TBCKL 0 1 TBCK PCMR D7 MSB TDRS D6 D5 D4 D3 D2 D1 D0 LSB TDRH Figure 8.1 Long Frame Sync PCM Timing - 13 - Publication Release Date: September, 2005 Revision A12 W6811 SYMBOL 1/TFS TFSL 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFDTD TBDTD THID TFRRH TFRRS TFRFH TDRS TDRH 1 DESCRIPTION MIN TYP FST, FSR Frequency --8 FST / FSR Minimum LOW Width 1 TBCK BCLKT, BCLKR Frequency 64 --BCLKT, BCLKR HIGH Pulse Width 50 --BCLKT, BCLKR LOW Pulse Width 50 --BCLKT 0 Falling Edge to FST Rising 20 --Edge Hold Time FST Rising Edge to BCLKT 1 Falling 80 --edge Setup Time BCLKT 2 Falling Edge to FST Falling 50 --Edge Hold Time FST Rising Edge to Valid PCMT Delay ----Time BCLKT Rising Edge to Valid PCMT ----Delay Time Delay Time from the Later of FST 10 --Falling Edge, or BCLKT 8 Falling Edge to PCMT Output High Impedance BCLKR 0 Falling Edge to FSR Rising 20 --Edge Hold Time FSR Rising Edge to BCLKR 1 Falling 80 --edge Setup Time BCLKR 2 Falling Edge to FSR Falling 50 --Edge Hold Time Valid PCMR to BCLKR Falling Edge 0 --Setup Time PCMR Hold Time from BCLKR Falling 50 --Edge Table 8.1 Long Frame Sync PCM Timing Parameters MAX --4096 ------- UNIT kHz sec kHz ns ns ns --- ns --- ns 60 ns 60 ns 60 ns --- ns --- ns --- ns --- ns --- ns TFSL must be at least ≥ TBCK - 14 - Publication Release Date: September, 2005 Revision A12 W6811 TFTRHM TFTRSM TMCKL TMCKH TRISE TFALL MCLK TMCK TFS TFTFH TFTFS FST TFTRS TFTRH BCLKT -1 0 TBCKH 1 2 3 TBDTD D7 PCMT 4 5 6 7 0 8 TBDTD D6 D5 TBCKL TBCK THID D4 D3 D2 1 D1 D0 MSB LSB TFS TFRFH TFRFS FSR TFRRS TFRRH BCLKR -1 0 TBCKH 1 2 3 4 5 6 7 TBCKL 0 8 1 TBCK PCMR D7 MSB TDRS D6 D5 D4 D3 D2 D1 D0 LSB TDRH Figure 8.2 Short Frame Sync PCM Timing - 15 - Publication Release Date: September, 2005 Revision A12 W6811 SYMBOL 1/TFS 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFTFS TBDTD THID TFRRH TFRRS TFRFH TFRFS TDRS TDRH DESCRIPTION FST, FSR Frequency BCLKT, BCLKR Frequency BCLKT, BCLKR HIGH Pulse Width BCLKT, BCLKR LOW Pulse Width BCLKT –1 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 0 Falling edge Setup Time BCLKT 0 Falling Edge to FST Falling Edge Hold Time FST Falling Edge to BCLKT 1 Falling Edge Setup Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from BCLKT 8 Falling Edge to PCMT Output High Impedance BCLKR –1 Falling Edge to FSR Rising Edge Hold Time FSR Rising Edge to BCLKR 0 Falling edge Setup Time BCLKR 0 Falling Edge to FSR Falling Edge Hold Time FSR Falling Edge to BCLKR 1 Falling Edge Setup Time Valid PCMR to BCLKR Falling Edge Setup Time PCMR Hold Time from BCLKR Falling Edge MIN --64 50 50 20 TYP 8 --------- MAX --4096 ------- UNIT kHz kHz ns ns ns 80 --- --- ns 50 50 ----- ----- ns ns 10 10 ----- 60 60 ns ns 20 --- --- ns 80 --- --- ns 50 50 ----- ----- ns ns 0 50 ----- ----- ns ns Table 8.2 Short Frame Sync PCM Timing Parameters - 16 - Publication Release Date: September, 2005 Revision A12 W6811 TFS FST TFSFH TFSRS TFSRH BCLKT -1 0 1 TBCKH 2 3 4 TBDTD PCMT 5 6 8 9 THID TBDTD D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB TDRS PCMR 7 10 11 12 13 14 LSB 17 18 THID TBDTD D7 D6 D5 D4 D3 D2 D1 D0 LSB MSB TDRS D7 D6 D5 D4 D3 D2 D1 D0 16 TBCK TBDTD TDRH MSB 15 TBCKL TDRH D7 D6 D5 D4 D3 D2 MSB D1 D0 LSB BCH = 0 B1 Channel BCH = 1 B2 Channel Figure 8.3 IDL PCM Timing SYMBOL 1/TFS 1/TBCK TBCKH TBCKL TFSRH TFSRS TFSFH TBDTD THID TDRS TDRH DESCRIPTION FST Frequency BCLKT Frequency BCLKT HIGH Pulse Width BCLKT LOW Pulse Width BCLKT –1 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 0 Falling edge Setup Time BCLKT 0 Falling Edge to FST Falling Edge Hold Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the BCLKT 8 Falling Edge (B1 channel) or BCLKT 18 Falling Edge (B2 Channel) to PCMT Output High Impedance Valid PCMR to BCLKT Falling Edge Setup Time PCMR Hold Time from BCLKT Falling Edge MIN --256 50 50 20 TYP 8 --------- MAX --4096 ------- UNIT kHz kHz ns ns ns 60 --- --- ns 20 --- --- ns 10 --- 60 ns 10 --- 50 ns 20 --- --- ns 75 --- --- ns Table 8.3 IDL PCM Timing Parameters - 17 - Publication Release Date: September, 2005 Revision A12 W6811 TFS FST TFSFH TFSRS TFSRH TBCKH TBCKL BCLKT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 TFDTD PCMT TBDTD D7 D6 D5 D4 D3 D2 D1 D0 TBDTD TDRS D7 D6 D5 D4 D3 D2 D1 D0 LSB TDRS TDRH TDRH D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 MSB D1 D0 LSB MSB BCH = 0 B1 Channel THID TBDTD TBCK LSB MSB MSB PCMR THID LSB BCH = 1 B2 Channel Figure 8.4 GCI PCM Timing SYMBOL 1/TFST 1/TBCK TBCKH TBCKL TFSRH TFSRS TFSFH TFDTD TBDTD THID TDRS TDRH DESCRIPTION FST Frequency BCLKT Frequency BCLKT HIGH Pulse Width BCLKT LOW Pulse Width BCLKT 0 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 1 Falling edge Setup Time BCLKT 1 Falling Edge to FST Falling Edge Hold Time FST Rising Edge to Valid PCMT Delay Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the BCLKT 16 Falling Edge (B1 channel) or BCLKT 32 Falling Edge (B2 Channel) to PCMT Output High Impedance Valid PCMR to BCLKT Rising Edge Setup Time PCMR Hold Time from BCLKT Rising Edge MIN --512 50 50 20 TYP 8 --------- MAX --6176 ------- UNIT kHz kHz ns ns ns 60 --- --- ns 20 --- --- ns ----10 ------- 60 60 50 ns ns ns 20 --- ----- --60 ns ns Table 8.4 GCI PCM Timing Parameters - 18 - Publication Release Date: September, 2005 Revision A12 W6811 SYMBOL 1/TMCK DESCRIPTION Master Clock Frequency MIN --- TMCKH / TMCK TMCKH MCLK Duty Cycle for 256 kHz Operation Minimum Pulse Width HIGH for MCLK(512 kHz or Higher) Minimum Pulse Width LOW for MCLK (512 kHz or Higher) MCLK falling Edge to FST Rising Edge Hold Time FST Rising Edge to MCLK Falling edge Setup Time Rise Time for All Digital Signals Fall Time for All Digital Signals 45% 50 TMCKL TFTRHM TFTRSM TRISE TFALL TYP 256 512 1536 1544 2048 2560 4096 MAX --- UNIT kHz --- 55% --- ns 50 --- --- ns 50 --- --- ns 50 --- --- ns ----- ----- 50 50 ns ns Table 8.5 General PCM Timing Parameters - 19 - Publication Release Date: September, 2005 Revision A12 W6811 9. ABSOLUTE MAXIMUM RATINGS 9.1. ABSOLUTE MAXIMUM RATINGS Condition Value Junction temperature 1500C Storage temperature range -650C to +1500C Voltage Applied to any pin Analog (VSSA - 0.3V) to (VDDA + 0.3V) (VSSD - 0.3V) to (VDDD + 0.3V) Analog Digital (VSSA – 1.0V) to (VDDA + 1.0V) (VSSD – 1.0V) to (VDDD + 1.0V) Digital Voltage applied to any pin (Input current limited to +/-20 mA) VDDA - VSSA ; VDDD - VSSD VDDD – -0.5V to +6V VDDA2 < 0.3V 1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. 2. At any time, the digital power supply should not be higher the 0.3V from the analog power supply. 9.2. OPERATING CONDITIONS Condition Value 0 0 Industrial operating temperature -40 C to +85 C Analog supply voltage (VDDA) +4.5V to +5.5V Digital supply voltage (VDDD) +2.7V to +3.3V Ground voltage (VSSA, VSSD) 0V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. - 20 - Publication Release Date: September, 2005 Revision A12 W6811 10. ELECTRICAL CHARACTERISTICS 10.1. GENERAL PARAMETERS Min (2) Symbo l Parameters VIL Input LOW Voltage VIH Input HIGH Voltage VOL PCMT Output LOW Voltage IOL = 1.6 mA VOH PCMT Output HIGH Voltage IOL = -1.6 mA IDDA IDDD VDDA Current (Operating) -ADC+DAC ISBA ISBD VCCA Current (Standby) PUI = 1 FSX running MCLK running PUI = 1 FSX = 0 MCLK running IPDA IPDD VCCA Current (Power Down) VCCD Current (Power Down) PUI = 0 PUI = 0 IIL Input Leakage Current IOL PCMT Output Leakage Current CIN Digital Input Capacitance COUT PCMT Output Capacitance 1. 2. Conditions Typ (1) Max (2) Units 0.5 V 2.2 V 0.4 VDDD – 0.5 V V 5.5 25 8 1000 mA μA 200 0.2 500 100 nA μA 200 200 500 500 nA nA VSSD<VIN<VDDD +/-10 μA VSSA<PCMT<VDDA High Z State +/-10 μA 10 pF 15 pF PCMT High Z Typical values: TA = 25°C , VDDA = 5.0 V, VDDD = 3.0 V All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. - 21 - Publication Release Date: September, 2005 Revision A12 W6811 10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS VDDA=5V ±10%; VSSA=0V; TA=-40°C to +85°C; all analog signals referred to VAG; MCLK=BCLK= 2.048 MHz; FST=FSR=8kHz Synchronous operation. PARAMETER SYM. CONDITION TYP. Absolute Level Max. Transmit Level Absolute Gain (0 dBm0 @ 1020 Hz; TA=+25°C) Absolute Gain variation with Temperature Frequency Response, Relative to 0dBm0 @ 1020 Hz LABS TXMAX 0 dBm0 = 0dBm @ 600Ω 3.17 dBm0 for μ-Law 3.14 dBm0 for A-Law 0 dBm0 @ 1020 Hz; TA=+25°C 1.096 1.579 1.573 0 GABST TA=0°C to TA=+70°C TA=-40°C to TA=+85°C GRTV Gain Variation vs. Level Tone (1020 Hz relative to –10 dBm0) GLT 15 Hz 50 Hz 60 Hz 200 Hz 300 to 3000 Hz 3300 Hz 3400 Hz 3600 Hz 4000 Hz 4600 Hz to 100 kHz +3 to –40 dBm0 -40 to –50 dBm0 -50 to –55 dBm0 GABS TRANSMIT (A/D) MIN. MAX. -------------0.25 +0.25 RECEIVE (D/A) MIN. MAX. -------------0.25 +0.25 0 -0.03 -0.05 +0.03 +0.05 -0.03 -0.05 +0.03 +0.05 dB --------------------------- -------1.0 -0.20 -0.35 -0.8 -------0.3 -0.6 -1.6 -40 -30 -26 -0.4 +0.15 +0.15 0 0 -14 -32 +0.3 +0.6 +1.6 -0.5 -0.5 -0.5 -0.5 -0.20 -0.35 -0.8 -------0.2 -0.4 -1.6 0 0 0 0 +0.15 +0.15 0 0 -14 -30 +0.2 +0.4 +1.6 dB - 22 - UNIT VPK VPK VPK dB dB Publication Release Date: September, 2005 Revision A12 W6811 10.3. ANALOG DISTORTION AND NOISE PARAMETERS VDDA=5V ±10%; VSSA=0V; TA=-40°C to +85°C; all analog signals referred to VAG; MCLK=BCLK= 2.048 MHz; FST=FSR=8kHz Synchronous operation. PARAMETER SYM. CONDITION Total Distortion vs. Level Tone (1020 Hz, μ-Law, C-Message Weighted) Total Distortion vs. Level Tone (1020 Hz, A-Law, Psophometric Weighted) Spurious Out-Of-Band at RO- (300 Hz to 3400 Hz @ 0dBm0) DLTμ Spurious In-Band (700 Hz to 1100 Hz @ 0dBm0) Intermodulation Distortion (300 Hz to 3400 Hz –4 to –21 dBm0 Crosstalk (1020 Hz @ 0dBm0) Absolute Group Delay Group Delay Distortion (relative to group delay @ 1200 Hz) DSPI +3 dBm0 0 dBm0 to -30 dBm0 -40 dBm0 -45 dBm0 +3 dBm0 0 dBm0 to -30 dBm0 -40 dBm0 -45 dBm0 4600 Hz to 7600 Hz 7600 Hz to 8400 Hz 8400 Hz to 100000 Hz 300 to 3000 Hz DIM Two tones Idle Channel Noise NIDL DLTA DSPO DXT τABS τD 1200 Hz 500 Hz 600 Hz 1000 Hz 2600 Hz 2800 Hz μ-Law; C-message A-Law; Psophometric TRANSMIT (A/D) MIN. TYP. MA X. 36 ----36 ----29 ----25 ----36 ----36 ----29 ----25 ----------------------- RECEIVE (D/A) MIN. TYP. MAX. UNIT 34 36 30 25 34 36 30 25 ------- ----------------------- -----------------30 -40 -30 dBC dBp dB --- --- -47 --- --- -47 dB --- --- -41 --- --- -41 dB --- --- -75 --- --- -75 dBm0 ----------------- ----------------- 360 750 380 130 130 750 18 -68 ----------------- ----------------- 240 750 370 120 120 750 13 -78 μsec μsec - 23 - dBrnc0 dBm0p Publication Release Date: September, 2005 Revision A12 W6811 10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS VDDA=5V ±10%; VSSA=0V; TA=-40°C to +85°C; all analog signals referred to VAG; PARAMETER AI Input Offset Voltage AI Input Current AI Input Resistance AI Input Capacitance AI Common Mode Input Voltage Range AI Common Mode Rejection Ratio AI Amp Gain Bandwidth Product AI Amp DC Open Loop Gain AI Amp Equivalent Input Noise AO Output Voltage Range SYM. VOFF,AI IIN,AI RIN,AI CIN,AI VCM,AI CONDITION AI+, AIAI+, AIAI+, AI- to VAG AI+, AIAI+, AI- MIN. ----10 --1.2 TYP. --±0.1 ------- MAX. ±25 ±1.0 --10 VDDA-1.2 CMRRTI AI+, AI- --- 60 --- dB GBWTI AO, RLD≥10kΩ --- 2150 --- kHz GTI NTI AO, RLD≥10kΩ C-Message Weighted RLD=10kΩ to VAG RLD=2kΩ to VAG AO, RO to VAG AO, RO 0.5 ≤AO,RO-≤ VDDA-0.5 RO-, 0 to 3400 Hz RO- to VAG Relative to VSSA Within ±25mV change Transmit Receive ----- 95 -24 ----- dB dBrnC 0.5 1.0 2 --±1.0 ----------- VDDA-0.5 VDDA-1.0 --100 --- Load Resistance Load Capacitance AO & RO Output Current RLDTGRO CLDTGRO IOUT1 RO- Output Resistance RRO- --- 1 --- RO- Output Offset Voltage Analog Ground Voltage VAG Output Resistance VOFF,ROVAG RVAG --2.429 --- --2.5 2.5 ±25 2.573 12.5 mV V Ω Power Supply Rejection Ratio (0 to 100 kHz to VDDA, Cmessage) PAI Input Offset Voltage PAI Input Current PAI Input Resistance PAI Amp Gain Bandwidth Product PSRR 30 30 80 75 ----- dBC ----10 --- --±0.05 --1000 ±20 ±1.0 ----- mV μA MΩ kHz VTG VOFF,PAI IIN,PAI RIN,PAI GBWPI PAI PAI PAI to VAG PAO- no load - 24 - UNIT. mV μA MΩ pF V V kΩ pF mA Ω Publication Release Date: September, 2005 Revision A12 W6811 PARAMETER Output Offset Voltage Load Resistance SYM. VOFF,PO RLDPO Load Capacitance CLDPO PO Output Current IOUTPO PO Output Resistance PO Differential Gain RPO GPO PO Differential Signal to Distortion C-Message weighted DPO PO Power Supply Rejection Ratio (0 to 25 kHz to VDDA, Differential out) PSRRPO CONDITION PAO+ to PAOPAO+, PAOdifferentially PAO+, PAOdifferentially 0.5 ≤AO,RO-≤ VDDA-0.5 PAO+ to PAORLD=300Ω, +3dBm0, 1 kHz, PAO+ to PAOZLD=300Ω ZLD=100nF + 100Ω ZLD=100nF + 20Ω 0 to 4 kHz 4 to 25 kHz - 25 - MIN. --300 TYP. ----- MAX. ±50 --- UNIT. mV Ω --- --- 1000 pF ±10.0 --- --- mA ---0.2 1 0 --+0.2 Ω dB 45 --- 60 40 ----- dBC --40 --- 40 55 40 ------- dB Publication Release Date: September, 2005 Revision A12 W6811 10.5. DIGITAL I/O 10.5.1. μ-Law Encode Decode Chatacteristics Normalized Encode Decision Levels 8159 7903 : 4319 4063 : 2143 2015 : 1055 991 : 511 479 : 239 223 : 103 95 : 35 31 : 3 1 0 Digital Code D4 D3 Chord Step D7 Sign D6 Chord D5 Chord 1 0 0 0 1 0 0 1 0 1 Normalized Decode Levels D2 Step D1 Step D0 Step 0 0 0 0 8031 : 0 1 1 1 1 4191 : 0 1 1 1 1 1 2079 : 0 1 0 1 1 1 1 1023 : 1 0 1 1 1 1 1 1 495 : 1 1 0 0 1 1 1 1 231 : 1 1 0 1 1 1 1 1 99 : 1 1 1 0 1 1 1 1 33 : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 2 0 Notes: Sign bit = 0 for negative values, sign bit = 1 for positive values - 26 - Publication Release Date: September, 2005 Revision A12 W6811 10.5.2. A-Law Encode Decode Characteristics Normalized Encode Decision Levels 4096 3968 : 2048 2048 : 1088 1024 : 544 512 : 272 256 : 136 128 : 68 64 : 2 0 Digital Code D4 D3 Chord Step D7 Sign D6 Chord D5 Chord 1 0 1 0 1 0 1 1 0 1 Normalized Decode Levels D2 Step D1 Step D0 Step 1 0 1 0 4032 : 0 0 1 0 1 2112 : 1 1 0 1 0 1 1056 : 0 0 0 0 1 0 1 528 : 1 0 0 1 0 1 0 1 264 : 1 1 1 0 0 1 0 1 132 : 1 1 1 0 0 1 0 1 66 : 1 1 0 1 0 1 0 1 1 Notes: 1. Sign bit = 0 for negative values, sign bit = 1 for positive values 2. Digital code includes inversion of all even number bits - 27 - Publication Release Date: September, 2005 Revision A12 W6811 10.5.3. PCM Codes for Zero and Full Scale Level + Full Scale + Zero - Zero - Full Scale Sign bit (D7) 1 1 0 0 μ-Law Chord bits (D6,D5,D4) 000 111 111 000 Step bits (D3,D2,D1,D0) 0000 1111 1111 0000 Sign bit (D7) 1 1 0 0 A-Law Chord bits (D6,D5,D4) 010 101 101 010 Step bits (D3,D2,D1,D0) 1010 0101 0101 1010 Sign bit (D7) 0 0 0 0 1 1 1 1 A-Law Chord bits (D6,D5,D4) 011 010 010 011 011 010 010 011 Step bits (D3,D2,D1,D0) 0100 0001 0001 0100 0100 0001 0001 0100 10.5.4. PCM Codes for 0dBm0 Output Sample 1 2 3 4 5 6 7 8 Sign bit (D7) 0 0 0 0 1 1 1 1 μ-Law Chord bits (D6,D5,D4) 001 000 000 001 001 000 000 001 Step bits (D3,D2,D1,D0) 1110 1011 1011 1110 1110 1011 1011 1110 - 28 - Publication Release Date: September, 2005 Revision A12 W6811 11. TYPICAL APPLICATION CIRCUIT +5VDC +3VDC AO 27K 22 23 AI+ 27K 0.1 uF 0.01 uF MCLK 24 1 VAG VREF 2 RO- 27K 3 27K PCMR BCLKR FSR 8 KHz Frame Sy nc 2.048 MHz Bit Clock 13 PCM OUT 10 11 9 PCM IN PAI 4 PAO- 5 PAO+ DIFFERENTIAL AUDIO OUT RL > 150 ohms + 17 W6811 u/A PUI VSSA 27K 16 14 15 MODE SELECT 20 12 POWER CONTROL 19 1.0 uF FST BCLKT PCMT AI- VSSD DIFFERENTIAL AUDIO IN + VDDD 21 1.0 uF VDDA 27K 8 0.1 uF 6 0.1 uF Figure 11.1 Typical circuit for Differential Analog I/O’s +5VDC +3VDC 23 27K 1.0 uF 27K 24 1 0.01 uF 0.1 uF AUDIO OUT RL > 2K ohms 2 27K 3 27K 4 5 AUDIO OUT RL > 150 ohms 100 uF VDDD FST BCLKT PCMT AIAI+ MCLK VAG VREF PCMR BCLKR FSR RO- 16 14 15 8 KHz Frame Sy nc 2.048 MHz Bit Clock 13 PCM OUT 10 11 9 PCM IN PAI PAOPAO+ W6811 VSSD AUDIO IN AO VSSA 22 u/A PUI 20 12 MODE SELECT POWER CONTROL 19 27K 17 21 1.0 uF VDDA 27K 8 0.1 uF 6 0.1 uF Figure 11.2 Typical circuit for Single Ended Analog I/O’s - 29 - Publication Release Date: September, 2005 Revision A12 W6811 +5VDC 1.0 uF 3.9K 23 100pF ELECTRET MICROPHONE 0.01 uF 0.1 uF 62K 24 1 2 27K 27K 3 1.5K 27K 4 5 AO VDDD 22 FST BCLKT PCMT AIAI+ MCLK VAG VREF PCMR BCLKR FSR RO- 16 14 15 8 KHz Frame Sy nc 2.048 MHz Bit Clock 13 PCM OUT 10 11 9 PCM IN PAI PAOPAO+ W6811 u/A PUI VSSA 100pF 20 12 MODE SELECT POWER CONTROL 19 3.9K VSSD 21 1.0 uF VDDA 62K 8 0.1 uF 6 0.1 uF 22 uF + +3VDC 1K 17 1.5K SPEAKER Figure 11.3 Handset Interface +5VDC +3VDC 0.01 uF 0.1 uF 24 1 27K 2 TRANSFORMER 600 OHM 1:1 3 27K 4 5 VDDD AI+ MCLK VAG VREF PCMR BCLKR FSR RO- 16 14 15 PAOPAO+ W6811 8 KHz Frame Sy nc 2.048 MHz Bit Clock 13 PCM OUT 10 11 9 PCM IN B1/B2 SELECT PAI VSSA 600 23 FST BCLKT PCMT AI- u/A PUI 20 12 MODE SELECT POWER CONTROL 19 1.0 uF AO VSSD 22 17 21 27K VDDA 27K 8 0.1 uF 6 0.1 uF Figure 11.4 Transformer Interface Circuit in GCI mode - 30 - Publication Release Date: September, 2005 Revision A12 W6811 12. PACKAGE SPECIFICATION 12.1. 24L TSSOP - 4.4X7.8MM PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS SYMBOL A A1 A2 L E HE D b c L1 e 01 MIN 0.05 0.80 0.50 4.30 7.70 0.19 0.09 DIMENSION IN MM NOM 0.90 0.60 6.40 BSC. 4.40 7.80 MAX 1.20 0.15 1.05 0.75 MIN 0.002 0.031 0.020 4.50 7.90 0.30 0.20 0.169 0.303 0.007 0.004 8 0 1.0 REF. 0.65 BSC. 0 DIMENSION IN INCH NOM MAX 0.043 0.006 0.035 0.041 0.024 0.030 0.252 BSC. 0.173 0.177 0.307 0.311 0.012 0.008 0.039 REF 0.026 BSC 8 Publication Release Date: September, September, 2005 - 31 Revision A12 W6811 12.2. 24L SOP-300MIL SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS 11 20 c E HE L 10 1 D 0.25 O A Y SEATING SEATING PLANE PLANE GAUGE PLANE e GAUGE PLANE A1 b SYMBOL A A1 b c E D e HE Y L 0 DIMENSIONS IN MM MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 7.40 7.60 12.60 13.00 1.27 BSC. 10.00 1065 0.10 0.40 1.27 0 8 DIMENSIONS IN INCH MIN MAX 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.013 0.291 0.299 0.946 0.512 0.050 BSC. 0.394 0.419 0.004 0.016 0.050 0 8 Publication Release Date: September, September, 2005 - 32 Revision A12 W6811 12.3. 24L SSOP-209 MIL SHRINK SMALL OUTLINE PACKAGE DIMENSIONS Publication Release Date: September, September, 2005 - 33 Revision A12 W6811 12.4. 24L PDIP – 300 MIL PLASTIC DUAL INLINE PACKAGE DIMENSIONS D 24 13 1 12 1 E E S c 1 2 AA A L Base Plane Mounting Plane B e1 SYMBOL A A1 A2 B B1 c D E E1 e1 L á eA S MIN 0.25 3.18 0.41 1.47 0.20 7.37 6.43 2.29 3.05 0° 8.38 DIMENSION IN MM NOM 3.30 0.46 1.52 0.25 31.95 7.62 6.55 2.54 3.30 8.89 eA á B1 MAX 4.45 3.43 0.56 1.63 0.36 32.26 7.87 6.68 2.79 3.56 15° 9.40 2.29 MIN 0.010 0.125 0.016 0.058 0.008 0.290 0.253 0.090 0.120 0° 0.330 DIMENSION IN INCH NOM MAX 0.175 0.130 0.018 0.060 0.010 1.258 0.300 0.258 0.100 0.130 0.350 0.135 0.022 0.064 0.014 1.270 0.310 0.263 0.110 0.140 15° 0.370 0.090 Publication Release Date: September, September, 2005 - 34 Revision A12 W6811 13. ORDERING INFORMATION Winbond Part Number Description W6811I _ _ Product Family W6811 Product Package Material: Blank = Standard Package G = Pb-free (RoHS) Package Package Type: W = 24-Lead Plastic Thin Small Outline Package (TSSOP) Type 1 S = 24-Lead Plastic Small Outline Package (SOG/SOP) R = 24-Lead Plastic Small Outline Package (SSOP) E = 24-Lead Plastic Dual Inline Package (PDIP) When ordering W6811 series devices, please refer to the following part numbers. Part Number W6811IW W6811IS W6811IR W6811IE W6811IWG W6811ISG W6811IRG W6811IEG Publication Release Date: September, September, 2005 - 35 Revision A12 W6811 14. VERSION HISTORY VERSION DATE PAGE DESCRIPTION A7 August 9, 2002 A8 September 26, 2002 A9 October 10, 2002 A10 October 23, 2003 34 Changed the package dimension of the SSOP24 package A11 April 2005 41 Add Important Notice A12 September, 2005 2 11, 12 22 23 23 29, 30 35 Preliminary Added reference to Pb-free RoHS packaging Capitalized logic HIGH/LOW Extended conditions on Table 10.2. Extended conditions on Table 10.3. Corrected Idle Channel Noise min/max and units. Improved Application Diagrams Added G package ordering code Publication Release Date: September, September, 2005 - 36 Revision A12 W6811 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. The information contained in this datasheet may be subject to change without notice. It is the responsibility of the customer to check the Winbond USA website (www.winbond-usa.com) periodically for the latest version of this document, and any Errata Sheets that may be generated Publication Release Date: September, September, 2005 - 37 Revision A12