W989D6CB / W989D2CB 512Mb Mobile LPSDR TABLE OF CONTENTS 1. GENERAL DESCRIPTION .......................................................................................................... 3 2. FEATURES .................................................................................................................................. 3 3. PIN CONFIGURATION ................................................................................................................ 4 3.1 Ball Assignment: LPSDR X 16 ............................................................................................................ 4 3.2 Ball Assignment: LPSDR X 32 ............................................................................................................ 4 4. PIN DESCRIPTION...................................................................................................................... 5 4.1 Signal Description ............................................................................................................................... 5 4.2 Addressing Table ................................................................................................................................ 5 5. BLOCK DIAGRAM ...................................................................................................................... 6 6. ELECTRICAL CHARACTERISTICS ........................................................................................... 7 6.1 Absolute Maximum Ratings ................................................................................................................ 7 6.2 Operating Conditions .......................................................................................................................... 7 6.3 Capacitance ........................................................................................................................................ 7 6.4 DC Characteristics .............................................................................................................................. 8 6.5 Automatic Temperature Compensated Self Refresh Current Feature .............................................. 10 6.6 AC Characteristics And AC Operating Conditions ............................................................................ 11 6.6.1 AC Characteristics.................................................................................................................................... 11 6.6.2 AC Test Condition .................................................................................................................................... 12 6.6.3 AC Latency Characteristics ...................................................................................................................... 13 7. FUNCTION DESCRIPTION ....................................................................................................... 14 7.1 Command Function ........................................................................................................................... 14 7.1.1Table 1. Truth Table .................................................................................................................................. 14 7.1.2 Functional Truth Table ............................................................................................................................. 15 7.1.3 Function Truth Table for CKE .................................................................................................................. 18 7.1.4 Bank Activate Command .......................................................................................................................... 19 7.1.5 Bank Precharge Command ...................................................................................................................... 19 7.1.6 Precharge All Command .......................................................................................................................... 19 7.1.7 Write Command ....................................................................................................................................... 19 7.1.8 Write with Auto Precharge Command ...................................................................................................... 19 7.1.9 Read Command ....................................................................................................................................... 19 7.1.10 Read with Auto Precharge Command.................................................................................................... 19 7.1.11 Extended Mode Register Set Command ............................................................................................... 19 7.1.12 Mode Register Set Command ................................................................................................................ 20 7.1.13 No-Operation Command ........................................................................................................................ 20 7.1.14 Burst Stop Command ............................................................................................................................. 20 7.1.15 Device Deselect Command.................................................................................................................... 20 7.1.16 Auto Refresh Command ......................................................................................................................... 20 7.1.17 Self Refresh Entry Command ................................................................................................................ 20 7.1.18 Self Refresh Exit Command ................................................................................................................... 20 7.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command ......................................................... 20 7.1.20 Clock Suspend Mode Exit / Power Down Mode Exit Command ............................................................ 20 7.1.21 Data Write/Output Enable, Data Mask/Output Disable Command ........................................................ 21 8.OPERATION ............................................................................................................................... 21 8.1 Read Operation ................................................................................................................................. 21 8.2 Write Operation ................................................................................................................................. 21 8.3 Precharge ......................................................................................................................................... 22 8.3.1 Auto Precharge ........................................................................................................................................ 22 8.3.2 READ with auto precharge interrupted by a READ (with or without auto precharge) ............................. 22 8.3.3 READ with auto precharge interrupted by a WRITE (with or without auto precharge) ............................ 23 8.3.4 WRITE with auto precharge interrupted by a READ (with or without auto precharge) ............................ 24 8.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) .......................... 25 - 1- Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.4 Burst Termination .............................................................................................................................. 26 8.5 Mode Register Operation .................................................................................................................. 27 8.5.1 Burst Length field (A2~A0) ....................................................................................................................... 27 8.5.2 Addressing Mode Select (A3) .................................................................................................................. 27 8.5.3 Addressing Sequence for Sequential Mode ............................................................................................. 28 8.5.4 Addressing Sequence for Interleave Mode .............................................................................................. 28 8.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13) .......................................... 29 8.5.6 Read Cycle CAS Latency = 3 ................................................................................................................ 29 8.5.7 CAS Latency field (A6~A4) ................................................................................................................... 30 8.5.8 Mode Register Definition .......................................................................................................................... 30 8.6 Extended Mode Register Description................................................................................................ 31 8.7 Simplified State Diagram................................................................................................................... 32 9. CONTROL TIMING WAVEFORMS ........................................................................................... 33 9.1 Command Input Timing ..................................................................................................................... 33 9.2 Read Timing ...................................................................................................................................... 34 9.3 Control Timing of Input Data (x16) .................................................................................................... 35 9.4 Control Timing of Output Data (x16) ................................................................................................. 36 9.5 Control Timing of Input Data (x32) .................................................................................................... 37 9.6 Control Timing of Output Data (x32) ................................................................................................. 38 9.7 Mode register Set (MRS) Cycle ........................................................................................................ 39 9.8 Extended Mode register Set (EMRS) Cycle ...................................................................................... 40 10. OPERATING TIMING EXAMPLE ............................................................................................ 41 10.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)....................................................... 41 10.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)............................ 42 10.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)....................................................... 43 10.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge)............................ 44 10.5 Interleaved Bank Write (Burst Length = 8) ...................................................................................... 45 10.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) ........................................................... 46 10.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ............................................................... 47 10.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) .................................................... 48 10.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)......................................................... 49 10.10 Auto Precharge Write (Burst Length = 4) ...................................................................................... 50 10.11 Auto Refresh Cycle ....................................................................................................................... 51 10.12 Self Refresh Cycle ........................................................................................................................ 52 10.13 Power Down Mode ........................................................................................................................ 53 10.14 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ............................................ 54 10.15 Deep Power Down Mode Entry ..................................................................................................... 55 10.16 Deep Power Down Mode Exit ....................................................................................................... 56 10.17 Auto Precharge Timing (Read Cycle) ........................................................................................... 57 10.18 Auto Precharge Timing (Write Cycle)............................................................................................ 58 10.19 Timing Chart of Read to Write Cycle............................................................................................. 59 10.20 Timing Chart for Write to Read Cycle ........................................................................................... 59 10.21 Timing Chart for Burst Stop Cycle (Burst Stop Command) ........................................................... 60 10.22 Timing Chart for Burst Stop Cycle (Precharge Command) ........................................................... 60 10.23 CKE/DQM Input Timing (Write Cycle) ........................................................................................... 61 10.24 CKE/DQM Input Timing (Read Cycle)........................................................................................... 62 11. PACKAGE DIMENSION .......................................................................................................... 63 11.1 : LPSDR X 16 .................................................................................................................................. 63 11.2 : LPSDR X 32 .................................................................................................................................. 64 12.ORDERING INFORMATION .................................................................................................... 65 13. REVISION HISTORY ............................................................................................................... 66 - 2- Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 1. GENERAL DESCRIPTION The Winbond 512Mb Low Power SDRAM is a low power synchronous memory containing 536,870,912 memory cells fabricated with Winbond high performance process technology. It is designed to consume less power than the ordinary SDRAM with low power features essential for applications which use batteries. It is available in two organizations: 4,194,304-words × 4 banks × 32 bits or 8,388,608 words × 4 banks × 16 bits. The device operates in a fully synchronous mode, and the output data are synchronized to positive edges of the system clock and is capable of delivering data at clock rate up to 166MHz. The device supports special low power functions such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh (ATCSR). The Low Power SDRAM is suitable for 2.5G / 3G cellular phone, PDA, digital still camera, mobile game consoles and other handheld applications where large memory density and low power consumption are required. The device operates from 1.8V power supply, and supports the 1.8V LVCMOS bus interface. 2. FEATURES Power supply VDD = 1.7V~1.95V CAS Latency: 2 and 3 VDDQ = 1.7V~1.95V Burst Length: 1, 2, 4, 8, and full page Frequency : 166MHz(-6),133MHz(-75) Refresh: 8K refresh cycle / 64ms Programmable Partial Array Self Refresh Interface: LVCMOS Power Down Mode Support package : Deep Power Down Mode (DPD) Programmable output buffer driver strength Automatic Temperature Compensated Self Refresh 54 balls VFBGA (x16) 90 balls VFBGA (x32) Operating Temperature Range Extended (-25°C ~ +85°C) Industrial (-40°C ~ +85°C) - 3- Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 3. PIN CONFIGURATION 3.1 Ball Assignment: LPSDR X 16 54Ball FBGA 1 2 3 A VSS DQ15 B DQ14 C 4 5 6 7 8 9 VSSQ VDDQ DQ0 VDD DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE CAS RAS WE G A12 A11 A9 BA0 BA1 CS H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD 7 8 9 (Top View) Pin Configuration 3.2 Ball Assignment: LPSDR X 32 90Ball FBGA 1 2 3 4 5 6 A DQ26 DQ24 VSS VDD DQ23 DQ21 B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19 C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ E VDDQ DQ31 NC NC DQ16 VSSQ F VSS DQM3 A3 A2 DQM2 VDD G A4 A5 A6 A10 A0 A1 H A7 A8 A12 NC BA1 A11 J CLK CKE A9 BA0 CS RAS K DQM1 NC NC CAS DQM0 L VDDQ DQ8 VSS VDD WE DQ7 M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 VSS VDD DQ0 DQ2 VSSQ (Top View) Pin Configuration - 4- Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 4. PIN DESCRIPTION 4.1 Signal Description BALL NAME FUNCTION A [n : 0] Address BA0, BA1 Bank Select DQ0~DQ15 (×16) DQ0~DQ31 (×32) CS RAS CAS WE DESCRIPTION Multiplexed pins for row and column address. A10 is Auto Precharge Select Select bank to activate during row address latch time, or bank to read/write during address latch time. Data Input/ Output Multiplexed pins for data output and input. Chip Select Row Address Strobe Column Address Strobe Write Enable I/O Mask CLK Clock Inputs CKE Clock Enable VDD VSS Power Ground Power for I/O Buffer Ground for I/O Buffer No Connection VSSQ NC Referred to RAS Referred to WE The output buffer is placed at Hi-Z (with latency of 2 in CL=2, 3;) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. UDQM / LDQM(x16) DQM0 ~ DQM3 (x32) VDDQ Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock, RAS , CAS and WE define the operation to be executed. System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode or Self Refresh mode is entered. Power supply for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Power supply separated from VDD, used for output buffers to improve noise. Separated ground from VSS, used for output buffers to improve noise. No connection 4.2 Addressing Table ITEM 512 Mb Number of banks 4 Bank address pins BA0,BA1 Auto precharge pin A10/AP X16 Row addresses A0-A12 Column addresses A0-A9 Refresh count x32 8K Row addresses A0-A12 Column addresses A0-A8 Refresh count 8K - 5- Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 5. BLOCK DIAGRAM CLK CLOCK BUFFER CKE CS CONTROL SIGNAL RAS COMMAND CAS DECODER GENERATOR COLUMN DECODER WE A10 MODE REGISTER A0 An BA0 BA1 COLUMN DECODER R O W D E C O R D E R R O W D E C O R D E R CELL ARRAY BANK #0 CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER DMn DQ BUFFER DATA CONTROL CIRCUIT REFRESH COUNTER DQ0 – DQn DQM COLUMN COUNTER COLUMN DECODER COLUMN DECODER R O W D E C O R D E R R O W CELL ARRAY D E C O R D E R BANK #2 SENSE AMPLIFIER CELL ARRAY BANK #3 SENSE AMPLIFIER - 6- Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 6. ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Ratings PARAMETER SYMBOL VALUES UNITS MIN MAX VDD −0.3 2.7 V Voltage on VDDQ relative to VSS VDDQ −0.3 2.7 V Voltage on any pin relative to VSS VIN, VOUT −0.3 2.7 V Tc -25 -40 85 85 °C Storage Temperature TSTG −55 150 °C Short Circuit Output Current IOUT ±50 mA PD 1.0 W Voltage on VDD relative to VSS Operating Temperature Power Dissipation 6.2 Operating Conditions SYMBOL MIN. TYP. MAX. UNIT Supply Voltage PARAMETER VDD 1.7 1.8 1.95 V Supply Voltage (for I/O Buffer) VDDQ 1.7 1.8 1.95 V Input High level Voltage VIH 0.8*VDDQ - VDDQ+0.3 V Input Low level Voltage VIL -0.3 - +0.3 V LVCOMS Output H Level Voltage (IOUT = -0.1 mA ) VOH 0.9*VDDQ - - V LVCMOS Output L Level Voltage (IOUT = +0.1 mA ) VOL - - 0.2 V II(L) -1 - 1 A IO(L) -5 - 5 A Input Leakage Current (0V VIN VDD, all other pins not under test = 0V) Output Leakage Current (Output disable , 0V VOUT VDDQ) Note: VIH(max) = VDD/ VDDQ+1.2V for pulse width < 5 ns , VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 ns 6.3 Capacitance PARAMETER SYMBOL MIN. MAX. UNIT CI 1.5 3.0 pf Input Capacitance (CLK) CCLK 1.5 3.5 pf Input/Output capacitance CIO 3.0 5.0 pf Input Capacitance (A[ n : 0] , BA0, BA1, CS , RAS , CAS , WE , DQM, CKE) Note: These parameters are periodically sampled and not 100% tested. - 7- Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 6.4 DC Characteristics (x16) PARAMETER / CONDITION -6 -75 MAX. MAX. 38 35 Low power 0.6 0.6 Normal power 0.8 0.8 Idd2N 10 10 mA Idd3P 3 3 mA 3, 4, 6 Idd3N 25 25 mA 3, 4, 6 Idd4 75 70 mA 2, 3, 4 Idd5 75 75 mA 2, 3, 4, 6 Izz 10 10 μA 5,8 SYM. Operating current: Active mode, 1 bank, BL = 1, tRC = tRC (min), Iout=0mA, Active Precharge command cycling without burst operation. IDD1 Standby current: Power-down mode, All banks idle, CKE = LOW. Idd2P Standby current: Nonpower-down mode, All banks idle, CKE = HIGH. Standby current: Active mode; CKE = LOW, CS# = HIGH, All banks active, No accesses in progress. Standby current: Active mode, CKE = HIGH, CS# = HIGH, All banks active after tRCD met, No accesses in progress. Operating current: Burst mode, All banks active, Iout=0mA, READ/WRITE command cycling, Auto refresh current: tRFC=tRFC (MIN), Auto refresh command cycling Deep Power Down Mode - 8- UNIT NOTES mA 2, 3, 4 mA 5 Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR (x32) PARAMETER / CONDITION -6 -75 MAX. MAX. 38 35 Low power 0.6 0.6 Normal power 0.8 0.8 Idd2N 10 10 mA Idd3P 3 3 mA 3, 4, 6 Idd3N 25 25 mA 3, 4, 6 Idd4 75 70 mA 2, 3, 4 Idd5 75 75 mA 2, 3, 4, 6 Izz 10 10 μA 5,8 SYM. Operating current: Active mode, 1 bank, BL = 1, tRC = tRC (min), Iout=0mA, Active Precharge command cycling without burst operation. IDD1 Standby current: Power-down mode, All banks idle, CKE = LOW. Idd2P Standby current: Nonpower-down mode, All banks idle, CKE = HIGH. Standby current: Active mode; CKE = LOW, CS# = HIGH, All banks active, No accesses in progress. Standby current: Active mode, CKE = HIGH, CS# = HIGH, All banks active after tRCD met, No accesses in progress. Operating current: Burst mode, All banks active, Iout=0mA, READ/WRITE command cycling, Auto refresh current: tRFC=tRFC (MIN), Auto refresh command cycling Deep Power Down Mode UNIT NOTES mA 2, 3, 4 mA 5 Notes: 1. A full initialization sequence is required before proper device operation is ensured. 2. Idd is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 3. The Idd current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 4. Address transitions average one transition every 2 clocks. 5. Measurement is taken 500ms after entering into this operating mode to provide tester measuring unit settling time. 6. Other input signals can transition only one time for every 2 clocks and are otherwise at valid Vih or Vil levels. 7. CKE is HIGH during the REFRESH command period tRFC (MIN) else CKE is LOW. The Idd7 limit is a nominal value and does not result in a fail value. 8. Typical values at 25°C (not a maximum value). - 9- Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 6.5 Automatic Temperature Compensated Self Refresh Current Feature IDD6 Low Power Normal Power TCSR Range 45℃ 85℃ 45℃ 85℃ Full Array 450 600 650 800 1/2 Array 350 500 550 700 1/4 Array 300 400 500 600 Units uA Note: 1. A full initialization sequence is required before proper device operation is ensured. 2. Measurement is taken 500ms after entering into this operating mode to provide tester measuring unit settling time. 3. Enables on-die refresh and address counters. 4. Values for Idd6 85°C full array and partial array are guaranteed for the entire temperature range. 5. IDD6 is typical value. - 10 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 6.6 AC Characteristics And AC Operating Conditions 6.6.1 AC Characteristics *CL= CAS Latency; (Notes: 5,6,7) PARAMETER SYM Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time -6 MIN. -75 MAX. UNIT NOTE - ns 8 50 100000 ns 8 MIN. MAX. 72.5 tRC 60 tRAS 42 tRCD 18 18 - ns 8 tCCD 1 1 - CLK 8 tRP 18 18 - ns 8 tRRD 12 15 - ns 8 tWR 15 15 - ns tLDR 1 1 tCK 6 1000 7.5 1000 ns 12 1000 12 1000 ns 100000 Read/Write(a) to Read/Write(b)Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Write-Recovery Time (Last data to Read) CLK Cycle Time CL * = 3 CL * = 2 CLK CLK High Level width tCH 2 2.5 - ns CLK Low Level width tCL 2 2.5 - ns 5.4 - 5.4 ns 6 - 8 ns 2.5 - ns 5.4 - 5.4 ns 7 6 - 6 ns 7 1 - ns Access Time from CLK CL * = 3 tAC CL * = 2 tOH Output Data Hold Time Output Data High Impedance Time CL * = 3 2.5 tHZ CL * = 2 Output Data Low tLZ 1 tSB 0 6 0 7.5 ns tT 0.3 1.2 0.3 1.2 ns Data-in Set-up Time tDS 1.5 1.5 - ns Data-in Hold Time tDH 1 1 - ns Address Set-up Time tAS 1.5 1.5 - ns Address Hold Time tAH 1 1 - ns Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) - 11 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR PARAMETER SYM -6 MIN. -75 MAX. MIN. MAX. UNIT CKE Set-up Time tCKS 1.5 1.5 - ns CKE Hold Time tCKH 1 1 - ns Command Set-up Time tCMS 1.5 1.5 - ns Command Hold Time tCMH tREF 1 1 - ns 64 ms tRSC 12 15 - ns tRFC 72 72 - ns tXSR 115 115 - ns Refresh Time Mode register Set Cycle Time Ref to Ref/Active Command period Self Refresh exit to next valid command delay 64 NOTE 8 6.6.2 AC Test Condition SYMBOL VIH(min) VIL(max) VREF VOTR SLEW PARAMETER Input High Voltage Level (AC) Input Low Voltage Level (AC) Input Signal Reference Level Output Signal Reference Level Input Signal Slew Rate VALUE 0.8 x VDDQ 0.2 x VDDQ 0.5 x VDDQ 0.5 x VDDQ 1 UNIT V V V V V/ns VDDQ VTT=0.9V RT=50Ω VIH(min) VREF output VIL(max) CLOAD = 30pF VSS tT Z = 50 Ω VOTR AC TEST LOAD tT SLEW = ( VIH(min)- VIL(max) / tT Transition times are measured between VIH and VIL. - 12 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR Note : 1. Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect deice reliability. 2. All voltages are referenced to VSS and VSSQ. 3. These parameters depend on the cycle rate. These values are measured at a cycle rate with the minimum values of tCK and tRC . Input signals transition once per tCK period. 4. These parameters depend on the output loading. Specified values are obtained with the output open. 5. Power-up sequence is described in Note 9. 6. AC TEST CONDITIONS : (refer to 6.6.2) 7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. 8. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: The number of clock cycles = specified value of timing / clock period (count fractions as a whole number) 9. Power up Sequence : The SDRAM should be powered up by the following sequence of operations. a. Power must be applied to VDD before or at the same time as VDDQ while all input signals are held in the “NOP” state. The CLK signal will be applied at power up with power. b. After power-up a pause of at least 200 uA is required. It is required that DQM and CKE signals must be held “High” (VDD levels ) to ensure that the DQ output is in High-impedance state. c. All banks must be precharged. d. The Mode Register Set command must be issued to initialize the Mode Register. e. The Extended Mode Register Set command must be issued to initialize the Extended Mode Register. f. Issue two or more Auto Refresh dummy cycles to stabilize the internal circuitry of the device. The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles. 6.6.3 AC Latency Characteristics CKE to clock disable (CKE Latency) 1 DQM to output in High-Z (Read DQM Latency) 2 DQM to input data delay (Write DQM Latency) 0 Write command to input data (Write Data Latency) 0 CS to Command input ( CS Latency) 0 Precharge to DQ Hi-Z Lead time Precharge to Last Valid data out Burst Stop Command to DQ Hi-Z Lead time Burst Stop Command to Last Valid data out Read with Auto Precharge Command to Active/Ref Command Write with Auto Precharge Command to Active/Ref Command - 13 - CL = 2 2 CL = 3 3 CL = 2 1 CL = 3 2 CL = 2 2 CL = 3 3 CL = 2 1 CL = 3 2 CL = 2 BL+ tRP CL = 3 BL+ tRP CL = 2 BL+1 + tRP CL = 3 BL+1 + tRP Cycle Cycle + ns Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 7. FUNCTION DESCRIPTION 7.1 Command Function 7.1.1Table 1. Truth Table BS0, Symbol Command Device State CKEn-1 CKEn DQM(5) A10 Address CS RAS CAS WE BS1 ACT Bank Activate PRE Bank Precharge Idle (3) H X X V V V L L H H Any H X X V L X L L H L PREA Precharge All Any H X X X H X L L H L WRIT Write Active (3) H X X V L V L H L L WRITA Write with Auto Precharge Active (3) H X X V H V L H L L READ Read Active (3) H X X V L V L H L H Read with Auto Precharge Active (3) H X X V H V L H L H Mode Register Set Idle H X X V V V L L L L Extended Mode Register Set Idle H X X V V V L L L L READA MRS EMRS NOP No-Operation BST Burst stop DSL Any H X X X X X L H H H Active (4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X AREF Auto-Refresh Idle H H X X X X L L L H SELF Self-Refresh Entry Idle H L X X X X H SELEX CSE PD CSEX PDEX Self-Refresh Exit Clock Suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit Power Down Mode Exit Idle (Self Refresh) L Active H L X X X X Idle/Active (6) H L X X X X Active L Any (Power Down) L H H H X X X X X X X X X L L L H X X X L H H H X X X X X X H X X X L H H H X X X X H X X X L H H X X DE Data Write/Output Enable Active H X L X X X X X X X DD Data Write/Output Disable Active H X H X X X X X X X DPD Deep Power Down Mode Entry Idle H L X X X X L H H L DPDE Deep Power Down Mode Exit Idle (DPD) L H X X X X X X X X Note 1. V = Valid, × = Don’t Care, L = Low level, H = High level 2. CKEn signal is input level when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BS0, BS1 signals. 4. Device state is Full Page Burst operation. 5. x32: DQM0-3, x16 : LDQM / UDQM 6. Power Down Mode cannot entry in the burst cycle. When this command assert in the burst cycle, device state is clock suspend mode. - 14 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 7.1.2 Functional Truth Table (See Note 1 at the end of this Table) Current State Idle Row active Read Write CS RAS CAS WE Address Command Action H X X X X DSL Nop L H H X X NOP/BST Nop L H L H BS, CA, A10 READ/READA ILLEGAL 3 L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT Row activating L L H L BS, A10 PRE/PREA Nop L L L H X AREF/SELF Refresh or Self refresh 2 L L L L Op-Code MRS/EMRS Mode register accessing 2 H X X X X DSL Nop L H H X X NOP/BST Nop L H L H BS, CA, A10 READ/READA Begin read: Determine AP 4 L H L L BS, CA, A10 WRIT/WRITA Begin write: Determine AP 4 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA Precharge 5 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop L H L H BS, CA, A10 READ/READA Term burst, new read: Determine AP L H L L BS, CA, A10 WRIT/WRITA Term burst, begin write: Determine AP L L H H BS, RA ACT L L H L BS, A10 PRE/PREA Term burst, precharging L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end. L H H H X NOP Continue burst to end L H H L X BST Burst stop, row active L H L H BS, CA, A10 READ/READA Term burst, start read: Determine AP 6, 7 L H L L BS, CA, A10 WRIT/WRITA Term burst, new write: Determine AP 6 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA Term burst. precharging 8 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL - 15 - ILLEGAL Notes 6 6,7 3 Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR Current State Read with auto precharge Write with auto precharge Precharging Row activating CS RAS CAS WE Address Command H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BS, CA, A10 READ/READA ILLEGAL 3 L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BS, CA, A10 READ/READA ILLEGAL 3 L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop → Idle after tRP L H H H X NOP Nop → Idle after tRP L H H L X BST ILLEGAL L H L H BS, CA, A10 READ/READA ILLEGAL 3 L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA Nop → Idle after tRP L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop → Row active after tRCD L H H H X NOP Nop → Row active after tRCD L H H L X BST ILLEGAL L H L H BS, CA, A10 READ/READA ILLEGAL 3 L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL - 16 - Action Notes Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR Current State Write recovering Write recovering with auto precharge Refreshing Mode register accessing CS RAS CAS WE Address Command H X X X X DSL Nop → Maintain Row active after tWR L H H H X NOP Nop → Maintain Row active after tWR L H H L X BST Nop → Maintain Row active after tWR L H L H BS, CA, A10 READ/READA Begin Read L H L L BS, CA, A10 WRIT/WRITA Begin new Write L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop → Enter precharge after tWR L H H H X NOP Nop → Enter precharge after tWR L H H L X BST Nop → Enter precharge after tWR L H L H BS, CA, A10 READ/READA ILLEGAL 3 L H L L BS, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BS, RA ACT ILLEGAL 3 L L H L BS, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Nop → Idle after tRFC L H H H X NOP Nop → Idle after tRFC L H H L X BST Nop → Idle after tRFC L H L X X READ/WRIT ILLEGAL L L H X X ACT/PRE/PREA ILLEGAL L L L X X AREF/SELF/MRS/ EMRS ILLEGAL H X X X X DSL Nop → Idle after tRSC L H H H X NOP Nop → Idle after tRSC L H H L X BST ILLEGAL L H L X X READ/WRIT ILLEGAL X ACT/PRE/PREA/ AREF/SELF/MRS/ EMRS ILLEGAL L L X X Action Notes 7 Note: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle (CKEn-1 = CKEn = ”1”) 2. Illegal if any bank is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied. 6. Must satisfy burst interrupt condition. 7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don’t satisfy tWR. Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data. - 17 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 7.1.3 Function Truth Table for CKE Current State Self refresh Power-Down Deep Power-Down All banks idle Row Active Any state other than listed above CKE n-1 n CS RAS CAS WE Address Action H X X X X X X N/A L H H X X X X Exit Self Refresh → Idle after tRFC L H L H H H X Exit Self Refresh → Idle after tRFC L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X Maintain Self Refresh H X X X X X X N/A L H L Notes H X X X X L H H H X L X X X X X Maintain Power-Down H X X X X X X N/A L H X X X X X Exit Deep Power-Down → Exit Sequence L L X X X X X Maintain Deep Power-Down H H X X X X X Refer to Function Truth Table H L H X X X X Enter Power-down 2 H L L H H H X Enter Power-Down 2 H L L H H L X Enter Deep Power-Down 3 H L L L L H X Self Refresh 1 H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Power-Down H H X X X X X Refer to Function Truth Table H L H X X X X Enter Power down 2 H L L H H H X Enter Power down 2 H L L L L H X ILLEGAL H L L H L X X ILLEGAL Exit Power Down → Idle after 1 clock cycle 2 H L L L X X X ILLEGAL L X X X X X X Power-Down → Row Active or Maintain PD H H X X X X X Refer to Function Truth Table Note: 1. Self refresh can enter only from the all banks idle state. 2. Power-down can enter only from the all banks idle or row active state. 3. Deep power-down can enter only from the all banks idle state. Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data. - 18 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 7.1.4 Bank Activate Command ( RAS = L, CAS = H, WE = H, BA0, BA1 = Bank, A0~An = Row Address) The Bank Activate command activates the bank designated by the BS (Bank Select) signal. Row addresses are latched on A0~An when this command is issued and the cell data is read out to the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). 7.1.5 Bank Precharge Command ( RAS = L, RAS = H, WE = L, BA0, BA1 = Bank, A10 =L ) The Bank Precharge command is used to close (or precharge) the bank that is activated. Using this command, systems can designated the bank to be closed by specifying the BS address bit setting in the command set. A Precharge command can be used to precharge each bank separately (Bank Precharge) or all four banks simultaneously (Precharge All). After the Bank Precharge command is issued, any one bank can close, and the closed bank transitions from the active state to the idle state. To re-activate the closed bank, a system has to wait the minimum tRP delay after issuing the Precharge command before issuing the Active Command for the device to complete the Precharge operation. 7.1.6 Precharge All Command ( RAS = L, CAS = H, WE = L, BA0, BA1 = Don’t care, A10 =H ) The Precharge All command is used to precharge all banks simultaneously. After this command is issued, all four banks close and transition from the active state to the idle state. 7.1.7 Write Command ( RAS = H, CAS = L, WE = L, BA0, BA1 = Bank, A10 = L ) The Write command initiates a Write operation to the bank selected by BA0 and BA1 address inputs. The write data is latched at the positive edge of CLK. Users should preprogram the length of the write data (Burst Length) and the column access sequence (Addressing Mode) by setting the Mode Resister at power-up prior to using the Write command. 7.1.8 Write with Auto Precharge Command ( RAS = H, CAS = L, WE = L, BA0, BA1 = Bank, A10 = H ) The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. The internal precharge starts in the cycles immediately following the cycle in which the last data is written independent of CAS Latency. 7.1.9 Read Command ( RAS = H, CAS = L, WE = H, BA0, BA1 = Bank, A10 = L ) The Read command performs a Read operation to the bank designated by BA0-1. The read data is issued sequentially synchronized to the positive edges of CLK. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Write operation. 7.1.10 Read with Auto Precharge Command ( RAS = H, CAS = L, WE = H, BA0, BA1 = Bank, A10 =H ) The Read with Auto Precharge command automatically performs the Precharge operation after the Read operation. When the CAS Latency = 3, the internal precharge starts two cycles before the last data is output. When the CAS Latency = 2, the internal precharge starts one cycle before the last data is output. 7.1.11 Extended Mode Register Set Command ( RAS = L, CAS = L, WE = L, BA0, BA1, A0~An = Register Data) The Extended Mode Register Set command is designed to support Partial Array Self Refresh, Temperature Compensated Self Refresh, and Output Driver Strength/Size by allowing users to program each value by setting predefined address bits. The default values in the Extended Mode Register after power-up are undefined; therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. - 19 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 7.1.12 Mode Register Set Command ( RAS = L, CAS = L, WE = L, BA0, BA1, A0~An = Register Data) The Mode Register Set command is used to program the values of CAS latency, Addressing Mode and Burst Length in the Mode Register. The default values in the Mode Register after power-up are undefined; therefore this command must be issued during the power-up sequence and re-issued after the Deep Power Down Exit Command. Also, this command can be issued while all banks are in the idle state. 7.1.13 No-Operation Command ( RAS = H, CAS = H, WE = H) The No-Operation command is used in cases such as preventing the device from registering unintended commands. The device performs no operation when this command is registered. This command is functionally equivalent to the Device Deselect command. 7.1.14 Burst Stop Command ( RAS = H, CAS = H, WE = L) The Burst stop command is used to stop the already activated burst operation. The activated page is left unclosed and future commands can be issued to access the same page of the active bank. If this command is issued during a burst read operation, the read data will go to a Hi-Z state after a delay equal to the CAS latency. If a burst stop command is issued during a burst write operation, then the burst data is terminated and data bus goes to Hi-Z at the same clock that the burst command is activated. Any remaining data from the burst write cycle is ignored. 7.1.15 Device Deselect Command ( CS = H) The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 7.1.16 Auto Refresh Command ( RAS = L, CAS = L, WE = H, CKE = H, BA0, BA1, A0~An = Don’t care) The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation must be performed 8192 times within 64 ms. The next command can be issued after tRC from the end of the Auto Refresh command. When the Auto Refresh command is issued, All banks must be in the idle state. The Auto Refresh operation is equivalent to the CAS -before- RAS operation in a conventional DRAM. 7.1.17 Self Refresh Entry Command ( RAS = L, CAS = L, WE = H, CKE = L, BA0, BA1, A0~An = Don’t care) When the Self Refresh Entry command is issued, the device enters the Self Refresh mode. While the device is in Self Refresh mode, the device automatically refreshes memory cells, and all input and I/O buffers (except the CKE buffer) are disabled. By asserting the CKE signal “high” (and by issuing the Self Refresh Exit command), the device exits the Self Refresh mode. 7.1.18 Self Refresh Exit Command (CKE = H, CS = H or CKE = H, RAS = H, CAS = H) This command is issued to exit out of the Self Refresh mode. One tRC delay is required prior to issuing any subsequent command from the end of the Self Refresh Exit command. 7.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command (CKE = L) The internal CLK is suspended for one cycle when this command is issued (when CKE is asserted “low”). The device state is held intact while the CLK is suspended. On the other hand, when the device is not operating the Burst cycle, this command performs entry into Power Down mode. All input and output buffers (except the CKE buffer) are turned off in Power Down mode. 7.1.20 Clock Suspend Mode Exit / Power Down Mode Exit Command (CKE = H) When the internal CLK has been suspended, operation of the internal CLK is resumed by providing this command (asserting CKE “high”). When the device is in Power Down mode, the device exits this mode and all disabled buffers are turned on to the active state. Any subsequent commands can be issued after one clock cycle from the end of this command. - 20 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 7.1.21 Data Write/Output Enable, Data Mask/Output Disable Command (DQM = L/H or LDQM, UDQM = L/H or DQM0-3=L/H) During a Write cycle, the DQM or LDQM, UDQM or DQM0-3 signals mask write data. Each of these signals control the input buffers per byte. During a Read cycle, the DQM or LDQM, UDQM or DQM0-3 signals control of the output buffers per byte. I/O Org. ×16 ×32 MASK PIN MASKED DQs LDQM DQ0~DQ7 UDQM: DQ8~DQ15 DQM0: DQ0~DQ7 DQM1: DQ8~DQ15 DQM2: DQ16~DQ23 DQM3: DQ24~DQ31 8.OPERATION 8.1 Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized to the positive edges of CLK (a Burst Read operation). The initial read data becomes available after CAS Latency from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. In addition, the burst length of read data and Addressing Mode must be set. Each bank is held in the active state unless the Precharge command is issued, so that the sense amplifiers can be used as secondary cache. When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Also, when the Burst Length is 1 and tRCD (min), the timing from the RAS command to the start of the Auto Precharge operation is shorter than tRAS (min). In this case, tRAS (min) must be satisfied by extending tRCD. When the Precharge operation is performed on a bank during a Burst Read operation, the Burst operation is terminated. When the Burst Length is full-page, column data is repeatedly read out until the Burst Stop command or Precharge command is issued. 8.2 Write Operation Issuing the Write command after tRCD from the Bank Activate command, the input data is latched sequentially, synchronizing with the positive edges of CLK after the Write command (Burst Write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other command for the entire burst data duration. Also, when the Burst Length is 1 and tRCD (min), the timing from the RAS command to the start of the Auto Precharge operation is shorter than tRAS (min). In this case, tRAS (min) must be satisfied by extending tRCD. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Burst Length is full-page, the input data is repeatedly latched until the Burst Stop command or the Precharge command is issued. When the Burst Read and Single Write mode is selected, the write burst length is 1 regardless of the read burst length. - 21 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.3 Precharge There are two commands which perform the Precharge operation: Bank Precharge and Precharge All. When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS (max) from the Bank Activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharged bank is then switched to the idle state. 8.3.1 Auto Precharge Auto precharge is a feature that performs the same individual-bank PRECHARGE function described previously, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. Another command cannot be issued to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time. Winbond SDRAM supports concurrent auto precharge; cases of concurrent auto precharge for READs and WRITEs are defined below. 8.3.2 READ with auto precharge interrupted by a READ (with or without auto precharge) A READ to bank m will interrupt a READ on bank n following the programmed CAS latency. The precharge to bank n begins when the READ to bank m is registered. T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Bank n NOP Page active Internal states READ-AP Bank n NOP READ-AP Bank m READ with burst of 4 NOP NOP NOP Interrupt burst, precharge Idle tRP-bank n Bank m Page active Address Bank n, Col a NOP tRP-bank m Precharge READ with burst of 4 Bank m, Col d Dout a DQ Dout a+1 Dout d Dout d+1 CL=3 (bank n) CL=3 (bank m) Don’t Care Note: 1. DQM is LOW. - 22 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.3.3 READ with auto precharge interrupted by a WRITE (with or without auto precharge) A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The precharge to bank n begins when the WRITE to bank m is registered. T1 T0 T2 T3 T4 T5 T6 T7 CLK Command Bank n Internal states READ-AP Bank n Page active NOP NOP NOP READ with burst of 4 WRITE-AP Bank m NOP NOP Interrupt burst, precharge Idle tWR-bank m tRP-bank n Page active Bank m Address NOP WRITE with burst of 4 Bank n, Col a Write-back Bank m, Col d DQM 1 DQ DOUT Din Din a d d+1 CL=3 (bank n) Din d+2 Din d+3 Don’t Care Note: 1. DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4. - 23 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.3.4 WRITE with auto precharge interrupted by a READ (with or without auto precharge) A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data in registered one clock prior to the READ to bank m. T1 T0 T2 T3 T4 T5 T6 T7 CLK Command Bank n NOP WRITE-AP Bank n Page active NOP WRITE with burst of 4 Internal states READ-AP Bank m NOP NOP Interrupt burst, write-back precharge tWR-bank n tRP-bank n NOP NOP tRP-bank m Bank m Address DQ Page active READ with burst of 4 Bank n, Col a Din a Bank m, Col d Dout d Din a+1 Dout d+1 CL=3 (bank m) Don’t Care Note: 1. DQM is LOW. - 24 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m. T1 T0 T2 T3 T4 T5 T6 T7 CLK Command Bank n Internal states NOP WRITE-AP Bank n NOP NOP NOP Interrupt burst, write-back WRITE with burst of 4 Page active WRITE-AP Bank m Page active Address DQ precharge tWR-bank m Write-back WRITE with burst of 4 Bank m, Col d Bank n, Col a Din a NOP tRP-bank n tWR-bank n Bank m NOP Din a+1 Din a+2 Din d Din d+1 Din d+2 Din d+3 Don’t Care Note: 1. DQM is LOW. - 25 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.4 Burst Termination The Read or Write command can be issued on any clock cycle. Whenever a Read operation is to be interrupted by a Write command, the output data must be masked by DQM to avoid I/O conflict. Also, when a Write operation is to be interrupted by a Read command, only the input data before the Read command is enable and the input data after the Read command is disabled. - Read Interrupted by a Precharge A Precharge command can be issued to terminate a Burst cycle early. When a Burst Read cycle is interrupted by a Precharge command, the read operation is terminated after ( CAS latency-1) clock cycles from the Precharge command. - Write Interrupted by a Precharge A burst Write cycle can be interrupted by a Precharge command, the input circuit is reset at the same clock cycle at which the Precharge command is issued. In this case, the DQM signal must be asserted high to prevent writing the invalid data to the cell array. - Read Interrupted by a Burst Stop When the Burst Stop command is issued for the bank in a Burst cycle, the Burst operation is terminated. When the Burst Stop command is issued during a Burst Read cycle, the read operation is terminated after clock cycle of ( CAS latency-1) from the Burst Stop command. - Write Interrupted by a Burst Stop When the Burst Stop command is issued during a Burst Write cycle, the write operation is terminated at the same clock cycle that the Burst Stop command is issued. - Write Interrupted by a Read A burst of write operation can be interrupted by a read command. The read command interrupts the write operation on the same clock that the read command is issued. All the burst writes that are presented on the data bus before the read command is issued will be written to the memory. Any remaining burst writes will be ignored once the read command is activated. There must be at least one clock bubble (Hi-Z state) on the data bus to avoid bus contention. - Read Interrupted by a Write A burst of read operation can be interrupted by a write command by driving output drivers in a Hi-Z state using DQM before write to avoid data conflict. DQM should be utilized if there is data from a Red command on the first and second cycles of the subsequent write cycles to ensure the read data are tri-stated. From the third clock cycle, the write command will control the data bus and DQM is not needed. - 26 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.5 Mode Register Operation The Mode register designates the operation mode for the Read or Write cycle. This register is divided into three fields; A Burst Length field to set the length of burst data, an Addressing Mode selected bits to designate the column access sequence in a Burst cycle, and a CAS Latency field to set the access time in clock cycle. The Mode Register is programmed by the Mode Register Set command when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0~An, BA0, BA1 address inputs. The initial value of the Mode Register after power-up is undefined; therefore the Mode Register Set command must be issued before proper operation. 8.5.1 Burst Length field (A2~A0) This field specifies the data length for column access using the A2~A0 pins and sets the Burst Length to be 1, 2, 4, 8, words, or full-page. A2 A1 A0 BUST LENGTH 0 0 0 1 word 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 1 1 Full-Page 8.5.2 Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential mode. When the A3 bit is 0, Sequential mode is selected. When the A3 bit is 1, Interleave mode is selected. Both Addressing modes support burst length of 1, 2, 4 and 8 words. Additionally, Sequential mode supports the full-page burst. A3 ADDRESSING MODE 0 Sequential 1 Interleave - 27 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR Addressing sequence of Sequential mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length shown as below table. 8.5.3 Addressing Sequence for Sequential Mode DATA Access Address Data0 n Data1 n+1 Data2 n+2 Data3 n+3 Data4 n+4 Data5 n+5 Data6 n+6 Data7 n+7 Burst Length 2 words (Address bits is A0) not carried from A0 to A1 4 words (Address bits is A1, A0) not carried from A1 to A2 8 words (Address bits is A2, A1, A0) not carried from A2 to A3 Addressing sequence of Interleave mode A column access is started from the input column address and is performed by inverting the address bits in the sequence shown as below table. 8.5.4 Addressing Sequence for Interleave Mode DATA Access Address Data0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data4 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data7 A8 A7 A6 A5 A4 A3 A2 A1 A0 - 28 - Burst Length 2 words 4 words 8 words Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13) INTERLEAVE MODE SEQUENTIAL MODE DATA A8 A7 A6 A5 A4 A3 A2 A1 Data0 0 0 Data1 0 Data2 A0 ADD ADD 0 0 0 1 1 0 1 13 13 13 0 0 0 0 1 1 0 0 12 13 + 1 14 0 0 0 0 0 1 1 1 1 15 13 + 2 15 Data3 0 0 0 0 0 1 1 1 0 14 13 + 3 8 Data4 0 0 0 0 0 1 0 0 1 9 13 + 4 9 Data5 0 0 0 0 0 1 0 0 0 8 13 + 5 10 Data6 0 0 0 0 0 1 0 1 1 11 13 + 6 11 Data7 0 0 0 0 0 1 0 1 0 10 13 + 7 12 calculated using A2, A1 and A0 bits not carry from A2 to A3 bit. 8.5.6 Read Cycle CAS Latency = 3 0 3 4 5 6 7 8 9 10 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Data Address { Interleave mode 13 Sequential mode 13 12 15 14 9 8 11 10 14 15 8 9 10 11 12 Command Read Address 13 DQ0~DQ7 1 2 - 29 - 11 Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.5.7 CAS Latency field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. The minimum value which satisfies the following formula must be set in this field. A6 A5 A4 0 1 0 2 clock 0 1 1 3 clock CAS Latency Reserved bits (A7, A8, A10, A11, A12, BA0, BA1) These bits are reserved for future operations. They must be set to 0 for normal operation. Single Write mode (A9) This bit is used to select the write mode. When the A9 bit is 0, Burst Read and Burst Write mode are selected. When the A9 bit is 1, Burst Read and Single Write mode are selected. A9 Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write 8.5.8 Mode Register Definition A0 A0 A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency BurstA0 Length A2 0 A0 A1 A0 0 A0 0 Sequential A0 1 Interleave A0 A0 1 0 0 0 1 1 1 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 1 0 1 0 1 0 A0 2 A0 4 A0 8 A0 2 A0 4 A0 8 1 A0 1 1 Reserved A0 Reserved A0 Full A0 Page A6 A3 A0 Addressing A0 Mode A7 A0 "0" Reserved A0 0 A0 1 Sequential A0 Interleave A0 A8 "0" Reserved A6 A0 A5 A4 A0 0 A0 0 A0 1 0 1 0 A0 1 A0 0 1 0 A10 "0" 0 0 0 A11 A0 "0" 0 1 A12 "0" A9 A0 WriteA0 Mode BA0 "0" BA1 "0" A0 Reserved A0 CAS Latency Reserved A0 Reserved 2 A0 3 Reserved A9 A0 Single Write Mode A0 0 A0 1 Burst read and A0 Burst write Burst read and A0 single write - 30 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.6 Extended Mode Register Description The Extended Mode Register designates the operation condition while SDRAM is in Self Refresh Mode and selects the output driver strength as full, 1/2, 1/4, or 1/8 strength. The register is divided into two fields; (1) Partial Array Self Refresh field selects how much banks or which part of a bank need to be refreshed during Self Refresh. (2) Driver Strength selected bit to control the size of output buffer. The initial value of the Extended Mode Register after power-up is Full Driver Strength, and all banks are refreshed during Self Refresh Mode. A2 A1 A0 A0 A1 Partial Array Self Refresh A2 A3 "0" A4 "0" Reserved A5 A6 Output Driver A7 "0" A8 "0" A9 "0" A10 "0" A11 "0" A12 "0" BA0 "0" BA1 "1" Self-Refresh coverage 0 0 0 0 0 1 All banks 0 1 0 0 1 1 1 0 0 Reserved 1 0 1 1 1 0 Reserved Reserved 1 1 1 Reserved Banks 0 and 1 (BA1=0) Bank 0 (BA1=BA0=0) Reserved Reserved Extended Mode Register Set A6 A5 Driver Strength 0 0 Full strength 0 1 1/2 strength 1 0 1/4 strength 1 1 1/8 strength - 31 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 8.7 Simplified State Diagram - 32 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 9. CONTROL TIMING WAVEFORMS 9.1 Command Input Timing tCL tCK CLK tCH VIH VIL tT tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH tCMH tT tCMS CS RAS CAS WE Address BA0, BA1 tCKS tCKH tCKS tCKH tCKS tCKH CKE - 33 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 9.2 Read Timing Read CAS Latency CLK CS RAS CAS WE Address BA0, BA1 tAC tAC tHZ tOH tLZ tOH Output Data Valid DQ Read Command Output Data Valid Burst Length - 34 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 9.3 Control Timing of Input Data (x16) (Word Mask) CLK tCMH tCMS tCMH tCMS LDQM tCMH tCMS tCMH tCMS UDQM tDS DQ0~DQ7 tDS Input Data Valid tDS DQ8~DQ15 tDH tDH Input Data Valid tDH Input Data Valid tDH tDS Input Data Valid tDS tDS tDH tDS Input Data Valid Input Data Valid tDS tDH tDH Input Data Valid tDH Input Data Valid (Clock Mask) CLK tCKH tCKS tCKH tDH tDS tDH tCKS CKE tDS DQ0~DQ7 Input Data Valid tDS DQ8~DQ15 tDH Input Data Valid tDS Input Data Valid tDS tDH tDS Input Data Valid tDS tDH Input Data Valid tDH Input Data Valid - 35 - tDH Input Data Valid tDS tDH Input Data Valid Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 9.4 Control Timing of Output Data (x16) (Output Enable) CLK tCMS tCMH tCMH tCMS tCMH tCMS LDQM tCMH tCMS UDQM tAC tOH tOH tHZ tAC Output Data Valid DQ0~DQ7 Output Data Valid tAC tAC tOH Output Data Valid tOH tAC Output Data Valid tHZ tOH tOH Output Data Valid tAC OPEN tAC tOH DQ8~DQ15 tLZ tOH Output Data Valid tLZ tAC OPEN (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tAC tOH Output Data Valid DQ0~DQ7 tAC tOH DQ8~DQ15 tAC tAC tOH tOH tOH Output Data Valid Output Data Valid tAC tAC tOH tOH Output Data Valid Output Data Valid - 36 - tAC tOH tAC Output Data Valid Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 9.5 Control Timing of Input Data (x32) CLK (Word Mask) tCMH tCMS tCMH tCMS DQM0 tCMH tCMS tCMH tCMS DQM1 tDS DQ0~DQ7 tDS tDS tDH tDH Input Data Valid tDS DQ24~DQ31 tDS tDH Input Data Valid tDH tDS Input Data Valid tDH tDS Input Data Valid DQ8~DQ15 DQ16~DQ23 tDH Input Data Valid Input Data Valid tDH tDS Input Data Valid tDH tDS Input Data Valid tDS tDH tDS Input Data Valid tDS tDH Input Data Valid tDS tDH tDH tDH Input Data Valid tDS Input Data Valid tDS tDH Input Data Valid tDH tDS Input Data Valid tDS Input Data Valid tDH tDH Input Data Valid tDS Input Data Valid tDH Input Data Valid *DQM2, 3 = “L” (Clock Mask) CLK tCKH tCKS tCKH tDH tDS tDH tCKS RAS tDS DQ0~DQ7 tDS DQ8~DQ15 tDH tDS tDH Input Data Valid tDS tDH tDH Input Data Valid tDS tDH tDH Input Data Valid Input Data Valid tDS tDH Input Data Valid Input Data Valid Input Data Valid tDS DQ24~DQ31 tDS Input Data Valid tDS DQ16~DQ23 tDH tDS Input Data Valid Input Data Valid tDS tDH Input Data Valid tDH Input Data Valid tDS tDH Input Data Valid tDS tDH Input Data Valid tDS tDH Input Data Valid tDS tDH Input Data Valid *DQM2, 3 = “L” - 37 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 9.6 Control Timing of Output Data (x32) (Output Enable) CLK tCMS tCMH tCMH tCMS tCMH tCMS DQM0 tCMH tCMS DQM1 tAC tHZ tAC tOH tOH Output Data Valid DQ0~DQ7 Output Data Valid tAC tAC tOH Output Data Valid tAC tAC tOH Output Data Valid DQ16~DQ23 tAC tOH tOH tAC Output Data Valid Output Data Valid tOH tAC Output Data Valid tAC tAC tAC OPEN tAC tLZ tOH tOH Output Data Valid DQ24~DQ31 Output Data Valid tLZ Output Data Valid tOH tAC Output Data Valid tHZ tAC tOH tOH tOH tOH Output Data Valid tAC OPEN tAC tOH DQ8~DQ15 tLZ tOH Output Data Valid tOH tAC Output Data Valid DQM2, 3 = “L” (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tAC tOH Output Data Valid DQ0~DQ7 tAC tOH tAC tAC Output Data Valid tAC tAC tOH tAC tOH Output Data Valid tAC Output Data Valid Output Data Valid tAC tAC Output Data Valid tOH tOH Output Data Valid tOH Output Data Valid tAC tAC Output Data Valid tOH tOH DQ16~DQ23 tOH Output Data Valid tAC Output Data Valid tOH DQ24~DQ31 tOH tOH DQ8~DQ15 tOH tAC tAC tOH tOH tAC Output Data Valid DQM2, 3 = “L” - 38 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 9.7 Mode register Set (MRS) Cycle tRSC CLK tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH CS RAS CAS WE tAS Address BA0,BA1 tAH Register set data next command A0 Burst Length A1 A2 A3 Addressing Mode A4 A5 CAS Latency A2 0 0 0 0 1 1 1 1 A6 A0 A7 0 Reserved A8 0 Reserved A0 A9 WriteA0 Mode A10 0 A0 A11 0 A0 An 0 BA0 0 A0 BA1 0 Reserved Mode Register Set A0 A0 A1 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A0 0 1 0 1 0 1 0 1 A0 A3 A0 0 A0 1 A6 0 0 0 0 1 A0 A5 A0 0 A0 0 A0 1 A0 1 A0 0 BurstA0 Length A0 A0 Sequential Interleave 1 A0 1 A0 A0 2 2 A0 A0 4 4 A0 A0 8 8 A0 Reserved A0 Reserved FullA0 Page A0 Mode Addressing A0 Sequential A0 Interleave A4 0 1 0 1 0 A0 A9 A0 0 A0 1 CAS A0 Latency A0 Reserved A0 Reserved 2 A0 3 Reserved Single Write Mode A0 Burst write Burst read and A0 single write Burst read and “Reserved” pins should be set to “0” during MRS cycle. - 39 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 9.8 Extended Mode register Set (EMRS) Cycle t RSC CLK t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH tAS tAH CS RAS CAS WE Address BA0,BA1 Register set data next command A0 PASR A1 A2 A3 0 A4 0 A5 Reserved Output Driver A2 0 0 0 0 1 1 1 1 A0 A0 A0 A1 A0 0 0 A0 0 1 A0 1 0 A0 1 1 A0 0 0 A0 0 1 A0 1 0 A0 1 1 Partial A0 Self Refresh All A0 banks Bank0,1 A0(BA1=0) A0 Bank0(BA0=BA1=0) A0 Reserved A6 A0 A7 0 A8 0 A0 A9 0 A10 0 A11 A0 0 AA0 n 0 BA 0 0 A01 BA 1 Reserved A6 A0 A5 0A 0 0 0A 0 1 1A 0 0 1A 0 1 A0 Strength Output Driver A0 Full Strength A0 1/2 Strength 1/4 Strength A0 A0 1/8 Strength Extended Mode Register Set "Reserved" pins should be set to "0" during EMRS cycle - 40 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10. OPERATING TIMING EXAMPLE 10.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) 1 0 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRAS tRP tRP tRAS CAS WE BA0 BA1 tRCD A10 RAa Address RAa tRCD tRCD RBb CBx RBb CAw tRCD RAc RBd RAc CAy RAe RBd CBz RAe DQM CKE DQ aw0 tRRD Bank #0 Active Bank #1 Bank #2 tAC tAC tAC aw1 aw2 aw3 bx0 bx1 Precharge Active bx3 cy0 tRRD tRRD Read bx2 Precharge Read cy1 cy2 cy3 tRRD Read Active tAC Precharge Active Active Read Idle Bank #3 - 41 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRAS tRP tRP tRAS CAS WE BA0 BA1 tRCD tRCD tRCD A10 RAa RBb Address RAa CAw RBb tRCD RBd RAc CBx CAy RAc RAe CBz RBd RAe DQM CKE tAC DQ tRRD Active Bank #0 Bank #1 Bank #2 tAC tAC aw0 aw1 aw2 aw3 bx0 tRRD Read bx2 bx3 tAC cy0 cy1 tRRD Active AP* Active bx1 cy3 dz0 tRRD AP* Read AP* Active Read cy2 Active Read Idle Bank #3 * AP is the internal precharge start timing - 42 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC RAS tRAS tRP tRAS tRP tRAS tRP CAS WE BA0 BA1 tRCD A10 Address tRCD RAa RAa tRCD RAc RBb CAx RBb CBy CAz RAc DQM CKE tAC DQ tAC ax0 ax1 tRRD Bank #0 Active Bank #2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 CZ0 tRRD Read Precharge Bank #1 ax2 tAC Precharge Active Active Read Precharge Read Idle Bank #3 - 43 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRC CS tRC RAS tRAS tRAS tRP tRAS tRP CAS WE BA0 BA1 tRCD A10 RAa Address RAa tRCD tRCD RBb CAx RAc RBb RAc CBy CAz DQM CKE tAC tAC DQ ax0 ax1 ax2 tRRD Bank #0 Active Bank #2 Bank #3 Idle ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 tRRD AP* Read Active Bank #1 ax3 tAC Active Read Read AP* * AP is the internal precharge start timing - 44 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.5 Interleaved Bank Write (Burst Length = 8) 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRP tRAS CAS tRCD tRCD tRCD WE BA0 BA1 A10 RAa Address RAa RBb CAx RAc CBy RBb CAz RAc DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 tRRD Bank #0 Active Bank #2 Bank #3 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 tRRD Precharge Write Active Bank #1 by1 Write Active Write Precharge Idle - 45 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRAS tRP tRP tRAS CAS WE BA0 BA1 tRCD A10 RAa Address RAa tRCD tRCD RAc RBb CAx RBb CBy RAc CAz DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 tRRD Bank #0 Active Bank #2 Bank #3 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 tRRD Active Write Active Bank #1 by1 Idle AP* | Write Write | AP* * AP is the internal precharge start timing - 46 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tCCD tCCD tCCD CS tRAS tRP tRAS tRP RAS CAS WE BA0 BA1 tRCD A10 RAa Address RAa tRCD RBb RBb CAI CBx CAy CAm CBz DQM CKE tAC DQ tAC al0 al1 al2 al3 bx0 tAC bx1 tAC tAC Ay0 Ay1 Ay2 am0 am1 am2 bz0 bz1 bz2 bz3 tRRD Bank #0 Active Active Bank #1 Bank #2 Bank #3 Read Read Read Read Precharge Read AP* Idle * AP is the internal precharge start timing - 47 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS tRP RAS CAS WE BA0 BA1 tRCD A10 Address RAa RAa CAx CAy DQM CKE tAC DQ tWR ax0 Q Q Bank #0 Active Read ax1 ax3 ax2 Q Q ax5 ax4 Q Q ay1 ay0 D D Write ay2 D ay4 ay3 D D Precharge Bank #1 Bank #2 Bank #3 Idle - 48 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BA0 BA1 tRCD A10 Address tRCD RAa RAa RAb CAw RAb CAx DQM CKE tAC DQ Bank #0 tAC aw0 Active Read aw1 AP* aw2 bx0 aw3 Active Read bx1 bx2 bx3 AP* Bank #1 Bank #2 Bank #3 Idle * AP is the internal precharge start timing - 49 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.10 Auto Precharge Write (Burst Length = 4) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BA0 BA1 tRCD tRCD A10 RAa Address RAa RAc RAb CAw RAb CAx RAc DQM CKE DQ Bank #0 aw0 Active Write aw1 aw2 bx0 aw3 AP* Active Write bx1 bx2 bx3 AP* Active Bank #1 Bank #2 Bank #3 Idle * AP is the internal precharge start timing - 50 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.11 Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRP tRFC tRFC CS RAS CAS WE BA0,BA1 A10 Address DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 51 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.12 Self Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP RAS CAS WE BA0,BA1 A10 Address DQM tSB CKE tCKS tCKS tCKS DQ tRFC All Bank Precharge Self Refresh Entry Self Refresh Exit Device Deselect (DSL) Cycle Arbitrary Cycle Note: The device exit the Self Refresh mode asynchronously at the rising edge of the CKE signal. After CKE goes high, the Device Deselect or No-operation command must be registered at the immediately following CLK rising edge, and CKE must remain high at least for tCKS delay immediately after exit the Self Refresh Mode. A bust of 8K auto refeesh cycle within 7.8us before entering and exiting is necessary if the system does not use the auto refresh function. - 52 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.13 Power Down Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BA A10 RAa Address RAa RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS tCKS DQ ax0 Active DSL Power Down Mode Power Down Mode Entry Exit ax1 ax2 tCKS ax3 Precharge & Power Down Mode Entry Active Device Deselect Power Down Mode Exit Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode. When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data. - 53 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.14 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS tRCD WE BA0 BA1 A10 RBa Address RBa CBv CBw CBx CBy CBz DQM CKE tAC tAC DQ av0 Q Bank #0 Active Bank #1 Bank #2 Bank #3 Read av1 Q av3 av2 Q Q aw0 ax0 D D ay0 D az1 az0 Q Q az2 Q az3 Q Single Write Read Idle - 54 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.15 Deep Power Down Mode Entry 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP RAS CAS WE BA0,BA1 A10 Address DQM tSB CKE tCKS DQ Active Banks Precharge Deep Power Down Entry - 55 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.16 Deep Power Down Mode Exit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP tRSC tRSC RAS CAS WE A10 OP-Code OP-Code Address DQM CKE tCKS DQ 200μs DSL tRCF All Banks Precharge Deep Power Down Exit Extended Mode Register Set Auto Refresh Auto Refresh Auto Refresh Arbitrary Cycle Mode Register Set Issue Auto Refresh cycle two or more Note: The device exits the Deep Power Down Mode asynchronously at the rising edge of the CKE signal. After CKE goes high, the Device Deselect or No-operation command must be register at the immediately following CLK rising edge, and CKE must remain high at least for tCKS delay immediately after exiting the Deep Power Down Mode. - 56 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.17 Auto Precharge Timing (Read Cycle) 0 1 Read AP 2 3 4 5 6 7 8 9 10 11 (1) CAS Latency=2 ( a ) burst length = 1 Command Act tRP DQ Q0 ( b ) burst length = 2 Command Read AP Act tRP DQ Q0 Q1 ( c ) burst length = 4 Command Read AP Act tRP DQ Q0 Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Act tRP Q7 (2) CAS Latency=3 ( a ) burst length = 1 Command Read AP Act tRP Q0 DQ ( b ) burst length = 2 Command Read AP Act tRP Q0 DQ Q1 ( c ) burst length = 4 Command Read AP Act tRP Q0 DQ Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP Act tRP Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Q7 Note: Read AP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min). “Dn” = Write data, and “Qn” = Read data - 57 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.18 Auto Precharge Timing (Write Cycle) 0 1 2 3 4 5 6 7 8 9 10 11 12 (1) burst length = 1 Command Write AP Act tWR DQ tRP D0 (2) burst length = 2 Command Write AP Act tWR DQ D0 tRP D1 (3) burst length = 4 Command AP Write Act tRP tWR DQ D0 D1 D2 D3 (4) burst length = 8 Command Write AP tWR DQ D0 Note: D1 D2 Wirte D3 D4 D5 D6 Act tRP D7 represents the Write with Auto precharge command. AP represents the start of internal precharging. Act represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min). “Dn” = Write data, and “Qn” = Read data - 58 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.19 Timing Chart of Read to Write Cycle In the case of Burst Length = 4 1 2 Read Write 0 (1) CAS Latency = 2 DQM Latency = 2 ( a ) Command 3 4 5 6 D1 D2 D3 D0 D1 D2 D1 D2 D3 D1 D2 7 8 9 10 9 10 11 DQM DQ D0 Read ( b ) Command Write DQM DQ D3 (2) CAS Latency = 3 DQM Latency = 2 Read ( a ) Command Write DQM D0 DQ Read ( b ) Command Write DQM D0 DQ D3 Note: The Output data must be masked by DQM to avoid I/O conflict. “Dn” = Write data, and “Qn” = Read data 10.20 Timing Chart for Write to Read Cycle In the case of Burst Length=4 0 1 2 3 4 5 6 7 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 11 (1) CAS Latency=2 ( a ) Command Write DQM DQ ( b ) Command Read tLDR D0 Read Write tLDR DQM DQ (2) CAS Latency=3 ( a ) Command D0 Write DQM D1 Read tLDR D0 DQ ( b ) Command Write Read tLDR DQM DQ D0 D1 Q3 Note: “Dn” = Write data, and “Qn” = Read data - 59 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.21 Timing Chart for Burst Stop Cycle (Burst Stop Command) 0 (1) Read cycle 1 2 3 4 5 6 7 8 9 10 11 ( a ) CAS latency =2 Command Read BST DQ Q0 Q1 Q2 Q3 Q4 Q0 Q1 BST Q2 Q3 ( b )CAS latency = 3 Command Read DQ Q4 (2) Write cycle Command Write Q0 DQ BST Q1 Q2 Q3 Q4 Note: BST represents the Burst stop command “Dn” = Write data, and “Qn” = Read data 10.22 Timing Chart for Burst Stop Cycle (Precharge Command) In the case of urst Length = 8 (1) Read cycle (a) CAS latency =2 Command 0 1 2 3 4 Read 5 6 7 8 9 10 11 PRCG DQ Q0 Q1 Q2 Q3 Q4 (b) CAS latency =3 Command Read PRCG DQ (2) Write cycle (a) CAS latency =2 Command Write DQM Latency = 0 Q0 Q1 Q2 Q3 Q4 PRCG Write tWR DQM DQ (b) CAS latency =3 Command Q0 Q1 Q2 Q3 Q4 PRCG Write tWR Write DQM Latency = 0 DQM DQ Q0 Q1 Q2 Q3 Q4 Note: PRCG represents the Precharge command. “Dn” = Write data, and “Qn” = Read data. - 60 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.23 CKE/DQM Input Timing (Write Cycle) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D6 D5 DQM MASK CKE MASK (1) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (2) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 D4 D5 D6 External CLK Internal CKE DQM DQ CKE MASK Note) “Dn” = Write data, and “Qn” = Read data (3) - 61 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 10.24 CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 Q1 Q2 Q3 Q4 5 6 7 External CLK Internal CKE DQM DQ Q6 Open Open (1) CLK cycle No. 1 2 3 Q1 Q2 Q3 4 5 7 6 External CLK Internal CKE DQM DQ Q4 Q6 Open (2) CLK cycle No. 1 2 Q1 Q2 3 4 5 6 7 External CLK Internal CKE DQM DQ Note) “Dn” = Write data, and “Qn” = Read data Q3 Q4 Q5 Q6 (3) - 62 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 11. PACKAGE DIMENSION 11.1 : LPSDR X 16 VFBGA54Ball (8X9 MM^2, Ball pitch:0.8mm) Note: 1. Ball land:0.5mm. Ball opening:0.4mm. PCB Ball land suggested ≦0.4mm 2. Dimensions apply to Solder Balls Post-Reflow.The Pre-Reflow diameter is 0.42 on a 0.4 SMD Ball Pad - 63 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 11.2 : LPSDR X 32 VFBGA90Ball (8X13 MM^2, Ball pitch:0.8mm) Note: 1. Ball land:0.5mm. Ball opening:0.4mm. PCB Ball land suggested ≦0.4mm 2. Dimensions apply to Solder Balls Post-Reflow. The Pre-Reflow diameter is 0.42 on a 0.4 SMD Ball Pad. - 64 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 12.ORDERING INFORMATION Mobile LPDDR/LPSDR SDRAM Package Part Numbering W 98 9 D 6 C B G X 6 I Product Line 98:mobile LPSDR SDRAM 94:mobile LPDDR SDRAM Temperature with standard Idd6 G:-25C~85C Density 7:27=128M 8:28=256M 9:29=512M with low power Idd6 E:-25C~85C I:-40C~85C Power Supply D:1.8/1.8 VDD / VDDQ Clock rate 5:5ns200MHz 6:6ns166MHz 7:7.5ns133MHz I/O Ports width 6:16bit 2:32bit Package Material X: Lead-free + Halogen-free Generation Design revision. Package configuration code G: 54VFBGA, 8mmx9mm H: 60VFBGA, 8mmx9mm J: 90VFBGA, 8mmx13mm Package or KGD K: KGD B: BGA Part number W989D6CBGX6I W989D6CBGX6E W989D6CBGX7E W989D6CBGX7G W989D2CBJX6I W989D2CBJX6E W989D2CBJX7E W989D2CBJX7G VDD/VDDQ I/O width Package 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 1.8V/1.8V 16 16 16 16 32 32 32 32 54VFBGA 54VFBGA 54VFBGA 54VFBGA 90VFBGA 90VFBGA 90VFBGA 90VFBGA - 65 - Others 166MHz, -40C~85C, Low 166MHz, -25C~85C, Low 133MHz, -25C~85C, Low 133MHz, -25C~85C 166MHz, -40C~85C, Low 166MHz, -25C~85C, Low 133MHz, -25C~85C, Low 133MHz, -25C~85C Power Power Power Power Power Power Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR 13. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A01-001 03/09/2011 All Product datasheet for customer. A01-002 03/24/2011 All 4 9 12 Update name of document title. Update operating temperature range. Update Idd2N value to 10mA. Update tRFC value to 72ns. A01-003 04/25/2011 9 10 12 Update IDD3P value. Add PASR. Change 6.6.2 figure. A01-004 06/27/2011 8,9 Update IDD2P,IDD4 value. A01-005 09/22/2011 8,9 Update IDD3P,IDD3N value. - 66 - Publication Release Date: Sep, 22, 2011 Revision A01-005 W989D6CB / W989D2CB 512Mb Mobile LPSDR Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation where in personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. ------------------------------------------------------------------------------------------------------------------------------------------------Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in the datasheet belong to their respective owners. - 67 - Publication Release Date: Sep, 22, 2011 Revision A01-005