W9825G6EH 4 M × 4 BANKS × 16 BITS SDRAM Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. AVAILABLE PART NUMBER...................................................................................................... 3 4. PIN CONFIGURATION ............................................................................................................... 4 5. PIN DESCRIPTION..................................................................................................................... 5 6. BLOCK DIAGRAM ...................................................................................................................... 6 7. FUNCTIONAL DESCRIPTION.................................................................................................... 7 7.1 Power Up and Initialization ............................................................................................. 7 7.2 Programming Mode Register.......................................................................................... 7 7.3 Bank Activate Command ................................................................................................ 7 7.4 Read and Write Access Modes ...................................................................................... 7 7.5 Burst Read Command .................................................................................................... 8 7.6 Burst Write Command .................................................................................................... 8 7.7 Read Interrupted by a Read ........................................................................................... 8 7.8 Read Interrupted by a Write............................................................................................ 8 7.9 Write Interrupted by a Write............................................................................................ 8 7.10 Write Interrupted by a Read............................................................................................ 8 7.11 Burst Stop Command ..................................................................................................... 8 7.12 Addressing Sequence of Sequential Mode .................................................................... 9 7.13 Addressing Sequence of Interleave Mode...................................................................... 9 7.14 Auto-precharge Command ........................................................................................... 10 7.15 Precharge Command.................................................................................................... 10 7.16 Self Refresh Command ................................................................................................ 10 7.17 Power Down Mode ....................................................................................................... 11 7.18 No Operation Command............................................................................................... 11 7.19 Deselect Command ...................................................................................................... 11 7.20 Clock Suspend Mode.................................................................................................... 11 8. OPERATION MODE ................................................................................................................. 12 9. ELECTRICAL CHARACTERISTICS......................................................................................... 13 9.1 Absolute Maximum Ratings .......................................................................................... 13 9.2 Recommended DC Operating Conditions .................................................................... 13 -1- Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 10. 11. 12. 9.3 Capacitance .................................................................................................................. 13 9.4 DC Characteristics ........................................................................................................ 14 9.5 AC Characteristics and Operating Condition................................................................ 15 TIMING WAVEFORMS ............................................................................................................. 17 10.1 Command Input Timing ................................................................................................ 17 10.2 Read Timing.................................................................................................................. 18 10.3 Control Timing of Input/Output Data ............................................................................. 19 10.4 Mode Register Set Cycle .............................................................................................. 20 OPERATING TIMING EXAMPLE ............................................................................................. 21 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 21 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)........... 22 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 23 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)........... 24 11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 25 11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 26 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 27 11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ................................... 28 11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ........................................ 29 11.10 Auto-precharge Write (Burst Length = 4) .................................................................... 30 11.11 Auto Refresh Cycle ..................................................................................................... 31 11.12 Self Refresh Cycle....................................................................................................... 32 11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)............................ 33 11.14 Power Down Mode ...................................................................................................... 34 11.15 Auto-precharge Timing (Read Cycle).......................................................................... 35 11.16 Auto-precharge Timing (Write Cycle).......................................................................... 36 11.17 Timing Chart of Read to Write Cycle........................................................................... 37 11.18 Timing Chart of Write to Read Cycle........................................................................... 37 11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 38 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 38 11.21 CKE/DQM Input Timing (Write Cycle)......................................................................... 39 11.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 40 PACKAGE SPECIFICATION .................................................................................................... 41 12.1 13. 54L TSOP II - 400 mil ................................................................................................... 41 REVISION HISTORY ................................................................................................................ 42 -2- Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 1. GENERAL DESCRIPTION W9825G6EH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 4M words × 4 banks × 16 bits. W9825G6EH delivers a data bandwidth of up to 200M words per second (-5). To fully comply with the personal computer industrial standard, W9825G6EH is sorted into the following speed grades: -5/-6/-6I/-6A/-75/75I and 75A. The -5 is compliant to the 200MHz/CL3 specification. The -6 is compliant to the 166MHz/CL3 or 133MHz/CL2 specification. The -6I/-6A is compliant to the 166MHz/CL3 specification (the -6I industrial grade, -6A automotive grade which is guaranteed to support -40°C ~ 85°C). The -75/75I/75A is compliant to the 133MHz/CL3 specification (the 75I industrial grade, 75A automotive grade which is guaranteed to support -40°C ~ 85°C). Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9825G6EH is ideal for main memory in high performance applications. 2. FEATURES • • • • • • • • • • • • • 3.3V ± 0.3V Power Supply Up to 200 MHz Clock Frequency 4,194,304 Words × 4 Banks × 16 Bits Organization Self Refresh Mode: Standard and Low Power CAS Latency: 2 and 3 Burst Length: 1, 2, 4, 8 and Full Page Burst Read, Single Writes Mode Byte Data Controlled by LDQM, UDQM Power Down Mode Auto-precharge and Controlled Precharge 8K Refresh Cycles/64 mS Interface: LVTTL Packaged in TSOP II 54-pin, 400 mil - 0.80, using Lead free materials with RoHS compliant 3. AVAILABLE PART NUMBER PART NUMBER W9825G6EH-5 W9825G6EH-6 W9825G6EH-6I W9825G6EH-6A W9825G6EH-75 W9825G6EH75I W9825G6EH75A SPEED GRADE SELF REFRESH CURRENT (MAX) 200MHz/CL3 166MHz/CL3 or 133MHz/CL2 166MHz/CL3 166MHz/CL3 133MHz/CL3 133MHz/CL3 133MHz/CL3 -3- OPERATING TEMPERATURE 3mA 0°C ~ 70°C 3mA 0°C ~ 70°C 3mA 3mA 3mA 3mA 3mA -40°C ~ 85°C -40°C ~ 85°C 0°C ~ 70°C -40°C ~ 85°C -40°C ~ 85°C Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 4. PIN CONFIGURATION VDD 1 54 VSS DQ0 2 53 DQ15 VDDQ 3 52 VSSQ DQ1 4 51 DQ14 DQ2 5 50 DQ13 VSSQ 6 49 VDDQ DQ3 7 48 DQ12 DQ4 8 47 DQ11 VDDQ 9 46 VSSQ DQ5 10 45 DQ10 DQ6 11 44 DQ9 VSSQ 12 43 VDDQ DQ7 13 42 DQ8 VDD 14 41 VSS LDQM 15 40 NC WE 16 39 UDQM CAS 17 38 CLK RAS 18 37 CKE CS 19 36 A12 BS0 20 35 A11 BS1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 VDD 27 28 VSS -4- Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 5. PIN DESCRIPTION PIN NUMBER PIN NAME FUNCTION 23−26, 22, 29−36 A0−A12 Address 20, 21 BS0, BS1 Bank Select 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, DQ0−DQ15 45, 47, 48, 50, 51, 53 19 18 CS RAS DESCRIPTION Multiplexed pins for row and column address. Row address: A0−A12. Column address: A0−A8. Select bank to activate during row address latch time, or bank to read/write during address latch time. Data Multiplexed pins for data output and input. Input/Output Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of Row Address the clock, RAS , CAS and WE define the operation Strobe to be executed. Column Address Strobe 17 CAS 16 WE 15, 39 LDQM, UDQM 38 CLK Clock Inputs 37 CKE CKE controls the clock activation and deactivation. Clock Enable When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. 1, 14, 27 VDD Power (+3.3V) Power for input buffers and logic circuit inside DRAM. 28, 41, 54 VSS 3, 9, 43, 49 VDDQ Power (+3.3V) Separated power from VDD, to improve DQ noise for I/O Buffer immunity. 6, 12, 46, 52 VSSQ Ground Separated ground from VSS, to improve DQ noise for I/O Buffer immunity. 40 NC Referred to RAS Write Enable Referred to RAS The output buffer is placed at Hi-Z(with latency of 2) Input/Output when DQM is sampled high in read cycle. In write Mask cycle, sampling DQM high will block the write operation with zero latency. Ground No Connection System clock used to sample inputs on the rising edge of clock. Ground for input buffers and logic circuit inside DRAM. No connection. (NC pin should be connected to GND or floating) -5- Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 6. BLOCK DIAGRAM CLK CLOCK BUFFER CKE CS CO NTRO L RAS G ENERATO R SIG NAL CO MMAND CAS DECO DER CO LUMN DECODER COLUMN DECO DER A10 MO DE REG IST ER A0 CELL ARRAY BANK #0 CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER DAT A CO NT RO L DQ BUFFER CIRCUIT DQ0 DQ15 CO LUMN COUNT ER LDQM UDQM CO LUMN DECO DER COLUMN DECO DER RO W DECO DER REFRESH CO UNT ER RO W DECO DER A9 A11 A12 BS0 BS1 RO W DECO DER RO W DECO DER WE CELL ARRAY BANK #2 SENSE AMPLIFIER CELL ARRAY BANK #3 SENSE AMPLIFIER Note: The cell array configuration is 8192 * 512 * 16. -6- Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 7. FUNCTIONAL DESCRIPTION 7.1 Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VDD + 0.3V on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. 7.2 Programming Mode Register After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table. 7.3 Bank Activate Command The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS (max). 7.4 Read and Write Access Modes After a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. -7- Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 7.5 Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode. 7.6 Burst Write Command The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. 7.7 Read Interrupted by a Read A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS Latency from the interrupting Read Command the is satisfied. 7.8 Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. 7.9 Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. 7.11 Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst read cycle interrupted by Burst Stop. -8- Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 7.12 Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 n BL = 2 (disturb address is A0) Data 1 n+1 No address carry from A0 to A1 Data 2 n+2 BL = 4 (disturb addresses are A0 and A1) Data 3 n+3 No address carry from A1 to A2 Data 4 n+4 Data 5 n+5 BL = 8 (disturb addresses are A0, A1 and A2) Data 6 n+6 No address carry from A2 to A3 Data 7 n+7 7.13 Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA ACCESS ADDRESS Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 -9- BURST LENGTH BL = 2 BL = 4 BL = 8 Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 7.14 Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is entered. During Auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS Latency. A Read or Write Command with Auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with Auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-pecharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-pecharge function is initiated. The SDRAM automatically enters the precharge operation two clock delay from the last burst write cycle. This delay is referred to as Write tWR. The bank undergoing Auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS (min). 7.15 Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits A10, BS0 and BS1 are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). 7.16 Self Refresh Command The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. Any subsequent commands can be issued after tXSR from the end of Self Refresh Command. If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 8,192 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. - 10 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 7.17 Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCKS (min) + tCK (min). 7.18 No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS , CAS and WE signals become don't cares. 7.20 Clock Suspend Mode During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. - 11 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 8. OPERATION MODE Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (Note (1) , (2)) DEICE STATE COMMAND CKEn-1 CKEn DQM BS0, 1 A10 A0−A9 A11, A12 CS RAS CAS WE Bank Active Idle H x x v v v L L H H Bank Precharge Any H x x v L x L L H L Precharge All Any H x x x H x L L H L Write Active (3) H x x v L v L H L L Write with Autoprecharge Active (3) H x x v H v L H L L Read Active (3) H x x v L v L H L H Read with Autoprecharge Active (3) H x x v H v L H L H Idle H x x v v v L L L L Mode Register Set No-operation Any H x x x x x L H H H Active (4) H x x x x x L H H L Device Deselect Any H x x x x x H x x x Auto-refresh Idle H H x x x x L L L H Self-refresh Entry Idle H L x x x x L L L H Self-refresh Exit Idle (S.R.) L H x x x x H x x x L H x x x x L H H x Clock Suspend Mode Entry Active H L x x x x x x x x Idle Active (5) H H L L x x x x x x x x H L x H x H x x Active L H x x x x x x x x Any (Power Down) L L H H x x x x x x x x H L x H x H x x Data Write/Output Enable Active H x L x x x x x x x Data Write/Output Disable Active H x H x x x x x x x Burst Stop Power Down Mode Entry Clock Suspend Mode Exit Power Down Mode Exit Notes: (1) v = valid x = Don't care L = Low Level H = High Level (2) CKEn signal is input level when commands are provided. CKEn-1 signal is the input level one clock cycle before the command is issued. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. - 12 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT NOTES Input, Output Voltage VIN, VOUT -0.5 ~ VDD + 0.5 (≤ 4.6V max.) V 1 Supply Voltage VDD, VDDQ -0.5 ~ 4.6 V 1 Operating Temperature (-5/-6/-75) TOPR 0 ~ 70 °C 1 Operating Temperature (-6I/-6A/75I/75A) TOPR -40 ~ 85 °C 1 Storage Temperature TSTG -55 ~ 150 °C 1 TSOLDER 260 °C 1 PD 1 W 1 IOUT 50 mA 1 Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Note: 1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 9.2 Recommended DC Operating Conditions (TA = 0 to 70°C for -5/-6/-75, TA = -40 to 85°C for -6I/-6A/75I/75A) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES VDD 3.0 3.3 3.6 V 2 VDDQ 3.0 3.3 3.6 V 2 Input High Voltage VIH 2.0 - VDD + 0.3 V 2 Input Low Voltage VIL -0.3 - 0.8 V 2 Supply Voltage Supply Voltage (for I/O Buffer) Note 2: VIH(max) = VDD/VDDQ+1.5V for pulse width < 5 nS VIL(min) = VSS/VSSQ-1.5V for pulse width < 5 nS 9.3 Capacitance (VDD = 3.3V ± 0.3V, f = 1 MHz, TA = 25°C) PARAMETER SYMBOL MIN. MAX. UNIT Input Capacitance (A0 to A12, BS0, BS1, CS , RAS , CAS , WE , LDQM, UDQM, CKE) CI - 3.8 pf Input Capacitance (CLK) CCLK - 3.5 pf Input/Output Capacitance CIO - 6.5 pf Note: These parameters are periodically sampled and not 100% tested. - 13 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 9.4 DC Characteristics (VDD = 3.3V ± 0.3V, TA = 0 to 70°C for -5/-6/-75, TA = -40 to 85°C for -6I/-6A/75I/75A) PARAMETER SYM. -5 -6/-6I/-6A -75/75I/75A MAX. MAX. MAX. UNIT NOTES Operating Current tCK = min., tRC = min. 1 Bank operation IDD1 110 100 90 3 CKE = VIH IDD2 65 50 35 3 IDD2P 2 2 2 3 IDD2S 15 15 15 IDD2PS 2 2 2 IDD3 85 70 55 IDD3P 15 10 10 IDD4 170 150 130 3, 4 IDD5 220 200 180 3 IDD6 3 3 3 SYMBOL MIN. MAX. UNIT II(L) -5 5 µA IO(L) -5 5 µA VOH 2.4 - V VOL - 0.4 V Active precharge command cycling without burst operation Standby Current tCK = min., CS = VIH VIH/L = VIH (min.)/VIL (max.) Bank: Inactive state CKE = VIL (Power Down Mode) Standby Current CKE = VIH CLK = VIL, CS = VIH VIH/L=VIH (min.)/VIL (max.) Bank: Inactive state CKE = VIL (Power Down Mode) No Operating Current CKE = VIH tCK = min., CS = VIH(min) Bank: Active state (4 Banks) CKE = VIL (Power Down Mode) mA Burst Operating Current tCK = min. Read/ Write command cycling Auto Refresh Current tCK = min. Auto refresh command cycling Self Refresh Current Self Refresh Mode CKE = 0.2V PARAMETER Input Leakage Current (0V ≤ VIN ≤ VDD, all other pins not under test = 0V) Output Leakage Current (Output disable, 0V ≤ VOUT ≤ VDDQ) LVTTL Output “H” Level Voltage (IOUT = -2 mA ) LVTTL Output “L” Level Voltage (IOUT = 2 mA ) - 14 - NOTES Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 9.5 AC Characteristics and Operating Condition (VDD = 3.3V ± 0.3V, TA = 0 to 70°C for -5/-6/-75, TA = -40 to 85°C for -6I/-6A/75I/75A) PARAMETER SYM. -5 MIN. -6 MAX. MIN. -6I/-6A MAX. MIN. -75/75I/75A MAX. MIN. MAX. Ref/Active to Ref/Active Command Period tRC 55 Active to precharge Command Period tRAS 40 Active to Read/Write Command Delay Time tRCD 15 15 18 20 Read/Write(a) to Read/Write(b) Command Period tCCD 1 1 1 1 Precharge to Active Command Period tRP 15 15 18 20 Active(a) to Active(b) Command Period tRRD 2 2 2 2 2 2 2 2 2 2 2 2 Write Recovery Time CLK Cycle Time CL* = 2 CL* = 3 CL* = 2 CL* = 3 CLK High Level width CLK Low Level width Access Time from CLK CL* = 2 CL* = 3 Output Data Hold Time Output Data High Impedance Time tWR tCK CL* = 3 100000 42 60 100000 42 65 100000 45 100000 tCK tCK 1000 7.5 1000 10 1000 10 1000 5 1000 6 1000 6 1000 7.5 1000 2 tCL 2 tAC 2 2 Output Data Low Impedance Time tLZ 0 Power Down Mode Entry Time tSB 0 Transition Time of CLK (Rise and Fall) tT 2.5 2 8 2.5 8 6 6 6 6 5 5 5 5.4 2 tHZ 2 2* nS tCK 10 tCH tOH CL* = 2 60 UNIT NOTES 2 9 3 9 5.4 5.4 5.4 6 7 5 5.4 5.4 5.4 7 0 6 0 1 0 7 0 1 0 7 0 1 9 7.5 nS 1 Data-in Set-up Time tDS 1.5 1.5 1.5 1.5 8 Data-in Hold Time tDH 1.0 0.8 0.8 1.0 8 Address Set-up Time tAS 1.5 1.5 1.5 1.5 8 Address Hold Time tAH 1.0 0.8 0.8 1.0 8 CKE Set-up Time tCKS 1.5 1.5 1.5 1.5 8 CKE Hold Time tCKH 1.0 0.8 0.8 1.0 8 Command Set-up Time tCMS 1.5 1.5 1.5 1.5 8 Command Hold Time tCMH 1.0 Refresh Time tREF Mode register Set Cycle Time tRSC 2 2 2 2 tCK Exit self refresh to ACTIVE command tXSR 70 72 72 75 nS 0.8 64 0.8 64 1.0 64 8 64 mS *CL = CAS Latency *If tCK ≧ 7.5 nS @CL2, tOH min. = 2.5 nS is guaranteed by W9825G6EH-6 - 15 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH Notes: 1. Operation exceeds " Absolute Maximum Ratings " may cause permanent damage to the devices. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up sequence please refer to "Functional Description" section described before. 6. AC Test Load diagram. 1.4 V 50 ohms output Z = 50 ohms 30pF AC TEST LOAD 7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 8. Assumed input rise and fall time (tT ) = 1nS. If tr & tf is longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter ( The tT maximum can’t be more than 10nS for low frequency application. ) 9. If clock rising time (tT) is longer than 1nS, (tT /2-0.5)nS should be added to the parameter. - 16 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 10. TIMING WAVEFORMS 10.1 Command Input Timing tCK tCL tCH VIH CLK VIL tT tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH tCMH tT tCMS CS RAS CAS WE A0-A12 BS0,1 tCKS tCKH tCKS tCKH tCKS tCKH CKE - 17 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 10.2 Read Timing Read CAS Latency CLK CS RAS CAS WE A0-A12 BS0,1 tAC tLZ Valid Data-Out DQ Read Command tHZ tAC tOH tOH Valid Data-Out Burst Length - 18 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 10.3 Control Timing of Input/Output Data Control Timing of Input Data (Word Mask) CLK tCMS tCMH tCMH tCMS DQM tDS tDH tDS tDS Valid Data-in Valid Data-in DQ0~15 tDH tDH tDS Valid Data-in tDH Valid Data-in (Clock Mask) CLK tCKH tCKS tCKH tDH tDS tDH tCKS CKE tDS DQ0~15 Valid Data-in tDS Valid Data-in tDH tDS tDH Valid Data-in Valid Data-in Control Timing of Output Data (Output Enable) CLK tCMS tCMH tCMH tCMS DQM tAC tOH tOH tAC tHZ tOH Valid Data-Out Valid Data-Out DQ0~15 tLZ tAC tOH tAC Valid Data-Out OPEN (Clock Mask) CLK tCKS tCKH tCKH tCKS CKE tOH DQ0~15 tAC tAC tAC tAC tOH tOH Valid Data-Out Valid Data-Out - 19 - tOH Valid Data-Out Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 10.4 Mode Register Set Cycle tRSC CLK tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH CS RAS CAS WE A0-A12 BS0,1 Register set data next command A0 A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency A2 0 0 0 0 1 1 1 1 A6 A0 A7 "0" (Test Mode) A8 "0" Reserved A9 WriteA0 Mode A10 "0" A0 A11 "0" A12 "0" BS0 "0" BS1 "0" A1 A0 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A0 0 1 0 1 0 1 0 1 Reserved A5 A0 A0 0 A0 0 A0 1 A0 1 A0 0 A0 A9 0 1 Reserved Reserved Full Page Addressing Mode Sequential Interleave A0 A3 0 1 A6 0 0 0 0 1 Burst Length Sequential Interleave 1 1 2 2 4 4 8 8 A4 0 1 0 1 0 CAS Latency Reserved Reserved 2 3 Reserved Single Write Mode Burst read and Burst write Burst read and single write * "Reserved" should stay "0" during MRS cycle. - 20 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11. OPERATING TIMING EXAMPLE 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) 0 CLK 1 2 3 4 6 5 CS 7 8 9 10 11 12 13 14 15 tRC 16 17 18 19 21 22 23 tRC tRC RAS 20 tRAS tRC tRP tRP tRAS tRAS tRP tRAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11,A12 RAa tRCD tRCD RBb CAw tRCD RAc CBx RBb RAe RBd RAc CAy RBd CBz RAe DQM CKE tAC DQ aw0 tRRD Bank #0 Active Bank #1 aw1 aw2 aw3 bx0 tRRD Read Precharge Active bx1 bx3 bx2 cy0 tRRD Active cy1 cy2 cy3 tRRD Precharge Read Precharge Read tAC tAC tAC Active Active Read Bank #2 Idle Bank #3 - 21 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD A10 A0-A9, A11,A12 tRCD tRCD RAa RBb RAa CAw tRCD RBd RAc RBb CBx RAc RAe RBd CAy CBz RAe DQM CKE tAC DQ tRRD Bank #0 Active Bank #1 Bank #2 Bank #3 aw1 aw2 aw3 bx0 bx1 tRRD Read Active tAC tAC tAC aw0 bx2 bx3 cy0 cy1 tRRD Active AP* cy3 dz0 tRRD Read AP* Read cy2 Active AP* Active Read Idle * AP is the internal precharge start timing - 22 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD A10 tRCD RBb RAa A0-A9, A11,A12 RAa tRCD CAx RAc RBb RAc CBy CAz DQM CKE tAC DQ tAC ax0 ax1 tRRD Bank #0 Active Bank #1 Bank #2 Bank #3 ax2 ax3 ax4 ax6 by0 by4 by1 by5 by6 by7 CZ0 tRRD Read Precharge ax5 tAC Precharge Active Read Active Read Precharge Idle - 23 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRC CS RAS tRAS tRP tRAS tRAS tRP CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11,A12 RAa tRCD tRCD RAc RBb CAx CBy RBb RAc CAz DQM CKE tAC DQ ax0 ax1 ax2 Active ax4 ax5 AP* Read Active Bank #1 ax3 ax6 ax7 by0 by1 by4 Active Read by5 by6 CZ0 tRRD tRRD Bank #0 tAC tAC AP* Read Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 24 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.5 Interleaved Bank Write (Burst Length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS CAS tRCD tRCD tRCD WE BS0 BS1 A10 A0-A9, A11,A12 RBb RAa RAa CAx RAc CBy RBb RAc CAz DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 tRRD Bank #0 Active Bank #1 Bank #2 Bank #3 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD Precharge Write Active Write Active Write Precharge Idle - 25 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRP tRAS tRAS CAS WE BS0 BS1 tRCD A10 A0-A9, A11,A12 tRCD RAa RAa tRCD RBb CAx RAb CBy RBb RAc CAz DQM CKE ax0 DQ ax1 ax4 ax5 ax6 ax7 by0 by1 tRRD Bank #0 Active Bank #2 Bank #3 Idle by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD AP* Write Active Bank #1 by2 Active Write AP* Write * AP is the internal precharge start timing - 26 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tCCD tCCD tCCD CS tRAS tRAS RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11,A12 RAa tRCD RBb CAI RBb CBx CAy CAm CBz DQM CKE DQ a0 a1 a2 a3 tAC tAC tAC tAC bx0 bx1 Ay0 Ay1 tAC Ay2 am0 am1 am2 bz0 bz1 bz2 bz3 tRRD Bank #0 Active Bank #2 Bank #3 Read Active Bank #1 Read Read Precharge Read Read AP* Idle * AP is the internal precharge start timing - 27 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) 0 1 2 3 5 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11,A12 RAa CAx CAy DQM CKE tAC DQ tWR ax0 Q Q Bank #0 Active ax1 ax2 Q ax3 Q ax5 ax4 Q Q Read ay1 ay0 D D Write ay2 D ay3 D ay4 D Precharge Bank #1 Bank #2 Bank #3 Idle - 28 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) CLK 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC RAS tRAS tRP tRAS CAS WE BS0 BS1 tRCD A10 tRCD RAa A0-A9, A11,A12 RAa RAb CAw RAb CAx DQM CKE tAC DQ tAC aw0 Bank #0 Active Read aw1 AP* aw2 aw3 bx0 Active Read bx1 bx2 bx3 AP* Bank #1 Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 29 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.10 Auto-precharge Write (Burst Length = 4) CLK 0 1 2 3 6 5 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD tRCD A10 RAb RAa A0-A9, A11,A12 RAa CAw RAb RAc CAx RAc DQM CKE DQ aw0 Active Bank #0 Write aw1 aw2 aw3 bx0 AP* Active Write bx1 bx2 bx3 AP* Active Bank #1 Bank #2 Bank #3 Idle * AP is the internal precharge start timing - 30 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.11 Auto Refresh Cycle CLK 0 1 2 3 tRP 4 5 6 7 8 9 10 11 tRC 12 13 14 15 16 17 18 19 20 21 22 23 tRC CS RAS CAS WE BS0,1 A10 A0-A9, A11,A12 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 31 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.12 Self Refresh Cycle CLK CS tRP RAS CAS WE BS0,1 A10 A0-A9, A11,A12 DQM tCKS tSB CKE tCKS DQ tXSR Self Refresh Cycle All Banks Precharge Self Refresh Entry No Operation / Command Inhibit Self Refresh Exit - 32 - Arbitrary Cycle Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS RAS CAS t RCD WE BS0 BS1 A10 A0-A9, A11,A12 RBa RBa CBv CBw CBx CBy CBz aw0 ax0 ay0 az0 az1 az2 az3 D D D Q Q Q Q DQM CKE tAC tAC DQ Bank #0 Active av0 av1 av2 av3 Q Q Q Q Read Single Write Read Bank #1 Bank #2 Bank #3 Idle - 33 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.14 Power Down Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BS A10 A0-A9, A11,A12 RAa RAa RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS ax0 Active tCKS tCKS DQ ax1 ax2 NOP Read ax3 Precharge NOP Active Precharge Standby Power Down mode Active Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode. When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data. - 34 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.15 Auto-precharge Timing (Read Cycle) 0 1 Read AP 2 3 4 5 6 7 8 9 10 11 (1) CAS Latency=2 ( a ) burst length = 1 Command Act tRP Q0 DQ ( b ) burst length = 2 Command Read AP Q0 DQ Act tRP Q1 ( c ) burst length = 4 Command Read AP Act tRP DQ Q0 Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Act tRP Q7 (2) CAS Latency=3 ( a ) burst length = 1 Command Read AP Act tRP Q0 DQ ( b ) burst length = 2 Command Read AP Q0 DQ ( c ) burst length = 4 Command Act tRP Read Q1 AP Act tRP Q0 DQ ( d ) burst length = 8 Command Q1 Q2 Q3 Read AP Q0 DQ Q1 Q2 Q3 Q4 Q5 Act tRP Q6 Q7 Note: Read AP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min). - 35 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.16 Auto-precharge Timing (Write Cycle) 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK (1) CAS Latency = 2 (a) burst length = 1 Command Write AP tWR DQ Act tRP D0 (b) burst length = 2 Command Write AP Act tWR DQ D0 tRP D1 (c) burst length = 4 Command AP Write DQ D0 D1 D2 Act tRP tWR D3 (d) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 (2) CAS Latency = 3 (a) burst length = 1 Command Write AP Act tWR DQ (b) burst length = 2 Command tRP D0 Write AP Act tWR DQ D0 tRP D1 (c) burst length = 4 Command Write AP Act tWR DQ D0 D1 D2 tRP D3 (d) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 Note ) Write represents the Write with Auto precharge command. AP represents the start of internal precharing. Act represents the Bank Active command. When the /auto precharge command is asserted,the period from Bank Activate command to the start of intermal precgarging must be at least tRAS (min). - 36 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.17 Timing Chart of Read to Write Cycle In the case of Burst Length = 4 1 0 2 3 4 5 6 D1 D2 D3 D0 D1 D2 D1 D2 D3 D1 D2 7 8 9 10 9 10 11 (1) CAS Latency=2 Read ( a ) Command Write DQM DQ D0 Read ( b ) Command Write DQM DQ (2) CAS Latency=3 Read ( a ) Command D3 Write DQM D0 DQ Read ( b ) Command Write DQM D0 DQ D3 Note: The Output data must be masked by DQM to avoid I/O conflict. 11.18 Timing Chart of Write to Read Cycle In the case of Burst Length=4 0 1 2 3 4 5 6 7 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 11 (1) CAS Latency=2 ( a ) Command Write Read DQM DQ ( b ) Command D0 Read Write DQM DQ (2) CAS Latency=3 ( a ) Command D0 D1 Write Read DQM DQ ( b ) Command D0 Write Read DQM DQ D0 D1 - 37 - Q3 Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 1 2 3 4 5 6 7 8 9 10 11 (1) Read cycle ( a ) CAS latency =2 Read Command BST Q0 DQ Q1 Q2 Q0 Q1 Q3 Q4 ( b )CAS latency = 3 Read Command BST DQ Q2 Q3 Q4 (2) Write cycle Write Command Q0 DQ BST Q1 Q2 Note: Q3 Q4 BST represents the Burst stop command 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) 0 1 2 3 4 5 6 7 8 9 10 11 (1 ) R e a d c y c le (a ) C A S la te n c y = 2 C om m and Read PRCG DQ (b ) C A S la te n c y = 3 C om m and Q0 Q1 Q2 Read Q3 Q4 PRCG Q0 DQ Q1 Q2 Q3 Q4 (2 ) W r ite c y c le C om m and PRCG W rite tW R DQM DQ Q0 Q1 Q2 Q3 Q4 - 38 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.21 CKE/DQM Input Timing (Write Cycle) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (1) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ DQM MASK D5 D6 5 6 7 D4 D5 D6 CKE MASK (2) CLK cycle No. 1 2 3 D1 D2 D3 4 External CLK Internal CKE DQM DQ CKE MASK (3) - 39 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 11.22 CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 Q1 Q2 Q3 Q4 6 5 7 External CLK Internal CKE DQM DQ Q6 Open Open (1) CLK cycle No. 1 2 3 Q1 Q2 Q3 4 5 6 7 External CLK Internal CKE DQM DQ Q4 Q6 Open (2) CLK cycle No. 1 2 Q1 Q2 3 4 5 6 7 Q4 Q5 Q6 External CLK Internal CKE DQM DQ Q3 (3) - 40 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 12. PACKAGE SPECIFICATION 12.1 54L TSOP II - 400 mil E1 E D C O O1 L L1 O O - 41 - Publication Release Date: Mar. 11, 2010 Revision A09 W9825G6EH 13. REVISION HISTORY VERSION A01 A02 DATE Dec. 12, 2007 Dec. 24, 2007 PAGE All 3, 13~15 A03 Jan. 29, 2008 13 3, 13~15 A04 Apr. 02, 2008 A05 A06 Aug. 01, 2008 Aug. 25, 2008 A07 Jul. 21, 2009 13 41 3, 13~15 13 15 A08 Oct. 12, 2009 15 A09 Mar. 11, 2010 13 3, 13~15 DESCRIPTION Formally data sheet Remove -6I/75I speed grades Revise overshoot/undershoot pulse width Before VIH (max.) = VDDVDDQ +1.2V for pulse width < 5 nS After VIH (max.) = VDD/VDDQ +1.2V for pulse width < 3 nS Before VIL (min.) = VSS/VSSQ -1.2V for pulse width < 5 nS After VIL (min.) = VSS/VSSQ -1.2V for pulse width < 3 nS Add -5/-6I grade parts and remove -6C grade parts Revise overshoot/undershoot pulse width Before VIH (max.) = VDD/VDDQ +1.2V for pulse width < 3 nS After VIH (max.) = VDD/VDDQ +1.5V for pulse width < 5 nS Before VIL (min.) = VSS/VSSQ -1.2V for pulse width < 3 nS After VIL (min.) = VSS/VSSQ -1.5V for pulse width < 5 nS Update 54L TSOP (II) package drawing and dimensions Add 75I industrial garde parts Revise Input/Output Voltage and Power Supply Voltage spec. in section 9.1 Absolute Maximum Ratings table Revise -75/75I grade parts AC parameter output data hold time tOH min. from 2.5 nS to 3 nS Add notice for -6 grade parts AC parameter output data hold time tOH min. If tCK ≧ 7.5 nS @CL2, tOH min. = 2.5 nS is guaranteed Revise soldering temperature from 250°C to 260°C Added -6A and 75A automotive grade parts Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 42 - Publication Release Date: Mar. 11, 2010 Revision A09