CMOS Programmable peripheral Interface WS82C55A Features Description • Pin Compatible with NMOS 8255A The WS82C55A is a high performance CMOS version of the industry standard 8255A and is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. The high performance and industry standard configuration of the WS82C55A make it compatible with the 80C86, and other microprocessors. • 24 Programmable I/O Pins • Fully TTL Compatible • High Speed, No “Wait State” Operation with 5MHz 80C86 and 8MHz 80C88 • Direct Bit Set/Reset Capability • Enhanced Control Word Read Capability • L7 Process Static CMOS circuit design insures low operating power. TTL compatibility over the full military temperature range and bus hold circuitry eliminate the need for pull-up resistors. The advanced SAJI process results in performance equal to or greater than existing functionally equivalent products at a fraction of the power. • 2.5mA Drive Capability on All I/O Ports • Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA Ordering Information SPEED PART NUMBERS WS82C55A-5P WS82C55AP 5MHz WS82C55A-5C 8MHz WS82C55AC 5MHz WS82C55A-5Q SPEED PART NUMBERS 8MHz WS82C55AQ 5MHz 8MHz TEMPERATURE RANGE o o 0 C to 70 C o o 0 C to 70 C o PKG. 40DIP 44 PLCC o 0 C to 70 C 44 QFP RD PA0 PA1 PA2 PA3 NC PA4 PA5 PA6 PA7 WR 34 WR 35 PA7 37 PA5 38 PA4 39 VCC 40 PA3 42 PA1 41 PA2 36 PA6 D1 D2. D3 D4 D5 D6 D7 VCC PB7 7 8 9 10 11 12 13 14 15 16 17 WS82C55A-5C WS82C55AC PLCC-44 18 1920 21 22 23 24 25 26 27 28 PB2 NC PB3 PB4 PB5 PB6 PB7 D0 CS GND A1 A0 PC7 NC PC6 PC5 PC4 PC0 PC1 PB6 21 NC 22 PB3 18 PB4 19 PB5 20 QFP-44 RESET PC2 PC3 PB0 PB1 33 32 31 30 29 28 27 26 25 24 23 WS82C55A-5Q WS82C55AQ VCC DIP-40 28 27 26 25 24 23 22 21 6 5 4 3 2 1 44 43 42 41 40 17 13 14 15 16 17 18 19 20 PA4 PA5 PA6 CS 1 PA7 WR GND 2 RESET A1 3 D0 A0 4 D1 PC7 5 D2 PC6 6 D3 D4 PC5 7 D5 PC4 8 D6 PC0 9 D7 PC1 10 VCC PC2 11 PB7 PB6 PB5 PB4 PB3 PB1 15 PB2 16 40 39 38 37 36 5 35 6 7 WS82C55A-5P 34 8 WS82C55AP 33 32 9 10 31 11 30 12 29 1 2 3 4 NC 12 PC3 13 PB0 14 PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 44 RD 43 PA0 Pinouts CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1 Wing Shing Computer Components Co., (H.K.)Ltd. Homepage: http://www.wingshing.com Tel:(852)2341 9276 Fax:(852)2797 8153 E-mail: [email protected] 39 38 37 36 35 34 33 32 31 30 29 RESET D0 D1 D2 D3 NC D4 D5 D6 D7 VCC WS82C55A Pin Description ( For DIP-40) SYMBOL PIN NUMBER VCC 26 VCC: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is recommended for decoupling. GND 7 GROUND D0-D7 27-34 I/O RESET 35 I RESET: A high on this input clears the control register and all ports (A, B, C) are set to the input mode with the “Bus Hold” circuitry turned on. CS 6 I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. RD 5 I READ: Read is an active low input control signal used by the CPU to read status information or data via the data bus. WR 36 I WRITE: Write is an active low input control signal used by the CPU to load control words and data into the 82C55A. A0-A1 8, 9 I ADDRESS: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1. PA0-PA7 1-4, 37-40 I/O PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are present on this port. PB0-PB7 18-25 I/O PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port. PC0-PC7 10-17 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port. TYPE DESCRIPTION DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus. Functional Diagram POWER SUPPLIES +5V GND GROUP A PORT A (8) GROUP A CONTROL GROUP A PORT C UPPER (4) BI-DIRECTIONAL DATA BUS D7-D0 DATA BUS BUFFER 8-BIT INTERNAL DATA BUS RD WR A1 READ WRITE CONTROL LOGIC GROUP B CONTROL GROUP B PORT C LOWER (4) GROUP B PORT B (8) A0 RESET CS 2 I/O PA7-PA0 I/O PC7-PC4 I/O PC3-PC0 I/O PB7-PB0 WS82C55A Functional Description POWER SUPPLIES Data Bus Buffer This three-state bi-directional 8-bit buffer is used to interface WS82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. +5V GND BI-DIRECTIONAL DATA BUS DATA BUS D7-D0 BUFFER Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. RD WR A1 A0 RESET (CS) Chip Select. A “low” on this input pin enables the communcation between the WS82C55A and the CPU The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a control word to the WS82C55A . The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the WS82C55A INPUT OPERATION (READ) CS 0 0 0 1 0 Port A → Data Bus 0 1 0 1 0 Port B → Data Bus 1 0 0 1 0 Port C → Data Bus 1 1 0 1 0 Control Word → Data Bus GROUP B PORT B (8) I/O PB7PB0 Group A and Group B Controls WS 82C55A BASIC OPERATION WR GROUP B CONTROL I/O PC3PC0 (RESET) Reset. A “high” on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode. “Bus hold” devices internal to the 82C55A will hold the I/O port inputs to a logic “1” state with a maximum hold current of 400µA. (A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1). RD 8-BIT INTERNAL DATA BUS GROUP B PORT C LOWER (4) I/O PC7PC4 FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER, READ/WRITE, GROUP A & B CONTROL LOGIC FUNCTIONS (WR) Write. A “low” on this input pin enables the CPU to write data or control words into the WS82C55A A0 GROUP A PORT C UPPER (4) I/O PA7PA0 CS (RD) Read. A “low” on this input pin enables 82C55A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from” the WS82C55A A1 READ WRITE CONTROL LOGIC GROUP A CONTROL GROUP A PORT A (8) Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports. Control Group A - Port A and Port C upper (C7 - C4) Control Group B - Port B and Port C lower (C3 - C0) OUTPUT OPERATION (WRITE) 0 0 1 0 0 Data Bus → Port A 0 1 1 0 0 Data Bus → Port B 1 0 1 0 0 Data Bus → Port C 1 1 1 0 0 Data Bus → Control The control word register can be both written and read as shown in the “Basic Operation” table. Figure 4 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic “1”, as this implies control word mode information. DISABLE FUNCTION X X X X 1 Data Bus → Three-State X X 1 1 0 Data Bus → Three-State 3 WS82C55A register will contain 9Bh. During the execution of the system program, any of the other modes may be selected using a single output instruction. This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine. Any port programmed as an output port is initialized to all zeros when the control word is written. Ports A, B, and C The WS82C55A contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or “personality” to further enhance the power and flexibility of the WS82C55A ADDRESS BUS Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both “pull-up” and “pull-down” bus-hold devices are present on Port A. See Figure 2A. CONTROL BUS DATA BUS Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. See Figure 2B. Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B. See Figure 2B. C B 8 A I/O PB7-PB0 INPUT MODE MODE 1 MODE 2 OUTPUT MODE VCC I/O 8 I/O PA7-PA0 A I/O 8 CONTROL CONTROL OR I/O OR I/O C I/O PA7-PA0 A BIDIRECTIONAL I/O PB7-PB0 P 4 PC7-PC4 PC3-PC0 B 8 FIGURE 2A. PORT A BUS-HOLD CONFIGURATION I/O C PB7-PB0 INTERNAL DATA OUT (LATCHED) 4 B 8 EXTERNAL PORT A PIN RESET OR MODE CHANGE A0-A1 CS 82C55A MODE 0 MASTER RESET OR MODE CHANGE INTERNAL DATA IN D7-D0 RD, WR CONTROL PA7-PA0 FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE CONTROL WORD INTERNAL DATA IN D7 D6 D5 D4 D3 D2 D1 D0 EXTERNAL PORT B, C PIN INTERNAL DATA OUT (LATCHED) GROUP B PORT C (LOWER) 1 = INPUT 0 = OUTPUT OUTPUT MODE PORT B 1 = INPUT 0 = OUTPUT FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION MODE SELECTION 0 = MODE 0 1 = MODE 1 FIGURE 2. BUS-HOLD CONFIGURATION Operational Description GROUP A Mode Selection PORT C (UPPER) 1 = INPUT 0 = OUTPUT There are three basic modes of operation than can be selected by the system software: Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bi-directional Bus PORT A 1 = INPUT 0 = OUTPUT When the reset input goes “high”, all ports will be set to the input mode with all 24 port lines held at a logic “one” level by internal bus hold devices. After the reset is removed, the WS82C55A can remain in the input mode with no additional initialization required. This eliminates the need to pullup or pulldown resistors in all-CMOS designs. The control word 4 MODE SELECTION 00 = MODE 0 01 = MODE 1 1X = MODE 2 MODE SET FLAG 1 = ACTIVE FIGURE 4. MODE DEFINITION FORMAT WS82C55A This function allows the programmer to enable or disable a CPU interrupt by a specific I/O device without affecting any other device in the interrupt structure. The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be “tailored” to almost any I/O structure. For instance: Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis. INTE Flip-Flop Definition (BIT-SET)-INTE is SET - Interrupt Enable (BIT-RESET)-INTE is Reset - Interrupt Disable NOTE: All Mask flip-flops are automatically reset during mode selection and device Reset. Operating Modes The mode definitions and possible mode combinations may seem confusing at first, but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the 82C55A has taken into account things such as efficient PC board layout, control signal definition vs. PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. Mode 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the three ports. No handshaking is required, data is simply written to or read from a specific port. Mode 0 Basic Functional Definitions: • Two 8-bit ports and two 4-bit ports • Any Port can be input or output Single Bit Set/Reset Feature (Figure 5) • Outputs are latched Any of the eight bits of Port C can be Set or Reset using a single Output instruction. This feature reduces software requirements in control-based applications. • Input are not latched • 16 different Input/Output configurations possible When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as if they were output ports. MODE 0 PORT DEFINITION A CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 X X X DON’T CARE BIT SET/RESET 1 = SET 0 = RESET BIT SELECT 0 1 2 3 4 0 1 0 1 0 0 0 1 1 0 0 0 0 0 1 5 1 0 1 6 0 1 1 7 1 B0 1 B1 1 B2 BIT SET/RESET FLAG 0 = ACTIVE FIGURE 5. BIT SET/RESET FORMAT Interrupt Control Functions When WS82C55A is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset function of port C. 5 B GROUP A PORTC PORT A (Upper) GROUP B # PORTC PORT B (Lower) D4 D3 D1 D0 0 0 0 0 Output Output 0 Output Output 0 0 0 1 Output Output 1 Output Input 0 0 1 0 Output Output 2 Input Output 0 0 1 1 Output Output 3 Input Input 0 1 0 0 Output Input 4 Output Output 0 1 0 1 Output Input 5 Output Input 0 1 1 0 Output Input 6 Input Output 0 1 1 1 Output Input 7 Input Input 1 0 0 0 Input Output 8 Output Output 1 0 0 1 Input Output 9 Output Input 1 0 1 0 Input Output 10 Input Output 1 0 1 1 Input Output 11 Input Input 1 1 0 0 Input Input 12 Output Output 1 1 0 1 Input Input 13 Output Input 1 1 1 0 Input Input 14 Input Output 1 1 1 1 Input Input 15 Input Input WS82C55A Mode 0 (Basic Input) tRR RD tIR tHR INPUT tAR tRA CS, A1, A0 D7-D0 tRD tDF Mode 0 (Basic Output) tWW WR tWD tDW D7-D0 tAW tWA CS, A1, A0 OUTPUT tWB Mode 0 Configurations CONTROL WORD #0 CONTROL WORD #2 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 8 A 82C55A 4 4 8 B 0 0 0 0 1 0 82C55A 4 PC7 - PC4 PA7 - PA0 PC7 - PC4 C D7 - D0 4 PC3 - PC0 8 PB7 - PB0 B PC3 - PC0 PB7 - PB0 CONTROL WORD #3 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 8 A 82C55A D7 - D0 0 8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 A CONTROL WORD #1 1 0 PA7 - PA0 C D7 - D0 0 4 8 B 0 0 0 0 1 1 8 PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 0 D7 - D0 4 8 B 6 PC7 - PC4 C PC3 - PC0 PB7 - PB0 PA7 - PA0 PC3 - PC0 PB7 - PB0 WS82C55A Mode 0 Configurations (Continued) CONTROL WORD #4 CONTROL WORD #8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 8 A 82C55A 4 4 8 B 0 0 1 0 0 82C55A 4 8 8 B 0 1 82C55A PB7 - PB0 0 0 0 1 82C55A 4 PC7 - PC4 PA7 - PA0 PC7 - PC4 C D7 - D0 4 PC3 - PC0 8 PB7 - PB0 B PC3 - PC0 PB7 - PB0 D7 D6 D5 D4 D3 D2 D1 D0 1 4 4 8 B 0 0 1 0 0 1 0 8 PA7 - PA0 A 82C55A 4 PC7 - PC4 PA7 - PA0 PC7 - PC4 C D7 - D0 4 PC3 - PC0 8 PB7 - PB0 B CONTROL WORD #7 PC3 - PC0 PB7 - PB0 CONTROL WORD #11 D7 D6 D5 D4 D3 D2 D1 D0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 1 1 8 A 82C55A D7 - D0 1 8 C D7 - D0 1 0 A 0 8 0 PC3 - PC0 CONTROL WORD #10 A 0 0 PA7 - PA0 D7 D6 D5 D4 D3 D2 D1 D0 0 4 PB7 - PB0 CONTROL WORD #6 1 PC7 - PC4 C D7 - D0 PC3 - PC0 1 B 1 4 PA7 - PA0 D7 D6 D5 D4 D3 D2 D1 D0 4 0 0 PC7 - PC4 C D7 - D0 0 0 82C55A 1 8 0 0 CONTROL WORD #9 A 1 0 8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 A CONTROL WORD #5 1 0 PA7 - PA0 C D7 - D0 0 4 8 B 0 1 0 0 1 1 8 PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 0 D7 - D0 4 8 B 7 PC7 - PC4 C PC3 - PC0 PB7 - PB0 PA7 - PA0 PC3 - PC0 PB7 - PB0 WS82C55A Mode 0 Configurations (Continued) CONTROL WORD #12 CONTROL WORD #14 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 8 A 82C55A 4 4 8 B 0 1 1 1 0 1 0 8 82C55A PA7 - PA0 4 PC7 - PC4 PC7 - PC4 C D7 - D0 4 PC3 - PC0 PC3 - PC0 8 PB7 - PB0 PB7 - PB0 B CONTROL WORD #15 D7 D6 D5 D4 D3 D2 D1 D0 0 1 A CONTROL WORD #13 1 0 PA7 - PA0 C D7 - D0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 1 1 8 A 82C55A D7 - D0 4 8 B 0 1 1 0 1 1 8 PA7 - PA0 PA7 - PA0 A 82C55A 4 PC7 - PC4 C 4 0 PC7 - PC4 C D7 - D0 4 PC3 - PC0 PC3 - PC0 8 PB7 - PB0 PB7 - PB0 B Operating Modes MODE 1 (PORT A) Mode 1 - (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “hand shaking” signals. In mode 1, port A and port B use the lines on port C to generate or accept these “hand shaking” signals. CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 INTE A PC6, PC7 1 = INPUT 0 = OUTPUT Mode 1 Basic Function Definitions: • Two Groups (Group A and Group B) • Each group contains one 8-bit port and one 4-bit control/data port • The 8-bit data port can be either input or output. Both inputs and outputs are latched. • The 4-bit port is used for control and status of the 8-bit port. 8 PA7-PA0 PC4 STBA PC5 IBFA INTRA PC3 RD PC6, PC7 2 I/O MODE 1 (PORT B) CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 Input Control Signal Definition 1 1 1 PB7-PB0 INTE B (Figures 6 and 7) PC2 8 STBB PC1 IBFB PC0 INTRB STB (Strobe Input) A “low” on this input loads data into the input latch. RD IBF (Input Buffer Full F/F) FIGURE 6. MODE 1 INPUT A “high” on this output indicates that the data has been loaded into the input latch: in essence, and acknowledgment. IBF is set by STB input being low and is reset by the rising edge of the RD input. 8 WS82C55A tST STB tSIB IBF tSIT tRIB INTR tRIT RD tPH INPUT FROM PERIPHERAL tPS FIGURE 7. MODE 1 (STROBED INPUT) INTR (Interrupt Request) INTE A A “high” on this output can be used to interrupt the CPU when and input device is requesting service. INTR is set by the condition: STB is a “one”, IBF is a “one” and INTE is a “one”. It is reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into the port. Controlled by Bit Set/Reset of PC6. INTE B Controlled by Bit Set/Reset of PC2. NOTE: 1. To strobe data into the peripheral device, the user must operate the strobe line in a hand shaking mode. The user needs to send OBF to the peripheral device, generates an ACK from the peripheral device and then latch data into the peripheral device on the rising edge of OBF. INTE A Controlled by bit set/reset of PC4. INTE B MODE 1 (PORT A) Controlled by bit set/reset of PC2. PA7-PA0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 Output Control Signal Definition (Figure 8 and 9) 1 0 1 1 1/0 OBF - Output Buffer Full F/F). The OBF output will go “low” to indicate that the CPU has written data out to be specified port. This does not mean valid data is sent out of the part at this time since OBF can go true before data is available. Data is guaranteed valid at the rising edge of OBF, (See Note 1). The OBF F/F will be set by the rising edge of the WR input and reset by ACK input being low. PC4, PC5 1 = INPUT 0 = OUTPUT INTE A 8 PC7 OBFA PC6 ACKA INTRA PC3 WR ACK - Acknowledge Input). A “low” on this input informs the 82C55A that the data from Port A or Port B is ready to be accepted. In essence, a response from the peripheral device indicating that it is ready to accept data, (See Note 1). PC4, PC5 2 MODE 1 (PORT B) PB7-PB0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 INTR - (Interrupt Request). A “high” on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set when ACK is a “one”, OBF is a “one” and INTE is a “one”. It is reset by the falling edge of WR. 1 1 PC1 OBFB PC2 ACKB PC0 INTRB 0 INTE B WR FIGURE 8. MODE 1 OUTPUT 9 8 WS82C55A tWOB WR tAOB OBF INTR tWIT ACK tAK tAIT OUTPUT tWB FIGURE 9. MODE 1 (STROBED OUTPUT) PA7-PA0 RD CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 1 8 PC4 STBA PC5 IIBFA PC6, PC7 1 = INPUT 0 = OUTPUT PC6, PC7 PB7, PB0 WR WR CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 INTRA PC3 0 PA7-PA0 2 1 0 1 0 1/0 I/O OBFB PC2 PC0 PC7 OBFA PC6 ACKA INTRA PC3 1 PC4, PC5 1 = INPUT 0 = OUTPUT 8 PC1 1 8 PC4, PC5 PB7, PB0 2 I/O 8 PC2 STBB ACKB PC1 IBFB INTRB PC0 INTRB RD PORT A - (STROBED INPUT) PORT B - (STROBED OUTPUT) PORT A - (STROBED OUTPUT) PORT B - (STROBED INPUT) Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications. FIGURE 10. COMBINATIONS OF MODE 1 Operating Modes Mode 2 (Strobed Bi-Directional Bus I/O) Output Operations The functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bi-directional bus I/O). “Hand shaking” signals are provided to maintain proper bus flow discipline similar to Mode 1. Interrupt generation and enable/disable functions are also available. OBF - (Output Buffer Full). The OBF output will go “low” to indicate that the CPU has written data out to port A. Mode 2 Basic Functional Definitions: • Used in Group A only • One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Port (Port C) • Both inputs and outputs are latched • The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port (Port A) INTE 1 - (The INTE flip-flop associated with OBF). Controlled by bit set/reset of PC4. ACK - (Acknowledge). A “low” on this input enables the three-state output buffer of port A to send out the data. Otherwise, the output buffer will be in the high impedance state. Input Operations STB - (Strobe Input). A “low” on this input loads data into the input latch. IBF - (Input Buffer Full F/F). A “high” on this output indicates that data has been loaded into the input latch. Bi-Directional Bus I/O Control Signal Definition INTE 2 - (The INTE flip-flop associated with IBF). Controlled by bit set/reset of PC4. (Figures 11, 12, 13, 14) INTR - (Interrupt Request). A high on this output can be used to interrupt the CPU for both input or output operations. 10 WS82C55A CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 INTRA PC3 1/0 1/0 1/0 PA7-PA0 PC2-PC0 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT 8 PC7 OBFA INTE 1 PC6 ACKA INTE 2 PC4 STBA PC5 IBFA WR GROUP B MODE 0 = MODE 0 1 = MODE 1 PC2-PC0 RD FIGURE 11. MODE CONTROL WORD 3 I/O FIGURE 12. MODE 2 DATA FROM CPU TO 82C55A WR tAOB OBF tWOB INTR tAK ACK tST STB tSIB IBF tAD tPS tKD PERIPHERAL BUS tRIB tPH RD DATA FROM PERIPHERAL TO WS82C55A DATA FROM WS82C55A TO PERIPHERAL DATA FROM WS82C55A TO CPU NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD ÷ OBF • MASK • ACK • WR) FIGURE 13. MODE 2 (BI-DIRECTIONAL) 11 WS82C55A MODE 2 AND MODE 0 (INPUT) MODE 2 AND MODE 0 (OUTPUT) PC3 PA7-PA0 1 1 0 1 1/0 PC2-PC0 1 = INPUT 0 = OUTPUT PA7-PA0 8 OBFA PC7 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 PC6 ACKA PC4 STBA PC5 IBFA PC2-PC0 PC3 INTRA 3 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 ACKA PC4 STBA IBFA PC5 3 I/O 8 WR MODE 2 AND MODE 1 (INPUT) PC3 PA7-PA0 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 0 PA7-PA0 8 OBFA PC6 ACKA PC4 STBA PC5 IBFA PC1 PC3 INTRA PC7 PB7-PB0 WR PC6 PB7, PB0 8 MODE 2 AND MODE 1 (OUTPUT) RD OBFA RD PB7-PB0 1 8 PC7 PC2-PC0 I/O WR 1 1/0 PC2-PC0 1 = INPUT 0 = OUTPUT RD 1 0 INTRA CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 OBFB PC2 ACKB PC0 INTRB RD WR FIGURE 14. MODE 2 COMBINATIONS 12 8 PC7 OBFA PC6 ACKA PC4 STBA PC5 IBFA PB7-PB0 8 INTRA 8 PC2 STBB PC1 IBFB PC0 INTRB WS82C55A MODE DEFINITION SUMMARY MODE 1 MODE 0 MODE 2 IN OUT IN OUT PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 In In In In In In In In Out Out Out Out Out Out Out Out In In In In In In In In Out Out Out Out Out Out Out Out PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 In In In In In In In In Out Out Out Out Out Out Out Out In In In In In In In In Out Out Out Out Out Out Out Out PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 In In In In In In In In Out Out Out Out Out Out Out Out INTRB IBFB STBB INTRA STBA IBFA I/O I/O INTRB OBFB ACKB INTRA I/O I/O ACKA OBFA Special Mode Combination Considerations GROUP A ONLY Mode 0 or Mode 1 Only I/O I/O I/O INTRA STBA IBFA ACKA OBFA INPUT CONFIGURATION There are several combinations of modes possible. For any combination, some or all of Port C lines are used for control or status. The remaining bits are either inputs or outputs as defined by a “Set Mode” command. D7 D6 D5 I/O I/O IBFA D4 D3 D2 INTEA INTRA INTEB GROUP A During a read of Port C, the state of all the Port C lines, except the ACK and STB lines, will be placed on the data bus. In place of the ACK and STB line states, flag status will appear on the data bus in the PC2, PC4, and PC6 bit positions as illustrated by Figure 17. D1 D0 IBFB INTRB GROUP B OUTPUT CONFIGURATION D7 D6 OBFA INTEA Through a “Write Port C” command, only the Port C pins programmed as outputs in a Mode 0 group can be written. No other pins can be affected by a “Write Port C” command, nor can the interrupt enable flags be accessed. To write to any Port C output programmed as an output in Mode 1 group or to change an interrupt enable flag, the “Set/Reset Port C Bit” command must be used. D5 D4 I/O I/O D3 D2 D1 D0 INTRA INTEB OBFB INTRB GROUP A GROUP B FIGURE 15. MODE 1 STATUS WORD FORMAT D7 D6 OBFA INTE1 D5 IBFA D4 INTE2 INTRA GROUP A With a “Set/Reset Port Cea Bit” command, any Port C line programmed as an output (including IBF and OBF) can be written, or an interrupt enable flag can be either set or reset. Port C lines programmed as inputs, including ACK and STB lines, associated with Port C fare not affected by a “Set/Reset Port C Bit” command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the “Set Reset Port C Bit” command will affect the Group A and Group B interrupt enable flags, as illustrated in Figure 17. D3 D2 D1 D0 X X X GROUP B (Defined by Mode 0 or Mode 1 Selection) FIGURE 16. MODE 2 STATUS WORD FORMAT Current Drive Capability Any output on Port A, B or C can sink or source 2.5mA. This feature allows the 82C55A to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. 13 WS82C55A Reading Port C Status (Figures 15 and 16) Applications of the WS82C55A-5 In Mode 0, Port C transfers data to or from the peripheral device. When the 82C55A is programmed to function in Modes 1 or 2, Port C generates or accepts “hand shaking” signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the “status” of each peripheral device and change the program flow accordingly. WS82C55A is a very powerful tool for interfacing peripheral equipment to the microcomputer system. It represents the optimum use of available pins and flexible enough to interface almost any I/O device without the need for additional external logic. Each peripheral device in a microcomputer system usually has a “service routine” associated with it. The routine manages the software interface between the device and the CPU. The functional definition of the WS82C55A is programmed by the I/O service routine and becomes an extension of the system software. By examining the I/O devices interface characteristics for both data transfer and timing, and matching this information to the examples and tables in the detailed operational description, a control word can easily be developed to initialize the WS82C55A to exactly "fit" the application. Figures 18 through 24 present a few examples of typical applications of the WS82C55A There is not special instruction to read the status information from Port C. A normal read operation of Port C is executed to perform this function. INTERRUPT ENABLE FLAG POSITION ALTERNATE PORT C PIN SIGNAL (MODE) INTE B PC2 ACKB (Output Mode 1) or STBB (Input Mode 1) INTE A2 PC4 STBA (Input Mode 1 or Mode 2) INTE A1 PC6 ACKA (Output Mode 1 or Mode 2) FIGURE 17. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2 INTERRUPT REQUEST PC3 PA0 PA1 PA2 PA3 PA4 PA5 MODE 1 PA6 (OUTPUT) PA7 PC7 PC6 PC5 PC4 HIGH SPEED PRINTER HAMMER RELAYS DATA READY ACK PAPER FEED FORWARD/REV. 82C55A PB0 PB1 PB2 PB3 PB4 MODE 1 PB5 (OUTPUT) PB6 PB7 PC1 PC2 PAPER FEED FORWARD/REV. RIBBON CARRIAGE SEN. DATA READY ACK PC0 INTERRUPT REQUEST CONTROL LOGIC AND DRIVERS FIGURE 18. PRINTER INTERFACE 14 WS82C55A INTERRUPT REQUEST PC3 MODE 1 (INPUT) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 R0 R1 R2 FULLY R3 DECODED R4 KEYBOARD R5 SHIFT CONTROL PC4 PC5 STROBE ACK INTERRUPT REQUEST PC3 MODE 1 (INPUT) WS82C55A-5 PB0 PB1 PB2 PB3 PB4 MODE 1 PB5 (OUTPUT) PB6 PB7 B0 B1 B2 BURROUGHS SELF-SCAN B3 DISPLAY B4 B5 BACKSPACE CLEAR PC4 PC5 WS PC6 82C55A-5 PC7 MODE 0 (INPUT) DATA READY ACK BLANKING CANCEL WORD PC1 PC2 PC6 PC7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 R0 R1 R2 FULLY R3 DECODED R4 KEYBOARD R5 SHIFT CONTROL STROBE ACK BUST LT TEST LT TERMINAL ADDRESS PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 INTERRUPT REQUEST FIGURE 20. KEYBOARD AND TERMINAL ADDRESS INTERFACE FIGURE 19. KEYBOARD AND DISPLAY INTERFACE INTERRUPT REQUEST PA0 PA1 PA2 PA3 PA4 MODE 0 PA5 (OUTPUT) PA6 PA7 PC4 PC5 PC6 PC7 LSB PC3 12-BIT A/D CONVERTER (DAC) PA0 PA1 PA2 PA3 PA4 PA5 MODE 1 PA6 (OUTPUT) PA7 ANALOG OUTPUT PC7 PC6 PC5 PC4 WS82C55A-5 PC0 PC1 BIT SET/RESET PC2 PC3 PB0 PB1 PB2 MODE 0 (INPUT) PB3 PC4 PC5 PC6 PC7 R0 R1 R2 CRT CONTROLLER R3 • CHARACTER GEN. • REFRESH BUFFER R4 • CURSOR CONTROL R5 SHIFT CONTROL DATA READY ACK BLANKED BLACK/WHITE STB DATA WS82C55A-5 PC2 PC1 PC0 SAMPLE EN STB LSB 8-BIT D/A CONVERTER (ADC) PB0 MODE 0 PB1 (OUTPUT) PB2 PB3 PB4 PB5 PB6 PB7 ANALOG INPUT MAB FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL ROW STB COLUMN STB CURSOR H/V STB CURSOR/ROW/COLUMN ADDRESS H&V FIGURE 22. BASIC CRT CONTROLLER INTERFACE 15 WS82C55A INTERRUPT REQUEST INTERRUPT REQUEST PC3 MODE 2 PC3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 D0 D1 D2 D3 D4 D5 D6 D7 PC4 PC5 PC7 PC6 DATA STB ACK (IN) DATA READY ACK (OUT) FLOPPY DISK CONTROLLER AND DRIVE MODE 1 (INPUT) PB0 PB1 PB2 MODE 0 PB3 (OUTPUT) PB4 PB5 PB6 PB7 R0 R1 R2 R3 R4 R5 R6 R7 PC4 PC5 PC6 STB ACK STOP/GO WS82C55A-5 WS82C55A-5 PC2 PC1 PC0 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 TRACK “0” SENSOR SYNC READY INDEX MODE 0 (INPUT) ENGAGE HEAD FORWARD/REV. READ ENABLE WRITE ENABLE DISC SELECT ENABLE CRC TEST BUSY LT PC0 PC1 PC2 PB0 PB1 PB2 MODE 0 PB3 (OUTPUT) PB4 PB5 PB6 PB7 FIGURE 23. BASIC FLOPPY DISC INTERFACE B LEVEL PAPER TAPE READER MACHINE TOOL START/STOP LIMIT SENSOR (H/V) OUT OF FLUID CHANGE TOOL LEFT/RIGHT UP/DOWN HOR. STEP STROBE VERT. STEP STROBE SLEW/STEP FLUID ENABLE EMERGENCY STOP FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE 16 WS82C55A TA = 25oC Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC+0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) PDIP Package . . . . . . . . . . . . . . . . . . . Operating Conditions θJA θJC 50oC/W N/A Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Junction Temperature Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V Operating Temperature Range o o WS82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 70 C PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VCC = 5.0V ±10%; TA = 0oC to +70oC (WS82C55A-5); LIMITS SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 2.2 - V VIL Logical Zero Input Voltage - 0.8 V VOH Logical One Output Voltage 3.0 VCC -0.4 - V IOH = -2.5mA, IOH = -100µA VOL Logical Zero Output Voltage - 0.4 V IOL +2.5mA II Input Leakage Current -1.0 +1.0 µA VIN = VCC or GND, DIP Pins: 5, 6, 8, 9, 35, 36 IO I/O Pin Leakage Current -10 +10 µA VO = VCC or GND DIP Pins: 27 - 34 IBHH Bus Hold High Current -50 -400 µA VO = 3.0V. Ports A, B, C IBHL Bus Hold Low Current 50 400 µA VO = 1.0V. Port A ONLY IDAR Darlington Drive Current -2.5 Note 2, 4 mA Ports A, B, C. Test Condition 3 ICCSB Standby Power Supply Current - 10 µA VCC = 5.5V, VIN = VCC or GND. Output Open ICCOP Operating Power Supply Current - 1 mA/MHz TA = +25oC, VCC = 5.0V, Typical (See Note 3) NOTES: 2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current. 3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0µs I/O Read/Write cycle time = 1mA). 4. Tested as VOH at -2.5mA. Capacitance SYMBOL TA = 25oC PARAMETER TYPICAL UNITS CIN Input Capacitance 10 pF CI/O I/O Capacitance 20 pF 17 TEST CONDITIONS FREQ = 1MHz, All Measurements are referenced to device GND WS82C55A AC Electrical Specifications o o VCC = +5V± 10%, GND = 0V; TA =0 C to 70 C WS82C55A*5 SYMBOL PARAMETER WS-XX82C55A MIN MAX MIN MAX UNITS TEST CONDITIONS READ TIMING (1) tAR Address Stable Before RD 0 - 0 - ns (2) tRA Address Stable After RD 0 - 0 - ns (3) tRR RD Pulse Width 250 - 150 - ns (4) tRD Data Valid From RD - 200 - 120 ns 1 (5) tDF Data Float After RD 10 75 10 75 ns 2 (6) tRV Time Between RDs and/or WRs 300 - 300 - ns WRITE TIMING (7) tAW Address Stable Before WR 0 - 0 - ns (8) tWA Address Stable After WR 20 - 20 - ns (9) tWW WR Pulse Width 100 - 100 - ns (10) tDW Data Valid to WR High 100 - 100 - ns 30 - 30 - ns (11) tWD Data Valid After WR High OTHER TIMING (12) tWB WR = 1 to Output - 350 - 350 ns (13) tIR Peripheral Data Before RD 0 - 0 - ns (14) tHR Peripheral Data After RD 0 - 0 - ns (15) tAK ACK Pulse Width 200 - 200 - ns (16) tST STB Pulse Width 100 - 100 - ns (17) tPS Peripheral Data Before STB High 20 - 20 - ns 1 50 - 50 - - 175 - 175 ns 1 20 250 20 250 ns 2 WR = 1 to OBF = 0 - 150 - 150 ns 1 (22) tAOB ACK = 0 to OBF = 1 - 150 - 150 ns 1 (23) tSIB STB = 0 to IBF = 1 - 150 - 150 ns 1 (24) tRIB RD = 1 to IBF = 0 - 150 - 150 ns 1 (25) tRIT RD = 0 to INTR = 0 - 200 - 200 ns 1 (26) tSIT STB = 1 to INTR = 1 - 150 - 150 ns 1 (27) tAIT ACK = 1 to INTR = 1 - 150 - 150 ns 1 (28) tWIT WR = 0 to INTR = 0 - 200 - 200 ns 1 (29) tRES Reset Pulse Width 500 - 500 - ns 1,(Note) (18) tPH Peripheral Data After STB High (19) tAD ACK = 0 to Output (20) tKD ACK = 1 to Output Float (21) tWOB ns NOTE: Period of initial Reset pulse after power-on must be at least 50µsec. Subsequent Reset pulses may be 500ns minimum. 18 WS82C55A Timing Waveforms tRR (3) RD tIR (13) tHR (14) INPUT tAR (1) tRA (2) CS, A1, A0 D7-D0 tRD (4) tDF (5) FIGURE 25. MODE 0 (BASIC INPUT) tWW (9) WR tDW (10) tWD (11) D7-D0 tAW (7) tWA (8) CS, A1, A0 OUTPUT tWS (12) FIGURE 26. MODE 0 (BASIC OUTPUT) tST (16) STB IBF tSIB (23) tSIT (26) tRIB (24) tRIT (25) INTR RD tPH (18) INPUT FROM PERIPHERAL tPS (17) FIGURE 27. MODE 1 (STROBED INPUT) 19 WS82C55A Timing Waveforms (Continued) tWOB (21) WR tAOB (22) OBF tWIT (28) INTR ACK tAK (15) tAIT (27) OUTPUT tWB (12) FIGURE 28. MODE 1 (STROBED OUTPUT) DATA FROM CPU TO 82C55A WR (NOTE) tAOB (22) OBF tWOB (21) INTR tAK (15) ACK tST (16) STB (NOTE) IBF tSIB (23) tAD (19) tPS (17) tKD (20) PERIPHERAL BUS tRIB (24) tPH (18) RD DATA FROM PERIPHERAL TO 82C55A DATA FROM 82C55A TO PERIPHERAL DATA FROM 82C55A TO CPU FIGURE 29. MODE 2 (BI-DIRECTIONAL) NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD • OBF • MASK • ACK • WR) 20 WS82C55A Timing Waveforms (Continued) A0-A1, CS A0-A1, CS tWA (8) tAW (7) tRA (2) tAR (1) tRR (3) DATA BUS RD tDW (10) tWD (11) (4) tRD tDF (5) DATA BUS WR VALID HIGH IMPEDANCE tWW (9) FIGURE 30. WRITE TIMING FIGURE 31. READ TIMING AC Test Circuit AC Testing Input, Output Waveforms V1 INPUT OUTPUT VIH + 0.4V VOH 1.5V R1 OUTPUT FROM DEVICE UNDER TEST TEST POINT R2 1.5V VOL VIL - 0.4V AC Testing: All AC Parameters tested as per test circuits. Input RISE and FALL times are driven at 1ns/V. C1 (SEE NOTE) TEST CONDITION DEFINITION TABLE NOTE: Includes STRAY and JIG Capacitance Burn-In Circuits WS82C55A-5 DIP40L F6 1 40 F11 F7 2 39 F12 F8 3 38 F13 F9 4 37 F14 F4 5 36 F2 F3 6 35 F5 GND 7 34 F15 F0 8 33 F11 F1 9 32 F12 F10 10 31 F13 F6 11 30 F14 F7 12 29 F15 F8 13 28 F11 F9 14 27 F12 F10 15 26 F6 16 25 F13 F7 17 24 F14 F8 18 23 F15 F9 19 22 F11 F10 20 21 F12 VCC C1 NOTES: 1. VCC = 5.5V ± 0.5V 2. VIH = 4.5V ± 10% 3. VIL = -0.2V to 0.4V 4. GND = 0V 21 TEST CONDITION V1 R1 R2 C1 1 1.7V 523Ω Open 150pF 2 VCC 2kΩ 1.7kΩ 50pF 3 1.5V 750Ω Open 50pF WS82C55A Die Characteristics DIE SIZE 86x99 mils RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR RESET CS GND D0 A1 D1 A0 D2 PC7 D3 PC6 D4 PC5 D5 PC4 D6 PC0 D7 PC1 VCC PC2 PD3 PB0 PB1 PB2 22 PB3 PB4 PB5 PB6 PB7 WS82C55A Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC ISSUE B) N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- A2 SEATING PLANE e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.980 2.095 D1 0.005 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 50.3 53.2 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 40 40 9 Rev. 0 12/93 23 WS82C55A Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N44.65 (JEDEC MS-018AC ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” A1 A D1 D 0.020 (0.51) MAX 3 PLCS 0.020 (0.51) MIN 0.045 (1.14) MIN INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.685 0.695 17.40 17.65 - D1 0.650 0.656 16.51 16.66 3 D2 0.291 0.319 7.40 8.10 4, 5 E 0.685 0.695 17.40 17.65 - E1 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4, 5 N 44 44 6 Rev. 2 11/97 SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. 24 WS82C55A (Unit : mm) Mirror finish QFP-44 Package material Lead frame material Pin treatment Solder plate thickness Epoxy resin 42 alloy Solder plating 5 mm or more Package weight (g) 0.41 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25