INTERSIL X28C010DI-15

X28C010
®
Data Sheet
May 11, 2005
FN8105.0
5 Volt, Byte Alterable EEPROM
Features
The Intersil X28C010 is a 128K x 8 EEPROM, fabricated
with Intersil's proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable nonvolatile memories, the X28C010 is a 5V only device. The
X28C010 features the JEDEC approved pin out for bytewide memories, compatible with industry standard
EEPROMs.
• Access time: 120ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or VPP control
circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
The X28C010 supports a 256-byte page write operation,
effectively providing a 19µs/byte write cycle and enabling the
entire memory to be typically written in less than 2.5
seconds. The X28C010 also features DATA Polling and
Toggle Bit Polling, system software support schemes used to
indicate the early completion of a write cycle. In addition, the
X28C010 supports Software Data Protection option.
• Low power CMOS
- Active: 50mA
- Standby: 500µA
• Software data protection
- Protects data against system level inadvertent writes
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Data retention is specified to
be greater than 100 years.
• High speed page write capability
• Highly reliable Direct Write™ cell
- Endurance: 100,000 write cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
Pinouts
31
3
30
NC
A12
A7
4
29
5
28
A14
A13
A6
A5
6
27
7
26
A4
A3
8
25
9
24
A2
A1
10
23
11
22
A0
I/O0
12
21
13
20
I/O1
I/O2
14
19
15
18
I/O5
I/O4
VSS
16
17
I/O3
A8
A9
A1
13
A0
14
CE
I/O1
VSS
I/O4
I/O7
16
18
20
23
24
A2
12
A3
11
OE
A10
26
25
A4
10
9
8
A11
OE
A6
7
A12
6
A10
CE
1
X28C010
(Bottom View)
A7
A15
5
4
I/O7
I/O6
A5
NC
2
A
16
NC
3
VCC
NC
36
34
NC
1
WE
35
A11
27
A9
28
A8
29
A 13
30
NC
32
A 14
31
NC
33
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4 3 2
WE
NC
A12
A15
A16
NC
VCC
WE
NC
NC
VCC
30
32 31
54 3 2
29
1
6
28
7
27
26
8
X28C010 25
9
(Top
View)
10
24
11
23
12
22
13
15 16 17 18 19 20 21
14
32 31 30
1
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
A7
A6
A5
A4
A3
A2
A1
A0
I/O 0
5
6
7
8
9
10
11
12
13
X28C010
(Top View)
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
14 15 16 17 18 19 20
I/O4
I/O5
I/O6
2
I/O0
I/O2
I/O 3
I/O5
I/O6
15
17
19
21
22
I/O1
I/O2
VSS
I/O3
A16
A15
VCC
WE
I/O4
I/O5
I/O6
32
I/O1
I/O2
VSS
I/O3
1
A 12
A 15
A 16
PGA
NC
X28C010
EXTENDED LCC
PLCC
LCC
CERDIP
Flat Pack
SOIC (R)
TSOP
A11
A9
A8
A13
A14
NC
NC
NC
WE
VCC
NC
NC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
X28C010
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
NC
VSS
NC
NC
I/O2
I/O1
I/O0
A0
A1
A2
A3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28C010
Ordering Information (Continued)
Ordering Information
PART NUMBER
X28C010D
ACCESS
TIME
PACKAGE
TEMP
RANGE (°C)
-
32-Ld Cerdip
0 to 70
X28C010D-12
120ns
32-Ld Cerdip
0 to 70
X28C010D-15
150ns
32-Ld Cerdip
0 to 70
-
32-Ld Cerdip
-40 to +85
X28C010DI-12
120ns
32-Ld Cerdip
-40 to +85
X28C010DI-15
150ns
32-Ld Cerdip
-40 to +85
X28C010DI15C7681
150ns
32-Ld Cerdip
-40 to +85
X28C010DM
-
32-Ld Cerdip
-55 to +125
X28C010DM-12
120ns
32-Ld Cerdip
-55 to +125
X28C010DMB-12
120ns
32-Ld Cerdip
MIL-STD-883
X28C010DMB12C7309
120ns
32-Ld Cerdip
MIL-STD-883
X28C010DMB12C7729
120ns
X28C010DMB-15
150ns
32-Ld Cerdip
MIL-STD-883
X28C010DMB15C7762
150ns
32-Ld Cerdip
MIL-STD-883
X28C010DMB-20
200ns
32-Ld Cerdip
MIL-STD-883
-
32-Ld Cerdip
X28C010DI
X28C010DMC7237
32-Ld Cerdip
MIL-STD-883
X28C010FI-12
120ns
32-Ld Flat Pack
-40 to +85
X28C010FI-15
150ns
32-Ld Flat Pack
-40 to +85
X28C010FI15C1009
150ns
32-Ld Flat Pack
-40 to +85
X28C010FI-20
200ns
32-Ld Flat Pack
-40 to +85
X28C010FI-25
250ns
32-Ld Flat Pack
-40 to +85
-
32-Ld Flat Pack
-55 to +125
X28C010FM-12
120ns
32-Ld Flat Pack
-55 to +125
X28C010FMB-15
150ns
32-Ld Flat Pack
MIL-STD-883
X28C010FMB15C7619
150ns
32-Ld Flat Pack
MIL-STD-883
X28C010FMB15C7808
150ns
32-Ld Flat Pack
MIL-STD-883
X28C010K-25
250ns
36-Ld Pin Grid
Array
0 to 70
X28C010KM-12
120ns
36-Ld Pin Grid
Array
-55 to +125
X28C010KM-25
250ns
36-Ld Pin Grid
Array
-55 to +125
X28C010KM25C7237
250ns
36-Ld Pin Grid
Array
-55 to +125
X28C010KMB-15
150ns
36-Ld Pin Grid
Array
MIL-STD-883
X28C010FM
2
PART NUMBER
ACCESS
TIME
PACKAGE
TEMP
RANGE (°C)
X28C010NM-12
120ns
32-Ld Extended
LCC
-55 to +125
X28C010NM-15
150ns
32-Ld Extended
LCC
-55 to +125
X28C010NMB-12
120ns
32-Ld Extended
LCC
MIL-STD-883
X28C010NMB-15
150ns
32-Ld Extended
LCC
MIL-STD-883
X28C010NMB15C7309
150ns
32-Ld Extended
LCC
MIL-STD-883
X28C010RI-12
120ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RI-20
200ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RI20C7168
200ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RI20C7975
200ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RI-20T1
200ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RI20T1C7168
200ns
32-Ld Ceramic
SOIC (Gull Wing)
-40 to +85
X28C010RM-15
150ns
32-Ld Ceramic
SOIC (Gull Wing)
-55 to +125
X28C010RMB-25
250ns
32-Ld Ceramic
MIL-STD-883
SOIC (Gull Wing)
FN8105.0
May 11, 2005
X28C010
Block Diagram
A8-A16
X Buffers
Latches and
Decoder
EEPROM
Array
A0-A7
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
CE
OE
WE
1Mbit
Control
Logic and
Timing
I/O0-I/O7
Data Inputs/Outputs
VCC
VSS
Pin Descriptions
Pin Names
Addresses (A0-A16)
The Address inputs select an 8-bit memory location during a
read or write operation.
SYMBOL
DESCRIPTION
A0-A16
Address Inputs
Chip Enable (CE)
I/O0-I/O7
Data Input/Output
WE
Write Enable
CE
Chip Enable
OE
Output Enable
VCC
+5V
VSS
Ground
NC
No Connect
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is
reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers,
and is used to initiate read operations.
Data In/Data Out (I/O0-I/O7)
Data is written to or read from the X28C010 through the I/O
pins.
Device Operation
Write Enable (WE)
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
The Write Enable input controls the writing of data to the
X28C010.
Read
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C010 supports both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs
last. Similarly, the data is latched internally by the rising edge
of either CE or WE, whichever occurs first. A byte write
operation, once initiated, will automatically continue to
completion, typically within 5ms.
3
FN8105.0
May 11, 2005
X28C010
Page Write Operation
The page write feature of the X28C010 allows the entire
memory to be written in 5 seconds. Page write allows two to
two hundred fifty-six bytes of data to be consecutively written
to the X28C010 prior to the commencement of the internal
programming cycle. The host can fetch data from another
device within the system during a page write operation
(change the source address), but the page address (A8
through A16) for each subsequent valid write cycle to the part
during this operation must be the same as the initial page
address.
I/O
DP
TB
5
4
3
2
1
0
Reserved
Toggle Bit
DATA Polling
FIGURE 1. STATUS BIT ASSIGNMENT
DATA Polling (I/O7)
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to two hundred fifty six bytes in the
same manner as the first byte was written. Each successive
byte load cycle, started by the WE HIGH to LOW transition,
must begin within 100µs of the falling edge of the preceding
WE. If a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively the page write window is infinitely wide,
so long as the host continues to access the device within the
byte load cycle time of 100µs.
The X28C010 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28C010, eliminating additional
interrupt inputs or external hardware. During the internal
programming cycle, any attempt to read the last byte written
will produce the complement of that data on I/O7 (i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O7 will reflect true data.
Note: If the X28C010 is in the protected state, and an illegal
write operation is attempted, DATA Polling will not operate.
Write Operation Status Bits
The X28C010 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle, I/O6 will toggle from HIGH to LOW and
LOW to HIGH on subsequent attempts to read the device.
When the internal cycle is complete the toggling will cease
and the device will be accessible for additional read or write
operations.
The X28C010 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown
in Figure 1.
Toggle Bit (I/O6)
DATA Polling I/O7
WE
Last
Write
CE
OE
VIH
VOH
HIGH Z
I/O7
VOL
A0-A14
An
An
An
X28C010
Ready
An
An
An
An
FIGURE 2. DATA POLLING BUS SEQUENCE
4
FN8105.0
May 11, 2005
X28C010
DATA Polling can effectively halve the time for writing to the
X28C010. The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 3 illustrates one method of implementing the routine.
Write Data
No
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO7
Compare?
No
Yes
X28C010
Ready
FIGURE 3. DATA POLLING SOFTWARE FLOW
The Toggle Bit I/O6
WE
Last
Write
CE
OE
VOH
I/O6
*
HIGH Z
VOL
*
X28C010
Ready
* Beginning and ending state of I/O6 will vary
FIGURE 4. TOGGLE BIT BUS SEQUENCE
5
FN8105.0
May 11, 2005
X28C010
• Noise Protection—A WE pulse less than 10ns will not
initiate a write cycle.
Last Write
• Default VCC Sense—All functions are inhibited when VCC
is ≤ 3.5V.
• Write inhibit—Holding either OE LOW, WE HIGH, or CE
HIGH will prevent an inadvertent write cycle during powerup and power-down, maintaining data integrity.
Load Accum
From Addr N
Software Data Protection
The X28C010 offers a software controlled data protection
feature. The X28C010 is shipped from Intersil with the
software data protection NOT ENABLED: that is the device
will be in the standard operating mode. In this mode data
should be protected during power-up/-down operations
through the use of external circuits. The host would then
have open read and write access of the device once VCC
was stable.
Compare
Accum with
Addr N
No
Compare
Ok?
The X28C010 can be automatically protected during powerup and power-down without the need for external circuits by
employing the software data protection feature. The internal
software data protection circuit is enabled after the first write
operation utilizing the software algorithm. This circuit is
nonvolatile and will remain set for the life of the device
unless the reset command is issued.
Yes
Ready
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling. This
can be especially helpful in an array comprised of multiple
X28C010 memories that is frequently updated. Toggle Bit
Polling can also provide a method for status checking in
multiprocessor applications. The timing diagram in Figure 4
illustrates the sequence of events on the bus. The software
flow diagram in Figure 5 illustrates a method for polling the
Toggle Bit.
Hardware Data Protection
The X28C010 provides three hardware features that protect
nonvolatile data from inadvertent writes.
Once the software protection is enabled, the X28C010 is
also protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be
issued prior to writing additional data to the device.
Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figures 6 and 7 for the sequence. The three byte sequence
opens the page write window enabling the host to write from
one to two hundred fifty-six bytes of data. Once the page
load cycle has been completed, the device will automatically
be returned to the data protected state.
Software Data Protection
VCC
(VCC)
0V
Data
Addr
AA
5555
55
2AAA
A0
5555
Writes
Ok
CE
≤ tBLC MAX
WE
tWC
Write
Protected
Byte
or
Page
FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE
6
FN8105.0
May 11, 2005
X28C010
Regardless of whether the device has previously been
protected or not, once the software data protection algorithm
is used and data has been written, the X28C010 will
automatically disable further writes unless another command
is issued to cancel it. If no further commands are issued the
X28C010 will be write protected during power-down and
after any subsequent power-up. The state of A15 and A16
while executing the algorithm is don’t care.
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data A0
to Address
5555
Write Data XX
to Any
Address
Optional
Byte/Page
Load Operation
Write Last
Byte
Last Address
After tWC
Re-Enters Data
Protected State
FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA
PROTECTION
Resetting Software Data Protection
VCC
Data
Addr
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
≥ tWC
Standard
Operating
Mode
CE
WE
FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
7
FN8105.0
May 11, 2005
X28C010
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Write Data 80
to Address
5555
Write Data AA
to Address
5555
concern. Enabling CE will cause transient current spikes.
The magnitude of these spikes is dependent on the output
capacitive loading of the I/Os. Therefore, the larger the array
sharing a common bus, the larger the transient spikes. The
voltage peaks associated with the current transients can be
suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended
that a 0.1µF high frequency ceramic capacitor be used
between VCC and VSS at each device. Depending on the
size of the array, the value of the capacitor may have to be
larger.
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between VCC and VSS for each eight
devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.
Write Data 55
to Address
2AAA
Write Data 20
to Address
5555
FIGURE 9. SOFTWARE SEQUENCE TO DEACTIVATE
SOFTWARE DATA PROTECTION
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an
EEPROM programmer, the following six step algorithm will
reset the internal protection circuit. After tWC, the X28C010
will be in standard operating mode.
Note: Once initiated, the sequence of write operations
should not be interrupted.
System Considerations
Because the X28C010 is frequently used in large memory
arrays, it is provided with a two line control architecture for
both read and write operations. Proper usage can provide
the lowest possible power dissipation and eliminate the
possibility of contention where multiple I/O pins share the
same bus.
To gain the most benefit, it is recommended that CE be
decoded from the address bus and be used as the primary
device selection input. Both OE and WE would then be
common among all devices in the array. For a read operation
this assures that all deselected devices are in their standby
mode and that only the selected device(s) is outputting data
on the bus.
Because the X28C010 has two power modes, standby and
active, proper decoupling of the memory array is of prime
8
FN8105.0
May 11, 2005
X28C010
Active Supply Current vs. Ambient Temperature
18
VCC = 5V
ICC WR (mA)
16
14
12
10
-55
+35
-10
+80
+125
Ambient Temperature (°C)
Standby Supply Current vs. Ambient Temperature
0.3
VCC = 5V
ISB (mA)
0.25
0.2
0.15
0.1
0.05
-55
+35
-10
+80
+125
Ambient Temperature (°C)
ICC (RD) by Temperature Over Frequency
60
5.0 VCC
50
ICC RD (mA)
-55°C
+25°C
40
+125°C
30
20
10
0
3
6
9
12
15
Frequency (MHz)
9
FN8105.0
May 11, 2005
X28C010
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias
X28C010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
X28C010I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
X28C010M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any pin with respect to VSS . . . . . . . . . . . . . . -1V to +7V
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature
(soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C tp +85°C
Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions (above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DC Electrical Specifications
SYMBOL
Over the recommended operating conditions, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
ICC
VCC Current (Active) (TTL Inputs)
CE = OE = VIL, WE = VIH, All I/O’s = Open,
Address Inputs = 0.4V/2.4V Levels @ f = 5MHz
50
mA
ISB1
VCC Current (Standby) (TTL Inputs)
CE = VIH, OE = VIL, All I/O’s = Open, Other Inputs = VIH
3
mA
ISB2
VCC Current (Standby) (CMOS
Inputs)
CE = VCC - 0.3V, OE = VIL, All I/O’s = Open,
Other Inputs = VCC
500
µA
ILI
Input Leakage Current
VIN = VSS to VCC
10
µA
ILO
Output Leakage Current
VOUT = VSS to VCC, CE = VIH
10
µA
VlL (Note 1) Input LOW Voltage
-1
0.8
V
VIH (Note 1) Input HIGH Voltage
2
VCC + 1
V
0.4
V
VOL
Output LOW Voltage
IOL = 2.1mA
VOH
Output HIGH Voltage
IOH = -400µA
2.4
V
NOTE:
1. VIL min. and VIH max. are for reference only and are not tested.
Power-Up Timing
SYMBOL
PARAMETER
MAX
UNIT
tPUR (Note 2)
Power-up to Read operation
100
µs
tPUW (Note 2)
Power-up to Write operation
5
ms
Capacitance
TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL
PARAMETER
TEST CONDITIONS
MAX
UNIT
CI/O (Note 2)
Input/Output capacitance
VI/O = 0V
10
pF
CIN (Note 2)
Input capacitance
VIN = 0V
10
pF
NOTE:
2. This parameter is periodically sampled and not 100% tested.
Endurance and Data Retention
PARAMETER
MIN
Endurance
10,000
Cycles per byte
Endurance
100,000
Cycles per page
Data Retention
100
Years
10
MAX
UNIT
FN8105.0
May 11, 2005
X28C010
Symbol Table
A.C. Conditions of Test
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input and output timing levels
1.5V
WAVEFORM
Mode Selection
CE
OE
WE
MODE
I/O
POWER
L
L
H
Read
DOUT
Active
L
H
L
Write
DIN
Active
H
X
X
Standby and
Write Inhibit
High Z
Standby
X
L
X
Write Inhibit
—
—
X
X
H
Write Inhibit
—
—
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Equivalent A.C. Load Circuit
5V
1.92kΩ
Output
1.37kΩ
100pF
AC Electrical Specifications
Over the recommended operating conditions, unless otherwise specified.
X28C010-12
SYMBOL
PARAMETER
MIN
MAX
X28C010-15
MIN
MAX
X28C010-20
MIN
MAX
X28C010-25
MIN
MAX
UNIT
READ CYCLE LIMITS
tRC
Read cycle time
tCE
Chip enable access time
120
150
200
250
ns
tAA
Address access time
120
150
200
250
ns
tOE
Output enable access time
50
50
50
50
ns
120
150
200
250
ns
tLZ (Note 3) CE LOW to active output
0
0
0
0
ns
tOLZ
(Note 3)
OE LOW to active output
0
0
0
0
ns
tHZ
(Note 3)
CE HIGH to high Z output
50
50
50
50
ns
tOHZ
(Note 3)
OE HIGH to high Z output
50
50
50
50
ns
tOH
Output hold from address change
11
0
0
0
0
ns
FN8105.0
May 11, 2005
X28C010
Read Cycle
tRC
Address
tCE
CE
tOE
OE
VIH
WE
tOLZ
tOHZ
tLZ
tOH
tHZ
HIGH Z
Data Valid
Data I/O
Data Valid
tAA
NOTE:
3. tLZ min.,tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point
when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
Write Cycle Limits
SYMBOL
tWC (Note 4)
PARAMETER
MIN
Write cycle time
MAX
UNIT
10
ms
tAS
Address setup time
0
ns
tAH
Address hold time
50
ns
tCS
Write setup time
0
ns
tCH
Write hold time
0
ns
tCW
CE pulse width
100
ns
tOES
OE HIGH setup time
10
ns
tOEH
OE HIGH hold time
10
ns
tWP
WE pulse width
100
ns
WE HIGH recovery
100
ns
tWPH
tDV
Data valid
tDS
Data setup
50
ns
tDH
Data hold
0
ns
tDW
Delay to next write
10
µs
tBLC
Byte load cycle
0.2
1
12
100
µs
µs
FN8105.0
May 11, 2005
X28C010
WE Controlled Write Cycle
tWC
Address
tAS
tAH
tCS
tCH
CE
OE
tOES
tOEH
tWP
WE
tWPH
tDV
Data In
Data Valid
tDH
tDS
Data Out
HIGH Z
NOTE:
4. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to complete internal write operation.
CE Controlled Write Cycle
tWC
Address
tAS
tAH
tCW
CE
tWPH
tOES
OE
tOEH
tCS
tCH
WE
tDV
Data Valid
Data In
tDS
tDH
HIGH Z
Data Out
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X28C010
Page Write Cycle
OE (Note 5)
CE
tBLC
tWP
WE
tWPH
Address* (Note 6)
Last Byte
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
Byte n+2
tWC
*For each successive write within the page write operation, A8-A16 should be the same or
writes to an unknown address could occur.
NOTES:
5. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch
data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
6. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the
CE or WE controlled write cycle timing.
DATA Polling Timing Diagram (Note 7)
Address
An
An
An
CE
WE
tOEH
tOES
OE
tDW
DIN = X
I/O7
DOUT = X
DOUT = X
tWC
14
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May 11, 2005
X28C010
Toggle Bit Timing Diagram
CE
WE
tOES
tOEH
OE
tDW
HIGH Z
I/O6
*
*
tWC
* I/O6 beginning and ending state will vary.
NOTE:
7. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
15
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X28C010
Packaging Information
32-Lead Hermetic, CerDIP, Package Code D32
1.690 (42.95)
Max.
0.610 (15.49)
0.500 (12.70)
Pin 1
0.005 (0.13) Min.
0.100 (2.54) Max.
Seating
Plane
0.232 (5.90) Max.
0.060 (1.52)
0.015 (0.38)
0.150 (3.81) Min.
0.200 (5.08)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
Typ. 0.100 (2.54)
0.065 (1.65)
0.033 (0.84)
Typ. 0.055 (1.40)
0.023 (0.58)
0.014 (0.36)
Typ. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
Typ. 0.614 (15.60)
0.015 (0.38)
0.008 (0.20)
0°
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
16
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X28C010
Packaging Information
32-Pad Ceramic Leadless Chip Carrier Package Type E
0.300 (7.62)
BSC
0.150 (3.81) BSC
0.015 (0.38)
0.020 (0.51) x 45° Ref.
0.003 (0.08)
0.095 (2.41)
Pin 1
0.075 (1.91)
0.022 (0.56)
0.006 (0.15)
DIA.
0.055 (1.39)
0.200 (5.08)
BSC
0.045 (1.14)
0.015 (0.38)
Min.
0.028 (0.71)
0.022 (0.56)
0.050 (1.27) BSC
TYP. (4) PLCS.
0.040 (1.02) x 45° Ref.
Typ. (3) Plcs.
(32) Plcs.
0.088 (2.24)
0.458 (11.63)
0.442 (11.22)
0.120 (3.05)
0.458 (11.63)
0.050 (1.27)
0.060 (1.52)
--
0.560 (14.22)
0.558 (14.17)
0.540 (13.71)
--
0.400 (10.16)
BSC
Pin 1 Index Corner
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
17
FN8105.0
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X28C010
Packaging Information
32-Lead Ceramic Flat Pack Type F
1.228 (31.19)
1.000 (25.40)
Pin 1 Index
1
0.019 (0.48)
0.015 (0.38)
32
0.050 (1.27) BSC
0.830 (21.08) Max.
0.045 (1.14) Max.
0.005 (0.13) Min.
0.440
0.430 (10.93)
0.007 (0.18)
0.004 (0.10)
0.120 (3.05)
0.090 (2.29)
0.370 (9.40)
0.270 (6.86)
0.347 (8.82)
0.330 (8.38)
0.026 (0.66)
Min.
0.030 (0.76)
Min.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
18
FN8105.0
May 11, 2005
X28C010
Packaging Information
32-Lead Plastic Leaded Chip Carrier Package Type J
0.030" Typical
32 Places
0.050"
Typical
0.420 (10.67)
0.050"
Typical
0.510"
Typical
0.400"
0.050 (1.27) Typ.
0.300"
Ref.
0.410"
FOOTPRINT
0.021 (0.53)
0.045 (1.14) x 45°
0.013 (0.33)
Typ. 0.017 (0.43)
Seating Plane
±0.004 Lead
CO - Planarity
—
0.015 (0.38)
0.495 (12.57)
0.485 (12.32)
Typ. 0.490 (12.45)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
Typ. 0.136 (3.45)
0.453 (11.51)
0.447 (11.35)
Typ. 0.450 (11.43)
0.300 (7.62)
Ref.
0.048 (1.22)
0.042 (1.07)
Pin 1
0.595 (15.11)
0.585 (14.86)
Typ. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
Typ. 0.550 (13.97)
0.400
Ref.
(10.16)
3° Typ.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
19
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X28C010
Packaging Information
32-Pad Stretched Ceramic Leadless Chip Carrier Package Type N
0.300 BSC
0.035 x 45° Ref.
Detail A
0.085 ± 0.010
Pin 1
0.005/0.015
Detail A
0.025 ± 0.003
0.006/0.022
0.400 BSC
0.050 ± 0.005
0.050 BSC
0.020 (1.02) x 45° Ref.
Typ. (3) Plcs.
0.450 ± 0.008
0.060/0.120
0.458 Max.
0.700 ± 0.010
0.708 Max.
Pin #1 Index Corner
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT±0.005 (0.127)
20
FN8105.0
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X28C010
Packaging Information
32-Lead Ceramic Small Outline Gull Wing Package Type R
0.060 Nom.
See Detail “A”
For Lead
Information
0.020 Min.
0.165 Typ.
0.340
±0.007
0.015 R Typ.
0.015 R
Typ.
0.035 Typ.
0.035 Min.
Detail “A”
0.050"
Typical
0.019
0.015
0.050"
Typical
0.830
Max.
0.750
±0.005
0.050
0.560"
Typical
FOOTPRINT
0.030" Typical
32 Places
0.440 Max.
0.560 Nom.
NOTES:
1. ALL DIMENSIONS IN INCHES
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
21
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May 11, 2005
X28C010
Packaging Information
36-Lead Ceramic Pin Grid Array Package Type K
15
17
19
21
22
A
0.008 (0.20)
13
14
12
11
16
18
20
23
24
25
26
0.050 (1.27)
A
10
9
27
28
8
7
29
30
NOTE: Leads 5, 14, 23, & 32
Typ. 0.100 (2.54)
All Leads
6
Typ. 0.180 (.010)
(4.57 ± .25)
4 Corners
5
2
36
34
32
4
3
1
35
33
31
Typ. 0.180 (.010)
(4.57 ± .25)
4 Corners
0.120 (3.05)
0.100 (2.54)
0.072 (1.83)
0.062 (1.57)
Pin 1 Index
0.770 (19.56)
0.750 (19.05)
SQ
A
0.020 (0.51)
0.016 (0.41)
A
0.185 (4.70)
0.175 (4.45)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
22
FN8105.0
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X28C010
Packaging Information
40-Lead Thin Small Outline Package (TSOP) Type T
0.493 (12.522)
0.483 (12.268)
0.045 (1.143)
0.035 (0.889) Pin #1 Ident
O 0.040 (1.016) 0.005 (0.127) Dp.
O 0.030 (0.762) X 0.003 (0.076) Dp.
(0.038)
0.965
0.048 (1.219)
1
0.0197 (0.500)
0.396 (10.058)
0.392 (9.957)
0.007 (0.178)
15° Typ.
A
0.0025 (0.065)
Seating
Plane
0.557 (14.148)
0.547 (13.894)
Seating
Plane
0.010 (0.254)
0.006 (0.152)
0.040 (1.016)
Detail A
0.032 (0.813) Typ.
0.006 (0.152)
Typ.
4° Typ.
0.017 (0.432)
0.017 (0.432)
0.020 (0.508) Typ.
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
Solder
Pads
FOOTPRINT
(0.012 ± 0.002)
Typical
40 Places
0.17 (0.007)
0.03 (0.001) 1.30 ± 0.05
(0.051 ± 0.002)
15 Eq. Spc.@ 0.50 ± 0.04
0.0197 0.016 = 9.50 ± 0.06
(0.374 ± 0.0024) Overall
Tol. Non-Cumulative
0.50 ± 0.04
(0.0197 ± 0.0016)
NOTE: ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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23
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